2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
211 ADVANCED_CONTEXT = 0,
216 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
217 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
218 LEGACY_64B_CONTEXT :\
222 FAULT_AND_HALT, /* Debug only */
224 FAULT_AND_CONTINUE /* Unsupported */
226 #define GEN8_CTX_ID_SHIFT 32
227 #define GEN8_CTX_ID_WIDTH 21
228 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
229 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
231 static int execlists_context_deferred_alloc(struct intel_context *ctx,
232 struct intel_engine_cs *engine);
233 static int intel_lr_context_pin(struct intel_context *ctx,
234 struct intel_engine_cs *engine);
237 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
239 * @enable_execlists: value of i915.enable_execlists module parameter.
241 * Only certain platforms support Execlists (the prerequisites being
242 * support for Logical Ring Contexts and Aliasing PPGTT or better).
244 * Return: 1 if Execlists is supported and has to be enabled.
246 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
248 WARN_ON(i915.enable_ppgtt == -1);
250 /* On platforms with execlist available, vGPU will only
251 * support execlist mode, no ring buffer mode.
253 if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
256 if (INTEL_INFO(dev)->gen >= 9)
259 if (enable_execlists == 0)
262 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
263 i915.use_mmio_flip >= 0)
270 logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
272 struct drm_device *dev = engine->dev;
274 if (IS_GEN8(dev) || IS_GEN9(dev))
275 engine->idle_lite_restore_wa = ~0;
277 engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
278 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
279 (engine->id == VCS || engine->id == VCS2);
281 engine->ctx_desc_template = GEN8_CTX_VALID;
282 engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
283 GEN8_CTX_ADDRESSING_MODE_SHIFT;
285 engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
286 engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
288 /* TODO: WaDisableLiteRestore when we start using semaphore
289 * signalling between Command Streamers */
290 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
292 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
293 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
294 if (engine->disable_lite_restore_wa)
295 engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
299 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
300 * descriptor for a pinned context
302 * @ctx: Context to work on
303 * @ring: Engine the descriptor will be used with
305 * The context descriptor encodes various attributes of a context,
306 * including its GTT address and some flags. Because it's fairly
307 * expensive to calculate, we'll just do it once and cache the result,
308 * which remains valid until the context is unpinned.
310 * This is what a descriptor looks like, from LSB to MSB:
311 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
312 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
313 * bits 32-52: ctx ID, a globally unique tag
314 * bits 53-54: mbz, reserved for use by hardware
315 * bits 55-63: group ID, currently unused and set to 0
318 intel_lr_context_descriptor_update(struct intel_context *ctx,
319 struct intel_engine_cs *engine)
323 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
325 desc = engine->ctx_desc_template; /* bits 0-11 */
326 desc |= ctx->engine[engine->id].lrc_vma->node.start + /* bits 12-31 */
327 LRC_PPHWSP_PN * PAGE_SIZE;
328 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
330 ctx->engine[engine->id].lrc_desc = desc;
333 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
334 struct intel_engine_cs *engine)
336 return ctx->engine[engine->id].lrc_desc;
339 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
340 struct drm_i915_gem_request *rq1)
343 struct intel_engine_cs *engine = rq0->engine;
344 struct drm_device *dev = engine->dev;
345 struct drm_i915_private *dev_priv = dev->dev_private;
349 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
350 rq1->elsp_submitted++;
355 desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
356 rq0->elsp_submitted++;
358 /* You must always write both descriptors in the order below. */
359 I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
360 I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
362 I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
363 /* The context is automatically loaded after the following */
364 I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
366 /* ELSP is a wo register, use another nearby reg for posting */
367 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
371 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
373 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
374 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
375 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
376 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
379 static void execlists_update_context(struct drm_i915_gem_request *rq)
381 struct intel_engine_cs *engine = rq->engine;
382 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
383 uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
385 reg_state[CTX_RING_TAIL+1] = rq->tail;
387 /* True 32b PPGTT with dynamic page allocation: update PDP
388 * registers and point the unallocated PDPs to scratch page.
389 * PML4 is allocated during ppgtt init, so this is not needed
392 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
393 execlists_update_context_pdps(ppgtt, reg_state);
396 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
397 struct drm_i915_gem_request *rq1)
399 struct drm_i915_private *dev_priv = rq0->i915;
400 unsigned int fw_domains = rq0->engine->fw_domains;
402 execlists_update_context(rq0);
405 execlists_update_context(rq1);
407 spin_lock_irq(&dev_priv->uncore.lock);
408 intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
410 execlists_elsp_write(rq0, rq1);
412 intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
413 spin_unlock_irq(&dev_priv->uncore.lock);
416 static void execlists_context_unqueue(struct intel_engine_cs *engine)
418 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
419 struct drm_i915_gem_request *cursor, *tmp;
421 assert_spin_locked(&engine->execlist_lock);
424 * If irqs are not active generate a warning as batches that finish
425 * without the irqs may get lost and a GPU Hang may occur.
427 WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
429 /* Try to read in pairs */
430 list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
434 } else if (req0->ctx == cursor->ctx) {
435 /* Same ctx: ignore first request, as second request
436 * will update tail past first request's workload */
437 cursor->elsp_submitted = req0->elsp_submitted;
438 list_del(&req0->execlist_link);
439 i915_gem_request_unreference(req0);
443 WARN_ON(req1->elsp_submitted);
451 if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
453 * WaIdleLiteRestore: make sure we never cause a lite restore
456 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
457 * resubmit the request. See gen8_emit_request() for where we
458 * prepare the padding after the end of the request.
460 struct intel_ringbuffer *ringbuf;
462 ringbuf = req0->ctx->engine[engine->id].ringbuf;
464 req0->tail &= ringbuf->size - 1;
467 execlists_submit_requests(req0, req1);
471 execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id)
473 struct drm_i915_gem_request *head_req;
475 assert_spin_locked(&engine->execlist_lock);
477 head_req = list_first_entry_or_null(&engine->execlist_queue,
478 struct drm_i915_gem_request,
481 if (WARN_ON(!head_req || (head_req->ctx_hw_id != ctx_id)))
484 WARN(head_req->elsp_submitted == 0, "Never submitted head request\n");
486 if (--head_req->elsp_submitted > 0)
489 list_del(&head_req->execlist_link);
490 i915_gem_request_unreference(head_req);
496 get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
499 struct drm_i915_private *dev_priv = engine->dev->dev_private;
502 read_pointer %= GEN8_CSB_ENTRIES;
504 status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer));
506 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
509 *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine,
516 * intel_lrc_irq_handler() - handle Context Switch interrupts
517 * @engine: Engine Command Streamer to handle.
519 * Check the unread Context Status Buffers and manage the submission of new
520 * contexts to the ELSP accordingly.
522 static void intel_lrc_irq_handler(unsigned long data)
524 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
525 struct drm_i915_private *dev_priv = engine->dev->dev_private;
527 unsigned int read_pointer, write_pointer;
528 u32 csb[GEN8_CSB_ENTRIES][2];
529 unsigned int csb_read = 0, i;
530 unsigned int submit_contexts = 0;
532 intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
534 status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine));
536 read_pointer = engine->next_context_status_buffer;
537 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
538 if (read_pointer > write_pointer)
539 write_pointer += GEN8_CSB_ENTRIES;
541 while (read_pointer < write_pointer) {
542 if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES))
544 csb[csb_read][0] = get_context_status(engine, ++read_pointer,
549 engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
551 /* Update the read pointer to the old write pointer. Manual ringbuffer
552 * management ftw </sarcasm> */
553 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine),
554 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
555 engine->next_context_status_buffer << 8));
557 intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
559 spin_lock(&engine->execlist_lock);
561 for (i = 0; i < csb_read; i++) {
562 if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) {
563 if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) {
564 if (execlists_check_remove_request(engine, csb[i][1]))
565 WARN(1, "Lite Restored request removed from queue\n");
567 WARN(1, "Preemption without Lite Restore\n");
570 if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE |
571 GEN8_CTX_STATUS_ELEMENT_SWITCH))
573 execlists_check_remove_request(engine, csb[i][1]);
576 if (submit_contexts) {
577 if (!engine->disable_lite_restore_wa ||
578 (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
579 execlists_context_unqueue(engine);
582 spin_unlock(&engine->execlist_lock);
584 if (unlikely(submit_contexts > 2))
585 DRM_ERROR("More than two context complete events?\n");
588 static void execlists_context_queue(struct drm_i915_gem_request *request)
590 struct intel_engine_cs *engine = request->engine;
591 struct drm_i915_gem_request *cursor;
592 int num_elements = 0;
594 spin_lock_bh(&engine->execlist_lock);
596 list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
597 if (++num_elements > 2)
600 if (num_elements > 2) {
601 struct drm_i915_gem_request *tail_req;
603 tail_req = list_last_entry(&engine->execlist_queue,
604 struct drm_i915_gem_request,
607 if (request->ctx == tail_req->ctx) {
608 WARN(tail_req->elsp_submitted != 0,
609 "More than 2 already-submitted reqs queued\n");
610 list_del(&tail_req->execlist_link);
611 i915_gem_request_unreference(tail_req);
615 i915_gem_request_reference(request);
616 list_add_tail(&request->execlist_link, &engine->execlist_queue);
617 request->ctx_hw_id = request->ctx->hw_id;
618 if (num_elements == 0)
619 execlists_context_unqueue(engine);
621 spin_unlock_bh(&engine->execlist_lock);
624 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
626 struct intel_engine_cs *engine = req->engine;
627 uint32_t flush_domains;
631 if (engine->gpu_caches_dirty)
632 flush_domains = I915_GEM_GPU_DOMAINS;
634 ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
638 engine->gpu_caches_dirty = false;
642 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
643 struct list_head *vmas)
645 const unsigned other_rings = ~intel_engine_flag(req->engine);
646 struct i915_vma *vma;
647 uint32_t flush_domains = 0;
648 bool flush_chipset = false;
651 list_for_each_entry(vma, vmas, exec_list) {
652 struct drm_i915_gem_object *obj = vma->obj;
654 if (obj->active & other_rings) {
655 ret = i915_gem_object_sync(obj, req->engine, &req);
660 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
661 flush_chipset |= i915_gem_clflush_object(obj, false);
663 flush_domains |= obj->base.write_domain;
666 if (flush_domains & I915_GEM_DOMAIN_GTT)
669 /* Unconditionally invalidate gpu caches and ensure that we do flush
670 * any residual writes from the previous batch.
672 return logical_ring_invalidate_all_caches(req);
675 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
677 struct intel_engine_cs *engine = request->engine;
680 /* Flush enough space to reduce the likelihood of waiting after
681 * we start building the request - in which case we will just
682 * have to repeat work.
684 request->reserved_space += MIN_SPACE_FOR_ADD_REQUEST;
686 if (request->ctx->engine[engine->id].state == NULL) {
687 ret = execlists_context_deferred_alloc(request->ctx, engine);
692 request->ringbuf = request->ctx->engine[engine->id].ringbuf;
694 if (i915.enable_guc_submission) {
696 * Check that the GuC has space for the request before
697 * going any further, as the i915_add_request() call
698 * later on mustn't fail ...
700 struct intel_guc *guc = &request->i915->guc;
702 ret = i915_guc_wq_check_space(guc->execbuf_client);
707 ret = intel_lr_context_pin(request->ctx, engine);
711 ret = intel_ring_begin(request, 0);
715 if (!request->ctx->engine[engine->id].initialised) {
716 ret = engine->init_context(request);
720 request->ctx->engine[engine->id].initialised = true;
723 /* Note that after this point, we have committed to using
724 * this request as it is being used to both track the
725 * state of engine initialisation and liveness of the
726 * golden renderstate above. Think twice before you try
727 * to cancel/unwind this request now.
730 request->reserved_space -= MIN_SPACE_FOR_ADD_REQUEST;
734 intel_lr_context_unpin(request->ctx, engine);
739 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
740 * @request: Request to advance the logical ringbuffer of.
742 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
743 * really happens during submission is that the context and current tail will be placed
744 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
745 * point, the tail *inside* the context is updated and the ELSP written to.
748 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
750 struct intel_ringbuffer *ringbuf = request->ringbuf;
751 struct drm_i915_private *dev_priv = request->i915;
752 struct intel_engine_cs *engine = request->engine;
754 intel_logical_ring_advance(ringbuf);
755 request->tail = ringbuf->tail;
758 * Here we add two extra NOOPs as padding to avoid
759 * lite restore of a context with HEAD==TAIL.
761 * Caller must reserve WA_TAIL_DWORDS for us!
763 intel_logical_ring_emit(ringbuf, MI_NOOP);
764 intel_logical_ring_emit(ringbuf, MI_NOOP);
765 intel_logical_ring_advance(ringbuf);
767 if (intel_engine_stopped(engine))
770 /* We keep the previous context alive until we retire the following
771 * request. This ensures that any the context object is still pinned
772 * for any residual writes the HW makes into it on the context switch
773 * into the next object following the breadcrumb. Otherwise, we may
774 * retire the context too early.
776 request->previous_context = engine->last_context;
777 engine->last_context = request->ctx;
779 if (dev_priv->guc.execbuf_client)
780 i915_guc_submit(dev_priv->guc.execbuf_client, request);
782 execlists_context_queue(request);
788 * execlists_submission() - submit a batchbuffer for execution, Execlists style
791 * @ring: Engine Command Streamer to submit to.
792 * @ctx: Context to employ for this submission.
793 * @args: execbuffer call arguments.
794 * @vmas: list of vmas.
795 * @batch_obj: the batchbuffer to submit.
796 * @exec_start: batchbuffer start virtual address pointer.
797 * @dispatch_flags: translated execbuffer call flags.
799 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
800 * away the submission details of the execbuffer ioctl call.
802 * Return: non-zero if the submission fails.
804 int intel_execlists_submission(struct i915_execbuffer_params *params,
805 struct drm_i915_gem_execbuffer2 *args,
806 struct list_head *vmas)
808 struct drm_device *dev = params->dev;
809 struct intel_engine_cs *engine = params->engine;
810 struct drm_i915_private *dev_priv = dev->dev_private;
811 struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf;
817 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
818 instp_mask = I915_EXEC_CONSTANTS_MASK;
819 switch (instp_mode) {
820 case I915_EXEC_CONSTANTS_REL_GENERAL:
821 case I915_EXEC_CONSTANTS_ABSOLUTE:
822 case I915_EXEC_CONSTANTS_REL_SURFACE:
823 if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {
824 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
828 if (instp_mode != dev_priv->relative_constants_mode) {
829 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
830 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
834 /* The HW changed the meaning on this bit on gen6 */
835 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
839 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
843 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
844 DRM_DEBUG("sol reset is gen7 only\n");
848 ret = execlists_move_to_gpu(params->request, vmas);
852 if (engine == &dev_priv->engine[RCS] &&
853 instp_mode != dev_priv->relative_constants_mode) {
854 ret = intel_ring_begin(params->request, 4);
858 intel_logical_ring_emit(ringbuf, MI_NOOP);
859 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
860 intel_logical_ring_emit_reg(ringbuf, INSTPM);
861 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
862 intel_logical_ring_advance(ringbuf);
864 dev_priv->relative_constants_mode = instp_mode;
867 exec_start = params->batch_obj_vm_offset +
868 args->batch_start_offset;
870 ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags);
874 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
876 i915_gem_execbuffer_move_to_active(vmas, params->request);
881 void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
883 struct drm_i915_gem_request *req, *tmp;
884 LIST_HEAD(cancel_list);
886 WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
888 spin_lock_bh(&engine->execlist_lock);
889 list_replace_init(&engine->execlist_queue, &cancel_list);
890 spin_unlock_bh(&engine->execlist_lock);
892 list_for_each_entry_safe(req, tmp, &cancel_list, execlist_link) {
893 list_del(&req->execlist_link);
894 i915_gem_request_unreference(req);
898 void intel_logical_ring_stop(struct intel_engine_cs *engine)
900 struct drm_i915_private *dev_priv = engine->dev->dev_private;
903 if (!intel_engine_initialized(engine))
906 ret = intel_engine_idle(engine);
908 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
911 /* TODO: Is this correct with Execlists enabled? */
912 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
913 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
914 DRM_ERROR("%s :timed out trying to stop ring\n", engine->name);
917 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
920 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
922 struct intel_engine_cs *engine = req->engine;
925 if (!engine->gpu_caches_dirty)
928 ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
932 engine->gpu_caches_dirty = false;
936 static int intel_lr_context_pin(struct intel_context *ctx,
937 struct intel_engine_cs *engine)
939 struct drm_i915_private *dev_priv = ctx->i915;
940 struct drm_i915_gem_object *ctx_obj;
941 struct intel_ringbuffer *ringbuf;
946 lockdep_assert_held(&ctx->i915->dev->struct_mutex);
948 if (ctx->engine[engine->id].pin_count++)
951 ctx_obj = ctx->engine[engine->id].state;
952 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
953 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
957 vaddr = i915_gem_object_pin_map(ctx_obj);
959 ret = PTR_ERR(vaddr);
963 lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
965 ringbuf = ctx->engine[engine->id].ringbuf;
966 ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf);
970 i915_gem_context_reference(ctx);
971 ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj);
972 intel_lr_context_descriptor_update(ctx, engine);
973 lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start;
974 ctx->engine[engine->id].lrc_reg_state = lrc_reg_state;
975 ctx_obj->dirty = true;
977 /* Invalidate GuC TLB. */
978 if (i915.enable_guc_submission)
979 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
984 i915_gem_object_unpin_map(ctx_obj);
986 i915_gem_object_ggtt_unpin(ctx_obj);
988 ctx->engine[engine->id].pin_count = 0;
992 void intel_lr_context_unpin(struct intel_context *ctx,
993 struct intel_engine_cs *engine)
995 struct drm_i915_gem_object *ctx_obj;
997 lockdep_assert_held(&ctx->i915->dev->struct_mutex);
998 GEM_BUG_ON(ctx->engine[engine->id].pin_count == 0);
1000 if (--ctx->engine[engine->id].pin_count)
1003 intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf);
1005 ctx_obj = ctx->engine[engine->id].state;
1006 i915_gem_object_unpin_map(ctx_obj);
1007 i915_gem_object_ggtt_unpin(ctx_obj);
1009 ctx->engine[engine->id].lrc_vma = NULL;
1010 ctx->engine[engine->id].lrc_desc = 0;
1011 ctx->engine[engine->id].lrc_reg_state = NULL;
1013 i915_gem_context_unreference(ctx);
1016 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1019 struct intel_engine_cs *engine = req->engine;
1020 struct intel_ringbuffer *ringbuf = req->ringbuf;
1021 struct drm_device *dev = engine->dev;
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 struct i915_workarounds *w = &dev_priv->workarounds;
1028 engine->gpu_caches_dirty = true;
1029 ret = logical_ring_flush_all_caches(req);
1033 ret = intel_ring_begin(req, w->count * 2 + 2);
1037 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1038 for (i = 0; i < w->count; i++) {
1039 intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
1040 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1042 intel_logical_ring_emit(ringbuf, MI_NOOP);
1044 intel_logical_ring_advance(ringbuf);
1046 engine->gpu_caches_dirty = true;
1047 ret = logical_ring_flush_all_caches(req);
1054 #define wa_ctx_emit(batch, index, cmd) \
1056 int __index = (index)++; \
1057 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1060 batch[__index] = (cmd); \
1063 #define wa_ctx_emit_reg(batch, index, reg) \
1064 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1067 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1068 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1069 * but there is a slight complication as this is applied in WA batch where the
1070 * values are only initialized once so we cannot take register value at the
1071 * beginning and reuse it further; hence we save its value to memory, upload a
1072 * constant value with bit21 set and then we restore it back with the saved value.
1073 * To simplify the WA, a constant value is formed by using the default value
1074 * of this register. This shouldn't be a problem because we are only modifying
1075 * it for a short period and this batch in non-premptible. We can ofcourse
1076 * use additional instructions that read the actual value of the register
1077 * at that time and set our bit of interest but it makes the WA complicated.
1079 * This WA is also required for Gen9 so extracting as a function avoids
1082 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
1083 uint32_t *const batch,
1086 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1089 * WaDisableLSQCROPERFforOCL:skl
1090 * This WA is implemented in skl_init_clock_gating() but since
1091 * this batch updates GEN8_L3SQCREG4 with default value we need to
1092 * set this bit here to retain the WA during flush.
1094 if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
1095 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1097 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1098 MI_SRM_LRM_GLOBAL_GTT));
1099 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1100 wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1101 wa_ctx_emit(batch, index, 0);
1103 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1104 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1105 wa_ctx_emit(batch, index, l3sqc4_flush);
1107 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1108 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1109 PIPE_CONTROL_DC_FLUSH_ENABLE));
1110 wa_ctx_emit(batch, index, 0);
1111 wa_ctx_emit(batch, index, 0);
1112 wa_ctx_emit(batch, index, 0);
1113 wa_ctx_emit(batch, index, 0);
1115 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1116 MI_SRM_LRM_GLOBAL_GTT));
1117 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1118 wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1119 wa_ctx_emit(batch, index, 0);
1124 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1126 uint32_t start_alignment)
1128 return wa_ctx->offset = ALIGN(offset, start_alignment);
1131 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1133 uint32_t size_alignment)
1135 wa_ctx->size = offset - wa_ctx->offset;
1137 WARN(wa_ctx->size % size_alignment,
1138 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1139 wa_ctx->size, size_alignment);
1144 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1146 * @ring: only applicable for RCS
1147 * @wa_ctx: structure representing wa_ctx
1148 * offset: specifies start of the batch, should be cache-aligned. This is updated
1149 * with the offset value received as input.
1150 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1151 * @batch: page in which WA are loaded
1152 * @offset: This field specifies the start of the batch, it should be
1153 * cache-aligned otherwise it is adjusted accordingly.
1154 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1155 * initialized at the beginning and shared across all contexts but this field
1156 * helps us to have multiple batches at different offsets and select them based
1157 * on a criteria. At the moment this batch always start at the beginning of the page
1158 * and at this point we don't have multiple wa_ctx batch buffers.
1160 * The number of WA applied are not known at the beginning; we use this field
1161 * to return the no of DWORDS written.
1163 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1164 * so it adds NOOPs as padding to make it cacheline aligned.
1165 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1166 * makes a complete batch buffer.
1168 * Return: non-zero if we exceed the PAGE_SIZE limit.
1171 static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1172 struct i915_wa_ctx_bb *wa_ctx,
1173 uint32_t *const batch,
1176 uint32_t scratch_addr;
1177 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1179 /* WaDisableCtxRestoreArbitration:bdw,chv */
1180 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1182 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1183 if (IS_BROADWELL(engine->dev)) {
1184 int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1190 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1191 /* Actual scratch location is at 128 bytes offset */
1192 scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1194 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1195 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1196 PIPE_CONTROL_GLOBAL_GTT_IVB |
1197 PIPE_CONTROL_CS_STALL |
1198 PIPE_CONTROL_QW_WRITE));
1199 wa_ctx_emit(batch, index, scratch_addr);
1200 wa_ctx_emit(batch, index, 0);
1201 wa_ctx_emit(batch, index, 0);
1202 wa_ctx_emit(batch, index, 0);
1204 /* Pad to end of cacheline */
1205 while (index % CACHELINE_DWORDS)
1206 wa_ctx_emit(batch, index, MI_NOOP);
1209 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1210 * execution depends on the length specified in terms of cache lines
1211 * in the register CTX_RCS_INDIRECT_CTX
1214 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1218 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1220 * @ring: only applicable for RCS
1221 * @wa_ctx: structure representing wa_ctx
1222 * offset: specifies start of the batch, should be cache-aligned.
1223 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1224 * @batch: page in which WA are loaded
1225 * @offset: This field specifies the start of this batch.
1226 * This batch is started immediately after indirect_ctx batch. Since we ensure
1227 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1229 * The number of DWORDS written are returned using this field.
1231 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1232 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1234 static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1235 struct i915_wa_ctx_bb *wa_ctx,
1236 uint32_t *const batch,
1239 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1241 /* WaDisableCtxRestoreArbitration:bdw,chv */
1242 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1244 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1246 return wa_ctx_end(wa_ctx, *offset = index, 1);
1249 static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1250 struct i915_wa_ctx_bb *wa_ctx,
1251 uint32_t *const batch,
1255 struct drm_device *dev = engine->dev;
1256 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1258 /* WaDisableCtxRestoreArbitration:skl,bxt */
1259 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1260 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1261 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1263 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1264 ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1269 /* Pad to end of cacheline */
1270 while (index % CACHELINE_DWORDS)
1271 wa_ctx_emit(batch, index, MI_NOOP);
1273 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1276 static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1277 struct i915_wa_ctx_bb *wa_ctx,
1278 uint32_t *const batch,
1281 struct drm_device *dev = engine->dev;
1282 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1284 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1285 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
1286 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1287 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1288 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1289 wa_ctx_emit(batch, index,
1290 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1291 wa_ctx_emit(batch, index, MI_NOOP);
1294 /* WaClearTdlStateAckDirtyBits:bxt */
1295 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1296 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
1298 wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
1299 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1301 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1);
1302 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1304 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2);
1305 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1307 wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2);
1308 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1309 wa_ctx_emit(batch, index, 0x0);
1310 wa_ctx_emit(batch, index, MI_NOOP);
1313 /* WaDisableCtxRestoreArbitration:skl,bxt */
1314 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1315 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1316 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1318 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1320 return wa_ctx_end(wa_ctx, *offset = index, 1);
1323 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1327 engine->wa_ctx.obj = i915_gem_object_create(engine->dev,
1329 if (IS_ERR(engine->wa_ctx.obj)) {
1330 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1331 ret = PTR_ERR(engine->wa_ctx.obj);
1332 engine->wa_ctx.obj = NULL;
1336 ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0);
1338 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1340 drm_gem_object_unreference(&engine->wa_ctx.obj->base);
1347 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1349 if (engine->wa_ctx.obj) {
1350 i915_gem_object_ggtt_unpin(engine->wa_ctx.obj);
1351 drm_gem_object_unreference(&engine->wa_ctx.obj->base);
1352 engine->wa_ctx.obj = NULL;
1356 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1362 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1364 WARN_ON(engine->id != RCS);
1366 /* update this when WA for higher Gen are added */
1367 if (INTEL_INFO(engine->dev)->gen > 9) {
1368 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1369 INTEL_INFO(engine->dev)->gen);
1373 /* some WA perform writes to scratch page, ensure it is valid */
1374 if (engine->scratch.obj == NULL) {
1375 DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1379 ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1381 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1385 page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1386 batch = kmap_atomic(page);
1389 if (INTEL_INFO(engine->dev)->gen == 8) {
1390 ret = gen8_init_indirectctx_bb(engine,
1391 &wa_ctx->indirect_ctx,
1397 ret = gen8_init_perctx_bb(engine,
1403 } else if (INTEL_INFO(engine->dev)->gen == 9) {
1404 ret = gen9_init_indirectctx_bb(engine,
1405 &wa_ctx->indirect_ctx,
1411 ret = gen9_init_perctx_bb(engine,
1420 kunmap_atomic(batch);
1422 lrc_destroy_wa_ctx_obj(engine);
1427 static void lrc_init_hws(struct intel_engine_cs *engine)
1429 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1431 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1432 (u32)engine->status_page.gfx_addr);
1433 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1436 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1438 struct drm_device *dev = engine->dev;
1439 struct drm_i915_private *dev_priv = dev->dev_private;
1440 unsigned int next_context_status_buffer_hw;
1442 lrc_init_hws(engine);
1444 I915_WRITE_IMR(engine,
1445 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1446 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1448 I915_WRITE(RING_MODE_GEN7(engine),
1449 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1450 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1451 POSTING_READ(RING_MODE_GEN7(engine));
1454 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1455 * zero, we need to read the write pointer from hardware and use its
1456 * value because "this register is power context save restored".
1457 * Effectively, these states have been observed:
1459 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1460 * BDW | CSB regs not reset | CSB regs reset |
1461 * CHT | CSB regs not reset | CSB regs not reset |
1465 next_context_status_buffer_hw =
1466 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine)));
1469 * When the CSB registers are reset (also after power-up / gpu reset),
1470 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1471 * this special case, so the first element read is CSB[0].
1473 if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
1474 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);
1476 engine->next_context_status_buffer = next_context_status_buffer_hw;
1477 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1479 intel_engine_init_hangcheck(engine);
1481 return intel_mocs_init_engine(engine);
1484 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1486 struct drm_device *dev = engine->dev;
1487 struct drm_i915_private *dev_priv = dev->dev_private;
1490 ret = gen8_init_common_ring(engine);
1494 /* We need to disable the AsyncFlip performance optimisations in order
1495 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1496 * programmed to '1' on all products.
1498 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1500 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1502 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1504 return init_workarounds_ring(engine);
1507 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1511 ret = gen8_init_common_ring(engine);
1515 return init_workarounds_ring(engine);
1518 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1520 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1521 struct intel_engine_cs *engine = req->engine;
1522 struct intel_ringbuffer *ringbuf = req->ringbuf;
1523 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1526 ret = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1530 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1531 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1532 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1534 intel_logical_ring_emit_reg(ringbuf,
1535 GEN8_RING_PDP_UDW(engine, i));
1536 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1537 intel_logical_ring_emit_reg(ringbuf,
1538 GEN8_RING_PDP_LDW(engine, i));
1539 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1542 intel_logical_ring_emit(ringbuf, MI_NOOP);
1543 intel_logical_ring_advance(ringbuf);
1548 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1549 u64 offset, unsigned dispatch_flags)
1551 struct intel_ringbuffer *ringbuf = req->ringbuf;
1552 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1555 /* Don't rely in hw updating PDPs, specially in lite-restore.
1556 * Ideally, we should set Force PD Restore in ctx descriptor,
1557 * but we can't. Force Restore would be a second option, but
1558 * it is unsafe in case of lite-restore (because the ctx is
1559 * not idle). PML4 is allocated during ppgtt init so this is
1560 * not needed in 48-bit.*/
1561 if (req->ctx->ppgtt &&
1562 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1563 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1564 !intel_vgpu_active(req->i915->dev)) {
1565 ret = intel_logical_ring_emit_pdps(req);
1570 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1573 ret = intel_ring_begin(req, 4);
1577 /* FIXME(BDW): Address space and security selectors. */
1578 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1580 (dispatch_flags & I915_DISPATCH_RS ?
1581 MI_BATCH_RESOURCE_STREAMER : 0));
1582 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1583 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1584 intel_logical_ring_emit(ringbuf, MI_NOOP);
1585 intel_logical_ring_advance(ringbuf);
1590 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
1592 struct drm_device *dev = engine->dev;
1593 struct drm_i915_private *dev_priv = dev->dev_private;
1594 unsigned long flags;
1596 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1599 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1600 if (engine->irq_refcount++ == 0) {
1601 I915_WRITE_IMR(engine,
1602 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1603 POSTING_READ(RING_IMR(engine->mmio_base));
1605 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1610 static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
1612 struct drm_device *dev = engine->dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614 unsigned long flags;
1616 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1617 if (--engine->irq_refcount == 0) {
1618 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1619 POSTING_READ(RING_IMR(engine->mmio_base));
1621 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1624 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1625 u32 invalidate_domains,
1628 struct intel_ringbuffer *ringbuf = request->ringbuf;
1629 struct intel_engine_cs *engine = ringbuf->engine;
1630 struct drm_device *dev = engine->dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1635 ret = intel_ring_begin(request, 4);
1639 cmd = MI_FLUSH_DW + 1;
1641 /* We always require a command barrier so that subsequent
1642 * commands, such as breadcrumb interrupts, are strictly ordered
1643 * wrt the contents of the write cache being flushed to memory
1644 * (and thus being coherent from the CPU).
1646 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1648 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1649 cmd |= MI_INVALIDATE_TLB;
1650 if (engine == &dev_priv->engine[VCS])
1651 cmd |= MI_INVALIDATE_BSD;
1654 intel_logical_ring_emit(ringbuf, cmd);
1655 intel_logical_ring_emit(ringbuf,
1656 I915_GEM_HWS_SCRATCH_ADDR |
1657 MI_FLUSH_DW_USE_GTT);
1658 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1659 intel_logical_ring_emit(ringbuf, 0); /* value */
1660 intel_logical_ring_advance(ringbuf);
1665 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1666 u32 invalidate_domains,
1669 struct intel_ringbuffer *ringbuf = request->ringbuf;
1670 struct intel_engine_cs *engine = ringbuf->engine;
1671 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1672 bool vf_flush_wa = false;
1676 flags |= PIPE_CONTROL_CS_STALL;
1678 if (flush_domains) {
1679 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1680 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1681 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1682 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1685 if (invalidate_domains) {
1686 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1687 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1688 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1689 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1690 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1691 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1692 flags |= PIPE_CONTROL_QW_WRITE;
1693 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1696 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1699 if (IS_GEN9(engine->dev))
1703 ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
1708 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1709 intel_logical_ring_emit(ringbuf, 0);
1710 intel_logical_ring_emit(ringbuf, 0);
1711 intel_logical_ring_emit(ringbuf, 0);
1712 intel_logical_ring_emit(ringbuf, 0);
1713 intel_logical_ring_emit(ringbuf, 0);
1716 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1717 intel_logical_ring_emit(ringbuf, flags);
1718 intel_logical_ring_emit(ringbuf, scratch_addr);
1719 intel_logical_ring_emit(ringbuf, 0);
1720 intel_logical_ring_emit(ringbuf, 0);
1721 intel_logical_ring_emit(ringbuf, 0);
1722 intel_logical_ring_advance(ringbuf);
1727 static u32 gen8_get_seqno(struct intel_engine_cs *engine)
1729 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1732 static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1734 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1737 static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
1740 * On BXT A steppings there is a HW coherency issue whereby the
1741 * MI_STORE_DATA_IMM storing the completed request's seqno
1742 * occasionally doesn't invalidate the CPU cache. Work around this by
1743 * clflushing the corresponding cacheline whenever the caller wants
1744 * the coherency to be guaranteed. Note that this cacheline is known
1745 * to be clean at this point, since we only write it in
1746 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1747 * this clflush in practice becomes an invalidate operation.
1749 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1752 static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1754 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1756 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1757 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1761 * Reserve space for 2 NOOPs at the end of each request to be
1762 * used as a workaround for not being allowed to do lite
1763 * restore with HEAD==TAIL (WaIdleLiteRestore).
1765 #define WA_TAIL_DWORDS 2
1767 static inline u32 hws_seqno_address(struct intel_engine_cs *engine)
1769 return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR;
1772 static int gen8_emit_request(struct drm_i915_gem_request *request)
1774 struct intel_ringbuffer *ringbuf = request->ringbuf;
1777 ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS);
1781 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1782 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1784 intel_logical_ring_emit(ringbuf,
1785 (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
1786 intel_logical_ring_emit(ringbuf,
1787 hws_seqno_address(request->engine) |
1788 MI_FLUSH_DW_USE_GTT);
1789 intel_logical_ring_emit(ringbuf, 0);
1790 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1791 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1792 intel_logical_ring_emit(ringbuf, MI_NOOP);
1793 return intel_logical_ring_advance_and_submit(request);
1796 static int gen8_emit_request_render(struct drm_i915_gem_request *request)
1798 struct intel_ringbuffer *ringbuf = request->ringbuf;
1801 ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS);
1805 /* We're using qword write, seqno should be aligned to 8 bytes. */
1806 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1808 /* w/a for post sync ops following a GPGPU operation we
1809 * need a prior CS_STALL, which is emitted by the flush
1810 * following the batch.
1812 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1813 intel_logical_ring_emit(ringbuf,
1814 (PIPE_CONTROL_GLOBAL_GTT_IVB |
1815 PIPE_CONTROL_CS_STALL |
1816 PIPE_CONTROL_QW_WRITE));
1817 intel_logical_ring_emit(ringbuf, hws_seqno_address(request->engine));
1818 intel_logical_ring_emit(ringbuf, 0);
1819 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1820 /* We're thrashing one dword of HWS. */
1821 intel_logical_ring_emit(ringbuf, 0);
1822 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1823 intel_logical_ring_emit(ringbuf, MI_NOOP);
1824 return intel_logical_ring_advance_and_submit(request);
1827 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1829 struct render_state so;
1832 ret = i915_gem_render_state_prepare(req->engine, &so);
1836 if (so.rodata == NULL)
1839 ret = req->engine->emit_bb_start(req, so.ggtt_offset,
1840 I915_DISPATCH_SECURE);
1844 ret = req->engine->emit_bb_start(req,
1845 (so.ggtt_offset + so.aux_batch_offset),
1846 I915_DISPATCH_SECURE);
1850 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1853 i915_gem_render_state_fini(&so);
1857 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1861 ret = intel_logical_ring_workarounds_emit(req);
1865 ret = intel_rcs_context_init_mocs(req);
1867 * Failing to program the MOCS is non-fatal.The system will not
1868 * run at peak performance. So generate an error and carry on.
1871 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1873 return intel_lr_context_render_state_init(req);
1877 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1879 * @ring: Engine Command Streamer.
1882 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1884 struct drm_i915_private *dev_priv;
1886 if (!intel_engine_initialized(engine))
1890 * Tasklet cannot be active at this point due intel_mark_active/idle
1891 * so this is just for documentation.
1893 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
1894 tasklet_kill(&engine->irq_tasklet);
1896 dev_priv = engine->dev->dev_private;
1898 if (engine->buffer) {
1899 intel_logical_ring_stop(engine);
1900 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1903 if (engine->cleanup)
1904 engine->cleanup(engine);
1906 i915_cmd_parser_fini_ring(engine);
1907 i915_gem_batch_pool_fini(&engine->batch_pool);
1909 if (engine->status_page.obj) {
1910 i915_gem_object_unpin_map(engine->status_page.obj);
1911 engine->status_page.obj = NULL;
1913 intel_lr_context_unpin(dev_priv->kernel_context, engine);
1915 engine->idle_lite_restore_wa = 0;
1916 engine->disable_lite_restore_wa = false;
1917 engine->ctx_desc_template = 0;
1919 lrc_destroy_wa_ctx_obj(engine);
1924 logical_ring_default_vfuncs(struct drm_device *dev,
1925 struct intel_engine_cs *engine)
1927 /* Default vfuncs which can be overriden by each engine. */
1928 engine->init_hw = gen8_init_common_ring;
1929 engine->emit_request = gen8_emit_request;
1930 engine->emit_flush = gen8_emit_flush;
1931 engine->irq_get = gen8_logical_ring_get_irq;
1932 engine->irq_put = gen8_logical_ring_put_irq;
1933 engine->emit_bb_start = gen8_emit_bb_start;
1934 engine->get_seqno = gen8_get_seqno;
1935 engine->set_seqno = gen8_set_seqno;
1936 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1937 engine->irq_seqno_barrier = bxt_a_seqno_barrier;
1938 engine->set_seqno = bxt_a_set_seqno;
1943 logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
1945 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1946 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1950 lrc_setup_hws(struct intel_engine_cs *engine,
1951 struct drm_i915_gem_object *dctx_obj)
1955 /* The HWSP is part of the default context object in LRC mode. */
1956 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) +
1957 LRC_PPHWSP_PN * PAGE_SIZE;
1958 hws = i915_gem_object_pin_map(dctx_obj);
1960 return PTR_ERR(hws);
1961 engine->status_page.page_addr = hws + LRC_PPHWSP_PN * PAGE_SIZE;
1962 engine->status_page.obj = dctx_obj;
1968 logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
1970 struct drm_i915_private *dev_priv = to_i915(dev);
1971 struct intel_context *dctx = dev_priv->kernel_context;
1972 enum forcewake_domains fw_domains;
1975 /* Intentionally left blank. */
1976 engine->buffer = NULL;
1979 INIT_LIST_HEAD(&engine->active_list);
1980 INIT_LIST_HEAD(&engine->request_list);
1981 i915_gem_batch_pool_init(dev, &engine->batch_pool);
1982 init_waitqueue_head(&engine->irq_queue);
1984 INIT_LIST_HEAD(&engine->buffers);
1985 INIT_LIST_HEAD(&engine->execlist_queue);
1986 spin_lock_init(&engine->execlist_lock);
1988 tasklet_init(&engine->irq_tasklet,
1989 intel_lrc_irq_handler, (unsigned long)engine);
1991 logical_ring_init_platform_invariants(engine);
1993 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1997 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1998 RING_CONTEXT_STATUS_PTR(engine),
1999 FW_REG_READ | FW_REG_WRITE);
2001 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
2002 RING_CONTEXT_STATUS_BUF_BASE(engine),
2005 engine->fw_domains = fw_domains;
2007 ret = i915_cmd_parser_init_ring(engine);
2011 ret = execlists_context_deferred_alloc(dctx, engine);
2015 /* As this is the default context, always pin it */
2016 ret = intel_lr_context_pin(dctx, engine);
2018 DRM_ERROR("Failed to pin context for %s: %d\n",
2023 /* And setup the hardware status page. */
2024 ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
2026 DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
2033 intel_logical_ring_cleanup(engine);
2037 static int logical_render_ring_init(struct drm_device *dev)
2039 struct drm_i915_private *dev_priv = dev->dev_private;
2040 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2043 engine->name = "render ring";
2045 engine->exec_id = I915_EXEC_RENDER;
2046 engine->guc_id = GUC_RENDER_ENGINE;
2047 engine->mmio_base = RENDER_RING_BASE;
2049 logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT);
2050 if (HAS_L3_DPF(dev))
2051 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2053 logical_ring_default_vfuncs(dev, engine);
2055 /* Override some for render ring. */
2056 if (INTEL_INFO(dev)->gen >= 9)
2057 engine->init_hw = gen9_init_render_ring;
2059 engine->init_hw = gen8_init_render_ring;
2060 engine->init_context = gen8_init_rcs_context;
2061 engine->cleanup = intel_fini_pipe_control;
2062 engine->emit_flush = gen8_emit_flush_render;
2063 engine->emit_request = gen8_emit_request_render;
2067 ret = intel_init_pipe_control(engine);
2071 ret = intel_init_workaround_bb(engine);
2074 * We continue even if we fail to initialize WA batch
2075 * because we only expect rare glitches but nothing
2076 * critical to prevent us from using GPU
2078 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2082 ret = logical_ring_init(dev, engine);
2084 lrc_destroy_wa_ctx_obj(engine);
2090 static int logical_bsd_ring_init(struct drm_device *dev)
2092 struct drm_i915_private *dev_priv = dev->dev_private;
2093 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2095 engine->name = "bsd ring";
2097 engine->exec_id = I915_EXEC_BSD;
2098 engine->guc_id = GUC_VIDEO_ENGINE;
2099 engine->mmio_base = GEN6_BSD_RING_BASE;
2101 logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT);
2102 logical_ring_default_vfuncs(dev, engine);
2104 return logical_ring_init(dev, engine);
2107 static int logical_bsd2_ring_init(struct drm_device *dev)
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2112 engine->name = "bsd2 ring";
2114 engine->exec_id = I915_EXEC_BSD;
2115 engine->guc_id = GUC_VIDEO_ENGINE2;
2116 engine->mmio_base = GEN8_BSD2_RING_BASE;
2118 logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT);
2119 logical_ring_default_vfuncs(dev, engine);
2121 return logical_ring_init(dev, engine);
2124 static int logical_blt_ring_init(struct drm_device *dev)
2126 struct drm_i915_private *dev_priv = dev->dev_private;
2127 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
2129 engine->name = "blitter ring";
2131 engine->exec_id = I915_EXEC_BLT;
2132 engine->guc_id = GUC_BLITTER_ENGINE;
2133 engine->mmio_base = BLT_RING_BASE;
2135 logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT);
2136 logical_ring_default_vfuncs(dev, engine);
2138 return logical_ring_init(dev, engine);
2141 static int logical_vebox_ring_init(struct drm_device *dev)
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
2146 engine->name = "video enhancement ring";
2148 engine->exec_id = I915_EXEC_VEBOX;
2149 engine->guc_id = GUC_VIDEOENHANCE_ENGINE;
2150 engine->mmio_base = VEBOX_RING_BASE;
2152 logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT);
2153 logical_ring_default_vfuncs(dev, engine);
2155 return logical_ring_init(dev, engine);
2159 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2162 * This function inits the engines for an Execlists submission style (the equivalent in the
2163 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2164 * those engines that are present in the hardware.
2166 * Return: non-zero if the initialization failed.
2168 int intel_logical_rings_init(struct drm_device *dev)
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2173 ret = logical_render_ring_init(dev);
2178 ret = logical_bsd_ring_init(dev);
2180 goto cleanup_render_ring;
2184 ret = logical_blt_ring_init(dev);
2186 goto cleanup_bsd_ring;
2189 if (HAS_VEBOX(dev)) {
2190 ret = logical_vebox_ring_init(dev);
2192 goto cleanup_blt_ring;
2195 if (HAS_BSD2(dev)) {
2196 ret = logical_bsd2_ring_init(dev);
2198 goto cleanup_vebox_ring;
2204 intel_logical_ring_cleanup(&dev_priv->engine[VECS]);
2206 intel_logical_ring_cleanup(&dev_priv->engine[BCS]);
2208 intel_logical_ring_cleanup(&dev_priv->engine[VCS]);
2209 cleanup_render_ring:
2210 intel_logical_ring_cleanup(&dev_priv->engine[RCS]);
2216 make_rpcs(struct drm_device *dev)
2221 * No explicit RPCS request is needed to ensure full
2222 * slice/subslice/EU enablement prior to Gen9.
2224 if (INTEL_INFO(dev)->gen < 9)
2228 * Starting in Gen9, render power gating can leave
2229 * slice/subslice/EU in a partially enabled state. We
2230 * must make an explicit request through RPCS for full
2233 if (INTEL_INFO(dev)->has_slice_pg) {
2234 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2235 rpcs |= INTEL_INFO(dev)->slice_total <<
2236 GEN8_RPCS_S_CNT_SHIFT;
2237 rpcs |= GEN8_RPCS_ENABLE;
2240 if (INTEL_INFO(dev)->has_subslice_pg) {
2241 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2242 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2243 GEN8_RPCS_SS_CNT_SHIFT;
2244 rpcs |= GEN8_RPCS_ENABLE;
2247 if (INTEL_INFO(dev)->has_eu_pg) {
2248 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2249 GEN8_RPCS_EU_MIN_SHIFT;
2250 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2251 GEN8_RPCS_EU_MAX_SHIFT;
2252 rpcs |= GEN8_RPCS_ENABLE;
2258 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2260 u32 indirect_ctx_offset;
2262 switch (INTEL_INFO(engine->dev)->gen) {
2264 MISSING_CASE(INTEL_INFO(engine->dev)->gen);
2267 indirect_ctx_offset =
2268 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2271 indirect_ctx_offset =
2272 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2276 return indirect_ctx_offset;
2280 populate_lr_context(struct intel_context *ctx,
2281 struct drm_i915_gem_object *ctx_obj,
2282 struct intel_engine_cs *engine,
2283 struct intel_ringbuffer *ringbuf)
2285 struct drm_device *dev = engine->dev;
2286 struct drm_i915_private *dev_priv = dev->dev_private;
2287 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2293 ppgtt = dev_priv->mm.aliasing_ppgtt;
2295 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2297 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2301 vaddr = i915_gem_object_pin_map(ctx_obj);
2302 if (IS_ERR(vaddr)) {
2303 ret = PTR_ERR(vaddr);
2304 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2307 ctx_obj->dirty = true;
2309 /* The second page of the context object contains some fields which must
2310 * be set up prior to the first execution. */
2311 reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
2313 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2314 * commands followed by (reg, value) pairs. The values we are setting here are
2315 * only for the first context restore: on a subsequent save, the GPU will
2316 * recreate this batchbuffer with new values (including all the missing
2317 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2318 reg_state[CTX_LRI_HEADER_0] =
2319 MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
2320 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
2321 RING_CONTEXT_CONTROL(engine),
2322 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2323 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2324 (HAS_RESOURCE_STREAMER(dev) ?
2325 CTX_CTRL_RS_CTX_ENABLE : 0)));
2326 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
2328 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
2330 /* Ring buffer start address is not known until the buffer is pinned.
2331 * It is written to the context image in execlists_update_context()
2333 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
2334 RING_START(engine->mmio_base), 0);
2335 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
2336 RING_CTL(engine->mmio_base),
2337 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2338 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
2339 RING_BBADDR_UDW(engine->mmio_base), 0);
2340 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
2341 RING_BBADDR(engine->mmio_base), 0);
2342 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
2343 RING_BBSTATE(engine->mmio_base),
2345 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
2346 RING_SBBADDR_UDW(engine->mmio_base), 0);
2347 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
2348 RING_SBBADDR(engine->mmio_base), 0);
2349 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
2350 RING_SBBSTATE(engine->mmio_base), 0);
2351 if (engine->id == RCS) {
2352 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
2353 RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
2354 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
2355 RING_INDIRECT_CTX(engine->mmio_base), 0);
2356 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
2357 RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2358 if (engine->wa_ctx.obj) {
2359 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2360 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2362 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2363 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2364 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2366 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2367 intel_lr_indirect_ctx_offset(engine) << 6;
2369 reg_state[CTX_BB_PER_CTX_PTR+1] =
2370 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2374 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2375 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
2376 RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2377 /* PDP values well be assigned later if needed */
2378 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
2380 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
2382 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
2384 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
2386 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
2388 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
2390 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
2392 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
2395 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2396 /* 64b PPGTT (48bit canonical)
2397 * PDP0_DESCRIPTOR contains the base address to PML4 and
2398 * other PDP Descriptors are ignored.
2400 ASSIGN_CTX_PML4(ppgtt, reg_state);
2403 * PDP*_DESCRIPTOR contains the base address of space supported.
2404 * With dynamic page allocation, PDPs may not be allocated at
2405 * this point. Point the unallocated PDPs to the scratch page
2407 execlists_update_context_pdps(ppgtt, reg_state);
2410 if (engine->id == RCS) {
2411 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2412 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2416 i915_gem_object_unpin_map(ctx_obj);
2422 * intel_lr_context_free() - free the LRC specific bits of a context
2423 * @ctx: the LR context to free.
2425 * The real context freeing is done in i915_gem_context_free: this only
2426 * takes care of the bits that are LRC related: the per-engine backing
2427 * objects and the logical ringbuffer.
2429 void intel_lr_context_free(struct intel_context *ctx)
2433 for (i = I915_NUM_ENGINES; --i >= 0; ) {
2434 struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
2435 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2440 WARN_ON(ctx->engine[i].pin_count);
2441 intel_ringbuffer_free(ringbuf);
2442 drm_gem_object_unreference(&ctx_obj->base);
2447 * intel_lr_context_size() - return the size of the context for an engine
2448 * @ring: which engine to find the context size for
2450 * Each engine may require a different amount of space for a context image,
2451 * so when allocating (or copying) an image, this function can be used to
2452 * find the right size for the specific engine.
2454 * Return: size (in bytes) of an engine-specific context image
2456 * Note: this size includes the HWSP, which is part of the context image
2457 * in LRC mode, but does not include the "shared data page" used with
2458 * GuC submission. The caller should account for this if using the GuC.
2460 uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2464 WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
2466 switch (engine->id) {
2468 if (INTEL_INFO(engine->dev)->gen >= 9)
2469 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2471 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2477 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2485 * execlists_context_deferred_alloc() - create the LRC specific bits of a context
2486 * @ctx: LR context to create.
2487 * @engine: engine to be used with the context.
2489 * This function can be called more than once, with different engines, if we plan
2490 * to use the context with them. The context backing objects and the ringbuffers
2491 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2492 * the creation is a deferred call: it's better to make sure first that we need to use
2493 * a given ring with the context.
2495 * Return: non-zero on error.
2497 static int execlists_context_deferred_alloc(struct intel_context *ctx,
2498 struct intel_engine_cs *engine)
2500 struct drm_device *dev = engine->dev;
2501 struct drm_i915_gem_object *ctx_obj;
2502 uint32_t context_size;
2503 struct intel_ringbuffer *ringbuf;
2506 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2507 WARN_ON(ctx->engine[engine->id].state);
2509 context_size = round_up(intel_lr_context_size(engine), 4096);
2511 /* One extra page as the sharing data between driver and GuC */
2512 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2514 ctx_obj = i915_gem_object_create(dev, context_size);
2515 if (IS_ERR(ctx_obj)) {
2516 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2517 return PTR_ERR(ctx_obj);
2520 ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
2521 if (IS_ERR(ringbuf)) {
2522 ret = PTR_ERR(ringbuf);
2523 goto error_deref_obj;
2526 ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
2528 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2532 ctx->engine[engine->id].ringbuf = ringbuf;
2533 ctx->engine[engine->id].state = ctx_obj;
2534 ctx->engine[engine->id].initialised = engine->init_context == NULL;
2539 intel_ringbuffer_free(ringbuf);
2541 drm_gem_object_unreference(&ctx_obj->base);
2542 ctx->engine[engine->id].ringbuf = NULL;
2543 ctx->engine[engine->id].state = NULL;
2547 void intel_lr_context_reset(struct drm_i915_private *dev_priv,
2548 struct intel_context *ctx)
2550 struct intel_engine_cs *engine;
2552 for_each_engine(engine, dev_priv) {
2553 struct drm_i915_gem_object *ctx_obj =
2554 ctx->engine[engine->id].state;
2555 struct intel_ringbuffer *ringbuf =
2556 ctx->engine[engine->id].ringbuf;
2558 uint32_t *reg_state;
2563 vaddr = i915_gem_object_pin_map(ctx_obj);
2564 if (WARN_ON(IS_ERR(vaddr)))
2567 reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
2568 ctx_obj->dirty = true;
2570 reg_state[CTX_RING_HEAD+1] = 0;
2571 reg_state[CTX_RING_TAIL+1] = 0;
2573 i915_gem_object_unpin_map(ctx_obj);