2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define CTX_LRI_HEADER_0 0x01
158 #define CTX_CONTEXT_CONTROL 0x02
159 #define CTX_RING_HEAD 0x04
160 #define CTX_RING_TAIL 0x06
161 #define CTX_RING_BUFFER_START 0x08
162 #define CTX_RING_BUFFER_CONTROL 0x0a
163 #define CTX_BB_HEAD_U 0x0c
164 #define CTX_BB_HEAD_L 0x0e
165 #define CTX_BB_STATE 0x10
166 #define CTX_SECOND_BB_HEAD_U 0x12
167 #define CTX_SECOND_BB_HEAD_L 0x14
168 #define CTX_SECOND_BB_STATE 0x16
169 #define CTX_BB_PER_CTX_PTR 0x18
170 #define CTX_RCS_INDIRECT_CTX 0x1a
171 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172 #define CTX_LRI_HEADER_1 0x21
173 #define CTX_CTX_TIMESTAMP 0x22
174 #define CTX_PDP3_UDW 0x24
175 #define CTX_PDP3_LDW 0x26
176 #define CTX_PDP2_UDW 0x28
177 #define CTX_PDP2_LDW 0x2a
178 #define CTX_PDP1_UDW 0x2c
179 #define CTX_PDP1_LDW 0x2e
180 #define CTX_PDP0_UDW 0x30
181 #define CTX_PDP0_LDW 0x32
182 #define CTX_LRI_HEADER_2 0x41
183 #define CTX_R_PWR_CLK_STATE 0x42
184 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
186 #define GEN8_CTX_VALID (1<<0)
187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
190 #define GEN8_CTX_PRIVILEGE (1<<8)
192 ADVANCED_CONTEXT = 0,
197 #define GEN8_CTX_MODE_SHIFT 3
200 FAULT_AND_HALT, /* Debug only */
202 FAULT_AND_CONTINUE /* Unsupported */
204 #define GEN8_CTX_ID_SHIFT 32
206 static int intel_lr_context_pin(struct intel_engine_cs *ring,
207 struct intel_context *ctx);
210 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
212 * @enable_execlists: value of i915.enable_execlists module parameter.
214 * Only certain platforms support Execlists (the prerequisites being
215 * support for Logical Ring Contexts and Aliasing PPGTT or better).
217 * Return: 1 if Execlists is supported and has to be enabled.
219 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
221 WARN_ON(i915.enable_ppgtt == -1);
223 if (INTEL_INFO(dev)->gen >= 9)
226 if (enable_execlists == 0)
229 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
230 i915.use_mmio_flip >= 0)
237 * intel_execlists_ctx_id() - get the Execlists Context ID
238 * @ctx_obj: Logical Ring Context backing object.
240 * Do not confuse with ctx->id! Unfortunately we have a name overload
241 * here: the old context ID we pass to userspace as a handler so that
242 * they can refer to a context, and the new context ID we pass to the
243 * ELSP so that the GPU can inform us of the context status via
246 * Return: 20-bits globally unique context ID.
248 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
250 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
252 /* LRCA is required to be 4K aligned so the more significant 20 bits
253 * are globally unique */
257 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
260 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
262 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
264 desc = GEN8_CTX_VALID;
265 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
266 desc |= GEN8_CTX_L3LLC_COHERENT;
267 desc |= GEN8_CTX_PRIVILEGE;
269 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
271 /* TODO: WaDisableLiteRestore when we start using semaphore
272 * signalling between Command Streamers */
273 /* desc |= GEN8_CTX_FORCE_RESTORE; */
278 static void execlists_elsp_write(struct intel_engine_cs *ring,
279 struct drm_i915_gem_object *ctx_obj0,
280 struct drm_i915_gem_object *ctx_obj1)
282 struct drm_device *dev = ring->dev;
283 struct drm_i915_private *dev_priv = dev->dev_private;
287 /* XXX: You must always write both descriptors in the order below. */
289 temp = execlists_ctx_descriptor(ctx_obj1);
292 desc[1] = (u32)(temp >> 32);
295 temp = execlists_ctx_descriptor(ctx_obj0);
296 desc[3] = (u32)(temp >> 32);
299 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
300 I915_WRITE(RING_ELSP(ring), desc[1]);
301 I915_WRITE(RING_ELSP(ring), desc[0]);
302 I915_WRITE(RING_ELSP(ring), desc[3]);
304 /* The context is automatically loaded after the following */
305 I915_WRITE(RING_ELSP(ring), desc[2]);
307 /* ELSP is a wo register, so use another nearby reg for posting instead */
308 POSTING_READ(RING_EXECLIST_STATUS(ring));
309 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
312 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
313 struct drm_i915_gem_object *ring_obj,
319 page = i915_gem_object_get_page(ctx_obj, 1);
320 reg_state = kmap_atomic(page);
322 reg_state[CTX_RING_TAIL+1] = tail;
323 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
325 kunmap_atomic(reg_state);
330 static void execlists_submit_contexts(struct intel_engine_cs *ring,
331 struct intel_context *to0, u32 tail0,
332 struct intel_context *to1, u32 tail1)
334 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
335 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
336 struct drm_i915_gem_object *ctx_obj1 = NULL;
337 struct intel_ringbuffer *ringbuf1 = NULL;
340 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
341 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
343 execlists_update_context(ctx_obj0, ringbuf0->obj, tail0);
346 ringbuf1 = to1->engine[ring->id].ringbuf;
347 ctx_obj1 = to1->engine[ring->id].state;
349 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
350 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
352 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1);
355 execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
358 static void execlists_context_unqueue(struct intel_engine_cs *ring)
360 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
361 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
363 assert_spin_locked(&ring->execlist_lock);
365 if (list_empty(&ring->execlist_queue))
368 /* Try to read in pairs */
369 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
373 } else if (req0->ctx == cursor->ctx) {
374 /* Same ctx: ignore first request, as second request
375 * will update tail past first request's workload */
376 cursor->elsp_submitted = req0->elsp_submitted;
377 list_del(&req0->execlist_link);
378 list_add_tail(&req0->execlist_link,
379 &ring->execlist_retired_req_list);
387 WARN_ON(req1 && req1->elsp_submitted);
389 execlists_submit_contexts(ring, req0->ctx, req0->tail,
390 req1 ? req1->ctx : NULL,
391 req1 ? req1->tail : 0);
393 req0->elsp_submitted++;
395 req1->elsp_submitted++;
398 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
401 struct drm_i915_gem_request *head_req;
403 assert_spin_locked(&ring->execlist_lock);
405 head_req = list_first_entry_or_null(&ring->execlist_queue,
406 struct drm_i915_gem_request,
409 if (head_req != NULL) {
410 struct drm_i915_gem_object *ctx_obj =
411 head_req->ctx->engine[ring->id].state;
412 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
413 WARN(head_req->elsp_submitted == 0,
414 "Never submitted head request\n");
416 if (--head_req->elsp_submitted <= 0) {
417 list_del(&head_req->execlist_link);
418 list_add_tail(&head_req->execlist_link,
419 &ring->execlist_retired_req_list);
429 * intel_lrc_irq_handler() - handle Context Switch interrupts
430 * @ring: Engine Command Streamer to handle.
432 * Check the unread Context Status Buffers and manage the submission of new
433 * contexts to the ELSP accordingly.
435 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
437 struct drm_i915_private *dev_priv = ring->dev->dev_private;
443 u32 submit_contexts = 0;
445 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
447 read_pointer = ring->next_context_status_buffer;
448 write_pointer = status_pointer & 0x07;
449 if (read_pointer > write_pointer)
452 spin_lock(&ring->execlist_lock);
454 while (read_pointer < write_pointer) {
456 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
457 (read_pointer % 6) * 8);
458 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
459 (read_pointer % 6) * 8 + 4);
461 if (status & GEN8_CTX_STATUS_PREEMPTED) {
462 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
463 if (execlists_check_remove_request(ring, status_id))
464 WARN(1, "Lite Restored request removed from queue\n");
466 WARN(1, "Preemption without Lite Restore\n");
469 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
470 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
471 if (execlists_check_remove_request(ring, status_id))
476 if (submit_contexts != 0)
477 execlists_context_unqueue(ring);
479 spin_unlock(&ring->execlist_lock);
481 WARN(submit_contexts > 2, "More than two context complete events?\n");
482 ring->next_context_status_buffer = write_pointer % 6;
484 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
485 ((u32)ring->next_context_status_buffer & 0x07) << 8);
488 static int execlists_context_queue(struct intel_engine_cs *ring,
489 struct intel_context *to,
491 struct drm_i915_gem_request *request)
493 struct drm_i915_gem_request *cursor;
494 struct drm_i915_private *dev_priv = ring->dev->dev_private;
496 int num_elements = 0;
498 if (to != ring->default_context)
499 intel_lr_context_pin(ring, to);
503 * If there isn't a request associated with this submission,
504 * create one as a temporary holder.
506 WARN(1, "execlist context submission without request");
507 request = kzalloc(sizeof(*request), GFP_KERNEL);
510 request->ring = ring;
513 WARN_ON(to != request->ctx);
515 request->tail = tail;
516 i915_gem_request_reference(request);
517 i915_gem_context_reference(request->ctx);
519 intel_runtime_pm_get(dev_priv);
521 spin_lock_irqsave(&ring->execlist_lock, flags);
523 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
524 if (++num_elements > 2)
527 if (num_elements > 2) {
528 struct drm_i915_gem_request *tail_req;
530 tail_req = list_last_entry(&ring->execlist_queue,
531 struct drm_i915_gem_request,
534 if (to == tail_req->ctx) {
535 WARN(tail_req->elsp_submitted != 0,
536 "More than 2 already-submitted reqs queued\n");
537 list_del(&tail_req->execlist_link);
538 list_add_tail(&tail_req->execlist_link,
539 &ring->execlist_retired_req_list);
543 list_add_tail(&request->execlist_link, &ring->execlist_queue);
544 if (num_elements == 0)
545 execlists_context_unqueue(ring);
547 spin_unlock_irqrestore(&ring->execlist_lock, flags);
552 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
553 struct intel_context *ctx)
555 struct intel_engine_cs *ring = ringbuf->ring;
556 uint32_t flush_domains;
560 if (ring->gpu_caches_dirty)
561 flush_domains = I915_GEM_GPU_DOMAINS;
563 ret = ring->emit_flush(ringbuf, ctx,
564 I915_GEM_GPU_DOMAINS, flush_domains);
568 ring->gpu_caches_dirty = false;
572 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
573 struct intel_context *ctx,
574 struct list_head *vmas)
576 struct intel_engine_cs *ring = ringbuf->ring;
577 struct i915_vma *vma;
578 uint32_t flush_domains = 0;
579 bool flush_chipset = false;
582 list_for_each_entry(vma, vmas, exec_list) {
583 struct drm_i915_gem_object *obj = vma->obj;
585 ret = i915_gem_object_sync(obj, ring);
589 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
590 flush_chipset |= i915_gem_clflush_object(obj, false);
592 flush_domains |= obj->base.write_domain;
595 if (flush_domains & I915_GEM_DOMAIN_GTT)
598 /* Unconditionally invalidate gpu caches and ensure that we do flush
599 * any residual writes from the previous batch.
601 return logical_ring_invalidate_all_caches(ringbuf, ctx);
605 * execlists_submission() - submit a batchbuffer for execution, Execlists style
608 * @ring: Engine Command Streamer to submit to.
609 * @ctx: Context to employ for this submission.
610 * @args: execbuffer call arguments.
611 * @vmas: list of vmas.
612 * @batch_obj: the batchbuffer to submit.
613 * @exec_start: batchbuffer start virtual address pointer.
614 * @flags: translated execbuffer call flags.
616 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
617 * away the submission details of the execbuffer ioctl call.
619 * Return: non-zero if the submission fails.
621 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
622 struct intel_engine_cs *ring,
623 struct intel_context *ctx,
624 struct drm_i915_gem_execbuffer2 *args,
625 struct list_head *vmas,
626 struct drm_i915_gem_object *batch_obj,
627 u64 exec_start, u32 flags)
629 struct drm_i915_private *dev_priv = dev->dev_private;
630 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
635 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
636 instp_mask = I915_EXEC_CONSTANTS_MASK;
637 switch (instp_mode) {
638 case I915_EXEC_CONSTANTS_REL_GENERAL:
639 case I915_EXEC_CONSTANTS_ABSOLUTE:
640 case I915_EXEC_CONSTANTS_REL_SURFACE:
641 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
642 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
646 if (instp_mode != dev_priv->relative_constants_mode) {
647 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
648 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
652 /* The HW changed the meaning on this bit on gen6 */
653 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
657 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
661 if (args->num_cliprects != 0) {
662 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
665 if (args->DR4 == 0xffffffff) {
666 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
670 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
671 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
676 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
677 DRM_DEBUG("sol reset is gen7 only\n");
681 ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
685 if (ring == &dev_priv->ring[RCS] &&
686 instp_mode != dev_priv->relative_constants_mode) {
687 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
691 intel_logical_ring_emit(ringbuf, MI_NOOP);
692 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
693 intel_logical_ring_emit(ringbuf, INSTPM);
694 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
695 intel_logical_ring_advance(ringbuf);
697 dev_priv->relative_constants_mode = instp_mode;
700 ret = ring->emit_bb_start(ringbuf, ctx, exec_start, flags);
704 i915_gem_execbuffer_move_to_active(vmas, ring);
705 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
710 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
712 struct drm_i915_gem_request *req, *tmp;
713 struct drm_i915_private *dev_priv = ring->dev->dev_private;
715 struct list_head retired_list;
717 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
718 if (list_empty(&ring->execlist_retired_req_list))
721 INIT_LIST_HEAD(&retired_list);
722 spin_lock_irqsave(&ring->execlist_lock, flags);
723 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
724 spin_unlock_irqrestore(&ring->execlist_lock, flags);
726 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
727 struct intel_context *ctx = req->ctx;
728 struct drm_i915_gem_object *ctx_obj =
729 ctx->engine[ring->id].state;
731 if (ctx_obj && (ctx != ring->default_context))
732 intel_lr_context_unpin(ring, ctx);
733 intel_runtime_pm_put(dev_priv);
734 i915_gem_context_unreference(ctx);
735 list_del(&req->execlist_link);
736 i915_gem_request_unreference(req);
740 void intel_logical_ring_stop(struct intel_engine_cs *ring)
742 struct drm_i915_private *dev_priv = ring->dev->dev_private;
745 if (!intel_ring_initialized(ring))
748 ret = intel_ring_idle(ring);
749 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
750 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
753 /* TODO: Is this correct with Execlists enabled? */
754 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
755 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
756 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
759 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
762 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
763 struct intel_context *ctx)
765 struct intel_engine_cs *ring = ringbuf->ring;
768 if (!ring->gpu_caches_dirty)
771 ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
775 ring->gpu_caches_dirty = false;
780 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
781 * @ringbuf: Logical Ringbuffer to advance.
783 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
784 * really happens during submission is that the context and current tail will be placed
785 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
786 * point, the tail *inside* the context is updated and the ELSP written to.
788 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
789 struct intel_context *ctx,
790 struct drm_i915_gem_request *request)
792 struct intel_engine_cs *ring = ringbuf->ring;
794 intel_logical_ring_advance(ringbuf);
796 if (intel_ring_stopped(ring))
799 execlists_context_queue(ring, ctx, ringbuf->tail, request);
802 static int intel_lr_context_pin(struct intel_engine_cs *ring,
803 struct intel_context *ctx)
805 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
806 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
809 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
810 if (ctx->engine[ring->id].pin_count++ == 0) {
811 ret = i915_gem_obj_ggtt_pin(ctx_obj,
812 GEN8_LR_CONTEXT_ALIGN, 0);
814 goto reset_pin_count;
816 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
824 i915_gem_object_ggtt_unpin(ctx_obj);
826 ctx->engine[ring->id].pin_count = 0;
831 void intel_lr_context_unpin(struct intel_engine_cs *ring,
832 struct intel_context *ctx)
834 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
835 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
838 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
839 if (--ctx->engine[ring->id].pin_count == 0) {
840 intel_unpin_ringbuffer_obj(ringbuf);
841 i915_gem_object_ggtt_unpin(ctx_obj);
846 static int logical_ring_alloc_request(struct intel_engine_cs *ring,
847 struct intel_context *ctx)
849 struct drm_i915_gem_request *request;
850 struct drm_i915_private *dev_private = ring->dev->dev_private;
853 if (ring->outstanding_lazy_request)
856 request = kzalloc(sizeof(*request), GFP_KERNEL);
860 if (ctx != ring->default_context) {
861 ret = intel_lr_context_pin(ring, ctx);
868 kref_init(&request->ref);
869 request->ring = ring;
870 request->uniq = dev_private->request_uniq++;
872 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
874 intel_lr_context_unpin(ring, ctx);
879 /* Hold a reference to the context this request belongs to
880 * (we will need it when the time comes to emit/retire the
884 i915_gem_context_reference(request->ctx);
886 ring->outstanding_lazy_request = request;
890 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
893 struct intel_engine_cs *ring = ringbuf->ring;
894 struct drm_i915_gem_request *request;
897 if (intel_ring_space(ringbuf) >= bytes)
900 list_for_each_entry(request, &ring->request_list, list) {
902 * The request queue is per-engine, so can contain requests
903 * from multiple ringbuffers. Here, we must ignore any that
904 * aren't from the ringbuffer we're considering.
906 struct intel_context *ctx = request->ctx;
907 if (ctx->engine[ring->id].ringbuf != ringbuf)
910 /* Would completion of this request free enough space? */
911 if (__intel_ring_space(request->tail, ringbuf->tail,
912 ringbuf->size) >= bytes) {
917 if (&request->list == &ring->request_list)
920 ret = i915_wait_request(request);
924 i915_gem_retire_requests_ring(ring);
926 return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC;
929 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
930 struct intel_context *ctx,
933 struct intel_engine_cs *ring = ringbuf->ring;
934 struct drm_device *dev = ring->dev;
935 struct drm_i915_private *dev_priv = dev->dev_private;
939 ret = logical_ring_wait_request(ringbuf, bytes);
943 /* Force the context submission in case we have been skipping it */
944 intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL);
946 /* With GEM the hangcheck timer should kick us out of the loop,
947 * leaving it early runs the risk of corrupting GEM state (due
948 * to running on almost untested codepaths). But on resume
949 * timers don't work yet, so prevent a complete hang in that
950 * case by choosing an insanely large timeout. */
951 end = jiffies + 60 * HZ;
955 if (intel_ring_space(ringbuf) >= bytes)
960 if (dev_priv->mm.interruptible && signal_pending(current)) {
965 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
966 dev_priv->mm.interruptible);
970 if (time_after(jiffies, end)) {
979 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
980 struct intel_context *ctx)
982 uint32_t __iomem *virt;
983 int rem = ringbuf->size - ringbuf->tail;
985 if (ringbuf->space < rem) {
986 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
992 virt = ringbuf->virtual_start + ringbuf->tail;
995 iowrite32(MI_NOOP, virt++);
998 intel_ring_update_space(ringbuf);
1003 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
1004 struct intel_context *ctx, int bytes)
1008 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1009 ret = logical_ring_wrap_buffer(ringbuf, ctx);
1014 if (unlikely(ringbuf->space < bytes)) {
1015 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
1024 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1026 * @ringbuf: Logical ringbuffer.
1027 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1029 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1030 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1031 * and also preallocates a request (every workload submission is still mediated through
1032 * requests, same as it did with legacy ringbuffer submission).
1034 * Return: non-zero if the ringbuffer is not ready to be written to.
1036 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
1037 struct intel_context *ctx, int num_dwords)
1039 struct intel_engine_cs *ring = ringbuf->ring;
1040 struct drm_device *dev = ring->dev;
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1044 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1045 dev_priv->mm.interruptible);
1049 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
1053 /* Preallocate the olr before touching the ring */
1054 ret = logical_ring_alloc_request(ring, ctx);
1058 ringbuf->space -= num_dwords * sizeof(uint32_t);
1062 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1063 struct intel_context *ctx)
1066 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1067 struct drm_device *dev = ring->dev;
1068 struct drm_i915_private *dev_priv = dev->dev_private;
1069 struct i915_workarounds *w = &dev_priv->workarounds;
1071 if (WARN_ON_ONCE(w->count == 0))
1074 ring->gpu_caches_dirty = true;
1075 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1079 ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
1083 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1084 for (i = 0; i < w->count; i++) {
1085 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1086 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1088 intel_logical_ring_emit(ringbuf, MI_NOOP);
1090 intel_logical_ring_advance(ringbuf);
1092 ring->gpu_caches_dirty = true;
1093 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1100 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1102 struct drm_device *dev = ring->dev;
1103 struct drm_i915_private *dev_priv = dev->dev_private;
1105 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1106 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1108 I915_WRITE(RING_MODE_GEN7(ring),
1109 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1110 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1111 POSTING_READ(RING_MODE_GEN7(ring));
1112 ring->next_context_status_buffer = 0;
1113 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1115 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1120 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1122 struct drm_device *dev = ring->dev;
1123 struct drm_i915_private *dev_priv = dev->dev_private;
1126 ret = gen8_init_common_ring(ring);
1130 /* We need to disable the AsyncFlip performance optimisations in order
1131 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1132 * programmed to '1' on all products.
1134 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1136 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1138 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1140 return init_workarounds_ring(ring);
1143 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1144 struct intel_context *ctx,
1145 u64 offset, unsigned flags)
1147 bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1150 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1154 /* FIXME(BDW): Address space and security selectors. */
1155 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1156 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1157 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1158 intel_logical_ring_emit(ringbuf, MI_NOOP);
1159 intel_logical_ring_advance(ringbuf);
1164 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1166 struct drm_device *dev = ring->dev;
1167 struct drm_i915_private *dev_priv = dev->dev_private;
1168 unsigned long flags;
1170 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1173 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1174 if (ring->irq_refcount++ == 0) {
1175 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1176 POSTING_READ(RING_IMR(ring->mmio_base));
1178 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1183 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1185 struct drm_device *dev = ring->dev;
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 unsigned long flags;
1189 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1190 if (--ring->irq_refcount == 0) {
1191 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1192 POSTING_READ(RING_IMR(ring->mmio_base));
1194 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1197 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1198 struct intel_context *ctx,
1199 u32 invalidate_domains,
1202 struct intel_engine_cs *ring = ringbuf->ring;
1203 struct drm_device *dev = ring->dev;
1204 struct drm_i915_private *dev_priv = dev->dev_private;
1208 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1212 cmd = MI_FLUSH_DW + 1;
1214 if (ring == &dev_priv->ring[VCS]) {
1215 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
1216 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1217 MI_FLUSH_DW_STORE_INDEX |
1218 MI_FLUSH_DW_OP_STOREDW;
1220 if (invalidate_domains & I915_GEM_DOMAIN_RENDER)
1221 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1222 MI_FLUSH_DW_OP_STOREDW;
1225 intel_logical_ring_emit(ringbuf, cmd);
1226 intel_logical_ring_emit(ringbuf,
1227 I915_GEM_HWS_SCRATCH_ADDR |
1228 MI_FLUSH_DW_USE_GTT);
1229 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1230 intel_logical_ring_emit(ringbuf, 0); /* value */
1231 intel_logical_ring_advance(ringbuf);
1236 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1237 struct intel_context *ctx,
1238 u32 invalidate_domains,
1241 struct intel_engine_cs *ring = ringbuf->ring;
1242 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1246 flags |= PIPE_CONTROL_CS_STALL;
1248 if (flush_domains) {
1249 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1250 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1253 if (invalidate_domains) {
1254 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1255 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1256 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1257 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1258 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1259 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1260 flags |= PIPE_CONTROL_QW_WRITE;
1261 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1264 ret = intel_logical_ring_begin(ringbuf, ctx, 6);
1268 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1269 intel_logical_ring_emit(ringbuf, flags);
1270 intel_logical_ring_emit(ringbuf, scratch_addr);
1271 intel_logical_ring_emit(ringbuf, 0);
1272 intel_logical_ring_emit(ringbuf, 0);
1273 intel_logical_ring_emit(ringbuf, 0);
1274 intel_logical_ring_advance(ringbuf);
1279 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1281 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1284 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1286 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1289 static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1290 struct drm_i915_gem_request *request)
1292 struct intel_engine_cs *ring = ringbuf->ring;
1296 ret = intel_logical_ring_begin(ringbuf, request->ctx, 6);
1300 cmd = MI_STORE_DWORD_IMM_GEN4;
1301 cmd |= MI_GLOBAL_GTT;
1303 intel_logical_ring_emit(ringbuf, cmd);
1304 intel_logical_ring_emit(ringbuf,
1305 (ring->status_page.gfx_addr +
1306 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1307 intel_logical_ring_emit(ringbuf, 0);
1308 intel_logical_ring_emit(ringbuf,
1309 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1310 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1311 intel_logical_ring_emit(ringbuf, MI_NOOP);
1312 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1317 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1318 struct intel_context *ctx)
1322 ret = intel_logical_ring_workarounds_emit(ring, ctx);
1326 return intel_lr_context_render_state_init(ring, ctx);
1330 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1332 * @ring: Engine Command Streamer.
1335 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1337 struct drm_i915_private *dev_priv;
1339 if (!intel_ring_initialized(ring))
1342 dev_priv = ring->dev->dev_private;
1344 intel_logical_ring_stop(ring);
1345 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1346 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1349 ring->cleanup(ring);
1351 i915_cmd_parser_fini_ring(ring);
1353 if (ring->status_page.obj) {
1354 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1355 ring->status_page.obj = NULL;
1359 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1363 /* Intentionally left blank. */
1364 ring->buffer = NULL;
1367 INIT_LIST_HEAD(&ring->active_list);
1368 INIT_LIST_HEAD(&ring->request_list);
1369 init_waitqueue_head(&ring->irq_queue);
1371 INIT_LIST_HEAD(&ring->execlist_queue);
1372 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1373 spin_lock_init(&ring->execlist_lock);
1375 ret = i915_cmd_parser_init_ring(ring);
1379 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1384 static int logical_render_ring_init(struct drm_device *dev)
1386 struct drm_i915_private *dev_priv = dev->dev_private;
1387 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1390 ring->name = "render ring";
1392 ring->mmio_base = RENDER_RING_BASE;
1393 ring->irq_enable_mask =
1394 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1395 ring->irq_keep_mask =
1396 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1397 if (HAS_L3_DPF(dev))
1398 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1400 ring->init_hw = gen8_init_render_ring;
1401 ring->init_context = gen8_init_rcs_context;
1402 ring->cleanup = intel_fini_pipe_control;
1403 ring->get_seqno = gen8_get_seqno;
1404 ring->set_seqno = gen8_set_seqno;
1405 ring->emit_request = gen8_emit_request;
1406 ring->emit_flush = gen8_emit_flush_render;
1407 ring->irq_get = gen8_logical_ring_get_irq;
1408 ring->irq_put = gen8_logical_ring_put_irq;
1409 ring->emit_bb_start = gen8_emit_bb_start;
1412 ret = logical_ring_init(dev, ring);
1416 return intel_init_pipe_control(ring);
1419 static int logical_bsd_ring_init(struct drm_device *dev)
1421 struct drm_i915_private *dev_priv = dev->dev_private;
1422 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1424 ring->name = "bsd ring";
1426 ring->mmio_base = GEN6_BSD_RING_BASE;
1427 ring->irq_enable_mask =
1428 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1429 ring->irq_keep_mask =
1430 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1432 ring->init_hw = gen8_init_common_ring;
1433 ring->get_seqno = gen8_get_seqno;
1434 ring->set_seqno = gen8_set_seqno;
1435 ring->emit_request = gen8_emit_request;
1436 ring->emit_flush = gen8_emit_flush;
1437 ring->irq_get = gen8_logical_ring_get_irq;
1438 ring->irq_put = gen8_logical_ring_put_irq;
1439 ring->emit_bb_start = gen8_emit_bb_start;
1441 return logical_ring_init(dev, ring);
1444 static int logical_bsd2_ring_init(struct drm_device *dev)
1446 struct drm_i915_private *dev_priv = dev->dev_private;
1447 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1449 ring->name = "bds2 ring";
1451 ring->mmio_base = GEN8_BSD2_RING_BASE;
1452 ring->irq_enable_mask =
1453 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1454 ring->irq_keep_mask =
1455 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1457 ring->init_hw = gen8_init_common_ring;
1458 ring->get_seqno = gen8_get_seqno;
1459 ring->set_seqno = gen8_set_seqno;
1460 ring->emit_request = gen8_emit_request;
1461 ring->emit_flush = gen8_emit_flush;
1462 ring->irq_get = gen8_logical_ring_get_irq;
1463 ring->irq_put = gen8_logical_ring_put_irq;
1464 ring->emit_bb_start = gen8_emit_bb_start;
1466 return logical_ring_init(dev, ring);
1469 static int logical_blt_ring_init(struct drm_device *dev)
1471 struct drm_i915_private *dev_priv = dev->dev_private;
1472 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1474 ring->name = "blitter ring";
1476 ring->mmio_base = BLT_RING_BASE;
1477 ring->irq_enable_mask =
1478 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1479 ring->irq_keep_mask =
1480 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1482 ring->init_hw = gen8_init_common_ring;
1483 ring->get_seqno = gen8_get_seqno;
1484 ring->set_seqno = gen8_set_seqno;
1485 ring->emit_request = gen8_emit_request;
1486 ring->emit_flush = gen8_emit_flush;
1487 ring->irq_get = gen8_logical_ring_get_irq;
1488 ring->irq_put = gen8_logical_ring_put_irq;
1489 ring->emit_bb_start = gen8_emit_bb_start;
1491 return logical_ring_init(dev, ring);
1494 static int logical_vebox_ring_init(struct drm_device *dev)
1496 struct drm_i915_private *dev_priv = dev->dev_private;
1497 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1499 ring->name = "video enhancement ring";
1501 ring->mmio_base = VEBOX_RING_BASE;
1502 ring->irq_enable_mask =
1503 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1504 ring->irq_keep_mask =
1505 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1507 ring->init_hw = gen8_init_common_ring;
1508 ring->get_seqno = gen8_get_seqno;
1509 ring->set_seqno = gen8_set_seqno;
1510 ring->emit_request = gen8_emit_request;
1511 ring->emit_flush = gen8_emit_flush;
1512 ring->irq_get = gen8_logical_ring_get_irq;
1513 ring->irq_put = gen8_logical_ring_put_irq;
1514 ring->emit_bb_start = gen8_emit_bb_start;
1516 return logical_ring_init(dev, ring);
1520 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1523 * This function inits the engines for an Execlists submission style (the equivalent in the
1524 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1525 * those engines that are present in the hardware.
1527 * Return: non-zero if the initialization failed.
1529 int intel_logical_rings_init(struct drm_device *dev)
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1534 ret = logical_render_ring_init(dev);
1539 ret = logical_bsd_ring_init(dev);
1541 goto cleanup_render_ring;
1545 ret = logical_blt_ring_init(dev);
1547 goto cleanup_bsd_ring;
1550 if (HAS_VEBOX(dev)) {
1551 ret = logical_vebox_ring_init(dev);
1553 goto cleanup_blt_ring;
1556 if (HAS_BSD2(dev)) {
1557 ret = logical_bsd2_ring_init(dev);
1559 goto cleanup_vebox_ring;
1562 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1564 goto cleanup_bsd2_ring;
1569 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1571 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1573 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1575 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1576 cleanup_render_ring:
1577 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1582 int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1583 struct intel_context *ctx)
1585 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1586 struct render_state so;
1587 struct drm_i915_file_private *file_priv = ctx->file_priv;
1588 struct drm_file *file = file_priv ? file_priv->file : NULL;
1591 ret = i915_gem_render_state_prepare(ring, &so);
1595 if (so.rodata == NULL)
1598 ret = ring->emit_bb_start(ringbuf,
1601 I915_DISPATCH_SECURE);
1605 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1607 ret = __i915_add_request(ring, file, so.obj);
1608 /* intel_logical_ring_add_request moves object to inactive if it
1611 i915_gem_render_state_fini(&so);
1616 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1617 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1619 struct drm_device *dev = ring->dev;
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1623 uint32_t *reg_state;
1627 ppgtt = dev_priv->mm.aliasing_ppgtt;
1629 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1631 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1635 ret = i915_gem_object_get_pages(ctx_obj);
1637 DRM_DEBUG_DRIVER("Could not get object pages\n");
1641 i915_gem_object_pin_pages(ctx_obj);
1643 /* The second page of the context object contains some fields which must
1644 * be set up prior to the first execution. */
1645 page = i915_gem_object_get_page(ctx_obj, 1);
1646 reg_state = kmap_atomic(page);
1648 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1649 * commands followed by (reg, value) pairs. The values we are setting here are
1650 * only for the first context restore: on a subsequent save, the GPU will
1651 * recreate this batchbuffer with new values (including all the missing
1652 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1653 if (ring->id == RCS)
1654 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1656 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1657 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1658 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1659 reg_state[CTX_CONTEXT_CONTROL+1] =
1660 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
1661 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1662 reg_state[CTX_RING_HEAD+1] = 0;
1663 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1664 reg_state[CTX_RING_TAIL+1] = 0;
1665 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1666 /* Ring buffer start address is not known until the buffer is pinned.
1667 * It is written to the context image in execlists_update_context()
1669 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1670 reg_state[CTX_RING_BUFFER_CONTROL+1] =
1671 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1672 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1673 reg_state[CTX_BB_HEAD_U+1] = 0;
1674 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1675 reg_state[CTX_BB_HEAD_L+1] = 0;
1676 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1677 reg_state[CTX_BB_STATE+1] = (1<<5);
1678 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1679 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1680 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1681 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1682 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1683 reg_state[CTX_SECOND_BB_STATE+1] = 0;
1684 if (ring->id == RCS) {
1685 /* TODO: according to BSpec, the register state context
1686 * for CHV does not have these. OTOH, these registers do
1687 * exist in CHV. I'm waiting for a clarification */
1688 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1689 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1690 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1691 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1692 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1693 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1695 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1696 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1697 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1698 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1699 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1700 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1701 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1702 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1703 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1704 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1705 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1706 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1707 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1708 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1709 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1710 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1711 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1712 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1713 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1714 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1715 if (ring->id == RCS) {
1716 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1717 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1718 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1721 kunmap_atomic(reg_state);
1724 set_page_dirty(page);
1725 i915_gem_object_unpin_pages(ctx_obj);
1731 * intel_lr_context_free() - free the LRC specific bits of a context
1732 * @ctx: the LR context to free.
1734 * The real context freeing is done in i915_gem_context_free: this only
1735 * takes care of the bits that are LRC related: the per-engine backing
1736 * objects and the logical ringbuffer.
1738 void intel_lr_context_free(struct intel_context *ctx)
1742 for (i = 0; i < I915_NUM_RINGS; i++) {
1743 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1746 struct intel_ringbuffer *ringbuf =
1747 ctx->engine[i].ringbuf;
1748 struct intel_engine_cs *ring = ringbuf->ring;
1750 if (ctx == ring->default_context) {
1751 intel_unpin_ringbuffer_obj(ringbuf);
1752 i915_gem_object_ggtt_unpin(ctx_obj);
1754 WARN_ON(ctx->engine[ring->id].pin_count);
1755 intel_destroy_ringbuffer_obj(ringbuf);
1757 drm_gem_object_unreference(&ctx_obj->base);
1762 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1766 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1770 if (INTEL_INFO(ring->dev)->gen >= 9)
1771 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1773 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1779 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1786 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1787 struct drm_i915_gem_object *default_ctx_obj)
1789 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1791 /* The status page is offset 0 from the default context object
1793 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1794 ring->status_page.page_addr =
1795 kmap(sg_page(default_ctx_obj->pages->sgl));
1796 ring->status_page.obj = default_ctx_obj;
1798 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1799 (u32)ring->status_page.gfx_addr);
1800 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1804 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1805 * @ctx: LR context to create.
1806 * @ring: engine to be used with the context.
1808 * This function can be called more than once, with different engines, if we plan
1809 * to use the context with them. The context backing objects and the ringbuffers
1810 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1811 * the creation is a deferred call: it's better to make sure first that we need to use
1812 * a given ring with the context.
1814 * Return: non-zero on error.
1816 int intel_lr_context_deferred_create(struct intel_context *ctx,
1817 struct intel_engine_cs *ring)
1819 const bool is_global_default_ctx = (ctx == ring->default_context);
1820 struct drm_device *dev = ring->dev;
1821 struct drm_i915_gem_object *ctx_obj;
1822 uint32_t context_size;
1823 struct intel_ringbuffer *ringbuf;
1826 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1827 WARN_ON(ctx->engine[ring->id].state);
1829 context_size = round_up(get_lr_context_size(ring), 4096);
1831 ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1832 if (IS_ERR(ctx_obj)) {
1833 ret = PTR_ERR(ctx_obj);
1834 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1838 if (is_global_default_ctx) {
1839 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1841 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1843 drm_gem_object_unreference(&ctx_obj->base);
1848 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1850 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1853 goto error_unpin_ctx;
1856 ringbuf->ring = ring;
1858 ringbuf->size = 32 * PAGE_SIZE;
1859 ringbuf->effective_size = ringbuf->size;
1862 ringbuf->last_retired_head = -1;
1863 intel_ring_update_space(ringbuf);
1865 if (ringbuf->obj == NULL) {
1866 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1869 "Failed to allocate ringbuffer obj %s: %d\n",
1871 goto error_free_rbuf;
1874 if (is_global_default_ctx) {
1875 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1878 "Failed to pin and map ringbuffer %s: %d\n",
1880 goto error_destroy_rbuf;
1886 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1888 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1892 ctx->engine[ring->id].ringbuf = ringbuf;
1893 ctx->engine[ring->id].state = ctx_obj;
1895 if (ctx == ring->default_context)
1896 lrc_setup_hardware_status_page(ring, ctx_obj);
1897 else if (ring->id == RCS && !ctx->rcs_initialized) {
1898 if (ring->init_context) {
1899 ret = ring->init_context(ring, ctx);
1901 DRM_ERROR("ring init context: %d\n", ret);
1902 ctx->engine[ring->id].ringbuf = NULL;
1903 ctx->engine[ring->id].state = NULL;
1908 ctx->rcs_initialized = true;
1914 if (is_global_default_ctx)
1915 intel_unpin_ringbuffer_obj(ringbuf);
1917 intel_destroy_ringbuffer_obj(ringbuf);
1921 if (is_global_default_ctx)
1922 i915_gem_object_ggtt_unpin(ctx_obj);
1923 drm_gem_object_unreference(&ctx_obj->base);