2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
194 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
195 (reg_state)[(pos)+1] = (val); \
198 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
199 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
200 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
201 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
204 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
205 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
206 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
210 ADVANCED_CONTEXT = 0,
215 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
216 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
217 LEGACY_64B_CONTEXT :\
221 FAULT_AND_HALT, /* Debug only */
223 FAULT_AND_CONTINUE /* Unsupported */
225 #define GEN8_CTX_ID_SHIFT 32
226 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
228 static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
229 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
230 struct drm_i915_gem_object *default_ctx_obj);
234 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
236 * @enable_execlists: value of i915.enable_execlists module parameter.
238 * Only certain platforms support Execlists (the prerequisites being
239 * support for Logical Ring Contexts and Aliasing PPGTT or better).
241 * Return: 1 if Execlists is supported and has to be enabled.
243 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
245 WARN_ON(i915.enable_ppgtt == -1);
247 /* On platforms with execlist available, vGPU will only
248 * support execlist mode, no ring buffer mode.
250 if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
253 if (INTEL_INFO(dev)->gen >= 9)
256 if (enable_execlists == 0)
259 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
260 i915.use_mmio_flip >= 0)
267 * intel_execlists_ctx_id() - get the Execlists Context ID
268 * @ctx_obj: Logical Ring Context backing object.
270 * Do not confuse with ctx->id! Unfortunately we have a name overload
271 * here: the old context ID we pass to userspace as a handler so that
272 * they can refer to a context, and the new context ID we pass to the
273 * ELSP so that the GPU can inform us of the context status via
276 * Return: 20-bits globally unique context ID.
278 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
280 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj) +
281 LRC_PPHWSP_PN * PAGE_SIZE;
283 /* LRCA is required to be 4K aligned so the more significant 20 bits
284 * are globally unique */
288 static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
290 struct drm_device *dev = ring->dev;
292 return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
293 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
294 (ring->id == VCS || ring->id == VCS2);
297 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
298 struct intel_engine_cs *ring)
300 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
302 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj) +
303 LRC_PPHWSP_PN * PAGE_SIZE;
305 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
307 desc = GEN8_CTX_VALID;
308 desc |= GEN8_CTX_ADDRESSING_MODE(dev) << GEN8_CTX_ADDRESSING_MODE_SHIFT;
309 if (IS_GEN8(ctx_obj->base.dev))
310 desc |= GEN8_CTX_L3LLC_COHERENT;
311 desc |= GEN8_CTX_PRIVILEGE;
313 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
315 /* TODO: WaDisableLiteRestore when we start using semaphore
316 * signalling between Command Streamers */
317 /* desc |= GEN8_CTX_FORCE_RESTORE; */
319 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
320 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
321 if (disable_lite_restore_wa(ring))
322 desc |= GEN8_CTX_FORCE_RESTORE;
327 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
328 struct drm_i915_gem_request *rq1)
331 struct intel_engine_cs *ring = rq0->ring;
332 struct drm_device *dev = ring->dev;
333 struct drm_i915_private *dev_priv = dev->dev_private;
337 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring);
338 rq1->elsp_submitted++;
343 desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring);
344 rq0->elsp_submitted++;
346 /* You must always write both descriptors in the order below. */
347 spin_lock(&dev_priv->uncore.lock);
348 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
349 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
350 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
352 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
353 /* The context is automatically loaded after the following */
354 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
356 /* ELSP is a wo register, use another nearby reg for posting */
357 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
358 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
359 spin_unlock(&dev_priv->uncore.lock);
362 static int execlists_update_context(struct drm_i915_gem_request *rq)
364 struct intel_engine_cs *ring = rq->ring;
365 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
366 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
367 struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
372 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
373 WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
375 page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
376 reg_state = kmap_atomic(page);
378 reg_state[CTX_RING_TAIL+1] = rq->tail;
379 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
381 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
382 /* True 32b PPGTT with dynamic page allocation: update PDP
383 * registers and point the unallocated PDPs to scratch page.
384 * PML4 is allocated during ppgtt init, so this is not needed
387 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
388 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
389 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
390 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
393 kunmap_atomic(reg_state);
398 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
399 struct drm_i915_gem_request *rq1)
401 execlists_update_context(rq0);
404 execlists_update_context(rq1);
406 execlists_elsp_write(rq0, rq1);
409 static void execlists_context_unqueue(struct intel_engine_cs *ring)
411 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
412 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
414 assert_spin_locked(&ring->execlist_lock);
417 * If irqs are not active generate a warning as batches that finish
418 * without the irqs may get lost and a GPU Hang may occur.
420 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
422 if (list_empty(&ring->execlist_queue))
425 /* Try to read in pairs */
426 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
430 } else if (req0->ctx == cursor->ctx) {
431 /* Same ctx: ignore first request, as second request
432 * will update tail past first request's workload */
433 cursor->elsp_submitted = req0->elsp_submitted;
434 list_move_tail(&req0->execlist_link,
435 &ring->execlist_retired_req_list);
443 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
445 * WaIdleLiteRestore: make sure we never cause a lite
446 * restore with HEAD==TAIL
448 if (req0->elsp_submitted) {
450 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
451 * as we resubmit the request. See gen8_emit_request()
452 * for where we prepare the padding after the end of the
455 struct intel_ringbuffer *ringbuf;
457 ringbuf = req0->ctx->engine[ring->id].ringbuf;
459 req0->tail &= ringbuf->size - 1;
463 WARN_ON(req1 && req1->elsp_submitted);
465 execlists_submit_requests(req0, req1);
468 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
471 struct drm_i915_gem_request *head_req;
473 assert_spin_locked(&ring->execlist_lock);
475 head_req = list_first_entry_or_null(&ring->execlist_queue,
476 struct drm_i915_gem_request,
479 if (head_req != NULL) {
480 struct drm_i915_gem_object *ctx_obj =
481 head_req->ctx->engine[ring->id].state;
482 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
483 WARN(head_req->elsp_submitted == 0,
484 "Never submitted head request\n");
486 if (--head_req->elsp_submitted <= 0) {
487 list_move_tail(&head_req->execlist_link,
488 &ring->execlist_retired_req_list);
497 static void get_context_status(struct intel_engine_cs *ring,
499 u32 *status, u32 *context_id)
501 struct drm_i915_private *dev_priv = ring->dev->dev_private;
503 if (WARN_ON(read_pointer >= GEN8_CSB_ENTRIES))
506 *status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer));
507 *context_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer));
511 * intel_lrc_irq_handler() - handle Context Switch interrupts
512 * @ring: Engine Command Streamer to handle.
514 * Check the unread Context Status Buffers and manage the submission of new
515 * contexts to the ELSP accordingly.
517 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
519 struct drm_i915_private *dev_priv = ring->dev->dev_private;
525 u32 submit_contexts = 0;
527 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
529 read_pointer = ring->next_context_status_buffer;
530 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
531 if (read_pointer > write_pointer)
532 write_pointer += GEN8_CSB_ENTRIES;
534 spin_lock(&ring->execlist_lock);
536 while (read_pointer < write_pointer) {
538 get_context_status(ring, ++read_pointer % GEN8_CSB_ENTRIES,
539 &status, &status_id);
541 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
544 if (status & GEN8_CTX_STATUS_PREEMPTED) {
545 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
546 if (execlists_check_remove_request(ring, status_id))
547 WARN(1, "Lite Restored request removed from queue\n");
549 WARN(1, "Preemption without Lite Restore\n");
552 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
553 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
554 if (execlists_check_remove_request(ring, status_id))
559 if (disable_lite_restore_wa(ring)) {
560 /* Prevent a ctx to preempt itself */
561 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) &&
562 (submit_contexts != 0))
563 execlists_context_unqueue(ring);
564 } else if (submit_contexts != 0) {
565 execlists_context_unqueue(ring);
568 spin_unlock(&ring->execlist_lock);
570 if (unlikely(submit_contexts > 2))
571 DRM_ERROR("More than two context complete events?\n");
573 ring->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
575 /* Update the read pointer to the old write pointer. Manual ringbuffer
576 * management ftw </sarcasm> */
577 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
578 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
579 ring->next_context_status_buffer << 8));
582 static int execlists_context_queue(struct drm_i915_gem_request *request)
584 struct intel_engine_cs *ring = request->ring;
585 struct drm_i915_gem_request *cursor;
586 int num_elements = 0;
588 if (request->ctx != ring->default_context)
589 intel_lr_context_pin(request);
591 i915_gem_request_reference(request);
593 spin_lock_irq(&ring->execlist_lock);
595 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
596 if (++num_elements > 2)
599 if (num_elements > 2) {
600 struct drm_i915_gem_request *tail_req;
602 tail_req = list_last_entry(&ring->execlist_queue,
603 struct drm_i915_gem_request,
606 if (request->ctx == tail_req->ctx) {
607 WARN(tail_req->elsp_submitted != 0,
608 "More than 2 already-submitted reqs queued\n");
609 list_move_tail(&tail_req->execlist_link,
610 &ring->execlist_retired_req_list);
614 list_add_tail(&request->execlist_link, &ring->execlist_queue);
615 if (num_elements == 0)
616 execlists_context_unqueue(ring);
618 spin_unlock_irq(&ring->execlist_lock);
623 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
625 struct intel_engine_cs *ring = req->ring;
626 uint32_t flush_domains;
630 if (ring->gpu_caches_dirty)
631 flush_domains = I915_GEM_GPU_DOMAINS;
633 ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
637 ring->gpu_caches_dirty = false;
641 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
642 struct list_head *vmas)
644 const unsigned other_rings = ~intel_ring_flag(req->ring);
645 struct i915_vma *vma;
646 uint32_t flush_domains = 0;
647 bool flush_chipset = false;
650 list_for_each_entry(vma, vmas, exec_list) {
651 struct drm_i915_gem_object *obj = vma->obj;
653 if (obj->active & other_rings) {
654 ret = i915_gem_object_sync(obj, req->ring, &req);
659 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
660 flush_chipset |= i915_gem_clflush_object(obj, false);
662 flush_domains |= obj->base.write_domain;
665 if (flush_domains & I915_GEM_DOMAIN_GTT)
668 /* Unconditionally invalidate gpu caches and ensure that we do flush
669 * any residual writes from the previous batch.
671 return logical_ring_invalidate_all_caches(req);
674 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
678 request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
680 if (request->ctx != request->ring->default_context) {
681 ret = intel_lr_context_pin(request);
686 if (i915.enable_guc_submission) {
688 * Check that the GuC has space for the request before
689 * going any further, as the i915_add_request() call
690 * later on mustn't fail ...
692 struct intel_guc *guc = &request->i915->guc;
694 ret = i915_guc_wq_check_space(guc->execbuf_client);
702 static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
705 struct intel_ringbuffer *ringbuf = req->ringbuf;
706 struct intel_engine_cs *ring = req->ring;
707 struct drm_i915_gem_request *target;
711 if (intel_ring_space(ringbuf) >= bytes)
714 /* The whole point of reserving space is to not wait! */
715 WARN_ON(ringbuf->reserved_in_use);
717 list_for_each_entry(target, &ring->request_list, list) {
719 * The request queue is per-engine, so can contain requests
720 * from multiple ringbuffers. Here, we must ignore any that
721 * aren't from the ringbuffer we're considering.
723 if (target->ringbuf != ringbuf)
726 /* Would completion of this request free enough space? */
727 space = __intel_ring_space(target->postfix, ringbuf->tail,
733 if (WARN_ON(&target->list == &ring->request_list))
736 ret = i915_wait_request(target);
740 ringbuf->space = space;
745 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
746 * @request: Request to advance the logical ringbuffer of.
748 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
749 * really happens during submission is that the context and current tail will be placed
750 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
751 * point, the tail *inside* the context is updated and the ELSP written to.
754 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
756 struct intel_engine_cs *ring = request->ring;
757 struct drm_i915_private *dev_priv = request->i915;
759 intel_logical_ring_advance(request->ringbuf);
761 request->tail = request->ringbuf->tail;
763 if (intel_ring_stopped(ring))
766 if (dev_priv->guc.execbuf_client)
767 i915_guc_submit(dev_priv->guc.execbuf_client, request);
769 execlists_context_queue(request);
772 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
774 uint32_t __iomem *virt;
775 int rem = ringbuf->size - ringbuf->tail;
777 virt = ringbuf->virtual_start + ringbuf->tail;
780 iowrite32(MI_NOOP, virt++);
783 intel_ring_update_space(ringbuf);
786 static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
788 struct intel_ringbuffer *ringbuf = req->ringbuf;
789 int remain_usable = ringbuf->effective_size - ringbuf->tail;
790 int remain_actual = ringbuf->size - ringbuf->tail;
791 int ret, total_bytes, wait_bytes = 0;
792 bool need_wrap = false;
794 if (ringbuf->reserved_in_use)
797 total_bytes = bytes + ringbuf->reserved_size;
799 if (unlikely(bytes > remain_usable)) {
801 * Not enough space for the basic request. So need to flush
802 * out the remainder and then wait for base + reserved.
804 wait_bytes = remain_actual + total_bytes;
807 if (unlikely(total_bytes > remain_usable)) {
809 * The base request will fit but the reserved space
810 * falls off the end. So only need to to wait for the
811 * reserved size after flushing out the remainder.
813 wait_bytes = remain_actual + ringbuf->reserved_size;
815 } else if (total_bytes > ringbuf->space) {
816 /* No wrapping required, just waiting. */
817 wait_bytes = total_bytes;
822 ret = logical_ring_wait_for_space(req, wait_bytes);
827 __wrap_ring_buffer(ringbuf);
834 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
836 * @req: The request to start some new work for
837 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
839 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
840 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
841 * and also preallocates a request (every workload submission is still mediated through
842 * requests, same as it did with legacy ringbuffer submission).
844 * Return: non-zero if the ringbuffer is not ready to be written to.
846 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
848 struct drm_i915_private *dev_priv;
851 WARN_ON(req == NULL);
852 dev_priv = req->ring->dev->dev_private;
854 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
855 dev_priv->mm.interruptible);
859 ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
863 req->ringbuf->space -= num_dwords * sizeof(uint32_t);
867 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
870 * The first call merely notes the reserve request and is common for
871 * all back ends. The subsequent localised _begin() call actually
872 * ensures that the reservation is available. Without the begin, if
873 * the request creator immediately submitted the request without
874 * adding any commands to it then there might not actually be
875 * sufficient room for the submission commands.
877 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
879 return intel_logical_ring_begin(request, 0);
883 * execlists_submission() - submit a batchbuffer for execution, Execlists style
886 * @ring: Engine Command Streamer to submit to.
887 * @ctx: Context to employ for this submission.
888 * @args: execbuffer call arguments.
889 * @vmas: list of vmas.
890 * @batch_obj: the batchbuffer to submit.
891 * @exec_start: batchbuffer start virtual address pointer.
892 * @dispatch_flags: translated execbuffer call flags.
894 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
895 * away the submission details of the execbuffer ioctl call.
897 * Return: non-zero if the submission fails.
899 int intel_execlists_submission(struct i915_execbuffer_params *params,
900 struct drm_i915_gem_execbuffer2 *args,
901 struct list_head *vmas)
903 struct drm_device *dev = params->dev;
904 struct intel_engine_cs *ring = params->ring;
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
912 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
913 instp_mask = I915_EXEC_CONSTANTS_MASK;
914 switch (instp_mode) {
915 case I915_EXEC_CONSTANTS_REL_GENERAL:
916 case I915_EXEC_CONSTANTS_ABSOLUTE:
917 case I915_EXEC_CONSTANTS_REL_SURFACE:
918 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
919 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
923 if (instp_mode != dev_priv->relative_constants_mode) {
924 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
925 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
929 /* The HW changed the meaning on this bit on gen6 */
930 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
934 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
938 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
939 DRM_DEBUG("sol reset is gen7 only\n");
943 ret = execlists_move_to_gpu(params->request, vmas);
947 if (ring == &dev_priv->ring[RCS] &&
948 instp_mode != dev_priv->relative_constants_mode) {
949 ret = intel_logical_ring_begin(params->request, 4);
953 intel_logical_ring_emit(ringbuf, MI_NOOP);
954 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
955 intel_logical_ring_emit_reg(ringbuf, INSTPM);
956 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
957 intel_logical_ring_advance(ringbuf);
959 dev_priv->relative_constants_mode = instp_mode;
962 exec_start = params->batch_obj_vm_offset +
963 args->batch_start_offset;
965 ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
969 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
971 i915_gem_execbuffer_move_to_active(vmas, params->request);
972 i915_gem_execbuffer_retire_commands(params);
977 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
979 struct drm_i915_gem_request *req, *tmp;
980 struct list_head retired_list;
982 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
983 if (list_empty(&ring->execlist_retired_req_list))
986 INIT_LIST_HEAD(&retired_list);
987 spin_lock_irq(&ring->execlist_lock);
988 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
989 spin_unlock_irq(&ring->execlist_lock);
991 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
992 struct intel_context *ctx = req->ctx;
993 struct drm_i915_gem_object *ctx_obj =
994 ctx->engine[ring->id].state;
996 if (ctx_obj && (ctx != ring->default_context))
997 intel_lr_context_unpin(req);
998 list_del(&req->execlist_link);
999 i915_gem_request_unreference(req);
1003 void intel_logical_ring_stop(struct intel_engine_cs *ring)
1005 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1008 if (!intel_ring_initialized(ring))
1011 ret = intel_ring_idle(ring);
1012 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
1013 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1016 /* TODO: Is this correct with Execlists enabled? */
1017 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
1018 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
1019 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
1022 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
1025 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
1027 struct intel_engine_cs *ring = req->ring;
1030 if (!ring->gpu_caches_dirty)
1033 ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1037 ring->gpu_caches_dirty = false;
1041 static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
1042 struct drm_i915_gem_object *ctx_obj,
1043 struct intel_ringbuffer *ringbuf)
1045 struct drm_device *dev = ring->dev;
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1049 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1050 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
1051 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
1055 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1059 ctx_obj->dirty = true;
1061 /* Invalidate GuC TLB. */
1062 if (i915.enable_guc_submission)
1063 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1068 i915_gem_object_ggtt_unpin(ctx_obj);
1073 static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
1076 struct intel_engine_cs *ring = rq->ring;
1077 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1078 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1080 if (rq->ctx->engine[ring->id].pin_count++ == 0) {
1081 ret = intel_lr_context_do_pin(ring, ctx_obj, ringbuf);
1083 goto reset_pin_count;
1088 rq->ctx->engine[ring->id].pin_count = 0;
1092 void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
1094 struct intel_engine_cs *ring = rq->ring;
1095 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1096 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1099 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1100 if (--rq->ctx->engine[ring->id].pin_count == 0) {
1101 intel_unpin_ringbuffer_obj(ringbuf);
1102 i915_gem_object_ggtt_unpin(ctx_obj);
1107 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1110 struct intel_engine_cs *ring = req->ring;
1111 struct intel_ringbuffer *ringbuf = req->ringbuf;
1112 struct drm_device *dev = ring->dev;
1113 struct drm_i915_private *dev_priv = dev->dev_private;
1114 struct i915_workarounds *w = &dev_priv->workarounds;
1119 ring->gpu_caches_dirty = true;
1120 ret = logical_ring_flush_all_caches(req);
1124 ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1128 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1129 for (i = 0; i < w->count; i++) {
1130 intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
1131 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1133 intel_logical_ring_emit(ringbuf, MI_NOOP);
1135 intel_logical_ring_advance(ringbuf);
1137 ring->gpu_caches_dirty = true;
1138 ret = logical_ring_flush_all_caches(req);
1145 #define wa_ctx_emit(batch, index, cmd) \
1147 int __index = (index)++; \
1148 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1151 batch[__index] = (cmd); \
1154 #define wa_ctx_emit_reg(batch, index, reg) \
1155 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1158 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1159 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1160 * but there is a slight complication as this is applied in WA batch where the
1161 * values are only initialized once so we cannot take register value at the
1162 * beginning and reuse it further; hence we save its value to memory, upload a
1163 * constant value with bit21 set and then we restore it back with the saved value.
1164 * To simplify the WA, a constant value is formed by using the default value
1165 * of this register. This shouldn't be a problem because we are only modifying
1166 * it for a short period and this batch in non-premptible. We can ofcourse
1167 * use additional instructions that read the actual value of the register
1168 * at that time and set our bit of interest but it makes the WA complicated.
1170 * This WA is also required for Gen9 so extracting as a function avoids
1173 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
1174 uint32_t *const batch,
1177 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1180 * WaDisableLSQCROPERFforOCL:skl
1181 * This WA is implemented in skl_init_clock_gating() but since
1182 * this batch updates GEN8_L3SQCREG4 with default value we need to
1183 * set this bit here to retain the WA during flush.
1185 if (IS_SKL_REVID(ring->dev, 0, SKL_REVID_E0))
1186 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1188 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1189 MI_SRM_LRM_GLOBAL_GTT));
1190 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1191 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1192 wa_ctx_emit(batch, index, 0);
1194 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1195 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1196 wa_ctx_emit(batch, index, l3sqc4_flush);
1198 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1199 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1200 PIPE_CONTROL_DC_FLUSH_ENABLE));
1201 wa_ctx_emit(batch, index, 0);
1202 wa_ctx_emit(batch, index, 0);
1203 wa_ctx_emit(batch, index, 0);
1204 wa_ctx_emit(batch, index, 0);
1206 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1207 MI_SRM_LRM_GLOBAL_GTT));
1208 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1209 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1210 wa_ctx_emit(batch, index, 0);
1215 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1217 uint32_t start_alignment)
1219 return wa_ctx->offset = ALIGN(offset, start_alignment);
1222 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1224 uint32_t size_alignment)
1226 wa_ctx->size = offset - wa_ctx->offset;
1228 WARN(wa_ctx->size % size_alignment,
1229 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1230 wa_ctx->size, size_alignment);
1235 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1237 * @ring: only applicable for RCS
1238 * @wa_ctx: structure representing wa_ctx
1239 * offset: specifies start of the batch, should be cache-aligned. This is updated
1240 * with the offset value received as input.
1241 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1242 * @batch: page in which WA are loaded
1243 * @offset: This field specifies the start of the batch, it should be
1244 * cache-aligned otherwise it is adjusted accordingly.
1245 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1246 * initialized at the beginning and shared across all contexts but this field
1247 * helps us to have multiple batches at different offsets and select them based
1248 * on a criteria. At the moment this batch always start at the beginning of the page
1249 * and at this point we don't have multiple wa_ctx batch buffers.
1251 * The number of WA applied are not known at the beginning; we use this field
1252 * to return the no of DWORDS written.
1254 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1255 * so it adds NOOPs as padding to make it cacheline aligned.
1256 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1257 * makes a complete batch buffer.
1259 * Return: non-zero if we exceed the PAGE_SIZE limit.
1262 static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
1263 struct i915_wa_ctx_bb *wa_ctx,
1264 uint32_t *const batch,
1267 uint32_t scratch_addr;
1268 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1270 /* WaDisableCtxRestoreArbitration:bdw,chv */
1271 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1273 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1274 if (IS_BROADWELL(ring->dev)) {
1275 int rc = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1281 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1282 /* Actual scratch location is at 128 bytes offset */
1283 scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;
1285 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1286 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1287 PIPE_CONTROL_GLOBAL_GTT_IVB |
1288 PIPE_CONTROL_CS_STALL |
1289 PIPE_CONTROL_QW_WRITE));
1290 wa_ctx_emit(batch, index, scratch_addr);
1291 wa_ctx_emit(batch, index, 0);
1292 wa_ctx_emit(batch, index, 0);
1293 wa_ctx_emit(batch, index, 0);
1295 /* Pad to end of cacheline */
1296 while (index % CACHELINE_DWORDS)
1297 wa_ctx_emit(batch, index, MI_NOOP);
1300 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1301 * execution depends on the length specified in terms of cache lines
1302 * in the register CTX_RCS_INDIRECT_CTX
1305 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1309 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1311 * @ring: only applicable for RCS
1312 * @wa_ctx: structure representing wa_ctx
1313 * offset: specifies start of the batch, should be cache-aligned.
1314 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1315 * @batch: page in which WA are loaded
1316 * @offset: This field specifies the start of this batch.
1317 * This batch is started immediately after indirect_ctx batch. Since we ensure
1318 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1320 * The number of DWORDS written are returned using this field.
1322 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1323 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1325 static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
1326 struct i915_wa_ctx_bb *wa_ctx,
1327 uint32_t *const batch,
1330 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1332 /* WaDisableCtxRestoreArbitration:bdw,chv */
1333 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1335 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1337 return wa_ctx_end(wa_ctx, *offset = index, 1);
1340 static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
1341 struct i915_wa_ctx_bb *wa_ctx,
1342 uint32_t *const batch,
1346 struct drm_device *dev = ring->dev;
1347 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1349 /* WaDisableCtxRestoreArbitration:skl,bxt */
1350 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1351 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1352 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1354 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1355 ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1360 /* Pad to end of cacheline */
1361 while (index % CACHELINE_DWORDS)
1362 wa_ctx_emit(batch, index, MI_NOOP);
1364 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1367 static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
1368 struct i915_wa_ctx_bb *wa_ctx,
1369 uint32_t *const batch,
1372 struct drm_device *dev = ring->dev;
1373 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1375 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1376 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
1377 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1378 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1379 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1380 wa_ctx_emit(batch, index,
1381 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1382 wa_ctx_emit(batch, index, MI_NOOP);
1385 /* WaDisableCtxRestoreArbitration:skl,bxt */
1386 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1387 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1388 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1390 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1392 return wa_ctx_end(wa_ctx, *offset = index, 1);
1395 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
1399 ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
1400 if (!ring->wa_ctx.obj) {
1401 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1405 ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
1407 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1409 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1416 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
1418 if (ring->wa_ctx.obj) {
1419 i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
1420 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1421 ring->wa_ctx.obj = NULL;
1425 static int intel_init_workaround_bb(struct intel_engine_cs *ring)
1431 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
1433 WARN_ON(ring->id != RCS);
1435 /* update this when WA for higher Gen are added */
1436 if (INTEL_INFO(ring->dev)->gen > 9) {
1437 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1438 INTEL_INFO(ring->dev)->gen);
1442 /* some WA perform writes to scratch page, ensure it is valid */
1443 if (ring->scratch.obj == NULL) {
1444 DRM_ERROR("scratch page not allocated for %s\n", ring->name);
1448 ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
1450 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1454 page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1455 batch = kmap_atomic(page);
1458 if (INTEL_INFO(ring->dev)->gen == 8) {
1459 ret = gen8_init_indirectctx_bb(ring,
1460 &wa_ctx->indirect_ctx,
1466 ret = gen8_init_perctx_bb(ring,
1472 } else if (INTEL_INFO(ring->dev)->gen == 9) {
1473 ret = gen9_init_indirectctx_bb(ring,
1474 &wa_ctx->indirect_ctx,
1480 ret = gen9_init_perctx_bb(ring,
1489 kunmap_atomic(batch);
1491 lrc_destroy_wa_ctx_obj(ring);
1496 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1498 struct drm_device *dev = ring->dev;
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 u8 next_context_status_buffer_hw;
1502 lrc_setup_hardware_status_page(ring,
1503 ring->default_context->engine[ring->id].state);
1505 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1506 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1508 I915_WRITE(RING_MODE_GEN7(ring),
1509 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1510 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1511 POSTING_READ(RING_MODE_GEN7(ring));
1514 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1515 * zero, we need to read the write pointer from hardware and use its
1516 * value because "this register is power context save restored".
1517 * Effectively, these states have been observed:
1519 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1520 * BDW | CSB regs not reset | CSB regs reset |
1521 * CHT | CSB regs not reset | CSB regs not reset |
1525 next_context_status_buffer_hw =
1526 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(ring)));
1529 * When the CSB registers are reset (also after power-up / gpu reset),
1530 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1531 * this special case, so the first element read is CSB[0].
1533 if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
1534 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);
1536 ring->next_context_status_buffer = next_context_status_buffer_hw;
1537 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1539 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1544 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1546 struct drm_device *dev = ring->dev;
1547 struct drm_i915_private *dev_priv = dev->dev_private;
1550 ret = gen8_init_common_ring(ring);
1554 /* We need to disable the AsyncFlip performance optimisations in order
1555 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1556 * programmed to '1' on all products.
1558 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1560 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1562 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1564 return init_workarounds_ring(ring);
1567 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1571 ret = gen8_init_common_ring(ring);
1575 return init_workarounds_ring(ring);
1578 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1580 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1581 struct intel_engine_cs *ring = req->ring;
1582 struct intel_ringbuffer *ringbuf = req->ringbuf;
1583 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1586 ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
1590 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1591 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1592 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1594 intel_logical_ring_emit_reg(ringbuf, GEN8_RING_PDP_UDW(ring, i));
1595 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1596 intel_logical_ring_emit_reg(ringbuf, GEN8_RING_PDP_LDW(ring, i));
1597 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1600 intel_logical_ring_emit(ringbuf, MI_NOOP);
1601 intel_logical_ring_advance(ringbuf);
1606 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1607 u64 offset, unsigned dispatch_flags)
1609 struct intel_ringbuffer *ringbuf = req->ringbuf;
1610 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1613 /* Don't rely in hw updating PDPs, specially in lite-restore.
1614 * Ideally, we should set Force PD Restore in ctx descriptor,
1615 * but we can't. Force Restore would be a second option, but
1616 * it is unsafe in case of lite-restore (because the ctx is
1617 * not idle). PML4 is allocated during ppgtt init so this is
1618 * not needed in 48-bit.*/
1619 if (req->ctx->ppgtt &&
1620 (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
1621 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1622 !intel_vgpu_active(req->i915->dev)) {
1623 ret = intel_logical_ring_emit_pdps(req);
1628 req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
1631 ret = intel_logical_ring_begin(req, 4);
1635 /* FIXME(BDW): Address space and security selectors. */
1636 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1638 (dispatch_flags & I915_DISPATCH_RS ?
1639 MI_BATCH_RESOURCE_STREAMER : 0));
1640 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1641 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1642 intel_logical_ring_emit(ringbuf, MI_NOOP);
1643 intel_logical_ring_advance(ringbuf);
1648 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1650 struct drm_device *dev = ring->dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 unsigned long flags;
1654 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1657 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1658 if (ring->irq_refcount++ == 0) {
1659 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1660 POSTING_READ(RING_IMR(ring->mmio_base));
1662 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1667 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1669 struct drm_device *dev = ring->dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 unsigned long flags;
1673 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1674 if (--ring->irq_refcount == 0) {
1675 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1676 POSTING_READ(RING_IMR(ring->mmio_base));
1678 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1681 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1682 u32 invalidate_domains,
1685 struct intel_ringbuffer *ringbuf = request->ringbuf;
1686 struct intel_engine_cs *ring = ringbuf->ring;
1687 struct drm_device *dev = ring->dev;
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1692 ret = intel_logical_ring_begin(request, 4);
1696 cmd = MI_FLUSH_DW + 1;
1698 /* We always require a command barrier so that subsequent
1699 * commands, such as breadcrumb interrupts, are strictly ordered
1700 * wrt the contents of the write cache being flushed to memory
1701 * (and thus being coherent from the CPU).
1703 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1705 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1706 cmd |= MI_INVALIDATE_TLB;
1707 if (ring == &dev_priv->ring[VCS])
1708 cmd |= MI_INVALIDATE_BSD;
1711 intel_logical_ring_emit(ringbuf, cmd);
1712 intel_logical_ring_emit(ringbuf,
1713 I915_GEM_HWS_SCRATCH_ADDR |
1714 MI_FLUSH_DW_USE_GTT);
1715 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1716 intel_logical_ring_emit(ringbuf, 0); /* value */
1717 intel_logical_ring_advance(ringbuf);
1722 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1723 u32 invalidate_domains,
1726 struct intel_ringbuffer *ringbuf = request->ringbuf;
1727 struct intel_engine_cs *ring = ringbuf->ring;
1728 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1729 bool vf_flush_wa = false;
1733 flags |= PIPE_CONTROL_CS_STALL;
1735 if (flush_domains) {
1736 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1737 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1738 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1741 if (invalidate_domains) {
1742 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1743 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1744 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1745 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1746 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1747 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1748 flags |= PIPE_CONTROL_QW_WRITE;
1749 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1752 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1755 if (IS_GEN9(ring->dev))
1759 ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1764 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1765 intel_logical_ring_emit(ringbuf, 0);
1766 intel_logical_ring_emit(ringbuf, 0);
1767 intel_logical_ring_emit(ringbuf, 0);
1768 intel_logical_ring_emit(ringbuf, 0);
1769 intel_logical_ring_emit(ringbuf, 0);
1772 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1773 intel_logical_ring_emit(ringbuf, flags);
1774 intel_logical_ring_emit(ringbuf, scratch_addr);
1775 intel_logical_ring_emit(ringbuf, 0);
1776 intel_logical_ring_emit(ringbuf, 0);
1777 intel_logical_ring_emit(ringbuf, 0);
1778 intel_logical_ring_advance(ringbuf);
1783 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1785 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1788 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1790 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1793 static u32 bxt_a_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1797 * On BXT A steppings there is a HW coherency issue whereby the
1798 * MI_STORE_DATA_IMM storing the completed request's seqno
1799 * occasionally doesn't invalidate the CPU cache. Work around this by
1800 * clflushing the corresponding cacheline whenever the caller wants
1801 * the coherency to be guaranteed. Note that this cacheline is known
1802 * to be clean at this point, since we only write it in
1803 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1804 * this clflush in practice becomes an invalidate operation.
1807 if (!lazy_coherency)
1808 intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
1810 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1813 static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1815 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1817 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1818 intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
1821 static int gen8_emit_request(struct drm_i915_gem_request *request)
1823 struct intel_ringbuffer *ringbuf = request->ringbuf;
1824 struct intel_engine_cs *ring = ringbuf->ring;
1829 * Reserve space for 2 NOOPs at the end of each request to be
1830 * used as a workaround for not being allowed to do lite
1831 * restore with HEAD==TAIL (WaIdleLiteRestore).
1833 ret = intel_logical_ring_begin(request, 8);
1837 cmd = MI_STORE_DWORD_IMM_GEN4;
1838 cmd |= MI_GLOBAL_GTT;
1840 intel_logical_ring_emit(ringbuf, cmd);
1841 intel_logical_ring_emit(ringbuf,
1842 (ring->status_page.gfx_addr +
1843 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1844 intel_logical_ring_emit(ringbuf, 0);
1845 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1846 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1847 intel_logical_ring_emit(ringbuf, MI_NOOP);
1848 intel_logical_ring_advance_and_submit(request);
1851 * Here we add two extra NOOPs as padding to avoid
1852 * lite restore of a context with HEAD==TAIL.
1854 intel_logical_ring_emit(ringbuf, MI_NOOP);
1855 intel_logical_ring_emit(ringbuf, MI_NOOP);
1856 intel_logical_ring_advance(ringbuf);
1861 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1863 struct render_state so;
1866 ret = i915_gem_render_state_prepare(req->ring, &so);
1870 if (so.rodata == NULL)
1873 ret = req->ring->emit_bb_start(req, so.ggtt_offset,
1874 I915_DISPATCH_SECURE);
1878 ret = req->ring->emit_bb_start(req,
1879 (so.ggtt_offset + so.aux_batch_offset),
1880 I915_DISPATCH_SECURE);
1884 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1887 i915_gem_render_state_fini(&so);
1891 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1895 ret = intel_logical_ring_workarounds_emit(req);
1899 ret = intel_rcs_context_init_mocs(req);
1901 * Failing to program the MOCS is non-fatal.The system will not
1902 * run at peak performance. So generate an error and carry on.
1905 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1907 return intel_lr_context_render_state_init(req);
1911 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1913 * @ring: Engine Command Streamer.
1916 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1918 struct drm_i915_private *dev_priv;
1920 if (!intel_ring_initialized(ring))
1923 dev_priv = ring->dev->dev_private;
1926 intel_logical_ring_stop(ring);
1927 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1931 ring->cleanup(ring);
1933 i915_cmd_parser_fini_ring(ring);
1934 i915_gem_batch_pool_fini(&ring->batch_pool);
1936 if (ring->status_page.obj) {
1937 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1938 ring->status_page.obj = NULL;
1941 lrc_destroy_wa_ctx_obj(ring);
1945 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1949 /* Intentionally left blank. */
1950 ring->buffer = NULL;
1953 INIT_LIST_HEAD(&ring->active_list);
1954 INIT_LIST_HEAD(&ring->request_list);
1955 i915_gem_batch_pool_init(dev, &ring->batch_pool);
1956 init_waitqueue_head(&ring->irq_queue);
1958 INIT_LIST_HEAD(&ring->buffers);
1959 INIT_LIST_HEAD(&ring->execlist_queue);
1960 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1961 spin_lock_init(&ring->execlist_lock);
1963 ret = i915_cmd_parser_init_ring(ring);
1967 ret = intel_lr_context_deferred_alloc(ring->default_context, ring);
1971 /* As this is the default context, always pin it */
1972 ret = intel_lr_context_do_pin(
1974 ring->default_context->engine[ring->id].state,
1975 ring->default_context->engine[ring->id].ringbuf);
1978 "Failed to pin and map ringbuffer %s: %d\n",
1986 intel_logical_ring_cleanup(ring);
1990 static int logical_render_ring_init(struct drm_device *dev)
1992 struct drm_i915_private *dev_priv = dev->dev_private;
1993 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1996 ring->name = "render ring";
1998 ring->mmio_base = RENDER_RING_BASE;
1999 ring->irq_enable_mask =
2000 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
2001 ring->irq_keep_mask =
2002 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
2003 if (HAS_L3_DPF(dev))
2004 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2006 if (INTEL_INFO(dev)->gen >= 9)
2007 ring->init_hw = gen9_init_render_ring;
2009 ring->init_hw = gen8_init_render_ring;
2010 ring->init_context = gen8_init_rcs_context;
2011 ring->cleanup = intel_fini_pipe_control;
2012 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2013 ring->get_seqno = bxt_a_get_seqno;
2014 ring->set_seqno = bxt_a_set_seqno;
2016 ring->get_seqno = gen8_get_seqno;
2017 ring->set_seqno = gen8_set_seqno;
2019 ring->emit_request = gen8_emit_request;
2020 ring->emit_flush = gen8_emit_flush_render;
2021 ring->irq_get = gen8_logical_ring_get_irq;
2022 ring->irq_put = gen8_logical_ring_put_irq;
2023 ring->emit_bb_start = gen8_emit_bb_start;
2027 ret = intel_init_pipe_control(ring);
2031 ret = intel_init_workaround_bb(ring);
2034 * We continue even if we fail to initialize WA batch
2035 * because we only expect rare glitches but nothing
2036 * critical to prevent us from using GPU
2038 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2042 ret = logical_ring_init(dev, ring);
2044 lrc_destroy_wa_ctx_obj(ring);
2050 static int logical_bsd_ring_init(struct drm_device *dev)
2052 struct drm_i915_private *dev_priv = dev->dev_private;
2053 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2055 ring->name = "bsd ring";
2057 ring->mmio_base = GEN6_BSD_RING_BASE;
2058 ring->irq_enable_mask =
2059 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2060 ring->irq_keep_mask =
2061 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2063 ring->init_hw = gen8_init_common_ring;
2064 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2065 ring->get_seqno = bxt_a_get_seqno;
2066 ring->set_seqno = bxt_a_set_seqno;
2068 ring->get_seqno = gen8_get_seqno;
2069 ring->set_seqno = gen8_set_seqno;
2071 ring->emit_request = gen8_emit_request;
2072 ring->emit_flush = gen8_emit_flush;
2073 ring->irq_get = gen8_logical_ring_get_irq;
2074 ring->irq_put = gen8_logical_ring_put_irq;
2075 ring->emit_bb_start = gen8_emit_bb_start;
2077 return logical_ring_init(dev, ring);
2080 static int logical_bsd2_ring_init(struct drm_device *dev)
2082 struct drm_i915_private *dev_priv = dev->dev_private;
2083 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2085 ring->name = "bds2 ring";
2087 ring->mmio_base = GEN8_BSD2_RING_BASE;
2088 ring->irq_enable_mask =
2089 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2090 ring->irq_keep_mask =
2091 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2093 ring->init_hw = gen8_init_common_ring;
2094 ring->get_seqno = gen8_get_seqno;
2095 ring->set_seqno = gen8_set_seqno;
2096 ring->emit_request = gen8_emit_request;
2097 ring->emit_flush = gen8_emit_flush;
2098 ring->irq_get = gen8_logical_ring_get_irq;
2099 ring->irq_put = gen8_logical_ring_put_irq;
2100 ring->emit_bb_start = gen8_emit_bb_start;
2102 return logical_ring_init(dev, ring);
2105 static int logical_blt_ring_init(struct drm_device *dev)
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2110 ring->name = "blitter ring";
2112 ring->mmio_base = BLT_RING_BASE;
2113 ring->irq_enable_mask =
2114 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2115 ring->irq_keep_mask =
2116 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2118 ring->init_hw = gen8_init_common_ring;
2119 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2120 ring->get_seqno = bxt_a_get_seqno;
2121 ring->set_seqno = bxt_a_set_seqno;
2123 ring->get_seqno = gen8_get_seqno;
2124 ring->set_seqno = gen8_set_seqno;
2126 ring->emit_request = gen8_emit_request;
2127 ring->emit_flush = gen8_emit_flush;
2128 ring->irq_get = gen8_logical_ring_get_irq;
2129 ring->irq_put = gen8_logical_ring_put_irq;
2130 ring->emit_bb_start = gen8_emit_bb_start;
2132 return logical_ring_init(dev, ring);
2135 static int logical_vebox_ring_init(struct drm_device *dev)
2137 struct drm_i915_private *dev_priv = dev->dev_private;
2138 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2140 ring->name = "video enhancement ring";
2142 ring->mmio_base = VEBOX_RING_BASE;
2143 ring->irq_enable_mask =
2144 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2145 ring->irq_keep_mask =
2146 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2148 ring->init_hw = gen8_init_common_ring;
2149 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2150 ring->get_seqno = bxt_a_get_seqno;
2151 ring->set_seqno = bxt_a_set_seqno;
2153 ring->get_seqno = gen8_get_seqno;
2154 ring->set_seqno = gen8_set_seqno;
2156 ring->emit_request = gen8_emit_request;
2157 ring->emit_flush = gen8_emit_flush;
2158 ring->irq_get = gen8_logical_ring_get_irq;
2159 ring->irq_put = gen8_logical_ring_put_irq;
2160 ring->emit_bb_start = gen8_emit_bb_start;
2162 return logical_ring_init(dev, ring);
2166 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2169 * This function inits the engines for an Execlists submission style (the equivalent in the
2170 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2171 * those engines that are present in the hardware.
2173 * Return: non-zero if the initialization failed.
2175 int intel_logical_rings_init(struct drm_device *dev)
2177 struct drm_i915_private *dev_priv = dev->dev_private;
2180 ret = logical_render_ring_init(dev);
2185 ret = logical_bsd_ring_init(dev);
2187 goto cleanup_render_ring;
2191 ret = logical_blt_ring_init(dev);
2193 goto cleanup_bsd_ring;
2196 if (HAS_VEBOX(dev)) {
2197 ret = logical_vebox_ring_init(dev);
2199 goto cleanup_blt_ring;
2202 if (HAS_BSD2(dev)) {
2203 ret = logical_bsd2_ring_init(dev);
2205 goto cleanup_vebox_ring;
2211 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
2213 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
2215 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
2216 cleanup_render_ring:
2217 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
2223 make_rpcs(struct drm_device *dev)
2228 * No explicit RPCS request is needed to ensure full
2229 * slice/subslice/EU enablement prior to Gen9.
2231 if (INTEL_INFO(dev)->gen < 9)
2235 * Starting in Gen9, render power gating can leave
2236 * slice/subslice/EU in a partially enabled state. We
2237 * must make an explicit request through RPCS for full
2240 if (INTEL_INFO(dev)->has_slice_pg) {
2241 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2242 rpcs |= INTEL_INFO(dev)->slice_total <<
2243 GEN8_RPCS_S_CNT_SHIFT;
2244 rpcs |= GEN8_RPCS_ENABLE;
2247 if (INTEL_INFO(dev)->has_subslice_pg) {
2248 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2249 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2250 GEN8_RPCS_SS_CNT_SHIFT;
2251 rpcs |= GEN8_RPCS_ENABLE;
2254 if (INTEL_INFO(dev)->has_eu_pg) {
2255 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2256 GEN8_RPCS_EU_MIN_SHIFT;
2257 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2258 GEN8_RPCS_EU_MAX_SHIFT;
2259 rpcs |= GEN8_RPCS_ENABLE;
2266 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
2267 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
2269 struct drm_device *dev = ring->dev;
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2273 uint32_t *reg_state;
2277 ppgtt = dev_priv->mm.aliasing_ppgtt;
2279 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2281 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2285 ret = i915_gem_object_get_pages(ctx_obj);
2287 DRM_DEBUG_DRIVER("Could not get object pages\n");
2291 i915_gem_object_pin_pages(ctx_obj);
2293 /* The second page of the context object contains some fields which must
2294 * be set up prior to the first execution. */
2295 page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2296 reg_state = kmap_atomic(page);
2298 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2299 * commands followed by (reg, value) pairs. The values we are setting here are
2300 * only for the first context restore: on a subsequent save, the GPU will
2301 * recreate this batchbuffer with new values (including all the missing
2302 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2303 reg_state[CTX_LRI_HEADER_0] =
2304 MI_LOAD_REGISTER_IMM(ring->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
2305 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(ring),
2306 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2307 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2308 CTX_CTRL_RS_CTX_ENABLE));
2309 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(ring->mmio_base), 0);
2310 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(ring->mmio_base), 0);
2311 /* Ring buffer start address is not known until the buffer is pinned.
2312 * It is written to the context image in execlists_update_context()
2314 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, RING_START(ring->mmio_base), 0);
2315 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, RING_CTL(ring->mmio_base),
2316 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2317 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, RING_BBADDR_UDW(ring->mmio_base), 0);
2318 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, RING_BBADDR(ring->mmio_base), 0);
2319 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, RING_BBSTATE(ring->mmio_base),
2321 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(ring->mmio_base), 0);
2322 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(ring->mmio_base), 0);
2323 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, RING_SBBSTATE(ring->mmio_base), 0);
2324 if (ring->id == RCS) {
2325 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(ring->mmio_base), 0);
2326 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(ring->mmio_base), 0);
2327 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, RING_INDIRECT_CTX_OFFSET(ring->mmio_base), 0);
2328 if (ring->wa_ctx.obj) {
2329 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
2330 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2332 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2333 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2334 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2336 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2337 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
2339 reg_state[CTX_BB_PER_CTX_PTR+1] =
2340 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2344 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2345 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(ring->mmio_base), 0);
2346 /* PDP values well be assigned later if needed */
2347 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(ring, 3), 0);
2348 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(ring, 3), 0);
2349 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(ring, 2), 0);
2350 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(ring, 2), 0);
2351 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(ring, 1), 0);
2352 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(ring, 1), 0);
2353 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(ring, 0), 0);
2354 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(ring, 0), 0);
2356 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2357 /* 64b PPGTT (48bit canonical)
2358 * PDP0_DESCRIPTOR contains the base address to PML4 and
2359 * other PDP Descriptors are ignored.
2361 ASSIGN_CTX_PML4(ppgtt, reg_state);
2364 * PDP*_DESCRIPTOR contains the base address of space supported.
2365 * With dynamic page allocation, PDPs may not be allocated at
2366 * this point. Point the unallocated PDPs to the scratch page
2368 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
2369 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
2370 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
2371 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
2374 if (ring->id == RCS) {
2375 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2376 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2380 kunmap_atomic(reg_state);
2381 i915_gem_object_unpin_pages(ctx_obj);
2387 * intel_lr_context_free() - free the LRC specific bits of a context
2388 * @ctx: the LR context to free.
2390 * The real context freeing is done in i915_gem_context_free: this only
2391 * takes care of the bits that are LRC related: the per-engine backing
2392 * objects and the logical ringbuffer.
2394 void intel_lr_context_free(struct intel_context *ctx)
2398 for (i = 0; i < I915_NUM_RINGS; i++) {
2399 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2402 struct intel_ringbuffer *ringbuf =
2403 ctx->engine[i].ringbuf;
2404 struct intel_engine_cs *ring = ringbuf->ring;
2406 if (ctx == ring->default_context) {
2407 intel_unpin_ringbuffer_obj(ringbuf);
2408 i915_gem_object_ggtt_unpin(ctx_obj);
2410 WARN_ON(ctx->engine[ring->id].pin_count);
2411 intel_ringbuffer_free(ringbuf);
2412 drm_gem_object_unreference(&ctx_obj->base);
2418 * intel_lr_context_size() - return the size of the context for an engine
2419 * @ring: which engine to find the context size for
2421 * Each engine may require a different amount of space for a context image,
2422 * so when allocating (or copying) an image, this function can be used to
2423 * find the right size for the specific engine.
2425 * Return: size (in bytes) of an engine-specific context image
2427 * Note: this size includes the HWSP, which is part of the context image
2428 * in LRC mode, but does not include the "shared data page" used with
2429 * GuC submission. The caller should account for this if using the GuC.
2431 uint32_t intel_lr_context_size(struct intel_engine_cs *ring)
2435 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
2439 if (INTEL_INFO(ring->dev)->gen >= 9)
2440 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2442 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2448 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2455 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
2456 struct drm_i915_gem_object *default_ctx_obj)
2458 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2461 /* The HWSP is part of the default context object in LRC mode. */
2462 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
2463 + LRC_PPHWSP_PN * PAGE_SIZE;
2464 page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
2465 ring->status_page.page_addr = kmap(page);
2466 ring->status_page.obj = default_ctx_obj;
2468 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
2469 (u32)ring->status_page.gfx_addr);
2470 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
2474 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2475 * @ctx: LR context to create.
2476 * @ring: engine to be used with the context.
2478 * This function can be called more than once, with different engines, if we plan
2479 * to use the context with them. The context backing objects and the ringbuffers
2480 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2481 * the creation is a deferred call: it's better to make sure first that we need to use
2482 * a given ring with the context.
2484 * Return: non-zero on error.
2487 int intel_lr_context_deferred_alloc(struct intel_context *ctx,
2488 struct intel_engine_cs *ring)
2490 struct drm_device *dev = ring->dev;
2491 struct drm_i915_gem_object *ctx_obj;
2492 uint32_t context_size;
2493 struct intel_ringbuffer *ringbuf;
2496 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2497 WARN_ON(ctx->engine[ring->id].state);
2499 context_size = round_up(intel_lr_context_size(ring), 4096);
2501 /* One extra page as the sharing data between driver and GuC */
2502 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2504 ctx_obj = i915_gem_alloc_object(dev, context_size);
2506 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2510 ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE);
2511 if (IS_ERR(ringbuf)) {
2512 ret = PTR_ERR(ringbuf);
2513 goto error_deref_obj;
2516 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
2518 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2522 ctx->engine[ring->id].ringbuf = ringbuf;
2523 ctx->engine[ring->id].state = ctx_obj;
2525 if (ctx != ring->default_context && ring->init_context) {
2526 struct drm_i915_gem_request *req;
2528 ret = i915_gem_request_alloc(ring,
2531 DRM_ERROR("ring create req: %d\n",
2536 ret = ring->init_context(req);
2538 DRM_ERROR("ring init context: %d\n",
2540 i915_gem_request_cancel(req);
2543 i915_add_request_no_flush(req);
2548 intel_ringbuffer_free(ringbuf);
2550 drm_gem_object_unreference(&ctx_obj->base);
2551 ctx->engine[ring->id].ringbuf = NULL;
2552 ctx->engine[ring->id].state = NULL;
2556 void intel_lr_context_reset(struct drm_device *dev,
2557 struct intel_context *ctx)
2559 struct drm_i915_private *dev_priv = dev->dev_private;
2560 struct intel_engine_cs *ring;
2563 for_each_ring(ring, dev_priv, i) {
2564 struct drm_i915_gem_object *ctx_obj =
2565 ctx->engine[ring->id].state;
2566 struct intel_ringbuffer *ringbuf =
2567 ctx->engine[ring->id].ringbuf;
2568 uint32_t *reg_state;
2574 if (i915_gem_object_get_pages(ctx_obj)) {
2575 WARN(1, "Failed get_pages for context obj\n");
2578 page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2579 reg_state = kmap_atomic(page);
2581 reg_state[CTX_RING_HEAD+1] = 0;
2582 reg_state[CTX_RING_TAIL+1] = 0;
2584 kunmap_atomic(reg_state);