2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
211 ADVANCED_CONTEXT = 0,
216 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
217 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
218 LEGACY_64B_CONTEXT :\
222 FAULT_AND_HALT, /* Debug only */
224 FAULT_AND_CONTINUE /* Unsupported */
226 #define GEN8_CTX_ID_SHIFT 32
227 #define GEN8_CTX_ID_WIDTH 21
228 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
229 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
231 static int execlists_context_deferred_alloc(struct intel_context *ctx,
232 struct intel_engine_cs *engine);
233 static int intel_lr_context_pin(struct intel_context *ctx,
234 struct intel_engine_cs *engine);
237 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
239 * @enable_execlists: value of i915.enable_execlists module parameter.
241 * Only certain platforms support Execlists (the prerequisites being
242 * support for Logical Ring Contexts and Aliasing PPGTT or better).
244 * Return: 1 if Execlists is supported and has to be enabled.
246 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
248 WARN_ON(i915.enable_ppgtt == -1);
250 /* On platforms with execlist available, vGPU will only
251 * support execlist mode, no ring buffer mode.
253 if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
256 if (INTEL_INFO(dev)->gen >= 9)
259 if (enable_execlists == 0)
262 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
263 i915.use_mmio_flip >= 0)
270 logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
272 struct drm_device *dev = engine->dev;
274 if (IS_GEN8(dev) || IS_GEN9(dev))
275 engine->idle_lite_restore_wa = ~0;
277 engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
278 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
279 (engine->id == VCS || engine->id == VCS2);
281 engine->ctx_desc_template = GEN8_CTX_VALID;
282 engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
283 GEN8_CTX_ADDRESSING_MODE_SHIFT;
285 engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
286 engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
288 /* TODO: WaDisableLiteRestore when we start using semaphore
289 * signalling between Command Streamers */
290 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
292 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
293 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
294 if (engine->disable_lite_restore_wa)
295 engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
299 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
300 * descriptor for a pinned context
302 * @ctx: Context to work on
303 * @ring: Engine the descriptor will be used with
305 * The context descriptor encodes various attributes of a context,
306 * including its GTT address and some flags. Because it's fairly
307 * expensive to calculate, we'll just do it once and cache the result,
308 * which remains valid until the context is unpinned.
310 * This is what a descriptor looks like, from LSB to MSB:
311 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
312 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
313 * bits 32-52: ctx ID, a globally unique tag
314 * bits 53-54: mbz, reserved for use by hardware
315 * bits 55-63: group ID, currently unused and set to 0
318 intel_lr_context_descriptor_update(struct intel_context *ctx,
319 struct intel_engine_cs *engine)
323 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
325 desc = engine->ctx_desc_template; /* bits 0-11 */
326 desc |= ctx->engine[engine->id].lrc_vma->node.start + /* bits 12-31 */
327 LRC_PPHWSP_PN * PAGE_SIZE;
328 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
330 ctx->engine[engine->id].lrc_desc = desc;
333 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
334 struct intel_engine_cs *engine)
336 return ctx->engine[engine->id].lrc_desc;
339 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
340 struct drm_i915_gem_request *rq1)
343 struct intel_engine_cs *engine = rq0->engine;
344 struct drm_device *dev = engine->dev;
345 struct drm_i915_private *dev_priv = dev->dev_private;
349 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
350 rq1->elsp_submitted++;
355 desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
356 rq0->elsp_submitted++;
358 /* You must always write both descriptors in the order below. */
359 I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
360 I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
362 I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
363 /* The context is automatically loaded after the following */
364 I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
366 /* ELSP is a wo register, use another nearby reg for posting */
367 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
371 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
373 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
374 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
375 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
376 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
379 static void execlists_update_context(struct drm_i915_gem_request *rq)
381 struct intel_engine_cs *engine = rq->engine;
382 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
383 uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
385 reg_state[CTX_RING_TAIL+1] = rq->tail;
387 /* True 32b PPGTT with dynamic page allocation: update PDP
388 * registers and point the unallocated PDPs to scratch page.
389 * PML4 is allocated during ppgtt init, so this is not needed
392 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
393 execlists_update_context_pdps(ppgtt, reg_state);
396 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
397 struct drm_i915_gem_request *rq1)
399 struct drm_i915_private *dev_priv = rq0->i915;
400 unsigned int fw_domains = rq0->engine->fw_domains;
402 execlists_update_context(rq0);
405 execlists_update_context(rq1);
407 spin_lock_irq(&dev_priv->uncore.lock);
408 intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
410 execlists_elsp_write(rq0, rq1);
412 intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
413 spin_unlock_irq(&dev_priv->uncore.lock);
416 static void execlists_context_unqueue(struct intel_engine_cs *engine)
418 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
419 struct drm_i915_gem_request *cursor, *tmp;
421 assert_spin_locked(&engine->execlist_lock);
424 * If irqs are not active generate a warning as batches that finish
425 * without the irqs may get lost and a GPU Hang may occur.
427 WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
429 /* Try to read in pairs */
430 list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
434 } else if (req0->ctx == cursor->ctx) {
435 /* Same ctx: ignore first request, as second request
436 * will update tail past first request's workload */
437 cursor->elsp_submitted = req0->elsp_submitted;
438 list_move_tail(&req0->execlist_link,
439 &engine->execlist_retired_req_list);
443 WARN_ON(req1->elsp_submitted);
451 if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
453 * WaIdleLiteRestore: make sure we never cause a lite restore
456 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
457 * resubmit the request. See gen8_emit_request() for where we
458 * prepare the padding after the end of the request.
460 struct intel_ringbuffer *ringbuf;
462 ringbuf = req0->ctx->engine[engine->id].ringbuf;
464 req0->tail &= ringbuf->size - 1;
467 execlists_submit_requests(req0, req1);
471 execlists_check_remove_request(struct intel_engine_cs *engine, u32 request_id)
473 struct drm_i915_gem_request *head_req;
475 assert_spin_locked(&engine->execlist_lock);
477 head_req = list_first_entry_or_null(&engine->execlist_queue,
478 struct drm_i915_gem_request,
484 if (unlikely(head_req->ctx_hw_id != request_id))
487 WARN(head_req->elsp_submitted == 0, "Never submitted head request\n");
489 if (--head_req->elsp_submitted > 0)
492 list_move_tail(&head_req->execlist_link,
493 &engine->execlist_retired_req_list);
499 get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
502 struct drm_i915_private *dev_priv = engine->dev->dev_private;
505 read_pointer %= GEN8_CSB_ENTRIES;
507 status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer));
509 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
512 *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine,
519 * intel_lrc_irq_handler() - handle Context Switch interrupts
520 * @engine: Engine Command Streamer to handle.
522 * Check the unread Context Status Buffers and manage the submission of new
523 * contexts to the ELSP accordingly.
525 static void intel_lrc_irq_handler(unsigned long data)
527 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
528 struct drm_i915_private *dev_priv = engine->dev->dev_private;
530 unsigned int read_pointer, write_pointer;
531 u32 csb[GEN8_CSB_ENTRIES][2];
532 unsigned int csb_read = 0, i;
533 unsigned int submit_contexts = 0;
535 intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
537 status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine));
539 read_pointer = engine->next_context_status_buffer;
540 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
541 if (read_pointer > write_pointer)
542 write_pointer += GEN8_CSB_ENTRIES;
544 while (read_pointer < write_pointer) {
545 if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES))
547 csb[csb_read][0] = get_context_status(engine, ++read_pointer,
552 engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
554 /* Update the read pointer to the old write pointer. Manual ringbuffer
555 * management ftw </sarcasm> */
556 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine),
557 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
558 engine->next_context_status_buffer << 8));
560 intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
562 spin_lock(&engine->execlist_lock);
564 for (i = 0; i < csb_read; i++) {
565 if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) {
566 if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) {
567 if (execlists_check_remove_request(engine, csb[i][1]))
568 WARN(1, "Lite Restored request removed from queue\n");
570 WARN(1, "Preemption without Lite Restore\n");
573 if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE |
574 GEN8_CTX_STATUS_ELEMENT_SWITCH))
576 execlists_check_remove_request(engine, csb[i][1]);
579 if (submit_contexts) {
580 if (!engine->disable_lite_restore_wa ||
581 (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
582 execlists_context_unqueue(engine);
585 spin_unlock(&engine->execlist_lock);
587 if (unlikely(submit_contexts > 2))
588 DRM_ERROR("More than two context complete events?\n");
591 static void execlists_context_queue(struct drm_i915_gem_request *request)
593 struct intel_engine_cs *engine = request->engine;
594 struct drm_i915_gem_request *cursor;
595 int num_elements = 0;
597 intel_lr_context_pin(request->ctx, request->engine);
598 i915_gem_request_reference(request);
600 spin_lock_bh(&engine->execlist_lock);
602 list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
603 if (++num_elements > 2)
606 if (num_elements > 2) {
607 struct drm_i915_gem_request *tail_req;
609 tail_req = list_last_entry(&engine->execlist_queue,
610 struct drm_i915_gem_request,
613 if (request->ctx == tail_req->ctx) {
614 WARN(tail_req->elsp_submitted != 0,
615 "More than 2 already-submitted reqs queued\n");
616 list_move_tail(&tail_req->execlist_link,
617 &engine->execlist_retired_req_list);
621 list_add_tail(&request->execlist_link, &engine->execlist_queue);
622 request->ctx_hw_id = request->ctx->hw_id;
623 if (num_elements == 0)
624 execlists_context_unqueue(engine);
626 spin_unlock_bh(&engine->execlist_lock);
629 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
631 struct intel_engine_cs *engine = req->engine;
632 uint32_t flush_domains;
636 if (engine->gpu_caches_dirty)
637 flush_domains = I915_GEM_GPU_DOMAINS;
639 ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
643 engine->gpu_caches_dirty = false;
647 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
648 struct list_head *vmas)
650 const unsigned other_rings = ~intel_engine_flag(req->engine);
651 struct i915_vma *vma;
652 uint32_t flush_domains = 0;
653 bool flush_chipset = false;
656 list_for_each_entry(vma, vmas, exec_list) {
657 struct drm_i915_gem_object *obj = vma->obj;
659 if (obj->active & other_rings) {
660 ret = i915_gem_object_sync(obj, req->engine, &req);
665 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
666 flush_chipset |= i915_gem_clflush_object(obj, false);
668 flush_domains |= obj->base.write_domain;
671 if (flush_domains & I915_GEM_DOMAIN_GTT)
674 /* Unconditionally invalidate gpu caches and ensure that we do flush
675 * any residual writes from the previous batch.
677 return logical_ring_invalidate_all_caches(req);
680 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
682 struct intel_engine_cs *engine = request->engine;
685 /* Flush enough space to reduce the likelihood of waiting after
686 * we start building the request - in which case we will just
687 * have to repeat work.
689 request->reserved_space += MIN_SPACE_FOR_ADD_REQUEST;
691 if (request->ctx->engine[engine->id].state == NULL) {
692 ret = execlists_context_deferred_alloc(request->ctx, engine);
697 request->ringbuf = request->ctx->engine[engine->id].ringbuf;
699 if (i915.enable_guc_submission) {
701 * Check that the GuC has space for the request before
702 * going any further, as the i915_add_request() call
703 * later on mustn't fail ...
705 struct intel_guc *guc = &request->i915->guc;
707 ret = i915_guc_wq_check_space(guc->execbuf_client);
712 ret = intel_lr_context_pin(request->ctx, engine);
716 ret = intel_ring_begin(request, 0);
720 if (!request->ctx->engine[engine->id].initialised) {
721 ret = engine->init_context(request);
725 request->ctx->engine[engine->id].initialised = true;
728 /* Note that after this point, we have committed to using
729 * this request as it is being used to both track the
730 * state of engine initialisation and liveness of the
731 * golden renderstate above. Think twice before you try
732 * to cancel/unwind this request now.
735 request->reserved_space -= MIN_SPACE_FOR_ADD_REQUEST;
739 intel_lr_context_unpin(request->ctx, engine);
744 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
745 * @request: Request to advance the logical ringbuffer of.
747 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
748 * really happens during submission is that the context and current tail will be placed
749 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
750 * point, the tail *inside* the context is updated and the ELSP written to.
753 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
755 struct intel_ringbuffer *ringbuf = request->ringbuf;
756 struct drm_i915_private *dev_priv = request->i915;
757 struct intel_engine_cs *engine = request->engine;
759 intel_logical_ring_advance(ringbuf);
760 request->tail = ringbuf->tail;
763 * Here we add two extra NOOPs as padding to avoid
764 * lite restore of a context with HEAD==TAIL.
766 * Caller must reserve WA_TAIL_DWORDS for us!
768 intel_logical_ring_emit(ringbuf, MI_NOOP);
769 intel_logical_ring_emit(ringbuf, MI_NOOP);
770 intel_logical_ring_advance(ringbuf);
772 if (intel_engine_stopped(engine))
775 /* We keep the previous context alive until we retire the following
776 * request. This ensures that any the context object is still pinned
777 * for any residual writes the HW makes into it on the context switch
778 * into the next object following the breadcrumb. Otherwise, we may
779 * retire the context too early.
781 request->previous_context = engine->last_context;
782 engine->last_context = request->ctx;
784 if (dev_priv->guc.execbuf_client)
785 i915_guc_submit(dev_priv->guc.execbuf_client, request);
787 execlists_context_queue(request);
793 * execlists_submission() - submit a batchbuffer for execution, Execlists style
796 * @ring: Engine Command Streamer to submit to.
797 * @ctx: Context to employ for this submission.
798 * @args: execbuffer call arguments.
799 * @vmas: list of vmas.
800 * @batch_obj: the batchbuffer to submit.
801 * @exec_start: batchbuffer start virtual address pointer.
802 * @dispatch_flags: translated execbuffer call flags.
804 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
805 * away the submission details of the execbuffer ioctl call.
807 * Return: non-zero if the submission fails.
809 int intel_execlists_submission(struct i915_execbuffer_params *params,
810 struct drm_i915_gem_execbuffer2 *args,
811 struct list_head *vmas)
813 struct drm_device *dev = params->dev;
814 struct intel_engine_cs *engine = params->engine;
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf;
822 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
823 instp_mask = I915_EXEC_CONSTANTS_MASK;
824 switch (instp_mode) {
825 case I915_EXEC_CONSTANTS_REL_GENERAL:
826 case I915_EXEC_CONSTANTS_ABSOLUTE:
827 case I915_EXEC_CONSTANTS_REL_SURFACE:
828 if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {
829 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
833 if (instp_mode != dev_priv->relative_constants_mode) {
834 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
835 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
839 /* The HW changed the meaning on this bit on gen6 */
840 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
844 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
848 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
849 DRM_DEBUG("sol reset is gen7 only\n");
853 ret = execlists_move_to_gpu(params->request, vmas);
857 if (engine == &dev_priv->engine[RCS] &&
858 instp_mode != dev_priv->relative_constants_mode) {
859 ret = intel_ring_begin(params->request, 4);
863 intel_logical_ring_emit(ringbuf, MI_NOOP);
864 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
865 intel_logical_ring_emit_reg(ringbuf, INSTPM);
866 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
867 intel_logical_ring_advance(ringbuf);
869 dev_priv->relative_constants_mode = instp_mode;
872 exec_start = params->batch_obj_vm_offset +
873 args->batch_start_offset;
875 ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags);
879 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
881 i915_gem_execbuffer_move_to_active(vmas, params->request);
886 void intel_execlists_retire_requests(struct intel_engine_cs *engine)
888 struct drm_i915_gem_request *req, *tmp;
889 struct list_head retired_list;
891 WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
892 if (list_empty(&engine->execlist_retired_req_list))
895 INIT_LIST_HEAD(&retired_list);
896 spin_lock_bh(&engine->execlist_lock);
897 list_replace_init(&engine->execlist_retired_req_list, &retired_list);
898 spin_unlock_bh(&engine->execlist_lock);
900 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
901 intel_lr_context_unpin(req->ctx, engine);
903 list_del(&req->execlist_link);
904 i915_gem_request_unreference(req);
908 void intel_logical_ring_stop(struct intel_engine_cs *engine)
910 struct drm_i915_private *dev_priv = engine->dev->dev_private;
913 if (!intel_engine_initialized(engine))
916 ret = intel_engine_idle(engine);
918 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
921 /* TODO: Is this correct with Execlists enabled? */
922 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
923 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
924 DRM_ERROR("%s :timed out trying to stop ring\n", engine->name);
927 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
930 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
932 struct intel_engine_cs *engine = req->engine;
935 if (!engine->gpu_caches_dirty)
938 ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
942 engine->gpu_caches_dirty = false;
946 static int intel_lr_context_pin(struct intel_context *ctx,
947 struct intel_engine_cs *engine)
949 struct drm_i915_private *dev_priv = ctx->i915;
950 struct drm_i915_gem_object *ctx_obj;
951 struct intel_ringbuffer *ringbuf;
956 lockdep_assert_held(&ctx->i915->dev->struct_mutex);
958 if (ctx->engine[engine->id].pin_count++)
961 ctx_obj = ctx->engine[engine->id].state;
962 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
963 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
967 vaddr = i915_gem_object_pin_map(ctx_obj);
969 ret = PTR_ERR(vaddr);
973 lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
975 ringbuf = ctx->engine[engine->id].ringbuf;
976 ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf);
980 i915_gem_context_reference(ctx);
981 ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj);
982 intel_lr_context_descriptor_update(ctx, engine);
983 lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start;
984 ctx->engine[engine->id].lrc_reg_state = lrc_reg_state;
985 ctx_obj->dirty = true;
987 /* Invalidate GuC TLB. */
988 if (i915.enable_guc_submission)
989 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
994 i915_gem_object_unpin_map(ctx_obj);
996 i915_gem_object_ggtt_unpin(ctx_obj);
998 ctx->engine[engine->id].pin_count = 0;
1002 void intel_lr_context_unpin(struct intel_context *ctx,
1003 struct intel_engine_cs *engine)
1005 struct drm_i915_gem_object *ctx_obj;
1007 lockdep_assert_held(&ctx->i915->dev->struct_mutex);
1008 GEM_BUG_ON(ctx->engine[engine->id].pin_count == 0);
1010 if (--ctx->engine[engine->id].pin_count)
1013 intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf);
1015 ctx_obj = ctx->engine[engine->id].state;
1016 i915_gem_object_unpin_map(ctx_obj);
1017 i915_gem_object_ggtt_unpin(ctx_obj);
1019 ctx->engine[engine->id].lrc_vma = NULL;
1020 ctx->engine[engine->id].lrc_desc = 0;
1021 ctx->engine[engine->id].lrc_reg_state = NULL;
1023 i915_gem_context_unreference(ctx);
1026 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1029 struct intel_engine_cs *engine = req->engine;
1030 struct intel_ringbuffer *ringbuf = req->ringbuf;
1031 struct drm_device *dev = engine->dev;
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 struct i915_workarounds *w = &dev_priv->workarounds;
1038 engine->gpu_caches_dirty = true;
1039 ret = logical_ring_flush_all_caches(req);
1043 ret = intel_ring_begin(req, w->count * 2 + 2);
1047 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1048 for (i = 0; i < w->count; i++) {
1049 intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
1050 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1052 intel_logical_ring_emit(ringbuf, MI_NOOP);
1054 intel_logical_ring_advance(ringbuf);
1056 engine->gpu_caches_dirty = true;
1057 ret = logical_ring_flush_all_caches(req);
1064 #define wa_ctx_emit(batch, index, cmd) \
1066 int __index = (index)++; \
1067 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1070 batch[__index] = (cmd); \
1073 #define wa_ctx_emit_reg(batch, index, reg) \
1074 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1077 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1078 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1079 * but there is a slight complication as this is applied in WA batch where the
1080 * values are only initialized once so we cannot take register value at the
1081 * beginning and reuse it further; hence we save its value to memory, upload a
1082 * constant value with bit21 set and then we restore it back with the saved value.
1083 * To simplify the WA, a constant value is formed by using the default value
1084 * of this register. This shouldn't be a problem because we are only modifying
1085 * it for a short period and this batch in non-premptible. We can ofcourse
1086 * use additional instructions that read the actual value of the register
1087 * at that time and set our bit of interest but it makes the WA complicated.
1089 * This WA is also required for Gen9 so extracting as a function avoids
1092 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
1093 uint32_t *const batch,
1096 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1099 * WaDisableLSQCROPERFforOCL:skl
1100 * This WA is implemented in skl_init_clock_gating() but since
1101 * this batch updates GEN8_L3SQCREG4 with default value we need to
1102 * set this bit here to retain the WA during flush.
1104 if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
1105 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1107 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1108 MI_SRM_LRM_GLOBAL_GTT));
1109 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1110 wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1111 wa_ctx_emit(batch, index, 0);
1113 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1114 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1115 wa_ctx_emit(batch, index, l3sqc4_flush);
1117 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1118 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1119 PIPE_CONTROL_DC_FLUSH_ENABLE));
1120 wa_ctx_emit(batch, index, 0);
1121 wa_ctx_emit(batch, index, 0);
1122 wa_ctx_emit(batch, index, 0);
1123 wa_ctx_emit(batch, index, 0);
1125 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1126 MI_SRM_LRM_GLOBAL_GTT));
1127 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1128 wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1129 wa_ctx_emit(batch, index, 0);
1134 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1136 uint32_t start_alignment)
1138 return wa_ctx->offset = ALIGN(offset, start_alignment);
1141 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1143 uint32_t size_alignment)
1145 wa_ctx->size = offset - wa_ctx->offset;
1147 WARN(wa_ctx->size % size_alignment,
1148 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1149 wa_ctx->size, size_alignment);
1154 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1156 * @ring: only applicable for RCS
1157 * @wa_ctx: structure representing wa_ctx
1158 * offset: specifies start of the batch, should be cache-aligned. This is updated
1159 * with the offset value received as input.
1160 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1161 * @batch: page in which WA are loaded
1162 * @offset: This field specifies the start of the batch, it should be
1163 * cache-aligned otherwise it is adjusted accordingly.
1164 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1165 * initialized at the beginning and shared across all contexts but this field
1166 * helps us to have multiple batches at different offsets and select them based
1167 * on a criteria. At the moment this batch always start at the beginning of the page
1168 * and at this point we don't have multiple wa_ctx batch buffers.
1170 * The number of WA applied are not known at the beginning; we use this field
1171 * to return the no of DWORDS written.
1173 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1174 * so it adds NOOPs as padding to make it cacheline aligned.
1175 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1176 * makes a complete batch buffer.
1178 * Return: non-zero if we exceed the PAGE_SIZE limit.
1181 static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1182 struct i915_wa_ctx_bb *wa_ctx,
1183 uint32_t *const batch,
1186 uint32_t scratch_addr;
1187 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1189 /* WaDisableCtxRestoreArbitration:bdw,chv */
1190 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1192 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1193 if (IS_BROADWELL(engine->dev)) {
1194 int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1200 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1201 /* Actual scratch location is at 128 bytes offset */
1202 scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1204 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1205 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1206 PIPE_CONTROL_GLOBAL_GTT_IVB |
1207 PIPE_CONTROL_CS_STALL |
1208 PIPE_CONTROL_QW_WRITE));
1209 wa_ctx_emit(batch, index, scratch_addr);
1210 wa_ctx_emit(batch, index, 0);
1211 wa_ctx_emit(batch, index, 0);
1212 wa_ctx_emit(batch, index, 0);
1214 /* Pad to end of cacheline */
1215 while (index % CACHELINE_DWORDS)
1216 wa_ctx_emit(batch, index, MI_NOOP);
1219 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1220 * execution depends on the length specified in terms of cache lines
1221 * in the register CTX_RCS_INDIRECT_CTX
1224 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1228 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1230 * @ring: only applicable for RCS
1231 * @wa_ctx: structure representing wa_ctx
1232 * offset: specifies start of the batch, should be cache-aligned.
1233 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1234 * @batch: page in which WA are loaded
1235 * @offset: This field specifies the start of this batch.
1236 * This batch is started immediately after indirect_ctx batch. Since we ensure
1237 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1239 * The number of DWORDS written are returned using this field.
1241 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1242 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1244 static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1245 struct i915_wa_ctx_bb *wa_ctx,
1246 uint32_t *const batch,
1249 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1251 /* WaDisableCtxRestoreArbitration:bdw,chv */
1252 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1254 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1256 return wa_ctx_end(wa_ctx, *offset = index, 1);
1259 static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1260 struct i915_wa_ctx_bb *wa_ctx,
1261 uint32_t *const batch,
1265 struct drm_device *dev = engine->dev;
1266 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1268 /* WaDisableCtxRestoreArbitration:skl,bxt */
1269 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1270 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1271 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1273 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1274 ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1279 /* Pad to end of cacheline */
1280 while (index % CACHELINE_DWORDS)
1281 wa_ctx_emit(batch, index, MI_NOOP);
1283 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1286 static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1287 struct i915_wa_ctx_bb *wa_ctx,
1288 uint32_t *const batch,
1291 struct drm_device *dev = engine->dev;
1292 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1294 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1295 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
1296 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1297 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1298 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1299 wa_ctx_emit(batch, index,
1300 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1301 wa_ctx_emit(batch, index, MI_NOOP);
1304 /* WaClearTdlStateAckDirtyBits:bxt */
1305 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1306 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
1308 wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
1309 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1311 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1);
1312 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1314 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2);
1315 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1317 wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2);
1318 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1319 wa_ctx_emit(batch, index, 0x0);
1320 wa_ctx_emit(batch, index, MI_NOOP);
1323 /* WaDisableCtxRestoreArbitration:skl,bxt */
1324 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1325 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1326 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1328 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1330 return wa_ctx_end(wa_ctx, *offset = index, 1);
1333 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1337 engine->wa_ctx.obj = i915_gem_object_create(engine->dev,
1339 if (IS_ERR(engine->wa_ctx.obj)) {
1340 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1341 ret = PTR_ERR(engine->wa_ctx.obj);
1342 engine->wa_ctx.obj = NULL;
1346 ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0);
1348 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1350 drm_gem_object_unreference(&engine->wa_ctx.obj->base);
1357 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1359 if (engine->wa_ctx.obj) {
1360 i915_gem_object_ggtt_unpin(engine->wa_ctx.obj);
1361 drm_gem_object_unreference(&engine->wa_ctx.obj->base);
1362 engine->wa_ctx.obj = NULL;
1366 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1372 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1374 WARN_ON(engine->id != RCS);
1376 /* update this when WA for higher Gen are added */
1377 if (INTEL_INFO(engine->dev)->gen > 9) {
1378 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1379 INTEL_INFO(engine->dev)->gen);
1383 /* some WA perform writes to scratch page, ensure it is valid */
1384 if (engine->scratch.obj == NULL) {
1385 DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1389 ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1391 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1395 page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1396 batch = kmap_atomic(page);
1399 if (INTEL_INFO(engine->dev)->gen == 8) {
1400 ret = gen8_init_indirectctx_bb(engine,
1401 &wa_ctx->indirect_ctx,
1407 ret = gen8_init_perctx_bb(engine,
1413 } else if (INTEL_INFO(engine->dev)->gen == 9) {
1414 ret = gen9_init_indirectctx_bb(engine,
1415 &wa_ctx->indirect_ctx,
1421 ret = gen9_init_perctx_bb(engine,
1430 kunmap_atomic(batch);
1432 lrc_destroy_wa_ctx_obj(engine);
1437 static void lrc_init_hws(struct intel_engine_cs *engine)
1439 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1441 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1442 (u32)engine->status_page.gfx_addr);
1443 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1446 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1448 struct drm_device *dev = engine->dev;
1449 struct drm_i915_private *dev_priv = dev->dev_private;
1450 unsigned int next_context_status_buffer_hw;
1452 lrc_init_hws(engine);
1454 I915_WRITE_IMR(engine,
1455 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1456 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1458 I915_WRITE(RING_MODE_GEN7(engine),
1459 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1460 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1461 POSTING_READ(RING_MODE_GEN7(engine));
1464 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1465 * zero, we need to read the write pointer from hardware and use its
1466 * value because "this register is power context save restored".
1467 * Effectively, these states have been observed:
1469 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1470 * BDW | CSB regs not reset | CSB regs reset |
1471 * CHT | CSB regs not reset | CSB regs not reset |
1475 next_context_status_buffer_hw =
1476 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine)));
1479 * When the CSB registers are reset (also after power-up / gpu reset),
1480 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1481 * this special case, so the first element read is CSB[0].
1483 if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
1484 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);
1486 engine->next_context_status_buffer = next_context_status_buffer_hw;
1487 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1489 intel_engine_init_hangcheck(engine);
1491 return intel_mocs_init_engine(engine);
1494 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1496 struct drm_device *dev = engine->dev;
1497 struct drm_i915_private *dev_priv = dev->dev_private;
1500 ret = gen8_init_common_ring(engine);
1504 /* We need to disable the AsyncFlip performance optimisations in order
1505 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1506 * programmed to '1' on all products.
1508 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1510 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1512 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1514 return init_workarounds_ring(engine);
1517 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1521 ret = gen8_init_common_ring(engine);
1525 return init_workarounds_ring(engine);
1528 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1530 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1531 struct intel_engine_cs *engine = req->engine;
1532 struct intel_ringbuffer *ringbuf = req->ringbuf;
1533 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1536 ret = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1540 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1541 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1542 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1544 intel_logical_ring_emit_reg(ringbuf,
1545 GEN8_RING_PDP_UDW(engine, i));
1546 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1547 intel_logical_ring_emit_reg(ringbuf,
1548 GEN8_RING_PDP_LDW(engine, i));
1549 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1552 intel_logical_ring_emit(ringbuf, MI_NOOP);
1553 intel_logical_ring_advance(ringbuf);
1558 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1559 u64 offset, unsigned dispatch_flags)
1561 struct intel_ringbuffer *ringbuf = req->ringbuf;
1562 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1565 /* Don't rely in hw updating PDPs, specially in lite-restore.
1566 * Ideally, we should set Force PD Restore in ctx descriptor,
1567 * but we can't. Force Restore would be a second option, but
1568 * it is unsafe in case of lite-restore (because the ctx is
1569 * not idle). PML4 is allocated during ppgtt init so this is
1570 * not needed in 48-bit.*/
1571 if (req->ctx->ppgtt &&
1572 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1573 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1574 !intel_vgpu_active(req->i915->dev)) {
1575 ret = intel_logical_ring_emit_pdps(req);
1580 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1583 ret = intel_ring_begin(req, 4);
1587 /* FIXME(BDW): Address space and security selectors. */
1588 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1590 (dispatch_flags & I915_DISPATCH_RS ?
1591 MI_BATCH_RESOURCE_STREAMER : 0));
1592 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1593 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1594 intel_logical_ring_emit(ringbuf, MI_NOOP);
1595 intel_logical_ring_advance(ringbuf);
1600 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
1602 struct drm_device *dev = engine->dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 unsigned long flags;
1606 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1609 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1610 if (engine->irq_refcount++ == 0) {
1611 I915_WRITE_IMR(engine,
1612 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1613 POSTING_READ(RING_IMR(engine->mmio_base));
1615 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1620 static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
1622 struct drm_device *dev = engine->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 unsigned long flags;
1626 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1627 if (--engine->irq_refcount == 0) {
1628 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1629 POSTING_READ(RING_IMR(engine->mmio_base));
1631 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1634 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1635 u32 invalidate_domains,
1638 struct intel_ringbuffer *ringbuf = request->ringbuf;
1639 struct intel_engine_cs *engine = ringbuf->engine;
1640 struct drm_device *dev = engine->dev;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1645 ret = intel_ring_begin(request, 4);
1649 cmd = MI_FLUSH_DW + 1;
1651 /* We always require a command barrier so that subsequent
1652 * commands, such as breadcrumb interrupts, are strictly ordered
1653 * wrt the contents of the write cache being flushed to memory
1654 * (and thus being coherent from the CPU).
1656 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1658 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1659 cmd |= MI_INVALIDATE_TLB;
1660 if (engine == &dev_priv->engine[VCS])
1661 cmd |= MI_INVALIDATE_BSD;
1664 intel_logical_ring_emit(ringbuf, cmd);
1665 intel_logical_ring_emit(ringbuf,
1666 I915_GEM_HWS_SCRATCH_ADDR |
1667 MI_FLUSH_DW_USE_GTT);
1668 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1669 intel_logical_ring_emit(ringbuf, 0); /* value */
1670 intel_logical_ring_advance(ringbuf);
1675 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1676 u32 invalidate_domains,
1679 struct intel_ringbuffer *ringbuf = request->ringbuf;
1680 struct intel_engine_cs *engine = ringbuf->engine;
1681 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1682 bool vf_flush_wa = false;
1686 flags |= PIPE_CONTROL_CS_STALL;
1688 if (flush_domains) {
1689 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1690 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1691 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1692 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1695 if (invalidate_domains) {
1696 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1697 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1698 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1699 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1700 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1701 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1702 flags |= PIPE_CONTROL_QW_WRITE;
1703 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1706 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1709 if (IS_GEN9(engine->dev))
1713 ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
1718 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1719 intel_logical_ring_emit(ringbuf, 0);
1720 intel_logical_ring_emit(ringbuf, 0);
1721 intel_logical_ring_emit(ringbuf, 0);
1722 intel_logical_ring_emit(ringbuf, 0);
1723 intel_logical_ring_emit(ringbuf, 0);
1726 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1727 intel_logical_ring_emit(ringbuf, flags);
1728 intel_logical_ring_emit(ringbuf, scratch_addr);
1729 intel_logical_ring_emit(ringbuf, 0);
1730 intel_logical_ring_emit(ringbuf, 0);
1731 intel_logical_ring_emit(ringbuf, 0);
1732 intel_logical_ring_advance(ringbuf);
1737 static u32 gen8_get_seqno(struct intel_engine_cs *engine)
1739 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1742 static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1744 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1747 static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
1750 * On BXT A steppings there is a HW coherency issue whereby the
1751 * MI_STORE_DATA_IMM storing the completed request's seqno
1752 * occasionally doesn't invalidate the CPU cache. Work around this by
1753 * clflushing the corresponding cacheline whenever the caller wants
1754 * the coherency to be guaranteed. Note that this cacheline is known
1755 * to be clean at this point, since we only write it in
1756 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1757 * this clflush in practice becomes an invalidate operation.
1759 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1762 static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1764 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1766 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1767 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1771 * Reserve space for 2 NOOPs at the end of each request to be
1772 * used as a workaround for not being allowed to do lite
1773 * restore with HEAD==TAIL (WaIdleLiteRestore).
1775 #define WA_TAIL_DWORDS 2
1777 static inline u32 hws_seqno_address(struct intel_engine_cs *engine)
1779 return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR;
1782 static int gen8_emit_request(struct drm_i915_gem_request *request)
1784 struct intel_ringbuffer *ringbuf = request->ringbuf;
1787 ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS);
1791 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1792 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1794 intel_logical_ring_emit(ringbuf,
1795 (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
1796 intel_logical_ring_emit(ringbuf,
1797 hws_seqno_address(request->engine) |
1798 MI_FLUSH_DW_USE_GTT);
1799 intel_logical_ring_emit(ringbuf, 0);
1800 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1801 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1802 intel_logical_ring_emit(ringbuf, MI_NOOP);
1803 return intel_logical_ring_advance_and_submit(request);
1806 static int gen8_emit_request_render(struct drm_i915_gem_request *request)
1808 struct intel_ringbuffer *ringbuf = request->ringbuf;
1811 ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS);
1815 /* We're using qword write, seqno should be aligned to 8 bytes. */
1816 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1818 /* w/a for post sync ops following a GPGPU operation we
1819 * need a prior CS_STALL, which is emitted by the flush
1820 * following the batch.
1822 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1823 intel_logical_ring_emit(ringbuf,
1824 (PIPE_CONTROL_GLOBAL_GTT_IVB |
1825 PIPE_CONTROL_CS_STALL |
1826 PIPE_CONTROL_QW_WRITE));
1827 intel_logical_ring_emit(ringbuf, hws_seqno_address(request->engine));
1828 intel_logical_ring_emit(ringbuf, 0);
1829 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1830 /* We're thrashing one dword of HWS. */
1831 intel_logical_ring_emit(ringbuf, 0);
1832 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1833 intel_logical_ring_emit(ringbuf, MI_NOOP);
1834 return intel_logical_ring_advance_and_submit(request);
1837 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1839 struct render_state so;
1842 ret = i915_gem_render_state_prepare(req->engine, &so);
1846 if (so.rodata == NULL)
1849 ret = req->engine->emit_bb_start(req, so.ggtt_offset,
1850 I915_DISPATCH_SECURE);
1854 ret = req->engine->emit_bb_start(req,
1855 (so.ggtt_offset + so.aux_batch_offset),
1856 I915_DISPATCH_SECURE);
1860 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1863 i915_gem_render_state_fini(&so);
1867 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1871 ret = intel_logical_ring_workarounds_emit(req);
1875 ret = intel_rcs_context_init_mocs(req);
1877 * Failing to program the MOCS is non-fatal.The system will not
1878 * run at peak performance. So generate an error and carry on.
1881 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1883 return intel_lr_context_render_state_init(req);
1887 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1889 * @ring: Engine Command Streamer.
1892 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1894 struct drm_i915_private *dev_priv;
1896 if (!intel_engine_initialized(engine))
1900 * Tasklet cannot be active at this point due intel_mark_active/idle
1901 * so this is just for documentation.
1903 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
1904 tasklet_kill(&engine->irq_tasklet);
1906 dev_priv = engine->dev->dev_private;
1908 if (engine->buffer) {
1909 intel_logical_ring_stop(engine);
1910 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1913 if (engine->cleanup)
1914 engine->cleanup(engine);
1916 i915_cmd_parser_fini_ring(engine);
1917 i915_gem_batch_pool_fini(&engine->batch_pool);
1919 if (engine->status_page.obj) {
1920 i915_gem_object_unpin_map(engine->status_page.obj);
1921 engine->status_page.obj = NULL;
1923 intel_lr_context_unpin(dev_priv->kernel_context, engine);
1925 engine->idle_lite_restore_wa = 0;
1926 engine->disable_lite_restore_wa = false;
1927 engine->ctx_desc_template = 0;
1929 lrc_destroy_wa_ctx_obj(engine);
1934 logical_ring_default_vfuncs(struct drm_device *dev,
1935 struct intel_engine_cs *engine)
1937 /* Default vfuncs which can be overriden by each engine. */
1938 engine->init_hw = gen8_init_common_ring;
1939 engine->emit_request = gen8_emit_request;
1940 engine->emit_flush = gen8_emit_flush;
1941 engine->irq_get = gen8_logical_ring_get_irq;
1942 engine->irq_put = gen8_logical_ring_put_irq;
1943 engine->emit_bb_start = gen8_emit_bb_start;
1944 engine->get_seqno = gen8_get_seqno;
1945 engine->set_seqno = gen8_set_seqno;
1946 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1947 engine->irq_seqno_barrier = bxt_a_seqno_barrier;
1948 engine->set_seqno = bxt_a_set_seqno;
1953 logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
1955 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1956 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1960 lrc_setup_hws(struct intel_engine_cs *engine,
1961 struct drm_i915_gem_object *dctx_obj)
1965 /* The HWSP is part of the default context object in LRC mode. */
1966 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) +
1967 LRC_PPHWSP_PN * PAGE_SIZE;
1968 hws = i915_gem_object_pin_map(dctx_obj);
1970 return PTR_ERR(hws);
1971 engine->status_page.page_addr = hws + LRC_PPHWSP_PN * PAGE_SIZE;
1972 engine->status_page.obj = dctx_obj;
1978 logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
1980 struct drm_i915_private *dev_priv = to_i915(dev);
1981 struct intel_context *dctx = dev_priv->kernel_context;
1982 enum forcewake_domains fw_domains;
1985 /* Intentionally left blank. */
1986 engine->buffer = NULL;
1989 INIT_LIST_HEAD(&engine->active_list);
1990 INIT_LIST_HEAD(&engine->request_list);
1991 i915_gem_batch_pool_init(dev, &engine->batch_pool);
1992 init_waitqueue_head(&engine->irq_queue);
1994 INIT_LIST_HEAD(&engine->buffers);
1995 INIT_LIST_HEAD(&engine->execlist_queue);
1996 INIT_LIST_HEAD(&engine->execlist_retired_req_list);
1997 spin_lock_init(&engine->execlist_lock);
1999 tasklet_init(&engine->irq_tasklet,
2000 intel_lrc_irq_handler, (unsigned long)engine);
2002 logical_ring_init_platform_invariants(engine);
2004 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
2008 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
2009 RING_CONTEXT_STATUS_PTR(engine),
2010 FW_REG_READ | FW_REG_WRITE);
2012 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
2013 RING_CONTEXT_STATUS_BUF_BASE(engine),
2016 engine->fw_domains = fw_domains;
2018 ret = i915_cmd_parser_init_ring(engine);
2022 ret = execlists_context_deferred_alloc(dctx, engine);
2026 /* As this is the default context, always pin it */
2027 ret = intel_lr_context_pin(dctx, engine);
2029 DRM_ERROR("Failed to pin context for %s: %d\n",
2034 /* And setup the hardware status page. */
2035 ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
2037 DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
2044 intel_logical_ring_cleanup(engine);
2048 static int logical_render_ring_init(struct drm_device *dev)
2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2054 engine->name = "render ring";
2056 engine->exec_id = I915_EXEC_RENDER;
2057 engine->guc_id = GUC_RENDER_ENGINE;
2058 engine->mmio_base = RENDER_RING_BASE;
2060 logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT);
2061 if (HAS_L3_DPF(dev))
2062 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2064 logical_ring_default_vfuncs(dev, engine);
2066 /* Override some for render ring. */
2067 if (INTEL_INFO(dev)->gen >= 9)
2068 engine->init_hw = gen9_init_render_ring;
2070 engine->init_hw = gen8_init_render_ring;
2071 engine->init_context = gen8_init_rcs_context;
2072 engine->cleanup = intel_fini_pipe_control;
2073 engine->emit_flush = gen8_emit_flush_render;
2074 engine->emit_request = gen8_emit_request_render;
2078 ret = intel_init_pipe_control(engine);
2082 ret = intel_init_workaround_bb(engine);
2085 * We continue even if we fail to initialize WA batch
2086 * because we only expect rare glitches but nothing
2087 * critical to prevent us from using GPU
2089 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2093 ret = logical_ring_init(dev, engine);
2095 lrc_destroy_wa_ctx_obj(engine);
2101 static int logical_bsd_ring_init(struct drm_device *dev)
2103 struct drm_i915_private *dev_priv = dev->dev_private;
2104 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2106 engine->name = "bsd ring";
2108 engine->exec_id = I915_EXEC_BSD;
2109 engine->guc_id = GUC_VIDEO_ENGINE;
2110 engine->mmio_base = GEN6_BSD_RING_BASE;
2112 logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT);
2113 logical_ring_default_vfuncs(dev, engine);
2115 return logical_ring_init(dev, engine);
2118 static int logical_bsd2_ring_init(struct drm_device *dev)
2120 struct drm_i915_private *dev_priv = dev->dev_private;
2121 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2123 engine->name = "bsd2 ring";
2125 engine->exec_id = I915_EXEC_BSD;
2126 engine->guc_id = GUC_VIDEO_ENGINE2;
2127 engine->mmio_base = GEN8_BSD2_RING_BASE;
2129 logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT);
2130 logical_ring_default_vfuncs(dev, engine);
2132 return logical_ring_init(dev, engine);
2135 static int logical_blt_ring_init(struct drm_device *dev)
2137 struct drm_i915_private *dev_priv = dev->dev_private;
2138 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
2140 engine->name = "blitter ring";
2142 engine->exec_id = I915_EXEC_BLT;
2143 engine->guc_id = GUC_BLITTER_ENGINE;
2144 engine->mmio_base = BLT_RING_BASE;
2146 logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT);
2147 logical_ring_default_vfuncs(dev, engine);
2149 return logical_ring_init(dev, engine);
2152 static int logical_vebox_ring_init(struct drm_device *dev)
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2155 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
2157 engine->name = "video enhancement ring";
2159 engine->exec_id = I915_EXEC_VEBOX;
2160 engine->guc_id = GUC_VIDEOENHANCE_ENGINE;
2161 engine->mmio_base = VEBOX_RING_BASE;
2163 logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT);
2164 logical_ring_default_vfuncs(dev, engine);
2166 return logical_ring_init(dev, engine);
2170 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2173 * This function inits the engines for an Execlists submission style (the equivalent in the
2174 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2175 * those engines that are present in the hardware.
2177 * Return: non-zero if the initialization failed.
2179 int intel_logical_rings_init(struct drm_device *dev)
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2184 ret = logical_render_ring_init(dev);
2189 ret = logical_bsd_ring_init(dev);
2191 goto cleanup_render_ring;
2195 ret = logical_blt_ring_init(dev);
2197 goto cleanup_bsd_ring;
2200 if (HAS_VEBOX(dev)) {
2201 ret = logical_vebox_ring_init(dev);
2203 goto cleanup_blt_ring;
2206 if (HAS_BSD2(dev)) {
2207 ret = logical_bsd2_ring_init(dev);
2209 goto cleanup_vebox_ring;
2215 intel_logical_ring_cleanup(&dev_priv->engine[VECS]);
2217 intel_logical_ring_cleanup(&dev_priv->engine[BCS]);
2219 intel_logical_ring_cleanup(&dev_priv->engine[VCS]);
2220 cleanup_render_ring:
2221 intel_logical_ring_cleanup(&dev_priv->engine[RCS]);
2227 make_rpcs(struct drm_device *dev)
2232 * No explicit RPCS request is needed to ensure full
2233 * slice/subslice/EU enablement prior to Gen9.
2235 if (INTEL_INFO(dev)->gen < 9)
2239 * Starting in Gen9, render power gating can leave
2240 * slice/subslice/EU in a partially enabled state. We
2241 * must make an explicit request through RPCS for full
2244 if (INTEL_INFO(dev)->has_slice_pg) {
2245 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2246 rpcs |= INTEL_INFO(dev)->slice_total <<
2247 GEN8_RPCS_S_CNT_SHIFT;
2248 rpcs |= GEN8_RPCS_ENABLE;
2251 if (INTEL_INFO(dev)->has_subslice_pg) {
2252 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2253 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2254 GEN8_RPCS_SS_CNT_SHIFT;
2255 rpcs |= GEN8_RPCS_ENABLE;
2258 if (INTEL_INFO(dev)->has_eu_pg) {
2259 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2260 GEN8_RPCS_EU_MIN_SHIFT;
2261 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2262 GEN8_RPCS_EU_MAX_SHIFT;
2263 rpcs |= GEN8_RPCS_ENABLE;
2269 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2271 u32 indirect_ctx_offset;
2273 switch (INTEL_INFO(engine->dev)->gen) {
2275 MISSING_CASE(INTEL_INFO(engine->dev)->gen);
2278 indirect_ctx_offset =
2279 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2282 indirect_ctx_offset =
2283 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2287 return indirect_ctx_offset;
2291 populate_lr_context(struct intel_context *ctx,
2292 struct drm_i915_gem_object *ctx_obj,
2293 struct intel_engine_cs *engine,
2294 struct intel_ringbuffer *ringbuf)
2296 struct drm_device *dev = engine->dev;
2297 struct drm_i915_private *dev_priv = dev->dev_private;
2298 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2304 ppgtt = dev_priv->mm.aliasing_ppgtt;
2306 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2308 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2312 vaddr = i915_gem_object_pin_map(ctx_obj);
2313 if (IS_ERR(vaddr)) {
2314 ret = PTR_ERR(vaddr);
2315 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2318 ctx_obj->dirty = true;
2320 /* The second page of the context object contains some fields which must
2321 * be set up prior to the first execution. */
2322 reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
2324 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2325 * commands followed by (reg, value) pairs. The values we are setting here are
2326 * only for the first context restore: on a subsequent save, the GPU will
2327 * recreate this batchbuffer with new values (including all the missing
2328 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2329 reg_state[CTX_LRI_HEADER_0] =
2330 MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
2331 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
2332 RING_CONTEXT_CONTROL(engine),
2333 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2334 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2335 (HAS_RESOURCE_STREAMER(dev) ?
2336 CTX_CTRL_RS_CTX_ENABLE : 0)));
2337 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
2339 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
2341 /* Ring buffer start address is not known until the buffer is pinned.
2342 * It is written to the context image in execlists_update_context()
2344 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
2345 RING_START(engine->mmio_base), 0);
2346 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
2347 RING_CTL(engine->mmio_base),
2348 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2349 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
2350 RING_BBADDR_UDW(engine->mmio_base), 0);
2351 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
2352 RING_BBADDR(engine->mmio_base), 0);
2353 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
2354 RING_BBSTATE(engine->mmio_base),
2356 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
2357 RING_SBBADDR_UDW(engine->mmio_base), 0);
2358 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
2359 RING_SBBADDR(engine->mmio_base), 0);
2360 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
2361 RING_SBBSTATE(engine->mmio_base), 0);
2362 if (engine->id == RCS) {
2363 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
2364 RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
2365 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
2366 RING_INDIRECT_CTX(engine->mmio_base), 0);
2367 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
2368 RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2369 if (engine->wa_ctx.obj) {
2370 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2371 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2373 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2374 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2375 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2377 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2378 intel_lr_indirect_ctx_offset(engine) << 6;
2380 reg_state[CTX_BB_PER_CTX_PTR+1] =
2381 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2385 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2386 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
2387 RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2388 /* PDP values well be assigned later if needed */
2389 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
2391 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
2393 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
2395 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
2397 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
2399 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
2401 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
2403 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
2406 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2407 /* 64b PPGTT (48bit canonical)
2408 * PDP0_DESCRIPTOR contains the base address to PML4 and
2409 * other PDP Descriptors are ignored.
2411 ASSIGN_CTX_PML4(ppgtt, reg_state);
2414 * PDP*_DESCRIPTOR contains the base address of space supported.
2415 * With dynamic page allocation, PDPs may not be allocated at
2416 * this point. Point the unallocated PDPs to the scratch page
2418 execlists_update_context_pdps(ppgtt, reg_state);
2421 if (engine->id == RCS) {
2422 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2423 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2427 i915_gem_object_unpin_map(ctx_obj);
2433 * intel_lr_context_free() - free the LRC specific bits of a context
2434 * @ctx: the LR context to free.
2436 * The real context freeing is done in i915_gem_context_free: this only
2437 * takes care of the bits that are LRC related: the per-engine backing
2438 * objects and the logical ringbuffer.
2440 void intel_lr_context_free(struct intel_context *ctx)
2444 for (i = I915_NUM_ENGINES; --i >= 0; ) {
2445 struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
2446 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2451 WARN_ON(ctx->engine[i].pin_count);
2452 intel_ringbuffer_free(ringbuf);
2453 drm_gem_object_unreference(&ctx_obj->base);
2458 * intel_lr_context_size() - return the size of the context for an engine
2459 * @ring: which engine to find the context size for
2461 * Each engine may require a different amount of space for a context image,
2462 * so when allocating (or copying) an image, this function can be used to
2463 * find the right size for the specific engine.
2465 * Return: size (in bytes) of an engine-specific context image
2467 * Note: this size includes the HWSP, which is part of the context image
2468 * in LRC mode, but does not include the "shared data page" used with
2469 * GuC submission. The caller should account for this if using the GuC.
2471 uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2475 WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
2477 switch (engine->id) {
2479 if (INTEL_INFO(engine->dev)->gen >= 9)
2480 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2482 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2488 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2496 * execlists_context_deferred_alloc() - create the LRC specific bits of a context
2497 * @ctx: LR context to create.
2498 * @engine: engine to be used with the context.
2500 * This function can be called more than once, with different engines, if we plan
2501 * to use the context with them. The context backing objects and the ringbuffers
2502 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2503 * the creation is a deferred call: it's better to make sure first that we need to use
2504 * a given ring with the context.
2506 * Return: non-zero on error.
2508 static int execlists_context_deferred_alloc(struct intel_context *ctx,
2509 struct intel_engine_cs *engine)
2511 struct drm_device *dev = engine->dev;
2512 struct drm_i915_gem_object *ctx_obj;
2513 uint32_t context_size;
2514 struct intel_ringbuffer *ringbuf;
2517 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2518 WARN_ON(ctx->engine[engine->id].state);
2520 context_size = round_up(intel_lr_context_size(engine), 4096);
2522 /* One extra page as the sharing data between driver and GuC */
2523 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2525 ctx_obj = i915_gem_object_create(dev, context_size);
2526 if (IS_ERR(ctx_obj)) {
2527 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2528 return PTR_ERR(ctx_obj);
2531 ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
2532 if (IS_ERR(ringbuf)) {
2533 ret = PTR_ERR(ringbuf);
2534 goto error_deref_obj;
2537 ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
2539 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2543 ctx->engine[engine->id].ringbuf = ringbuf;
2544 ctx->engine[engine->id].state = ctx_obj;
2545 ctx->engine[engine->id].initialised = engine->init_context == NULL;
2550 intel_ringbuffer_free(ringbuf);
2552 drm_gem_object_unreference(&ctx_obj->base);
2553 ctx->engine[engine->id].ringbuf = NULL;
2554 ctx->engine[engine->id].state = NULL;
2558 void intel_lr_context_reset(struct drm_i915_private *dev_priv,
2559 struct intel_context *ctx)
2561 struct intel_engine_cs *engine;
2563 for_each_engine(engine, dev_priv) {
2564 struct drm_i915_gem_object *ctx_obj =
2565 ctx->engine[engine->id].state;
2566 struct intel_ringbuffer *ringbuf =
2567 ctx->engine[engine->id].ringbuf;
2569 uint32_t *reg_state;
2574 vaddr = i915_gem_object_pin_map(ctx_obj);
2575 if (WARN_ON(IS_ERR(vaddr)))
2578 reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
2579 ctx_obj->dirty = true;
2581 reg_state[CTX_RING_HEAD+1] = 0;
2582 reg_state[CTX_RING_TAIL+1] = 0;
2584 i915_gem_object_unpin_map(ctx_obj);