2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
194 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
195 (reg_state)[(pos)+1] = (val); \
198 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
199 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
200 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
201 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
204 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
205 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
206 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
210 ADVANCED_CONTEXT = 0,
215 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
216 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
217 LEGACY_64B_CONTEXT :\
221 FAULT_AND_HALT, /* Debug only */
223 FAULT_AND_CONTINUE /* Unsupported */
225 #define GEN8_CTX_ID_SHIFT 32
226 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
228 static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
229 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
230 struct drm_i915_gem_object *default_ctx_obj);
234 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
236 * @enable_execlists: value of i915.enable_execlists module parameter.
238 * Only certain platforms support Execlists (the prerequisites being
239 * support for Logical Ring Contexts and Aliasing PPGTT or better).
241 * Return: 1 if Execlists is supported and has to be enabled.
243 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
245 WARN_ON(i915.enable_ppgtt == -1);
247 /* On platforms with execlist available, vGPU will only
248 * support execlist mode, no ring buffer mode.
250 if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
253 if (INTEL_INFO(dev)->gen >= 9)
256 if (enable_execlists == 0)
259 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
260 i915.use_mmio_flip >= 0)
267 logical_ring_init_platform_invariants(struct intel_engine_cs *ring)
269 struct drm_device *dev = ring->dev;
271 ring->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
272 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
273 (ring->id == VCS || ring->id == VCS2);
275 ring->ctx_desc_template = GEN8_CTX_VALID;
276 ring->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
277 GEN8_CTX_ADDRESSING_MODE_SHIFT;
279 ring->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
280 ring->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
282 /* TODO: WaDisableLiteRestore when we start using semaphore
283 * signalling between Command Streamers */
284 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
286 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
287 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
288 if (ring->disable_lite_restore_wa)
289 ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
293 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
294 * descriptor for a pinned context
296 * @ctx: Context to work on
297 * @ring: Engine the descriptor will be used with
299 * The context descriptor encodes various attributes of a context,
300 * including its GTT address and some flags. Because it's fairly
301 * expensive to calculate, we'll just do it once and cache the result,
302 * which remains valid until the context is unpinned.
304 * This is what a descriptor looks like, from LSB to MSB:
305 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
306 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
307 * bits 32-51: ctx ID, a globally unique tag (the LRCA again!)
308 * bits 52-63: reserved, may encode the engine ID (for GuC)
311 intel_lr_context_descriptor_update(struct intel_context *ctx,
312 struct intel_engine_cs *ring)
316 lrca = ctx->engine[ring->id].lrc_vma->node.start +
317 LRC_PPHWSP_PN * PAGE_SIZE;
319 desc = ring->ctx_desc_template; /* bits 0-11 */
320 desc |= lrca; /* bits 12-31 */
321 desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */
323 ctx->engine[ring->id].lrc_desc = desc;
326 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
327 struct intel_engine_cs *ring)
329 return ctx->engine[ring->id].lrc_desc;
333 * intel_execlists_ctx_id() - get the Execlists Context ID
334 * @ctx: Context to get the ID for
335 * @ring: Engine to get the ID for
337 * Do not confuse with ctx->id! Unfortunately we have a name overload
338 * here: the old context ID we pass to userspace as a handler so that
339 * they can refer to a context, and the new context ID we pass to the
340 * ELSP so that the GPU can inform us of the context status via
343 * The context ID is a portion of the context descriptor, so we can
344 * just extract the required part from the cached descriptor.
346 * Return: 20-bits globally unique context ID.
348 u32 intel_execlists_ctx_id(struct intel_context *ctx,
349 struct intel_engine_cs *ring)
351 return intel_lr_context_descriptor(ctx, ring) >> GEN8_CTX_ID_SHIFT;
354 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
355 struct drm_i915_gem_request *rq1)
358 struct intel_engine_cs *ring = rq0->ring;
359 struct drm_device *dev = ring->dev;
360 struct drm_i915_private *dev_priv = dev->dev_private;
364 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring);
365 rq1->elsp_submitted++;
370 desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring);
371 rq0->elsp_submitted++;
373 /* You must always write both descriptors in the order below. */
374 spin_lock(&dev_priv->uncore.lock);
375 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
376 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
377 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
379 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
380 /* The context is automatically loaded after the following */
381 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
383 /* ELSP is a wo register, use another nearby reg for posting */
384 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
385 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
386 spin_unlock(&dev_priv->uncore.lock);
389 static int execlists_update_context(struct drm_i915_gem_request *rq)
391 struct intel_engine_cs *ring = rq->ring;
392 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
393 uint32_t *reg_state = rq->ctx->engine[ring->id].lrc_reg_state;
395 reg_state[CTX_RING_TAIL+1] = rq->tail;
396 reg_state[CTX_RING_BUFFER_START+1] = rq->ringbuf->vma->node.start;
398 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
399 /* True 32b PPGTT with dynamic page allocation: update PDP
400 * registers and point the unallocated PDPs to scratch page.
401 * PML4 is allocated during ppgtt init, so this is not needed
404 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
405 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
406 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
407 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
413 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
414 struct drm_i915_gem_request *rq1)
416 execlists_update_context(rq0);
419 execlists_update_context(rq1);
421 execlists_elsp_write(rq0, rq1);
424 static void execlists_context_unqueue(struct intel_engine_cs *ring)
426 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
427 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
429 assert_spin_locked(&ring->execlist_lock);
432 * If irqs are not active generate a warning as batches that finish
433 * without the irqs may get lost and a GPU Hang may occur.
435 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
437 if (list_empty(&ring->execlist_queue))
440 /* Try to read in pairs */
441 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
445 } else if (req0->ctx == cursor->ctx) {
446 /* Same ctx: ignore first request, as second request
447 * will update tail past first request's workload */
448 cursor->elsp_submitted = req0->elsp_submitted;
449 list_move_tail(&req0->execlist_link,
450 &ring->execlist_retired_req_list);
458 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
460 * WaIdleLiteRestore: make sure we never cause a lite
461 * restore with HEAD==TAIL
463 if (req0->elsp_submitted) {
465 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
466 * as we resubmit the request. See gen8_emit_request()
467 * for where we prepare the padding after the end of the
470 struct intel_ringbuffer *ringbuf;
472 ringbuf = req0->ctx->engine[ring->id].ringbuf;
474 req0->tail &= ringbuf->size - 1;
478 WARN_ON(req1 && req1->elsp_submitted);
480 execlists_submit_requests(req0, req1);
483 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
486 struct drm_i915_gem_request *head_req;
488 assert_spin_locked(&ring->execlist_lock);
490 head_req = list_first_entry_or_null(&ring->execlist_queue,
491 struct drm_i915_gem_request,
494 if (head_req != NULL) {
495 if (intel_execlists_ctx_id(head_req->ctx, ring) == request_id) {
496 WARN(head_req->elsp_submitted == 0,
497 "Never submitted head request\n");
499 if (--head_req->elsp_submitted <= 0) {
500 list_move_tail(&head_req->execlist_link,
501 &ring->execlist_retired_req_list);
510 static void get_context_status(struct intel_engine_cs *ring,
512 u32 *status, u32 *context_id)
514 struct drm_i915_private *dev_priv = ring->dev->dev_private;
516 if (WARN_ON(read_pointer >= GEN8_CSB_ENTRIES))
519 *status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer));
520 *context_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer));
524 * intel_lrc_irq_handler() - handle Context Switch interrupts
525 * @ring: Engine Command Streamer to handle.
527 * Check the unread Context Status Buffers and manage the submission of new
528 * contexts to the ELSP accordingly.
530 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
532 struct drm_i915_private *dev_priv = ring->dev->dev_private;
538 u32 submit_contexts = 0;
540 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
542 read_pointer = ring->next_context_status_buffer;
543 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
544 if (read_pointer > write_pointer)
545 write_pointer += GEN8_CSB_ENTRIES;
547 spin_lock(&ring->execlist_lock);
549 while (read_pointer < write_pointer) {
551 get_context_status(ring, ++read_pointer % GEN8_CSB_ENTRIES,
552 &status, &status_id);
554 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
557 if (status & GEN8_CTX_STATUS_PREEMPTED) {
558 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
559 if (execlists_check_remove_request(ring, status_id))
560 WARN(1, "Lite Restored request removed from queue\n");
562 WARN(1, "Preemption without Lite Restore\n");
565 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
566 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
567 if (execlists_check_remove_request(ring, status_id))
572 if (ring->disable_lite_restore_wa) {
573 /* Prevent a ctx to preempt itself */
574 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) &&
575 (submit_contexts != 0))
576 execlists_context_unqueue(ring);
577 } else if (submit_contexts != 0) {
578 execlists_context_unqueue(ring);
581 spin_unlock(&ring->execlist_lock);
583 if (unlikely(submit_contexts > 2))
584 DRM_ERROR("More than two context complete events?\n");
586 ring->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
588 /* Update the read pointer to the old write pointer. Manual ringbuffer
589 * management ftw </sarcasm> */
590 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
591 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
592 ring->next_context_status_buffer << 8));
595 static int execlists_context_queue(struct drm_i915_gem_request *request)
597 struct intel_engine_cs *ring = request->ring;
598 struct drm_i915_gem_request *cursor;
599 int num_elements = 0;
601 if (request->ctx != ring->default_context)
602 intel_lr_context_pin(request);
604 i915_gem_request_reference(request);
606 spin_lock_irq(&ring->execlist_lock);
608 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
609 if (++num_elements > 2)
612 if (num_elements > 2) {
613 struct drm_i915_gem_request *tail_req;
615 tail_req = list_last_entry(&ring->execlist_queue,
616 struct drm_i915_gem_request,
619 if (request->ctx == tail_req->ctx) {
620 WARN(tail_req->elsp_submitted != 0,
621 "More than 2 already-submitted reqs queued\n");
622 list_move_tail(&tail_req->execlist_link,
623 &ring->execlist_retired_req_list);
627 list_add_tail(&request->execlist_link, &ring->execlist_queue);
628 if (num_elements == 0)
629 execlists_context_unqueue(ring);
631 spin_unlock_irq(&ring->execlist_lock);
636 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
638 struct intel_engine_cs *ring = req->ring;
639 uint32_t flush_domains;
643 if (ring->gpu_caches_dirty)
644 flush_domains = I915_GEM_GPU_DOMAINS;
646 ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
650 ring->gpu_caches_dirty = false;
654 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
655 struct list_head *vmas)
657 const unsigned other_rings = ~intel_ring_flag(req->ring);
658 struct i915_vma *vma;
659 uint32_t flush_domains = 0;
660 bool flush_chipset = false;
663 list_for_each_entry(vma, vmas, exec_list) {
664 struct drm_i915_gem_object *obj = vma->obj;
666 if (obj->active & other_rings) {
667 ret = i915_gem_object_sync(obj, req->ring, &req);
672 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
673 flush_chipset |= i915_gem_clflush_object(obj, false);
675 flush_domains |= obj->base.write_domain;
678 if (flush_domains & I915_GEM_DOMAIN_GTT)
681 /* Unconditionally invalidate gpu caches and ensure that we do flush
682 * any residual writes from the previous batch.
684 return logical_ring_invalidate_all_caches(req);
687 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
691 request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
693 if (request->ctx != request->ring->default_context) {
694 ret = intel_lr_context_pin(request);
699 if (i915.enable_guc_submission) {
701 * Check that the GuC has space for the request before
702 * going any further, as the i915_add_request() call
703 * later on mustn't fail ...
705 struct intel_guc *guc = &request->i915->guc;
707 ret = i915_guc_wq_check_space(guc->execbuf_client);
715 static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
718 struct intel_ringbuffer *ringbuf = req->ringbuf;
719 struct intel_engine_cs *ring = req->ring;
720 struct drm_i915_gem_request *target;
724 if (intel_ring_space(ringbuf) >= bytes)
727 /* The whole point of reserving space is to not wait! */
728 WARN_ON(ringbuf->reserved_in_use);
730 list_for_each_entry(target, &ring->request_list, list) {
732 * The request queue is per-engine, so can contain requests
733 * from multiple ringbuffers. Here, we must ignore any that
734 * aren't from the ringbuffer we're considering.
736 if (target->ringbuf != ringbuf)
739 /* Would completion of this request free enough space? */
740 space = __intel_ring_space(target->postfix, ringbuf->tail,
746 if (WARN_ON(&target->list == &ring->request_list))
749 ret = i915_wait_request(target);
753 ringbuf->space = space;
758 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
759 * @request: Request to advance the logical ringbuffer of.
761 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
762 * really happens during submission is that the context and current tail will be placed
763 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
764 * point, the tail *inside* the context is updated and the ELSP written to.
767 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
769 struct intel_engine_cs *ring = request->ring;
770 struct drm_i915_private *dev_priv = request->i915;
772 intel_logical_ring_advance(request->ringbuf);
774 request->tail = request->ringbuf->tail;
776 if (intel_ring_stopped(ring))
779 if (dev_priv->guc.execbuf_client)
780 i915_guc_submit(dev_priv->guc.execbuf_client, request);
782 execlists_context_queue(request);
785 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
787 uint32_t __iomem *virt;
788 int rem = ringbuf->size - ringbuf->tail;
790 virt = ringbuf->virtual_start + ringbuf->tail;
793 iowrite32(MI_NOOP, virt++);
796 intel_ring_update_space(ringbuf);
799 static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
801 struct intel_ringbuffer *ringbuf = req->ringbuf;
802 int remain_usable = ringbuf->effective_size - ringbuf->tail;
803 int remain_actual = ringbuf->size - ringbuf->tail;
804 int ret, total_bytes, wait_bytes = 0;
805 bool need_wrap = false;
807 if (ringbuf->reserved_in_use)
810 total_bytes = bytes + ringbuf->reserved_size;
812 if (unlikely(bytes > remain_usable)) {
814 * Not enough space for the basic request. So need to flush
815 * out the remainder and then wait for base + reserved.
817 wait_bytes = remain_actual + total_bytes;
820 if (unlikely(total_bytes > remain_usable)) {
822 * The base request will fit but the reserved space
823 * falls off the end. So only need to to wait for the
824 * reserved size after flushing out the remainder.
826 wait_bytes = remain_actual + ringbuf->reserved_size;
828 } else if (total_bytes > ringbuf->space) {
829 /* No wrapping required, just waiting. */
830 wait_bytes = total_bytes;
835 ret = logical_ring_wait_for_space(req, wait_bytes);
840 __wrap_ring_buffer(ringbuf);
847 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
849 * @req: The request to start some new work for
850 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
852 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
853 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
854 * and also preallocates a request (every workload submission is still mediated through
855 * requests, same as it did with legacy ringbuffer submission).
857 * Return: non-zero if the ringbuffer is not ready to be written to.
859 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
861 struct drm_i915_private *dev_priv;
864 WARN_ON(req == NULL);
865 dev_priv = req->ring->dev->dev_private;
867 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
868 dev_priv->mm.interruptible);
872 ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
876 req->ringbuf->space -= num_dwords * sizeof(uint32_t);
880 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
883 * The first call merely notes the reserve request and is common for
884 * all back ends. The subsequent localised _begin() call actually
885 * ensures that the reservation is available. Without the begin, if
886 * the request creator immediately submitted the request without
887 * adding any commands to it then there might not actually be
888 * sufficient room for the submission commands.
890 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
892 return intel_logical_ring_begin(request, 0);
896 * execlists_submission() - submit a batchbuffer for execution, Execlists style
899 * @ring: Engine Command Streamer to submit to.
900 * @ctx: Context to employ for this submission.
901 * @args: execbuffer call arguments.
902 * @vmas: list of vmas.
903 * @batch_obj: the batchbuffer to submit.
904 * @exec_start: batchbuffer start virtual address pointer.
905 * @dispatch_flags: translated execbuffer call flags.
907 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
908 * away the submission details of the execbuffer ioctl call.
910 * Return: non-zero if the submission fails.
912 int intel_execlists_submission(struct i915_execbuffer_params *params,
913 struct drm_i915_gem_execbuffer2 *args,
914 struct list_head *vmas)
916 struct drm_device *dev = params->dev;
917 struct intel_engine_cs *ring = params->ring;
918 struct drm_i915_private *dev_priv = dev->dev_private;
919 struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
925 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
926 instp_mask = I915_EXEC_CONSTANTS_MASK;
927 switch (instp_mode) {
928 case I915_EXEC_CONSTANTS_REL_GENERAL:
929 case I915_EXEC_CONSTANTS_ABSOLUTE:
930 case I915_EXEC_CONSTANTS_REL_SURFACE:
931 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
932 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
936 if (instp_mode != dev_priv->relative_constants_mode) {
937 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
938 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
942 /* The HW changed the meaning on this bit on gen6 */
943 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
947 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
951 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
952 DRM_DEBUG("sol reset is gen7 only\n");
956 ret = execlists_move_to_gpu(params->request, vmas);
960 if (ring == &dev_priv->ring[RCS] &&
961 instp_mode != dev_priv->relative_constants_mode) {
962 ret = intel_logical_ring_begin(params->request, 4);
966 intel_logical_ring_emit(ringbuf, MI_NOOP);
967 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
968 intel_logical_ring_emit_reg(ringbuf, INSTPM);
969 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
970 intel_logical_ring_advance(ringbuf);
972 dev_priv->relative_constants_mode = instp_mode;
975 exec_start = params->batch_obj_vm_offset +
976 args->batch_start_offset;
978 ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
982 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
984 i915_gem_execbuffer_move_to_active(vmas, params->request);
985 i915_gem_execbuffer_retire_commands(params);
990 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
992 struct drm_i915_gem_request *req, *tmp;
993 struct list_head retired_list;
995 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
996 if (list_empty(&ring->execlist_retired_req_list))
999 INIT_LIST_HEAD(&retired_list);
1000 spin_lock_irq(&ring->execlist_lock);
1001 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
1002 spin_unlock_irq(&ring->execlist_lock);
1004 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
1005 struct intel_context *ctx = req->ctx;
1006 struct drm_i915_gem_object *ctx_obj =
1007 ctx->engine[ring->id].state;
1009 if (ctx_obj && (ctx != ring->default_context))
1010 intel_lr_context_unpin(req);
1011 list_del(&req->execlist_link);
1012 i915_gem_request_unreference(req);
1016 void intel_logical_ring_stop(struct intel_engine_cs *ring)
1018 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1021 if (!intel_ring_initialized(ring))
1024 ret = intel_ring_idle(ring);
1025 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
1026 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1029 /* TODO: Is this correct with Execlists enabled? */
1030 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
1031 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
1032 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
1035 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
1038 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
1040 struct intel_engine_cs *ring = req->ring;
1043 if (!ring->gpu_caches_dirty)
1046 ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1050 ring->gpu_caches_dirty = false;
1054 static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
1055 struct intel_context *ctx)
1057 struct drm_device *dev = ring->dev;
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1059 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
1060 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1061 struct page *lrc_state_page;
1064 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1066 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
1067 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
1071 lrc_state_page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
1072 if (WARN_ON(!lrc_state_page)) {
1077 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1081 ctx->engine[ring->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj);
1082 intel_lr_context_descriptor_update(ctx, ring);
1083 ctx->engine[ring->id].lrc_reg_state = kmap(lrc_state_page);
1084 ctx_obj->dirty = true;
1086 /* Invalidate GuC TLB. */
1087 if (i915.enable_guc_submission)
1088 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1093 i915_gem_object_ggtt_unpin(ctx_obj);
1098 static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
1101 struct intel_engine_cs *ring = rq->ring;
1103 if (rq->ctx->engine[ring->id].pin_count++ == 0) {
1104 ret = intel_lr_context_do_pin(ring, rq->ctx);
1106 goto reset_pin_count;
1111 rq->ctx->engine[ring->id].pin_count = 0;
1115 void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
1117 struct intel_engine_cs *ring = rq->ring;
1118 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1119 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1121 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1126 if (--rq->ctx->engine[ring->id].pin_count == 0) {
1127 kunmap(kmap_to_page(rq->ctx->engine[ring->id].lrc_reg_state));
1128 intel_unpin_ringbuffer_obj(ringbuf);
1129 i915_gem_object_ggtt_unpin(ctx_obj);
1130 rq->ctx->engine[ring->id].lrc_vma = NULL;
1131 rq->ctx->engine[ring->id].lrc_desc = 0;
1132 rq->ctx->engine[ring->id].lrc_reg_state = NULL;
1136 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1139 struct intel_engine_cs *ring = req->ring;
1140 struct intel_ringbuffer *ringbuf = req->ringbuf;
1141 struct drm_device *dev = ring->dev;
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 struct i915_workarounds *w = &dev_priv->workarounds;
1148 ring->gpu_caches_dirty = true;
1149 ret = logical_ring_flush_all_caches(req);
1153 ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1157 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1158 for (i = 0; i < w->count; i++) {
1159 intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
1160 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1162 intel_logical_ring_emit(ringbuf, MI_NOOP);
1164 intel_logical_ring_advance(ringbuf);
1166 ring->gpu_caches_dirty = true;
1167 ret = logical_ring_flush_all_caches(req);
1174 #define wa_ctx_emit(batch, index, cmd) \
1176 int __index = (index)++; \
1177 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1180 batch[__index] = (cmd); \
1183 #define wa_ctx_emit_reg(batch, index, reg) \
1184 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1187 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1188 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1189 * but there is a slight complication as this is applied in WA batch where the
1190 * values are only initialized once so we cannot take register value at the
1191 * beginning and reuse it further; hence we save its value to memory, upload a
1192 * constant value with bit21 set and then we restore it back with the saved value.
1193 * To simplify the WA, a constant value is formed by using the default value
1194 * of this register. This shouldn't be a problem because we are only modifying
1195 * it for a short period and this batch in non-premptible. We can ofcourse
1196 * use additional instructions that read the actual value of the register
1197 * at that time and set our bit of interest but it makes the WA complicated.
1199 * This WA is also required for Gen9 so extracting as a function avoids
1202 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
1203 uint32_t *const batch,
1206 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1209 * WaDisableLSQCROPERFforOCL:skl
1210 * This WA is implemented in skl_init_clock_gating() but since
1211 * this batch updates GEN8_L3SQCREG4 with default value we need to
1212 * set this bit here to retain the WA during flush.
1214 if (IS_SKL_REVID(ring->dev, 0, SKL_REVID_E0))
1215 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1217 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1218 MI_SRM_LRM_GLOBAL_GTT));
1219 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1220 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1221 wa_ctx_emit(batch, index, 0);
1223 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1224 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1225 wa_ctx_emit(batch, index, l3sqc4_flush);
1227 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1228 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1229 PIPE_CONTROL_DC_FLUSH_ENABLE));
1230 wa_ctx_emit(batch, index, 0);
1231 wa_ctx_emit(batch, index, 0);
1232 wa_ctx_emit(batch, index, 0);
1233 wa_ctx_emit(batch, index, 0);
1235 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1236 MI_SRM_LRM_GLOBAL_GTT));
1237 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1238 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1239 wa_ctx_emit(batch, index, 0);
1244 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1246 uint32_t start_alignment)
1248 return wa_ctx->offset = ALIGN(offset, start_alignment);
1251 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1253 uint32_t size_alignment)
1255 wa_ctx->size = offset - wa_ctx->offset;
1257 WARN(wa_ctx->size % size_alignment,
1258 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1259 wa_ctx->size, size_alignment);
1264 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1266 * @ring: only applicable for RCS
1267 * @wa_ctx: structure representing wa_ctx
1268 * offset: specifies start of the batch, should be cache-aligned. This is updated
1269 * with the offset value received as input.
1270 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1271 * @batch: page in which WA are loaded
1272 * @offset: This field specifies the start of the batch, it should be
1273 * cache-aligned otherwise it is adjusted accordingly.
1274 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1275 * initialized at the beginning and shared across all contexts but this field
1276 * helps us to have multiple batches at different offsets and select them based
1277 * on a criteria. At the moment this batch always start at the beginning of the page
1278 * and at this point we don't have multiple wa_ctx batch buffers.
1280 * The number of WA applied are not known at the beginning; we use this field
1281 * to return the no of DWORDS written.
1283 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1284 * so it adds NOOPs as padding to make it cacheline aligned.
1285 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1286 * makes a complete batch buffer.
1288 * Return: non-zero if we exceed the PAGE_SIZE limit.
1291 static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
1292 struct i915_wa_ctx_bb *wa_ctx,
1293 uint32_t *const batch,
1296 uint32_t scratch_addr;
1297 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1299 /* WaDisableCtxRestoreArbitration:bdw,chv */
1300 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1302 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1303 if (IS_BROADWELL(ring->dev)) {
1304 int rc = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1310 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1311 /* Actual scratch location is at 128 bytes offset */
1312 scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;
1314 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1315 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1316 PIPE_CONTROL_GLOBAL_GTT_IVB |
1317 PIPE_CONTROL_CS_STALL |
1318 PIPE_CONTROL_QW_WRITE));
1319 wa_ctx_emit(batch, index, scratch_addr);
1320 wa_ctx_emit(batch, index, 0);
1321 wa_ctx_emit(batch, index, 0);
1322 wa_ctx_emit(batch, index, 0);
1324 /* Pad to end of cacheline */
1325 while (index % CACHELINE_DWORDS)
1326 wa_ctx_emit(batch, index, MI_NOOP);
1329 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1330 * execution depends on the length specified in terms of cache lines
1331 * in the register CTX_RCS_INDIRECT_CTX
1334 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1338 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1340 * @ring: only applicable for RCS
1341 * @wa_ctx: structure representing wa_ctx
1342 * offset: specifies start of the batch, should be cache-aligned.
1343 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1344 * @batch: page in which WA are loaded
1345 * @offset: This field specifies the start of this batch.
1346 * This batch is started immediately after indirect_ctx batch. Since we ensure
1347 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1349 * The number of DWORDS written are returned using this field.
1351 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1352 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1354 static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
1355 struct i915_wa_ctx_bb *wa_ctx,
1356 uint32_t *const batch,
1359 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1361 /* WaDisableCtxRestoreArbitration:bdw,chv */
1362 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1364 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1366 return wa_ctx_end(wa_ctx, *offset = index, 1);
1369 static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
1370 struct i915_wa_ctx_bb *wa_ctx,
1371 uint32_t *const batch,
1375 struct drm_device *dev = ring->dev;
1376 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1378 /* WaDisableCtxRestoreArbitration:skl,bxt */
1379 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1380 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1381 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1383 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1384 ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1389 /* Pad to end of cacheline */
1390 while (index % CACHELINE_DWORDS)
1391 wa_ctx_emit(batch, index, MI_NOOP);
1393 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1396 static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
1397 struct i915_wa_ctx_bb *wa_ctx,
1398 uint32_t *const batch,
1401 struct drm_device *dev = ring->dev;
1402 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1404 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1405 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
1406 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1407 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1408 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1409 wa_ctx_emit(batch, index,
1410 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1411 wa_ctx_emit(batch, index, MI_NOOP);
1414 /* WaDisableCtxRestoreArbitration:skl,bxt */
1415 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1416 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1417 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1419 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1421 return wa_ctx_end(wa_ctx, *offset = index, 1);
1424 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
1428 ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
1429 if (!ring->wa_ctx.obj) {
1430 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1434 ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
1436 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1438 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1445 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
1447 if (ring->wa_ctx.obj) {
1448 i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
1449 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1450 ring->wa_ctx.obj = NULL;
1454 static int intel_init_workaround_bb(struct intel_engine_cs *ring)
1460 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
1462 WARN_ON(ring->id != RCS);
1464 /* update this when WA for higher Gen are added */
1465 if (INTEL_INFO(ring->dev)->gen > 9) {
1466 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1467 INTEL_INFO(ring->dev)->gen);
1471 /* some WA perform writes to scratch page, ensure it is valid */
1472 if (ring->scratch.obj == NULL) {
1473 DRM_ERROR("scratch page not allocated for %s\n", ring->name);
1477 ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
1479 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1483 page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1484 batch = kmap_atomic(page);
1487 if (INTEL_INFO(ring->dev)->gen == 8) {
1488 ret = gen8_init_indirectctx_bb(ring,
1489 &wa_ctx->indirect_ctx,
1495 ret = gen8_init_perctx_bb(ring,
1501 } else if (INTEL_INFO(ring->dev)->gen == 9) {
1502 ret = gen9_init_indirectctx_bb(ring,
1503 &wa_ctx->indirect_ctx,
1509 ret = gen9_init_perctx_bb(ring,
1518 kunmap_atomic(batch);
1520 lrc_destroy_wa_ctx_obj(ring);
1525 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1527 struct drm_device *dev = ring->dev;
1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529 u8 next_context_status_buffer_hw;
1531 lrc_setup_hardware_status_page(ring,
1532 ring->default_context->engine[ring->id].state);
1534 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1535 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1537 I915_WRITE(RING_MODE_GEN7(ring),
1538 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1539 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1540 POSTING_READ(RING_MODE_GEN7(ring));
1543 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1544 * zero, we need to read the write pointer from hardware and use its
1545 * value because "this register is power context save restored".
1546 * Effectively, these states have been observed:
1548 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1549 * BDW | CSB regs not reset | CSB regs reset |
1550 * CHT | CSB regs not reset | CSB regs not reset |
1554 next_context_status_buffer_hw =
1555 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(ring)));
1558 * When the CSB registers are reset (also after power-up / gpu reset),
1559 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1560 * this special case, so the first element read is CSB[0].
1562 if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
1563 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);
1565 ring->next_context_status_buffer = next_context_status_buffer_hw;
1566 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1568 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1573 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1575 struct drm_device *dev = ring->dev;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1579 ret = gen8_init_common_ring(ring);
1583 /* We need to disable the AsyncFlip performance optimisations in order
1584 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1585 * programmed to '1' on all products.
1587 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1589 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1591 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1593 return init_workarounds_ring(ring);
1596 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1600 ret = gen8_init_common_ring(ring);
1604 return init_workarounds_ring(ring);
1607 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1609 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1610 struct intel_engine_cs *ring = req->ring;
1611 struct intel_ringbuffer *ringbuf = req->ringbuf;
1612 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1615 ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
1619 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1620 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1621 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1623 intel_logical_ring_emit_reg(ringbuf, GEN8_RING_PDP_UDW(ring, i));
1624 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1625 intel_logical_ring_emit_reg(ringbuf, GEN8_RING_PDP_LDW(ring, i));
1626 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1629 intel_logical_ring_emit(ringbuf, MI_NOOP);
1630 intel_logical_ring_advance(ringbuf);
1635 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1636 u64 offset, unsigned dispatch_flags)
1638 struct intel_ringbuffer *ringbuf = req->ringbuf;
1639 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1642 /* Don't rely in hw updating PDPs, specially in lite-restore.
1643 * Ideally, we should set Force PD Restore in ctx descriptor,
1644 * but we can't. Force Restore would be a second option, but
1645 * it is unsafe in case of lite-restore (because the ctx is
1646 * not idle). PML4 is allocated during ppgtt init so this is
1647 * not needed in 48-bit.*/
1648 if (req->ctx->ppgtt &&
1649 (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
1650 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1651 !intel_vgpu_active(req->i915->dev)) {
1652 ret = intel_logical_ring_emit_pdps(req);
1657 req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
1660 ret = intel_logical_ring_begin(req, 4);
1664 /* FIXME(BDW): Address space and security selectors. */
1665 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1667 (dispatch_flags & I915_DISPATCH_RS ?
1668 MI_BATCH_RESOURCE_STREAMER : 0));
1669 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1670 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1671 intel_logical_ring_emit(ringbuf, MI_NOOP);
1672 intel_logical_ring_advance(ringbuf);
1677 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1679 struct drm_device *dev = ring->dev;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 unsigned long flags;
1683 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1686 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1687 if (ring->irq_refcount++ == 0) {
1688 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1689 POSTING_READ(RING_IMR(ring->mmio_base));
1691 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1696 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1698 struct drm_device *dev = ring->dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 unsigned long flags;
1702 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1703 if (--ring->irq_refcount == 0) {
1704 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1705 POSTING_READ(RING_IMR(ring->mmio_base));
1707 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1710 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1711 u32 invalidate_domains,
1714 struct intel_ringbuffer *ringbuf = request->ringbuf;
1715 struct intel_engine_cs *ring = ringbuf->ring;
1716 struct drm_device *dev = ring->dev;
1717 struct drm_i915_private *dev_priv = dev->dev_private;
1721 ret = intel_logical_ring_begin(request, 4);
1725 cmd = MI_FLUSH_DW + 1;
1727 /* We always require a command barrier so that subsequent
1728 * commands, such as breadcrumb interrupts, are strictly ordered
1729 * wrt the contents of the write cache being flushed to memory
1730 * (and thus being coherent from the CPU).
1732 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1734 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1735 cmd |= MI_INVALIDATE_TLB;
1736 if (ring == &dev_priv->ring[VCS])
1737 cmd |= MI_INVALIDATE_BSD;
1740 intel_logical_ring_emit(ringbuf, cmd);
1741 intel_logical_ring_emit(ringbuf,
1742 I915_GEM_HWS_SCRATCH_ADDR |
1743 MI_FLUSH_DW_USE_GTT);
1744 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1745 intel_logical_ring_emit(ringbuf, 0); /* value */
1746 intel_logical_ring_advance(ringbuf);
1751 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1752 u32 invalidate_domains,
1755 struct intel_ringbuffer *ringbuf = request->ringbuf;
1756 struct intel_engine_cs *ring = ringbuf->ring;
1757 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1758 bool vf_flush_wa = false;
1762 flags |= PIPE_CONTROL_CS_STALL;
1764 if (flush_domains) {
1765 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1766 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1767 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1768 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1771 if (invalidate_domains) {
1772 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1773 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1774 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1775 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1776 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1777 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1778 flags |= PIPE_CONTROL_QW_WRITE;
1779 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1782 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1785 if (IS_GEN9(ring->dev))
1789 ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1794 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1795 intel_logical_ring_emit(ringbuf, 0);
1796 intel_logical_ring_emit(ringbuf, 0);
1797 intel_logical_ring_emit(ringbuf, 0);
1798 intel_logical_ring_emit(ringbuf, 0);
1799 intel_logical_ring_emit(ringbuf, 0);
1802 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1803 intel_logical_ring_emit(ringbuf, flags);
1804 intel_logical_ring_emit(ringbuf, scratch_addr);
1805 intel_logical_ring_emit(ringbuf, 0);
1806 intel_logical_ring_emit(ringbuf, 0);
1807 intel_logical_ring_emit(ringbuf, 0);
1808 intel_logical_ring_advance(ringbuf);
1813 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1815 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1818 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1820 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1823 static u32 bxt_a_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1827 * On BXT A steppings there is a HW coherency issue whereby the
1828 * MI_STORE_DATA_IMM storing the completed request's seqno
1829 * occasionally doesn't invalidate the CPU cache. Work around this by
1830 * clflushing the corresponding cacheline whenever the caller wants
1831 * the coherency to be guaranteed. Note that this cacheline is known
1832 * to be clean at this point, since we only write it in
1833 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1834 * this clflush in practice becomes an invalidate operation.
1837 if (!lazy_coherency)
1838 intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
1840 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1843 static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1845 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1847 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1848 intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
1851 static int gen8_emit_request(struct drm_i915_gem_request *request)
1853 struct intel_ringbuffer *ringbuf = request->ringbuf;
1854 struct intel_engine_cs *ring = ringbuf->ring;
1859 * Reserve space for 2 NOOPs at the end of each request to be
1860 * used as a workaround for not being allowed to do lite
1861 * restore with HEAD==TAIL (WaIdleLiteRestore).
1863 ret = intel_logical_ring_begin(request, 8);
1867 cmd = MI_STORE_DWORD_IMM_GEN4;
1868 cmd |= MI_GLOBAL_GTT;
1870 intel_logical_ring_emit(ringbuf, cmd);
1871 intel_logical_ring_emit(ringbuf,
1872 (ring->status_page.gfx_addr +
1873 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1874 intel_logical_ring_emit(ringbuf, 0);
1875 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1876 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1877 intel_logical_ring_emit(ringbuf, MI_NOOP);
1878 intel_logical_ring_advance_and_submit(request);
1881 * Here we add two extra NOOPs as padding to avoid
1882 * lite restore of a context with HEAD==TAIL.
1884 intel_logical_ring_emit(ringbuf, MI_NOOP);
1885 intel_logical_ring_emit(ringbuf, MI_NOOP);
1886 intel_logical_ring_advance(ringbuf);
1891 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1893 struct render_state so;
1896 ret = i915_gem_render_state_prepare(req->ring, &so);
1900 if (so.rodata == NULL)
1903 ret = req->ring->emit_bb_start(req, so.ggtt_offset,
1904 I915_DISPATCH_SECURE);
1908 ret = req->ring->emit_bb_start(req,
1909 (so.ggtt_offset + so.aux_batch_offset),
1910 I915_DISPATCH_SECURE);
1914 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1917 i915_gem_render_state_fini(&so);
1921 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1925 ret = intel_logical_ring_workarounds_emit(req);
1929 ret = intel_rcs_context_init_mocs(req);
1931 * Failing to program the MOCS is non-fatal.The system will not
1932 * run at peak performance. So generate an error and carry on.
1935 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1937 return intel_lr_context_render_state_init(req);
1941 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1943 * @ring: Engine Command Streamer.
1946 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1948 struct drm_i915_private *dev_priv;
1950 if (!intel_ring_initialized(ring))
1953 dev_priv = ring->dev->dev_private;
1956 intel_logical_ring_stop(ring);
1957 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1961 ring->cleanup(ring);
1963 i915_cmd_parser_fini_ring(ring);
1964 i915_gem_batch_pool_fini(&ring->batch_pool);
1966 if (ring->status_page.obj) {
1967 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1968 ring->status_page.obj = NULL;
1971 ring->disable_lite_restore_wa = false;
1972 ring->ctx_desc_template = 0;
1974 lrc_destroy_wa_ctx_obj(ring);
1979 logical_ring_default_vfuncs(struct drm_device *dev,
1980 struct intel_engine_cs *ring)
1982 /* Default vfuncs which can be overriden by each engine. */
1983 ring->init_hw = gen8_init_common_ring;
1984 ring->emit_request = gen8_emit_request;
1985 ring->emit_flush = gen8_emit_flush;
1986 ring->irq_get = gen8_logical_ring_get_irq;
1987 ring->irq_put = gen8_logical_ring_put_irq;
1988 ring->emit_bb_start = gen8_emit_bb_start;
1989 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1990 ring->get_seqno = bxt_a_get_seqno;
1991 ring->set_seqno = bxt_a_set_seqno;
1993 ring->get_seqno = gen8_get_seqno;
1994 ring->set_seqno = gen8_set_seqno;
1999 logical_ring_default_irqs(struct intel_engine_cs *ring, unsigned shift)
2001 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2002 ring->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2006 logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
2010 /* Intentionally left blank. */
2011 ring->buffer = NULL;
2014 INIT_LIST_HEAD(&ring->active_list);
2015 INIT_LIST_HEAD(&ring->request_list);
2016 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2017 init_waitqueue_head(&ring->irq_queue);
2019 INIT_LIST_HEAD(&ring->buffers);
2020 INIT_LIST_HEAD(&ring->execlist_queue);
2021 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
2022 spin_lock_init(&ring->execlist_lock);
2024 logical_ring_init_platform_invariants(ring);
2026 ret = i915_cmd_parser_init_ring(ring);
2030 ret = intel_lr_context_deferred_alloc(ring->default_context, ring);
2034 /* As this is the default context, always pin it */
2035 ret = intel_lr_context_do_pin(ring, ring->default_context);
2038 "Failed to pin and map ringbuffer %s: %d\n",
2046 intel_logical_ring_cleanup(ring);
2050 static int logical_render_ring_init(struct drm_device *dev)
2052 struct drm_i915_private *dev_priv = dev->dev_private;
2053 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2056 ring->name = "render ring";
2058 ring->mmio_base = RENDER_RING_BASE;
2060 logical_ring_default_irqs(ring, GEN8_RCS_IRQ_SHIFT);
2061 if (HAS_L3_DPF(dev))
2062 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2064 logical_ring_default_vfuncs(dev, ring);
2066 /* Override some for render ring. */
2067 if (INTEL_INFO(dev)->gen >= 9)
2068 ring->init_hw = gen9_init_render_ring;
2070 ring->init_hw = gen8_init_render_ring;
2071 ring->init_context = gen8_init_rcs_context;
2072 ring->cleanup = intel_fini_pipe_control;
2073 ring->emit_flush = gen8_emit_flush_render;
2077 ret = intel_init_pipe_control(ring);
2081 ret = intel_init_workaround_bb(ring);
2084 * We continue even if we fail to initialize WA batch
2085 * because we only expect rare glitches but nothing
2086 * critical to prevent us from using GPU
2088 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2092 ret = logical_ring_init(dev, ring);
2094 lrc_destroy_wa_ctx_obj(ring);
2100 static int logical_bsd_ring_init(struct drm_device *dev)
2102 struct drm_i915_private *dev_priv = dev->dev_private;
2103 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2105 ring->name = "bsd ring";
2107 ring->mmio_base = GEN6_BSD_RING_BASE;
2109 logical_ring_default_irqs(ring, GEN8_VCS1_IRQ_SHIFT);
2110 logical_ring_default_vfuncs(dev, ring);
2112 return logical_ring_init(dev, ring);
2115 static int logical_bsd2_ring_init(struct drm_device *dev)
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2120 ring->name = "bsd2 ring";
2122 ring->mmio_base = GEN8_BSD2_RING_BASE;
2124 logical_ring_default_irqs(ring, GEN8_VCS2_IRQ_SHIFT);
2125 logical_ring_default_vfuncs(dev, ring);
2127 return logical_ring_init(dev, ring);
2130 static int logical_blt_ring_init(struct drm_device *dev)
2132 struct drm_i915_private *dev_priv = dev->dev_private;
2133 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2135 ring->name = "blitter ring";
2137 ring->mmio_base = BLT_RING_BASE;
2139 logical_ring_default_irqs(ring, GEN8_BCS_IRQ_SHIFT);
2140 logical_ring_default_vfuncs(dev, ring);
2142 return logical_ring_init(dev, ring);
2145 static int logical_vebox_ring_init(struct drm_device *dev)
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2148 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2150 ring->name = "video enhancement ring";
2152 ring->mmio_base = VEBOX_RING_BASE;
2154 logical_ring_default_irqs(ring, GEN8_VECS_IRQ_SHIFT);
2155 logical_ring_default_vfuncs(dev, ring);
2157 return logical_ring_init(dev, ring);
2161 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2164 * This function inits the engines for an Execlists submission style (the equivalent in the
2165 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2166 * those engines that are present in the hardware.
2168 * Return: non-zero if the initialization failed.
2170 int intel_logical_rings_init(struct drm_device *dev)
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2175 ret = logical_render_ring_init(dev);
2180 ret = logical_bsd_ring_init(dev);
2182 goto cleanup_render_ring;
2186 ret = logical_blt_ring_init(dev);
2188 goto cleanup_bsd_ring;
2191 if (HAS_VEBOX(dev)) {
2192 ret = logical_vebox_ring_init(dev);
2194 goto cleanup_blt_ring;
2197 if (HAS_BSD2(dev)) {
2198 ret = logical_bsd2_ring_init(dev);
2200 goto cleanup_vebox_ring;
2206 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
2208 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
2210 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
2211 cleanup_render_ring:
2212 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
2218 make_rpcs(struct drm_device *dev)
2223 * No explicit RPCS request is needed to ensure full
2224 * slice/subslice/EU enablement prior to Gen9.
2226 if (INTEL_INFO(dev)->gen < 9)
2230 * Starting in Gen9, render power gating can leave
2231 * slice/subslice/EU in a partially enabled state. We
2232 * must make an explicit request through RPCS for full
2235 if (INTEL_INFO(dev)->has_slice_pg) {
2236 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2237 rpcs |= INTEL_INFO(dev)->slice_total <<
2238 GEN8_RPCS_S_CNT_SHIFT;
2239 rpcs |= GEN8_RPCS_ENABLE;
2242 if (INTEL_INFO(dev)->has_subslice_pg) {
2243 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2244 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2245 GEN8_RPCS_SS_CNT_SHIFT;
2246 rpcs |= GEN8_RPCS_ENABLE;
2249 if (INTEL_INFO(dev)->has_eu_pg) {
2250 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2251 GEN8_RPCS_EU_MIN_SHIFT;
2252 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2253 GEN8_RPCS_EU_MAX_SHIFT;
2254 rpcs |= GEN8_RPCS_ENABLE;
2261 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
2262 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
2264 struct drm_device *dev = ring->dev;
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2268 uint32_t *reg_state;
2272 ppgtt = dev_priv->mm.aliasing_ppgtt;
2274 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2276 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2280 ret = i915_gem_object_get_pages(ctx_obj);
2282 DRM_DEBUG_DRIVER("Could not get object pages\n");
2286 i915_gem_object_pin_pages(ctx_obj);
2288 /* The second page of the context object contains some fields which must
2289 * be set up prior to the first execution. */
2290 page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2291 reg_state = kmap_atomic(page);
2293 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2294 * commands followed by (reg, value) pairs. The values we are setting here are
2295 * only for the first context restore: on a subsequent save, the GPU will
2296 * recreate this batchbuffer with new values (including all the missing
2297 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2298 reg_state[CTX_LRI_HEADER_0] =
2299 MI_LOAD_REGISTER_IMM(ring->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
2300 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(ring),
2301 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2302 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2303 CTX_CTRL_RS_CTX_ENABLE));
2304 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(ring->mmio_base), 0);
2305 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(ring->mmio_base), 0);
2306 /* Ring buffer start address is not known until the buffer is pinned.
2307 * It is written to the context image in execlists_update_context()
2309 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, RING_START(ring->mmio_base), 0);
2310 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, RING_CTL(ring->mmio_base),
2311 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2312 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, RING_BBADDR_UDW(ring->mmio_base), 0);
2313 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, RING_BBADDR(ring->mmio_base), 0);
2314 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, RING_BBSTATE(ring->mmio_base),
2316 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(ring->mmio_base), 0);
2317 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(ring->mmio_base), 0);
2318 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, RING_SBBSTATE(ring->mmio_base), 0);
2319 if (ring->id == RCS) {
2320 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(ring->mmio_base), 0);
2321 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(ring->mmio_base), 0);
2322 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, RING_INDIRECT_CTX_OFFSET(ring->mmio_base), 0);
2323 if (ring->wa_ctx.obj) {
2324 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
2325 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2327 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2328 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2329 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2331 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2332 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
2334 reg_state[CTX_BB_PER_CTX_PTR+1] =
2335 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2339 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2340 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(ring->mmio_base), 0);
2341 /* PDP values well be assigned later if needed */
2342 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(ring, 3), 0);
2343 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(ring, 3), 0);
2344 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(ring, 2), 0);
2345 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(ring, 2), 0);
2346 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(ring, 1), 0);
2347 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(ring, 1), 0);
2348 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(ring, 0), 0);
2349 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(ring, 0), 0);
2351 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2352 /* 64b PPGTT (48bit canonical)
2353 * PDP0_DESCRIPTOR contains the base address to PML4 and
2354 * other PDP Descriptors are ignored.
2356 ASSIGN_CTX_PML4(ppgtt, reg_state);
2359 * PDP*_DESCRIPTOR contains the base address of space supported.
2360 * With dynamic page allocation, PDPs may not be allocated at
2361 * this point. Point the unallocated PDPs to the scratch page
2363 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
2364 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
2365 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
2366 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
2369 if (ring->id == RCS) {
2370 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2371 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2375 kunmap_atomic(reg_state);
2376 i915_gem_object_unpin_pages(ctx_obj);
2382 * intel_lr_context_free() - free the LRC specific bits of a context
2383 * @ctx: the LR context to free.
2385 * The real context freeing is done in i915_gem_context_free: this only
2386 * takes care of the bits that are LRC related: the per-engine backing
2387 * objects and the logical ringbuffer.
2389 void intel_lr_context_free(struct intel_context *ctx)
2393 for (i = 0; i < I915_NUM_RINGS; i++) {
2394 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2397 struct intel_ringbuffer *ringbuf =
2398 ctx->engine[i].ringbuf;
2399 struct intel_engine_cs *ring = ringbuf->ring;
2401 if (ctx == ring->default_context) {
2402 intel_unpin_ringbuffer_obj(ringbuf);
2403 i915_gem_object_ggtt_unpin(ctx_obj);
2405 WARN_ON(ctx->engine[ring->id].pin_count);
2406 intel_ringbuffer_free(ringbuf);
2407 drm_gem_object_unreference(&ctx_obj->base);
2413 * intel_lr_context_size() - return the size of the context for an engine
2414 * @ring: which engine to find the context size for
2416 * Each engine may require a different amount of space for a context image,
2417 * so when allocating (or copying) an image, this function can be used to
2418 * find the right size for the specific engine.
2420 * Return: size (in bytes) of an engine-specific context image
2422 * Note: this size includes the HWSP, which is part of the context image
2423 * in LRC mode, but does not include the "shared data page" used with
2424 * GuC submission. The caller should account for this if using the GuC.
2426 uint32_t intel_lr_context_size(struct intel_engine_cs *ring)
2430 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
2434 if (INTEL_INFO(ring->dev)->gen >= 9)
2435 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2437 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2443 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2450 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
2451 struct drm_i915_gem_object *default_ctx_obj)
2453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2456 /* The HWSP is part of the default context object in LRC mode. */
2457 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
2458 + LRC_PPHWSP_PN * PAGE_SIZE;
2459 page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
2460 ring->status_page.page_addr = kmap(page);
2461 ring->status_page.obj = default_ctx_obj;
2463 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
2464 (u32)ring->status_page.gfx_addr);
2465 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
2469 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2470 * @ctx: LR context to create.
2471 * @ring: engine to be used with the context.
2473 * This function can be called more than once, with different engines, if we plan
2474 * to use the context with them. The context backing objects and the ringbuffers
2475 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2476 * the creation is a deferred call: it's better to make sure first that we need to use
2477 * a given ring with the context.
2479 * Return: non-zero on error.
2482 int intel_lr_context_deferred_alloc(struct intel_context *ctx,
2483 struct intel_engine_cs *ring)
2485 struct drm_device *dev = ring->dev;
2486 struct drm_i915_gem_object *ctx_obj;
2487 uint32_t context_size;
2488 struct intel_ringbuffer *ringbuf;
2491 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2492 WARN_ON(ctx->engine[ring->id].state);
2494 context_size = round_up(intel_lr_context_size(ring), 4096);
2496 /* One extra page as the sharing data between driver and GuC */
2497 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2499 ctx_obj = i915_gem_alloc_object(dev, context_size);
2501 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2505 ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE);
2506 if (IS_ERR(ringbuf)) {
2507 ret = PTR_ERR(ringbuf);
2508 goto error_deref_obj;
2511 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
2513 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2517 ctx->engine[ring->id].ringbuf = ringbuf;
2518 ctx->engine[ring->id].state = ctx_obj;
2520 if (ctx != ring->default_context && ring->init_context) {
2521 struct drm_i915_gem_request *req;
2523 ret = i915_gem_request_alloc(ring,
2526 DRM_ERROR("ring create req: %d\n",
2531 ret = ring->init_context(req);
2533 DRM_ERROR("ring init context: %d\n",
2535 i915_gem_request_cancel(req);
2538 i915_add_request_no_flush(req);
2543 intel_ringbuffer_free(ringbuf);
2545 drm_gem_object_unreference(&ctx_obj->base);
2546 ctx->engine[ring->id].ringbuf = NULL;
2547 ctx->engine[ring->id].state = NULL;
2551 void intel_lr_context_reset(struct drm_device *dev,
2552 struct intel_context *ctx)
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555 struct intel_engine_cs *ring;
2558 for_each_ring(ring, dev_priv, i) {
2559 struct drm_i915_gem_object *ctx_obj =
2560 ctx->engine[ring->id].state;
2561 struct intel_ringbuffer *ringbuf =
2562 ctx->engine[ring->id].ringbuf;
2563 uint32_t *reg_state;
2569 if (i915_gem_object_get_pages(ctx_obj)) {
2570 WARN(1, "Failed get_pages for context obj\n");
2573 page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2574 reg_state = kmap_atomic(page);
2576 reg_state[CTX_RING_HEAD+1] = 0;
2577 reg_state[CTX_RING_TAIL+1] = 0;
2579 kunmap_atomic(reg_state);