2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
194 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
195 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
196 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
199 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
200 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
201 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
205 ADVANCED_CONTEXT = 0,
210 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
211 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
212 LEGACY_64B_CONTEXT :\
216 FAULT_AND_HALT, /* Debug only */
218 FAULT_AND_CONTINUE /* Unsupported */
220 #define GEN8_CTX_ID_SHIFT 32
221 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
223 static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
224 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
225 struct drm_i915_gem_object *default_ctx_obj);
229 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
231 * @enable_execlists: value of i915.enable_execlists module parameter.
233 * Only certain platforms support Execlists (the prerequisites being
234 * support for Logical Ring Contexts and Aliasing PPGTT or better).
236 * Return: 1 if Execlists is supported and has to be enabled.
238 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
240 WARN_ON(i915.enable_ppgtt == -1);
242 /* On platforms with execlist available, vGPU will only
243 * support execlist mode, no ring buffer mode.
245 if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
248 if (INTEL_INFO(dev)->gen >= 9)
251 if (enable_execlists == 0)
254 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
255 i915.use_mmio_flip >= 0)
262 * intel_execlists_ctx_id() - get the Execlists Context ID
263 * @ctx_obj: Logical Ring Context backing object.
265 * Do not confuse with ctx->id! Unfortunately we have a name overload
266 * here: the old context ID we pass to userspace as a handler so that
267 * they can refer to a context, and the new context ID we pass to the
268 * ELSP so that the GPU can inform us of the context status via
271 * Return: 20-bits globally unique context ID.
273 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
275 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj) +
276 LRC_PPHWSP_PN * PAGE_SIZE;
278 /* LRCA is required to be 4K aligned so the more significant 20 bits
279 * are globally unique */
283 static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
285 struct drm_device *dev = ring->dev;
287 return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
288 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
289 (ring->id == VCS || ring->id == VCS2);
292 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
293 struct intel_engine_cs *ring)
295 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
297 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj) +
298 LRC_PPHWSP_PN * PAGE_SIZE;
300 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
302 desc = GEN8_CTX_VALID;
303 desc |= GEN8_CTX_ADDRESSING_MODE(dev) << GEN8_CTX_ADDRESSING_MODE_SHIFT;
304 if (IS_GEN8(ctx_obj->base.dev))
305 desc |= GEN8_CTX_L3LLC_COHERENT;
306 desc |= GEN8_CTX_PRIVILEGE;
308 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
310 /* TODO: WaDisableLiteRestore when we start using semaphore
311 * signalling between Command Streamers */
312 /* desc |= GEN8_CTX_FORCE_RESTORE; */
314 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
315 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
316 if (disable_lite_restore_wa(ring))
317 desc |= GEN8_CTX_FORCE_RESTORE;
322 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
323 struct drm_i915_gem_request *rq1)
326 struct intel_engine_cs *ring = rq0->ring;
327 struct drm_device *dev = ring->dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
332 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring);
333 rq1->elsp_submitted++;
338 desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring);
339 rq0->elsp_submitted++;
341 /* You must always write both descriptors in the order below. */
342 spin_lock(&dev_priv->uncore.lock);
343 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
344 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
345 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
347 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
348 /* The context is automatically loaded after the following */
349 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
351 /* ELSP is a wo register, use another nearby reg for posting */
352 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
353 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
354 spin_unlock(&dev_priv->uncore.lock);
357 static int execlists_update_context(struct drm_i915_gem_request *rq)
359 struct intel_engine_cs *ring = rq->ring;
360 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
361 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
362 struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
367 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
368 WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
370 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
371 reg_state = kmap_atomic(page);
373 reg_state[CTX_RING_TAIL+1] = rq->tail;
374 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
376 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
377 /* True 32b PPGTT with dynamic page allocation: update PDP
378 * registers and point the unallocated PDPs to scratch page.
379 * PML4 is allocated during ppgtt init, so this is not needed
382 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
383 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
384 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
385 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
388 kunmap_atomic(reg_state);
393 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
394 struct drm_i915_gem_request *rq1)
396 execlists_update_context(rq0);
399 execlists_update_context(rq1);
401 execlists_elsp_write(rq0, rq1);
404 static void execlists_context_unqueue(struct intel_engine_cs *ring)
406 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
407 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
409 assert_spin_locked(&ring->execlist_lock);
412 * If irqs are not active generate a warning as batches that finish
413 * without the irqs may get lost and a GPU Hang may occur.
415 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
417 if (list_empty(&ring->execlist_queue))
420 /* Try to read in pairs */
421 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
425 } else if (req0->ctx == cursor->ctx) {
426 /* Same ctx: ignore first request, as second request
427 * will update tail past first request's workload */
428 cursor->elsp_submitted = req0->elsp_submitted;
429 list_del(&req0->execlist_link);
430 list_add_tail(&req0->execlist_link,
431 &ring->execlist_retired_req_list);
439 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
441 * WaIdleLiteRestore: make sure we never cause a lite
442 * restore with HEAD==TAIL
444 if (req0->elsp_submitted) {
446 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
447 * as we resubmit the request. See gen8_emit_request()
448 * for where we prepare the padding after the end of the
451 struct intel_ringbuffer *ringbuf;
453 ringbuf = req0->ctx->engine[ring->id].ringbuf;
455 req0->tail &= ringbuf->size - 1;
459 WARN_ON(req1 && req1->elsp_submitted);
461 execlists_submit_requests(req0, req1);
464 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
467 struct drm_i915_gem_request *head_req;
469 assert_spin_locked(&ring->execlist_lock);
471 head_req = list_first_entry_or_null(&ring->execlist_queue,
472 struct drm_i915_gem_request,
475 if (head_req != NULL) {
476 struct drm_i915_gem_object *ctx_obj =
477 head_req->ctx->engine[ring->id].state;
478 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
479 WARN(head_req->elsp_submitted == 0,
480 "Never submitted head request\n");
482 if (--head_req->elsp_submitted <= 0) {
483 list_del(&head_req->execlist_link);
484 list_add_tail(&head_req->execlist_link,
485 &ring->execlist_retired_req_list);
495 * intel_lrc_irq_handler() - handle Context Switch interrupts
496 * @ring: Engine Command Streamer to handle.
498 * Check the unread Context Status Buffers and manage the submission of new
499 * contexts to the ELSP accordingly.
501 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
503 struct drm_i915_private *dev_priv = ring->dev->dev_private;
509 u32 submit_contexts = 0;
511 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
513 read_pointer = ring->next_context_status_buffer;
514 write_pointer = status_pointer & 0x07;
515 if (read_pointer > write_pointer)
518 spin_lock(&ring->execlist_lock);
520 while (read_pointer < write_pointer) {
522 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer % 6));
523 status_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer % 6));
525 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
528 if (status & GEN8_CTX_STATUS_PREEMPTED) {
529 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
530 if (execlists_check_remove_request(ring, status_id))
531 WARN(1, "Lite Restored request removed from queue\n");
533 WARN(1, "Preemption without Lite Restore\n");
536 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
537 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
538 if (execlists_check_remove_request(ring, status_id))
543 if (disable_lite_restore_wa(ring)) {
544 /* Prevent a ctx to preempt itself */
545 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) &&
546 (submit_contexts != 0))
547 execlists_context_unqueue(ring);
548 } else if (submit_contexts != 0) {
549 execlists_context_unqueue(ring);
552 spin_unlock(&ring->execlist_lock);
554 WARN(submit_contexts > 2, "More than two context complete events?\n");
555 ring->next_context_status_buffer = write_pointer % 6;
557 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
558 _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8));
561 static int execlists_context_queue(struct drm_i915_gem_request *request)
563 struct intel_engine_cs *ring = request->ring;
564 struct drm_i915_gem_request *cursor;
565 int num_elements = 0;
567 if (request->ctx != ring->default_context)
568 intel_lr_context_pin(request);
570 i915_gem_request_reference(request);
572 spin_lock_irq(&ring->execlist_lock);
574 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
575 if (++num_elements > 2)
578 if (num_elements > 2) {
579 struct drm_i915_gem_request *tail_req;
581 tail_req = list_last_entry(&ring->execlist_queue,
582 struct drm_i915_gem_request,
585 if (request->ctx == tail_req->ctx) {
586 WARN(tail_req->elsp_submitted != 0,
587 "More than 2 already-submitted reqs queued\n");
588 list_del(&tail_req->execlist_link);
589 list_add_tail(&tail_req->execlist_link,
590 &ring->execlist_retired_req_list);
594 list_add_tail(&request->execlist_link, &ring->execlist_queue);
595 if (num_elements == 0)
596 execlists_context_unqueue(ring);
598 spin_unlock_irq(&ring->execlist_lock);
603 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
605 struct intel_engine_cs *ring = req->ring;
606 uint32_t flush_domains;
610 if (ring->gpu_caches_dirty)
611 flush_domains = I915_GEM_GPU_DOMAINS;
613 ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
617 ring->gpu_caches_dirty = false;
621 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
622 struct list_head *vmas)
624 const unsigned other_rings = ~intel_ring_flag(req->ring);
625 struct i915_vma *vma;
626 uint32_t flush_domains = 0;
627 bool flush_chipset = false;
630 list_for_each_entry(vma, vmas, exec_list) {
631 struct drm_i915_gem_object *obj = vma->obj;
633 if (obj->active & other_rings) {
634 ret = i915_gem_object_sync(obj, req->ring, &req);
639 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
640 flush_chipset |= i915_gem_clflush_object(obj, false);
642 flush_domains |= obj->base.write_domain;
645 if (flush_domains & I915_GEM_DOMAIN_GTT)
648 /* Unconditionally invalidate gpu caches and ensure that we do flush
649 * any residual writes from the previous batch.
651 return logical_ring_invalidate_all_caches(req);
654 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
658 request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
660 if (request->ctx != request->ring->default_context) {
661 ret = intel_lr_context_pin(request);
669 static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
672 struct intel_ringbuffer *ringbuf = req->ringbuf;
673 struct intel_engine_cs *ring = req->ring;
674 struct drm_i915_gem_request *target;
678 if (intel_ring_space(ringbuf) >= bytes)
681 /* The whole point of reserving space is to not wait! */
682 WARN_ON(ringbuf->reserved_in_use);
684 list_for_each_entry(target, &ring->request_list, list) {
686 * The request queue is per-engine, so can contain requests
687 * from multiple ringbuffers. Here, we must ignore any that
688 * aren't from the ringbuffer we're considering.
690 if (target->ringbuf != ringbuf)
693 /* Would completion of this request free enough space? */
694 space = __intel_ring_space(target->postfix, ringbuf->tail,
700 if (WARN_ON(&target->list == &ring->request_list))
703 ret = i915_wait_request(target);
707 ringbuf->space = space;
712 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
713 * @request: Request to advance the logical ringbuffer of.
715 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
716 * really happens during submission is that the context and current tail will be placed
717 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
718 * point, the tail *inside* the context is updated and the ELSP written to.
721 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
723 struct intel_engine_cs *ring = request->ring;
724 struct drm_i915_private *dev_priv = request->i915;
726 intel_logical_ring_advance(request->ringbuf);
728 request->tail = request->ringbuf->tail;
730 if (intel_ring_stopped(ring))
733 if (dev_priv->guc.execbuf_client)
734 i915_guc_submit(dev_priv->guc.execbuf_client, request);
736 execlists_context_queue(request);
739 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
741 uint32_t __iomem *virt;
742 int rem = ringbuf->size - ringbuf->tail;
744 virt = ringbuf->virtual_start + ringbuf->tail;
747 iowrite32(MI_NOOP, virt++);
750 intel_ring_update_space(ringbuf);
753 static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
755 struct intel_ringbuffer *ringbuf = req->ringbuf;
756 int remain_usable = ringbuf->effective_size - ringbuf->tail;
757 int remain_actual = ringbuf->size - ringbuf->tail;
758 int ret, total_bytes, wait_bytes = 0;
759 bool need_wrap = false;
761 if (ringbuf->reserved_in_use)
764 total_bytes = bytes + ringbuf->reserved_size;
766 if (unlikely(bytes > remain_usable)) {
768 * Not enough space for the basic request. So need to flush
769 * out the remainder and then wait for base + reserved.
771 wait_bytes = remain_actual + total_bytes;
774 if (unlikely(total_bytes > remain_usable)) {
776 * The base request will fit but the reserved space
777 * falls off the end. So only need to to wait for the
778 * reserved size after flushing out the remainder.
780 wait_bytes = remain_actual + ringbuf->reserved_size;
782 } else if (total_bytes > ringbuf->space) {
783 /* No wrapping required, just waiting. */
784 wait_bytes = total_bytes;
789 ret = logical_ring_wait_for_space(req, wait_bytes);
794 __wrap_ring_buffer(ringbuf);
801 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
803 * @req: The request to start some new work for
804 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
806 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
807 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
808 * and also preallocates a request (every workload submission is still mediated through
809 * requests, same as it did with legacy ringbuffer submission).
811 * Return: non-zero if the ringbuffer is not ready to be written to.
813 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
815 struct drm_i915_private *dev_priv;
818 WARN_ON(req == NULL);
819 dev_priv = req->ring->dev->dev_private;
821 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
822 dev_priv->mm.interruptible);
826 ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
830 req->ringbuf->space -= num_dwords * sizeof(uint32_t);
834 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
837 * The first call merely notes the reserve request and is common for
838 * all back ends. The subsequent localised _begin() call actually
839 * ensures that the reservation is available. Without the begin, if
840 * the request creator immediately submitted the request without
841 * adding any commands to it then there might not actually be
842 * sufficient room for the submission commands.
844 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
846 return intel_logical_ring_begin(request, 0);
850 * execlists_submission() - submit a batchbuffer for execution, Execlists style
853 * @ring: Engine Command Streamer to submit to.
854 * @ctx: Context to employ for this submission.
855 * @args: execbuffer call arguments.
856 * @vmas: list of vmas.
857 * @batch_obj: the batchbuffer to submit.
858 * @exec_start: batchbuffer start virtual address pointer.
859 * @dispatch_flags: translated execbuffer call flags.
861 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
862 * away the submission details of the execbuffer ioctl call.
864 * Return: non-zero if the submission fails.
866 int intel_execlists_submission(struct i915_execbuffer_params *params,
867 struct drm_i915_gem_execbuffer2 *args,
868 struct list_head *vmas)
870 struct drm_device *dev = params->dev;
871 struct intel_engine_cs *ring = params->ring;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873 struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
879 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
880 instp_mask = I915_EXEC_CONSTANTS_MASK;
881 switch (instp_mode) {
882 case I915_EXEC_CONSTANTS_REL_GENERAL:
883 case I915_EXEC_CONSTANTS_ABSOLUTE:
884 case I915_EXEC_CONSTANTS_REL_SURFACE:
885 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
886 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
890 if (instp_mode != dev_priv->relative_constants_mode) {
891 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
892 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
896 /* The HW changed the meaning on this bit on gen6 */
897 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
901 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
905 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
906 DRM_DEBUG("sol reset is gen7 only\n");
910 ret = execlists_move_to_gpu(params->request, vmas);
914 if (ring == &dev_priv->ring[RCS] &&
915 instp_mode != dev_priv->relative_constants_mode) {
916 ret = intel_logical_ring_begin(params->request, 4);
920 intel_logical_ring_emit(ringbuf, MI_NOOP);
921 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
922 intel_logical_ring_emit_reg(ringbuf, INSTPM);
923 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
924 intel_logical_ring_advance(ringbuf);
926 dev_priv->relative_constants_mode = instp_mode;
929 exec_start = params->batch_obj_vm_offset +
930 args->batch_start_offset;
932 ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
936 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
938 i915_gem_execbuffer_move_to_active(vmas, params->request);
939 i915_gem_execbuffer_retire_commands(params);
944 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
946 struct drm_i915_gem_request *req, *tmp;
947 struct list_head retired_list;
949 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
950 if (list_empty(&ring->execlist_retired_req_list))
953 INIT_LIST_HEAD(&retired_list);
954 spin_lock_irq(&ring->execlist_lock);
955 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
956 spin_unlock_irq(&ring->execlist_lock);
958 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
959 struct intel_context *ctx = req->ctx;
960 struct drm_i915_gem_object *ctx_obj =
961 ctx->engine[ring->id].state;
963 if (ctx_obj && (ctx != ring->default_context))
964 intel_lr_context_unpin(req);
965 list_del(&req->execlist_link);
966 i915_gem_request_unreference(req);
970 void intel_logical_ring_stop(struct intel_engine_cs *ring)
972 struct drm_i915_private *dev_priv = ring->dev->dev_private;
975 if (!intel_ring_initialized(ring))
978 ret = intel_ring_idle(ring);
979 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
980 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
983 /* TODO: Is this correct with Execlists enabled? */
984 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
985 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
986 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
989 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
992 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
994 struct intel_engine_cs *ring = req->ring;
997 if (!ring->gpu_caches_dirty)
1000 ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1004 ring->gpu_caches_dirty = false;
1008 static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
1009 struct drm_i915_gem_object *ctx_obj,
1010 struct intel_ringbuffer *ringbuf)
1012 struct drm_device *dev = ring->dev;
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1016 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1017 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
1018 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
1022 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1026 ctx_obj->dirty = true;
1028 /* Invalidate GuC TLB. */
1029 if (i915.enable_guc_submission)
1030 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1035 i915_gem_object_ggtt_unpin(ctx_obj);
1040 static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
1043 struct intel_engine_cs *ring = rq->ring;
1044 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1045 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1047 if (rq->ctx->engine[ring->id].pin_count++ == 0) {
1048 ret = intel_lr_context_do_pin(ring, ctx_obj, ringbuf);
1050 goto reset_pin_count;
1055 rq->ctx->engine[ring->id].pin_count = 0;
1059 void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
1061 struct intel_engine_cs *ring = rq->ring;
1062 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1063 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1066 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1067 if (--rq->ctx->engine[ring->id].pin_count == 0) {
1068 intel_unpin_ringbuffer_obj(ringbuf);
1069 i915_gem_object_ggtt_unpin(ctx_obj);
1074 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1077 struct intel_engine_cs *ring = req->ring;
1078 struct intel_ringbuffer *ringbuf = req->ringbuf;
1079 struct drm_device *dev = ring->dev;
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 struct i915_workarounds *w = &dev_priv->workarounds;
1083 if (WARN_ON_ONCE(w->count == 0))
1086 ring->gpu_caches_dirty = true;
1087 ret = logical_ring_flush_all_caches(req);
1091 ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1095 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1096 for (i = 0; i < w->count; i++) {
1097 intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
1098 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1100 intel_logical_ring_emit(ringbuf, MI_NOOP);
1102 intel_logical_ring_advance(ringbuf);
1104 ring->gpu_caches_dirty = true;
1105 ret = logical_ring_flush_all_caches(req);
1112 #define wa_ctx_emit(batch, index, cmd) \
1114 int __index = (index)++; \
1115 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1118 batch[__index] = (cmd); \
1121 #define wa_ctx_emit_reg(batch, index, reg) \
1122 wa_ctx_emit((batch), (index), (reg))
1125 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1126 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1127 * but there is a slight complication as this is applied in WA batch where the
1128 * values are only initialized once so we cannot take register value at the
1129 * beginning and reuse it further; hence we save its value to memory, upload a
1130 * constant value with bit21 set and then we restore it back with the saved value.
1131 * To simplify the WA, a constant value is formed by using the default value
1132 * of this register. This shouldn't be a problem because we are only modifying
1133 * it for a short period and this batch in non-premptible. We can ofcourse
1134 * use additional instructions that read the actual value of the register
1135 * at that time and set our bit of interest but it makes the WA complicated.
1137 * This WA is also required for Gen9 so extracting as a function avoids
1140 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
1141 uint32_t *const batch,
1144 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1147 * WaDisableLSQCROPERFforOCL:skl
1148 * This WA is implemented in skl_init_clock_gating() but since
1149 * this batch updates GEN8_L3SQCREG4 with default value we need to
1150 * set this bit here to retain the WA during flush.
1152 if (IS_SKL_REVID(ring->dev, 0, SKL_REVID_E0))
1153 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1155 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1156 MI_SRM_LRM_GLOBAL_GTT));
1157 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1158 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1159 wa_ctx_emit(batch, index, 0);
1161 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1162 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1163 wa_ctx_emit(batch, index, l3sqc4_flush);
1165 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1166 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1167 PIPE_CONTROL_DC_FLUSH_ENABLE));
1168 wa_ctx_emit(batch, index, 0);
1169 wa_ctx_emit(batch, index, 0);
1170 wa_ctx_emit(batch, index, 0);
1171 wa_ctx_emit(batch, index, 0);
1173 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1174 MI_SRM_LRM_GLOBAL_GTT));
1175 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1176 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1177 wa_ctx_emit(batch, index, 0);
1182 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1184 uint32_t start_alignment)
1186 return wa_ctx->offset = ALIGN(offset, start_alignment);
1189 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1191 uint32_t size_alignment)
1193 wa_ctx->size = offset - wa_ctx->offset;
1195 WARN(wa_ctx->size % size_alignment,
1196 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1197 wa_ctx->size, size_alignment);
1202 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1204 * @ring: only applicable for RCS
1205 * @wa_ctx: structure representing wa_ctx
1206 * offset: specifies start of the batch, should be cache-aligned. This is updated
1207 * with the offset value received as input.
1208 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1209 * @batch: page in which WA are loaded
1210 * @offset: This field specifies the start of the batch, it should be
1211 * cache-aligned otherwise it is adjusted accordingly.
1212 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1213 * initialized at the beginning and shared across all contexts but this field
1214 * helps us to have multiple batches at different offsets and select them based
1215 * on a criteria. At the moment this batch always start at the beginning of the page
1216 * and at this point we don't have multiple wa_ctx batch buffers.
1218 * The number of WA applied are not known at the beginning; we use this field
1219 * to return the no of DWORDS written.
1221 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1222 * so it adds NOOPs as padding to make it cacheline aligned.
1223 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1224 * makes a complete batch buffer.
1226 * Return: non-zero if we exceed the PAGE_SIZE limit.
1229 static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
1230 struct i915_wa_ctx_bb *wa_ctx,
1231 uint32_t *const batch,
1234 uint32_t scratch_addr;
1235 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1237 /* WaDisableCtxRestoreArbitration:bdw,chv */
1238 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1240 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1241 if (IS_BROADWELL(ring->dev)) {
1242 int rc = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1248 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1249 /* Actual scratch location is at 128 bytes offset */
1250 scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;
1252 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1253 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1254 PIPE_CONTROL_GLOBAL_GTT_IVB |
1255 PIPE_CONTROL_CS_STALL |
1256 PIPE_CONTROL_QW_WRITE));
1257 wa_ctx_emit(batch, index, scratch_addr);
1258 wa_ctx_emit(batch, index, 0);
1259 wa_ctx_emit(batch, index, 0);
1260 wa_ctx_emit(batch, index, 0);
1262 /* Pad to end of cacheline */
1263 while (index % CACHELINE_DWORDS)
1264 wa_ctx_emit(batch, index, MI_NOOP);
1267 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1268 * execution depends on the length specified in terms of cache lines
1269 * in the register CTX_RCS_INDIRECT_CTX
1272 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1276 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1278 * @ring: only applicable for RCS
1279 * @wa_ctx: structure representing wa_ctx
1280 * offset: specifies start of the batch, should be cache-aligned.
1281 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1282 * @batch: page in which WA are loaded
1283 * @offset: This field specifies the start of this batch.
1284 * This batch is started immediately after indirect_ctx batch. Since we ensure
1285 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1287 * The number of DWORDS written are returned using this field.
1289 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1290 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1292 static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
1293 struct i915_wa_ctx_bb *wa_ctx,
1294 uint32_t *const batch,
1297 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1299 /* WaDisableCtxRestoreArbitration:bdw,chv */
1300 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1302 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1304 return wa_ctx_end(wa_ctx, *offset = index, 1);
1307 static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
1308 struct i915_wa_ctx_bb *wa_ctx,
1309 uint32_t *const batch,
1313 struct drm_device *dev = ring->dev;
1314 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1316 /* WaDisableCtxRestoreArbitration:skl,bxt */
1317 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1318 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1319 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1321 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1322 ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1327 /* Pad to end of cacheline */
1328 while (index % CACHELINE_DWORDS)
1329 wa_ctx_emit(batch, index, MI_NOOP);
1331 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1334 static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
1335 struct i915_wa_ctx_bb *wa_ctx,
1336 uint32_t *const batch,
1339 struct drm_device *dev = ring->dev;
1340 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1342 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1343 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
1344 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1345 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1346 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1347 wa_ctx_emit(batch, index,
1348 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1349 wa_ctx_emit(batch, index, MI_NOOP);
1352 /* WaDisableCtxRestoreArbitration:skl,bxt */
1353 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1354 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1355 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1357 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1359 return wa_ctx_end(wa_ctx, *offset = index, 1);
1362 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
1366 ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
1367 if (!ring->wa_ctx.obj) {
1368 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1372 ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
1374 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1376 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1383 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
1385 if (ring->wa_ctx.obj) {
1386 i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
1387 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1388 ring->wa_ctx.obj = NULL;
1392 static int intel_init_workaround_bb(struct intel_engine_cs *ring)
1398 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
1400 WARN_ON(ring->id != RCS);
1402 /* update this when WA for higher Gen are added */
1403 if (INTEL_INFO(ring->dev)->gen > 9) {
1404 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1405 INTEL_INFO(ring->dev)->gen);
1409 /* some WA perform writes to scratch page, ensure it is valid */
1410 if (ring->scratch.obj == NULL) {
1411 DRM_ERROR("scratch page not allocated for %s\n", ring->name);
1415 ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
1417 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1421 page = i915_gem_object_get_page(wa_ctx->obj, 0);
1422 batch = kmap_atomic(page);
1425 if (INTEL_INFO(ring->dev)->gen == 8) {
1426 ret = gen8_init_indirectctx_bb(ring,
1427 &wa_ctx->indirect_ctx,
1433 ret = gen8_init_perctx_bb(ring,
1439 } else if (INTEL_INFO(ring->dev)->gen == 9) {
1440 ret = gen9_init_indirectctx_bb(ring,
1441 &wa_ctx->indirect_ctx,
1447 ret = gen9_init_perctx_bb(ring,
1456 kunmap_atomic(batch);
1458 lrc_destroy_wa_ctx_obj(ring);
1463 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1465 struct drm_device *dev = ring->dev;
1466 struct drm_i915_private *dev_priv = dev->dev_private;
1468 lrc_setup_hardware_status_page(ring,
1469 ring->default_context->engine[ring->id].state);
1471 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1472 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1474 if (ring->status_page.obj) {
1475 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1476 (u32)ring->status_page.gfx_addr);
1477 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1480 I915_WRITE(RING_MODE_GEN7(ring),
1481 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1482 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1483 POSTING_READ(RING_MODE_GEN7(ring));
1484 ring->next_context_status_buffer = 0;
1485 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1487 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1492 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1494 struct drm_device *dev = ring->dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1498 ret = gen8_init_common_ring(ring);
1502 /* We need to disable the AsyncFlip performance optimisations in order
1503 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1504 * programmed to '1' on all products.
1506 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1508 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1510 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1512 return init_workarounds_ring(ring);
1515 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1519 ret = gen8_init_common_ring(ring);
1523 return init_workarounds_ring(ring);
1526 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1528 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1529 struct intel_engine_cs *ring = req->ring;
1530 struct intel_ringbuffer *ringbuf = req->ringbuf;
1531 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1534 ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
1538 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1539 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1540 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1542 intel_logical_ring_emit_reg(ringbuf, GEN8_RING_PDP_UDW(ring, i));
1543 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1544 intel_logical_ring_emit_reg(ringbuf, GEN8_RING_PDP_LDW(ring, i));
1545 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1548 intel_logical_ring_emit(ringbuf, MI_NOOP);
1549 intel_logical_ring_advance(ringbuf);
1554 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1555 u64 offset, unsigned dispatch_flags)
1557 struct intel_ringbuffer *ringbuf = req->ringbuf;
1558 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1561 /* Don't rely in hw updating PDPs, specially in lite-restore.
1562 * Ideally, we should set Force PD Restore in ctx descriptor,
1563 * but we can't. Force Restore would be a second option, but
1564 * it is unsafe in case of lite-restore (because the ctx is
1565 * not idle). PML4 is allocated during ppgtt init so this is
1566 * not needed in 48-bit.*/
1567 if (req->ctx->ppgtt &&
1568 (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
1569 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1570 !intel_vgpu_active(req->i915->dev)) {
1571 ret = intel_logical_ring_emit_pdps(req);
1576 req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
1579 ret = intel_logical_ring_begin(req, 4);
1583 /* FIXME(BDW): Address space and security selectors. */
1584 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1586 (dispatch_flags & I915_DISPATCH_RS ?
1587 MI_BATCH_RESOURCE_STREAMER : 0));
1588 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1589 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1590 intel_logical_ring_emit(ringbuf, MI_NOOP);
1591 intel_logical_ring_advance(ringbuf);
1596 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1598 struct drm_device *dev = ring->dev;
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600 unsigned long flags;
1602 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1605 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1606 if (ring->irq_refcount++ == 0) {
1607 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1608 POSTING_READ(RING_IMR(ring->mmio_base));
1610 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1615 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1617 struct drm_device *dev = ring->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619 unsigned long flags;
1621 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1622 if (--ring->irq_refcount == 0) {
1623 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1624 POSTING_READ(RING_IMR(ring->mmio_base));
1626 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1629 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1630 u32 invalidate_domains,
1633 struct intel_ringbuffer *ringbuf = request->ringbuf;
1634 struct intel_engine_cs *ring = ringbuf->ring;
1635 struct drm_device *dev = ring->dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1640 ret = intel_logical_ring_begin(request, 4);
1644 cmd = MI_FLUSH_DW + 1;
1646 /* We always require a command barrier so that subsequent
1647 * commands, such as breadcrumb interrupts, are strictly ordered
1648 * wrt the contents of the write cache being flushed to memory
1649 * (and thus being coherent from the CPU).
1651 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1653 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1654 cmd |= MI_INVALIDATE_TLB;
1655 if (ring == &dev_priv->ring[VCS])
1656 cmd |= MI_INVALIDATE_BSD;
1659 intel_logical_ring_emit(ringbuf, cmd);
1660 intel_logical_ring_emit(ringbuf,
1661 I915_GEM_HWS_SCRATCH_ADDR |
1662 MI_FLUSH_DW_USE_GTT);
1663 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1664 intel_logical_ring_emit(ringbuf, 0); /* value */
1665 intel_logical_ring_advance(ringbuf);
1670 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1671 u32 invalidate_domains,
1674 struct intel_ringbuffer *ringbuf = request->ringbuf;
1675 struct intel_engine_cs *ring = ringbuf->ring;
1676 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1681 flags |= PIPE_CONTROL_CS_STALL;
1683 if (flush_domains) {
1684 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1685 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1688 if (invalidate_domains) {
1689 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1690 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1691 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1692 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1693 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1694 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1695 flags |= PIPE_CONTROL_QW_WRITE;
1696 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1700 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1703 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
1704 flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
1706 ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1711 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1712 intel_logical_ring_emit(ringbuf, 0);
1713 intel_logical_ring_emit(ringbuf, 0);
1714 intel_logical_ring_emit(ringbuf, 0);
1715 intel_logical_ring_emit(ringbuf, 0);
1716 intel_logical_ring_emit(ringbuf, 0);
1719 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1720 intel_logical_ring_emit(ringbuf, flags);
1721 intel_logical_ring_emit(ringbuf, scratch_addr);
1722 intel_logical_ring_emit(ringbuf, 0);
1723 intel_logical_ring_emit(ringbuf, 0);
1724 intel_logical_ring_emit(ringbuf, 0);
1725 intel_logical_ring_advance(ringbuf);
1730 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1732 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1735 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1737 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1740 static u32 bxt_a_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1744 * On BXT A steppings there is a HW coherency issue whereby the
1745 * MI_STORE_DATA_IMM storing the completed request's seqno
1746 * occasionally doesn't invalidate the CPU cache. Work around this by
1747 * clflushing the corresponding cacheline whenever the caller wants
1748 * the coherency to be guaranteed. Note that this cacheline is known
1749 * to be clean at this point, since we only write it in
1750 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1751 * this clflush in practice becomes an invalidate operation.
1754 if (!lazy_coherency)
1755 intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
1757 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1760 static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1762 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1764 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1765 intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
1768 static int gen8_emit_request(struct drm_i915_gem_request *request)
1770 struct intel_ringbuffer *ringbuf = request->ringbuf;
1771 struct intel_engine_cs *ring = ringbuf->ring;
1776 * Reserve space for 2 NOOPs at the end of each request to be
1777 * used as a workaround for not being allowed to do lite
1778 * restore with HEAD==TAIL (WaIdleLiteRestore).
1780 ret = intel_logical_ring_begin(request, 8);
1784 cmd = MI_STORE_DWORD_IMM_GEN4;
1785 cmd |= MI_GLOBAL_GTT;
1787 intel_logical_ring_emit(ringbuf, cmd);
1788 intel_logical_ring_emit(ringbuf,
1789 (ring->status_page.gfx_addr +
1790 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1791 intel_logical_ring_emit(ringbuf, 0);
1792 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1793 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1794 intel_logical_ring_emit(ringbuf, MI_NOOP);
1795 intel_logical_ring_advance_and_submit(request);
1798 * Here we add two extra NOOPs as padding to avoid
1799 * lite restore of a context with HEAD==TAIL.
1801 intel_logical_ring_emit(ringbuf, MI_NOOP);
1802 intel_logical_ring_emit(ringbuf, MI_NOOP);
1803 intel_logical_ring_advance(ringbuf);
1808 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1810 struct render_state so;
1813 ret = i915_gem_render_state_prepare(req->ring, &so);
1817 if (so.rodata == NULL)
1820 ret = req->ring->emit_bb_start(req, so.ggtt_offset,
1821 I915_DISPATCH_SECURE);
1825 ret = req->ring->emit_bb_start(req,
1826 (so.ggtt_offset + so.aux_batch_offset),
1827 I915_DISPATCH_SECURE);
1831 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1834 i915_gem_render_state_fini(&so);
1838 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1842 ret = intel_logical_ring_workarounds_emit(req);
1846 ret = intel_rcs_context_init_mocs(req);
1848 * Failing to program the MOCS is non-fatal.The system will not
1849 * run at peak performance. So generate an error and carry on.
1852 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1854 return intel_lr_context_render_state_init(req);
1858 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1860 * @ring: Engine Command Streamer.
1863 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1865 struct drm_i915_private *dev_priv;
1867 if (!intel_ring_initialized(ring))
1870 dev_priv = ring->dev->dev_private;
1872 intel_logical_ring_stop(ring);
1873 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1876 ring->cleanup(ring);
1878 i915_cmd_parser_fini_ring(ring);
1879 i915_gem_batch_pool_fini(&ring->batch_pool);
1881 if (ring->status_page.obj) {
1882 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1883 ring->status_page.obj = NULL;
1886 lrc_destroy_wa_ctx_obj(ring);
1889 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1893 /* Intentionally left blank. */
1894 ring->buffer = NULL;
1897 INIT_LIST_HEAD(&ring->active_list);
1898 INIT_LIST_HEAD(&ring->request_list);
1899 i915_gem_batch_pool_init(dev, &ring->batch_pool);
1900 init_waitqueue_head(&ring->irq_queue);
1902 INIT_LIST_HEAD(&ring->buffers);
1903 INIT_LIST_HEAD(&ring->execlist_queue);
1904 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1905 spin_lock_init(&ring->execlist_lock);
1907 ret = i915_cmd_parser_init_ring(ring);
1911 ret = intel_lr_context_deferred_alloc(ring->default_context, ring);
1915 /* As this is the default context, always pin it */
1916 ret = intel_lr_context_do_pin(
1918 ring->default_context->engine[ring->id].state,
1919 ring->default_context->engine[ring->id].ringbuf);
1922 "Failed to pin and map ringbuffer %s: %d\n",
1930 static int logical_render_ring_init(struct drm_device *dev)
1932 struct drm_i915_private *dev_priv = dev->dev_private;
1933 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1936 ring->name = "render ring";
1938 ring->mmio_base = RENDER_RING_BASE;
1939 ring->irq_enable_mask =
1940 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1941 ring->irq_keep_mask =
1942 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1943 if (HAS_L3_DPF(dev))
1944 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1946 if (INTEL_INFO(dev)->gen >= 9)
1947 ring->init_hw = gen9_init_render_ring;
1949 ring->init_hw = gen8_init_render_ring;
1950 ring->init_context = gen8_init_rcs_context;
1951 ring->cleanup = intel_fini_pipe_control;
1952 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1953 ring->get_seqno = bxt_a_get_seqno;
1954 ring->set_seqno = bxt_a_set_seqno;
1956 ring->get_seqno = gen8_get_seqno;
1957 ring->set_seqno = gen8_set_seqno;
1959 ring->emit_request = gen8_emit_request;
1960 ring->emit_flush = gen8_emit_flush_render;
1961 ring->irq_get = gen8_logical_ring_get_irq;
1962 ring->irq_put = gen8_logical_ring_put_irq;
1963 ring->emit_bb_start = gen8_emit_bb_start;
1967 ret = intel_init_pipe_control(ring);
1971 ret = intel_init_workaround_bb(ring);
1974 * We continue even if we fail to initialize WA batch
1975 * because we only expect rare glitches but nothing
1976 * critical to prevent us from using GPU
1978 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1982 ret = logical_ring_init(dev, ring);
1984 lrc_destroy_wa_ctx_obj(ring);
1990 static int logical_bsd_ring_init(struct drm_device *dev)
1992 struct drm_i915_private *dev_priv = dev->dev_private;
1993 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1995 ring->name = "bsd ring";
1997 ring->mmio_base = GEN6_BSD_RING_BASE;
1998 ring->irq_enable_mask =
1999 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2000 ring->irq_keep_mask =
2001 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2003 ring->init_hw = gen8_init_common_ring;
2004 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2005 ring->get_seqno = bxt_a_get_seqno;
2006 ring->set_seqno = bxt_a_set_seqno;
2008 ring->get_seqno = gen8_get_seqno;
2009 ring->set_seqno = gen8_set_seqno;
2011 ring->emit_request = gen8_emit_request;
2012 ring->emit_flush = gen8_emit_flush;
2013 ring->irq_get = gen8_logical_ring_get_irq;
2014 ring->irq_put = gen8_logical_ring_put_irq;
2015 ring->emit_bb_start = gen8_emit_bb_start;
2017 return logical_ring_init(dev, ring);
2020 static int logical_bsd2_ring_init(struct drm_device *dev)
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2025 ring->name = "bds2 ring";
2027 ring->mmio_base = GEN8_BSD2_RING_BASE;
2028 ring->irq_enable_mask =
2029 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2030 ring->irq_keep_mask =
2031 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2033 ring->init_hw = gen8_init_common_ring;
2034 ring->get_seqno = gen8_get_seqno;
2035 ring->set_seqno = gen8_set_seqno;
2036 ring->emit_request = gen8_emit_request;
2037 ring->emit_flush = gen8_emit_flush;
2038 ring->irq_get = gen8_logical_ring_get_irq;
2039 ring->irq_put = gen8_logical_ring_put_irq;
2040 ring->emit_bb_start = gen8_emit_bb_start;
2042 return logical_ring_init(dev, ring);
2045 static int logical_blt_ring_init(struct drm_device *dev)
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2050 ring->name = "blitter ring";
2052 ring->mmio_base = BLT_RING_BASE;
2053 ring->irq_enable_mask =
2054 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2055 ring->irq_keep_mask =
2056 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2058 ring->init_hw = gen8_init_common_ring;
2059 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2060 ring->get_seqno = bxt_a_get_seqno;
2061 ring->set_seqno = bxt_a_set_seqno;
2063 ring->get_seqno = gen8_get_seqno;
2064 ring->set_seqno = gen8_set_seqno;
2066 ring->emit_request = gen8_emit_request;
2067 ring->emit_flush = gen8_emit_flush;
2068 ring->irq_get = gen8_logical_ring_get_irq;
2069 ring->irq_put = gen8_logical_ring_put_irq;
2070 ring->emit_bb_start = gen8_emit_bb_start;
2072 return logical_ring_init(dev, ring);
2075 static int logical_vebox_ring_init(struct drm_device *dev)
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2080 ring->name = "video enhancement ring";
2082 ring->mmio_base = VEBOX_RING_BASE;
2083 ring->irq_enable_mask =
2084 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2085 ring->irq_keep_mask =
2086 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2088 ring->init_hw = gen8_init_common_ring;
2089 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2090 ring->get_seqno = bxt_a_get_seqno;
2091 ring->set_seqno = bxt_a_set_seqno;
2093 ring->get_seqno = gen8_get_seqno;
2094 ring->set_seqno = gen8_set_seqno;
2096 ring->emit_request = gen8_emit_request;
2097 ring->emit_flush = gen8_emit_flush;
2098 ring->irq_get = gen8_logical_ring_get_irq;
2099 ring->irq_put = gen8_logical_ring_put_irq;
2100 ring->emit_bb_start = gen8_emit_bb_start;
2102 return logical_ring_init(dev, ring);
2106 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2109 * This function inits the engines for an Execlists submission style (the equivalent in the
2110 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2111 * those engines that are present in the hardware.
2113 * Return: non-zero if the initialization failed.
2115 int intel_logical_rings_init(struct drm_device *dev)
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2120 ret = logical_render_ring_init(dev);
2125 ret = logical_bsd_ring_init(dev);
2127 goto cleanup_render_ring;
2131 ret = logical_blt_ring_init(dev);
2133 goto cleanup_bsd_ring;
2136 if (HAS_VEBOX(dev)) {
2137 ret = logical_vebox_ring_init(dev);
2139 goto cleanup_blt_ring;
2142 if (HAS_BSD2(dev)) {
2143 ret = logical_bsd2_ring_init(dev);
2145 goto cleanup_vebox_ring;
2151 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
2153 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
2155 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
2156 cleanup_render_ring:
2157 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
2163 make_rpcs(struct drm_device *dev)
2168 * No explicit RPCS request is needed to ensure full
2169 * slice/subslice/EU enablement prior to Gen9.
2171 if (INTEL_INFO(dev)->gen < 9)
2175 * Starting in Gen9, render power gating can leave
2176 * slice/subslice/EU in a partially enabled state. We
2177 * must make an explicit request through RPCS for full
2180 if (INTEL_INFO(dev)->has_slice_pg) {
2181 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2182 rpcs |= INTEL_INFO(dev)->slice_total <<
2183 GEN8_RPCS_S_CNT_SHIFT;
2184 rpcs |= GEN8_RPCS_ENABLE;
2187 if (INTEL_INFO(dev)->has_subslice_pg) {
2188 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2189 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2190 GEN8_RPCS_SS_CNT_SHIFT;
2191 rpcs |= GEN8_RPCS_ENABLE;
2194 if (INTEL_INFO(dev)->has_eu_pg) {
2195 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2196 GEN8_RPCS_EU_MIN_SHIFT;
2197 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2198 GEN8_RPCS_EU_MAX_SHIFT;
2199 rpcs |= GEN8_RPCS_ENABLE;
2206 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
2207 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
2209 struct drm_device *dev = ring->dev;
2210 struct drm_i915_private *dev_priv = dev->dev_private;
2211 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2213 uint32_t *reg_state;
2217 ppgtt = dev_priv->mm.aliasing_ppgtt;
2219 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2221 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2225 ret = i915_gem_object_get_pages(ctx_obj);
2227 DRM_DEBUG_DRIVER("Could not get object pages\n");
2231 i915_gem_object_pin_pages(ctx_obj);
2233 /* The second page of the context object contains some fields which must
2234 * be set up prior to the first execution. */
2235 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2236 reg_state = kmap_atomic(page);
2238 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2239 * commands followed by (reg, value) pairs. The values we are setting here are
2240 * only for the first context restore: on a subsequent save, the GPU will
2241 * recreate this batchbuffer with new values (including all the missing
2242 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2243 if (ring->id == RCS)
2244 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
2246 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
2247 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
2248 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
2249 reg_state[CTX_CONTEXT_CONTROL+1] =
2250 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2251 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2252 CTX_CTRL_RS_CTX_ENABLE);
2253 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
2254 reg_state[CTX_RING_HEAD+1] = 0;
2255 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
2256 reg_state[CTX_RING_TAIL+1] = 0;
2257 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
2258 /* Ring buffer start address is not known until the buffer is pinned.
2259 * It is written to the context image in execlists_update_context()
2261 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
2262 reg_state[CTX_RING_BUFFER_CONTROL+1] =
2263 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
2264 reg_state[CTX_BB_HEAD_U] = RING_BBADDR_UDW(ring->mmio_base);
2265 reg_state[CTX_BB_HEAD_U+1] = 0;
2266 reg_state[CTX_BB_HEAD_L] = RING_BBADDR(ring->mmio_base);
2267 reg_state[CTX_BB_HEAD_L+1] = 0;
2268 reg_state[CTX_BB_STATE] = RING_BBSTATE(ring->mmio_base);
2269 reg_state[CTX_BB_STATE+1] = RING_BB_PPGTT;
2270 reg_state[CTX_SECOND_BB_HEAD_U] = RING_SBBADDR_UDW(ring->mmio_base);
2271 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
2272 reg_state[CTX_SECOND_BB_HEAD_L] = RING_SBBADDR(ring->mmio_base);
2273 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
2274 reg_state[CTX_SECOND_BB_STATE] = RING_SBBSTATE(ring->mmio_base);
2275 reg_state[CTX_SECOND_BB_STATE+1] = 0;
2276 if (ring->id == RCS) {
2277 reg_state[CTX_BB_PER_CTX_PTR] = RING_BB_PER_CTX_PTR(ring->mmio_base);
2278 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
2279 reg_state[CTX_RCS_INDIRECT_CTX] = RING_INDIRECT_CTX(ring->mmio_base);
2280 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
2281 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = RING_INDIRECT_CTX_OFFSET(ring->mmio_base);
2282 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
2283 if (ring->wa_ctx.obj) {
2284 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
2285 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2287 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2288 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2289 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2291 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2292 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
2294 reg_state[CTX_BB_PER_CTX_PTR+1] =
2295 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2299 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
2300 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
2301 reg_state[CTX_CTX_TIMESTAMP] = RING_CTX_TIMESTAMP(ring->mmio_base);
2302 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
2303 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
2304 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
2305 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
2306 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
2307 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
2308 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
2309 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
2310 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
2312 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2313 /* 64b PPGTT (48bit canonical)
2314 * PDP0_DESCRIPTOR contains the base address to PML4 and
2315 * other PDP Descriptors are ignored.
2317 ASSIGN_CTX_PML4(ppgtt, reg_state);
2320 * PDP*_DESCRIPTOR contains the base address of space supported.
2321 * With dynamic page allocation, PDPs may not be allocated at
2322 * this point. Point the unallocated PDPs to the scratch page
2324 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
2325 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
2326 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
2327 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
2330 if (ring->id == RCS) {
2331 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2332 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
2333 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
2336 kunmap_atomic(reg_state);
2339 set_page_dirty(page);
2340 i915_gem_object_unpin_pages(ctx_obj);
2346 * intel_lr_context_free() - free the LRC specific bits of a context
2347 * @ctx: the LR context to free.
2349 * The real context freeing is done in i915_gem_context_free: this only
2350 * takes care of the bits that are LRC related: the per-engine backing
2351 * objects and the logical ringbuffer.
2353 void intel_lr_context_free(struct intel_context *ctx)
2357 for (i = 0; i < I915_NUM_RINGS; i++) {
2358 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2361 struct intel_ringbuffer *ringbuf =
2362 ctx->engine[i].ringbuf;
2363 struct intel_engine_cs *ring = ringbuf->ring;
2365 if (ctx == ring->default_context) {
2366 intel_unpin_ringbuffer_obj(ringbuf);
2367 i915_gem_object_ggtt_unpin(ctx_obj);
2369 WARN_ON(ctx->engine[ring->id].pin_count);
2370 intel_ringbuffer_free(ringbuf);
2371 drm_gem_object_unreference(&ctx_obj->base);
2376 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
2380 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
2384 if (INTEL_INFO(ring->dev)->gen >= 9)
2385 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2387 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2393 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2400 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
2401 struct drm_i915_gem_object *default_ctx_obj)
2403 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2406 /* The HWSP is part of the default context object in LRC mode. */
2407 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
2408 + LRC_PPHWSP_PN * PAGE_SIZE;
2409 page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
2410 ring->status_page.page_addr = kmap(page);
2411 ring->status_page.obj = default_ctx_obj;
2413 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
2414 (u32)ring->status_page.gfx_addr);
2415 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
2419 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2420 * @ctx: LR context to create.
2421 * @ring: engine to be used with the context.
2423 * This function can be called more than once, with different engines, if we plan
2424 * to use the context with them. The context backing objects and the ringbuffers
2425 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2426 * the creation is a deferred call: it's better to make sure first that we need to use
2427 * a given ring with the context.
2429 * Return: non-zero on error.
2432 int intel_lr_context_deferred_alloc(struct intel_context *ctx,
2433 struct intel_engine_cs *ring)
2435 struct drm_device *dev = ring->dev;
2436 struct drm_i915_gem_object *ctx_obj;
2437 uint32_t context_size;
2438 struct intel_ringbuffer *ringbuf;
2441 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2442 WARN_ON(ctx->engine[ring->id].state);
2444 context_size = round_up(get_lr_context_size(ring), 4096);
2446 /* One extra page as the sharing data between driver and GuC */
2447 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2449 ctx_obj = i915_gem_alloc_object(dev, context_size);
2451 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2455 ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE);
2456 if (IS_ERR(ringbuf)) {
2457 ret = PTR_ERR(ringbuf);
2458 goto error_deref_obj;
2461 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
2463 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2467 ctx->engine[ring->id].ringbuf = ringbuf;
2468 ctx->engine[ring->id].state = ctx_obj;
2470 if (ctx != ring->default_context && ring->init_context) {
2471 struct drm_i915_gem_request *req;
2473 ret = i915_gem_request_alloc(ring,
2476 DRM_ERROR("ring create req: %d\n",
2481 ret = ring->init_context(req);
2483 DRM_ERROR("ring init context: %d\n",
2485 i915_gem_request_cancel(req);
2488 i915_add_request_no_flush(req);
2493 intel_ringbuffer_free(ringbuf);
2495 drm_gem_object_unreference(&ctx_obj->base);
2496 ctx->engine[ring->id].ringbuf = NULL;
2497 ctx->engine[ring->id].state = NULL;
2501 void intel_lr_context_reset(struct drm_device *dev,
2502 struct intel_context *ctx)
2504 struct drm_i915_private *dev_priv = dev->dev_private;
2505 struct intel_engine_cs *ring;
2508 for_each_ring(ring, dev_priv, i) {
2509 struct drm_i915_gem_object *ctx_obj =
2510 ctx->engine[ring->id].state;
2511 struct intel_ringbuffer *ringbuf =
2512 ctx->engine[ring->id].ringbuf;
2513 uint32_t *reg_state;
2519 if (i915_gem_object_get_pages(ctx_obj)) {
2520 WARN(1, "Failed get_pages for context obj\n");
2523 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2524 reg_state = kmap_atomic(page);
2526 reg_state[CTX_RING_HEAD+1] = 0;
2527 reg_state[CTX_RING_TAIL+1] = 0;
2529 kunmap_atomic(reg_state);