2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
161 GEN8_CTX_STATUS_PREEMPTED | \
162 GEN8_CTX_STATUS_ELEMENT_SWITCH)
164 #define CTX_LRI_HEADER_0 0x01
165 #define CTX_CONTEXT_CONTROL 0x02
166 #define CTX_RING_HEAD 0x04
167 #define CTX_RING_TAIL 0x06
168 #define CTX_RING_BUFFER_START 0x08
169 #define CTX_RING_BUFFER_CONTROL 0x0a
170 #define CTX_BB_HEAD_U 0x0c
171 #define CTX_BB_HEAD_L 0x0e
172 #define CTX_BB_STATE 0x10
173 #define CTX_SECOND_BB_HEAD_U 0x12
174 #define CTX_SECOND_BB_HEAD_L 0x14
175 #define CTX_SECOND_BB_STATE 0x16
176 #define CTX_BB_PER_CTX_PTR 0x18
177 #define CTX_RCS_INDIRECT_CTX 0x1a
178 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
179 #define CTX_LRI_HEADER_1 0x21
180 #define CTX_CTX_TIMESTAMP 0x22
181 #define CTX_PDP3_UDW 0x24
182 #define CTX_PDP3_LDW 0x26
183 #define CTX_PDP2_UDW 0x28
184 #define CTX_PDP2_LDW 0x2a
185 #define CTX_PDP1_UDW 0x2c
186 #define CTX_PDP1_LDW 0x2e
187 #define CTX_PDP0_UDW 0x30
188 #define CTX_PDP0_LDW 0x32
189 #define CTX_LRI_HEADER_2 0x41
190 #define CTX_R_PWR_CLK_STATE 0x42
191 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
193 #define GEN8_CTX_VALID (1<<0)
194 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
195 #define GEN8_CTX_FORCE_RESTORE (1<<2)
196 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
197 #define GEN8_CTX_PRIVILEGE (1<<8)
199 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
200 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
201 (reg_state)[(pos)+1] = (val); \
204 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
205 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
206 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
207 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
210 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
211 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
212 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
217 FAULT_AND_HALT, /* Debug only */
219 FAULT_AND_CONTINUE /* Unsupported */
221 #define GEN8_CTX_ID_SHIFT 32
222 #define GEN8_CTX_ID_WIDTH 21
223 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
224 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
226 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
227 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
229 #define WA_TAIL_DWORDS 2
231 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
232 struct intel_engine_cs *engine);
233 static void execlists_init_reg_state(u32 *reg_state,
234 struct i915_gem_context *ctx,
235 struct intel_engine_cs *engine,
236 struct intel_ring *ring);
239 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
240 * @dev_priv: i915 device private
241 * @enable_execlists: value of i915.enable_execlists module parameter.
243 * Only certain platforms support Execlists (the prerequisites being
244 * support for Logical Ring Contexts and Aliasing PPGTT or better).
246 * Return: 1 if Execlists is supported and has to be enabled.
248 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
250 /* On platforms with execlist available, vGPU will only
251 * support execlist mode, no ring buffer mode.
253 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
256 if (INTEL_GEN(dev_priv) >= 9)
259 if (enable_execlists == 0)
262 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
263 USES_PPGTT(dev_priv) &&
264 i915.use_mmio_flip >= 0)
271 logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
273 struct drm_i915_private *dev_priv = engine->i915;
275 engine->disable_lite_restore_wa =
276 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
277 (engine->id == VCS || engine->id == VCS2);
279 engine->ctx_desc_template = GEN8_CTX_VALID;
280 if (IS_GEN8(dev_priv))
281 engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
282 engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
284 /* TODO: WaDisableLiteRestore when we start using semaphore
285 * signalling between Command Streamers */
286 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
288 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
289 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
290 if (engine->disable_lite_restore_wa)
291 engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
295 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
296 * descriptor for a pinned context
297 * @ctx: Context to work on
298 * @engine: Engine the descriptor will be used with
300 * The context descriptor encodes various attributes of a context,
301 * including its GTT address and some flags. Because it's fairly
302 * expensive to calculate, we'll just do it once and cache the result,
303 * which remains valid until the context is unpinned.
305 * This is what a descriptor looks like, from LSB to MSB::
307 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
308 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
309 * bits 32-52: ctx ID, a globally unique tag
310 * bits 53-54: mbz, reserved for use by hardware
311 * bits 55-63: group ID, currently unused and set to 0
314 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
315 struct intel_engine_cs *engine)
317 struct intel_context *ce = &ctx->engine[engine->id];
320 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
322 desc = ctx->desc_template; /* bits 3-4 */
323 desc |= engine->ctx_desc_template; /* bits 0-11 */
324 desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE;
326 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
331 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
332 struct intel_engine_cs *engine)
334 return ctx->engine[engine->id].lrc_desc;
338 execlists_context_status_change(struct drm_i915_gem_request *rq,
339 unsigned long status)
342 * Only used when GVT-g is enabled now. When GVT-g is disabled,
343 * The compiler should eliminate this function as dead-code.
345 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
348 atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
352 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
354 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
355 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
356 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
357 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
360 static u64 execlists_update_context(struct drm_i915_gem_request *rq)
362 struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
363 struct i915_hw_ppgtt *ppgtt =
364 rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
365 u32 *reg_state = ce->lrc_reg_state;
367 reg_state[CTX_RING_TAIL+1] = rq->tail;
369 /* True 32b PPGTT with dynamic page allocation: update PDP
370 * registers and point the unallocated PDPs to scratch page.
371 * PML4 is allocated during ppgtt init, so this is not needed
374 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
375 execlists_update_context_pdps(ppgtt, reg_state);
380 static void execlists_submit_ports(struct intel_engine_cs *engine)
382 struct drm_i915_private *dev_priv = engine->i915;
383 struct execlist_port *port = engine->execlist_port;
385 dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
389 execlists_context_status_change(port[0].request,
390 INTEL_CONTEXT_SCHEDULE_IN);
391 desc[0] = execlists_update_context(port[0].request);
392 engine->preempt_wa = port[0].count++; /* bdw only? fixed on skl? */
394 if (port[1].request) {
395 GEM_BUG_ON(port[1].count);
396 execlists_context_status_change(port[1].request,
397 INTEL_CONTEXT_SCHEDULE_IN);
398 desc[1] = execlists_update_context(port[1].request);
403 GEM_BUG_ON(desc[0] == desc[1]);
405 /* You must always write both descriptors in the order below. */
406 writel(upper_32_bits(desc[1]), elsp);
407 writel(lower_32_bits(desc[1]), elsp);
409 writel(upper_32_bits(desc[0]), elsp);
410 /* The context is automatically loaded after the following */
411 writel(lower_32_bits(desc[0]), elsp);
414 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
416 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
417 i915_gem_context_force_single_submission(ctx));
420 static bool can_merge_ctx(const struct i915_gem_context *prev,
421 const struct i915_gem_context *next)
426 if (ctx_single_port_submission(prev))
432 static void execlists_dequeue(struct intel_engine_cs *engine)
434 struct drm_i915_gem_request *last;
435 struct execlist_port *port = engine->execlist_port;
440 last = port->request;
442 /* WaIdleLiteRestore:bdw,skl
443 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
444 * as we resubmit the request. See gen8_emit_breadcrumb()
445 * for where we prepare the padding after the end of the
448 last->tail = last->wa_tail;
450 GEM_BUG_ON(port[1].request);
452 /* Hardware submission is through 2 ports. Conceptually each port
453 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
454 * static for a context, and unique to each, so we only execute
455 * requests belonging to a single context from each ring. RING_HEAD
456 * is maintained by the CS in the context image, it marks the place
457 * where it got up to last time, and through RING_TAIL we tell the CS
458 * where we want to execute up to this time.
460 * In this list the requests are in order of execution. Consecutive
461 * requests from the same context are adjacent in the ringbuffer. We
462 * can combine these requests into a single RING_TAIL update:
464 * RING_HEAD...req1...req2
466 * since to execute req2 the CS must first execute req1.
468 * Our goal then is to point each port to the end of a consecutive
469 * sequence of requests as being the most optimal (fewest wake ups
470 * and context switches) submission.
473 spin_lock_irqsave(&engine->timeline->lock, flags);
474 rb = engine->execlist_first;
476 struct drm_i915_gem_request *cursor =
477 rb_entry(rb, typeof(*cursor), priotree.node);
479 /* Can we combine this request with the current port? It has to
480 * be the same context/ringbuffer and not have any exceptions
481 * (e.g. GVT saying never to combine contexts).
483 * If we can combine the requests, we can execute both by
484 * updating the RING_TAIL to point to the end of the second
485 * request, and so we never need to tell the hardware about
488 if (last && !can_merge_ctx(cursor->ctx, last->ctx)) {
489 /* If we are on the second port and cannot combine
490 * this request with the last, then we are done.
492 if (port != engine->execlist_port)
495 /* If GVT overrides us we only ever submit port[0],
496 * leaving port[1] empty. Note that we also have
497 * to be careful that we don't queue the same
498 * context (even though a different request) to
501 if (ctx_single_port_submission(last->ctx) ||
502 ctx_single_port_submission(cursor->ctx))
505 GEM_BUG_ON(last->ctx == cursor->ctx);
507 i915_gem_request_assign(&port->request, last);
512 rb_erase(&cursor->priotree.node, &engine->execlist_queue);
513 RB_CLEAR_NODE(&cursor->priotree.node);
514 cursor->priotree.priority = INT_MAX;
516 __i915_gem_request_submit(cursor);
521 i915_gem_request_assign(&port->request, last);
522 engine->execlist_first = rb;
524 spin_unlock_irqrestore(&engine->timeline->lock, flags);
527 execlists_submit_ports(engine);
530 static bool execlists_elsp_idle(struct intel_engine_cs *engine)
532 return !engine->execlist_port[0].request;
536 * intel_execlists_idle() - Determine if all engine submission ports are idle
537 * @dev_priv: i915 device private
539 * Return true if there are no requests pending on any of the submission ports
542 bool intel_execlists_idle(struct drm_i915_private *dev_priv)
544 struct intel_engine_cs *engine;
545 enum intel_engine_id id;
547 if (!i915.enable_execlists)
550 for_each_engine(engine, dev_priv, id)
551 if (!execlists_elsp_idle(engine))
557 static bool execlists_elsp_ready(struct intel_engine_cs *engine)
561 port = 1; /* wait for a free slot */
562 if (engine->disable_lite_restore_wa || engine->preempt_wa)
563 port = 0; /* wait for GPU to be idle before continuing */
565 return !engine->execlist_port[port].request;
569 * Check the unread Context Status Buffers and manage the submission of new
570 * contexts to the ELSP accordingly.
572 static void intel_lrc_irq_handler(unsigned long data)
574 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
575 struct execlist_port *port = engine->execlist_port;
576 struct drm_i915_private *dev_priv = engine->i915;
578 intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
580 if (!execlists_elsp_idle(engine)) {
581 u32 __iomem *csb_mmio =
582 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
584 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
585 unsigned int csb, head, tail;
587 csb = readl(csb_mmio);
588 head = GEN8_CSB_READ_PTR(csb);
589 tail = GEN8_CSB_WRITE_PTR(csb);
591 tail += GEN8_CSB_ENTRIES;
592 while (head < tail) {
593 unsigned int idx = ++head % GEN8_CSB_ENTRIES;
594 unsigned int status = readl(buf + 2 * idx);
596 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
599 GEM_BUG_ON(port[0].count == 0);
600 if (--port[0].count == 0) {
601 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
602 execlists_context_status_change(port[0].request,
603 INTEL_CONTEXT_SCHEDULE_OUT);
605 i915_gem_request_put(port[0].request);
607 memset(&port[1], 0, sizeof(port[1]));
609 engine->preempt_wa = false;
612 GEM_BUG_ON(port[0].count == 0 &&
613 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
616 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
617 GEN8_CSB_WRITE_PTR(csb) << 8),
621 if (execlists_elsp_ready(engine))
622 execlists_dequeue(engine);
624 intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
627 static bool insert_request(struct i915_priotree *pt, struct rb_root *root)
629 struct rb_node **p, *rb;
632 /* most positive priority is scheduled first, equal priorities fifo */
636 struct i915_priotree *pos;
639 pos = rb_entry(rb, typeof(*pos), node);
640 if (pt->priority > pos->priority) {
647 rb_link_node(&pt->node, rb, p);
648 rb_insert_color(&pt->node, root);
653 static void execlists_submit_request(struct drm_i915_gem_request *request)
655 struct intel_engine_cs *engine = request->engine;
658 /* Will be called from irq-context when using foreign fences. */
659 spin_lock_irqsave(&engine->timeline->lock, flags);
661 if (insert_request(&request->priotree, &engine->execlist_queue))
662 engine->execlist_first = &request->priotree.node;
663 if (execlists_elsp_idle(engine))
664 tasklet_hi_schedule(&engine->irq_tasklet);
666 spin_unlock_irqrestore(&engine->timeline->lock, flags);
669 static struct intel_engine_cs *
670 pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
672 struct intel_engine_cs *engine;
674 engine = container_of(pt,
675 struct drm_i915_gem_request,
677 if (engine != locked) {
679 spin_unlock_irq(&locked->timeline->lock);
680 spin_lock_irq(&engine->timeline->lock);
686 static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
688 struct intel_engine_cs *engine = NULL;
689 struct i915_dependency *dep, *p;
690 struct i915_dependency stack;
693 if (prio <= READ_ONCE(request->priotree.priority))
696 /* Need BKL in order to use the temporary link inside i915_dependency */
697 lockdep_assert_held(&request->i915->drm.struct_mutex);
699 stack.signaler = &request->priotree;
700 list_add(&stack.dfs_link, &dfs);
702 /* Recursively bump all dependent priorities to match the new request.
704 * A naive approach would be to use recursion:
705 * static void update_priorities(struct i915_priotree *pt, prio) {
706 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
707 * update_priorities(dep->signal, prio)
708 * insert_request(pt);
710 * but that may have unlimited recursion depth and so runs a very
711 * real risk of overunning the kernel stack. Instead, we build
712 * a flat list of all dependencies starting with the current request.
713 * As we walk the list of dependencies, we add all of its dependencies
714 * to the end of the list (this may include an already visited
715 * request) and continue to walk onwards onto the new dependencies. The
716 * end result is a topological list of requests in reverse order, the
717 * last element in the list is the request we must execute first.
719 list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
720 struct i915_priotree *pt = dep->signaler;
722 list_for_each_entry(p, &pt->signalers_list, signal_link)
723 if (prio > READ_ONCE(p->signaler->priority))
724 list_move_tail(&p->dfs_link, &dfs);
726 list_safe_reset_next(dep, p, dfs_link);
727 if (!RB_EMPTY_NODE(&pt->node))
730 engine = pt_lock_engine(pt, engine);
732 /* If it is not already in the rbtree, we can update the
733 * priority inplace and skip over it (and its dependencies)
734 * if it is referenced *again* as we descend the dfs.
736 if (prio > pt->priority && RB_EMPTY_NODE(&pt->node)) {
738 list_del_init(&dep->dfs_link);
742 /* Fifo and depth-first replacement ensure our deps execute before us */
743 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
744 struct i915_priotree *pt = dep->signaler;
746 INIT_LIST_HEAD(&dep->dfs_link);
748 engine = pt_lock_engine(pt, engine);
750 if (prio <= pt->priority)
753 GEM_BUG_ON(RB_EMPTY_NODE(&pt->node));
756 rb_erase(&pt->node, &engine->execlist_queue);
757 if (insert_request(pt, &engine->execlist_queue))
758 engine->execlist_first = &pt->node;
762 spin_unlock_irq(&engine->timeline->lock);
764 /* XXX Do we need to preempt to make room for us and our deps? */
767 static int execlists_context_pin(struct intel_engine_cs *engine,
768 struct i915_gem_context *ctx)
770 struct intel_context *ce = &ctx->engine[engine->id];
775 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
781 ret = execlists_context_deferred_alloc(ctx, engine);
785 GEM_BUG_ON(!ce->state);
788 if (ctx->ggtt_offset_bias)
789 flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
790 if (i915_gem_context_is_kernel(ctx))
793 ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
797 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
799 ret = PTR_ERR(vaddr);
803 ret = intel_ring_pin(ce->ring, ctx->ggtt_offset_bias);
807 intel_lr_context_descriptor_update(ctx, engine);
809 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
810 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
811 i915_ggtt_offset(ce->ring->vma);
813 ce->state->obj->mm.dirty = true;
815 i915_gem_context_get(ctx);
819 i915_gem_object_unpin_map(ce->state->obj);
821 __i915_vma_unpin(ce->state);
827 static void execlists_context_unpin(struct intel_engine_cs *engine,
828 struct i915_gem_context *ctx)
830 struct intel_context *ce = &ctx->engine[engine->id];
832 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
833 GEM_BUG_ON(ce->pin_count == 0);
838 intel_ring_unpin(ce->ring);
840 i915_gem_object_unpin_map(ce->state->obj);
841 i915_vma_unpin(ce->state);
843 i915_gem_context_put(ctx);
846 static int execlists_request_alloc(struct drm_i915_gem_request *request)
848 struct intel_engine_cs *engine = request->engine;
849 struct intel_context *ce = &request->ctx->engine[engine->id];
852 GEM_BUG_ON(!ce->pin_count);
854 /* Flush enough space to reduce the likelihood of waiting after
855 * we start building the request - in which case we will just
856 * have to repeat work.
858 request->reserved_space += EXECLISTS_REQUEST_SIZE;
860 GEM_BUG_ON(!ce->ring);
861 request->ring = ce->ring;
863 if (i915.enable_guc_submission) {
865 * Check that the GuC has space for the request before
866 * going any further, as the i915_add_request() call
867 * later on mustn't fail ...
869 ret = i915_guc_wq_reserve(request);
874 ret = intel_ring_begin(request, 0);
878 if (!ce->initialised) {
879 ret = engine->init_context(request);
883 ce->initialised = true;
886 /* Note that after this point, we have committed to using
887 * this request as it is being used to both track the
888 * state of engine initialisation and liveness of the
889 * golden renderstate above. Think twice before you try
890 * to cancel/unwind this request now.
893 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
897 if (i915.enable_guc_submission)
898 i915_guc_wq_unreserve(request);
903 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
906 struct intel_ring *ring = req->ring;
907 struct i915_workarounds *w = &req->i915->workarounds;
912 ret = req->engine->emit_flush(req, EMIT_BARRIER);
916 ret = intel_ring_begin(req, w->count * 2 + 2);
920 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
921 for (i = 0; i < w->count; i++) {
922 intel_ring_emit_reg(ring, w->reg[i].addr);
923 intel_ring_emit(ring, w->reg[i].value);
925 intel_ring_emit(ring, MI_NOOP);
927 intel_ring_advance(ring);
929 ret = req->engine->emit_flush(req, EMIT_BARRIER);
936 #define wa_ctx_emit(batch, index, cmd) \
938 int __index = (index)++; \
939 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
942 batch[__index] = (cmd); \
945 #define wa_ctx_emit_reg(batch, index, reg) \
946 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
949 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
950 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
951 * but there is a slight complication as this is applied in WA batch where the
952 * values are only initialized once so we cannot take register value at the
953 * beginning and reuse it further; hence we save its value to memory, upload a
954 * constant value with bit21 set and then we restore it back with the saved value.
955 * To simplify the WA, a constant value is formed by using the default value
956 * of this register. This shouldn't be a problem because we are only modifying
957 * it for a short period and this batch in non-premptible. We can ofcourse
958 * use additional instructions that read the actual value of the register
959 * at that time and set our bit of interest but it makes the WA complicated.
961 * This WA is also required for Gen9 so extracting as a function avoids
964 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
968 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
970 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
971 MI_SRM_LRM_GLOBAL_GTT));
972 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
973 wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256);
974 wa_ctx_emit(batch, index, 0);
976 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
977 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
978 wa_ctx_emit(batch, index, l3sqc4_flush);
980 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
981 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
982 PIPE_CONTROL_DC_FLUSH_ENABLE));
983 wa_ctx_emit(batch, index, 0);
984 wa_ctx_emit(batch, index, 0);
985 wa_ctx_emit(batch, index, 0);
986 wa_ctx_emit(batch, index, 0);
988 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
989 MI_SRM_LRM_GLOBAL_GTT));
990 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
991 wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256);
992 wa_ctx_emit(batch, index, 0);
997 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
999 uint32_t start_alignment)
1001 return wa_ctx->offset = ALIGN(offset, start_alignment);
1004 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1006 uint32_t size_alignment)
1008 wa_ctx->size = offset - wa_ctx->offset;
1010 WARN(wa_ctx->size % size_alignment,
1011 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1012 wa_ctx->size, size_alignment);
1017 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1018 * initialized at the beginning and shared across all contexts but this field
1019 * helps us to have multiple batches at different offsets and select them based
1020 * on a criteria. At the moment this batch always start at the beginning of the page
1021 * and at this point we don't have multiple wa_ctx batch buffers.
1023 * The number of WA applied are not known at the beginning; we use this field
1024 * to return the no of DWORDS written.
1026 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1027 * so it adds NOOPs as padding to make it cacheline aligned.
1028 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1029 * makes a complete batch buffer.
1031 static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1032 struct i915_wa_ctx_bb *wa_ctx,
1036 uint32_t scratch_addr;
1037 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1039 /* WaDisableCtxRestoreArbitration:bdw,chv */
1040 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1042 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1043 if (IS_BROADWELL(engine->i915)) {
1044 int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1050 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1051 /* Actual scratch location is at 128 bytes offset */
1052 scratch_addr = i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1054 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1055 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1056 PIPE_CONTROL_GLOBAL_GTT_IVB |
1057 PIPE_CONTROL_CS_STALL |
1058 PIPE_CONTROL_QW_WRITE));
1059 wa_ctx_emit(batch, index, scratch_addr);
1060 wa_ctx_emit(batch, index, 0);
1061 wa_ctx_emit(batch, index, 0);
1062 wa_ctx_emit(batch, index, 0);
1064 /* Pad to end of cacheline */
1065 while (index % CACHELINE_DWORDS)
1066 wa_ctx_emit(batch, index, MI_NOOP);
1069 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1070 * execution depends on the length specified in terms of cache lines
1071 * in the register CTX_RCS_INDIRECT_CTX
1074 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1078 * This batch is started immediately after indirect_ctx batch. Since we ensure
1079 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1081 * The number of DWORDS written are returned using this field.
1083 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1084 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1086 static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1087 struct i915_wa_ctx_bb *wa_ctx,
1091 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1093 /* WaDisableCtxRestoreArbitration:bdw,chv */
1094 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1096 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1098 return wa_ctx_end(wa_ctx, *offset = index, 1);
1101 static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1102 struct i915_wa_ctx_bb *wa_ctx,
1107 struct drm_i915_private *dev_priv = engine->i915;
1108 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1110 /* WaDisableCtxRestoreArbitration:bxt */
1111 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1112 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1114 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1115 ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1120 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */
1121 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1122 wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2);
1123 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(
1124 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE));
1125 wa_ctx_emit(batch, index, MI_NOOP);
1127 /* WaClearSlmSpaceAtContextSwitch:kbl */
1128 /* Actual scratch location is at 128 bytes offset */
1129 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
1131 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1133 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1134 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1135 PIPE_CONTROL_GLOBAL_GTT_IVB |
1136 PIPE_CONTROL_CS_STALL |
1137 PIPE_CONTROL_QW_WRITE));
1138 wa_ctx_emit(batch, index, scratch_addr);
1139 wa_ctx_emit(batch, index, 0);
1140 wa_ctx_emit(batch, index, 0);
1141 wa_ctx_emit(batch, index, 0);
1144 /* WaMediaPoolStateCmdInWABB:bxt */
1145 if (HAS_POOLED_EU(engine->i915)) {
1147 * EU pool configuration is setup along with golden context
1148 * during context initialization. This value depends on
1149 * device type (2x6 or 3x6) and needs to be updated based
1150 * on which subslice is disabled especially for 2x6
1151 * devices, however it is safe to load default
1152 * configuration of 3x6 device instead of masking off
1153 * corresponding bits because HW ignores bits of a disabled
1154 * subslice and drops down to appropriate config. Please
1155 * see render_state_setup() in i915_gem_render_state.c for
1156 * possible configurations, to avoid duplication they are
1157 * not shown here again.
1159 u32 eu_pool_config = 0x00777000;
1160 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
1161 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
1162 wa_ctx_emit(batch, index, eu_pool_config);
1163 wa_ctx_emit(batch, index, 0);
1164 wa_ctx_emit(batch, index, 0);
1165 wa_ctx_emit(batch, index, 0);
1168 /* Pad to end of cacheline */
1169 while (index % CACHELINE_DWORDS)
1170 wa_ctx_emit(batch, index, MI_NOOP);
1172 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1175 static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1176 struct i915_wa_ctx_bb *wa_ctx,
1180 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1182 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
1183 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
1184 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1185 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1186 wa_ctx_emit(batch, index,
1187 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1188 wa_ctx_emit(batch, index, MI_NOOP);
1191 /* WaClearTdlStateAckDirtyBits:bxt */
1192 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
1193 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
1195 wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
1196 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1198 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1);
1199 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1201 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2);
1202 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1204 wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2);
1205 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1206 wa_ctx_emit(batch, index, 0x0);
1207 wa_ctx_emit(batch, index, MI_NOOP);
1210 /* WaDisableCtxRestoreArbitration:bxt */
1211 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1212 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1214 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1216 return wa_ctx_end(wa_ctx, *offset = index, 1);
1219 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1221 struct drm_i915_gem_object *obj;
1222 struct i915_vma *vma;
1225 obj = i915_gem_object_create(engine->i915, PAGE_ALIGN(size));
1227 return PTR_ERR(obj);
1229 vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
1235 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1239 engine->wa_ctx.vma = vma;
1243 i915_gem_object_put(obj);
1247 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1249 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1252 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1254 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1260 WARN_ON(engine->id != RCS);
1262 /* update this when WA for higher Gen are added */
1263 if (INTEL_GEN(engine->i915) > 9) {
1264 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1265 INTEL_GEN(engine->i915));
1269 /* some WA perform writes to scratch page, ensure it is valid */
1270 if (!engine->scratch) {
1271 DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1275 ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1277 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1281 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1282 batch = kmap_atomic(page);
1285 if (IS_GEN8(engine->i915)) {
1286 ret = gen8_init_indirectctx_bb(engine,
1287 &wa_ctx->indirect_ctx,
1293 ret = gen8_init_perctx_bb(engine,
1299 } else if (IS_GEN9(engine->i915)) {
1300 ret = gen9_init_indirectctx_bb(engine,
1301 &wa_ctx->indirect_ctx,
1307 ret = gen9_init_perctx_bb(engine,
1316 kunmap_atomic(batch);
1318 lrc_destroy_wa_ctx_obj(engine);
1323 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1325 struct drm_i915_private *dev_priv = engine->i915;
1328 ret = intel_mocs_init_engine(engine);
1332 intel_engine_reset_breadcrumbs(engine);
1333 intel_engine_init_hangcheck(engine);
1335 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1336 I915_WRITE(RING_MODE_GEN7(engine),
1337 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1338 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1339 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1340 engine->status_page.ggtt_offset);
1341 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1343 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1345 /* After a GPU reset, we may have requests to replay */
1346 if (!execlists_elsp_idle(engine)) {
1347 engine->execlist_port[0].count = 0;
1348 engine->execlist_port[1].count = 0;
1349 execlists_submit_ports(engine);
1355 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1357 struct drm_i915_private *dev_priv = engine->i915;
1360 ret = gen8_init_common_ring(engine);
1364 /* We need to disable the AsyncFlip performance optimisations in order
1365 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1366 * programmed to '1' on all products.
1368 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1370 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1372 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1374 return init_workarounds_ring(engine);
1377 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1381 ret = gen8_init_common_ring(engine);
1385 return init_workarounds_ring(engine);
1388 static void reset_common_ring(struct intel_engine_cs *engine,
1389 struct drm_i915_gem_request *request)
1391 struct drm_i915_private *dev_priv = engine->i915;
1392 struct execlist_port *port = engine->execlist_port;
1393 struct intel_context *ce;
1395 /* If the request was innocent, we leave the request in the ELSP
1396 * and will try to replay it on restarting. The context image may
1397 * have been corrupted by the reset, in which case we may have
1398 * to service a new GPU hang, but more likely we can continue on
1401 * If the request was guilty, we presume the context is corrupt
1402 * and have to at least restore the RING register in the context
1403 * image back to the expected values to skip over the guilty request.
1405 if (!request || request->fence.error != -EIO)
1408 /* We want a simple context + ring to execute the breadcrumb update.
1409 * We cannot rely on the context being intact across the GPU hang,
1410 * so clear it and rebuild just what we need for the breadcrumb.
1411 * All pending requests for this context will be zapped, and any
1412 * future request will be after userspace has had the opportunity
1413 * to recreate its own state.
1415 ce = &request->ctx->engine[engine->id];
1416 execlists_init_reg_state(ce->lrc_reg_state,
1417 request->ctx, engine, ce->ring);
1419 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1420 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1421 i915_ggtt_offset(ce->ring->vma);
1422 ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
1424 request->ring->head = request->postfix;
1425 request->ring->last_retired_head = -1;
1426 intel_ring_update_space(request->ring);
1428 if (i915.enable_guc_submission)
1431 /* Catch up with any missed context-switch interrupts */
1432 I915_WRITE(RING_CONTEXT_STATUS_PTR(engine), _MASKED_FIELD(0xffff, 0));
1433 if (request->ctx != port[0].request->ctx) {
1434 i915_gem_request_put(port[0].request);
1436 memset(&port[1], 0, sizeof(port[1]));
1439 GEM_BUG_ON(request->ctx != port[0].request->ctx);
1441 /* Reset WaIdleLiteRestore:bdw,skl as well */
1442 request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
1445 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1447 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1448 struct intel_ring *ring = req->ring;
1449 struct intel_engine_cs *engine = req->engine;
1450 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1453 ret = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1457 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1458 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1459 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1461 intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i));
1462 intel_ring_emit(ring, upper_32_bits(pd_daddr));
1463 intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i));
1464 intel_ring_emit(ring, lower_32_bits(pd_daddr));
1467 intel_ring_emit(ring, MI_NOOP);
1468 intel_ring_advance(ring);
1473 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1474 u64 offset, u32 len,
1475 unsigned int dispatch_flags)
1477 struct intel_ring *ring = req->ring;
1478 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1481 /* Don't rely in hw updating PDPs, specially in lite-restore.
1482 * Ideally, we should set Force PD Restore in ctx descriptor,
1483 * but we can't. Force Restore would be a second option, but
1484 * it is unsafe in case of lite-restore (because the ctx is
1485 * not idle). PML4 is allocated during ppgtt init so this is
1486 * not needed in 48-bit.*/
1487 if (req->ctx->ppgtt &&
1488 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1489 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1490 !intel_vgpu_active(req->i915)) {
1491 ret = intel_logical_ring_emit_pdps(req);
1496 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1499 ret = intel_ring_begin(req, 4);
1503 /* FIXME(BDW): Address space and security selectors. */
1504 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 |
1506 (dispatch_flags & I915_DISPATCH_RS ?
1507 MI_BATCH_RESOURCE_STREAMER : 0));
1508 intel_ring_emit(ring, lower_32_bits(offset));
1509 intel_ring_emit(ring, upper_32_bits(offset));
1510 intel_ring_emit(ring, MI_NOOP);
1511 intel_ring_advance(ring);
1516 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1518 struct drm_i915_private *dev_priv = engine->i915;
1519 I915_WRITE_IMR(engine,
1520 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1521 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1524 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1526 struct drm_i915_private *dev_priv = engine->i915;
1527 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1530 static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1532 struct intel_ring *ring = request->ring;
1536 ret = intel_ring_begin(request, 4);
1540 cmd = MI_FLUSH_DW + 1;
1542 /* We always require a command barrier so that subsequent
1543 * commands, such as breadcrumb interrupts, are strictly ordered
1544 * wrt the contents of the write cache being flushed to memory
1545 * (and thus being coherent from the CPU).
1547 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1549 if (mode & EMIT_INVALIDATE) {
1550 cmd |= MI_INVALIDATE_TLB;
1551 if (request->engine->id == VCS)
1552 cmd |= MI_INVALIDATE_BSD;
1555 intel_ring_emit(ring, cmd);
1556 intel_ring_emit(ring,
1557 I915_GEM_HWS_SCRATCH_ADDR |
1558 MI_FLUSH_DW_USE_GTT);
1559 intel_ring_emit(ring, 0); /* upper addr */
1560 intel_ring_emit(ring, 0); /* value */
1561 intel_ring_advance(ring);
1566 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1569 struct intel_ring *ring = request->ring;
1570 struct intel_engine_cs *engine = request->engine;
1572 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1573 bool vf_flush_wa = false, dc_flush_wa = false;
1578 flags |= PIPE_CONTROL_CS_STALL;
1580 if (mode & EMIT_FLUSH) {
1581 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1582 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1583 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1584 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1587 if (mode & EMIT_INVALIDATE) {
1588 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1589 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1590 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1591 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1592 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1593 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1594 flags |= PIPE_CONTROL_QW_WRITE;
1595 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1598 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1601 if (IS_GEN9(request->i915))
1604 /* WaForGAMHang:kbl */
1605 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1617 ret = intel_ring_begin(request, len);
1622 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1623 intel_ring_emit(ring, 0);
1624 intel_ring_emit(ring, 0);
1625 intel_ring_emit(ring, 0);
1626 intel_ring_emit(ring, 0);
1627 intel_ring_emit(ring, 0);
1631 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1632 intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE);
1633 intel_ring_emit(ring, 0);
1634 intel_ring_emit(ring, 0);
1635 intel_ring_emit(ring, 0);
1636 intel_ring_emit(ring, 0);
1639 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1640 intel_ring_emit(ring, flags);
1641 intel_ring_emit(ring, scratch_addr);
1642 intel_ring_emit(ring, 0);
1643 intel_ring_emit(ring, 0);
1644 intel_ring_emit(ring, 0);
1647 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1648 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL);
1649 intel_ring_emit(ring, 0);
1650 intel_ring_emit(ring, 0);
1651 intel_ring_emit(ring, 0);
1652 intel_ring_emit(ring, 0);
1655 intel_ring_advance(ring);
1660 static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
1663 * On BXT A steppings there is a HW coherency issue whereby the
1664 * MI_STORE_DATA_IMM storing the completed request's seqno
1665 * occasionally doesn't invalidate the CPU cache. Work around this by
1666 * clflushing the corresponding cacheline whenever the caller wants
1667 * the coherency to be guaranteed. Note that this cacheline is known
1668 * to be clean at this point, since we only write it in
1669 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1670 * this clflush in practice becomes an invalidate operation.
1672 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1676 * Reserve space for 2 NOOPs at the end of each request to be
1677 * used as a workaround for not being allowed to do lite
1678 * restore with HEAD==TAIL (WaIdleLiteRestore).
1680 static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *out)
1684 request->wa_tail = intel_ring_offset(request->ring, out);
1687 static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request,
1690 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1691 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1693 *out++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
1694 *out++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT;
1696 *out++ = request->global_seqno;
1697 *out++ = MI_USER_INTERRUPT;
1699 request->tail = intel_ring_offset(request->ring, out);
1701 gen8_emit_wa_tail(request, out);
1704 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
1706 static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request,
1709 /* We're using qword write, seqno should be aligned to 8 bytes. */
1710 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1712 /* w/a for post sync ops following a GPGPU operation we
1713 * need a prior CS_STALL, which is emitted by the flush
1714 * following the batch.
1716 *out++ = GFX_OP_PIPE_CONTROL(6);
1717 *out++ = (PIPE_CONTROL_GLOBAL_GTT_IVB |
1718 PIPE_CONTROL_CS_STALL |
1719 PIPE_CONTROL_QW_WRITE);
1720 *out++ = intel_hws_seqno_address(request->engine);
1722 *out++ = request->global_seqno;
1723 /* We're thrashing one dword of HWS. */
1725 *out++ = MI_USER_INTERRUPT;
1727 request->tail = intel_ring_offset(request->ring, out);
1729 gen8_emit_wa_tail(request, out);
1732 static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS;
1734 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1738 ret = intel_logical_ring_workarounds_emit(req);
1742 ret = intel_rcs_context_init_mocs(req);
1744 * Failing to program the MOCS is non-fatal.The system will not
1745 * run at peak performance. So generate an error and carry on.
1748 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1750 return i915_gem_render_state_emit(req);
1754 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1755 * @engine: Engine Command Streamer.
1757 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1759 struct drm_i915_private *dev_priv;
1762 * Tasklet cannot be active at this point due intel_mark_active/idle
1763 * so this is just for documentation.
1765 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
1766 tasklet_kill(&engine->irq_tasklet);
1768 dev_priv = engine->i915;
1770 if (engine->buffer) {
1771 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1774 if (engine->cleanup)
1775 engine->cleanup(engine);
1777 if (engine->status_page.vma) {
1778 i915_gem_object_unpin_map(engine->status_page.vma->obj);
1779 engine->status_page.vma = NULL;
1782 intel_engine_cleanup_common(engine);
1784 lrc_destroy_wa_ctx_obj(engine);
1785 engine->i915 = NULL;
1786 dev_priv->engine[engine->id] = NULL;
1790 void intel_execlists_enable_submission(struct drm_i915_private *dev_priv)
1792 struct intel_engine_cs *engine;
1793 enum intel_engine_id id;
1795 for_each_engine(engine, dev_priv, id) {
1796 engine->submit_request = execlists_submit_request;
1797 engine->schedule = execlists_schedule;
1802 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1804 /* Default vfuncs which can be overriden by each engine. */
1805 engine->init_hw = gen8_init_common_ring;
1806 engine->reset_hw = reset_common_ring;
1808 engine->context_pin = execlists_context_pin;
1809 engine->context_unpin = execlists_context_unpin;
1811 engine->request_alloc = execlists_request_alloc;
1813 engine->emit_flush = gen8_emit_flush;
1814 engine->emit_breadcrumb = gen8_emit_breadcrumb;
1815 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
1816 engine->submit_request = execlists_submit_request;
1817 engine->schedule = execlists_schedule;
1819 engine->irq_enable = gen8_logical_ring_enable_irq;
1820 engine->irq_disable = gen8_logical_ring_disable_irq;
1821 engine->emit_bb_start = gen8_emit_bb_start;
1822 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1823 engine->irq_seqno_barrier = bxt_a_seqno_barrier;
1827 logical_ring_default_irqs(struct intel_engine_cs *engine)
1829 unsigned shift = engine->irq_shift;
1830 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1831 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1835 lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
1837 const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
1840 /* The HWSP is part of the default context object in LRC mode. */
1841 hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1843 return PTR_ERR(hws);
1845 engine->status_page.page_addr = hws + hws_offset;
1846 engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset;
1847 engine->status_page.vma = vma;
1853 logical_ring_setup(struct intel_engine_cs *engine)
1855 struct drm_i915_private *dev_priv = engine->i915;
1856 enum forcewake_domains fw_domains;
1858 intel_engine_setup_common(engine);
1860 /* Intentionally left blank. */
1861 engine->buffer = NULL;
1863 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1867 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1868 RING_CONTEXT_STATUS_PTR(engine),
1869 FW_REG_READ | FW_REG_WRITE);
1871 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1872 RING_CONTEXT_STATUS_BUF_BASE(engine),
1875 engine->fw_domains = fw_domains;
1877 tasklet_init(&engine->irq_tasklet,
1878 intel_lrc_irq_handler, (unsigned long)engine);
1880 logical_ring_init_platform_invariants(engine);
1881 logical_ring_default_vfuncs(engine);
1882 logical_ring_default_irqs(engine);
1886 logical_ring_init(struct intel_engine_cs *engine)
1888 struct i915_gem_context *dctx = engine->i915->kernel_context;
1891 ret = intel_engine_init_common(engine);
1895 /* And setup the hardware status page. */
1896 ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
1898 DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
1905 intel_logical_ring_cleanup(engine);
1909 int logical_render_ring_init(struct intel_engine_cs *engine)
1911 struct drm_i915_private *dev_priv = engine->i915;
1914 logical_ring_setup(engine);
1916 if (HAS_L3_DPF(dev_priv))
1917 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1919 /* Override some for render ring. */
1920 if (INTEL_GEN(dev_priv) >= 9)
1921 engine->init_hw = gen9_init_render_ring;
1923 engine->init_hw = gen8_init_render_ring;
1924 engine->init_context = gen8_init_rcs_context;
1925 engine->emit_flush = gen8_emit_flush_render;
1926 engine->emit_breadcrumb = gen8_emit_breadcrumb_render;
1927 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz;
1929 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
1933 ret = intel_init_workaround_bb(engine);
1936 * We continue even if we fail to initialize WA batch
1937 * because we only expect rare glitches but nothing
1938 * critical to prevent us from using GPU
1940 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1944 return logical_ring_init(engine);
1947 int logical_xcs_ring_init(struct intel_engine_cs *engine)
1949 logical_ring_setup(engine);
1951 return logical_ring_init(engine);
1955 make_rpcs(struct drm_i915_private *dev_priv)
1960 * No explicit RPCS request is needed to ensure full
1961 * slice/subslice/EU enablement prior to Gen9.
1963 if (INTEL_GEN(dev_priv) < 9)
1967 * Starting in Gen9, render power gating can leave
1968 * slice/subslice/EU in a partially enabled state. We
1969 * must make an explicit request through RPCS for full
1972 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
1973 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1974 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
1975 GEN8_RPCS_S_CNT_SHIFT;
1976 rpcs |= GEN8_RPCS_ENABLE;
1979 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
1980 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1981 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
1982 GEN8_RPCS_SS_CNT_SHIFT;
1983 rpcs |= GEN8_RPCS_ENABLE;
1986 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
1987 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1988 GEN8_RPCS_EU_MIN_SHIFT;
1989 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1990 GEN8_RPCS_EU_MAX_SHIFT;
1991 rpcs |= GEN8_RPCS_ENABLE;
1997 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
1999 u32 indirect_ctx_offset;
2001 switch (INTEL_GEN(engine->i915)) {
2003 MISSING_CASE(INTEL_GEN(engine->i915));
2006 indirect_ctx_offset =
2007 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2010 indirect_ctx_offset =
2011 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2015 return indirect_ctx_offset;
2018 static void execlists_init_reg_state(u32 *reg_state,
2019 struct i915_gem_context *ctx,
2020 struct intel_engine_cs *engine,
2021 struct intel_ring *ring)
2023 struct drm_i915_private *dev_priv = engine->i915;
2024 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
2026 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2027 * commands followed by (reg, value) pairs. The values we are setting here are
2028 * only for the first context restore: on a subsequent save, the GPU will
2029 * recreate this batchbuffer with new values (including all the missing
2030 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2031 reg_state[CTX_LRI_HEADER_0] =
2032 MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
2033 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
2034 RING_CONTEXT_CONTROL(engine),
2035 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2036 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2037 (HAS_RESOURCE_STREAMER(dev_priv) ?
2038 CTX_CTRL_RS_CTX_ENABLE : 0)));
2039 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
2041 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
2043 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
2044 RING_START(engine->mmio_base), 0);
2045 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
2046 RING_CTL(engine->mmio_base),
2047 RING_CTL_SIZE(ring->size) | RING_VALID);
2048 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
2049 RING_BBADDR_UDW(engine->mmio_base), 0);
2050 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
2051 RING_BBADDR(engine->mmio_base), 0);
2052 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
2053 RING_BBSTATE(engine->mmio_base),
2055 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
2056 RING_SBBADDR_UDW(engine->mmio_base), 0);
2057 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
2058 RING_SBBADDR(engine->mmio_base), 0);
2059 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
2060 RING_SBBSTATE(engine->mmio_base), 0);
2061 if (engine->id == RCS) {
2062 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
2063 RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
2064 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
2065 RING_INDIRECT_CTX(engine->mmio_base), 0);
2066 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
2067 RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2068 if (engine->wa_ctx.vma) {
2069 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2070 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2072 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2073 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2074 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2076 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2077 intel_lr_indirect_ctx_offset(engine) << 6;
2079 reg_state[CTX_BB_PER_CTX_PTR+1] =
2080 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2084 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2085 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
2086 RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2087 /* PDP values well be assigned later if needed */
2088 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
2090 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
2092 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
2094 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
2096 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
2098 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
2100 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
2102 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
2105 if (ppgtt && USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2106 /* 64b PPGTT (48bit canonical)
2107 * PDP0_DESCRIPTOR contains the base address to PML4 and
2108 * other PDP Descriptors are ignored.
2110 ASSIGN_CTX_PML4(ppgtt, reg_state);
2113 if (engine->id == RCS) {
2114 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2115 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2116 make_rpcs(dev_priv));
2121 populate_lr_context(struct i915_gem_context *ctx,
2122 struct drm_i915_gem_object *ctx_obj,
2123 struct intel_engine_cs *engine,
2124 struct intel_ring *ring)
2129 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2131 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2135 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2136 if (IS_ERR(vaddr)) {
2137 ret = PTR_ERR(vaddr);
2138 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2141 ctx_obj->mm.dirty = true;
2143 /* The second page of the context object contains some fields which must
2144 * be set up prior to the first execution. */
2146 execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
2149 i915_gem_object_unpin_map(ctx_obj);
2155 * intel_lr_context_size() - return the size of the context for an engine
2156 * @engine: which engine to find the context size for
2158 * Each engine may require a different amount of space for a context image,
2159 * so when allocating (or copying) an image, this function can be used to
2160 * find the right size for the specific engine.
2162 * Return: size (in bytes) of an engine-specific context image
2164 * Note: this size includes the HWSP, which is part of the context image
2165 * in LRC mode, but does not include the "shared data page" used with
2166 * GuC submission. The caller should account for this if using the GuC.
2168 uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2172 WARN_ON(INTEL_GEN(engine->i915) < 8);
2174 switch (engine->id) {
2176 if (INTEL_GEN(engine->i915) >= 9)
2177 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2179 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2185 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2192 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2193 struct intel_engine_cs *engine)
2195 struct drm_i915_gem_object *ctx_obj;
2196 struct intel_context *ce = &ctx->engine[engine->id];
2197 struct i915_vma *vma;
2198 uint32_t context_size;
2199 struct intel_ring *ring;
2204 context_size = round_up(intel_lr_context_size(engine),
2205 I915_GTT_PAGE_SIZE);
2207 /* One extra page as the sharing data between driver and GuC */
2208 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2210 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2211 if (IS_ERR(ctx_obj)) {
2212 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2213 return PTR_ERR(ctx_obj);
2216 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL);
2219 goto error_deref_obj;
2222 ring = intel_engine_create_ring(engine, ctx->ring_size);
2224 ret = PTR_ERR(ring);
2225 goto error_deref_obj;
2228 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2230 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2231 goto error_ring_free;
2236 ce->initialised = engine->init_context == NULL;
2241 intel_ring_free(ring);
2243 i915_gem_object_put(ctx_obj);
2247 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2249 struct intel_engine_cs *engine;
2250 struct i915_gem_context *ctx;
2251 enum intel_engine_id id;
2253 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2254 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2255 * that stored in context. As we only write new commands from
2256 * ce->ring->tail onwards, everything before that is junk. If the GPU
2257 * starts reading from its RING_HEAD from the context, it may try to
2258 * execute that junk and die.
2260 * So to avoid that we reset the context images upon resume. For
2261 * simplicity, we just zero everything out.
2263 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2264 for_each_engine(engine, dev_priv, id) {
2265 struct intel_context *ce = &ctx->engine[engine->id];
2271 reg = i915_gem_object_pin_map(ce->state->obj,
2273 if (WARN_ON(IS_ERR(reg)))
2276 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2277 reg[CTX_RING_HEAD+1] = 0;
2278 reg[CTX_RING_TAIL+1] = 0;
2280 ce->state->obj->mm.dirty = true;
2281 i915_gem_object_unpin_map(ce->state->obj);
2283 ce->ring->head = ce->ring->tail = 0;
2284 ce->ring->last_retired_head = -1;
2285 intel_ring_update_space(ce->ring);