2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_ALIGN 4096
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 ADVANCED_CONTEXT = 0,
198 #define GEN8_CTX_MODE_SHIFT 3
201 FAULT_AND_HALT, /* Debug only */
203 FAULT_AND_CONTINUE /* Unsupported */
205 #define GEN8_CTX_ID_SHIFT 32
208 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
210 * @enable_execlists: value of i915.enable_execlists module parameter.
212 * Only certain platforms support Execlists (the prerequisites being
213 * support for Logical Ring Contexts and Aliasing PPGTT or better),
214 * and only when enabled via module parameter.
216 * Return: 1 if Execlists is supported and has to be enabled.
218 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
220 WARN_ON(i915.enable_ppgtt == -1);
222 if (enable_execlists == 0)
225 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
226 i915.use_mmio_flip >= 0)
233 * intel_execlists_ctx_id() - get the Execlists Context ID
234 * @ctx_obj: Logical Ring Context backing object.
236 * Do not confuse with ctx->id! Unfortunately we have a name overload
237 * here: the old context ID we pass to userspace as a handler so that
238 * they can refer to a context, and the new context ID we pass to the
239 * ELSP so that the GPU can inform us of the context status via
242 * Return: 20-bits globally unique context ID.
244 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
246 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
248 /* LRCA is required to be 4K aligned so the more significant 20 bits
249 * are globally unique */
253 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
256 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
258 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
260 desc = GEN8_CTX_VALID;
261 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
262 desc |= GEN8_CTX_L3LLC_COHERENT;
263 desc |= GEN8_CTX_PRIVILEGE;
265 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
267 /* TODO: WaDisableLiteRestore when we start using semaphore
268 * signalling between Command Streamers */
269 /* desc |= GEN8_CTX_FORCE_RESTORE; */
274 static void execlists_elsp_write(struct intel_engine_cs *ring,
275 struct drm_i915_gem_object *ctx_obj0,
276 struct drm_i915_gem_object *ctx_obj1)
278 struct drm_i915_private *dev_priv = ring->dev->dev_private;
283 /* XXX: You must always write both descriptors in the order below. */
285 temp = execlists_ctx_descriptor(ctx_obj1);
288 desc[1] = (u32)(temp >> 32);
291 temp = execlists_ctx_descriptor(ctx_obj0);
292 desc[3] = (u32)(temp >> 32);
295 /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
298 * The other problem is that we can't just call gen6_gt_force_wake_get()
299 * because that function calls intel_runtime_pm_get(), which might sleep.
300 * Instead, we do the runtime_pm_get/put when creating/destroying requests.
302 spin_lock_irqsave(&dev_priv->uncore.lock, flags);
303 if (IS_CHERRYVIEW(dev_priv->dev)) {
304 if (dev_priv->uncore.fw_rendercount++ == 0)
305 dev_priv->uncore.funcs.force_wake_get(dev_priv,
307 if (dev_priv->uncore.fw_mediacount++ == 0)
308 dev_priv->uncore.funcs.force_wake_get(dev_priv,
311 if (dev_priv->uncore.forcewake_count++ == 0)
312 dev_priv->uncore.funcs.force_wake_get(dev_priv,
315 spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
317 I915_WRITE(RING_ELSP(ring), desc[1]);
318 I915_WRITE(RING_ELSP(ring), desc[0]);
319 I915_WRITE(RING_ELSP(ring), desc[3]);
320 /* The context is automatically loaded after the following */
321 I915_WRITE(RING_ELSP(ring), desc[2]);
323 /* ELSP is a wo register, so use another nearby reg for posting instead */
324 POSTING_READ(RING_EXECLIST_STATUS(ring));
326 /* Release Force Wakeup (see the big comment above). */
327 spin_lock_irqsave(&dev_priv->uncore.lock, flags);
328 if (IS_CHERRYVIEW(dev_priv->dev)) {
329 if (--dev_priv->uncore.fw_rendercount == 0)
330 dev_priv->uncore.funcs.force_wake_put(dev_priv,
332 if (--dev_priv->uncore.fw_mediacount == 0)
333 dev_priv->uncore.funcs.force_wake_put(dev_priv,
336 if (--dev_priv->uncore.forcewake_count == 0)
337 dev_priv->uncore.funcs.force_wake_put(dev_priv,
341 spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
344 static int execlists_ctx_write_tail(struct drm_i915_gem_object *ctx_obj, u32 tail)
349 page = i915_gem_object_get_page(ctx_obj, 1);
350 reg_state = kmap_atomic(page);
352 reg_state[CTX_RING_TAIL+1] = tail;
354 kunmap_atomic(reg_state);
359 static void execlists_submit_contexts(struct intel_engine_cs *ring,
360 struct intel_context *to0, u32 tail0,
361 struct intel_context *to1, u32 tail1)
363 struct drm_i915_gem_object *ctx_obj0;
364 struct drm_i915_gem_object *ctx_obj1 = NULL;
366 ctx_obj0 = to0->engine[ring->id].state;
368 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
370 execlists_ctx_write_tail(ctx_obj0, tail0);
373 ctx_obj1 = to1->engine[ring->id].state;
375 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
377 execlists_ctx_write_tail(ctx_obj1, tail1);
380 execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
383 static void execlists_context_unqueue(struct intel_engine_cs *ring)
385 struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL;
386 struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL;
387 struct drm_i915_private *dev_priv = ring->dev->dev_private;
389 assert_spin_locked(&ring->execlist_lock);
391 if (list_empty(&ring->execlist_queue))
394 /* Try to read in pairs */
395 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
399 } else if (req0->ctx == cursor->ctx) {
400 /* Same ctx: ignore first request, as second request
401 * will update tail past first request's workload */
402 cursor->elsp_submitted = req0->elsp_submitted;
403 list_del(&req0->execlist_link);
404 queue_work(dev_priv->wq, &req0->work);
412 WARN_ON(req1 && req1->elsp_submitted);
414 execlists_submit_contexts(ring, req0->ctx, req0->tail,
415 req1 ? req1->ctx : NULL,
416 req1 ? req1->tail : 0);
418 req0->elsp_submitted++;
420 req1->elsp_submitted++;
423 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
426 struct drm_i915_private *dev_priv = ring->dev->dev_private;
427 struct intel_ctx_submit_request *head_req;
429 assert_spin_locked(&ring->execlist_lock);
431 head_req = list_first_entry_or_null(&ring->execlist_queue,
432 struct intel_ctx_submit_request,
435 if (head_req != NULL) {
436 struct drm_i915_gem_object *ctx_obj =
437 head_req->ctx->engine[ring->id].state;
438 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
439 WARN(head_req->elsp_submitted == 0,
440 "Never submitted head request\n");
442 if (--head_req->elsp_submitted <= 0) {
443 list_del(&head_req->execlist_link);
444 queue_work(dev_priv->wq, &head_req->work);
454 * intel_execlists_handle_ctx_events() - handle Context Switch interrupts
455 * @ring: Engine Command Streamer to handle.
457 * Check the unread Context Status Buffers and manage the submission of new
458 * contexts to the ELSP accordingly.
460 void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring)
462 struct drm_i915_private *dev_priv = ring->dev->dev_private;
468 u32 submit_contexts = 0;
470 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
472 read_pointer = ring->next_context_status_buffer;
473 write_pointer = status_pointer & 0x07;
474 if (read_pointer > write_pointer)
477 spin_lock(&ring->execlist_lock);
479 while (read_pointer < write_pointer) {
481 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
482 (read_pointer % 6) * 8);
483 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
484 (read_pointer % 6) * 8 + 4);
486 if (status & GEN8_CTX_STATUS_PREEMPTED) {
487 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
488 if (execlists_check_remove_request(ring, status_id))
489 WARN(1, "Lite Restored request removed from queue\n");
491 WARN(1, "Preemption without Lite Restore\n");
494 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
495 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
496 if (execlists_check_remove_request(ring, status_id))
501 if (submit_contexts != 0)
502 execlists_context_unqueue(ring);
504 spin_unlock(&ring->execlist_lock);
506 WARN(submit_contexts > 2, "More than two context complete events?\n");
507 ring->next_context_status_buffer = write_pointer % 6;
509 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
510 ((u32)ring->next_context_status_buffer & 0x07) << 8);
513 static void execlists_free_request_task(struct work_struct *work)
515 struct intel_ctx_submit_request *req =
516 container_of(work, struct intel_ctx_submit_request, work);
517 struct drm_device *dev = req->ring->dev;
518 struct drm_i915_private *dev_priv = dev->dev_private;
520 intel_runtime_pm_put(dev_priv);
522 mutex_lock(&dev->struct_mutex);
523 i915_gem_context_unreference(req->ctx);
524 mutex_unlock(&dev->struct_mutex);
529 static int execlists_context_queue(struct intel_engine_cs *ring,
530 struct intel_context *to,
533 struct intel_ctx_submit_request *req = NULL, *cursor;
534 struct drm_i915_private *dev_priv = ring->dev->dev_private;
536 int num_elements = 0;
538 req = kzalloc(sizeof(*req), GFP_KERNEL);
542 i915_gem_context_reference(req->ctx);
545 INIT_WORK(&req->work, execlists_free_request_task);
547 intel_runtime_pm_get(dev_priv);
549 spin_lock_irqsave(&ring->execlist_lock, flags);
551 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
552 if (++num_elements > 2)
555 if (num_elements > 2) {
556 struct intel_ctx_submit_request *tail_req;
558 tail_req = list_last_entry(&ring->execlist_queue,
559 struct intel_ctx_submit_request,
562 if (to == tail_req->ctx) {
563 WARN(tail_req->elsp_submitted != 0,
564 "More than 2 already-submitted reqs queued\n");
565 list_del(&tail_req->execlist_link);
566 queue_work(dev_priv->wq, &tail_req->work);
570 list_add_tail(&req->execlist_link, &ring->execlist_queue);
571 if (num_elements == 0)
572 execlists_context_unqueue(ring);
574 spin_unlock_irqrestore(&ring->execlist_lock, flags);
579 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf)
581 struct intel_engine_cs *ring = ringbuf->ring;
582 uint32_t flush_domains;
586 if (ring->gpu_caches_dirty)
587 flush_domains = I915_GEM_GPU_DOMAINS;
589 ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains);
593 ring->gpu_caches_dirty = false;
597 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
598 struct list_head *vmas)
600 struct intel_engine_cs *ring = ringbuf->ring;
601 struct i915_vma *vma;
602 uint32_t flush_domains = 0;
603 bool flush_chipset = false;
606 list_for_each_entry(vma, vmas, exec_list) {
607 struct drm_i915_gem_object *obj = vma->obj;
609 ret = i915_gem_object_sync(obj, ring);
613 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
614 flush_chipset |= i915_gem_clflush_object(obj, false);
616 flush_domains |= obj->base.write_domain;
619 if (flush_domains & I915_GEM_DOMAIN_GTT)
622 /* Unconditionally invalidate gpu caches and ensure that we do flush
623 * any residual writes from the previous batch.
625 return logical_ring_invalidate_all_caches(ringbuf);
629 * execlists_submission() - submit a batchbuffer for execution, Execlists style
632 * @ring: Engine Command Streamer to submit to.
633 * @ctx: Context to employ for this submission.
634 * @args: execbuffer call arguments.
635 * @vmas: list of vmas.
636 * @batch_obj: the batchbuffer to submit.
637 * @exec_start: batchbuffer start virtual address pointer.
638 * @flags: translated execbuffer call flags.
640 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
641 * away the submission details of the execbuffer ioctl call.
643 * Return: non-zero if the submission fails.
645 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
646 struct intel_engine_cs *ring,
647 struct intel_context *ctx,
648 struct drm_i915_gem_execbuffer2 *args,
649 struct list_head *vmas,
650 struct drm_i915_gem_object *batch_obj,
651 u64 exec_start, u32 flags)
653 struct drm_i915_private *dev_priv = dev->dev_private;
654 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
659 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
660 instp_mask = I915_EXEC_CONSTANTS_MASK;
661 switch (instp_mode) {
662 case I915_EXEC_CONSTANTS_REL_GENERAL:
663 case I915_EXEC_CONSTANTS_ABSOLUTE:
664 case I915_EXEC_CONSTANTS_REL_SURFACE:
665 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
666 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
670 if (instp_mode != dev_priv->relative_constants_mode) {
671 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
672 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
676 /* The HW changed the meaning on this bit on gen6 */
677 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
681 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
685 if (args->num_cliprects != 0) {
686 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
689 if (args->DR4 == 0xffffffff) {
690 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
694 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
695 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
700 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
701 DRM_DEBUG("sol reset is gen7 only\n");
705 ret = execlists_move_to_gpu(ringbuf, vmas);
709 if (ring == &dev_priv->ring[RCS] &&
710 instp_mode != dev_priv->relative_constants_mode) {
711 ret = intel_logical_ring_begin(ringbuf, 4);
715 intel_logical_ring_emit(ringbuf, MI_NOOP);
716 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
717 intel_logical_ring_emit(ringbuf, INSTPM);
718 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
719 intel_logical_ring_advance(ringbuf);
721 dev_priv->relative_constants_mode = instp_mode;
724 ret = ring->emit_bb_start(ringbuf, exec_start, flags);
728 i915_gem_execbuffer_move_to_active(vmas, ring);
729 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
734 void intel_logical_ring_stop(struct intel_engine_cs *ring)
736 struct drm_i915_private *dev_priv = ring->dev->dev_private;
739 if (!intel_ring_initialized(ring))
742 ret = intel_ring_idle(ring);
743 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
744 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
747 /* TODO: Is this correct with Execlists enabled? */
748 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
749 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
750 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
753 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
756 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf)
758 struct intel_engine_cs *ring = ringbuf->ring;
761 if (!ring->gpu_caches_dirty)
764 ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS);
768 ring->gpu_caches_dirty = false;
773 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
774 * @ringbuf: Logical Ringbuffer to advance.
776 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
777 * really happens during submission is that the context and current tail will be placed
778 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
779 * point, the tail *inside* the context is updated and the ELSP written to.
781 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf)
783 struct intel_engine_cs *ring = ringbuf->ring;
784 struct intel_context *ctx = ringbuf->FIXME_lrc_ctx;
786 intel_logical_ring_advance(ringbuf);
788 if (intel_ring_stopped(ring))
791 execlists_context_queue(ring, ctx, ringbuf->tail);
794 static int logical_ring_alloc_seqno(struct intel_engine_cs *ring,
795 struct intel_context *ctx)
797 if (ring->outstanding_lazy_seqno)
800 if (ring->preallocated_lazy_request == NULL) {
801 struct drm_i915_gem_request *request;
803 request = kmalloc(sizeof(*request), GFP_KERNEL);
807 /* Hold a reference to the context this request belongs to
808 * (we will need it when the time comes to emit/retire the
812 i915_gem_context_reference(request->ctx);
814 ring->preallocated_lazy_request = request;
817 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
820 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
823 struct intel_engine_cs *ring = ringbuf->ring;
824 struct drm_i915_gem_request *request;
828 if (ringbuf->last_retired_head != -1) {
829 ringbuf->head = ringbuf->last_retired_head;
830 ringbuf->last_retired_head = -1;
832 ringbuf->space = intel_ring_space(ringbuf);
833 if (ringbuf->space >= bytes)
837 list_for_each_entry(request, &ring->request_list, list) {
838 if (__intel_ring_space(request->tail, ringbuf->tail,
839 ringbuf->size) >= bytes) {
840 seqno = request->seqno;
848 ret = i915_wait_seqno(ring, seqno);
852 i915_gem_retire_requests_ring(ring);
853 ringbuf->head = ringbuf->last_retired_head;
854 ringbuf->last_retired_head = -1;
856 ringbuf->space = intel_ring_space(ringbuf);
860 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
863 struct intel_engine_cs *ring = ringbuf->ring;
864 struct drm_device *dev = ring->dev;
865 struct drm_i915_private *dev_priv = dev->dev_private;
869 ret = logical_ring_wait_request(ringbuf, bytes);
873 /* Force the context submission in case we have been skipping it */
874 intel_logical_ring_advance_and_submit(ringbuf);
876 /* With GEM the hangcheck timer should kick us out of the loop,
877 * leaving it early runs the risk of corrupting GEM state (due
878 * to running on almost untested codepaths). But on resume
879 * timers don't work yet, so prevent a complete hang in that
880 * case by choosing an insanely large timeout. */
881 end = jiffies + 60 * HZ;
884 ringbuf->head = I915_READ_HEAD(ring);
885 ringbuf->space = intel_ring_space(ringbuf);
886 if (ringbuf->space >= bytes) {
893 if (dev_priv->mm.interruptible && signal_pending(current)) {
898 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
899 dev_priv->mm.interruptible);
903 if (time_after(jiffies, end)) {
912 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf)
914 uint32_t __iomem *virt;
915 int rem = ringbuf->size - ringbuf->tail;
917 if (ringbuf->space < rem) {
918 int ret = logical_ring_wait_for_space(ringbuf, rem);
924 virt = ringbuf->virtual_start + ringbuf->tail;
927 iowrite32(MI_NOOP, virt++);
930 ringbuf->space = intel_ring_space(ringbuf);
935 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes)
939 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
940 ret = logical_ring_wrap_buffer(ringbuf);
945 if (unlikely(ringbuf->space < bytes)) {
946 ret = logical_ring_wait_for_space(ringbuf, bytes);
955 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
957 * @ringbuf: Logical ringbuffer.
958 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
960 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
961 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
962 * and also preallocates a request (every workload submission is still mediated through
963 * requests, same as it did with legacy ringbuffer submission).
965 * Return: non-zero if the ringbuffer is not ready to be written to.
967 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords)
969 struct intel_engine_cs *ring = ringbuf->ring;
970 struct drm_device *dev = ring->dev;
971 struct drm_i915_private *dev_priv = dev->dev_private;
974 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
975 dev_priv->mm.interruptible);
979 ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t));
983 /* Preallocate the olr before touching the ring */
984 ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx);
988 ringbuf->space -= num_dwords * sizeof(uint32_t);
992 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
993 struct intel_context *ctx)
996 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
997 struct drm_device *dev = ring->dev;
998 struct drm_i915_private *dev_priv = dev->dev_private;
999 struct i915_workarounds *w = &dev_priv->workarounds;
1001 if (WARN_ON(w->count == 0))
1004 ring->gpu_caches_dirty = true;
1005 ret = logical_ring_flush_all_caches(ringbuf);
1009 ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2);
1013 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1014 for (i = 0; i < w->count; i++) {
1015 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1016 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1018 intel_logical_ring_emit(ringbuf, MI_NOOP);
1020 intel_logical_ring_advance(ringbuf);
1022 ring->gpu_caches_dirty = true;
1023 ret = logical_ring_flush_all_caches(ringbuf);
1030 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1032 struct drm_device *dev = ring->dev;
1033 struct drm_i915_private *dev_priv = dev->dev_private;
1035 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1036 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1038 I915_WRITE(RING_MODE_GEN7(ring),
1039 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1040 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1041 POSTING_READ(RING_MODE_GEN7(ring));
1042 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1044 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1049 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1051 struct drm_device *dev = ring->dev;
1052 struct drm_i915_private *dev_priv = dev->dev_private;
1055 ret = gen8_init_common_ring(ring);
1059 /* We need to disable the AsyncFlip performance optimisations in order
1060 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1061 * programmed to '1' on all products.
1063 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1065 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1067 ret = intel_init_pipe_control(ring);
1071 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1073 return init_workarounds_ring(ring);
1076 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1077 u64 offset, unsigned flags)
1079 bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1082 ret = intel_logical_ring_begin(ringbuf, 4);
1086 /* FIXME(BDW): Address space and security selectors. */
1087 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1088 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1089 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1090 intel_logical_ring_emit(ringbuf, MI_NOOP);
1091 intel_logical_ring_advance(ringbuf);
1096 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1098 struct drm_device *dev = ring->dev;
1099 struct drm_i915_private *dev_priv = dev->dev_private;
1100 unsigned long flags;
1102 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1105 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1106 if (ring->irq_refcount++ == 0) {
1107 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1108 POSTING_READ(RING_IMR(ring->mmio_base));
1110 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1115 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1117 struct drm_device *dev = ring->dev;
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 unsigned long flags;
1121 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1122 if (--ring->irq_refcount == 0) {
1123 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1124 POSTING_READ(RING_IMR(ring->mmio_base));
1126 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1129 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1130 u32 invalidate_domains,
1133 struct intel_engine_cs *ring = ringbuf->ring;
1134 struct drm_device *dev = ring->dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1139 ret = intel_logical_ring_begin(ringbuf, 4);
1143 cmd = MI_FLUSH_DW + 1;
1145 if (ring == &dev_priv->ring[VCS]) {
1146 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
1147 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1148 MI_FLUSH_DW_STORE_INDEX |
1149 MI_FLUSH_DW_OP_STOREDW;
1151 if (invalidate_domains & I915_GEM_DOMAIN_RENDER)
1152 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1153 MI_FLUSH_DW_OP_STOREDW;
1156 intel_logical_ring_emit(ringbuf, cmd);
1157 intel_logical_ring_emit(ringbuf,
1158 I915_GEM_HWS_SCRATCH_ADDR |
1159 MI_FLUSH_DW_USE_GTT);
1160 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1161 intel_logical_ring_emit(ringbuf, 0); /* value */
1162 intel_logical_ring_advance(ringbuf);
1167 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1168 u32 invalidate_domains,
1171 struct intel_engine_cs *ring = ringbuf->ring;
1172 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1176 flags |= PIPE_CONTROL_CS_STALL;
1178 if (flush_domains) {
1179 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1180 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1183 if (invalidate_domains) {
1184 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1185 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1186 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1187 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1188 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1189 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1190 flags |= PIPE_CONTROL_QW_WRITE;
1191 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1194 ret = intel_logical_ring_begin(ringbuf, 6);
1198 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1199 intel_logical_ring_emit(ringbuf, flags);
1200 intel_logical_ring_emit(ringbuf, scratch_addr);
1201 intel_logical_ring_emit(ringbuf, 0);
1202 intel_logical_ring_emit(ringbuf, 0);
1203 intel_logical_ring_emit(ringbuf, 0);
1204 intel_logical_ring_advance(ringbuf);
1209 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1211 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1214 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1216 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1219 static int gen8_emit_request(struct intel_ringbuffer *ringbuf)
1221 struct intel_engine_cs *ring = ringbuf->ring;
1225 ret = intel_logical_ring_begin(ringbuf, 6);
1229 cmd = MI_STORE_DWORD_IMM_GEN8;
1230 cmd |= MI_GLOBAL_GTT;
1232 intel_logical_ring_emit(ringbuf, cmd);
1233 intel_logical_ring_emit(ringbuf,
1234 (ring->status_page.gfx_addr +
1235 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1236 intel_logical_ring_emit(ringbuf, 0);
1237 intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno);
1238 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1239 intel_logical_ring_emit(ringbuf, MI_NOOP);
1240 intel_logical_ring_advance_and_submit(ringbuf);
1246 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1248 * @ring: Engine Command Streamer.
1251 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1253 struct drm_i915_private *dev_priv;
1255 if (!intel_ring_initialized(ring))
1258 dev_priv = ring->dev->dev_private;
1260 intel_logical_ring_stop(ring);
1261 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1262 ring->preallocated_lazy_request = NULL;
1263 ring->outstanding_lazy_seqno = 0;
1266 ring->cleanup(ring);
1268 i915_cmd_parser_fini_ring(ring);
1270 if (ring->status_page.obj) {
1271 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1272 ring->status_page.obj = NULL;
1276 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1280 /* Intentionally left blank. */
1281 ring->buffer = NULL;
1284 INIT_LIST_HEAD(&ring->active_list);
1285 INIT_LIST_HEAD(&ring->request_list);
1286 init_waitqueue_head(&ring->irq_queue);
1288 INIT_LIST_HEAD(&ring->execlist_queue);
1289 spin_lock_init(&ring->execlist_lock);
1290 ring->next_context_status_buffer = 0;
1292 ret = i915_cmd_parser_init_ring(ring);
1297 ret = ring->init(ring);
1302 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1307 static int logical_render_ring_init(struct drm_device *dev)
1309 struct drm_i915_private *dev_priv = dev->dev_private;
1310 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1312 ring->name = "render ring";
1314 ring->mmio_base = RENDER_RING_BASE;
1315 ring->irq_enable_mask =
1316 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1317 ring->irq_keep_mask =
1318 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1319 if (HAS_L3_DPF(dev))
1320 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1322 ring->init = gen8_init_render_ring;
1323 ring->init_context = intel_logical_ring_workarounds_emit;
1324 ring->cleanup = intel_fini_pipe_control;
1325 ring->get_seqno = gen8_get_seqno;
1326 ring->set_seqno = gen8_set_seqno;
1327 ring->emit_request = gen8_emit_request;
1328 ring->emit_flush = gen8_emit_flush_render;
1329 ring->irq_get = gen8_logical_ring_get_irq;
1330 ring->irq_put = gen8_logical_ring_put_irq;
1331 ring->emit_bb_start = gen8_emit_bb_start;
1333 return logical_ring_init(dev, ring);
1336 static int logical_bsd_ring_init(struct drm_device *dev)
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1341 ring->name = "bsd ring";
1343 ring->mmio_base = GEN6_BSD_RING_BASE;
1344 ring->irq_enable_mask =
1345 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1346 ring->irq_keep_mask =
1347 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1349 ring->init = gen8_init_common_ring;
1350 ring->get_seqno = gen8_get_seqno;
1351 ring->set_seqno = gen8_set_seqno;
1352 ring->emit_request = gen8_emit_request;
1353 ring->emit_flush = gen8_emit_flush;
1354 ring->irq_get = gen8_logical_ring_get_irq;
1355 ring->irq_put = gen8_logical_ring_put_irq;
1356 ring->emit_bb_start = gen8_emit_bb_start;
1358 return logical_ring_init(dev, ring);
1361 static int logical_bsd2_ring_init(struct drm_device *dev)
1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1366 ring->name = "bds2 ring";
1368 ring->mmio_base = GEN8_BSD2_RING_BASE;
1369 ring->irq_enable_mask =
1370 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1371 ring->irq_keep_mask =
1372 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1374 ring->init = gen8_init_common_ring;
1375 ring->get_seqno = gen8_get_seqno;
1376 ring->set_seqno = gen8_set_seqno;
1377 ring->emit_request = gen8_emit_request;
1378 ring->emit_flush = gen8_emit_flush;
1379 ring->irq_get = gen8_logical_ring_get_irq;
1380 ring->irq_put = gen8_logical_ring_put_irq;
1381 ring->emit_bb_start = gen8_emit_bb_start;
1383 return logical_ring_init(dev, ring);
1386 static int logical_blt_ring_init(struct drm_device *dev)
1388 struct drm_i915_private *dev_priv = dev->dev_private;
1389 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1391 ring->name = "blitter ring";
1393 ring->mmio_base = BLT_RING_BASE;
1394 ring->irq_enable_mask =
1395 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1396 ring->irq_keep_mask =
1397 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1399 ring->init = gen8_init_common_ring;
1400 ring->get_seqno = gen8_get_seqno;
1401 ring->set_seqno = gen8_set_seqno;
1402 ring->emit_request = gen8_emit_request;
1403 ring->emit_flush = gen8_emit_flush;
1404 ring->irq_get = gen8_logical_ring_get_irq;
1405 ring->irq_put = gen8_logical_ring_put_irq;
1406 ring->emit_bb_start = gen8_emit_bb_start;
1408 return logical_ring_init(dev, ring);
1411 static int logical_vebox_ring_init(struct drm_device *dev)
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1416 ring->name = "video enhancement ring";
1418 ring->mmio_base = VEBOX_RING_BASE;
1419 ring->irq_enable_mask =
1420 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1421 ring->irq_keep_mask =
1422 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1424 ring->init = gen8_init_common_ring;
1425 ring->get_seqno = gen8_get_seqno;
1426 ring->set_seqno = gen8_set_seqno;
1427 ring->emit_request = gen8_emit_request;
1428 ring->emit_flush = gen8_emit_flush;
1429 ring->irq_get = gen8_logical_ring_get_irq;
1430 ring->irq_put = gen8_logical_ring_put_irq;
1431 ring->emit_bb_start = gen8_emit_bb_start;
1433 return logical_ring_init(dev, ring);
1437 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1440 * This function inits the engines for an Execlists submission style (the equivalent in the
1441 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1442 * those engines that are present in the hardware.
1444 * Return: non-zero if the initialization failed.
1446 int intel_logical_rings_init(struct drm_device *dev)
1448 struct drm_i915_private *dev_priv = dev->dev_private;
1451 ret = logical_render_ring_init(dev);
1456 ret = logical_bsd_ring_init(dev);
1458 goto cleanup_render_ring;
1462 ret = logical_blt_ring_init(dev);
1464 goto cleanup_bsd_ring;
1467 if (HAS_VEBOX(dev)) {
1468 ret = logical_vebox_ring_init(dev);
1470 goto cleanup_blt_ring;
1473 if (HAS_BSD2(dev)) {
1474 ret = logical_bsd2_ring_init(dev);
1476 goto cleanup_vebox_ring;
1479 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1481 goto cleanup_bsd2_ring;
1486 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1488 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1490 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1492 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1493 cleanup_render_ring:
1494 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1499 int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1500 struct intel_context *ctx)
1502 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1503 struct render_state so;
1504 struct drm_i915_file_private *file_priv = ctx->file_priv;
1505 struct drm_file *file = file_priv ? file_priv->file : NULL;
1508 ret = i915_gem_render_state_prepare(ring, &so);
1512 if (so.rodata == NULL)
1515 ret = ring->emit_bb_start(ringbuf,
1517 I915_DISPATCH_SECURE);
1521 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1523 ret = __i915_add_request(ring, file, so.obj, NULL);
1524 /* intel_logical_ring_add_request moves object to inactive if it
1527 i915_gem_render_state_fini(&so);
1532 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1533 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1535 struct drm_device *dev = ring->dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 struct drm_i915_gem_object *ring_obj = ringbuf->obj;
1538 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1540 uint32_t *reg_state;
1544 ppgtt = dev_priv->mm.aliasing_ppgtt;
1546 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1548 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1552 ret = i915_gem_object_get_pages(ctx_obj);
1554 DRM_DEBUG_DRIVER("Could not get object pages\n");
1558 i915_gem_object_pin_pages(ctx_obj);
1560 /* The second page of the context object contains some fields which must
1561 * be set up prior to the first execution. */
1562 page = i915_gem_object_get_page(ctx_obj, 1);
1563 reg_state = kmap_atomic(page);
1565 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1566 * commands followed by (reg, value) pairs. The values we are setting here are
1567 * only for the first context restore: on a subsequent save, the GPU will
1568 * recreate this batchbuffer with new values (including all the missing
1569 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1570 if (ring->id == RCS)
1571 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1573 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1574 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1575 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1576 reg_state[CTX_CONTEXT_CONTROL+1] =
1577 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
1578 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1579 reg_state[CTX_RING_HEAD+1] = 0;
1580 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1581 reg_state[CTX_RING_TAIL+1] = 0;
1582 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1583 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
1584 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1585 reg_state[CTX_RING_BUFFER_CONTROL+1] =
1586 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1587 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1588 reg_state[CTX_BB_HEAD_U+1] = 0;
1589 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1590 reg_state[CTX_BB_HEAD_L+1] = 0;
1591 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1592 reg_state[CTX_BB_STATE+1] = (1<<5);
1593 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1594 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1595 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1596 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1597 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1598 reg_state[CTX_SECOND_BB_STATE+1] = 0;
1599 if (ring->id == RCS) {
1600 /* TODO: according to BSpec, the register state context
1601 * for CHV does not have these. OTOH, these registers do
1602 * exist in CHV. I'm waiting for a clarification */
1603 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1604 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1605 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1606 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1607 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1608 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1610 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1611 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1612 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1613 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1614 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1615 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1616 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1617 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1618 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1619 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1620 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1621 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1622 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1623 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1624 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1625 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1626 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1627 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1628 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1629 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1630 if (ring->id == RCS) {
1631 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1632 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1633 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1636 kunmap_atomic(reg_state);
1639 set_page_dirty(page);
1640 i915_gem_object_unpin_pages(ctx_obj);
1646 * intel_lr_context_free() - free the LRC specific bits of a context
1647 * @ctx: the LR context to free.
1649 * The real context freeing is done in i915_gem_context_free: this only
1650 * takes care of the bits that are LRC related: the per-engine backing
1651 * objects and the logical ringbuffer.
1653 void intel_lr_context_free(struct intel_context *ctx)
1657 for (i = 0; i < I915_NUM_RINGS; i++) {
1658 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1659 struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
1662 intel_destroy_ringbuffer_obj(ringbuf);
1664 i915_gem_object_ggtt_unpin(ctx_obj);
1665 drm_gem_object_unreference(&ctx_obj->base);
1670 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1674 WARN_ON(INTEL_INFO(ring->dev)->gen != 8);
1678 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1684 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1691 static int lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1692 struct drm_i915_gem_object *default_ctx_obj)
1694 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1696 /* The status page is offset 0 from the default context object
1698 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1699 ring->status_page.page_addr =
1700 kmap(sg_page(default_ctx_obj->pages->sgl));
1701 if (ring->status_page.page_addr == NULL)
1703 ring->status_page.obj = default_ctx_obj;
1705 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1706 (u32)ring->status_page.gfx_addr);
1707 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1713 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1714 * @ctx: LR context to create.
1715 * @ring: engine to be used with the context.
1717 * This function can be called more than once, with different engines, if we plan
1718 * to use the context with them. The context backing objects and the ringbuffers
1719 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1720 * the creation is a deferred call: it's better to make sure first that we need to use
1721 * a given ring with the context.
1723 * Return: non-zero on error.
1725 int intel_lr_context_deferred_create(struct intel_context *ctx,
1726 struct intel_engine_cs *ring)
1728 struct drm_device *dev = ring->dev;
1729 struct drm_i915_gem_object *ctx_obj;
1730 uint32_t context_size;
1731 struct intel_ringbuffer *ringbuf;
1734 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1735 if (ctx->engine[ring->id].state)
1738 context_size = round_up(get_lr_context_size(ring), 4096);
1740 ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1741 if (IS_ERR(ctx_obj)) {
1742 ret = PTR_ERR(ctx_obj);
1743 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1747 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1749 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret);
1750 drm_gem_object_unreference(&ctx_obj->base);
1754 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1756 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1758 i915_gem_object_ggtt_unpin(ctx_obj);
1759 drm_gem_object_unreference(&ctx_obj->base);
1764 ringbuf->ring = ring;
1765 ringbuf->FIXME_lrc_ctx = ctx;
1767 ringbuf->size = 32 * PAGE_SIZE;
1768 ringbuf->effective_size = ringbuf->size;
1771 ringbuf->space = ringbuf->size;
1772 ringbuf->last_retired_head = -1;
1774 /* TODO: For now we put this in the mappable region so that we can reuse
1775 * the existing ringbuffer code which ioremaps it. When we start
1776 * creating many contexts, this will no longer work and we must switch
1777 * to a kmapish interface.
1779 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1781 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n",
1786 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1788 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1789 intel_destroy_ringbuffer_obj(ringbuf);
1793 ctx->engine[ring->id].ringbuf = ringbuf;
1794 ctx->engine[ring->id].state = ctx_obj;
1796 if (ctx == ring->default_context) {
1797 ret = lrc_setup_hardware_status_page(ring, ctx_obj);
1799 DRM_ERROR("Failed to setup hardware status page\n");
1804 if (ring->id == RCS && !ctx->rcs_initialized) {
1805 if (ring->init_context) {
1806 ret = ring->init_context(ring, ctx);
1808 DRM_ERROR("ring init context: %d\n", ret);
1811 ret = intel_lr_context_render_state_init(ring, ctx);
1813 DRM_ERROR("Init render state failed: %d\n", ret);
1814 ctx->engine[ring->id].ringbuf = NULL;
1815 ctx->engine[ring->id].state = NULL;
1816 intel_destroy_ringbuffer_obj(ringbuf);
1819 ctx->rcs_initialized = true;
1826 i915_gem_object_ggtt_unpin(ctx_obj);
1827 drm_gem_object_unreference(&ctx_obj->base);