drivers/gpu/drm/i915/intel_lrc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *    Michel Thierry <michel.thierry@intel.com>
  26  *    Thomas Daniel <thomas.daniel@intel.com>
  27  *    Oscar Mateo <oscar.mateo@intel.com>
  28  *
  29  */
  30
  31 /**
  32  * DOC: Logical Rings, Logical Ring Contexts and Execlists
  33  *
  34  * Motivation:
  35  * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
  36  * These expanded contexts enable a number of new abilities, especially
  37  * "Execlists" (also implemented in this file).
  38  *
  39  * One of the main differences with the legacy HW contexts is that logical
  40  * ring contexts incorporate many more things to the context's state, like
  41  * PDPs or ringbuffer control registers:
  42  *
  43  * The reason why PDPs are included in the context is straightforward: as
  44  * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
  45  * contained there mean you don't need to do a ppgtt->switch_mm yourself,
  46  * instead, the GPU will do it for you on the context switch.
  47  *
  48  * But, what about the ringbuffer control registers (head, tail, etc..)?
  49  * shouldn't we just need a set of those per engine command streamer? This is
  50  * where the name "Logical Rings" starts to make sense: by virtualizing the
  51  * rings, the engine cs shifts to a new "ring buffer" with every context
  52  * switch. When you want to submit a workload to the GPU you: A) choose your
  53  * context, B) find its appropriate virtualized ring, C) write commands to it
  54  * and then, finally, D) tell the GPU to switch to that context.
  55  *
  56  * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
  57  * to a contexts is via a context execution list, ergo "Execlists".
  58  *
  59  * LRC implementation:
  60  * Regarding the creation of contexts, we have:
  61  *
  62  * - One global default context.
  63  * - One local default context for each opened fd.
  64  * - One local extra context for each context create ioctl call.
  65  *
  66  * Now that ringbuffers belong per-context (and not per-engine, like before)
  67  * and that contexts are uniquely tied to a given engine (and not reusable,
  68  * like before) we need:
  69  *
  70  * - One ringbuffer per-engine inside each context.
  71  * - One backing object per-engine inside each context.
  72  *
  73  * The global default context starts its life with these new objects fully
  74  * allocated and populated. The local default context for each opened fd is
  75  * more complex, because we don't know at creation time which engine is going
  76  * to use them. To handle this, we have implemented a deferred creation of LR
  77  * contexts:
  78  *
  79  * The local context starts its life as a hollow or blank holder, that only
  80  * gets populated for a given engine once we receive an execbuffer. If later
  81  * on we receive another execbuffer ioctl for the same context but a different
  82  * engine, we allocate/populate a new ringbuffer and context backing object and
  83  * so on.
  84  *
  85  * Finally, regarding local contexts created using the ioctl call: as they are
  86  * only allowed with the render ring, we can allocate & populate them right
  87  * away (no need to defer anything, at least for now).
  88  *
  89  * Execlists implementation:
  90  * Execlists are the new method by which, on gen8+ hardware, workloads are
  91  * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
  92  * This method works as follows:
  93  *
  94  * When a request is committed, its commands (the BB start and any leading or
  95  * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
  96  * for the appropriate context. The tail pointer in the hardware context is not
  97  * updated at this time, but instead, kept by the driver in the ringbuffer
  98  * structure. A structure representing this request is added to a request queue
  99  * for the appropriate engine: this structure contains a copy of the context's
 100  * tail after the request was written to the ring buffer and a pointer to the
 101  * context itself.
 102  *
 103  * If the engine's request queue was empty before the request was added, the
 104  * queue is processed immediately. Otherwise the queue will be processed during
 105  * a context switch interrupt. In any case, elements on the queue will get sent
 106  * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 107  * globally unique 20-bits submission ID.
 108  *
 109  * When execution of a request completes, the GPU updates the context status
 110  * buffer with a context complete event and generates a context switch interrupt.
 111  * During the interrupt handling, the driver examines the events in the buffer:
 112  * for each context complete event, if the announced ID matches that on the head
 113  * of the request queue, then that request is retired and removed from the queue.
 114  *
 115  * After processing, if any requests were retired and the queue is not empty
 116  * then a new execution list can be submitted. The two requests at the front of
 117  * the queue are next to be submitted but since a context may not occur twice in
 118  * an execution list, if subsequent requests have the same ID as the first then
 119  * the two requests must be combined. This is done simply by discarding requests
 120  * at the head of the queue until either only one requests is left (in which case
 121  * we use a NULL second context) or the first two requests have unique IDs.
 122  *
 123  * By always executing the first two requests in the queue the driver ensures
 124  * that the GPU is kept as busy as possible. In the case where a single context
 125  * completes but a second context is still executing, the request for this second
 126  * context will be at the head of the queue when we remove the first one. This
 127  * request will then be resubmitted along with a new request for a different context,
 128  * which will cause the hardware to continue executing the second request and queue
 129  * the new request (the GPU detects the condition of a context getting preempted
 130  * with the same context and optimizes the context switch flow by not doing
 131  * preemption, but just sampling the new tail pointer).
 132  *
 133  */
 134
 135 #include <drm/drmP.h>
 136 #include <drm/i915_drm.h>
 137 #include "i915_drv.h"
 138
 139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
 140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
 141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
 142
 143 #define RING_EXECLIST_QFULL             (1 << 0x2)
 144 #define RING_EXECLIST1_VALID            (1 << 0x3)
 145 #define RING_EXECLIST0_VALID            (1 << 0x4)
 146 #define RING_EXECLIST_ACTIVE_STATUS     (3 << 0xE)
 147 #define RING_EXECLIST1_ACTIVE           (1 << 0x11)
 148 #define RING_EXECLIST0_ACTIVE           (1 << 0x12)
 149
 150 #define GEN8_CTX_STATUS_IDLE_ACTIVE     (1 << 0)
 151 #define GEN8_CTX_STATUS_PREEMPTED       (1 << 1)
 152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH  (1 << 2)
 153 #define GEN8_CTX_STATUS_ACTIVE_IDLE     (1 << 3)
 154 #define GEN8_CTX_STATUS_COMPLETE        (1 << 4)
 155 #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
 156
 157 #define CTX_LRI_HEADER_0                0x01
 158 #define CTX_CONTEXT_CONTROL             0x02
 159 #define CTX_RING_HEAD                   0x04
 160 #define CTX_RING_TAIL                   0x06
 161 #define CTX_RING_BUFFER_START           0x08
 162 #define CTX_RING_BUFFER_CONTROL         0x0a
 163 #define CTX_BB_HEAD_U                   0x0c
 164 #define CTX_BB_HEAD_L                   0x0e
 165 #define CTX_BB_STATE                    0x10
 166 #define CTX_SECOND_BB_HEAD_U            0x12
 167 #define CTX_SECOND_BB_HEAD_L            0x14
 168 #define CTX_SECOND_BB_STATE             0x16
 169 #define CTX_BB_PER_CTX_PTR              0x18
 170 #define CTX_RCS_INDIRECT_CTX            0x1a
 171 #define CTX_RCS_INDIRECT_CTX_OFFSET     0x1c
 172 #define CTX_LRI_HEADER_1                0x21
 173 #define CTX_CTX_TIMESTAMP               0x22
 174 #define CTX_PDP3_UDW                    0x24
 175 #define CTX_PDP3_LDW                    0x26
 176 #define CTX_PDP2_UDW                    0x28
 177 #define CTX_PDP2_LDW                    0x2a
 178 #define CTX_PDP1_UDW                    0x2c
 179 #define CTX_PDP1_LDW                    0x2e
 180 #define CTX_PDP0_UDW                    0x30
 181 #define CTX_PDP0_LDW                    0x32
 182 #define CTX_LRI_HEADER_2                0x41
 183 #define CTX_R_PWR_CLK_STATE             0x42
 184 #define CTX_GPGPU_CSR_BASE_ADDRESS      0x44
 185
 186 #define GEN8_CTX_VALID (1<<0)
 187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
 188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
 189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
 190 #define GEN8_CTX_PRIVILEGE (1<<8)
 191 enum {
 192         ADVANCED_CONTEXT = 0,
 193         LEGACY_CONTEXT,
 194         ADVANCED_AD_CONTEXT,
 195         LEGACY_64B_CONTEXT
 196 };
 197 #define GEN8_CTX_MODE_SHIFT 3
 198 enum {
 199         FAULT_AND_HANG = 0,
 200         FAULT_AND_HALT, /* Debug only */
 201         FAULT_AND_STREAM,
 202         FAULT_AND_CONTINUE /* Unsupported */
 203 };
 204 #define GEN8_CTX_ID_SHIFT 32
 205
 206 /**
 207  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 208  * @dev: DRM device.
 209  * @enable_execlists: value of i915.enable_execlists module parameter.
 210  *
 211  * Only certain platforms support Execlists (the prerequisites being
 212  * support for Logical Ring Contexts and Aliasing PPGTT or better),
 213  * and only when enabled via module parameter.
 214  *
 215  * Return: 1 if Execlists is supported and has to be enabled.
 216  */
 217 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
 218 {
 219         WARN_ON(i915.enable_ppgtt == -1);
 220
 221         if (INTEL_INFO(dev)->gen >= 9)
 222                 return 1;
 223
 224         if (enable_execlists == 0)
 225                 return 0;
 226
 227         if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
 228             i915.use_mmio_flip >= 0)
 229                 return 1;
 230
 231         return 0;
 232 }
 233
 234 /**
 235  * intel_execlists_ctx_id() - get the Execlists Context ID
 236  * @ctx_obj: Logical Ring Context backing object.
 237  *
 238  * Do not confuse with ctx->id! Unfortunately we have a name overload
 239  * here: the old context ID we pass to userspace as a handler so that
 240  * they can refer to a context, and the new context ID we pass to the
 241  * ELSP so that the GPU can inform us of the context status via
 242  * interrupts.
 243  *
 244  * Return: 20-bits globally unique context ID.
 245  */
 246 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
 247 {
 248         u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 249
 250         /* LRCA is required to be 4K aligned so the more significant 20 bits
 251          * are globally unique */
 252         return lrca >> 12;
 253 }
 254
 255 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
 256 {
 257         uint64_t desc;
 258         uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 259
 260         WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
 261
 262         desc = GEN8_CTX_VALID;
 263         desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
 264         desc |= GEN8_CTX_L3LLC_COHERENT;
 265         desc |= GEN8_CTX_PRIVILEGE;
 266         desc |= lrca;
 267         desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
 268
 269         /* TODO: WaDisableLiteRestore when we start using semaphore
 270          * signalling between Command Streamers */
 271         /* desc |= GEN8_CTX_FORCE_RESTORE; */
 272
 273         return desc;
 274 }
 275
 276 static void execlists_elsp_write(struct intel_engine_cs *ring,
 277                                  struct drm_i915_gem_object *ctx_obj0,
 278                                  struct drm_i915_gem_object *ctx_obj1)
 279 {
 280         struct drm_device *dev = ring->dev;
 281         struct drm_i915_private *dev_priv = dev->dev_private;
 282         uint64_t temp = 0;
 283         uint32_t desc[4];
 284         unsigned long flags;
 285
 286         /* XXX: You must always write both descriptors in the order below. */
 287         if (ctx_obj1)
 288                 temp = execlists_ctx_descriptor(ctx_obj1);
 289         else
 290                 temp = 0;
 291         desc[1] = (u32)(temp >> 32);
 292         desc[0] = (u32)temp;
 293
 294         temp = execlists_ctx_descriptor(ctx_obj0);
 295         desc[3] = (u32)(temp >> 32);
 296         desc[2] = (u32)temp;
 297
 298         /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
 299          * are in progress.
 300          *
 301          * The other problem is that we can't just call gen6_gt_force_wake_get()
 302          * because that function calls intel_runtime_pm_get(), which might sleep.
 303          * Instead, we do the runtime_pm_get/put when creating/destroying requests.
 304          */
 305         spin_lock_irqsave(&dev_priv->uncore.lock, flags);
 306         if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
 307                 if (dev_priv->uncore.fw_rendercount++ == 0)
 308                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 309                                                               FORCEWAKE_RENDER);
 310                 if (dev_priv->uncore.fw_mediacount++ == 0)
 311                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 312                                                               FORCEWAKE_MEDIA);
 313                 if (INTEL_INFO(dev)->gen >= 9) {
 314                         if (dev_priv->uncore.fw_blittercount++ == 0)
 315                                 dev_priv->uncore.funcs.force_wake_get(dev_priv,
 316                                                         FORCEWAKE_BLITTER);
 317                 }
 318         } else {
 319                 if (dev_priv->uncore.forcewake_count++ == 0)
 320                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 321                                                               FORCEWAKE_ALL);
 322         }
 323         spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 324
 325         I915_WRITE(RING_ELSP(ring), desc[1]);
 326         I915_WRITE(RING_ELSP(ring), desc[0]);
 327         I915_WRITE(RING_ELSP(ring), desc[3]);
 328         /* The context is automatically loaded after the following */
 329         I915_WRITE(RING_ELSP(ring), desc[2]);
 330
 331         /* ELSP is a wo register, so use another nearby reg for posting instead */
 332         POSTING_READ(RING_EXECLIST_STATUS(ring));
 333
 334         /* Release Force Wakeup (see the big comment above). */
 335         spin_lock_irqsave(&dev_priv->uncore.lock, flags);
 336         if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
 337                 if (--dev_priv->uncore.fw_rendercount == 0)
 338                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 339                                                               FORCEWAKE_RENDER);
 340                 if (--dev_priv->uncore.fw_mediacount == 0)
 341                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 342                                                               FORCEWAKE_MEDIA);
 343                 if (INTEL_INFO(dev)->gen >= 9) {
 344                         if (--dev_priv->uncore.fw_blittercount == 0)
 345                                 dev_priv->uncore.funcs.force_wake_put(dev_priv,
 346                                                         FORCEWAKE_BLITTER);
 347                 }
 348         } else {
 349                 if (--dev_priv->uncore.forcewake_count == 0)
 350                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 351                                                               FORCEWAKE_ALL);
 352         }
 353
 354         spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 355 }
 356
 357 static int execlists_ctx_write_tail(struct drm_i915_gem_object *ctx_obj, u32 tail)
 358 {
 359         struct page *page;
 360         uint32_t *reg_state;
 361
 362         page = i915_gem_object_get_page(ctx_obj, 1);
 363         reg_state = kmap_atomic(page);
 364
 365         reg_state[CTX_RING_TAIL+1] = tail;
 366
 367         kunmap_atomic(reg_state);
 368
 369         return 0;
 370 }
 371
 372 static void execlists_submit_contexts(struct intel_engine_cs *ring,
 373                                       struct intel_context *to0, u32 tail0,
 374                                       struct intel_context *to1, u32 tail1)
 375 {
 376         struct drm_i915_gem_object *ctx_obj0;
 377         struct drm_i915_gem_object *ctx_obj1 = NULL;
 378
 379         ctx_obj0 = to0->engine[ring->id].state;
 380         BUG_ON(!ctx_obj0);
 381         WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
 382
 383         execlists_ctx_write_tail(ctx_obj0, tail0);
 384
 385         if (to1) {
 386                 ctx_obj1 = to1->engine[ring->id].state;
 387                 BUG_ON(!ctx_obj1);
 388                 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
 389
 390                 execlists_ctx_write_tail(ctx_obj1, tail1);
 391         }
 392
 393         execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
 394 }
 395
 396 static void execlists_context_unqueue(struct intel_engine_cs *ring)
 397 {
 398         struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL;
 399         struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL;
 400
 401         assert_spin_locked(&ring->execlist_lock);
 402
 403         if (list_empty(&ring->execlist_queue))
 404                 return;
 405
 406         /* Try to read in pairs */
 407         list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
 408                                  execlist_link) {
 409                 if (!req0) {
 410                         req0 = cursor;
 411                 } else if (req0->ctx == cursor->ctx) {
 412                         /* Same ctx: ignore first request, as second request
 413                          * will update tail past first request's workload */
 414                         cursor->elsp_submitted = req0->elsp_submitted;
 415                         list_del(&req0->execlist_link);
 416                         list_add_tail(&req0->execlist_link,
 417                                 &ring->execlist_retired_req_list);
 418                         req0 = cursor;
 419                 } else {
 420                         req1 = cursor;
 421                         break;
 422                 }
 423         }
 424
 425         WARN_ON(req1 && req1->elsp_submitted);
 426
 427         execlists_submit_contexts(ring, req0->ctx, req0->tail,
 428                                   req1 ? req1->ctx : NULL,
 429                                   req1 ? req1->tail : 0);
 430
 431         req0->elsp_submitted++;
 432         if (req1)
 433                 req1->elsp_submitted++;
 434 }
 435
 436 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 437                                            u32 request_id)
 438 {
 439         struct intel_ctx_submit_request *head_req;
 440
 441         assert_spin_locked(&ring->execlist_lock);
 442
 443         head_req = list_first_entry_or_null(&ring->execlist_queue,
 444                                             struct intel_ctx_submit_request,
 445                                             execlist_link);
 446
 447         if (head_req != NULL) {
 448                 struct drm_i915_gem_object *ctx_obj =
 449                                 head_req->ctx->engine[ring->id].state;
 450                 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
 451                         WARN(head_req->elsp_submitted == 0,
 452                              "Never submitted head request\n");
 453
 454                         if (--head_req->elsp_submitted <= 0) {
 455                                 list_del(&head_req->execlist_link);
 456                                 list_add_tail(&head_req->execlist_link,
 457                                         &ring->execlist_retired_req_list);
 458                                 return true;
 459                         }
 460                 }
 461         }
 462
 463         return false;
 464 }
 465
 466 /**
 467  * intel_execlists_handle_ctx_events() - handle Context Switch interrupts
 468  * @ring: Engine Command Streamer to handle.
 469  *
 470  * Check the unread Context Status Buffers and manage the submission of new
 471  * contexts to the ELSP accordingly.
 472  */
 473 void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring)
 474 {
 475         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 476         u32 status_pointer;
 477         u8 read_pointer;
 478         u8 write_pointer;
 479         u32 status;
 480         u32 status_id;
 481         u32 submit_contexts = 0;
 482
 483         status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
 484
 485         read_pointer = ring->next_context_status_buffer;
 486         write_pointer = status_pointer & 0x07;
 487         if (read_pointer > write_pointer)
 488                 write_pointer += 6;
 489
 490         spin_lock(&ring->execlist_lock);
 491
 492         while (read_pointer < write_pointer) {
 493                 read_pointer++;
 494                 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 495                                 (read_pointer % 6) * 8);
 496                 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 497                                 (read_pointer % 6) * 8 + 4);
 498
 499                 if (status & GEN8_CTX_STATUS_PREEMPTED) {
 500                         if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
 501                                 if (execlists_check_remove_request(ring, status_id))
 502                                         WARN(1, "Lite Restored request removed from queue\n");
 503                         } else
 504                                 WARN(1, "Preemption without Lite Restore\n");
 505                 }
 506
 507                  if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
 508                      (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
 509                         if (execlists_check_remove_request(ring, status_id))
 510                                 submit_contexts++;
 511                 }
 512         }
 513
 514         if (submit_contexts != 0)
 515                 execlists_context_unqueue(ring);
 516
 517         spin_unlock(&ring->execlist_lock);
 518
 519         WARN(submit_contexts > 2, "More than two context complete events?\n");
 520         ring->next_context_status_buffer = write_pointer % 6;
 521
 522         I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
 523                    ((u32)ring->next_context_status_buffer & 0x07) << 8);
 524 }
 525
 526 static int execlists_context_queue(struct intel_engine_cs *ring,
 527                                    struct intel_context *to,
 528                                    u32 tail)
 529 {
 530         struct intel_ctx_submit_request *req = NULL, *cursor;
 531         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 532         unsigned long flags;
 533         int num_elements = 0;
 534
 535         req = kzalloc(sizeof(*req), GFP_KERNEL);
 536         if (req == NULL)
 537                 return -ENOMEM;
 538         req->ctx = to;
 539         i915_gem_context_reference(req->ctx);
 540         req->ring = ring;
 541         req->tail = tail;
 542
 543         intel_runtime_pm_get(dev_priv);
 544
 545         spin_lock_irqsave(&ring->execlist_lock, flags);
 546
 547         list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
 548                 if (++num_elements > 2)
 549                         break;
 550
 551         if (num_elements > 2) {
 552                 struct intel_ctx_submit_request *tail_req;
 553
 554                 tail_req = list_last_entry(&ring->execlist_queue,
 555                                            struct intel_ctx_submit_request,
 556                                            execlist_link);
 557
 558                 if (to == tail_req->ctx) {
 559                         WARN(tail_req->elsp_submitted != 0,
 560                              "More than 2 already-submitted reqs queued\n");
 561                         list_del(&tail_req->execlist_link);
 562                         list_add_tail(&tail_req->execlist_link,
 563                                 &ring->execlist_retired_req_list);
 564                 }
 565         }
 566
 567         list_add_tail(&req->execlist_link, &ring->execlist_queue);
 568         if (num_elements == 0)
 569                 execlists_context_unqueue(ring);
 570
 571         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 572
 573         return 0;
 574 }
 575
 576 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf)
 577 {
 578         struct intel_engine_cs *ring = ringbuf->ring;
 579         uint32_t flush_domains;
 580         int ret;
 581
 582         flush_domains = 0;
 583         if (ring->gpu_caches_dirty)
 584                 flush_domains = I915_GEM_GPU_DOMAINS;
 585
 586         ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains);
 587         if (ret)
 588                 return ret;
 589
 590         ring->gpu_caches_dirty = false;
 591         return 0;
 592 }
 593
 594 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
 595                                  struct list_head *vmas)
 596 {
 597         struct intel_engine_cs *ring = ringbuf->ring;
 598         struct i915_vma *vma;
 599         uint32_t flush_domains = 0;
 600         bool flush_chipset = false;
 601         int ret;
 602
 603         list_for_each_entry(vma, vmas, exec_list) {
 604                 struct drm_i915_gem_object *obj = vma->obj;
 605
 606                 ret = i915_gem_object_sync(obj, ring);
 607                 if (ret)
 608                         return ret;
 609
 610                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 611                         flush_chipset |= i915_gem_clflush_object(obj, false);
 612
 613                 flush_domains |= obj->base.write_domain;
 614         }
 615
 616         if (flush_domains & I915_GEM_DOMAIN_GTT)
 617                 wmb();
 618
 619         /* Unconditionally invalidate gpu caches and ensure that we do flush
 620          * any residual writes from the previous batch.
 621          */
 622         return logical_ring_invalidate_all_caches(ringbuf);
 623 }
 624
 625 /**
 626  * execlists_submission() - submit a batchbuffer for execution, Execlists style
 627  * @dev: DRM device.
 628  * @file: DRM file.
 629  * @ring: Engine Command Streamer to submit to.
 630  * @ctx: Context to employ for this submission.
 631  * @args: execbuffer call arguments.
 632  * @vmas: list of vmas.
 633  * @batch_obj: the batchbuffer to submit.
 634  * @exec_start: batchbuffer start virtual address pointer.
 635  * @flags: translated execbuffer call flags.
 636  *
 637  * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 638  * away the submission details of the execbuffer ioctl call.
 639  *
 640  * Return: non-zero if the submission fails.
 641  */
 642 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
 643                                struct intel_engine_cs *ring,
 644                                struct intel_context *ctx,
 645                                struct drm_i915_gem_execbuffer2 *args,
 646                                struct list_head *vmas,
 647                                struct drm_i915_gem_object *batch_obj,
 648                                u64 exec_start, u32 flags)
 649 {
 650         struct drm_i915_private *dev_priv = dev->dev_private;
 651         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 652         int instp_mode;
 653         u32 instp_mask;
 654         int ret;
 655
 656         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
 657         instp_mask = I915_EXEC_CONSTANTS_MASK;
 658         switch (instp_mode) {
 659         case I915_EXEC_CONSTANTS_REL_GENERAL:
 660         case I915_EXEC_CONSTANTS_ABSOLUTE:
 661         case I915_EXEC_CONSTANTS_REL_SURFACE:
 662                 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
 663                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
 664                         return -EINVAL;
 665                 }
 666
 667                 if (instp_mode != dev_priv->relative_constants_mode) {
 668                         if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
 669                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
 670                                 return -EINVAL;
 671                         }
 672
 673                         /* The HW changed the meaning on this bit on gen6 */
 674                         instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
 675                 }
 676                 break;
 677         default:
 678                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
 679                 return -EINVAL;
 680         }
 681
 682         if (args->num_cliprects != 0) {
 683                 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
 684                 return -EINVAL;
 685         } else {
 686                 if (args->DR4 == 0xffffffff) {
 687                         DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 688                         args->DR4 = 0;
 689                 }
 690
 691                 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
 692                         DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
 693                         return -EINVAL;
 694                 }
 695         }
 696
 697         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
 698                 DRM_DEBUG("sol reset is gen7 only\n");
 699                 return -EINVAL;
 700         }
 701
 702         ret = execlists_move_to_gpu(ringbuf, vmas);
 703         if (ret)
 704                 return ret;
 705
 706         if (ring == &dev_priv->ring[RCS] &&
 707             instp_mode != dev_priv->relative_constants_mode) {
 708                 ret = intel_logical_ring_begin(ringbuf, 4);
 709                 if (ret)
 710                         return ret;
 711
 712                 intel_logical_ring_emit(ringbuf, MI_NOOP);
 713                 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
 714                 intel_logical_ring_emit(ringbuf, INSTPM);
 715                 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
 716                 intel_logical_ring_advance(ringbuf);
 717
 718                 dev_priv->relative_constants_mode = instp_mode;
 719         }
 720
 721         ret = ring->emit_bb_start(ringbuf, exec_start, flags);
 722         if (ret)
 723                 return ret;
 724
 725         i915_gem_execbuffer_move_to_active(vmas, ring);
 726         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 727
 728         return 0;
 729 }
 730
 731 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
 732 {
 733         struct intel_ctx_submit_request *req, *tmp;
 734         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 735         unsigned long flags;
 736         struct list_head retired_list;
 737
 738         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 739         if (list_empty(&ring->execlist_retired_req_list))
 740                 return;
 741
 742         INIT_LIST_HEAD(&retired_list);
 743         spin_lock_irqsave(&ring->execlist_lock, flags);
 744         list_replace_init(&ring->execlist_retired_req_list, &retired_list);
 745         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 746
 747         list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
 748                 intel_runtime_pm_put(dev_priv);
 749                 i915_gem_context_unreference(req->ctx);
 750                 list_del(&req->execlist_link);
 751                 kfree(req);
 752         }
 753 }
 754
 755 void intel_logical_ring_stop(struct intel_engine_cs *ring)
 756 {
 757         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 758         int ret;
 759
 760         if (!intel_ring_initialized(ring))
 761                 return;
 762
 763         ret = intel_ring_idle(ring);
 764         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
 765                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 766                           ring->name, ret);
 767
 768         /* TODO: Is this correct with Execlists enabled? */
 769         I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 770         if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 771                 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 772                 return;
 773         }
 774         I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 775 }
 776
 777 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf)
 778 {
 779         struct intel_engine_cs *ring = ringbuf->ring;
 780         int ret;
 781
 782         if (!ring->gpu_caches_dirty)
 783                 return 0;
 784
 785         ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS);
 786         if (ret)
 787                 return ret;
 788
 789         ring->gpu_caches_dirty = false;
 790         return 0;
 791 }
 792
 793 /**
 794  * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
 795  * @ringbuf: Logical Ringbuffer to advance.
 796  *
 797  * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 798  * really happens during submission is that the context and current tail will be placed
 799  * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 800  * point, the tail *inside* the context is updated and the ELSP written to.
 801  */
 802 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf)
 803 {
 804         struct intel_engine_cs *ring = ringbuf->ring;
 805         struct intel_context *ctx = ringbuf->FIXME_lrc_ctx;
 806
 807         intel_logical_ring_advance(ringbuf);
 808
 809         if (intel_ring_stopped(ring))
 810                 return;
 811
 812         execlists_context_queue(ring, ctx, ringbuf->tail);
 813 }
 814
 815 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 816                 struct intel_context *ctx)
 817 {
 818         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 819         int ret = 0;
 820
 821         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 822         if (ctx->engine[ring->id].unpin_count++ == 0) {
 823                 ret = i915_gem_obj_ggtt_pin(ctx_obj,
 824                                 GEN8_LR_CONTEXT_ALIGN, 0);
 825                 if (ret)
 826                         ctx->engine[ring->id].unpin_count = 0;
 827         }
 828
 829         return ret;
 830 }
 831
 832 void intel_lr_context_unpin(struct intel_engine_cs *ring,
 833                 struct intel_context *ctx)
 834 {
 835         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 836
 837         if (ctx_obj) {
 838                 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 839                 if (--ctx->engine[ring->id].unpin_count == 0)
 840                         i915_gem_object_ggtt_unpin(ctx_obj);
 841         }
 842 }
 843
 844 static int logical_ring_alloc_seqno(struct intel_engine_cs *ring,
 845                                     struct intel_context *ctx)
 846 {
 847         int ret;
 848
 849         if (ring->outstanding_lazy_seqno)
 850                 return 0;
 851
 852         if (ring->preallocated_lazy_request == NULL) {
 853                 struct drm_i915_gem_request *request;
 854
 855                 request = kmalloc(sizeof(*request), GFP_KERNEL);
 856                 if (request == NULL)
 857                         return -ENOMEM;
 858
 859                 if (ctx != ring->default_context) {
 860                         ret = intel_lr_context_pin(ring, ctx);
 861                         if (ret) {
 862                                 kfree(request);
 863                                 return ret;
 864                         }
 865                 }
 866
 867                 /* Hold a reference to the context this request belongs to
 868                  * (we will need it when the time comes to emit/retire the
 869                  * request).
 870                  */
 871                 request->ctx = ctx;
 872                 i915_gem_context_reference(request->ctx);
 873
 874                 ring->preallocated_lazy_request = request;
 875         }
 876
 877         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
 878 }
 879
 880 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
 881                                      int bytes)
 882 {
 883         struct intel_engine_cs *ring = ringbuf->ring;
 884         struct drm_i915_gem_request *request;
 885         u32 seqno = 0;
 886         int ret;
 887
 888         if (ringbuf->last_retired_head != -1) {
 889                 ringbuf->head = ringbuf->last_retired_head;
 890                 ringbuf->last_retired_head = -1;
 891
 892                 ringbuf->space = intel_ring_space(ringbuf);
 893                 if (ringbuf->space >= bytes)
 894                         return 0;
 895         }
 896
 897         list_for_each_entry(request, &ring->request_list, list) {
 898                 if (__intel_ring_space(request->tail, ringbuf->tail,
 899                                        ringbuf->size) >= bytes) {
 900                         seqno = request->seqno;
 901                         break;
 902                 }
 903         }
 904
 905         if (seqno == 0)
 906                 return -ENOSPC;
 907
 908         ret = i915_wait_seqno(ring, seqno);
 909         if (ret)
 910                 return ret;
 911
 912         i915_gem_retire_requests_ring(ring);
 913         ringbuf->head = ringbuf->last_retired_head;
 914         ringbuf->last_retired_head = -1;
 915
 916         ringbuf->space = intel_ring_space(ringbuf);
 917         return 0;
 918 }
 919
 920 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
 921                                        int bytes)
 922 {
 923         struct intel_engine_cs *ring = ringbuf->ring;
 924         struct drm_device *dev = ring->dev;
 925         struct drm_i915_private *dev_priv = dev->dev_private;
 926         unsigned long end;
 927         int ret;
 928
 929         ret = logical_ring_wait_request(ringbuf, bytes);
 930         if (ret != -ENOSPC)
 931                 return ret;
 932
 933         /* Force the context submission in case we have been skipping it */
 934         intel_logical_ring_advance_and_submit(ringbuf);
 935
 936         /* With GEM the hangcheck timer should kick us out of the loop,
 937          * leaving it early runs the risk of corrupting GEM state (due
 938          * to running on almost untested codepaths). But on resume
 939          * timers don't work yet, so prevent a complete hang in that
 940          * case by choosing an insanely large timeout. */
 941         end = jiffies + 60 * HZ;
 942
 943         do {
 944                 ringbuf->head = I915_READ_HEAD(ring);
 945                 ringbuf->space = intel_ring_space(ringbuf);
 946                 if (ringbuf->space >= bytes) {
 947                         ret = 0;
 948                         break;
 949                 }
 950
 951                 msleep(1);
 952
 953                 if (dev_priv->mm.interruptible && signal_pending(current)) {
 954                         ret = -ERESTARTSYS;
 955                         break;
 956                 }
 957
 958                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
 959                                            dev_priv->mm.interruptible);
 960                 if (ret)
 961                         break;
 962
 963                 if (time_after(jiffies, end)) {
 964                         ret = -EBUSY;
 965                         break;
 966                 }
 967         } while (1);
 968
 969         return ret;
 970 }
 971
 972 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf)
 973 {
 974         uint32_t __iomem *virt;
 975         int rem = ringbuf->size - ringbuf->tail;
 976
 977         if (ringbuf->space < rem) {
 978                 int ret = logical_ring_wait_for_space(ringbuf, rem);
 979
 980                 if (ret)
 981                         return ret;
 982         }
 983
 984         virt = ringbuf->virtual_start + ringbuf->tail;
 985         rem /= 4;
 986         while (rem--)
 987                 iowrite32(MI_NOOP, virt++);
 988
 989         ringbuf->tail = 0;
 990         ringbuf->space = intel_ring_space(ringbuf);
 991
 992         return 0;
 993 }
 994
 995 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes)
 996 {
 997         int ret;
 998
 999         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1000                 ret = logical_ring_wrap_buffer(ringbuf);
1001                 if (unlikely(ret))
1002                         return ret;
1003         }
1004
1005         if (unlikely(ringbuf->space < bytes)) {
1006                 ret = logical_ring_wait_for_space(ringbuf, bytes);
1007                 if (unlikely(ret))
1008                         return ret;
1009         }
1010
1011         return 0;
1012 }
1013
1014 /**
1015  * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1016  *
1017  * @ringbuf: Logical ringbuffer.
1018  * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1019  *
1020  * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1021  * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1022  * and also preallocates a request (every workload submission is still mediated through
1023  * requests, same as it did with legacy ringbuffer submission).
1024  *
1025  * Return: non-zero if the ringbuffer is not ready to be written to.
1026  */
1027 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords)
1028 {
1029         struct intel_engine_cs *ring = ringbuf->ring;
1030         struct drm_device *dev = ring->dev;
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         int ret;
1033
1034         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1035                                    dev_priv->mm.interruptible);
1036         if (ret)
1037                 return ret;
1038
1039         ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t));
1040         if (ret)
1041                 return ret;
1042
1043         /* Preallocate the olr before touching the ring */
1044         ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx);
1045         if (ret)
1046                 return ret;
1047
1048         ringbuf->space -= num_dwords * sizeof(uint32_t);
1049         return 0;
1050 }
1051
1052 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1053                                                struct intel_context *ctx)
1054 {
1055         int ret, i;
1056         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1057         struct drm_device *dev = ring->dev;
1058         struct drm_i915_private *dev_priv = dev->dev_private;
1059         struct i915_workarounds *w = &dev_priv->workarounds;
1060
1061         if (WARN_ON(w->count == 0))
1062                 return 0;
1063
1064         ring->gpu_caches_dirty = true;
1065         ret = logical_ring_flush_all_caches(ringbuf);
1066         if (ret)
1067                 return ret;
1068
1069         ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2);
1070         if (ret)
1071                 return ret;
1072
1073         intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1074         for (i = 0; i < w->count; i++) {
1075                 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1076                 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1077         }
1078         intel_logical_ring_emit(ringbuf, MI_NOOP);
1079
1080         intel_logical_ring_advance(ringbuf);
1081
1082         ring->gpu_caches_dirty = true;
1083         ret = logical_ring_flush_all_caches(ringbuf);
1084         if (ret)
1085                 return ret;
1086
1087         return 0;
1088 }
1089
1090 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1091 {
1092         struct drm_device *dev = ring->dev;
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094
1095         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1096         I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1097
1098         I915_WRITE(RING_MODE_GEN7(ring),
1099                    _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1100                    _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1101         POSTING_READ(RING_MODE_GEN7(ring));
1102         DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1103
1104         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1105
1106         return 0;
1107 }
1108
1109 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1110 {
1111         struct drm_device *dev = ring->dev;
1112         struct drm_i915_private *dev_priv = dev->dev_private;
1113         int ret;
1114
1115         ret = gen8_init_common_ring(ring);
1116         if (ret)
1117                 return ret;
1118
1119         /* We need to disable the AsyncFlip performance optimisations in order
1120          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1121          * programmed to '1' on all products.
1122          *
1123          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1124          */
1125         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1126
1127         ret = intel_init_pipe_control(ring);
1128         if (ret)
1129                 return ret;
1130
1131         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1132
1133         return init_workarounds_ring(ring);
1134 }
1135
1136 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1137                               u64 offset, unsigned flags)
1138 {
1139         bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1140         int ret;
1141
1142         ret = intel_logical_ring_begin(ringbuf, 4);
1143         if (ret)
1144                 return ret;
1145
1146         /* FIXME(BDW): Address space and security selectors. */
1147         intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1148         intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1149         intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1150         intel_logical_ring_emit(ringbuf, MI_NOOP);
1151         intel_logical_ring_advance(ringbuf);
1152
1153         return 0;
1154 }
1155
1156 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1157 {
1158         struct drm_device *dev = ring->dev;
1159         struct drm_i915_private *dev_priv = dev->dev_private;
1160         unsigned long flags;
1161
1162         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1163                 return false;
1164
1165         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1166         if (ring->irq_refcount++ == 0) {
1167                 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1168                 POSTING_READ(RING_IMR(ring->mmio_base));
1169         }
1170         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1171
1172         return true;
1173 }
1174
1175 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1176 {
1177         struct drm_device *dev = ring->dev;
1178         struct drm_i915_private *dev_priv = dev->dev_private;
1179         unsigned long flags;
1180
1181         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1182         if (--ring->irq_refcount == 0) {
1183                 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1184                 POSTING_READ(RING_IMR(ring->mmio_base));
1185         }
1186         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1187 }
1188
1189 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1190                            u32 invalidate_domains,
1191                            u32 unused)
1192 {
1193         struct intel_engine_cs *ring = ringbuf->ring;
1194         struct drm_device *dev = ring->dev;
1195         struct drm_i915_private *dev_priv = dev->dev_private;
1196         uint32_t cmd;
1197         int ret;
1198
1199         ret = intel_logical_ring_begin(ringbuf, 4);
1200         if (ret)
1201                 return ret;
1202
1203         cmd = MI_FLUSH_DW + 1;
1204
1205         if (ring == &dev_priv->ring[VCS]) {
1206                 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
1207                         cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1208                                 MI_FLUSH_DW_STORE_INDEX |
1209                                 MI_FLUSH_DW_OP_STOREDW;
1210         } else {
1211                 if (invalidate_domains & I915_GEM_DOMAIN_RENDER)
1212                         cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1213                                 MI_FLUSH_DW_OP_STOREDW;
1214         }
1215
1216         intel_logical_ring_emit(ringbuf, cmd);
1217         intel_logical_ring_emit(ringbuf,
1218                                 I915_GEM_HWS_SCRATCH_ADDR |
1219                                 MI_FLUSH_DW_USE_GTT);
1220         intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1221         intel_logical_ring_emit(ringbuf, 0); /* value */
1222         intel_logical_ring_advance(ringbuf);
1223
1224         return 0;
1225 }
1226
1227 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1228                                   u32 invalidate_domains,
1229                                   u32 flush_domains)
1230 {
1231         struct intel_engine_cs *ring = ringbuf->ring;
1232         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1233         u32 flags = 0;
1234         int ret;
1235
1236         flags |= PIPE_CONTROL_CS_STALL;
1237
1238         if (flush_domains) {
1239                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1240                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1241         }
1242
1243         if (invalidate_domains) {
1244                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1245                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1246                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1247                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1248                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1249                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1250                 flags |= PIPE_CONTROL_QW_WRITE;
1251                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1252         }
1253
1254         ret = intel_logical_ring_begin(ringbuf, 6);
1255         if (ret)
1256                 return ret;
1257
1258         intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1259         intel_logical_ring_emit(ringbuf, flags);
1260         intel_logical_ring_emit(ringbuf, scratch_addr);
1261         intel_logical_ring_emit(ringbuf, 0);
1262         intel_logical_ring_emit(ringbuf, 0);
1263         intel_logical_ring_emit(ringbuf, 0);
1264         intel_logical_ring_advance(ringbuf);
1265
1266         return 0;
1267 }
1268
1269 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1270 {
1271         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1272 }
1273
1274 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1275 {
1276         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1277 }
1278
1279 static int gen8_emit_request(struct intel_ringbuffer *ringbuf)
1280 {
1281         struct intel_engine_cs *ring = ringbuf->ring;
1282         u32 cmd;
1283         int ret;
1284
1285         ret = intel_logical_ring_begin(ringbuf, 6);
1286         if (ret)
1287                 return ret;
1288
1289         cmd = MI_STORE_DWORD_IMM_GEN8;
1290         cmd |= MI_GLOBAL_GTT;
1291
1292         intel_logical_ring_emit(ringbuf, cmd);
1293         intel_logical_ring_emit(ringbuf,
1294                                 (ring->status_page.gfx_addr +
1295                                 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1296         intel_logical_ring_emit(ringbuf, 0);
1297         intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno);
1298         intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1299         intel_logical_ring_emit(ringbuf, MI_NOOP);
1300         intel_logical_ring_advance_and_submit(ringbuf);
1301
1302         return 0;
1303 }
1304
1305 /**
1306  * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1307  *
1308  * @ring: Engine Command Streamer.
1309  *
1310  */
1311 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1312 {
1313         struct drm_i915_private *dev_priv;
1314
1315         if (!intel_ring_initialized(ring))
1316                 return;
1317
1318         dev_priv = ring->dev->dev_private;
1319
1320         intel_logical_ring_stop(ring);
1321         WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1322         ring->preallocated_lazy_request = NULL;
1323         ring->outstanding_lazy_seqno = 0;
1324
1325         if (ring->cleanup)
1326                 ring->cleanup(ring);
1327
1328         i915_cmd_parser_fini_ring(ring);
1329
1330         if (ring->status_page.obj) {
1331                 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1332                 ring->status_page.obj = NULL;
1333         }
1334 }
1335
1336 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1337 {
1338         int ret;
1339
1340         /* Intentionally left blank. */
1341         ring->buffer = NULL;
1342
1343         ring->dev = dev;
1344         INIT_LIST_HEAD(&ring->active_list);
1345         INIT_LIST_HEAD(&ring->request_list);
1346         init_waitqueue_head(&ring->irq_queue);
1347
1348         INIT_LIST_HEAD(&ring->execlist_queue);
1349         INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1350         spin_lock_init(&ring->execlist_lock);
1351         ring->next_context_status_buffer = 0;
1352
1353         ret = i915_cmd_parser_init_ring(ring);
1354         if (ret)
1355                 return ret;
1356
1357         if (ring->init) {
1358                 ret = ring->init(ring);
1359                 if (ret)
1360                         return ret;
1361         }
1362
1363         ret = intel_lr_context_deferred_create(ring->default_context, ring);
1364
1365         return ret;
1366 }
1367
1368 static int logical_render_ring_init(struct drm_device *dev)
1369 {
1370         struct drm_i915_private *dev_priv = dev->dev_private;
1371         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1372
1373         ring->name = "render ring";
1374         ring->id = RCS;
1375         ring->mmio_base = RENDER_RING_BASE;
1376         ring->irq_enable_mask =
1377                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1378         ring->irq_keep_mask =
1379                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1380         if (HAS_L3_DPF(dev))
1381                 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1382
1383         ring->init = gen8_init_render_ring;
1384         ring->init_context = intel_logical_ring_workarounds_emit;
1385         ring->cleanup = intel_fini_pipe_control;
1386         ring->get_seqno = gen8_get_seqno;
1387         ring->set_seqno = gen8_set_seqno;
1388         ring->emit_request = gen8_emit_request;
1389         ring->emit_flush = gen8_emit_flush_render;
1390         ring->irq_get = gen8_logical_ring_get_irq;
1391         ring->irq_put = gen8_logical_ring_put_irq;
1392         ring->emit_bb_start = gen8_emit_bb_start;
1393
1394         return logical_ring_init(dev, ring);
1395 }
1396
1397 static int logical_bsd_ring_init(struct drm_device *dev)
1398 {
1399         struct drm_i915_private *dev_priv = dev->dev_private;
1400         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1401
1402         ring->name = "bsd ring";
1403         ring->id = VCS;
1404         ring->mmio_base = GEN6_BSD_RING_BASE;
1405         ring->irq_enable_mask =
1406                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1407         ring->irq_keep_mask =
1408                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1409
1410         ring->init = gen8_init_common_ring;
1411         ring->get_seqno = gen8_get_seqno;
1412         ring->set_seqno = gen8_set_seqno;
1413         ring->emit_request = gen8_emit_request;
1414         ring->emit_flush = gen8_emit_flush;
1415         ring->irq_get = gen8_logical_ring_get_irq;
1416         ring->irq_put = gen8_logical_ring_put_irq;
1417         ring->emit_bb_start = gen8_emit_bb_start;
1418
1419         return logical_ring_init(dev, ring);
1420 }
1421
1422 static int logical_bsd2_ring_init(struct drm_device *dev)
1423 {
1424         struct drm_i915_private *dev_priv = dev->dev_private;
1425         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1426
1427         ring->name = "bds2 ring";
1428         ring->id = VCS2;
1429         ring->mmio_base = GEN8_BSD2_RING_BASE;
1430         ring->irq_enable_mask =
1431                 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1432         ring->irq_keep_mask =
1433                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1434
1435         ring->init = gen8_init_common_ring;
1436         ring->get_seqno = gen8_get_seqno;
1437         ring->set_seqno = gen8_set_seqno;
1438         ring->emit_request = gen8_emit_request;
1439         ring->emit_flush = gen8_emit_flush;
1440         ring->irq_get = gen8_logical_ring_get_irq;
1441         ring->irq_put = gen8_logical_ring_put_irq;
1442         ring->emit_bb_start = gen8_emit_bb_start;
1443
1444         return logical_ring_init(dev, ring);
1445 }
1446
1447 static int logical_blt_ring_init(struct drm_device *dev)
1448 {
1449         struct drm_i915_private *dev_priv = dev->dev_private;
1450         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1451
1452         ring->name = "blitter ring";
1453         ring->id = BCS;
1454         ring->mmio_base = BLT_RING_BASE;
1455         ring->irq_enable_mask =
1456                 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1457         ring->irq_keep_mask =
1458                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1459
1460         ring->init = gen8_init_common_ring;
1461         ring->get_seqno = gen8_get_seqno;
1462         ring->set_seqno = gen8_set_seqno;
1463         ring->emit_request = gen8_emit_request;
1464         ring->emit_flush = gen8_emit_flush;
1465         ring->irq_get = gen8_logical_ring_get_irq;
1466         ring->irq_put = gen8_logical_ring_put_irq;
1467         ring->emit_bb_start = gen8_emit_bb_start;
1468
1469         return logical_ring_init(dev, ring);
1470 }
1471
1472 static int logical_vebox_ring_init(struct drm_device *dev)
1473 {
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1476
1477         ring->name = "video enhancement ring";
1478         ring->id = VECS;
1479         ring->mmio_base = VEBOX_RING_BASE;
1480         ring->irq_enable_mask =
1481                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1482         ring->irq_keep_mask =
1483                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1484
1485         ring->init = gen8_init_common_ring;
1486         ring->get_seqno = gen8_get_seqno;
1487         ring->set_seqno = gen8_set_seqno;
1488         ring->emit_request = gen8_emit_request;
1489         ring->emit_flush = gen8_emit_flush;
1490         ring->irq_get = gen8_logical_ring_get_irq;
1491         ring->irq_put = gen8_logical_ring_put_irq;
1492         ring->emit_bb_start = gen8_emit_bb_start;
1493
1494         return logical_ring_init(dev, ring);
1495 }
1496
1497 /**
1498  * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1499  * @dev: DRM device.
1500  *
1501  * This function inits the engines for an Execlists submission style (the equivalent in the
1502  * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1503  * those engines that are present in the hardware.
1504  *
1505  * Return: non-zero if the initialization failed.
1506  */
1507 int intel_logical_rings_init(struct drm_device *dev)
1508 {
1509         struct drm_i915_private *dev_priv = dev->dev_private;
1510         int ret;
1511
1512         ret = logical_render_ring_init(dev);
1513         if (ret)
1514                 return ret;
1515
1516         if (HAS_BSD(dev)) {
1517                 ret = logical_bsd_ring_init(dev);
1518                 if (ret)
1519                         goto cleanup_render_ring;
1520         }
1521
1522         if (HAS_BLT(dev)) {
1523                 ret = logical_blt_ring_init(dev);
1524                 if (ret)
1525                         goto cleanup_bsd_ring;
1526         }
1527
1528         if (HAS_VEBOX(dev)) {
1529                 ret = logical_vebox_ring_init(dev);
1530                 if (ret)
1531                         goto cleanup_blt_ring;
1532         }
1533
1534         if (HAS_BSD2(dev)) {
1535                 ret = logical_bsd2_ring_init(dev);
1536                 if (ret)
1537                         goto cleanup_vebox_ring;
1538         }
1539
1540         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1541         if (ret)
1542                 goto cleanup_bsd2_ring;
1543
1544         return 0;
1545
1546 cleanup_bsd2_ring:
1547         intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1548 cleanup_vebox_ring:
1549         intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1550 cleanup_blt_ring:
1551         intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1552 cleanup_bsd_ring:
1553         intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1554 cleanup_render_ring:
1555         intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1556
1557         return ret;
1558 }
1559
1560 int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1561                                        struct intel_context *ctx)
1562 {
1563         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1564         struct render_state so;
1565         struct drm_i915_file_private *file_priv = ctx->file_priv;
1566         struct drm_file *file = file_priv ? file_priv->file : NULL;
1567         int ret;
1568
1569         ret = i915_gem_render_state_prepare(ring, &so);
1570         if (ret)
1571                 return ret;
1572
1573         if (so.rodata == NULL)
1574                 return 0;
1575
1576         ret = ring->emit_bb_start(ringbuf,
1577                         so.ggtt_offset,
1578                         I915_DISPATCH_SECURE);
1579         if (ret)
1580                 goto out;
1581
1582         i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1583
1584         ret = __i915_add_request(ring, file, so.obj, NULL);
1585         /* intel_logical_ring_add_request moves object to inactive if it
1586          * fails */
1587 out:
1588         i915_gem_render_state_fini(&so);
1589         return ret;
1590 }
1591
1592 static int
1593 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1594                     struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1595 {
1596         struct drm_device *dev = ring->dev;
1597         struct drm_i915_private *dev_priv = dev->dev_private;
1598         struct drm_i915_gem_object *ring_obj = ringbuf->obj;
1599         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1600         struct page *page;
1601         uint32_t *reg_state;
1602         int ret;
1603
1604         if (!ppgtt)
1605                 ppgtt = dev_priv->mm.aliasing_ppgtt;
1606
1607         ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1608         if (ret) {
1609                 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1610                 return ret;
1611         }
1612
1613         ret = i915_gem_object_get_pages(ctx_obj);
1614         if (ret) {
1615                 DRM_DEBUG_DRIVER("Could not get object pages\n");
1616                 return ret;
1617         }
1618
1619         i915_gem_object_pin_pages(ctx_obj);
1620
1621         /* The second page of the context object contains some fields which must
1622          * be set up prior to the first execution. */
1623         page = i915_gem_object_get_page(ctx_obj, 1);
1624         reg_state = kmap_atomic(page);
1625
1626         /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1627          * commands followed by (reg, value) pairs. The values we are setting here are
1628          * only for the first context restore: on a subsequent save, the GPU will
1629          * recreate this batchbuffer with new values (including all the missing
1630          * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1631         if (ring->id == RCS)
1632                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1633         else
1634                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1635         reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1636         reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1637         reg_state[CTX_CONTEXT_CONTROL+1] =
1638                         _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
1639         reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1640         reg_state[CTX_RING_HEAD+1] = 0;
1641         reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1642         reg_state[CTX_RING_TAIL+1] = 0;
1643         reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1644         reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
1645         reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1646         reg_state[CTX_RING_BUFFER_CONTROL+1] =
1647                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1648         reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1649         reg_state[CTX_BB_HEAD_U+1] = 0;
1650         reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1651         reg_state[CTX_BB_HEAD_L+1] = 0;
1652         reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1653         reg_state[CTX_BB_STATE+1] = (1<<5);
1654         reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1655         reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1656         reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1657         reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1658         reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1659         reg_state[CTX_SECOND_BB_STATE+1] = 0;
1660         if (ring->id == RCS) {
1661                 /* TODO: according to BSpec, the register state context
1662                  * for CHV does not have these. OTOH, these registers do
1663                  * exist in CHV. I'm waiting for a clarification */
1664                 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1665                 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1666                 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1667                 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1668                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1669                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1670         }
1671         reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1672         reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1673         reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1674         reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1675         reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1676         reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1677         reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1678         reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1679         reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1680         reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1681         reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1682         reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1683         reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1684         reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1685         reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1686         reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1687         reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1688         reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1689         reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1690         reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1691         if (ring->id == RCS) {
1692                 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1693                 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1694                 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1695         }
1696
1697         kunmap_atomic(reg_state);
1698
1699         ctx_obj->dirty = 1;
1700         set_page_dirty(page);
1701         i915_gem_object_unpin_pages(ctx_obj);
1702
1703         return 0;
1704 }
1705
1706 /**
1707  * intel_lr_context_free() - free the LRC specific bits of a context
1708  * @ctx: the LR context to free.
1709  *
1710  * The real context freeing is done in i915_gem_context_free: this only
1711  * takes care of the bits that are LRC related: the per-engine backing
1712  * objects and the logical ringbuffer.
1713  */
1714 void intel_lr_context_free(struct intel_context *ctx)
1715 {
1716         int i;
1717
1718         for (i = 0; i < I915_NUM_RINGS; i++) {
1719                 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1720
1721                 if (ctx_obj) {
1722                         struct intel_ringbuffer *ringbuf =
1723                                         ctx->engine[i].ringbuf;
1724                         struct intel_engine_cs *ring = ringbuf->ring;
1725
1726                         intel_destroy_ringbuffer_obj(ringbuf);
1727                         kfree(ringbuf);
1728                         if (ctx == ring->default_context)
1729                                 i915_gem_object_ggtt_unpin(ctx_obj);
1730                         drm_gem_object_unreference(&ctx_obj->base);
1731                 }
1732         }
1733 }
1734
1735 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1736 {
1737         int ret = 0;
1738
1739         WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1740
1741         switch (ring->id) {
1742         case RCS:
1743                 if (INTEL_INFO(ring->dev)->gen >= 9)
1744                         ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1745                 else
1746                         ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1747                 break;
1748         case VCS:
1749         case BCS:
1750         case VECS:
1751         case VCS2:
1752                 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1753                 break;
1754         }
1755
1756         return ret;
1757 }
1758
1759 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1760                 struct drm_i915_gem_object *default_ctx_obj)
1761 {
1762         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1763
1764         /* The status page is offset 0 from the default context object
1765          * in LRC mode. */
1766         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1767         ring->status_page.page_addr =
1768                         kmap(sg_page(default_ctx_obj->pages->sgl));
1769         ring->status_page.obj = default_ctx_obj;
1770
1771         I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1772                         (u32)ring->status_page.gfx_addr);
1773         POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1774 }
1775
1776 /**
1777  * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1778  * @ctx: LR context to create.
1779  * @ring: engine to be used with the context.
1780  *
1781  * This function can be called more than once, with different engines, if we plan
1782  * to use the context with them. The context backing objects and the ringbuffers
1783  * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1784  * the creation is a deferred call: it's better to make sure first that we need to use
1785  * a given ring with the context.
1786  *
1787  * Return: non-zero on error.
1788  */
1789 int intel_lr_context_deferred_create(struct intel_context *ctx,
1790                                      struct intel_engine_cs *ring)
1791 {
1792         const bool is_global_default_ctx = (ctx == ring->default_context);
1793         struct drm_device *dev = ring->dev;
1794         struct drm_i915_gem_object *ctx_obj;
1795         uint32_t context_size;
1796         struct intel_ringbuffer *ringbuf;
1797         int ret;
1798
1799         WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1800         if (ctx->engine[ring->id].state)
1801                 return 0;
1802
1803         context_size = round_up(get_lr_context_size(ring), 4096);
1804
1805         ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1806         if (IS_ERR(ctx_obj)) {
1807                 ret = PTR_ERR(ctx_obj);
1808                 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1809                 return ret;
1810         }
1811
1812         if (is_global_default_ctx) {
1813                 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1814                 if (ret) {
1815                         DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1816                                         ret);
1817                         drm_gem_object_unreference(&ctx_obj->base);
1818                         return ret;
1819                 }
1820         }
1821
1822         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1823         if (!ringbuf) {
1824                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1825                                 ring->name);
1826                 if (is_global_default_ctx)
1827                         i915_gem_object_ggtt_unpin(ctx_obj);
1828                 drm_gem_object_unreference(&ctx_obj->base);
1829                 ret = -ENOMEM;
1830                 return ret;
1831         }
1832
1833         ringbuf->ring = ring;
1834         ringbuf->FIXME_lrc_ctx = ctx;
1835
1836         ringbuf->size = 32 * PAGE_SIZE;
1837         ringbuf->effective_size = ringbuf->size;
1838         ringbuf->head = 0;
1839         ringbuf->tail = 0;
1840         ringbuf->space = ringbuf->size;
1841         ringbuf->last_retired_head = -1;
1842
1843         /* TODO: For now we put this in the mappable region so that we can reuse
1844          * the existing ringbuffer code which ioremaps it. When we start
1845          * creating many contexts, this will no longer work and we must switch
1846          * to a kmapish interface.
1847          */
1848         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1849         if (ret) {
1850                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n",
1851                                 ring->name, ret);
1852                 goto error;
1853         }
1854
1855         ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1856         if (ret) {
1857                 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1858                 intel_destroy_ringbuffer_obj(ringbuf);
1859                 goto error;
1860         }
1861
1862         ctx->engine[ring->id].ringbuf = ringbuf;
1863         ctx->engine[ring->id].state = ctx_obj;
1864
1865         if (ctx == ring->default_context)
1866                 lrc_setup_hardware_status_page(ring, ctx_obj);
1867
1868         if (ring->id == RCS && !ctx->rcs_initialized) {
1869                 if (ring->init_context) {
1870                         ret = ring->init_context(ring, ctx);
1871                         if (ret)
1872                                 DRM_ERROR("ring init context: %d\n", ret);
1873                 }
1874
1875                 ret = intel_lr_context_render_state_init(ring, ctx);
1876                 if (ret) {
1877                         DRM_ERROR("Init render state failed: %d\n", ret);
1878                         ctx->engine[ring->id].ringbuf = NULL;
1879                         ctx->engine[ring->id].state = NULL;
1880                         intel_destroy_ringbuffer_obj(ringbuf);
1881                         goto error;
1882                 }
1883                 ctx->rcs_initialized = true;
1884         }
1885
1886         return 0;
1887
1888 error:
1889         kfree(ringbuf);
1890         if (is_global_default_ctx)
1891                 i915_gem_object_ggtt_unpin(ctx_obj);
1892         drm_gem_object_unreference(&ctx_obj->base);
1893         return ret;
1894 }