2 * Copyright © 2014 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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21 * DEALINGS IN THE SOFTWARE.
27 #define GEN8_LR_CONTEXT_ALIGN 4096
30 #define RING_ELSP(ring) _MMIO((ring)->mmio_base + 0x230)
31 #define RING_EXECLIST_STATUS_LO(ring) _MMIO((ring)->mmio_base + 0x234)
32 #define RING_EXECLIST_STATUS_HI(ring) _MMIO((ring)->mmio_base + 0x234 + 4)
33 #define RING_CONTEXT_CONTROL(ring) _MMIO((ring)->mmio_base + 0x244)
34 #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
35 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
36 #define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
37 #define RING_CONTEXT_STATUS_BUF_LO(ring, i) _MMIO((ring)->mmio_base + 0x370 + (i) * 8)
38 #define RING_CONTEXT_STATUS_BUF_HI(ring, i) _MMIO((ring)->mmio_base + 0x370 + (i) * 8 + 4)
39 #define RING_CONTEXT_STATUS_PTR(ring) _MMIO((ring)->mmio_base + 0x3a0)
41 /* The docs specify that the write pointer wraps around after 5h, "After status
42 * is written out to the last available status QW at offset 5h, this pointer
45 * Therefore, one must infer than even though there are 3 bits available, 6 and
46 * 7 appear to be * reserved.
48 #define GEN8_CSB_ENTRIES 6
49 #define GEN8_CSB_PTR_MASK 0x7
50 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
51 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
52 #define GEN8_CSB_WRITE_PTR(csb_status) \
53 (((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
54 #define GEN8_CSB_READ_PTR(csb_status) \
55 (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
58 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
59 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
60 void intel_logical_ring_stop(struct intel_engine_cs *ring);
61 void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
62 int intel_logical_rings_init(struct drm_device *dev);
63 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
65 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
67 * intel_logical_ring_advance() - advance the ringbuffer tail
68 * @ringbuf: Ringbuffer to advance.
70 * The tail is only updated in our logical ringbuffer struct.
72 static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
74 ringbuf->tail &= ringbuf->size - 1;
77 * intel_logical_ring_emit() - write a DWORD to the ringbuffer.
78 * @ringbuf: Ringbuffer to write to.
79 * @data: DWORD to write.
81 static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
84 iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
87 static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
90 intel_logical_ring_emit(ringbuf, i915_mmio_reg_offset(reg));
93 /* Logical Ring Contexts */
95 /* One extra page is added before LRC for GuC as shared data */
96 #define LRC_GUCSHR_PN (0)
97 #define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1)
98 #define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
100 void intel_lr_context_free(struct intel_context *ctx);
101 uint32_t intel_lr_context_size(struct intel_engine_cs *ring);
102 int intel_lr_context_deferred_alloc(struct intel_context *ctx,
103 struct intel_engine_cs *ring);
104 void intel_lr_context_unpin(struct drm_i915_gem_request *req);
105 void intel_lr_context_reset(struct drm_device *dev,
106 struct intel_context *ctx);
107 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
108 struct intel_engine_cs *ring);
111 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
112 struct i915_execbuffer_params;
113 int intel_execlists_submission(struct i915_execbuffer_params *params,
114 struct drm_i915_gem_execbuffer2 *args,
115 struct list_head *vmas);
116 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
118 void intel_lrc_irq_handler(struct intel_engine_cs *ring);
119 void intel_execlists_retire_requests(struct intel_engine_cs *ring);
121 #endif /* _INTEL_LRC_H_ */