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23 #include "intel_mocs.h"
24 #include "intel_lrc.h"
25 #include "intel_ringbuffer.h"
27 /* structures required */
28 struct drm_i915_mocs_entry {
33 struct drm_i915_mocs_table {
35 const struct drm_i915_mocs_entry *table;
38 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
39 #define LE_CACHEABILITY(value) ((value) << 0)
40 #define LE_TGT_CACHE(value) ((value) << 2)
41 #define LE_LRUM(value) ((value) << 4)
42 #define LE_AOM(value) ((value) << 6)
43 #define LE_RSC(value) ((value) << 7)
44 #define LE_SCC(value) ((value) << 8)
45 #define LE_PFM(value) ((value) << 11)
46 #define LE_SCF(value) ((value) << 14)
48 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
49 #define L3_ESC(value) ((value) << 0)
50 #define L3_SCC(value) ((value) << 1)
51 #define L3_CACHEABILITY(value) ((value) << 4)
54 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
56 /* (e)LLC caching options */
57 #define LE_PAGETABLE 0
62 /* L3 caching options */
69 #define LE_TC_PAGETABLE 0
71 #define LE_TC_LLC_ELLC 2
72 #define LE_TC_LLC_ELLC_ALT 3
77 * These are the MOCS tables that are programmed across all the rings.
78 * The control value is programmed to all the rings that support the
79 * MOCS registers. While the l3cc_values are only programmed to the
80 * LNCFCMOCS0 - LNCFCMOCS32 registers.
82 * These tables are intended to be kept reasonably consistent across
83 * platforms. However some of the fields are not applicable to all of
86 * Entries not part of the following tables are undefined as far as
87 * userspace is concerned and shouldn't be relied upon. For the time
88 * being they will be implicitly initialized to the strictest caching
89 * configuration (uncached) to guarantee forwards compatibility with
90 * userspace programs written against more recent kernels providing
91 * additional MOCS entries.
93 * NOTE: These tables MUST start with being uncached and the length
94 * MUST be less than 63 as the last two registers are reserved
95 * by the hardware. These tables are part of the kernel ABI and
96 * may only be updated incrementally by adding entries at the
99 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
100 [I915_MOCS_UNCACHED] = {
102 .control_value = LE_CACHEABILITY(LE_UC) |
103 LE_TGT_CACHE(LE_TC_LLC_ELLC) |
104 LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
105 LE_PFM(0) | LE_SCF(0),
108 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
112 .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
113 LE_TGT_CACHE(LE_TC_LLC_ELLC) |
114 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
115 LE_PFM(0) | LE_SCF(0),
117 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
119 [I915_MOCS_CACHED] = {
121 .control_value = LE_CACHEABILITY(LE_WB) |
122 LE_TGT_CACHE(LE_TC_LLC_ELLC) |
123 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
124 LE_PFM(0) | LE_SCF(0),
126 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
130 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
131 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
132 [I915_MOCS_UNCACHED] = {
134 .control_value = LE_CACHEABILITY(LE_UC) |
135 LE_TGT_CACHE(LE_TC_LLC_ELLC) |
136 LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
137 LE_PFM(0) | LE_SCF(0),
140 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
144 .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
145 LE_TGT_CACHE(LE_TC_LLC_ELLC) |
146 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
147 LE_PFM(0) | LE_SCF(0),
150 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
152 [I915_MOCS_CACHED] = {
154 .control_value = LE_CACHEABILITY(LE_UC) |
155 LE_TGT_CACHE(LE_TC_LLC_ELLC) |
156 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
157 LE_PFM(0) | LE_SCF(0),
160 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
165 * get_mocs_settings()
166 * @dev_priv: i915 device.
167 * @table: Output table that will be made to point at appropriate
168 * MOCS values for the device.
170 * This function will return the values of the MOCS table that needs to
171 * be programmed for the platform. It will return the values that need
172 * to be programmed and if they need to be programmed.
174 * Return: true if there are applicable MOCS settings for the device.
176 static bool get_mocs_settings(struct drm_i915_private *dev_priv,
177 struct drm_i915_mocs_table *table)
181 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
182 table->size = ARRAY_SIZE(skylake_mocs_table);
183 table->table = skylake_mocs_table;
185 } else if (IS_BROXTON(dev_priv)) {
186 table->size = ARRAY_SIZE(broxton_mocs_table);
187 table->table = broxton_mocs_table;
190 WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
191 "Platform that should have a MOCS table does not.\n");
194 /* WaDisableSkipCaching:skl,bxt,kbl */
195 if (IS_GEN9(dev_priv)) {
198 for (i = 0; i < table->size; i++)
199 if (WARN_ON(table->table[i].l3cc_value &
200 (L3_ESC(1) | L3_SCC(0x7))))
207 static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
211 return GEN9_GFX_MOCS(index);
213 return GEN9_MFX0_MOCS(index);
215 return GEN9_BLT_MOCS(index);
217 return GEN9_VEBOX_MOCS(index);
219 return GEN9_MFX1_MOCS(index);
221 MISSING_CASE(engine_id);
222 return INVALID_MMIO_REG;
227 * intel_mocs_init_engine() - emit the mocs control table
228 * @engine: The engine for whom to emit the registers.
230 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
231 * given table starting at the given address.
233 * Return: 0 on success, otherwise the error status.
235 int intel_mocs_init_engine(struct intel_engine_cs *engine)
237 struct drm_i915_private *dev_priv = engine->i915;
238 struct drm_i915_mocs_table table;
241 if (!get_mocs_settings(dev_priv, &table))
244 if (WARN_ON(table.size > GEN9_NUM_MOCS_ENTRIES))
247 for (index = 0; index < table.size; index++)
248 I915_WRITE(mocs_register(engine->id, index),
249 table.table[index].control_value);
252 * Ok, now set the unused entries to uncached. These entries
253 * are officially undefined and no contract for the contents
254 * and settings is given for these entries.
256 * Entry 0 in the table is uncached - so we are just writing
257 * that value to all the used entries.
259 for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
260 I915_WRITE(mocs_register(engine->id, index),
261 table.table[0].control_value);
267 * emit_mocs_control_table() - emit the mocs control table
268 * @req: Request to set up the MOCS table for.
269 * @table: The values to program into the control regs.
271 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
272 * given table starting at the given address.
274 * Return: 0 on success, otherwise the error status.
276 static int emit_mocs_control_table(struct drm_i915_gem_request *req,
277 const struct drm_i915_mocs_table *table)
279 struct intel_ring *ring = req->ring;
280 enum intel_engine_id engine = req->engine->id;
284 if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
287 ret = intel_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
291 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
293 for (index = 0; index < table->size; index++) {
294 intel_ring_emit_reg(ring, mocs_register(engine, index));
295 intel_ring_emit(ring, table->table[index].control_value);
299 * Ok, now set the unused entries to uncached. These entries
300 * are officially undefined and no contract for the contents
301 * and settings is given for these entries.
303 * Entry 0 in the table is uncached - so we are just writing
304 * that value to all the used entries.
306 for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
307 intel_ring_emit_reg(ring, mocs_register(engine, index));
308 intel_ring_emit(ring, table->table[0].control_value);
311 intel_ring_emit(ring, MI_NOOP);
312 intel_ring_advance(ring);
317 static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
321 return table->table[low].l3cc_value |
322 table->table[high].l3cc_value << 16;
326 * emit_mocs_l3cc_table() - emit the mocs control table
327 * @req: Request to set up the MOCS table for.
328 * @table: The values to program into the control regs.
330 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
331 * given table starting at the given address. This register set is
332 * programmed in pairs.
334 * Return: 0 on success, otherwise the error status.
336 static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
337 const struct drm_i915_mocs_table *table)
339 struct intel_ring *ring = req->ring;
343 if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
346 ret = intel_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
350 intel_ring_emit(ring,
351 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
353 for (i = 0; i < table->size/2; i++) {
354 intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i));
355 intel_ring_emit(ring, l3cc_combine(table, 2*i, 2*i+1));
358 if (table->size & 0x01) {
359 /* Odd table size - 1 left over */
360 intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i));
361 intel_ring_emit(ring, l3cc_combine(table, 2*i, 0));
366 * Now set the rest of the table to uncached - use entry 0 as
367 * this will be uncached. Leave the last pair uninitialised as
368 * they are reserved by the hardware.
370 for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
371 intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i));
372 intel_ring_emit(ring, l3cc_combine(table, 0, 0));
375 intel_ring_emit(ring, MI_NOOP);
376 intel_ring_advance(ring);
382 * intel_mocs_init_l3cc_table() - program the mocs control table
383 * @dev: The the device to be programmed.
385 * This function simply programs the mocs registers for the given table
386 * starting at the given address. This register set is programmed in pairs.
388 * These registers may get programmed more than once, it is simpler to
389 * re-program 32 registers than maintain the state of when they were programmed.
390 * We are always reprogramming with the same values and this only on context
395 void intel_mocs_init_l3cc_table(struct drm_device *dev)
397 struct drm_i915_private *dev_priv = to_i915(dev);
398 struct drm_i915_mocs_table table;
401 if (!get_mocs_settings(dev_priv, &table))
404 for (i = 0; i < table.size/2; i++)
405 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 2*i+1));
407 /* Odd table size - 1 left over */
408 if (table.size & 0x01) {
409 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 0));
414 * Now set the rest of the table to uncached - use entry 0 as
415 * this will be uncached. Leave the last pair as initialised as
416 * they are reserved by the hardware.
418 for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++)
419 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0));
423 * intel_rcs_context_init_mocs() - program the MOCS register.
424 * @req: Request to set up the MOCS tables for.
426 * This function will emit a batch buffer with the values required for
427 * programming the MOCS register values for all the currently supported
430 * These registers are partially stored in the RCS context, so they are
431 * emitted at the same time so that when a context is created these registers
432 * are set up. These registers have to be emitted into the start of the
433 * context as setting the ELSP will re-init some of these registers back
436 * Return: 0 on success, otherwise the error status.
438 int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
440 struct drm_i915_mocs_table t;
443 if (get_mocs_settings(req->i915, &t)) {
444 /* Program the RCS control registers */
445 ret = emit_mocs_control_table(req, &t);
449 /* Now program the l3cc registers */
450 ret = emit_mocs_l3cc_table(req, &t);