4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <linux/seq_file.h>
35 #include "intel_drv.h"
37 /* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41 #define IMAGE_MAX_WIDTH 2048
42 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43 /* on 830 and 845 these large limits result in the card hanging */
44 #define IMAGE_MAX_WIDTH_LEGACY 1024
45 #define IMAGE_MAX_HEIGHT_LEGACY 1088
47 /* overlay register definitions */
49 #define OCMD_TILED_SURFACE (0x1<<19)
50 #define OCMD_MIRROR_MASK (0x3<<17)
51 #define OCMD_MIRROR_MODE (0x3<<17)
52 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53 #define OCMD_MIRROR_VERTICAL (0x2<<17)
54 #define OCMD_MIRROR_BOTH (0x3<<17)
55 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_422_PACKED (0x8<<10)
64 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65 #define OCMD_YUV_420_PLANAR (0xc<<10)
66 #define OCMD_YUV_422_PLANAR (0xd<<10)
67 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
70 #define OCMD_BUF_TYPE_MASK (0x1<<5)
71 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
72 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
73 #define OCMD_TEST_MODE (0x1<<4)
74 #define OCMD_BUFFER_SELECT (0x3<<2)
75 #define OCMD_BUFFER0 (0x0<<2)
76 #define OCMD_BUFFER1 (0x1<<2)
77 #define OCMD_FIELD_SELECT (0x1<<2)
78 #define OCMD_FIELD0 (0x0<<1)
79 #define OCMD_FIELD1 (0x1<<1)
80 #define OCMD_ENABLE (0x1<<0)
82 /* OCONFIG register */
83 #define OCONF_PIPE_MASK (0x1<<18)
84 #define OCONF_PIPE_A (0x0<<18)
85 #define OCONF_PIPE_B (0x1<<18)
86 #define OCONF_GAMMA2_ENABLE (0x1<<16)
87 #define OCONF_CSC_MODE_BT601 (0x0<<5)
88 #define OCONF_CSC_MODE_BT709 (0x1<<5)
89 #define OCONF_CSC_BYPASS (0x1<<4)
90 #define OCONF_CC_OUT_8BIT (0x1<<3)
91 #define OCONF_TEST_MODE (0x1<<2)
92 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
93 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
95 /* DCLRKM (dst-key) register */
96 #define DST_KEY_ENABLE (0x1<<31)
97 #define CLK_RGB24_MASK 0x0
98 #define CLK_RGB16_MASK 0x070307
99 #define CLK_RGB15_MASK 0x070707
100 #define CLK_RGB8I_MASK 0xffffff
102 #define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104 #define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
107 /* overlay flip addr flag */
108 #define OFC_UPDATE 0x1
110 /* polyphase filter coefficients */
111 #define N_HORIZ_Y_TAPS 5
112 #define N_VERT_Y_TAPS 3
113 #define N_HORIZ_UV_TAPS 3
114 #define N_VERT_UV_TAPS 3
118 /* memory bufferd overlay registers */
119 struct overlay_registers {
147 u32 RESERVED1; /* 0x6C */
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
173 /* overlay flip addr flag */
174 #define OFC_UPDATE 0x1
176 #define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
177 #define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev))
180 static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
182 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
183 struct overlay_registers *regs;
185 /* no recursive mappings */
186 BUG_ON(overlay->virt_addr);
188 if (OVERLAY_NONPHYSICAL(overlay->dev)) {
189 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
190 overlay->reg_bo->gtt_offset);
193 DRM_ERROR("failed to map overlay regs in GTT\n");
197 regs = overlay->reg_bo->phys_obj->handle->vaddr;
199 return overlay->virt_addr = regs;
202 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
204 if (OVERLAY_NONPHYSICAL(overlay->dev))
205 io_mapping_unmap_atomic(overlay->virt_addr);
207 overlay->virt_addr = NULL;
212 /* overlay needs to be disable in OCMD reg */
213 static int intel_overlay_on(struct intel_overlay *overlay)
215 struct drm_device *dev = overlay->dev;
217 drm_i915_private_t *dev_priv = dev->dev_private;
219 BUG_ON(overlay->active);
222 overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
225 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
226 OUT_RING(overlay->flip_addr | OFC_UPDATE);
227 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
231 overlay->last_flip_req =
232 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
233 if (overlay->last_flip_req == 0)
236 ret = i915_do_wait_request(dev,
237 overlay->last_flip_req, 1, &dev_priv->render_ring);
241 overlay->hw_wedged = 0;
242 overlay->last_flip_req = 0;
246 /* overlay needs to be enabled in OCMD reg */
247 static void intel_overlay_continue(struct intel_overlay *overlay,
248 bool load_polyphase_filter)
250 struct drm_device *dev = overlay->dev;
251 drm_i915_private_t *dev_priv = dev->dev_private;
252 u32 flip_addr = overlay->flip_addr;
255 BUG_ON(!overlay->active);
257 if (load_polyphase_filter)
258 flip_addr |= OFC_UPDATE;
260 /* check for underruns */
261 tmp = I915_READ(DOVSTA);
263 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
266 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
270 overlay->last_flip_req =
271 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
274 static int intel_overlay_wait_flip(struct intel_overlay *overlay)
276 struct drm_device *dev = overlay->dev;
277 drm_i915_private_t *dev_priv = dev->dev_private;
281 if (overlay->last_flip_req != 0) {
282 ret = i915_do_wait_request(dev, overlay->last_flip_req,
283 1, &dev_priv->render_ring);
285 overlay->last_flip_req = 0;
287 tmp = I915_READ(ISR);
289 if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
294 /* synchronous slowpath */
295 overlay->hw_wedged = RELEASE_OLD_VID;
298 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
302 overlay->last_flip_req =
303 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
304 if (overlay->last_flip_req == 0)
307 ret = i915_do_wait_request(dev, overlay->last_flip_req,
308 1, &dev_priv->render_ring);
312 overlay->hw_wedged = 0;
313 overlay->last_flip_req = 0;
317 /* overlay needs to be disabled in OCMD reg */
318 static int intel_overlay_off(struct intel_overlay *overlay)
320 u32 flip_addr = overlay->flip_addr;
321 struct drm_device *dev = overlay->dev;
322 drm_i915_private_t *dev_priv = dev->dev_private;
325 BUG_ON(!overlay->active);
327 /* According to intel docs the overlay hw may hang (when switching
328 * off) without loading the filter coeffs. It is however unclear whether
329 * this applies to the disabling of the overlay or to the switching off
330 * of the hw. Do it in both cases */
331 flip_addr |= OFC_UPDATE;
333 /* wait for overlay to go idle */
334 overlay->hw_wedged = SWITCH_OFF_STAGE_1;
337 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
339 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
343 overlay->last_flip_req =
344 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
345 if (overlay->last_flip_req == 0)
348 ret = i915_do_wait_request(dev, overlay->last_flip_req,
349 1, &dev_priv->render_ring);
353 /* turn overlay off */
354 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
357 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
359 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
363 overlay->last_flip_req =
364 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
365 if (overlay->last_flip_req == 0)
368 ret = i915_do_wait_request(dev, overlay->last_flip_req,
369 1, &dev_priv->render_ring);
373 overlay->hw_wedged = 0;
374 overlay->last_flip_req = 0;
378 static void intel_overlay_off_tail(struct intel_overlay *overlay)
380 struct drm_gem_object *obj;
382 /* never have the overlay hw on without showing a frame */
383 BUG_ON(!overlay->vid_bo);
384 obj = &overlay->vid_bo->base;
386 i915_gem_object_unpin(obj);
387 drm_gem_object_unreference(obj);
388 overlay->vid_bo = NULL;
390 overlay->crtc->overlay = NULL;
391 overlay->crtc = NULL;
395 /* recover from an interruption due to a signal
396 * We have to be careful not to repeat work forever an make forward progess. */
397 int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
400 struct drm_device *dev = overlay->dev;
401 struct drm_gem_object *obj;
402 drm_i915_private_t *dev_priv = dev->dev_private;
406 if (overlay->hw_wedged == HW_WEDGED)
409 if (overlay->last_flip_req == 0) {
410 overlay->last_flip_req =
411 i915_add_request(dev, NULL, 0, &dev_priv->render_ring);
412 if (overlay->last_flip_req == 0)
416 ret = i915_do_wait_request(dev, overlay->last_flip_req,
417 interruptible, &dev_priv->render_ring);
421 switch (overlay->hw_wedged) {
422 case RELEASE_OLD_VID:
423 obj = &overlay->old_vid_bo->base;
424 i915_gem_object_unpin(obj);
425 drm_gem_object_unreference(obj);
426 overlay->old_vid_bo = NULL;
428 case SWITCH_OFF_STAGE_1:
429 flip_addr = overlay->flip_addr;
430 flip_addr |= OFC_UPDATE;
432 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
435 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
437 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
441 overlay->last_flip_req = i915_add_request(dev, NULL,
442 0, &dev_priv->render_ring);
443 if (overlay->last_flip_req == 0)
446 ret = i915_do_wait_request(dev, overlay->last_flip_req,
447 interruptible, &dev_priv->render_ring);
451 case SWITCH_OFF_STAGE_2:
452 intel_overlay_off_tail(overlay);
455 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
458 overlay->hw_wedged = 0;
459 overlay->last_flip_req = 0;
463 /* Wait for pending overlay flip and release old frame.
464 * Needs to be called before the overlay register are changed
465 * via intel_overlay_(un)map_regs_atomic */
466 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
469 struct drm_gem_object *obj;
471 /* only wait if there is actually an old frame to release to
472 * guarantee forward progress */
473 if (!overlay->old_vid_bo)
476 ret = intel_overlay_wait_flip(overlay);
480 obj = &overlay->old_vid_bo->base;
481 i915_gem_object_unpin(obj);
482 drm_gem_object_unreference(obj);
483 overlay->old_vid_bo = NULL;
488 struct put_image_params {
505 static int packed_depth_bytes(u32 format)
507 switch (format & I915_OVERLAY_DEPTH_MASK) {
508 case I915_OVERLAY_YUV422:
510 case I915_OVERLAY_YUV411:
511 /* return 6; not implemented */
517 static int packed_width_bytes(u32 format, short width)
519 switch (format & I915_OVERLAY_DEPTH_MASK) {
520 case I915_OVERLAY_YUV422:
527 static int uv_hsubsampling(u32 format)
529 switch (format & I915_OVERLAY_DEPTH_MASK) {
530 case I915_OVERLAY_YUV422:
531 case I915_OVERLAY_YUV420:
533 case I915_OVERLAY_YUV411:
534 case I915_OVERLAY_YUV410:
541 static int uv_vsubsampling(u32 format)
543 switch (format & I915_OVERLAY_DEPTH_MASK) {
544 case I915_OVERLAY_YUV420:
545 case I915_OVERLAY_YUV410:
547 case I915_OVERLAY_YUV422:
548 case I915_OVERLAY_YUV411:
555 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
557 u32 mask, shift, ret;
565 ret = ((offset + width + mask) >> shift) - (offset >> shift);
572 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
573 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
574 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
575 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
576 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
577 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
578 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
579 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
580 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
581 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
582 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
583 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
584 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
585 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
586 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
587 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
588 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
589 0xb000, 0x3000, 0x0800, 0x3000, 0xb000};
590 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
591 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
592 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
593 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
594 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
595 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
596 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
597 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
598 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
599 0x3000, 0x0800, 0x3000};
601 static void update_polyphase_filter(struct overlay_registers *regs)
603 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
604 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
607 static bool update_scaling_factors(struct intel_overlay *overlay,
608 struct overlay_registers *regs,
609 struct put_image_params *params)
611 /* fixed point with a 12 bit shift */
612 u32 xscale, yscale, xscale_UV, yscale_UV;
614 #define FRACT_MASK 0xfff
615 bool scale_changed = false;
616 int uv_hscale = uv_hsubsampling(params->format);
617 int uv_vscale = uv_vsubsampling(params->format);
619 if (params->dst_w > 1)
620 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
623 xscale = 1 << FP_SHIFT;
625 if (params->dst_h > 1)
626 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
629 yscale = 1 << FP_SHIFT;
631 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
632 xscale_UV = xscale/uv_hscale;
633 yscale_UV = yscale/uv_vscale;
634 /* make the Y scale to UV scale ratio an exact multiply */
635 xscale = xscale_UV * uv_hscale;
636 yscale = yscale_UV * uv_vscale;
642 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
643 scale_changed = true;
644 overlay->old_xscale = xscale;
645 overlay->old_yscale = yscale;
647 regs->YRGBSCALE = ((yscale & FRACT_MASK) << 20)
648 | ((xscale >> FP_SHIFT) << 16)
649 | ((xscale & FRACT_MASK) << 3);
650 regs->UVSCALE = ((yscale_UV & FRACT_MASK) << 20)
651 | ((xscale_UV >> FP_SHIFT) << 16)
652 | ((xscale_UV & FRACT_MASK) << 3);
653 regs->UVSCALEV = ((yscale >> FP_SHIFT) << 16)
654 | ((yscale_UV >> FP_SHIFT) << 0);
657 update_polyphase_filter(regs);
659 return scale_changed;
662 static void update_colorkey(struct intel_overlay *overlay,
663 struct overlay_registers *regs)
665 u32 key = overlay->color_key;
666 switch (overlay->crtc->base.fb->bits_per_pixel) {
669 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
671 if (overlay->crtc->base.fb->depth == 15) {
672 regs->DCLRKV = RGB15_TO_COLORKEY(key);
673 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
675 regs->DCLRKV = RGB16_TO_COLORKEY(key);
676 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
681 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
685 static u32 overlay_cmd_reg(struct put_image_params *params)
687 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
689 if (params->format & I915_OVERLAY_YUV_PLANAR) {
690 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
691 case I915_OVERLAY_YUV422:
692 cmd |= OCMD_YUV_422_PLANAR;
694 case I915_OVERLAY_YUV420:
695 cmd |= OCMD_YUV_420_PLANAR;
697 case I915_OVERLAY_YUV411:
698 case I915_OVERLAY_YUV410:
699 cmd |= OCMD_YUV_410_PLANAR;
702 } else { /* YUV packed */
703 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
704 case I915_OVERLAY_YUV422:
705 cmd |= OCMD_YUV_422_PACKED;
707 case I915_OVERLAY_YUV411:
708 cmd |= OCMD_YUV_411_PACKED;
712 switch (params->format & I915_OVERLAY_SWAP_MASK) {
713 case I915_OVERLAY_NO_SWAP:
715 case I915_OVERLAY_UV_SWAP:
718 case I915_OVERLAY_Y_SWAP:
721 case I915_OVERLAY_Y_AND_UV_SWAP:
722 cmd |= OCMD_Y_AND_UV_SWAP;
730 int intel_overlay_do_put_image(struct intel_overlay *overlay,
731 struct drm_gem_object *new_bo,
732 struct put_image_params *params)
735 struct overlay_registers *regs;
736 bool scale_changed = false;
737 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
738 struct drm_device *dev = overlay->dev;
740 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
741 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
744 ret = intel_overlay_release_old_vid(overlay);
748 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
752 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
756 if (!overlay->active) {
757 regs = intel_overlay_map_regs_atomic(overlay);
762 regs->OCONFIG = OCONF_CC_OUT_8BIT;
763 if (IS_I965GM(overlay->dev))
764 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
765 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
766 OCONF_PIPE_A : OCONF_PIPE_B;
767 intel_overlay_unmap_regs_atomic(overlay);
769 ret = intel_overlay_on(overlay);
774 regs = intel_overlay_map_regs_atomic(overlay);
780 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
781 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
783 if (params->format & I915_OVERLAY_YUV_PACKED)
784 tmp_width = packed_width_bytes(params->format, params->src_w);
786 tmp_width = params->src_w;
788 regs->SWIDTH = params->src_w;
789 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
790 params->offset_Y, tmp_width);
791 regs->SHEIGHT = params->src_h;
792 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
793 regs->OSTRIDE = params->stride_Y;
795 if (params->format & I915_OVERLAY_YUV_PLANAR) {
796 int uv_hscale = uv_hsubsampling(params->format);
797 int uv_vscale = uv_vsubsampling(params->format);
799 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
800 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
801 params->src_w/uv_hscale);
802 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
803 params->src_w/uv_hscale);
804 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
805 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
806 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
807 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
808 regs->OSTRIDE |= params->stride_UV << 16;
811 scale_changed = update_scaling_factors(overlay, regs, params);
813 update_colorkey(overlay, regs);
815 regs->OCMD = overlay_cmd_reg(params);
817 intel_overlay_unmap_regs_atomic(overlay);
819 intel_overlay_continue(overlay, scale_changed);
821 overlay->old_vid_bo = overlay->vid_bo;
822 overlay->vid_bo = to_intel_bo(new_bo);
827 i915_gem_object_unpin(new_bo);
831 int intel_overlay_switch_off(struct intel_overlay *overlay)
834 struct overlay_registers *regs;
835 struct drm_device *dev = overlay->dev;
837 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
838 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
840 if (overlay->hw_wedged) {
841 ret = intel_overlay_recover_from_interrupt(overlay, 1);
846 if (!overlay->active)
849 ret = intel_overlay_release_old_vid(overlay);
853 regs = intel_overlay_map_regs_atomic(overlay);
855 intel_overlay_unmap_regs_atomic(overlay);
857 ret = intel_overlay_off(overlay);
861 intel_overlay_off_tail(overlay);
866 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
867 struct intel_crtc *crtc)
869 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
871 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
873 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
876 pipeconf = I915_READ(pipeconf_reg);
878 /* can't use the overlay with double wide pipe */
879 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
885 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
887 struct drm_device *dev = overlay->dev;
888 drm_i915_private_t *dev_priv = dev->dev_private;
890 u32 pfit_control = I915_READ(PFIT_CONTROL);
892 /* XXX: This is not the same logic as in the xorg driver, but more in
893 * line with the intel documentation for the i965 */
894 if (!IS_I965G(dev) && (pfit_control & VERT_AUTO_SCALE)) {
895 ratio = I915_READ(PFIT_AUTO_RATIOS) >> PFIT_VERT_SCALE_SHIFT;
896 } else { /* on i965 use the PGM reg to read out the autoscaler values */
897 ratio = I915_READ(PFIT_PGM_RATIOS);
899 ratio >>= PFIT_VERT_SCALE_SHIFT_965;
901 ratio >>= PFIT_VERT_SCALE_SHIFT;
904 overlay->pfit_vscale_ratio = ratio;
907 static int check_overlay_dst(struct intel_overlay *overlay,
908 struct drm_intel_overlay_put_image *rec)
910 struct drm_display_mode *mode = &overlay->crtc->base.mode;
912 if ((rec->dst_x < mode->crtc_hdisplay)
913 && (rec->dst_x + rec->dst_width
914 <= mode->crtc_hdisplay)
915 && (rec->dst_y < mode->crtc_vdisplay)
916 && (rec->dst_y + rec->dst_height
917 <= mode->crtc_vdisplay))
923 static int check_overlay_scaling(struct put_image_params *rec)
927 /* downscaling limit is 8.0 */
928 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
931 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
938 static int check_overlay_src(struct drm_device *dev,
939 struct drm_intel_overlay_put_image *rec,
940 struct drm_gem_object *new_bo)
944 int uv_hscale = uv_hsubsampling(rec->flags);
945 int uv_vscale = uv_vsubsampling(rec->flags);
948 /* check src dimensions */
949 if (IS_845G(dev) || IS_I830(dev)) {
950 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY
951 || rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
954 if (rec->src_height > IMAGE_MAX_HEIGHT
955 || rec->src_width > IMAGE_MAX_WIDTH)
958 /* better safe than sorry, use 4 as the maximal subsampling ratio */
959 if (rec->src_height < N_VERT_Y_TAPS*4
960 || rec->src_width < N_HORIZ_Y_TAPS*4)
963 /* check alignment constraints */
964 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
965 case I915_OVERLAY_RGB:
966 /* not implemented */
968 case I915_OVERLAY_YUV_PACKED:
969 depth = packed_depth_bytes(rec->flags);
974 /* ignore UV planes */
978 /* check pixel alignment */
979 if (rec->offset_Y % depth)
982 case I915_OVERLAY_YUV_PLANAR:
983 if (uv_vscale < 0 || uv_hscale < 0)
985 /* no offset restrictions for planar formats */
991 if (rec->src_width % uv_hscale)
994 /* stride checking */
995 if (IS_I830(dev) || IS_845G(dev))
1000 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1002 if (IS_I965G(dev) && rec->stride_Y < 512)
1005 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1007 if (rec->stride_Y > tmp*1024 || rec->stride_UV > 2*1024)
1010 /* check buffer dimensions */
1011 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1012 case I915_OVERLAY_RGB:
1013 case I915_OVERLAY_YUV_PACKED:
1014 /* always 4 Y values per depth pixels */
1015 if (packed_width_bytes(rec->flags, rec->src_width)
1019 tmp = rec->stride_Y*rec->src_height;
1020 if (rec->offset_Y + tmp > new_bo->size)
1023 case I915_OVERLAY_YUV_PLANAR:
1024 if (rec->src_width > rec->stride_Y)
1026 if (rec->src_width/uv_hscale > rec->stride_UV)
1029 tmp = rec->stride_Y*rec->src_height;
1030 if (rec->offset_Y + tmp > new_bo->size)
1032 tmp = rec->stride_UV*rec->src_height;
1034 if (rec->offset_U + tmp > new_bo->size
1035 || rec->offset_V + tmp > new_bo->size)
1043 int intel_overlay_put_image(struct drm_device *dev, void *data,
1044 struct drm_file *file_priv)
1046 struct drm_intel_overlay_put_image *put_image_rec = data;
1047 drm_i915_private_t *dev_priv = dev->dev_private;
1048 struct intel_overlay *overlay;
1049 struct drm_mode_object *drmmode_obj;
1050 struct intel_crtc *crtc;
1051 struct drm_gem_object *new_bo;
1052 struct put_image_params *params;
1056 DRM_ERROR("called with no initialization\n");
1060 overlay = dev_priv->overlay;
1062 DRM_DEBUG("userspace bug: no overlay\n");
1066 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1067 mutex_lock(&dev->mode_config.mutex);
1068 mutex_lock(&dev->struct_mutex);
1070 ret = intel_overlay_switch_off(overlay);
1072 mutex_unlock(&dev->struct_mutex);
1073 mutex_unlock(&dev->mode_config.mutex);
1078 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1082 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1083 DRM_MODE_OBJECT_CRTC);
1088 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1090 new_bo = drm_gem_object_lookup(dev, file_priv,
1091 put_image_rec->bo_handle);
1097 mutex_lock(&dev->mode_config.mutex);
1098 mutex_lock(&dev->struct_mutex);
1100 if (overlay->hw_wedged) {
1101 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1106 if (overlay->crtc != crtc) {
1107 struct drm_display_mode *mode = &crtc->base.mode;
1108 ret = intel_overlay_switch_off(overlay);
1112 ret = check_overlay_possible_on_crtc(overlay, crtc);
1116 overlay->crtc = crtc;
1117 crtc->overlay = overlay;
1119 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1120 /* and line to wide, i.e. one-line-mode */
1121 && mode->hdisplay > 1024) {
1122 overlay->pfit_active = 1;
1123 update_pfit_vscale_ratio(overlay);
1125 overlay->pfit_active = 0;
1128 ret = check_overlay_dst(overlay, put_image_rec);
1132 if (overlay->pfit_active) {
1133 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1134 overlay->pfit_vscale_ratio);
1135 /* shifting right rounds downwards, so add 1 */
1136 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1137 overlay->pfit_vscale_ratio) + 1;
1139 params->dst_y = put_image_rec->dst_y;
1140 params->dst_h = put_image_rec->dst_height;
1142 params->dst_x = put_image_rec->dst_x;
1143 params->dst_w = put_image_rec->dst_width;
1145 params->src_w = put_image_rec->src_width;
1146 params->src_h = put_image_rec->src_height;
1147 params->src_scan_w = put_image_rec->src_scan_width;
1148 params->src_scan_h = put_image_rec->src_scan_height;
1149 if (params->src_scan_h > params->src_h
1150 || params->src_scan_w > params->src_w) {
1155 ret = check_overlay_src(dev, put_image_rec, new_bo);
1158 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1159 params->stride_Y = put_image_rec->stride_Y;
1160 params->stride_UV = put_image_rec->stride_UV;
1161 params->offset_Y = put_image_rec->offset_Y;
1162 params->offset_U = put_image_rec->offset_U;
1163 params->offset_V = put_image_rec->offset_V;
1165 /* Check scaling after src size to prevent a divide-by-zero. */
1166 ret = check_overlay_scaling(params);
1170 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1174 mutex_unlock(&dev->struct_mutex);
1175 mutex_unlock(&dev->mode_config.mutex);
1182 mutex_unlock(&dev->struct_mutex);
1183 mutex_unlock(&dev->mode_config.mutex);
1184 drm_gem_object_unreference_unlocked(new_bo);
1191 static void update_reg_attrs(struct intel_overlay *overlay,
1192 struct overlay_registers *regs)
1194 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1195 regs->OCLRC1 = overlay->saturation;
1198 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1202 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1205 for (i = 0; i < 3; i++) {
1206 if (((gamma1 >> i * 8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1213 static bool check_gamma5_errata(u32 gamma5)
1217 for (i = 0; i < 3; i++) {
1218 if (((gamma5 >> i*8) & 0xff) == 0x80)
1225 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1227 if (!check_gamma_bounds(0, attrs->gamma0)
1228 || !check_gamma_bounds(attrs->gamma0, attrs->gamma1)
1229 || !check_gamma_bounds(attrs->gamma1, attrs->gamma2)
1230 || !check_gamma_bounds(attrs->gamma2, attrs->gamma3)
1231 || !check_gamma_bounds(attrs->gamma3, attrs->gamma4)
1232 || !check_gamma_bounds(attrs->gamma4, attrs->gamma5)
1233 || !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1235 if (!check_gamma5_errata(attrs->gamma5))
1240 int intel_overlay_attrs(struct drm_device *dev, void *data,
1241 struct drm_file *file_priv)
1243 struct drm_intel_overlay_attrs *attrs = data;
1244 drm_i915_private_t *dev_priv = dev->dev_private;
1245 struct intel_overlay *overlay;
1246 struct overlay_registers *regs;
1250 DRM_ERROR("called with no initialization\n");
1254 overlay = dev_priv->overlay;
1256 DRM_DEBUG("userspace bug: no overlay\n");
1260 mutex_lock(&dev->mode_config.mutex);
1261 mutex_lock(&dev->struct_mutex);
1263 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1264 attrs->color_key = overlay->color_key;
1265 attrs->brightness = overlay->brightness;
1266 attrs->contrast = overlay->contrast;
1267 attrs->saturation = overlay->saturation;
1270 attrs->gamma0 = I915_READ(OGAMC0);
1271 attrs->gamma1 = I915_READ(OGAMC1);
1272 attrs->gamma2 = I915_READ(OGAMC2);
1273 attrs->gamma3 = I915_READ(OGAMC3);
1274 attrs->gamma4 = I915_READ(OGAMC4);
1275 attrs->gamma5 = I915_READ(OGAMC5);
1279 overlay->color_key = attrs->color_key;
1280 if (attrs->brightness >= -128 && attrs->brightness <= 127) {
1281 overlay->brightness = attrs->brightness;
1286 if (attrs->contrast <= 255) {
1287 overlay->contrast = attrs->contrast;
1292 if (attrs->saturation <= 1023) {
1293 overlay->saturation = attrs->saturation;
1299 regs = intel_overlay_map_regs_atomic(overlay);
1305 update_reg_attrs(overlay, regs);
1307 intel_overlay_unmap_regs_atomic(overlay);
1309 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1310 if (!IS_I9XX(dev)) {
1315 if (overlay->active) {
1320 ret = check_gamma(attrs);
1324 I915_WRITE(OGAMC0, attrs->gamma0);
1325 I915_WRITE(OGAMC1, attrs->gamma1);
1326 I915_WRITE(OGAMC2, attrs->gamma2);
1327 I915_WRITE(OGAMC3, attrs->gamma3);
1328 I915_WRITE(OGAMC4, attrs->gamma4);
1329 I915_WRITE(OGAMC5, attrs->gamma5);
1335 mutex_unlock(&dev->struct_mutex);
1336 mutex_unlock(&dev->mode_config.mutex);
1341 void intel_setup_overlay(struct drm_device *dev)
1343 drm_i915_private_t *dev_priv = dev->dev_private;
1344 struct intel_overlay *overlay;
1345 struct drm_gem_object *reg_bo;
1346 struct overlay_registers *regs;
1349 if (!OVERLAY_EXISTS(dev))
1352 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1357 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1360 overlay->reg_bo = to_intel_bo(reg_bo);
1362 if (OVERLAY_NONPHYSICAL(dev)) {
1363 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1365 DRM_ERROR("failed to pin overlay register bo\n");
1368 overlay->flip_addr = overlay->reg_bo->gtt_offset;
1370 ret = i915_gem_attach_phys_object(dev, reg_bo,
1371 I915_GEM_PHYS_OVERLAY_REGS,
1374 DRM_ERROR("failed to attach phys overlay regs\n");
1377 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1380 /* init all values */
1381 overlay->color_key = 0x0101fe;
1382 overlay->brightness = -19;
1383 overlay->contrast = 75;
1384 overlay->saturation = 146;
1386 regs = intel_overlay_map_regs_atomic(overlay);
1390 memset(regs, 0, sizeof(struct overlay_registers));
1391 update_polyphase_filter(regs);
1393 update_reg_attrs(overlay, regs);
1395 intel_overlay_unmap_regs_atomic(overlay);
1397 dev_priv->overlay = overlay;
1398 DRM_INFO("initialized overlay support\n");
1402 drm_gem_object_unreference(reg_bo);
1408 void intel_cleanup_overlay(struct drm_device *dev)
1410 drm_i915_private_t *dev_priv = dev->dev_private;
1412 if (dev_priv->overlay) {
1413 /* The bo's should be free'd by the generic code already.
1414 * Furthermore modesetting teardown happens beforehand so the
1415 * hardware should be off already */
1416 BUG_ON(dev_priv->overlay->active);
1418 kfree(dev_priv->overlay);
1422 struct intel_overlay_error_state {
1423 struct overlay_registers regs;
1429 struct intel_overlay_error_state *
1430 intel_overlay_capture_error_state(struct drm_device *dev)
1432 drm_i915_private_t *dev_priv = dev->dev_private;
1433 struct intel_overlay *overlay = dev_priv->overlay;
1434 struct intel_overlay_error_state *error;
1435 struct overlay_registers __iomem *regs;
1437 if (!overlay || !overlay->active)
1440 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1444 error->dovsta = I915_READ(DOVSTA);
1445 error->isr = I915_READ(ISR);
1446 if (OVERLAY_NONPHYSICAL(overlay->dev))
1447 error->base = (long) overlay->reg_bo->gtt_offset;
1449 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1451 regs = intel_overlay_map_regs_atomic(overlay);
1455 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1456 intel_overlay_unmap_regs_atomic(overlay);
1466 intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1468 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1469 error->dovsta, error->isr);
1470 seq_printf(m, " Register file at 0x%08lx:\n",
1473 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)