4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
33 #include "intel_drv.h"
35 /* Limits for overlay size. According to intel doc, the real limits are:
36 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
37 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
38 * the mininum of both. */
39 #define IMAGE_MAX_WIDTH 2048
40 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
41 /* on 830 and 845 these large limits result in the card hanging */
42 #define IMAGE_MAX_WIDTH_LEGACY 1024
43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
45 /* overlay register definitions */
47 #define OCMD_TILED_SURFACE (0x1<<19)
48 #define OCMD_MIRROR_MASK (0x3<<17)
49 #define OCMD_MIRROR_MODE (0x3<<17)
50 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
51 #define OCMD_MIRROR_VERTICAL (0x2<<17)
52 #define OCMD_MIRROR_BOTH (0x3<<17)
53 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
54 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
55 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
56 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
58 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
60 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
61 #define OCMD_YUV_422_PACKED (0x8<<10)
62 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_420_PLANAR (0xc<<10)
64 #define OCMD_YUV_422_PLANAR (0xd<<10)
65 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
66 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
67 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
68 #define OCMD_BUF_TYPE_MASK (0x1<<5)
69 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
70 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
71 #define OCMD_TEST_MODE (0x1<<4)
72 #define OCMD_BUFFER_SELECT (0x3<<2)
73 #define OCMD_BUFFER0 (0x0<<2)
74 #define OCMD_BUFFER1 (0x1<<2)
75 #define OCMD_FIELD_SELECT (0x1<<2)
76 #define OCMD_FIELD0 (0x0<<1)
77 #define OCMD_FIELD1 (0x1<<1)
78 #define OCMD_ENABLE (0x1<<0)
80 /* OCONFIG register */
81 #define OCONF_PIPE_MASK (0x1<<18)
82 #define OCONF_PIPE_A (0x0<<18)
83 #define OCONF_PIPE_B (0x1<<18)
84 #define OCONF_GAMMA2_ENABLE (0x1<<16)
85 #define OCONF_CSC_MODE_BT601 (0x0<<5)
86 #define OCONF_CSC_MODE_BT709 (0x1<<5)
87 #define OCONF_CSC_BYPASS (0x1<<4)
88 #define OCONF_CC_OUT_8BIT (0x1<<3)
89 #define OCONF_TEST_MODE (0x1<<2)
90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
91 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
93 /* DCLRKM (dst-key) register */
94 #define DST_KEY_ENABLE (0x1<<31)
95 #define CLK_RGB24_MASK 0x0
96 #define CLK_RGB16_MASK 0x070307
97 #define CLK_RGB15_MASK 0x070707
98 #define CLK_RGB8I_MASK 0xffffff
100 #define RGB16_TO_COLORKEY(c) \
101 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
102 #define RGB15_TO_COLORKEY(c) \
103 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
105 /* overlay flip addr flag */
106 #define OFC_UPDATE 0x1
108 /* polyphase filter coefficients */
109 #define N_HORIZ_Y_TAPS 5
110 #define N_VERT_Y_TAPS 3
111 #define N_HORIZ_UV_TAPS 3
112 #define N_VERT_UV_TAPS 3
116 /* memory bufferd overlay registers */
117 struct overlay_registers {
145 u32 RESERVED1; /* 0x6C */
158 u32 FASTHSCALE; /* 0xA0 */
159 u32 UVSCALEV; /* 0xA4 */
160 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
161 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
162 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
163 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
164 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
165 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
166 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
167 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
168 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171 struct intel_overlay {
172 struct drm_device *dev;
173 struct intel_crtc *crtc;
174 struct drm_i915_gem_object *vid_bo;
175 struct drm_i915_gem_object *old_vid_bo;
178 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
180 u32 brightness, contrast, saturation;
181 u32 old_xscale, old_yscale;
182 /* register access */
184 struct drm_i915_gem_object *reg_bo;
186 uint32_t last_flip_req;
187 void (*flip_tail)(struct intel_overlay *);
190 static struct overlay_registers *
191 intel_overlay_map_regs(struct intel_overlay *overlay)
193 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
194 struct overlay_registers *regs;
196 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
197 regs = overlay->reg_bo->phys_obj->handle->vaddr;
199 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
200 overlay->reg_bo->gtt_offset);
205 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
206 struct overlay_registers *regs)
208 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
209 io_mapping_unmap(regs);
212 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
213 struct drm_i915_gem_request *request,
214 void (*tail)(struct intel_overlay *))
216 struct drm_device *dev = overlay->dev;
217 drm_i915_private_t *dev_priv = dev->dev_private;
220 BUG_ON(overlay->last_flip_req);
221 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
226 overlay->last_flip_req = request->seqno;
227 overlay->flip_tail = tail;
228 ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req,
233 overlay->last_flip_req = 0;
237 /* Workaround for i830 bug where pipe a must be enable to change control regs */
239 i830_activate_pipe_a(struct drm_device *dev)
241 drm_i915_private_t *dev_priv = dev->dev_private;
242 struct intel_crtc *crtc;
243 struct drm_crtc_helper_funcs *crtc_funcs;
244 struct drm_display_mode vesa_640x480 = {
245 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
246 752, 800, 0, 480, 489, 492, 525, 0,
247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
250 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
251 if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
254 /* most i8xx have pipe a forced on, so don't trust dpms mode */
255 if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
258 crtc_funcs = crtc->base.helper_private;
259 if (crtc_funcs->dpms == NULL)
262 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
264 mode = drm_mode_duplicate(dev, &vesa_640x480);
265 drm_mode_set_crtcinfo(mode, 0);
266 if (!drm_crtc_helper_set_mode(&crtc->base, mode,
267 crtc->base.x, crtc->base.y,
271 crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
276 i830_deactivate_pipe_a(struct drm_device *dev)
278 drm_i915_private_t *dev_priv = dev->dev_private;
279 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
280 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
282 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
285 /* overlay needs to be disable in OCMD reg */
286 static int intel_overlay_on(struct intel_overlay *overlay)
288 struct drm_device *dev = overlay->dev;
289 struct drm_i915_private *dev_priv = dev->dev_private;
290 struct drm_i915_gem_request *request;
291 int pipe_a_quirk = 0;
294 BUG_ON(overlay->active);
298 pipe_a_quirk = i830_activate_pipe_a(dev);
299 if (pipe_a_quirk < 0)
303 request = kzalloc(sizeof(*request), GFP_KERNEL);
304 if (request == NULL) {
309 ret = BEGIN_LP_RING(4);
315 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
316 OUT_RING(overlay->flip_addr | OFC_UPDATE);
317 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
321 ret = intel_overlay_do_wait_request(overlay, request, NULL);
324 i830_deactivate_pipe_a(dev);
329 /* overlay needs to be enabled in OCMD reg */
330 static int intel_overlay_continue(struct intel_overlay *overlay,
331 bool load_polyphase_filter)
333 struct drm_device *dev = overlay->dev;
334 drm_i915_private_t *dev_priv = dev->dev_private;
335 struct drm_i915_gem_request *request;
336 u32 flip_addr = overlay->flip_addr;
340 BUG_ON(!overlay->active);
342 request = kzalloc(sizeof(*request), GFP_KERNEL);
346 if (load_polyphase_filter)
347 flip_addr |= OFC_UPDATE;
349 /* check for underruns */
350 tmp = I915_READ(DOVSTA);
352 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
354 ret = BEGIN_LP_RING(2);
359 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
363 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
369 overlay->last_flip_req = request->seqno;
373 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
375 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
377 i915_gem_object_unpin(obj);
378 drm_gem_object_unreference(&obj->base);
380 overlay->old_vid_bo = NULL;
383 static void intel_overlay_off_tail(struct intel_overlay *overlay)
385 struct drm_i915_gem_object *obj = overlay->vid_bo;
387 /* never have the overlay hw on without showing a frame */
388 BUG_ON(!overlay->vid_bo);
390 i915_gem_object_unpin(obj);
391 drm_gem_object_unreference(&obj->base);
392 overlay->vid_bo = NULL;
394 overlay->crtc->overlay = NULL;
395 overlay->crtc = NULL;
399 /* overlay needs to be disabled in OCMD reg */
400 static int intel_overlay_off(struct intel_overlay *overlay)
402 struct drm_device *dev = overlay->dev;
403 struct drm_i915_private *dev_priv = dev->dev_private;
404 u32 flip_addr = overlay->flip_addr;
405 struct drm_i915_gem_request *request;
408 BUG_ON(!overlay->active);
410 request = kzalloc(sizeof(*request), GFP_KERNEL);
414 /* According to intel docs the overlay hw may hang (when switching
415 * off) without loading the filter coeffs. It is however unclear whether
416 * this applies to the disabling of the overlay or to the switching off
417 * of the hw. Do it in both cases */
418 flip_addr |= OFC_UPDATE;
420 ret = BEGIN_LP_RING(6);
425 /* wait for overlay to go idle */
426 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
428 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
429 /* turn overlay off */
430 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
432 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
435 return intel_overlay_do_wait_request(overlay, request,
436 intel_overlay_off_tail);
439 /* recover from an interruption due to a signal
440 * We have to be careful not to repeat work forever an make forward progess. */
441 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
443 struct drm_device *dev = overlay->dev;
444 drm_i915_private_t *dev_priv = dev->dev_private;
447 if (overlay->last_flip_req == 0)
450 ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req,
455 if (overlay->flip_tail)
456 overlay->flip_tail(overlay);
458 overlay->last_flip_req = 0;
462 /* Wait for pending overlay flip and release old frame.
463 * Needs to be called before the overlay register are changed
464 * via intel_overlay_(un)map_regs
466 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
468 struct drm_device *dev = overlay->dev;
469 drm_i915_private_t *dev_priv = dev->dev_private;
472 /* Only wait if there is actually an old frame to release to
473 * guarantee forward progress.
475 if (!overlay->old_vid_bo)
478 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
479 struct drm_i915_gem_request *request;
481 /* synchronous slowpath */
482 request = kzalloc(sizeof(*request), GFP_KERNEL);
486 ret = BEGIN_LP_RING(2);
492 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
496 ret = intel_overlay_do_wait_request(overlay, request,
497 intel_overlay_release_old_vid_tail);
502 intel_overlay_release_old_vid_tail(overlay);
506 struct put_image_params {
523 static int packed_depth_bytes(u32 format)
525 switch (format & I915_OVERLAY_DEPTH_MASK) {
526 case I915_OVERLAY_YUV422:
528 case I915_OVERLAY_YUV411:
529 /* return 6; not implemented */
535 static int packed_width_bytes(u32 format, short width)
537 switch (format & I915_OVERLAY_DEPTH_MASK) {
538 case I915_OVERLAY_YUV422:
545 static int uv_hsubsampling(u32 format)
547 switch (format & I915_OVERLAY_DEPTH_MASK) {
548 case I915_OVERLAY_YUV422:
549 case I915_OVERLAY_YUV420:
551 case I915_OVERLAY_YUV411:
552 case I915_OVERLAY_YUV410:
559 static int uv_vsubsampling(u32 format)
561 switch (format & I915_OVERLAY_DEPTH_MASK) {
562 case I915_OVERLAY_YUV420:
563 case I915_OVERLAY_YUV410:
565 case I915_OVERLAY_YUV422:
566 case I915_OVERLAY_YUV411:
573 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
575 u32 mask, shift, ret;
583 ret = ((offset + width + mask) >> shift) - (offset >> shift);
590 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
591 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
592 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
593 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
594 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
595 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
596 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
597 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
598 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
599 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
600 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
601 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
602 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
603 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
604 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
605 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
606 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
607 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
610 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
611 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
612 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
613 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
614 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
615 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
616 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
617 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
618 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
619 0x3000, 0x0800, 0x3000
622 static void update_polyphase_filter(struct overlay_registers *regs)
624 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
625 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
628 static bool update_scaling_factors(struct intel_overlay *overlay,
629 struct overlay_registers *regs,
630 struct put_image_params *params)
632 /* fixed point with a 12 bit shift */
633 u32 xscale, yscale, xscale_UV, yscale_UV;
635 #define FRACT_MASK 0xfff
636 bool scale_changed = false;
637 int uv_hscale = uv_hsubsampling(params->format);
638 int uv_vscale = uv_vsubsampling(params->format);
640 if (params->dst_w > 1)
641 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
644 xscale = 1 << FP_SHIFT;
646 if (params->dst_h > 1)
647 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
650 yscale = 1 << FP_SHIFT;
652 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
653 xscale_UV = xscale/uv_hscale;
654 yscale_UV = yscale/uv_vscale;
655 /* make the Y scale to UV scale ratio an exact multiply */
656 xscale = xscale_UV * uv_hscale;
657 yscale = yscale_UV * uv_vscale;
663 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
664 scale_changed = true;
665 overlay->old_xscale = xscale;
666 overlay->old_yscale = yscale;
668 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
669 ((xscale >> FP_SHIFT) << 16) |
670 ((xscale & FRACT_MASK) << 3));
672 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
673 ((xscale_UV >> FP_SHIFT) << 16) |
674 ((xscale_UV & FRACT_MASK) << 3));
676 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
677 ((yscale_UV >> FP_SHIFT) << 0)));
680 update_polyphase_filter(regs);
682 return scale_changed;
685 static void update_colorkey(struct intel_overlay *overlay,
686 struct overlay_registers *regs)
688 u32 key = overlay->color_key;
690 switch (overlay->crtc->base.fb->bits_per_pixel) {
693 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
697 if (overlay->crtc->base.fb->depth == 15) {
698 regs->DCLRKV = RGB15_TO_COLORKEY(key);
699 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
701 regs->DCLRKV = RGB16_TO_COLORKEY(key);
702 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
709 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
714 static u32 overlay_cmd_reg(struct put_image_params *params)
716 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
718 if (params->format & I915_OVERLAY_YUV_PLANAR) {
719 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
720 case I915_OVERLAY_YUV422:
721 cmd |= OCMD_YUV_422_PLANAR;
723 case I915_OVERLAY_YUV420:
724 cmd |= OCMD_YUV_420_PLANAR;
726 case I915_OVERLAY_YUV411:
727 case I915_OVERLAY_YUV410:
728 cmd |= OCMD_YUV_410_PLANAR;
731 } else { /* YUV packed */
732 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
733 case I915_OVERLAY_YUV422:
734 cmd |= OCMD_YUV_422_PACKED;
736 case I915_OVERLAY_YUV411:
737 cmd |= OCMD_YUV_411_PACKED;
741 switch (params->format & I915_OVERLAY_SWAP_MASK) {
742 case I915_OVERLAY_NO_SWAP:
744 case I915_OVERLAY_UV_SWAP:
747 case I915_OVERLAY_Y_SWAP:
750 case I915_OVERLAY_Y_AND_UV_SWAP:
751 cmd |= OCMD_Y_AND_UV_SWAP;
759 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
760 struct drm_i915_gem_object *new_bo,
761 struct put_image_params *params)
764 struct overlay_registers *regs;
765 bool scale_changed = false;
766 struct drm_device *dev = overlay->dev;
768 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
769 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
772 ret = intel_overlay_release_old_vid(overlay);
776 ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
780 ret = i915_gem_object_put_fence(new_bo);
784 if (!overlay->active) {
785 regs = intel_overlay_map_regs(overlay);
790 regs->OCONFIG = OCONF_CC_OUT_8BIT;
791 if (IS_GEN4(overlay->dev))
792 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
793 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
794 OCONF_PIPE_A : OCONF_PIPE_B;
795 intel_overlay_unmap_regs(overlay, regs);
797 ret = intel_overlay_on(overlay);
802 regs = intel_overlay_map_regs(overlay);
808 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
809 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
811 if (params->format & I915_OVERLAY_YUV_PACKED)
812 tmp_width = packed_width_bytes(params->format, params->src_w);
814 tmp_width = params->src_w;
816 regs->SWIDTH = params->src_w;
817 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
818 params->offset_Y, tmp_width);
819 regs->SHEIGHT = params->src_h;
820 regs->OBUF_0Y = new_bo->gtt_offset + params->offset_Y;
821 regs->OSTRIDE = params->stride_Y;
823 if (params->format & I915_OVERLAY_YUV_PLANAR) {
824 int uv_hscale = uv_hsubsampling(params->format);
825 int uv_vscale = uv_vsubsampling(params->format);
827 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
828 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
829 params->src_w/uv_hscale);
830 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
831 params->src_w/uv_hscale);
832 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
833 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
834 regs->OBUF_0U = new_bo->gtt_offset + params->offset_U;
835 regs->OBUF_0V = new_bo->gtt_offset + params->offset_V;
836 regs->OSTRIDE |= params->stride_UV << 16;
839 scale_changed = update_scaling_factors(overlay, regs, params);
841 update_colorkey(overlay, regs);
843 regs->OCMD = overlay_cmd_reg(params);
845 intel_overlay_unmap_regs(overlay, regs);
847 ret = intel_overlay_continue(overlay, scale_changed);
851 overlay->old_vid_bo = overlay->vid_bo;
852 overlay->vid_bo = new_bo;
857 i915_gem_object_unpin(new_bo);
861 int intel_overlay_switch_off(struct intel_overlay *overlay)
863 struct overlay_registers *regs;
864 struct drm_device *dev = overlay->dev;
867 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
868 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
870 ret = intel_overlay_recover_from_interrupt(overlay);
874 if (!overlay->active)
877 ret = intel_overlay_release_old_vid(overlay);
881 regs = intel_overlay_map_regs(overlay);
883 intel_overlay_unmap_regs(overlay, regs);
885 ret = intel_overlay_off(overlay);
889 intel_overlay_off_tail(overlay);
893 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
894 struct intel_crtc *crtc)
896 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
901 /* can't use the overlay with double wide pipe */
902 if (INTEL_INFO(overlay->dev)->gen < 4 &&
903 (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
909 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
911 struct drm_device *dev = overlay->dev;
912 drm_i915_private_t *dev_priv = dev->dev_private;
913 u32 pfit_control = I915_READ(PFIT_CONTROL);
916 /* XXX: This is not the same logic as in the xorg driver, but more in
917 * line with the intel documentation for the i965
919 if (INTEL_INFO(dev)->gen >= 4) {
920 /* on i965 use the PGM reg to read out the autoscaler values */
921 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
923 if (pfit_control & VERT_AUTO_SCALE)
924 ratio = I915_READ(PFIT_AUTO_RATIOS);
926 ratio = I915_READ(PFIT_PGM_RATIOS);
927 ratio >>= PFIT_VERT_SCALE_SHIFT;
930 overlay->pfit_vscale_ratio = ratio;
933 static int check_overlay_dst(struct intel_overlay *overlay,
934 struct drm_intel_overlay_put_image *rec)
936 struct drm_display_mode *mode = &overlay->crtc->base.mode;
938 if (rec->dst_x < mode->hdisplay &&
939 rec->dst_x + rec->dst_width <= mode->hdisplay &&
940 rec->dst_y < mode->vdisplay &&
941 rec->dst_y + rec->dst_height <= mode->vdisplay)
947 static int check_overlay_scaling(struct put_image_params *rec)
951 /* downscaling limit is 8.0 */
952 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
955 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
962 static int check_overlay_src(struct drm_device *dev,
963 struct drm_intel_overlay_put_image *rec,
964 struct drm_i915_gem_object *new_bo)
966 int uv_hscale = uv_hsubsampling(rec->flags);
967 int uv_vscale = uv_vsubsampling(rec->flags);
972 /* check src dimensions */
973 if (IS_845G(dev) || IS_I830(dev)) {
974 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
975 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
978 if (rec->src_height > IMAGE_MAX_HEIGHT ||
979 rec->src_width > IMAGE_MAX_WIDTH)
983 /* better safe than sorry, use 4 as the maximal subsampling ratio */
984 if (rec->src_height < N_VERT_Y_TAPS*4 ||
985 rec->src_width < N_HORIZ_Y_TAPS*4)
988 /* check alignment constraints */
989 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
990 case I915_OVERLAY_RGB:
991 /* not implemented */
994 case I915_OVERLAY_YUV_PACKED:
998 depth = packed_depth_bytes(rec->flags);
1002 /* ignore UV planes */
1006 /* check pixel alignment */
1007 if (rec->offset_Y % depth)
1011 case I915_OVERLAY_YUV_PLANAR:
1012 if (uv_vscale < 0 || uv_hscale < 0)
1014 /* no offset restrictions for planar formats */
1021 if (rec->src_width % uv_hscale)
1024 /* stride checking */
1025 if (IS_I830(dev) || IS_845G(dev))
1030 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1032 if (IS_GEN4(dev) && rec->stride_Y < 512)
1035 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1037 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1040 /* check buffer dimensions */
1041 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1042 case I915_OVERLAY_RGB:
1043 case I915_OVERLAY_YUV_PACKED:
1044 /* always 4 Y values per depth pixels */
1045 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1048 tmp = rec->stride_Y*rec->src_height;
1049 if (rec->offset_Y + tmp > new_bo->base.size)
1053 case I915_OVERLAY_YUV_PLANAR:
1054 if (rec->src_width > rec->stride_Y)
1056 if (rec->src_width/uv_hscale > rec->stride_UV)
1059 tmp = rec->stride_Y * rec->src_height;
1060 if (rec->offset_Y + tmp > new_bo->base.size)
1063 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1064 if (rec->offset_U + tmp > new_bo->base.size ||
1065 rec->offset_V + tmp > new_bo->base.size)
1074 * Return the pipe currently connected to the panel fitter,
1075 * or -1 if the panel fitter is not present or not in use
1077 static int intel_panel_fitter_pipe(struct drm_device *dev)
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1082 /* i830 doesn't have a panel fitter */
1086 pfit_control = I915_READ(PFIT_CONTROL);
1088 /* See if the panel fitter is in use */
1089 if ((pfit_control & PFIT_ENABLE) == 0)
1092 /* 965 can place panel fitter on either pipe */
1094 return (pfit_control >> 29) & 0x3;
1096 /* older chips can only use pipe 1 */
1100 int intel_overlay_put_image(struct drm_device *dev, void *data,
1101 struct drm_file *file_priv)
1103 struct drm_intel_overlay_put_image *put_image_rec = data;
1104 drm_i915_private_t *dev_priv = dev->dev_private;
1105 struct intel_overlay *overlay;
1106 struct drm_mode_object *drmmode_obj;
1107 struct intel_crtc *crtc;
1108 struct drm_i915_gem_object *new_bo;
1109 struct put_image_params *params;
1113 DRM_ERROR("called with no initialization\n");
1117 overlay = dev_priv->overlay;
1119 DRM_DEBUG("userspace bug: no overlay\n");
1123 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1124 mutex_lock(&dev->mode_config.mutex);
1125 mutex_lock(&dev->struct_mutex);
1127 ret = intel_overlay_switch_off(overlay);
1129 mutex_unlock(&dev->struct_mutex);
1130 mutex_unlock(&dev->mode_config.mutex);
1135 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1139 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1140 DRM_MODE_OBJECT_CRTC);
1145 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1147 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1148 put_image_rec->bo_handle));
1149 if (&new_bo->base == NULL) {
1154 mutex_lock(&dev->mode_config.mutex);
1155 mutex_lock(&dev->struct_mutex);
1157 if (new_bo->tiling_mode) {
1158 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1163 ret = intel_overlay_recover_from_interrupt(overlay);
1167 if (overlay->crtc != crtc) {
1168 struct drm_display_mode *mode = &crtc->base.mode;
1169 ret = intel_overlay_switch_off(overlay);
1173 ret = check_overlay_possible_on_crtc(overlay, crtc);
1177 overlay->crtc = crtc;
1178 crtc->overlay = overlay;
1180 /* line too wide, i.e. one-line-mode */
1181 if (mode->hdisplay > 1024 &&
1182 intel_panel_fitter_pipe(dev) == crtc->pipe) {
1183 overlay->pfit_active = 1;
1184 update_pfit_vscale_ratio(overlay);
1186 overlay->pfit_active = 0;
1189 ret = check_overlay_dst(overlay, put_image_rec);
1193 if (overlay->pfit_active) {
1194 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1195 overlay->pfit_vscale_ratio);
1196 /* shifting right rounds downwards, so add 1 */
1197 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1198 overlay->pfit_vscale_ratio) + 1;
1200 params->dst_y = put_image_rec->dst_y;
1201 params->dst_h = put_image_rec->dst_height;
1203 params->dst_x = put_image_rec->dst_x;
1204 params->dst_w = put_image_rec->dst_width;
1206 params->src_w = put_image_rec->src_width;
1207 params->src_h = put_image_rec->src_height;
1208 params->src_scan_w = put_image_rec->src_scan_width;
1209 params->src_scan_h = put_image_rec->src_scan_height;
1210 if (params->src_scan_h > params->src_h ||
1211 params->src_scan_w > params->src_w) {
1216 ret = check_overlay_src(dev, put_image_rec, new_bo);
1219 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1220 params->stride_Y = put_image_rec->stride_Y;
1221 params->stride_UV = put_image_rec->stride_UV;
1222 params->offset_Y = put_image_rec->offset_Y;
1223 params->offset_U = put_image_rec->offset_U;
1224 params->offset_V = put_image_rec->offset_V;
1226 /* Check scaling after src size to prevent a divide-by-zero. */
1227 ret = check_overlay_scaling(params);
1231 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1235 mutex_unlock(&dev->struct_mutex);
1236 mutex_unlock(&dev->mode_config.mutex);
1243 mutex_unlock(&dev->struct_mutex);
1244 mutex_unlock(&dev->mode_config.mutex);
1245 drm_gem_object_unreference_unlocked(&new_bo->base);
1252 static void update_reg_attrs(struct intel_overlay *overlay,
1253 struct overlay_registers *regs)
1255 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1256 regs->OCLRC1 = overlay->saturation;
1259 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1263 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1266 for (i = 0; i < 3; i++) {
1267 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1274 static bool check_gamma5_errata(u32 gamma5)
1278 for (i = 0; i < 3; i++) {
1279 if (((gamma5 >> i*8) & 0xff) == 0x80)
1286 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1288 if (!check_gamma_bounds(0, attrs->gamma0) ||
1289 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1290 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1291 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1292 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1293 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1294 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1297 if (!check_gamma5_errata(attrs->gamma5))
1303 int intel_overlay_attrs(struct drm_device *dev, void *data,
1304 struct drm_file *file_priv)
1306 struct drm_intel_overlay_attrs *attrs = data;
1307 drm_i915_private_t *dev_priv = dev->dev_private;
1308 struct intel_overlay *overlay;
1309 struct overlay_registers *regs;
1313 DRM_ERROR("called with no initialization\n");
1317 overlay = dev_priv->overlay;
1319 DRM_DEBUG("userspace bug: no overlay\n");
1323 mutex_lock(&dev->mode_config.mutex);
1324 mutex_lock(&dev->struct_mutex);
1327 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1328 attrs->color_key = overlay->color_key;
1329 attrs->brightness = overlay->brightness;
1330 attrs->contrast = overlay->contrast;
1331 attrs->saturation = overlay->saturation;
1333 if (!IS_GEN2(dev)) {
1334 attrs->gamma0 = I915_READ(OGAMC0);
1335 attrs->gamma1 = I915_READ(OGAMC1);
1336 attrs->gamma2 = I915_READ(OGAMC2);
1337 attrs->gamma3 = I915_READ(OGAMC3);
1338 attrs->gamma4 = I915_READ(OGAMC4);
1339 attrs->gamma5 = I915_READ(OGAMC5);
1342 if (attrs->brightness < -128 || attrs->brightness > 127)
1344 if (attrs->contrast > 255)
1346 if (attrs->saturation > 1023)
1349 overlay->color_key = attrs->color_key;
1350 overlay->brightness = attrs->brightness;
1351 overlay->contrast = attrs->contrast;
1352 overlay->saturation = attrs->saturation;
1354 regs = intel_overlay_map_regs(overlay);
1360 update_reg_attrs(overlay, regs);
1362 intel_overlay_unmap_regs(overlay, regs);
1364 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1368 if (overlay->active) {
1373 ret = check_gamma(attrs);
1377 I915_WRITE(OGAMC0, attrs->gamma0);
1378 I915_WRITE(OGAMC1, attrs->gamma1);
1379 I915_WRITE(OGAMC2, attrs->gamma2);
1380 I915_WRITE(OGAMC3, attrs->gamma3);
1381 I915_WRITE(OGAMC4, attrs->gamma4);
1382 I915_WRITE(OGAMC5, attrs->gamma5);
1388 mutex_unlock(&dev->struct_mutex);
1389 mutex_unlock(&dev->mode_config.mutex);
1394 void intel_setup_overlay(struct drm_device *dev)
1396 drm_i915_private_t *dev_priv = dev->dev_private;
1397 struct intel_overlay *overlay;
1398 struct drm_i915_gem_object *reg_bo;
1399 struct overlay_registers *regs;
1402 if (!HAS_OVERLAY(dev))
1405 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1409 mutex_lock(&dev->struct_mutex);
1410 if (WARN_ON(dev_priv->overlay))
1415 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1418 overlay->reg_bo = reg_bo;
1420 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1421 ret = i915_gem_attach_phys_object(dev, reg_bo,
1422 I915_GEM_PHYS_OVERLAY_REGS,
1425 DRM_ERROR("failed to attach phys overlay regs\n");
1428 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
1430 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true);
1432 DRM_ERROR("failed to pin overlay register bo\n");
1435 overlay->flip_addr = reg_bo->gtt_offset;
1437 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1439 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1444 /* init all values */
1445 overlay->color_key = 0x0101fe;
1446 overlay->brightness = -19;
1447 overlay->contrast = 75;
1448 overlay->saturation = 146;
1450 regs = intel_overlay_map_regs(overlay);
1454 memset(regs, 0, sizeof(struct overlay_registers));
1455 update_polyphase_filter(regs);
1456 update_reg_attrs(overlay, regs);
1458 intel_overlay_unmap_regs(overlay, regs);
1460 dev_priv->overlay = overlay;
1461 mutex_unlock(&dev->struct_mutex);
1462 DRM_INFO("initialized overlay support\n");
1466 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1467 i915_gem_object_unpin(reg_bo);
1469 drm_gem_object_unreference(®_bo->base);
1471 mutex_unlock(&dev->struct_mutex);
1476 void intel_cleanup_overlay(struct drm_device *dev)
1478 drm_i915_private_t *dev_priv = dev->dev_private;
1480 if (!dev_priv->overlay)
1483 /* The bo's should be free'd by the generic code already.
1484 * Furthermore modesetting teardown happens beforehand so the
1485 * hardware should be off already */
1486 BUG_ON(dev_priv->overlay->active);
1488 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1489 kfree(dev_priv->overlay);
1492 #ifdef CONFIG_DEBUG_FS
1493 #include <linux/seq_file.h>
1495 struct intel_overlay_error_state {
1496 struct overlay_registers regs;
1502 static struct overlay_registers *
1503 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1505 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
1506 struct overlay_registers *regs;
1508 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1509 regs = overlay->reg_bo->phys_obj->handle->vaddr;
1511 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1512 overlay->reg_bo->gtt_offset);
1517 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1518 struct overlay_registers *regs)
1520 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1521 io_mapping_unmap_atomic(regs);
1525 struct intel_overlay_error_state *
1526 intel_overlay_capture_error_state(struct drm_device *dev)
1528 drm_i915_private_t *dev_priv = dev->dev_private;
1529 struct intel_overlay *overlay = dev_priv->overlay;
1530 struct intel_overlay_error_state *error;
1531 struct overlay_registers __iomem *regs;
1533 if (!overlay || !overlay->active)
1536 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1540 error->dovsta = I915_READ(DOVSTA);
1541 error->isr = I915_READ(ISR);
1542 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1543 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1545 error->base = (long) overlay->reg_bo->gtt_offset;
1547 regs = intel_overlay_map_regs_atomic(overlay);
1551 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1552 intel_overlay_unmap_regs_atomic(overlay, regs);
1562 intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1564 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1565 error->dovsta, error->isr);
1566 seq_printf(m, " Register file at 0x%08lx:\n",
1569 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)