2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
31 #include "intel_drv.h"
33 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
36 intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
37 struct drm_display_mode *adjusted_mode)
39 adjusted_mode->hdisplay = fixed_mode->hdisplay;
40 adjusted_mode->hsync_start = fixed_mode->hsync_start;
41 adjusted_mode->hsync_end = fixed_mode->hsync_end;
42 adjusted_mode->htotal = fixed_mode->htotal;
44 adjusted_mode->vdisplay = fixed_mode->vdisplay;
45 adjusted_mode->vsync_start = fixed_mode->vsync_start;
46 adjusted_mode->vsync_end = fixed_mode->vsync_end;
47 adjusted_mode->vtotal = fixed_mode->vtotal;
49 adjusted_mode->clock = fixed_mode->clock;
51 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
54 /* adjusted_mode has been preset to be the panel's fixed mode */
56 intel_pch_panel_fitting(struct drm_device *dev,
58 struct drm_display_mode *mode,
59 struct drm_display_mode *adjusted_mode)
61 struct drm_i915_private *dev_priv = dev->dev_private;
62 int x, y, width, height;
64 x = y = width = height = 0;
66 /* Native modes don't need fitting */
67 if (adjusted_mode->hdisplay == mode->hdisplay &&
68 adjusted_mode->vdisplay == mode->vdisplay)
71 switch (fitting_mode) {
72 case DRM_MODE_SCALE_CENTER:
73 width = mode->hdisplay;
74 height = mode->vdisplay;
75 x = (adjusted_mode->hdisplay - width + 1)/2;
76 y = (adjusted_mode->vdisplay - height + 1)/2;
79 case DRM_MODE_SCALE_ASPECT:
80 /* Scale but preserve the aspect ratio */
82 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
83 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
84 if (scaled_width > scaled_height) { /* pillar */
85 width = scaled_height / mode->vdisplay;
86 x = (adjusted_mode->hdisplay - width + 1) / 2;
88 height = adjusted_mode->vdisplay;
89 } else if (scaled_width < scaled_height) { /* letter */
90 height = scaled_width / mode->hdisplay;
91 y = (adjusted_mode->vdisplay - height + 1) / 2;
93 width = adjusted_mode->hdisplay;
96 width = adjusted_mode->hdisplay;
97 height = adjusted_mode->vdisplay;
103 case DRM_MODE_SCALE_FULLSCREEN:
105 width = adjusted_mode->hdisplay;
106 height = adjusted_mode->vdisplay;
111 dev_priv->pch_pf_pos = (x << 16) | y;
112 dev_priv->pch_pf_size = (width << 16) | height;
115 static int is_backlight_combination_mode(struct drm_device *dev)
117 struct drm_i915_private *dev_priv = dev->dev_private;
119 if (INTEL_INFO(dev)->gen >= 4)
120 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
123 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
128 static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
132 /* Restore the CTL value if it lost, e.g. GPU reset */
134 if (HAS_PCH_SPLIT(dev_priv->dev)) {
135 val = I915_READ(BLC_PWM_PCH_CTL2);
136 if (dev_priv->saveBLC_PWM_CTL2 == 0) {
137 dev_priv->saveBLC_PWM_CTL2 = val;
138 } else if (val == 0) {
139 I915_WRITE(BLC_PWM_PCH_CTL2,
140 dev_priv->saveBLC_PWM_CTL);
141 val = dev_priv->saveBLC_PWM_CTL;
144 val = I915_READ(BLC_PWM_CTL);
145 if (dev_priv->saveBLC_PWM_CTL == 0) {
146 dev_priv->saveBLC_PWM_CTL = val;
147 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
148 } else if (val == 0) {
149 I915_WRITE(BLC_PWM_CTL,
150 dev_priv->saveBLC_PWM_CTL);
151 I915_WRITE(BLC_PWM_CTL2,
152 dev_priv->saveBLC_PWM_CTL2);
153 val = dev_priv->saveBLC_PWM_CTL;
160 u32 intel_panel_get_max_backlight(struct drm_device *dev)
162 struct drm_i915_private *dev_priv = dev->dev_private;
165 max = i915_read_blc_pwm_ctl(dev_priv);
167 /* XXX add code here to query mode clock or hardware clock
168 * and program max PWM appropriately.
170 printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
174 if (HAS_PCH_SPLIT(dev)) {
177 if (IS_PINEVIEW(dev)) {
181 if (INTEL_INFO(dev)->gen < 4)
185 if (is_backlight_combination_mode(dev))
189 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
193 u32 intel_panel_get_backlight(struct drm_device *dev)
195 struct drm_i915_private *dev_priv = dev->dev_private;
198 if (HAS_PCH_SPLIT(dev)) {
199 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
201 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
202 if (IS_PINEVIEW(dev))
205 if (is_backlight_combination_mode(dev)){
209 pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
215 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
219 static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
221 struct drm_i915_private *dev_priv = dev->dev_private;
222 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
223 I915_WRITE(BLC_PWM_CPU_CTL, val | level);
226 void intel_panel_set_backlight(struct drm_device *dev, u32 level)
228 struct drm_i915_private *dev_priv = dev->dev_private;
231 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
233 if (HAS_PCH_SPLIT(dev))
234 return intel_pch_panel_set_backlight(dev, level);
236 if (is_backlight_combination_mode(dev)){
237 u32 max = intel_panel_get_max_backlight(dev);
240 lpbc = level * 0xfe / max + 1;
242 pci_write_config_byte(dev->pdev, PCI_LBPC, lpbc);
245 tmp = I915_READ(BLC_PWM_CTL);
246 if (IS_PINEVIEW(dev)) {
247 tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
250 tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
251 I915_WRITE(BLC_PWM_CTL, tmp | level);