drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         I915_WRITE(GEN8_CONFIG0,
  66                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  67
  68         /* WaEnableChickenDCPR:skl,bxt,kbl */
  69         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  70                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  71
  72         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  73         /* WaFbcWakeMemOn:skl,bxt,kbl */
  74         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  75                    DISP_FBC_WM_DIS |
  76                    DISP_FBC_MEMORY_WAKE);
  77
  78         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  79         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  80                    ILK_DPFC_DISABLE_DUMMY0);
  81 }
  82
  83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
  84 {
  85         gen9_init_clock_gating(dev_priv);
  86
  87         /* WaDisableSDEUnitClockGating:bxt */
  88         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  89                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  90
  91         /*
  92          * FIXME:
  93          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  94          */
  95         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  96                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  97
  98         /*
  99          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 100          * to stay fully on.
 101          */
 102         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 103                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 104                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 105 }
 106
 107 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 108 {
 109         u32 tmp;
 110
 111         tmp = I915_READ(CLKCFG);
 112
 113         switch (tmp & CLKCFG_FSB_MASK) {
 114         case CLKCFG_FSB_533:
 115                 dev_priv->fsb_freq = 533; /* 133*4 */
 116                 break;
 117         case CLKCFG_FSB_800:
 118                 dev_priv->fsb_freq = 800; /* 200*4 */
 119                 break;
 120         case CLKCFG_FSB_667:
 121                 dev_priv->fsb_freq =  667; /* 167*4 */
 122                 break;
 123         case CLKCFG_FSB_400:
 124                 dev_priv->fsb_freq = 400; /* 100*4 */
 125                 break;
 126         }
 127
 128         switch (tmp & CLKCFG_MEM_MASK) {
 129         case CLKCFG_MEM_533:
 130                 dev_priv->mem_freq = 533;
 131                 break;
 132         case CLKCFG_MEM_667:
 133                 dev_priv->mem_freq = 667;
 134                 break;
 135         case CLKCFG_MEM_800:
 136                 dev_priv->mem_freq = 800;
 137                 break;
 138         }
 139
 140         /* detect pineview DDR3 setting */
 141         tmp = I915_READ(CSHRDDR3CTL);
 142         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 143 }
 144
 145 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 146 {
 147         u16 ddrpll, csipll;
 148
 149         ddrpll = I915_READ16(DDRMPLL1);
 150         csipll = I915_READ16(CSIPLL0);
 151
 152         switch (ddrpll & 0xff) {
 153         case 0xc:
 154                 dev_priv->mem_freq = 800;
 155                 break;
 156         case 0x10:
 157                 dev_priv->mem_freq = 1066;
 158                 break;
 159         case 0x14:
 160                 dev_priv->mem_freq = 1333;
 161                 break;
 162         case 0x18:
 163                 dev_priv->mem_freq = 1600;
 164                 break;
 165         default:
 166                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 167                                  ddrpll & 0xff);
 168                 dev_priv->mem_freq = 0;
 169                 break;
 170         }
 171
 172         dev_priv->ips.r_t = dev_priv->mem_freq;
 173
 174         switch (csipll & 0x3ff) {
 175         case 0x00c:
 176                 dev_priv->fsb_freq = 3200;
 177                 break;
 178         case 0x00e:
 179                 dev_priv->fsb_freq = 3733;
 180                 break;
 181         case 0x010:
 182                 dev_priv->fsb_freq = 4266;
 183                 break;
 184         case 0x012:
 185                 dev_priv->fsb_freq = 4800;
 186                 break;
 187         case 0x014:
 188                 dev_priv->fsb_freq = 5333;
 189                 break;
 190         case 0x016:
 191                 dev_priv->fsb_freq = 5866;
 192                 break;
 193         case 0x018:
 194                 dev_priv->fsb_freq = 6400;
 195                 break;
 196         default:
 197                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 198                                  csipll & 0x3ff);
 199                 dev_priv->fsb_freq = 0;
 200                 break;
 201         }
 202
 203         if (dev_priv->fsb_freq == 3200) {
 204                 dev_priv->ips.c_m = 0;
 205         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 206                 dev_priv->ips.c_m = 1;
 207         } else {
 208                 dev_priv->ips.c_m = 2;
 209         }
 210 }
 211
 212 static const struct cxsr_latency cxsr_latency_table[] = {
 213         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 214         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 215         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 216         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 217         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 218
 219         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 220         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 221         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 222         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 223         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 224
 225         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 226         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 227         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 228         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 229         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 230
 231         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 232         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 233         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 234         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 235         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 236
 237         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 238         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 239         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 240         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 241         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 242
 243         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 244         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 245         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 246         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 247         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 248 };
 249
 250 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 251                                                          bool is_ddr3,
 252                                                          int fsb,
 253                                                          int mem)
 254 {
 255         const struct cxsr_latency *latency;
 256         int i;
 257
 258         if (fsb == 0 || mem == 0)
 259                 return NULL;
 260
 261         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 262                 latency = &cxsr_latency_table[i];
 263                 if (is_desktop == latency->is_desktop &&
 264                     is_ddr3 == latency->is_ddr3 &&
 265                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 266                         return latency;
 267         }
 268
 269         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 270
 271         return NULL;
 272 }
 273
 274 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 275 {
 276         u32 val;
 277
 278         mutex_lock(&dev_priv->rps.hw_lock);
 279
 280         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 281         if (enable)
 282                 val &= ~FORCE_DDR_HIGH_FREQ;
 283         else
 284                 val |= FORCE_DDR_HIGH_FREQ;
 285         val &= ~FORCE_DDR_LOW_FREQ;
 286         val |= FORCE_DDR_FREQ_REQ_ACK;
 287         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 288
 289         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 290                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 291                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 292
 293         mutex_unlock(&dev_priv->rps.hw_lock);
 294 }
 295
 296 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 297 {
 298         u32 val;
 299
 300         mutex_lock(&dev_priv->rps.hw_lock);
 301
 302         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 303         if (enable)
 304                 val |= DSP_MAXFIFO_PM5_ENABLE;
 305         else
 306                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 307         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 308
 309         mutex_unlock(&dev_priv->rps.hw_lock);
 310 }
 311
 312 #define FW_WM(value, plane) \
 313         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 314
 315 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 316 {
 317         bool was_enabled;
 318         u32 val;
 319
 320         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 321                 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 322                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 323                 POSTING_READ(FW_BLC_SELF_VLV);
 324         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 325                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 326                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 327                 POSTING_READ(FW_BLC_SELF);
 328         } else if (IS_PINEVIEW(dev_priv)) {
 329                 val = I915_READ(DSPFW3);
 330                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 331                 if (enable)
 332                         val |= PINEVIEW_SELF_REFRESH_EN;
 333                 else
 334                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 335                 I915_WRITE(DSPFW3, val);
 336                 POSTING_READ(DSPFW3);
 337         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 338                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 339                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 340                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 341                 I915_WRITE(FW_BLC_SELF, val);
 342                 POSTING_READ(FW_BLC_SELF);
 343         } else if (IS_I915GM(dev_priv)) {
 344                 /*
 345                  * FIXME can't find a bit like this for 915G, and
 346                  * and yet it does have the related watermark in
 347                  * FW_BLC_SELF. What's going on?
 348                  */
 349                 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 350                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 351                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 352                 I915_WRITE(INSTPM, val);
 353                 POSTING_READ(INSTPM);
 354         } else {
 355                 return false;
 356         }
 357
 358         DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
 359                       enableddisabled(enable),
 360                       enableddisabled(was_enabled));
 361
 362         return was_enabled;
 363 }
 364
 365 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 366 {
 367         bool ret;
 368
 369         mutex_lock(&dev_priv->wm.wm_mutex);
 370         ret = _intel_set_memory_cxsr(dev_priv, enable);
 371         dev_priv->wm.vlv.cxsr = enable;
 372         mutex_unlock(&dev_priv->wm.wm_mutex);
 373
 374         return ret;
 375 }
 376
 377 /*
 378  * Latency for FIFO fetches is dependent on several factors:
 379  *   - memory configuration (speed, channels)
 380  *   - chipset
 381  *   - current MCH state
 382  * It can be fairly high in some situations, so here we assume a fairly
 383  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 384  * set this value too high, the FIFO will fetch frequently to stay full)
 385  * and power consumption (set it too low to save power and we might see
 386  * FIFO underruns and display "flicker").
 387  *
 388  * A value of 5us seems to be a good balance; safe for very low end
 389  * platforms but not overly aggressive on lower latency configs.
 390  */
 391 static const int pessimal_latency_ns = 5000;
 392
 393 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 394         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 395
 396 static int vlv_get_fifo_size(struct intel_plane *plane)
 397 {
 398         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 399         int sprite0_start, sprite1_start, size;
 400
 401         if (plane->id == PLANE_CURSOR)
 402                 return 63;
 403
 404         switch (plane->pipe) {
 405                 uint32_t dsparb, dsparb2, dsparb3;
 406         case PIPE_A:
 407                 dsparb = I915_READ(DSPARB);
 408                 dsparb2 = I915_READ(DSPARB2);
 409                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 410                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 411                 break;
 412         case PIPE_B:
 413                 dsparb = I915_READ(DSPARB);
 414                 dsparb2 = I915_READ(DSPARB2);
 415                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 416                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 417                 break;
 418         case PIPE_C:
 419                 dsparb2 = I915_READ(DSPARB2);
 420                 dsparb3 = I915_READ(DSPARB3);
 421                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 422                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 423                 break;
 424         default:
 425                 return 0;
 426         }
 427
 428         switch (plane->id) {
 429         case PLANE_PRIMARY:
 430                 size = sprite0_start;
 431                 break;
 432         case PLANE_SPRITE0:
 433                 size = sprite1_start - sprite0_start;
 434                 break;
 435         case PLANE_SPRITE1:
 436                 size = 512 - 1 - sprite1_start;
 437                 break;
 438         default:
 439                 return 0;
 440         }
 441
 442         DRM_DEBUG_KMS("%s FIFO size: %d\n", plane->base.name, size);
 443
 444         return size;
 445 }
 446
 447 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 448 {
 449         uint32_t dsparb = I915_READ(DSPARB);
 450         int size;
 451
 452         size = dsparb & 0x7f;
 453         if (plane)
 454                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 455
 456         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 457                       plane ? "B" : "A", size);
 458
 459         return size;
 460 }
 461
 462 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 463 {
 464         uint32_t dsparb = I915_READ(DSPARB);
 465         int size;
 466
 467         size = dsparb & 0x1ff;
 468         if (plane)
 469                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 470         size >>= 1; /* Convert to cachelines */
 471
 472         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 473                       plane ? "B" : "A", size);
 474
 475         return size;
 476 }
 477
 478 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 479 {
 480         uint32_t dsparb = I915_READ(DSPARB);
 481         int size;
 482
 483         size = dsparb & 0x7f;
 484         size >>= 2; /* Convert to cachelines */
 485
 486         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 487                       plane ? "B" : "A",
 488                       size);
 489
 490         return size;
 491 }
 492
 493 /* Pineview has different values for various configs */
 494 static const struct intel_watermark_params pineview_display_wm = {
 495         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 496         .max_wm = PINEVIEW_MAX_WM,
 497         .default_wm = PINEVIEW_DFT_WM,
 498         .guard_size = PINEVIEW_GUARD_WM,
 499         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 500 };
 501 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 502         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 503         .max_wm = PINEVIEW_MAX_WM,
 504         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 505         .guard_size = PINEVIEW_GUARD_WM,
 506         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 507 };
 508 static const struct intel_watermark_params pineview_cursor_wm = {
 509         .fifo_size = PINEVIEW_CURSOR_FIFO,
 510         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 511         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 512         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 513         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 514 };
 515 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 516         .fifo_size = PINEVIEW_CURSOR_FIFO,
 517         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 518         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 519         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 520         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 521 };
 522 static const struct intel_watermark_params g4x_wm_info = {
 523         .fifo_size = G4X_FIFO_SIZE,
 524         .max_wm = G4X_MAX_WM,
 525         .default_wm = G4X_MAX_WM,
 526         .guard_size = 2,
 527         .cacheline_size = G4X_FIFO_LINE_SIZE,
 528 };
 529 static const struct intel_watermark_params g4x_cursor_wm_info = {
 530         .fifo_size = I965_CURSOR_FIFO,
 531         .max_wm = I965_CURSOR_MAX_WM,
 532         .default_wm = I965_CURSOR_DFT_WM,
 533         .guard_size = 2,
 534         .cacheline_size = G4X_FIFO_LINE_SIZE,
 535 };
 536 static const struct intel_watermark_params i965_cursor_wm_info = {
 537         .fifo_size = I965_CURSOR_FIFO,
 538         .max_wm = I965_CURSOR_MAX_WM,
 539         .default_wm = I965_CURSOR_DFT_WM,
 540         .guard_size = 2,
 541         .cacheline_size = I915_FIFO_LINE_SIZE,
 542 };
 543 static const struct intel_watermark_params i945_wm_info = {
 544         .fifo_size = I945_FIFO_SIZE,
 545         .max_wm = I915_MAX_WM,
 546         .default_wm = 1,
 547         .guard_size = 2,
 548         .cacheline_size = I915_FIFO_LINE_SIZE,
 549 };
 550 static const struct intel_watermark_params i915_wm_info = {
 551         .fifo_size = I915_FIFO_SIZE,
 552         .max_wm = I915_MAX_WM,
 553         .default_wm = 1,
 554         .guard_size = 2,
 555         .cacheline_size = I915_FIFO_LINE_SIZE,
 556 };
 557 static const struct intel_watermark_params i830_a_wm_info = {
 558         .fifo_size = I855GM_FIFO_SIZE,
 559         .max_wm = I915_MAX_WM,
 560         .default_wm = 1,
 561         .guard_size = 2,
 562         .cacheline_size = I830_FIFO_LINE_SIZE,
 563 };
 564 static const struct intel_watermark_params i830_bc_wm_info = {
 565         .fifo_size = I855GM_FIFO_SIZE,
 566         .max_wm = I915_MAX_WM/2,
 567         .default_wm = 1,
 568         .guard_size = 2,
 569         .cacheline_size = I830_FIFO_LINE_SIZE,
 570 };
 571 static const struct intel_watermark_params i845_wm_info = {
 572         .fifo_size = I830_FIFO_SIZE,
 573         .max_wm = I915_MAX_WM,
 574         .default_wm = 1,
 575         .guard_size = 2,
 576         .cacheline_size = I830_FIFO_LINE_SIZE,
 577 };
 578
 579 /**
 580  * intel_calculate_wm - calculate watermark level
 581  * @clock_in_khz: pixel clock
 582  * @wm: chip FIFO params
 583  * @cpp: bytes per pixel
 584  * @latency_ns: memory latency for the platform
 585  *
 586  * Calculate the watermark level (the level at which the display plane will
 587  * start fetching from memory again).  Each chip has a different display
 588  * FIFO size and allocation, so the caller needs to figure that out and pass
 589  * in the correct intel_watermark_params structure.
 590  *
 591  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 592  * on the pixel size.  When it reaches the watermark level, it'll start
 593  * fetching FIFO line sized based chunks from memory until the FIFO fills
 594  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 595  * will occur, and a display engine hang could result.
 596  */
 597 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 598                                         const struct intel_watermark_params *wm,
 599                                         int fifo_size, int cpp,
 600                                         unsigned long latency_ns)
 601 {
 602         long entries_required, wm_size;
 603
 604         /*
 605          * Note: we need to make sure we don't overflow for various clock &
 606          * latency values.
 607          * clocks go from a few thousand to several hundred thousand.
 608          * latency is usually a few thousand
 609          */
 610         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 611                 1000;
 612         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 613
 614         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 615
 616         wm_size = fifo_size - (entries_required + wm->guard_size);
 617
 618         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 619
 620         /* Don't promote wm_size to unsigned... */
 621         if (wm_size > (long)wm->max_wm)
 622                 wm_size = wm->max_wm;
 623         if (wm_size <= 0)
 624                 wm_size = wm->default_wm;
 625
 626         /*
 627          * Bspec seems to indicate that the value shouldn't be lower than
 628          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 629          * Lets go for 8 which is the burst size since certain platforms
 630          * already use a hardcoded 8 (which is what the spec says should be
 631          * done).
 632          */
 633         if (wm_size <= 8)
 634                 wm_size = 8;
 635
 636         return wm_size;
 637 }
 638
 639 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 640 {
 641         struct intel_crtc *crtc, *enabled = NULL;
 642
 643         for_each_intel_crtc(&dev_priv->drm, crtc) {
 644                 if (intel_crtc_active(crtc)) {
 645                         if (enabled)
 646                                 return NULL;
 647                         enabled = crtc;
 648                 }
 649         }
 650
 651         return enabled;
 652 }
 653
 654 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 655 {
 656         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 657         struct intel_crtc *crtc;
 658         const struct cxsr_latency *latency;
 659         u32 reg;
 660         unsigned long wm;
 661
 662         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 663                                          dev_priv->is_ddr3,
 664                                          dev_priv->fsb_freq,
 665                                          dev_priv->mem_freq);
 666         if (!latency) {
 667                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 668                 intel_set_memory_cxsr(dev_priv, false);
 669                 return;
 670         }
 671
 672         crtc = single_enabled_crtc(dev_priv);
 673         if (crtc) {
 674                 const struct drm_display_mode *adjusted_mode =
 675                         &crtc->config->base.adjusted_mode;
 676                 const struct drm_framebuffer *fb =
 677                         crtc->base.primary->state->fb;
 678                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 679                 int clock = adjusted_mode->crtc_clock;
 680
 681                 /* Display SR */
 682                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 683                                         pineview_display_wm.fifo_size,
 684                                         cpp, latency->display_sr);
 685                 reg = I915_READ(DSPFW1);
 686                 reg &= ~DSPFW_SR_MASK;
 687                 reg |= FW_WM(wm, SR);
 688                 I915_WRITE(DSPFW1, reg);
 689                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 690
 691                 /* cursor SR */
 692                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 693                                         pineview_display_wm.fifo_size,
 694                                         cpp, latency->cursor_sr);
 695                 reg = I915_READ(DSPFW3);
 696                 reg &= ~DSPFW_CURSOR_SR_MASK;
 697                 reg |= FW_WM(wm, CURSOR_SR);
 698                 I915_WRITE(DSPFW3, reg);
 699
 700                 /* Display HPLL off SR */
 701                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 702                                         pineview_display_hplloff_wm.fifo_size,
 703                                         cpp, latency->display_hpll_disable);
 704                 reg = I915_READ(DSPFW3);
 705                 reg &= ~DSPFW_HPLL_SR_MASK;
 706                 reg |= FW_WM(wm, HPLL_SR);
 707                 I915_WRITE(DSPFW3, reg);
 708
 709                 /* cursor HPLL off SR */
 710                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 711                                         pineview_display_hplloff_wm.fifo_size,
 712                                         cpp, latency->cursor_hpll_disable);
 713                 reg = I915_READ(DSPFW3);
 714                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 715                 reg |= FW_WM(wm, HPLL_CURSOR);
 716                 I915_WRITE(DSPFW3, reg);
 717                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 718
 719                 intel_set_memory_cxsr(dev_priv, true);
 720         } else {
 721                 intel_set_memory_cxsr(dev_priv, false);
 722         }
 723 }
 724
 725 static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
 726                             int plane,
 727                             const struct intel_watermark_params *display,
 728                             int display_latency_ns,
 729                             const struct intel_watermark_params *cursor,
 730                             int cursor_latency_ns,
 731                             int *plane_wm,
 732                             int *cursor_wm)
 733 {
 734         struct intel_crtc *crtc;
 735         const struct drm_display_mode *adjusted_mode;
 736         const struct drm_framebuffer *fb;
 737         int htotal, hdisplay, clock, cpp;
 738         int line_time_us, line_count;
 739         int entries, tlb_miss;
 740
 741         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 742         if (!intel_crtc_active(crtc)) {
 743                 *cursor_wm = cursor->guard_size;
 744                 *plane_wm = display->guard_size;
 745                 return false;
 746         }
 747
 748         adjusted_mode = &crtc->config->base.adjusted_mode;
 749         fb = crtc->base.primary->state->fb;
 750         clock = adjusted_mode->crtc_clock;
 751         htotal = adjusted_mode->crtc_htotal;
 752         hdisplay = crtc->config->pipe_src_w;
 753         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 754
 755         /* Use the small buffer method to calculate plane watermark */
 756         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 757         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 758         if (tlb_miss > 0)
 759                 entries += tlb_miss;
 760         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 761         *plane_wm = entries + display->guard_size;
 762         if (*plane_wm > (int)display->max_wm)
 763                 *plane_wm = display->max_wm;
 764
 765         /* Use the large buffer method to calculate cursor watermark */
 766         line_time_us = max(htotal * 1000 / clock, 1);
 767         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 768         entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
 769         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 770         if (tlb_miss > 0)
 771                 entries += tlb_miss;
 772         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 773         *cursor_wm = entries + cursor->guard_size;
 774         if (*cursor_wm > (int)cursor->max_wm)
 775                 *cursor_wm = (int)cursor->max_wm;
 776
 777         return true;
 778 }
 779
 780 /*
 781  * Check the wm result.
 782  *
 783  * If any calculated watermark values is larger than the maximum value that
 784  * can be programmed into the associated watermark register, that watermark
 785  * must be disabled.
 786  */
 787 static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
 788                            int display_wm, int cursor_wm,
 789                            const struct intel_watermark_params *display,
 790                            const struct intel_watermark_params *cursor)
 791 {
 792         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 793                       display_wm, cursor_wm);
 794
 795         if (display_wm > display->max_wm) {
 796                 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
 797                               display_wm, display->max_wm);
 798                 return false;
 799         }
 800
 801         if (cursor_wm > cursor->max_wm) {
 802                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
 803                               cursor_wm, cursor->max_wm);
 804                 return false;
 805         }
 806
 807         if (!(display_wm || cursor_wm)) {
 808                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 809                 return false;
 810         }
 811
 812         return true;
 813 }
 814
 815 static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
 816                              int plane,
 817                              int latency_ns,
 818                              const struct intel_watermark_params *display,
 819                              const struct intel_watermark_params *cursor,
 820                              int *display_wm, int *cursor_wm)
 821 {
 822         struct intel_crtc *crtc;
 823         const struct drm_display_mode *adjusted_mode;
 824         const struct drm_framebuffer *fb;
 825         int hdisplay, htotal, cpp, clock;
 826         unsigned long line_time_us;
 827         int line_count, line_size;
 828         int small, large;
 829         int entries;
 830
 831         if (!latency_ns) {
 832                 *display_wm = *cursor_wm = 0;
 833                 return false;
 834         }
 835
 836         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 837         adjusted_mode = &crtc->config->base.adjusted_mode;
 838         fb = crtc->base.primary->state->fb;
 839         clock = adjusted_mode->crtc_clock;
 840         htotal = adjusted_mode->crtc_htotal;
 841         hdisplay = crtc->config->pipe_src_w;
 842         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 843
 844         line_time_us = max(htotal * 1000 / clock, 1);
 845         line_count = (latency_ns / line_time_us + 1000) / 1000;
 846         line_size = hdisplay * cpp;
 847
 848         /* Use the minimum of the small and large buffer method for primary */
 849         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 850         large = line_count * line_size;
 851
 852         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 853         *display_wm = entries + display->guard_size;
 854
 855         /* calculate the self-refresh watermark for display cursor */
 856         entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
 857         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 858         *cursor_wm = entries + cursor->guard_size;
 859
 860         return g4x_check_srwm(dev_priv,
 861                               *display_wm, *cursor_wm,
 862                               display, cursor);
 863 }
 864
 865 #define FW_WM_VLV(value, plane) \
 866         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 867
 868 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 869                                 const struct vlv_wm_values *wm)
 870 {
 871         enum pipe pipe;
 872
 873         for_each_pipe(dev_priv, pipe) {
 874                 I915_WRITE(VLV_DDL(pipe),
 875                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
 876                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
 877                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
 878                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
 879         }
 880
 881         /*
 882          * Zero the (unused) WM1 watermarks, and also clear all the
 883          * high order bits so that there are no out of bounds values
 884          * present in the registers during the reprogramming.
 885          */
 886         I915_WRITE(DSPHOWM, 0);
 887         I915_WRITE(DSPHOWM1, 0);
 888         I915_WRITE(DSPFW4, 0);
 889         I915_WRITE(DSPFW5, 0);
 890         I915_WRITE(DSPFW6, 0);
 891
 892         I915_WRITE(DSPFW1,
 893                    FW_WM(wm->sr.plane, SR) |
 894                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 895                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 896                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 897         I915_WRITE(DSPFW2,
 898                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
 899                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 900                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 901         I915_WRITE(DSPFW3,
 902                    FW_WM(wm->sr.cursor, CURSOR_SR));
 903
 904         if (IS_CHERRYVIEW(dev_priv)) {
 905                 I915_WRITE(DSPFW7_CHV,
 906                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
 907                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
 908                 I915_WRITE(DSPFW8_CHV,
 909                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
 910                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
 911                 I915_WRITE(DSPFW9_CHV,
 912                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
 913                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
 914                 I915_WRITE(DSPHOWM,
 915                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 916                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
 917                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
 918                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
 919                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
 920                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
 921                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
 922                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
 923                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
 924                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
 925         } else {
 926                 I915_WRITE(DSPFW7,
 927                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
 928                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
 929                 I915_WRITE(DSPHOWM,
 930                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 931                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
 932                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
 933                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
 934                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
 935                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
 936                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
 937         }
 938
 939         POSTING_READ(DSPFW1);
 940 }
 941
 942 #undef FW_WM_VLV
 943
 944 enum vlv_wm_level {
 945         VLV_WM_LEVEL_PM2,
 946         VLV_WM_LEVEL_PM5,
 947         VLV_WM_LEVEL_DDR_DVFS,
 948 };
 949
 950 /* latency must be in 0.1us units. */
 951 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 952                                    unsigned int pipe_htotal,
 953                                    unsigned int horiz_pixels,
 954                                    unsigned int cpp,
 955                                    unsigned int latency)
 956 {
 957         unsigned int ret;
 958
 959         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 960         ret = (ret + 1) * horiz_pixels * cpp;
 961         ret = DIV_ROUND_UP(ret, 64);
 962
 963         return ret;
 964 }
 965
 966 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
 967 {
 968         /* all latencies in usec */
 969         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 970
 971         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 972
 973         if (IS_CHERRYVIEW(dev_priv)) {
 974                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 975                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 976
 977                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 978         }
 979 }
 980
 981 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 982                                      const struct intel_plane_state *plane_state,
 983                                      int level)
 984 {
 985         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 986         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 987         const struct drm_display_mode *adjusted_mode =
 988                 &crtc_state->base.adjusted_mode;
 989         int clock, htotal, cpp, width, wm;
 990
 991         if (dev_priv->wm.pri_latency[level] == 0)
 992                 return USHRT_MAX;
 993
 994         if (!plane_state->base.visible)
 995                 return 0;
 996
 997         cpp = drm_format_plane_cpp(plane_state->base.fb->pixel_format, 0);
 998         clock = adjusted_mode->crtc_clock;
 999         htotal = adjusted_mode->crtc_htotal;
1000         width = crtc_state->pipe_src_w;
1001         if (WARN_ON(htotal == 0))
1002                 htotal = 1;
1003
1004         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1005                 /*
1006                  * FIXME the formula gives values that are
1007                  * too big for the cursor FIFO, and hence we
1008                  * would never be able to use cursors. For
1009                  * now just hardcode the watermark.
1010                  */
1011                 wm = 63;
1012         } else {
1013                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1014                                     dev_priv->wm.pri_latency[level] * 10);
1015         }
1016
1017         return min_t(int, wm, USHRT_MAX);
1018 }
1019
1020 static void vlv_compute_fifo(struct intel_crtc *crtc)
1021 {
1022         struct drm_device *dev = crtc->base.dev;
1023         struct vlv_wm_state *wm_state = &crtc->wm_state;
1024         struct intel_plane *plane;
1025         unsigned int total_rate = 0;
1026         const int fifo_size = 512 - 1;
1027         int fifo_extra, fifo_left = fifo_size;
1028
1029         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1030                 struct intel_plane_state *state =
1031                         to_intel_plane_state(plane->base.state);
1032
1033                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1034                         continue;
1035
1036                 if (state->base.visible) {
1037                         wm_state->num_active_planes++;
1038                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1039                 }
1040         }
1041
1042         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1043                 struct intel_plane_state *state =
1044                         to_intel_plane_state(plane->base.state);
1045                 unsigned int rate;
1046
1047                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1048                         plane->wm.fifo_size = 63;
1049                         continue;
1050                 }
1051
1052                 if (!state->base.visible) {
1053                         plane->wm.fifo_size = 0;
1054                         continue;
1055                 }
1056
1057                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1058                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1059                 fifo_left -= plane->wm.fifo_size;
1060         }
1061
1062         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1063
1064         /* spread the remainder evenly */
1065         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1066                 int plane_extra;
1067
1068                 if (fifo_left == 0)
1069                         break;
1070
1071                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1072                         continue;
1073
1074                 /* give it all to the first plane if none are active */
1075                 if (plane->wm.fifo_size == 0 &&
1076                     wm_state->num_active_planes)
1077                         continue;
1078
1079                 plane_extra = min(fifo_extra, fifo_left);
1080                 plane->wm.fifo_size += plane_extra;
1081                 fifo_left -= plane_extra;
1082         }
1083
1084         WARN_ON(fifo_left != 0);
1085 }
1086
1087 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1088 {
1089         if (wm > fifo_size)
1090                 return USHRT_MAX;
1091         else
1092                 return fifo_size - wm;
1093 }
1094
1095 static void vlv_invert_wms(struct intel_crtc *crtc)
1096 {
1097         struct vlv_wm_state *wm_state = &crtc->wm_state;
1098         int level;
1099
1100         for (level = 0; level < wm_state->num_levels; level++) {
1101                 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1102                 const int sr_fifo_size =
1103                         INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1104                 struct intel_plane *plane;
1105
1106                 wm_state->sr[level].plane =
1107                         vlv_invert_wm_value(wm_state->sr[level].plane,
1108                                             sr_fifo_size);
1109                 wm_state->sr[level].cursor =
1110                         vlv_invert_wm_value(wm_state->sr[level].cursor,
1111                                             63);
1112
1113                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1114                         wm_state->wm[level].plane[plane->id] =
1115                                 vlv_invert_wm_value(wm_state->wm[level].plane[plane->id],
1116                                                     plane->wm.fifo_size);
1117                 }
1118         }
1119 }
1120
1121 static void vlv_compute_wm(struct intel_crtc *crtc)
1122 {
1123         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1124         struct vlv_wm_state *wm_state = &crtc->wm_state;
1125         struct intel_plane *plane;
1126         int level;
1127
1128         memset(wm_state, 0, sizeof(*wm_state));
1129
1130         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1131         wm_state->num_levels = dev_priv->wm.max_level + 1;
1132
1133         wm_state->num_active_planes = 0;
1134
1135         vlv_compute_fifo(crtc);
1136
1137         if (wm_state->num_active_planes != 1)
1138                 wm_state->cxsr = false;
1139
1140         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1141                 struct intel_plane_state *state =
1142                         to_intel_plane_state(plane->base.state);
1143                 int level;
1144
1145                 if (!state->base.visible)
1146                         continue;
1147
1148                 /* normal watermarks */
1149                 for (level = 0; level < wm_state->num_levels; level++) {
1150                         int wm = vlv_compute_wm_level(crtc->config, state, level);
1151                         int max_wm = plane->wm.fifo_size;
1152
1153                         /* hack */
1154                         if (WARN_ON(level == 0 && wm > max_wm))
1155                                 wm = max_wm;
1156
1157                         if (wm > max_wm)
1158                                 break;
1159
1160                         wm_state->wm[level].plane[plane->id] = wm;
1161                 }
1162
1163                 wm_state->num_levels = level;
1164
1165                 if (!wm_state->cxsr)
1166                         continue;
1167
1168                 /* maxfifo watermarks */
1169                 if (plane->id == PLANE_CURSOR) {
1170                         for (level = 0; level < wm_state->num_levels; level++)
1171                                 wm_state->sr[level].cursor =
1172                                         wm_state->wm[level].plane[PLANE_CURSOR];
1173                 } else {
1174                         for (level = 0; level < wm_state->num_levels; level++)
1175                                 wm_state->sr[level].plane =
1176                                         max(wm_state->sr[level].plane,
1177                                             wm_state->wm[level].plane[plane->id]);
1178                 }
1179         }
1180
1181         /* clear any (partially) filled invalid levels */
1182         for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
1183                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1184                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1185         }
1186
1187         vlv_invert_wms(crtc);
1188 }
1189
1190 #define VLV_FIFO(plane, value) \
1191         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1192
1193 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1194 {
1195         struct drm_device *dev = crtc->base.dev;
1196         struct drm_i915_private *dev_priv = to_i915(dev);
1197         struct intel_plane *plane;
1198         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1199
1200         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1201                 switch (plane->id) {
1202                 case PLANE_PRIMARY:
1203                         sprite0_start = plane->wm.fifo_size;
1204                         break;
1205                 case PLANE_SPRITE0:
1206                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1207                         break;
1208                 case PLANE_SPRITE1:
1209                         fifo_size = sprite1_start + plane->wm.fifo_size;
1210                         break;
1211                 case PLANE_CURSOR:
1212                         WARN_ON(plane->wm.fifo_size != 63);
1213                         break;
1214                 default:
1215                         MISSING_CASE(plane->id);
1216                         break;
1217                 }
1218         }
1219
1220         WARN_ON(fifo_size != 512 - 1);
1221
1222         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1223                       pipe_name(crtc->pipe), sprite0_start,
1224                       sprite1_start, fifo_size);
1225
1226         spin_lock(&dev_priv->wm.dsparb_lock);
1227
1228         switch (crtc->pipe) {
1229                 uint32_t dsparb, dsparb2, dsparb3;
1230         case PIPE_A:
1231                 dsparb = I915_READ(DSPARB);
1232                 dsparb2 = I915_READ(DSPARB2);
1233
1234                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1235                             VLV_FIFO(SPRITEB, 0xff));
1236                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1237                            VLV_FIFO(SPRITEB, sprite1_start));
1238
1239                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1240                              VLV_FIFO(SPRITEB_HI, 0x1));
1241                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1242                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1243
1244                 I915_WRITE(DSPARB, dsparb);
1245                 I915_WRITE(DSPARB2, dsparb2);
1246                 break;
1247         case PIPE_B:
1248                 dsparb = I915_READ(DSPARB);
1249                 dsparb2 = I915_READ(DSPARB2);
1250
1251                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1252                             VLV_FIFO(SPRITED, 0xff));
1253                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1254                            VLV_FIFO(SPRITED, sprite1_start));
1255
1256                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1257                              VLV_FIFO(SPRITED_HI, 0xff));
1258                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1259                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1260
1261                 I915_WRITE(DSPARB, dsparb);
1262                 I915_WRITE(DSPARB2, dsparb2);
1263                 break;
1264         case PIPE_C:
1265                 dsparb3 = I915_READ(DSPARB3);
1266                 dsparb2 = I915_READ(DSPARB2);
1267
1268                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1269                              VLV_FIFO(SPRITEF, 0xff));
1270                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1271                             VLV_FIFO(SPRITEF, sprite1_start));
1272
1273                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1274                              VLV_FIFO(SPRITEF_HI, 0xff));
1275                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1276                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1277
1278                 I915_WRITE(DSPARB3, dsparb3);
1279                 I915_WRITE(DSPARB2, dsparb2);
1280                 break;
1281         default:
1282                 break;
1283         }
1284
1285         POSTING_READ(DSPARB);
1286
1287         spin_unlock(&dev_priv->wm.dsparb_lock);
1288 }
1289
1290 #undef VLV_FIFO
1291
1292 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
1293                          struct vlv_wm_values *wm)
1294 {
1295         struct intel_crtc *crtc;
1296         int num_active_crtcs = 0;
1297
1298         wm->level = dev_priv->wm.max_level;
1299         wm->cxsr = true;
1300
1301         for_each_intel_crtc(&dev_priv->drm, crtc) {
1302                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1303
1304                 if (!crtc->active)
1305                         continue;
1306
1307                 if (!wm_state->cxsr)
1308                         wm->cxsr = false;
1309
1310                 num_active_crtcs++;
1311                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1312         }
1313
1314         if (num_active_crtcs != 1)
1315                 wm->cxsr = false;
1316
1317         if (num_active_crtcs > 1)
1318                 wm->level = VLV_WM_LEVEL_PM2;
1319
1320         for_each_intel_crtc(&dev_priv->drm, crtc) {
1321                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1322                 enum pipe pipe = crtc->pipe;
1323
1324                 if (!crtc->active)
1325                         continue;
1326
1327                 wm->pipe[pipe] = wm_state->wm[wm->level];
1328                 if (wm->cxsr)
1329                         wm->sr = wm_state->sr[wm->level];
1330
1331                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
1332                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
1333                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
1334                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
1335         }
1336 }
1337
1338 static bool is_disabling(int old, int new, int threshold)
1339 {
1340         return old >= threshold && new < threshold;
1341 }
1342
1343 static bool is_enabling(int old, int new, int threshold)
1344 {
1345         return old < threshold && new >= threshold;
1346 }
1347
1348 static void vlv_update_wm(struct intel_crtc *crtc)
1349 {
1350         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1351         enum pipe pipe = crtc->pipe;
1352         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
1353         struct vlv_wm_values new_wm = {};
1354
1355         vlv_compute_wm(crtc);
1356         vlv_merge_wm(dev_priv, &new_wm);
1357
1358         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) {
1359                 /* FIXME should be part of crtc atomic commit */
1360                 vlv_pipe_set_fifo_size(crtc);
1361
1362                 return;
1363         }
1364
1365         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
1366                 chv_set_memory_dvfs(dev_priv, false);
1367
1368         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
1369                 chv_set_memory_pm5(dev_priv, false);
1370
1371         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1372                 _intel_set_memory_cxsr(dev_priv, false);
1373
1374         /* FIXME should be part of crtc atomic commit */
1375         vlv_pipe_set_fifo_size(crtc);
1376
1377         vlv_write_wm_values(dev_priv, &new_wm);
1378
1379         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1380                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1381                       pipe_name(pipe), new_wm.pipe[pipe].plane[PLANE_PRIMARY], new_wm.pipe[pipe].plane[PLANE_CURSOR],
1382                       new_wm.pipe[pipe].plane[PLANE_SPRITE0], new_wm.pipe[pipe].plane[PLANE_SPRITE1],
1383                       new_wm.sr.plane, new_wm.sr.cursor, new_wm.level, new_wm.cxsr);
1384
1385         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1386                 _intel_set_memory_cxsr(dev_priv, true);
1387
1388         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
1389                 chv_set_memory_pm5(dev_priv, true);
1390
1391         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
1392                 chv_set_memory_dvfs(dev_priv, true);
1393
1394         *old_wm = new_wm;
1395 }
1396
1397 #define single_plane_enabled(mask) is_power_of_2(mask)
1398
1399 static void g4x_update_wm(struct intel_crtc *crtc)
1400 {
1401         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1402         static const int sr_latency_ns = 12000;
1403         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1404         int plane_sr, cursor_sr;
1405         unsigned int enabled = 0;
1406         bool cxsr_enabled;
1407
1408         if (g4x_compute_wm0(dev_priv, PIPE_A,
1409                             &g4x_wm_info, pessimal_latency_ns,
1410                             &g4x_cursor_wm_info, pessimal_latency_ns,
1411                             &planea_wm, &cursora_wm))
1412                 enabled |= 1 << PIPE_A;
1413
1414         if (g4x_compute_wm0(dev_priv, PIPE_B,
1415                             &g4x_wm_info, pessimal_latency_ns,
1416                             &g4x_cursor_wm_info, pessimal_latency_ns,
1417                             &planeb_wm, &cursorb_wm))
1418                 enabled |= 1 << PIPE_B;
1419
1420         if (single_plane_enabled(enabled) &&
1421             g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1422                              sr_latency_ns,
1423                              &g4x_wm_info,
1424                              &g4x_cursor_wm_info,
1425                              &plane_sr, &cursor_sr)) {
1426                 cxsr_enabled = true;
1427         } else {
1428                 cxsr_enabled = false;
1429                 intel_set_memory_cxsr(dev_priv, false);
1430                 plane_sr = cursor_sr = 0;
1431         }
1432
1433         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1434                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1435                       planea_wm, cursora_wm,
1436                       planeb_wm, cursorb_wm,
1437                       plane_sr, cursor_sr);
1438
1439         I915_WRITE(DSPFW1,
1440                    FW_WM(plane_sr, SR) |
1441                    FW_WM(cursorb_wm, CURSORB) |
1442                    FW_WM(planeb_wm, PLANEB) |
1443                    FW_WM(planea_wm, PLANEA));
1444         I915_WRITE(DSPFW2,
1445                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1446                    FW_WM(cursora_wm, CURSORA));
1447         /* HPLL off in SR has some issues on G4x... disable it */
1448         I915_WRITE(DSPFW3,
1449                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1450                    FW_WM(cursor_sr, CURSOR_SR));
1451
1452         if (cxsr_enabled)
1453                 intel_set_memory_cxsr(dev_priv, true);
1454 }
1455
1456 static void i965_update_wm(struct intel_crtc *unused_crtc)
1457 {
1458         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1459         struct intel_crtc *crtc;
1460         int srwm = 1;
1461         int cursor_sr = 16;
1462         bool cxsr_enabled;
1463
1464         /* Calc sr entries for one plane configs */
1465         crtc = single_enabled_crtc(dev_priv);
1466         if (crtc) {
1467                 /* self-refresh has much higher latency */
1468                 static const int sr_latency_ns = 12000;
1469                 const struct drm_display_mode *adjusted_mode =
1470                         &crtc->config->base.adjusted_mode;
1471                 const struct drm_framebuffer *fb =
1472                         crtc->base.primary->state->fb;
1473                 int clock = adjusted_mode->crtc_clock;
1474                 int htotal = adjusted_mode->crtc_htotal;
1475                 int hdisplay = crtc->config->pipe_src_w;
1476                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1477                 unsigned long line_time_us;
1478                 int entries;
1479
1480                 line_time_us = max(htotal * 1000 / clock, 1);
1481
1482                 /* Use ns/us then divide to preserve precision */
1483                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1484                         cpp * hdisplay;
1485                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1486                 srwm = I965_FIFO_SIZE - entries;
1487                 if (srwm < 0)
1488                         srwm = 1;
1489                 srwm &= 0x1ff;
1490                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1491                               entries, srwm);
1492
1493                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1494                         cpp * crtc->base.cursor->state->crtc_w;
1495                 entries = DIV_ROUND_UP(entries,
1496                                           i965_cursor_wm_info.cacheline_size);
1497                 cursor_sr = i965_cursor_wm_info.fifo_size -
1498                         (entries + i965_cursor_wm_info.guard_size);
1499
1500                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1501                         cursor_sr = i965_cursor_wm_info.max_wm;
1502
1503                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1504                               "cursor %d\n", srwm, cursor_sr);
1505
1506                 cxsr_enabled = true;
1507         } else {
1508                 cxsr_enabled = false;
1509                 /* Turn off self refresh if both pipes are enabled */
1510                 intel_set_memory_cxsr(dev_priv, false);
1511         }
1512
1513         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1514                       srwm);
1515
1516         /* 965 has limitations... */
1517         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1518                    FW_WM(8, CURSORB) |
1519                    FW_WM(8, PLANEB) |
1520                    FW_WM(8, PLANEA));
1521         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1522                    FW_WM(8, PLANEC_OLD));
1523         /* update cursor SR watermark */
1524         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1525
1526         if (cxsr_enabled)
1527                 intel_set_memory_cxsr(dev_priv, true);
1528 }
1529
1530 #undef FW_WM
1531
1532 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1533 {
1534         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1535         const struct intel_watermark_params *wm_info;
1536         uint32_t fwater_lo;
1537         uint32_t fwater_hi;
1538         int cwm, srwm = 1;
1539         int fifo_size;
1540         int planea_wm, planeb_wm;
1541         struct intel_crtc *crtc, *enabled = NULL;
1542
1543         if (IS_I945GM(dev_priv))
1544                 wm_info = &i945_wm_info;
1545         else if (!IS_GEN2(dev_priv))
1546                 wm_info = &i915_wm_info;
1547         else
1548                 wm_info = &i830_a_wm_info;
1549
1550         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1551         crtc = intel_get_crtc_for_plane(dev_priv, 0);
1552         if (intel_crtc_active(crtc)) {
1553                 const struct drm_display_mode *adjusted_mode =
1554                         &crtc->config->base.adjusted_mode;
1555                 const struct drm_framebuffer *fb =
1556                         crtc->base.primary->state->fb;
1557                 int cpp;
1558
1559                 if (IS_GEN2(dev_priv))
1560                         cpp = 4;
1561                 else
1562                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1563
1564                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1565                                                wm_info, fifo_size, cpp,
1566                                                pessimal_latency_ns);
1567                 enabled = crtc;
1568         } else {
1569                 planea_wm = fifo_size - wm_info->guard_size;
1570                 if (planea_wm > (long)wm_info->max_wm)
1571                         planea_wm = wm_info->max_wm;
1572         }
1573
1574         if (IS_GEN2(dev_priv))
1575                 wm_info = &i830_bc_wm_info;
1576
1577         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1578         crtc = intel_get_crtc_for_plane(dev_priv, 1);
1579         if (intel_crtc_active(crtc)) {
1580                 const struct drm_display_mode *adjusted_mode =
1581                         &crtc->config->base.adjusted_mode;
1582                 const struct drm_framebuffer *fb =
1583                         crtc->base.primary->state->fb;
1584                 int cpp;
1585
1586                 if (IS_GEN2(dev_priv))
1587                         cpp = 4;
1588                 else
1589                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1590
1591                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1592                                                wm_info, fifo_size, cpp,
1593                                                pessimal_latency_ns);
1594                 if (enabled == NULL)
1595                         enabled = crtc;
1596                 else
1597                         enabled = NULL;
1598         } else {
1599                 planeb_wm = fifo_size - wm_info->guard_size;
1600                 if (planeb_wm > (long)wm_info->max_wm)
1601                         planeb_wm = wm_info->max_wm;
1602         }
1603
1604         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1605
1606         if (IS_I915GM(dev_priv) && enabled) {
1607                 struct drm_i915_gem_object *obj;
1608
1609                 obj = intel_fb_obj(enabled->base.primary->state->fb);
1610
1611                 /* self-refresh seems busted with untiled */
1612                 if (!i915_gem_object_is_tiled(obj))
1613                         enabled = NULL;
1614         }
1615
1616         /*
1617          * Overlay gets an aggressive default since video jitter is bad.
1618          */
1619         cwm = 2;
1620
1621         /* Play safe and disable self-refresh before adjusting watermarks. */
1622         intel_set_memory_cxsr(dev_priv, false);
1623
1624         /* Calc sr entries for one plane configs */
1625         if (HAS_FW_BLC(dev_priv) && enabled) {
1626                 /* self-refresh has much higher latency */
1627                 static const int sr_latency_ns = 6000;
1628                 const struct drm_display_mode *adjusted_mode =
1629                         &enabled->config->base.adjusted_mode;
1630                 const struct drm_framebuffer *fb =
1631                         enabled->base.primary->state->fb;
1632                 int clock = adjusted_mode->crtc_clock;
1633                 int htotal = adjusted_mode->crtc_htotal;
1634                 int hdisplay = enabled->config->pipe_src_w;
1635                 int cpp;
1636                 unsigned long line_time_us;
1637                 int entries;
1638
1639                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1640                         cpp = 4;
1641                 else
1642                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1643
1644                 line_time_us = max(htotal * 1000 / clock, 1);
1645
1646                 /* Use ns/us then divide to preserve precision */
1647                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1648                         cpp * hdisplay;
1649                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1650                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1651                 srwm = wm_info->fifo_size - entries;
1652                 if (srwm < 0)
1653                         srwm = 1;
1654
1655                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1656                         I915_WRITE(FW_BLC_SELF,
1657                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1658                 else
1659                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1660         }
1661
1662         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1663                       planea_wm, planeb_wm, cwm, srwm);
1664
1665         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1666         fwater_hi = (cwm & 0x1f);
1667
1668         /* Set request length to 8 cachelines per fetch */
1669         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1670         fwater_hi = fwater_hi | (1 << 8);
1671
1672         I915_WRITE(FW_BLC, fwater_lo);
1673         I915_WRITE(FW_BLC2, fwater_hi);
1674
1675         if (enabled)
1676                 intel_set_memory_cxsr(dev_priv, true);
1677 }
1678
1679 static void i845_update_wm(struct intel_crtc *unused_crtc)
1680 {
1681         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1682         struct intel_crtc *crtc;
1683         const struct drm_display_mode *adjusted_mode;
1684         uint32_t fwater_lo;
1685         int planea_wm;
1686
1687         crtc = single_enabled_crtc(dev_priv);
1688         if (crtc == NULL)
1689                 return;
1690
1691         adjusted_mode = &crtc->config->base.adjusted_mode;
1692         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1693                                        &i845_wm_info,
1694                                        dev_priv->display.get_fifo_size(dev_priv, 0),
1695                                        4, pessimal_latency_ns);
1696         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1697         fwater_lo |= (3<<8) | planea_wm;
1698
1699         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1700
1701         I915_WRITE(FW_BLC, fwater_lo);
1702 }
1703
1704 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1705 {
1706         uint32_t pixel_rate;
1707
1708         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1709
1710         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1711          * adjust the pixel_rate here. */
1712
1713         if (pipe_config->pch_pfit.enabled) {
1714                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1715                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1716
1717                 pipe_w = pipe_config->pipe_src_w;
1718                 pipe_h = pipe_config->pipe_src_h;
1719
1720                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1721                 pfit_h = pfit_size & 0xFFFF;
1722                 if (pipe_w < pfit_w)
1723                         pipe_w = pfit_w;
1724                 if (pipe_h < pfit_h)
1725                         pipe_h = pfit_h;
1726
1727                 if (WARN_ON(!pfit_w || !pfit_h))
1728                         return pixel_rate;
1729
1730                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1731                                      pfit_w * pfit_h);
1732         }
1733
1734         return pixel_rate;
1735 }
1736
1737 /* latency must be in 0.1us units. */
1738 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1739 {
1740         uint64_t ret;
1741
1742         if (WARN(latency == 0, "Latency value missing\n"))
1743                 return UINT_MAX;
1744
1745         ret = (uint64_t) pixel_rate * cpp * latency;
1746         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1747
1748         return ret;
1749 }
1750
1751 /* latency must be in 0.1us units. */
1752 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1753                                uint32_t horiz_pixels, uint8_t cpp,
1754                                uint32_t latency)
1755 {
1756         uint32_t ret;
1757
1758         if (WARN(latency == 0, "Latency value missing\n"))
1759                 return UINT_MAX;
1760         if (WARN_ON(!pipe_htotal))
1761                 return UINT_MAX;
1762
1763         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1764         ret = (ret + 1) * horiz_pixels * cpp;
1765         ret = DIV_ROUND_UP(ret, 64) + 2;
1766         return ret;
1767 }
1768
1769 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1770                            uint8_t cpp)
1771 {
1772         /*
1773          * Neither of these should be possible since this function shouldn't be
1774          * called if the CRTC is off or the plane is invisible.  But let's be
1775          * extra paranoid to avoid a potential divide-by-zero if we screw up
1776          * elsewhere in the driver.
1777          */
1778         if (WARN_ON(!cpp))
1779                 return 0;
1780         if (WARN_ON(!horiz_pixels))
1781                 return 0;
1782
1783         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1784 }
1785
1786 struct ilk_wm_maximums {
1787         uint16_t pri;
1788         uint16_t spr;
1789         uint16_t cur;
1790         uint16_t fbc;
1791 };
1792
1793 /*
1794  * For both WM_PIPE and WM_LP.
1795  * mem_value must be in 0.1us units.
1796  */
1797 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1798                                    const struct intel_plane_state *pstate,
1799                                    uint32_t mem_value,
1800                                    bool is_lp)
1801 {
1802         int cpp = pstate->base.fb ?
1803                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1804         uint32_t method1, method2;
1805
1806         if (!cstate->base.active || !pstate->base.visible)
1807                 return 0;
1808
1809         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1810
1811         if (!is_lp)
1812                 return method1;
1813
1814         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1815                                  cstate->base.adjusted_mode.crtc_htotal,
1816                                  drm_rect_width(&pstate->base.dst),
1817                                  cpp, mem_value);
1818
1819         return min(method1, method2);
1820 }
1821
1822 /*
1823  * For both WM_PIPE and WM_LP.
1824  * mem_value must be in 0.1us units.
1825  */
1826 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1827                                    const struct intel_plane_state *pstate,
1828                                    uint32_t mem_value)
1829 {
1830         int cpp = pstate->base.fb ?
1831                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1832         uint32_t method1, method2;
1833
1834         if (!cstate->base.active || !pstate->base.visible)
1835                 return 0;
1836
1837         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1838         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1839                                  cstate->base.adjusted_mode.crtc_htotal,
1840                                  drm_rect_width(&pstate->base.dst),
1841                                  cpp, mem_value);
1842         return min(method1, method2);
1843 }
1844
1845 /*
1846  * For both WM_PIPE and WM_LP.
1847  * mem_value must be in 0.1us units.
1848  */
1849 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1850                                    const struct intel_plane_state *pstate,
1851                                    uint32_t mem_value)
1852 {
1853         /*
1854          * We treat the cursor plane as always-on for the purposes of watermark
1855          * calculation.  Until we have two-stage watermark programming merged,
1856          * this is necessary to avoid flickering.
1857          */
1858         int cpp = 4;
1859         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1860
1861         if (!cstate->base.active)
1862                 return 0;
1863
1864         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1865                               cstate->base.adjusted_mode.crtc_htotal,
1866                               width, cpp, mem_value);
1867 }
1868
1869 /* Only for WM_LP. */
1870 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1871                                    const struct intel_plane_state *pstate,
1872                                    uint32_t pri_val)
1873 {
1874         int cpp = pstate->base.fb ?
1875                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1876
1877         if (!cstate->base.active || !pstate->base.visible)
1878                 return 0;
1879
1880         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1881 }
1882
1883 static unsigned int
1884 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
1885 {
1886         if (INTEL_GEN(dev_priv) >= 8)
1887                 return 3072;
1888         else if (INTEL_GEN(dev_priv) >= 7)
1889                 return 768;
1890         else
1891                 return 512;
1892 }
1893
1894 static unsigned int
1895 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1896                      int level, bool is_sprite)
1897 {
1898         if (INTEL_GEN(dev_priv) >= 8)
1899                 /* BDW primary/sprite plane watermarks */
1900                 return level == 0 ? 255 : 2047;
1901         else if (INTEL_GEN(dev_priv) >= 7)
1902                 /* IVB/HSW primary/sprite plane watermarks */
1903                 return level == 0 ? 127 : 1023;
1904         else if (!is_sprite)
1905                 /* ILK/SNB primary plane watermarks */
1906                 return level == 0 ? 127 : 511;
1907         else
1908                 /* ILK/SNB sprite plane watermarks */
1909                 return level == 0 ? 63 : 255;
1910 }
1911
1912 static unsigned int
1913 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
1914 {
1915         if (INTEL_GEN(dev_priv) >= 7)
1916                 return level == 0 ? 63 : 255;
1917         else
1918                 return level == 0 ? 31 : 63;
1919 }
1920
1921 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
1922 {
1923         if (INTEL_GEN(dev_priv) >= 8)
1924                 return 31;
1925         else
1926                 return 15;
1927 }
1928
1929 /* Calculate the maximum primary/sprite plane watermark */
1930 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1931                                      int level,
1932                                      const struct intel_wm_config *config,
1933                                      enum intel_ddb_partitioning ddb_partitioning,
1934                                      bool is_sprite)
1935 {
1936         struct drm_i915_private *dev_priv = to_i915(dev);
1937         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
1938
1939         /* if sprites aren't enabled, sprites get nothing */
1940         if (is_sprite && !config->sprites_enabled)
1941                 return 0;
1942
1943         /* HSW allows LP1+ watermarks even with multiple pipes */
1944         if (level == 0 || config->num_pipes_active > 1) {
1945                 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
1946
1947                 /*
1948                  * For some reason the non self refresh
1949                  * FIFO size is only half of the self
1950                  * refresh FIFO size on ILK/SNB.
1951                  */
1952                 if (INTEL_GEN(dev_priv) <= 6)
1953                         fifo_size /= 2;
1954         }
1955
1956         if (config->sprites_enabled) {
1957                 /* level 0 is always calculated with 1:1 split */
1958                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1959                         if (is_sprite)
1960                                 fifo_size *= 5;
1961                         fifo_size /= 6;
1962                 } else {
1963                         fifo_size /= 2;
1964                 }
1965         }
1966
1967         /* clamp to max that the registers can hold */
1968         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
1969 }
1970
1971 /* Calculate the maximum cursor plane watermark */
1972 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1973                                       int level,
1974                                       const struct intel_wm_config *config)
1975 {
1976         /* HSW LP1+ watermarks w/ multiple pipes */
1977         if (level > 0 && config->num_pipes_active > 1)
1978                 return 64;
1979
1980         /* otherwise just report max that registers can hold */
1981         return ilk_cursor_wm_reg_max(to_i915(dev), level);
1982 }
1983
1984 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1985                                     int level,
1986                                     const struct intel_wm_config *config,
1987                                     enum intel_ddb_partitioning ddb_partitioning,
1988                                     struct ilk_wm_maximums *max)
1989 {
1990         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1991         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1992         max->cur = ilk_cursor_wm_max(dev, level, config);
1993         max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
1994 }
1995
1996 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
1997                                         int level,
1998                                         struct ilk_wm_maximums *max)
1999 {
2000         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2001         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2002         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2003         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2004 }
2005
2006 static bool ilk_validate_wm_level(int level,
2007                                   const struct ilk_wm_maximums *max,
2008                                   struct intel_wm_level *result)
2009 {
2010         bool ret;
2011
2012         /* already determined to be invalid? */
2013         if (!result->enable)
2014                 return false;
2015
2016         result->enable = result->pri_val <= max->pri &&
2017                          result->spr_val <= max->spr &&
2018                          result->cur_val <= max->cur;
2019
2020         ret = result->enable;
2021
2022         /*
2023          * HACK until we can pre-compute everything,
2024          * and thus fail gracefully if LP0 watermarks
2025          * are exceeded...
2026          */
2027         if (level == 0 && !result->enable) {
2028                 if (result->pri_val > max->pri)
2029                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2030                                       level, result->pri_val, max->pri);
2031                 if (result->spr_val > max->spr)
2032                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2033                                       level, result->spr_val, max->spr);
2034                 if (result->cur_val > max->cur)
2035                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2036                                       level, result->cur_val, max->cur);
2037
2038                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2039                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2040                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2041                 result->enable = true;
2042         }
2043
2044         return ret;
2045 }
2046
2047 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2048                                  const struct intel_crtc *intel_crtc,
2049                                  int level,
2050                                  struct intel_crtc_state *cstate,
2051                                  struct intel_plane_state *pristate,
2052                                  struct intel_plane_state *sprstate,
2053                                  struct intel_plane_state *curstate,
2054                                  struct intel_wm_level *result)
2055 {
2056         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2057         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2058         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2059
2060         /* WM1+ latency values stored in 0.5us units */
2061         if (level > 0) {
2062                 pri_latency *= 5;
2063                 spr_latency *= 5;
2064                 cur_latency *= 5;
2065         }
2066
2067         if (pristate) {
2068                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2069                                                      pri_latency, level);
2070                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2071         }
2072
2073         if (sprstate)
2074                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2075
2076         if (curstate)
2077                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2078
2079         result->enable = true;
2080 }
2081
2082 static uint32_t
2083 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2084 {
2085         const struct intel_atomic_state *intel_state =
2086                 to_intel_atomic_state(cstate->base.state);
2087         const struct drm_display_mode *adjusted_mode =
2088                 &cstate->base.adjusted_mode;
2089         u32 linetime, ips_linetime;
2090
2091         if (!cstate->base.active)
2092                 return 0;
2093         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2094                 return 0;
2095         if (WARN_ON(intel_state->cdclk == 0))
2096                 return 0;
2097
2098         /* The WM are computed with base on how long it takes to fill a single
2099          * row at the given clock rate, multiplied by 8.
2100          * */
2101         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2102                                      adjusted_mode->crtc_clock);
2103         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2104                                          intel_state->cdclk);
2105
2106         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2107                PIPE_WM_LINETIME_TIME(linetime);
2108 }
2109
2110 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2111                                   uint16_t wm[8])
2112 {
2113         if (IS_GEN9(dev_priv)) {
2114                 uint32_t val;
2115                 int ret, i;
2116                 int level, max_level = ilk_wm_max_level(dev_priv);
2117
2118                 /* read the first set of memory latencies[0:3] */
2119                 val = 0; /* data0 to be programmed to 0 for first set */
2120                 mutex_lock(&dev_priv->rps.hw_lock);
2121                 ret = sandybridge_pcode_read(dev_priv,
2122                                              GEN9_PCODE_READ_MEM_LATENCY,
2123                                              &val);
2124                 mutex_unlock(&dev_priv->rps.hw_lock);
2125
2126                 if (ret) {
2127                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2128                         return;
2129                 }
2130
2131                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2132                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2133                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2134                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2135                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2136                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2137                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2138
2139                 /* read the second set of memory latencies[4:7] */
2140                 val = 1; /* data0 to be programmed to 1 for second set */
2141                 mutex_lock(&dev_priv->rps.hw_lock);
2142                 ret = sandybridge_pcode_read(dev_priv,
2143                                              GEN9_PCODE_READ_MEM_LATENCY,
2144                                              &val);
2145                 mutex_unlock(&dev_priv->rps.hw_lock);
2146                 if (ret) {
2147                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2148                         return;
2149                 }
2150
2151                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2152                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2153                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2154                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2155                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2156                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2157                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2158
2159                 /*
2160                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2161                  * need to be disabled. We make sure to sanitize the values out
2162                  * of the punit to satisfy this requirement.
2163                  */
2164                 for (level = 1; level <= max_level; level++) {
2165                         if (wm[level] == 0) {
2166                                 for (i = level + 1; i <= max_level; i++)
2167                                         wm[i] = 0;
2168                                 break;
2169                         }
2170                 }
2171
2172                 /*
2173                  * WaWmMemoryReadLatency:skl
2174                  *
2175                  * punit doesn't take into account the read latency so we need
2176                  * to add 2us to the various latency levels we retrieve from the
2177                  * punit when level 0 response data us 0us.
2178                  */
2179                 if (wm[0] == 0) {
2180                         wm[0] += 2;
2181                         for (level = 1; level <= max_level; level++) {
2182                                 if (wm[level] == 0)
2183                                         break;
2184                                 wm[level] += 2;
2185                         }
2186                 }
2187
2188         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2189                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2190
2191                 wm[0] = (sskpd >> 56) & 0xFF;
2192                 if (wm[0] == 0)
2193                         wm[0] = sskpd & 0xF;
2194                 wm[1] = (sskpd >> 4) & 0xFF;
2195                 wm[2] = (sskpd >> 12) & 0xFF;
2196                 wm[3] = (sskpd >> 20) & 0x1FF;
2197                 wm[4] = (sskpd >> 32) & 0x1FF;
2198         } else if (INTEL_GEN(dev_priv) >= 6) {
2199                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2200
2201                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2202                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2203                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2204                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2205         } else if (INTEL_GEN(dev_priv) >= 5) {
2206                 uint32_t mltr = I915_READ(MLTR_ILK);
2207
2208                 /* ILK primary LP0 latency is 700 ns */
2209                 wm[0] = 7;
2210                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2211                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2212         }
2213 }
2214
2215 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2216                                        uint16_t wm[5])
2217 {
2218         /* ILK sprite LP0 latency is 1300 ns */
2219         if (IS_GEN5(dev_priv))
2220                 wm[0] = 13;
2221 }
2222
2223 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2224                                        uint16_t wm[5])
2225 {
2226         /* ILK cursor LP0 latency is 1300 ns */
2227         if (IS_GEN5(dev_priv))
2228                 wm[0] = 13;
2229
2230         /* WaDoubleCursorLP3Latency:ivb */
2231         if (IS_IVYBRIDGE(dev_priv))
2232                 wm[3] *= 2;
2233 }
2234
2235 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2236 {
2237         /* how many WM levels are we expecting */
2238         if (INTEL_GEN(dev_priv) >= 9)
2239                 return 7;
2240         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2241                 return 4;
2242         else if (INTEL_GEN(dev_priv) >= 6)
2243                 return 3;
2244         else
2245                 return 2;
2246 }
2247
2248 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2249                                    const char *name,
2250                                    const uint16_t wm[8])
2251 {
2252         int level, max_level = ilk_wm_max_level(dev_priv);
2253
2254         for (level = 0; level <= max_level; level++) {
2255                 unsigned int latency = wm[level];
2256
2257                 if (latency == 0) {
2258                         DRM_ERROR("%s WM%d latency not provided\n",
2259                                   name, level);
2260                         continue;
2261                 }
2262
2263                 /*
2264                  * - latencies are in us on gen9.
2265                  * - before then, WM1+ latency values are in 0.5us units
2266                  */
2267                 if (IS_GEN9(dev_priv))
2268                         latency *= 10;
2269                 else if (level > 0)
2270                         latency *= 5;
2271
2272                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2273                               name, level, wm[level],
2274                               latency / 10, latency % 10);
2275         }
2276 }
2277
2278 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2279                                     uint16_t wm[5], uint16_t min)
2280 {
2281         int level, max_level = ilk_wm_max_level(dev_priv);
2282
2283         if (wm[0] >= min)
2284                 return false;
2285
2286         wm[0] = max(wm[0], min);
2287         for (level = 1; level <= max_level; level++)
2288                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2289
2290         return true;
2291 }
2292
2293 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2294 {
2295         bool changed;
2296
2297         /*
2298          * The BIOS provided WM memory latency values are often
2299          * inadequate for high resolution displays. Adjust them.
2300          */
2301         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2302                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2303                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2304
2305         if (!changed)
2306                 return;
2307
2308         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2309         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2310         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2311         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2312 }
2313
2314 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2315 {
2316         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2317
2318         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2319                sizeof(dev_priv->wm.pri_latency));
2320         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2321                sizeof(dev_priv->wm.pri_latency));
2322
2323         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2324         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2325
2326         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2327         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2328         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2329
2330         if (IS_GEN6(dev_priv))
2331                 snb_wm_latency_quirk(dev_priv);
2332 }
2333
2334 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2335 {
2336         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2337         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2338 }
2339
2340 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2341                                  struct intel_pipe_wm *pipe_wm)
2342 {
2343         /* LP0 watermark maximums depend on this pipe alone */
2344         const struct intel_wm_config config = {
2345                 .num_pipes_active = 1,
2346                 .sprites_enabled = pipe_wm->sprites_enabled,
2347                 .sprites_scaled = pipe_wm->sprites_scaled,
2348         };
2349         struct ilk_wm_maximums max;
2350
2351         /* LP0 watermarks always use 1/2 DDB partitioning */
2352         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2353
2354         /* At least LP0 must be valid */
2355         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2356                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2357                 return false;
2358         }
2359
2360         return true;
2361 }
2362
2363 /* Compute new watermarks for the pipe */
2364 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2365 {
2366         struct drm_atomic_state *state = cstate->base.state;
2367         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2368         struct intel_pipe_wm *pipe_wm;
2369         struct drm_device *dev = state->dev;
2370         const struct drm_i915_private *dev_priv = to_i915(dev);
2371         struct intel_plane *intel_plane;
2372         struct intel_plane_state *pristate = NULL;
2373         struct intel_plane_state *sprstate = NULL;
2374         struct intel_plane_state *curstate = NULL;
2375         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2376         struct ilk_wm_maximums max;
2377
2378         pipe_wm = &cstate->wm.ilk.optimal;
2379
2380         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2381                 struct intel_plane_state *ps;
2382
2383                 ps = intel_atomic_get_existing_plane_state(state,
2384                                                            intel_plane);
2385                 if (!ps)
2386                         continue;
2387
2388                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2389                         pristate = ps;
2390                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2391                         sprstate = ps;
2392                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2393                         curstate = ps;
2394         }
2395
2396         pipe_wm->pipe_enabled = cstate->base.active;
2397         if (sprstate) {
2398                 pipe_wm->sprites_enabled = sprstate->base.visible;
2399                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2400                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2401                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2402         }
2403
2404         usable_level = max_level;
2405
2406         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2407         if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
2408                 usable_level = 1;
2409
2410         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2411         if (pipe_wm->sprites_scaled)
2412                 usable_level = 0;
2413
2414         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2415                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2416
2417         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2418         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2419
2420         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2421                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2422
2423         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2424                 return -EINVAL;
2425
2426         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
2427
2428         for (level = 1; level <= max_level; level++) {
2429                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2430
2431                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2432                                      pristate, sprstate, curstate, wm);
2433
2434                 /*
2435                  * Disable any watermark level that exceeds the
2436                  * register maximums since such watermarks are
2437                  * always invalid.
2438                  */
2439                 if (level > usable_level)
2440                         continue;
2441
2442                 if (ilk_validate_wm_level(level, &max, wm))
2443                         pipe_wm->wm[level] = *wm;
2444                 else
2445                         usable_level = level;
2446         }
2447
2448         return 0;
2449 }
2450
2451 /*
2452  * Build a set of 'intermediate' watermark values that satisfy both the old
2453  * state and the new state.  These can be programmed to the hardware
2454  * immediately.
2455  */
2456 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2457                                        struct intel_crtc *intel_crtc,
2458                                        struct intel_crtc_state *newstate)
2459 {
2460         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2461         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2462         int level, max_level = ilk_wm_max_level(to_i915(dev));
2463
2464         /*
2465          * Start with the final, target watermarks, then combine with the
2466          * currently active watermarks to get values that are safe both before
2467          * and after the vblank.
2468          */
2469         *a = newstate->wm.ilk.optimal;
2470         a->pipe_enabled |= b->pipe_enabled;
2471         a->sprites_enabled |= b->sprites_enabled;
2472         a->sprites_scaled |= b->sprites_scaled;
2473
2474         for (level = 0; level <= max_level; level++) {
2475                 struct intel_wm_level *a_wm = &a->wm[level];
2476                 const struct intel_wm_level *b_wm = &b->wm[level];
2477
2478                 a_wm->enable &= b_wm->enable;
2479                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2480                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2481                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2482                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2483         }
2484
2485         /*
2486          * We need to make sure that these merged watermark values are
2487          * actually a valid configuration themselves.  If they're not,
2488          * there's no safe way to transition from the old state to
2489          * the new state, so we need to fail the atomic transaction.
2490          */
2491         if (!ilk_validate_pipe_wm(dev, a))
2492                 return -EINVAL;
2493
2494         /*
2495          * If our intermediate WM are identical to the final WM, then we can
2496          * omit the post-vblank programming; only update if it's different.
2497          */
2498         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2499                 newstate->wm.need_postvbl_update = false;
2500
2501         return 0;
2502 }
2503
2504 /*
2505  * Merge the watermarks from all active pipes for a specific level.
2506  */
2507 static void ilk_merge_wm_level(struct drm_device *dev,
2508                                int level,
2509                                struct intel_wm_level *ret_wm)
2510 {
2511         const struct intel_crtc *intel_crtc;
2512
2513         ret_wm->enable = true;
2514
2515         for_each_intel_crtc(dev, intel_crtc) {
2516                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2517                 const struct intel_wm_level *wm = &active->wm[level];
2518
2519                 if (!active->pipe_enabled)
2520                         continue;
2521
2522                 /*
2523                  * The watermark values may have been used in the past,
2524                  * so we must maintain them in the registers for some
2525                  * time even if the level is now disabled.
2526                  */
2527                 if (!wm->enable)
2528                         ret_wm->enable = false;
2529
2530                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2531                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2532                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2533                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2534         }
2535 }
2536
2537 /*
2538  * Merge all low power watermarks for all active pipes.
2539  */
2540 static void ilk_wm_merge(struct drm_device *dev,
2541                          const struct intel_wm_config *config,
2542                          const struct ilk_wm_maximums *max,
2543                          struct intel_pipe_wm *merged)
2544 {
2545         struct drm_i915_private *dev_priv = to_i915(dev);
2546         int level, max_level = ilk_wm_max_level(dev_priv);
2547         int last_enabled_level = max_level;
2548
2549         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2550         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2551             config->num_pipes_active > 1)
2552                 last_enabled_level = 0;
2553
2554         /* ILK: FBC WM must be disabled always */
2555         merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
2556
2557         /* merge each WM1+ level */
2558         for (level = 1; level <= max_level; level++) {
2559                 struct intel_wm_level *wm = &merged->wm[level];
2560
2561                 ilk_merge_wm_level(dev, level, wm);
2562
2563                 if (level > last_enabled_level)
2564                         wm->enable = false;
2565                 else if (!ilk_validate_wm_level(level, max, wm))
2566                         /* make sure all following levels get disabled */
2567                         last_enabled_level = level - 1;
2568
2569                 /*
2570                  * The spec says it is preferred to disable
2571                  * FBC WMs instead of disabling a WM level.
2572                  */
2573                 if (wm->fbc_val > max->fbc) {
2574                         if (wm->enable)
2575                                 merged->fbc_wm_enabled = false;
2576                         wm->fbc_val = 0;
2577                 }
2578         }
2579
2580         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2581         /*
2582          * FIXME this is racy. FBC might get enabled later.
2583          * What we should check here is whether FBC can be
2584          * enabled sometime later.
2585          */
2586         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2587             intel_fbc_is_active(dev_priv)) {
2588                 for (level = 2; level <= max_level; level++) {
2589                         struct intel_wm_level *wm = &merged->wm[level];
2590
2591                         wm->enable = false;
2592                 }
2593         }
2594 }
2595
2596 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2597 {
2598         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2599         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2600 }
2601
2602 /* The value we need to program into the WM_LPx latency field */
2603 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2604 {
2605         struct drm_i915_private *dev_priv = to_i915(dev);
2606
2607         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2608                 return 2 * level;
2609         else
2610                 return dev_priv->wm.pri_latency[level];
2611 }
2612
2613 static void ilk_compute_wm_results(struct drm_device *dev,
2614                                    const struct intel_pipe_wm *merged,
2615                                    enum intel_ddb_partitioning partitioning,
2616                                    struct ilk_wm_values *results)
2617 {
2618         struct drm_i915_private *dev_priv = to_i915(dev);
2619         struct intel_crtc *intel_crtc;
2620         int level, wm_lp;
2621
2622         results->enable_fbc_wm = merged->fbc_wm_enabled;
2623         results->partitioning = partitioning;
2624
2625         /* LP1+ register values */
2626         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2627                 const struct intel_wm_level *r;
2628
2629                 level = ilk_wm_lp_to_level(wm_lp, merged);
2630
2631                 r = &merged->wm[level];
2632
2633                 /*
2634                  * Maintain the watermark values even if the level is
2635                  * disabled. Doing otherwise could cause underruns.
2636                  */
2637                 results->wm_lp[wm_lp - 1] =
2638                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2639                         (r->pri_val << WM1_LP_SR_SHIFT) |
2640                         r->cur_val;
2641
2642                 if (r->enable)
2643                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2644
2645                 if (INTEL_GEN(dev_priv) >= 8)
2646                         results->wm_lp[wm_lp - 1] |=
2647                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2648                 else
2649                         results->wm_lp[wm_lp - 1] |=
2650                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2651
2652                 /*
2653                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2654                  * level is disabled. Doing otherwise could cause underruns.
2655                  */
2656                 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
2657                         WARN_ON(wm_lp != 1);
2658                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2659                 } else
2660                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2661         }
2662
2663         /* LP0 register values */
2664         for_each_intel_crtc(dev, intel_crtc) {
2665                 enum pipe pipe = intel_crtc->pipe;
2666                 const struct intel_wm_level *r =
2667                         &intel_crtc->wm.active.ilk.wm[0];
2668
2669                 if (WARN_ON(!r->enable))
2670                         continue;
2671
2672                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2673
2674                 results->wm_pipe[pipe] =
2675                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2676                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2677                         r->cur_val;
2678         }
2679 }
2680
2681 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2682  * case both are at the same level. Prefer r1 in case they're the same. */
2683 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2684                                                   struct intel_pipe_wm *r1,
2685                                                   struct intel_pipe_wm *r2)
2686 {
2687         int level, max_level = ilk_wm_max_level(to_i915(dev));
2688         int level1 = 0, level2 = 0;
2689
2690         for (level = 1; level <= max_level; level++) {
2691                 if (r1->wm[level].enable)
2692                         level1 = level;
2693                 if (r2->wm[level].enable)
2694                         level2 = level;
2695         }
2696
2697         if (level1 == level2) {
2698                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2699                         return r2;
2700                 else
2701                         return r1;
2702         } else if (level1 > level2) {
2703                 return r1;
2704         } else {
2705                 return r2;
2706         }
2707 }
2708
2709 /* dirty bits used to track which watermarks need changes */
2710 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2711 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2712 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2713 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2714 #define WM_DIRTY_FBC (1 << 24)
2715 #define WM_DIRTY_DDB (1 << 25)
2716
2717 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2718                                          const struct ilk_wm_values *old,
2719                                          const struct ilk_wm_values *new)
2720 {
2721         unsigned int dirty = 0;
2722         enum pipe pipe;
2723         int wm_lp;
2724
2725         for_each_pipe(dev_priv, pipe) {
2726                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2727                         dirty |= WM_DIRTY_LINETIME(pipe);
2728                         /* Must disable LP1+ watermarks too */
2729                         dirty |= WM_DIRTY_LP_ALL;
2730                 }
2731
2732                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2733                         dirty |= WM_DIRTY_PIPE(pipe);
2734                         /* Must disable LP1+ watermarks too */
2735                         dirty |= WM_DIRTY_LP_ALL;
2736                 }
2737         }
2738
2739         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2740                 dirty |= WM_DIRTY_FBC;
2741                 /* Must disable LP1+ watermarks too */
2742                 dirty |= WM_DIRTY_LP_ALL;
2743         }
2744
2745         if (old->partitioning != new->partitioning) {
2746                 dirty |= WM_DIRTY_DDB;
2747                 /* Must disable LP1+ watermarks too */
2748                 dirty |= WM_DIRTY_LP_ALL;
2749         }
2750
2751         /* LP1+ watermarks already deemed dirty, no need to continue */
2752         if (dirty & WM_DIRTY_LP_ALL)
2753                 return dirty;
2754
2755         /* Find the lowest numbered LP1+ watermark in need of an update... */
2756         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2757                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2758                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2759                         break;
2760         }
2761
2762         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2763         for (; wm_lp <= 3; wm_lp++)
2764                 dirty |= WM_DIRTY_LP(wm_lp);
2765
2766         return dirty;
2767 }
2768
2769 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2770                                unsigned int dirty)
2771 {
2772         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2773         bool changed = false;
2774
2775         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2776                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2777                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2778                 changed = true;
2779         }
2780         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2781                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2782                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2783                 changed = true;
2784         }
2785         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2786                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2787                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2788                 changed = true;
2789         }
2790
2791         /*
2792          * Don't touch WM1S_LP_EN here.
2793          * Doing so could cause underruns.
2794          */
2795
2796         return changed;
2797 }
2798
2799 /*
2800  * The spec says we shouldn't write when we don't need, because every write
2801  * causes WMs to be re-evaluated, expending some power.
2802  */
2803 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2804                                 struct ilk_wm_values *results)
2805 {
2806         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2807         unsigned int dirty;
2808         uint32_t val;
2809
2810         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2811         if (!dirty)
2812                 return;
2813
2814         _ilk_disable_lp_wm(dev_priv, dirty);
2815
2816         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2817                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2818         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2819                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2820         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2821                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2822
2823         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2824                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2825         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2826                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2827         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2828                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2829
2830         if (dirty & WM_DIRTY_DDB) {
2831                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2832                         val = I915_READ(WM_MISC);
2833                         if (results->partitioning == INTEL_DDB_PART_1_2)
2834                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2835                         else
2836                                 val |= WM_MISC_DATA_PARTITION_5_6;
2837                         I915_WRITE(WM_MISC, val);
2838                 } else {
2839                         val = I915_READ(DISP_ARB_CTL2);
2840                         if (results->partitioning == INTEL_DDB_PART_1_2)
2841                                 val &= ~DISP_DATA_PARTITION_5_6;
2842                         else
2843                                 val |= DISP_DATA_PARTITION_5_6;
2844                         I915_WRITE(DISP_ARB_CTL2, val);
2845                 }
2846         }
2847
2848         if (dirty & WM_DIRTY_FBC) {
2849                 val = I915_READ(DISP_ARB_CTL);
2850                 if (results->enable_fbc_wm)
2851                         val &= ~DISP_FBC_WM_DIS;
2852                 else
2853                         val |= DISP_FBC_WM_DIS;
2854                 I915_WRITE(DISP_ARB_CTL, val);
2855         }
2856
2857         if (dirty & WM_DIRTY_LP(1) &&
2858             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2859                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2860
2861         if (INTEL_GEN(dev_priv) >= 7) {
2862                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2863                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2864                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2865                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2866         }
2867
2868         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2869                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2870         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2871                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2872         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2873                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2874
2875         dev_priv->wm.hw = *results;
2876 }
2877
2878 bool ilk_disable_lp_wm(struct drm_device *dev)
2879 {
2880         struct drm_i915_private *dev_priv = to_i915(dev);
2881
2882         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2883 }
2884
2885 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2886
2887 /*
2888  * FIXME: We still don't have the proper code detect if we need to apply the WA,
2889  * so assume we'll always need it in order to avoid underruns.
2890  */
2891 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2892 {
2893         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2894
2895         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2896             IS_KABYLAKE(dev_priv))
2897                 return true;
2898
2899         return false;
2900 }
2901
2902 static bool
2903 intel_has_sagv(struct drm_i915_private *dev_priv)
2904 {
2905         if (IS_KABYLAKE(dev_priv))
2906                 return true;
2907
2908         if (IS_SKYLAKE(dev_priv) &&
2909             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2910                 return true;
2911
2912         return false;
2913 }
2914
2915 /*
2916  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2917  * depending on power and performance requirements. The display engine access
2918  * to system memory is blocked during the adjustment time. Because of the
2919  * blocking time, having this enabled can cause full system hangs and/or pipe
2920  * underruns if we don't meet all of the following requirements:
2921  *
2922  *  - <= 1 pipe enabled
2923  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2924  *  - We're not using an interlaced display configuration
2925  */
2926 int
2927 intel_enable_sagv(struct drm_i915_private *dev_priv)
2928 {
2929         int ret;
2930
2931         if (!intel_has_sagv(dev_priv))
2932                 return 0;
2933
2934         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2935                 return 0;
2936
2937         DRM_DEBUG_KMS("Enabling the SAGV\n");
2938         mutex_lock(&dev_priv->rps.hw_lock);
2939
2940         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2941                                       GEN9_SAGV_ENABLE);
2942
2943         /* We don't need to wait for the SAGV when enabling */
2944         mutex_unlock(&dev_priv->rps.hw_lock);
2945
2946         /*
2947          * Some skl systems, pre-release machines in particular,
2948          * don't actually have an SAGV.
2949          */
2950         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2951                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2952                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2953                 return 0;
2954         } else if (ret < 0) {
2955                 DRM_ERROR("Failed to enable the SAGV\n");
2956                 return ret;
2957         }
2958
2959         dev_priv->sagv_status = I915_SAGV_ENABLED;
2960         return 0;
2961 }
2962
2963 int
2964 intel_disable_sagv(struct drm_i915_private *dev_priv)
2965 {
2966         int ret;
2967
2968         if (!intel_has_sagv(dev_priv))
2969                 return 0;
2970
2971         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2972                 return 0;
2973
2974         DRM_DEBUG_KMS("Disabling the SAGV\n");
2975         mutex_lock(&dev_priv->rps.hw_lock);
2976
2977         /* bspec says to keep retrying for at least 1 ms */
2978         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2979                                 GEN9_SAGV_DISABLE,
2980                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
2981                                 1);
2982         mutex_unlock(&dev_priv->rps.hw_lock);
2983
2984         /*
2985          * Some skl systems, pre-release machines in particular,
2986          * don't actually have an SAGV.
2987          */
2988         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2989                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2990                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2991                 return 0;
2992         } else if (ret < 0) {
2993                 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
2994                 return ret;
2995         }
2996
2997         dev_priv->sagv_status = I915_SAGV_DISABLED;
2998         return 0;
2999 }
3000
3001 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3002 {
3003         struct drm_device *dev = state->dev;
3004         struct drm_i915_private *dev_priv = to_i915(dev);
3005         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3006         struct intel_crtc *crtc;
3007         struct intel_plane *plane;
3008         struct intel_crtc_state *cstate;
3009         enum pipe pipe;
3010         int level, latency;
3011
3012         if (!intel_has_sagv(dev_priv))
3013                 return false;
3014
3015         /*
3016          * SKL workaround: bspec recommends we disable the SAGV when we have
3017          * more then one pipe enabled
3018          *
3019          * If there are no active CRTCs, no additional checks need be performed
3020          */
3021         if (hweight32(intel_state->active_crtcs) == 0)
3022                 return true;
3023         else if (hweight32(intel_state->active_crtcs) > 1)
3024                 return false;
3025
3026         /* Since we're now guaranteed to only have one active CRTC... */
3027         pipe = ffs(intel_state->active_crtcs) - 1;
3028         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3029         cstate = to_intel_crtc_state(crtc->base.state);
3030
3031         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3032                 return false;
3033
3034         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3035                 struct skl_plane_wm *wm =
3036                         &cstate->wm.skl.optimal.planes[plane->id];
3037
3038                 /* Skip this plane if it's not enabled */
3039                 if (!wm->wm[0].plane_en)
3040                         continue;
3041
3042                 /* Find the highest enabled wm level for this plane */
3043                 for (level = ilk_wm_max_level(dev_priv);
3044                      !wm->wm[level].plane_en; --level)
3045                      { }
3046
3047                 latency = dev_priv->wm.skl_latency[level];
3048
3049                 if (skl_needs_memory_bw_wa(intel_state) &&
3050                     plane->base.state->fb->modifier ==
3051                     I915_FORMAT_MOD_X_TILED)
3052                         latency += 15;
3053
3054                 /*
3055                  * If any of the planes on this pipe don't enable wm levels
3056                  * that incur memory latencies higher then 30µs we can't enable
3057                  * the SAGV
3058                  */
3059                 if (latency < SKL_SAGV_BLOCK_TIME)
3060                         return false;
3061         }
3062
3063         return true;
3064 }
3065
3066 static void
3067 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3068                                    const struct intel_crtc_state *cstate,
3069                                    struct skl_ddb_entry *alloc, /* out */
3070                                    int *num_active /* out */)
3071 {
3072         struct drm_atomic_state *state = cstate->base.state;
3073         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3074         struct drm_i915_private *dev_priv = to_i915(dev);
3075         struct drm_crtc *for_crtc = cstate->base.crtc;
3076         unsigned int pipe_size, ddb_size;
3077         int nth_active_pipe;
3078
3079         if (WARN_ON(!state) || !cstate->base.active) {
3080                 alloc->start = 0;
3081                 alloc->end = 0;
3082                 *num_active = hweight32(dev_priv->active_crtcs);
3083                 return;
3084         }
3085
3086         if (intel_state->active_pipe_changes)
3087                 *num_active = hweight32(intel_state->active_crtcs);
3088         else
3089                 *num_active = hweight32(dev_priv->active_crtcs);
3090
3091         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3092         WARN_ON(ddb_size == 0);
3093
3094         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3095
3096         /*
3097          * If the state doesn't change the active CRTC's, then there's
3098          * no need to recalculate; the existing pipe allocation limits
3099          * should remain unchanged.  Note that we're safe from racing
3100          * commits since any racing commit that changes the active CRTC
3101          * list would need to grab _all_ crtc locks, including the one
3102          * we currently hold.
3103          */
3104         if (!intel_state->active_pipe_changes) {
3105                 /*
3106                  * alloc may be cleared by clear_intel_crtc_state,
3107                  * copy from old state to be sure
3108                  */
3109                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3110                 return;
3111         }
3112
3113         nth_active_pipe = hweight32(intel_state->active_crtcs &
3114                                     (drm_crtc_mask(for_crtc) - 1));
3115         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3116         alloc->start = nth_active_pipe * ddb_size / *num_active;
3117         alloc->end = alloc->start + pipe_size;
3118 }
3119
3120 static unsigned int skl_cursor_allocation(int num_active)
3121 {
3122         if (num_active == 1)
3123                 return 32;
3124
3125         return 8;
3126 }
3127
3128 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3129 {
3130         entry->start = reg & 0x3ff;
3131         entry->end = (reg >> 16) & 0x3ff;
3132         if (entry->end)
3133                 entry->end += 1;
3134 }
3135
3136 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3137                           struct skl_ddb_allocation *ddb /* out */)
3138 {
3139         struct intel_crtc *crtc;
3140
3141         memset(ddb, 0, sizeof(*ddb));
3142
3143         for_each_intel_crtc(&dev_priv->drm, crtc) {
3144                 enum intel_display_power_domain power_domain;
3145                 enum plane_id plane_id;
3146                 enum pipe pipe = crtc->pipe;
3147
3148                 power_domain = POWER_DOMAIN_PIPE(pipe);
3149                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3150                         continue;
3151
3152                 for_each_plane_id_on_crtc(crtc, plane_id) {
3153                         u32 val;
3154
3155                         if (plane_id != PLANE_CURSOR)
3156                                 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3157                         else
3158                                 val = I915_READ(CUR_BUF_CFG(pipe));
3159
3160                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3161                 }
3162
3163                 intel_display_power_put(dev_priv, power_domain);
3164         }
3165 }
3166
3167 /*
3168  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3169  * The bspec defines downscale amount as:
3170  *
3171  * """
3172  * Horizontal down scale amount = maximum[1, Horizontal source size /
3173  *                                           Horizontal destination size]
3174  * Vertical down scale amount = maximum[1, Vertical source size /
3175  *                                         Vertical destination size]
3176  * Total down scale amount = Horizontal down scale amount *
3177  *                           Vertical down scale amount
3178  * """
3179  *
3180  * Return value is provided in 16.16 fixed point form to retain fractional part.
3181  * Caller should take care of dividing & rounding off the value.
3182  */
3183 static uint32_t
3184 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3185 {
3186         uint32_t downscale_h, downscale_w;
3187         uint32_t src_w, src_h, dst_w, dst_h;
3188
3189         if (WARN_ON(!pstate->base.visible))
3190                 return DRM_PLANE_HELPER_NO_SCALING;
3191
3192         /* n.b., src is 16.16 fixed point, dst is whole integer */
3193         src_w = drm_rect_width(&pstate->base.src);
3194         src_h = drm_rect_height(&pstate->base.src);
3195         dst_w = drm_rect_width(&pstate->base.dst);
3196         dst_h = drm_rect_height(&pstate->base.dst);
3197         if (drm_rotation_90_or_270(pstate->base.rotation))
3198                 swap(dst_w, dst_h);
3199
3200         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3201         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3202
3203         /* Provide result in 16.16 fixed point */
3204         return (uint64_t)downscale_w * downscale_h >> 16;
3205 }
3206
3207 static unsigned int
3208 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3209                              const struct drm_plane_state *pstate,
3210                              int y)
3211 {
3212         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3213         struct drm_framebuffer *fb = pstate->fb;
3214         uint32_t down_scale_amount, data_rate;
3215         uint32_t width = 0, height = 0;
3216         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3217
3218         if (!intel_pstate->base.visible)
3219                 return 0;
3220         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3221                 return 0;
3222         if (y && format != DRM_FORMAT_NV12)
3223                 return 0;
3224
3225         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3226         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3227
3228         if (drm_rotation_90_or_270(pstate->rotation))
3229                 swap(width, height);
3230
3231         /* for planar format */
3232         if (format == DRM_FORMAT_NV12) {
3233                 if (y)  /* y-plane data rate */
3234                         data_rate = width * height *
3235                                 drm_format_plane_cpp(format, 0);
3236                 else    /* uv-plane data rate */
3237                         data_rate = (width / 2) * (height / 2) *
3238                                 drm_format_plane_cpp(format, 1);
3239         } else {
3240                 /* for packed formats */
3241                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3242         }
3243
3244         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3245
3246         return (uint64_t)data_rate * down_scale_amount >> 16;
3247 }
3248
3249 /*
3250  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3251  * a 8192x4096@32bpp framebuffer:
3252  *   3 * 4096 * 8192  * 4 < 2^32
3253  */
3254 static unsigned int
3255 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3256                                  unsigned *plane_data_rate,
3257                                  unsigned *plane_y_data_rate)
3258 {
3259         struct drm_crtc_state *cstate = &intel_cstate->base;
3260         struct drm_atomic_state *state = cstate->state;
3261         struct drm_plane *plane;
3262         const struct drm_plane_state *pstate;
3263         unsigned int total_data_rate = 0;
3264
3265         if (WARN_ON(!state))
3266                 return 0;
3267
3268         /* Calculate and cache data rate for each plane */
3269         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3270                 enum plane_id plane_id = to_intel_plane(plane)->id;
3271                 unsigned int rate;
3272
3273                 /* packed/uv */
3274                 rate = skl_plane_relative_data_rate(intel_cstate,
3275                                                     pstate, 0);
3276                 plane_data_rate[plane_id] = rate;
3277
3278                 total_data_rate += rate;
3279
3280                 /* y-plane */
3281                 rate = skl_plane_relative_data_rate(intel_cstate,
3282                                                     pstate, 1);
3283                 plane_y_data_rate[plane_id] = rate;
3284
3285                 total_data_rate += rate;
3286         }
3287
3288         return total_data_rate;
3289 }
3290
3291 static uint16_t
3292 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3293                   const int y)
3294 {
3295         struct drm_framebuffer *fb = pstate->fb;
3296         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3297         uint32_t src_w, src_h;
3298         uint32_t min_scanlines = 8;
3299         uint8_t plane_bpp;
3300
3301         if (WARN_ON(!fb))
3302                 return 0;
3303
3304         /* For packed formats, no y-plane, return 0 */
3305         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3306                 return 0;
3307
3308         /* For Non Y-tile return 8-blocks */
3309         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3310             fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3311                 return 8;
3312
3313         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3314         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3315
3316         if (drm_rotation_90_or_270(pstate->rotation))
3317                 swap(src_w, src_h);
3318
3319         /* Halve UV plane width and height for NV12 */
3320         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3321                 src_w /= 2;
3322                 src_h /= 2;
3323         }
3324
3325         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3326                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3327         else
3328                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3329
3330         if (drm_rotation_90_or_270(pstate->rotation)) {
3331                 switch (plane_bpp) {
3332                 case 1:
3333                         min_scanlines = 32;
3334                         break;
3335                 case 2:
3336                         min_scanlines = 16;
3337                         break;
3338                 case 4:
3339                         min_scanlines = 8;
3340                         break;
3341                 case 8:
3342                         min_scanlines = 4;
3343                         break;
3344                 default:
3345                         WARN(1, "Unsupported pixel depth %u for rotation",
3346                              plane_bpp);
3347                         min_scanlines = 32;
3348                 }
3349         }
3350
3351         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3352 }
3353
3354 static void
3355 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3356                  uint16_t *minimum, uint16_t *y_minimum)
3357 {
3358         const struct drm_plane_state *pstate;
3359         struct drm_plane *plane;
3360
3361         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3362                 enum plane_id plane_id = to_intel_plane(plane)->id;
3363
3364                 if (plane_id == PLANE_CURSOR)
3365                         continue;
3366
3367                 if (!pstate->visible)
3368                         continue;
3369
3370                 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
3371                 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
3372         }
3373
3374         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3375 }
3376
3377 static int
3378 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3379                       struct skl_ddb_allocation *ddb /* out */)
3380 {
3381         struct drm_atomic_state *state = cstate->base.state;
3382         struct drm_crtc *crtc = cstate->base.crtc;
3383         struct drm_device *dev = crtc->dev;
3384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3385         enum pipe pipe = intel_crtc->pipe;
3386         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3387         uint16_t alloc_size, start;
3388         uint16_t minimum[I915_MAX_PLANES] = {};
3389         uint16_t y_minimum[I915_MAX_PLANES] = {};
3390         unsigned int total_data_rate;
3391         enum plane_id plane_id;
3392         int num_active;
3393         unsigned plane_data_rate[I915_MAX_PLANES] = {};
3394         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3395
3396         /* Clear the partitioning for disabled planes. */
3397         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3398         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3399
3400         if (WARN_ON(!state))
3401                 return 0;
3402
3403         if (!cstate->base.active) {
3404                 alloc->start = alloc->end = 0;
3405                 return 0;
3406         }
3407
3408         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3409         alloc_size = skl_ddb_entry_size(alloc);
3410         if (alloc_size == 0) {
3411                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3412                 return 0;
3413         }
3414
3415         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3416
3417         /*
3418          * 1. Allocate the mininum required blocks for each active plane
3419          * and allocate the cursor, it doesn't require extra allocation
3420          * proportional to the data rate.
3421          */
3422
3423         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3424                 alloc_size -= minimum[plane_id];
3425                 alloc_size -= y_minimum[plane_id];
3426         }
3427
3428         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3429         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3430
3431         /*
3432          * 2. Distribute the remaining space in proportion to the amount of
3433          * data each plane needs to fetch from memory.
3434          *
3435          * FIXME: we may not allocate every single block here.
3436          */
3437         total_data_rate = skl_get_total_relative_data_rate(cstate,
3438                                                            plane_data_rate,
3439                                                            plane_y_data_rate);
3440         if (total_data_rate == 0)
3441                 return 0;
3442
3443         start = alloc->start;
3444         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3445                 unsigned int data_rate, y_data_rate;
3446                 uint16_t plane_blocks, y_plane_blocks = 0;
3447
3448                 if (plane_id == PLANE_CURSOR)
3449                         continue;
3450
3451                 data_rate = plane_data_rate[plane_id];
3452
3453                 /*
3454                  * allocation for (packed formats) or (uv-plane part of planar format):
3455                  * promote the expression to 64 bits to avoid overflowing, the
3456                  * result is < available as data_rate / total_data_rate < 1
3457                  */
3458                 plane_blocks = minimum[plane_id];
3459                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3460                                         total_data_rate);
3461
3462                 /* Leave disabled planes at (0,0) */
3463                 if (data_rate) {
3464                         ddb->plane[pipe][plane_id].start = start;
3465                         ddb->plane[pipe][plane_id].end = start + plane_blocks;
3466                 }
3467
3468                 start += plane_blocks;
3469
3470                 /*
3471                  * allocation for y_plane part of planar format:
3472                  */
3473                 y_data_rate = plane_y_data_rate[plane_id];
3474
3475                 y_plane_blocks = y_minimum[plane_id];
3476                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3477                                         total_data_rate);
3478
3479                 if (y_data_rate) {
3480                         ddb->y_plane[pipe][plane_id].start = start;
3481                         ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
3482                 }
3483
3484                 start += y_plane_blocks;
3485         }
3486
3487         return 0;
3488 }
3489
3490 /*
3491  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3492  * for the read latency) and cpp should always be <= 8, so that
3493  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3494  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3495 */
3496 static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
3497                                          uint32_t latency)
3498 {
3499         uint32_t wm_intermediate_val;
3500         uint_fixed_16_16_t ret;
3501
3502         if (latency == 0)
3503                 return FP_16_16_MAX;
3504
3505         wm_intermediate_val = latency * pixel_rate * cpp;
3506         ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512);
3507         return ret;
3508 }
3509
3510 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
3511                         uint32_t pipe_htotal,
3512                         uint32_t latency,
3513                         uint_fixed_16_16_t plane_blocks_per_line)
3514 {
3515         uint32_t wm_intermediate_val;
3516         uint_fixed_16_16_t ret;
3517
3518         if (latency == 0)
3519                 return FP_16_16_MAX;
3520
3521         wm_intermediate_val = latency * pixel_rate;
3522         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
3523                                            pipe_htotal * 1000);
3524         ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line);
3525         return ret;
3526 }
3527
3528 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3529                                               struct intel_plane_state *pstate)
3530 {
3531         uint64_t adjusted_pixel_rate;
3532         uint64_t downscale_amount;
3533         uint64_t pixel_rate;
3534
3535         /* Shouldn't reach here on disabled planes... */
3536         if (WARN_ON(!pstate->base.visible))
3537                 return 0;
3538
3539         /*
3540          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3541          * with additional adjustments for plane-specific scaling.
3542          */
3543         adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3544         downscale_amount = skl_plane_downscale_amount(pstate);
3545
3546         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3547         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3548
3549         return pixel_rate;
3550 }
3551
3552 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3553                                 struct intel_crtc_state *cstate,
3554                                 struct intel_plane_state *intel_pstate,
3555                                 uint16_t ddb_allocation,
3556                                 int level,
3557                                 uint16_t *out_blocks, /* out */
3558                                 uint8_t *out_lines, /* out */
3559                                 bool *enabled /* out */)
3560 {
3561         struct drm_plane_state *pstate = &intel_pstate->base;
3562         struct drm_framebuffer *fb = pstate->fb;
3563         uint32_t latency = dev_priv->wm.skl_latency[level];
3564         uint_fixed_16_16_t method1, method2;
3565         uint_fixed_16_16_t plane_blocks_per_line;
3566         uint_fixed_16_16_t selected_result;
3567         uint32_t interm_pbpl;
3568         uint32_t plane_bytes_per_line;
3569         uint32_t res_blocks, res_lines;
3570         uint8_t cpp;
3571         uint32_t width = 0, height = 0;
3572         uint32_t plane_pixel_rate;
3573         uint_fixed_16_16_t y_tile_minimum;
3574         uint32_t y_min_scanlines;
3575         struct intel_atomic_state *state =
3576                 to_intel_atomic_state(cstate->base.state);
3577         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3578         bool y_tiled, x_tiled;
3579
3580         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3581                 *enabled = false;
3582                 return 0;
3583         }
3584
3585         y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3586                   fb->modifier == I915_FORMAT_MOD_Yf_TILED;
3587         x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
3588
3589         /* Display WA #1141: kbl. */
3590         if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
3591                 latency += 4;
3592
3593         if (apply_memory_bw_wa && x_tiled)
3594                 latency += 15;
3595
3596         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3597         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3598
3599         if (drm_rotation_90_or_270(pstate->rotation))
3600                 swap(width, height);
3601
3602         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3603         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3604
3605         if (drm_rotation_90_or_270(pstate->rotation)) {
3606                 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3607                         drm_format_plane_cpp(fb->pixel_format, 1) :
3608                         drm_format_plane_cpp(fb->pixel_format, 0);
3609
3610                 switch (cpp) {
3611                 case 1:
3612                         y_min_scanlines = 16;
3613                         break;
3614                 case 2:
3615                         y_min_scanlines = 8;
3616                         break;
3617                 case 4:
3618                         y_min_scanlines = 4;
3619                         break;
3620                 default:
3621                         MISSING_CASE(cpp);
3622                         return -EINVAL;
3623                 }
3624         } else {
3625                 y_min_scanlines = 4;
3626         }
3627
3628         if (apply_memory_bw_wa)
3629                 y_min_scanlines *= 2;
3630
3631         plane_bytes_per_line = width * cpp;
3632         if (y_tiled) {
3633                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
3634                                            y_min_scanlines, 512);
3635                 plane_blocks_per_line =
3636                       fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines);
3637         } else if (x_tiled) {
3638                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
3639                 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
3640         } else {
3641                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
3642                 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
3643         }
3644
3645         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3646         method2 = skl_wm_method2(plane_pixel_rate,
3647                                  cstate->base.adjusted_mode.crtc_htotal,
3648                                  latency,
3649                                  plane_blocks_per_line);
3650
3651         y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines,
3652                                              plane_blocks_per_line);
3653
3654         if (y_tiled) {
3655                 selected_result = max_fixed_16_16(method2, y_tile_minimum);
3656         } else {
3657                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3658                     (plane_bytes_per_line / 512 < 1))
3659                         selected_result = method2;
3660                 else if ((ddb_allocation /
3661                         fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
3662                         selected_result = min_fixed_16_16(method1, method2);
3663                 else
3664                         selected_result = method1;
3665         }
3666
3667         res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1;
3668         res_lines = DIV_ROUND_UP(selected_result.val,
3669                                  plane_blocks_per_line.val);
3670
3671         if (level >= 1 && level <= 7) {
3672                 if (y_tiled) {
3673                         res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
3674                         res_lines += y_min_scanlines;
3675                 } else {
3676                         res_blocks++;
3677                 }
3678         }
3679
3680         if (res_blocks >= ddb_allocation || res_lines > 31) {
3681                 *enabled = false;
3682
3683                 /*
3684                  * If there are no valid level 0 watermarks, then we can't
3685                  * support this display configuration.
3686                  */
3687                 if (level) {
3688                         return 0;
3689                 } else {
3690                         struct drm_plane *plane = pstate->plane;
3691
3692                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3693                         DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
3694                                       plane->base.id, plane->name,
3695                                       res_blocks, ddb_allocation, res_lines);
3696                         return -EINVAL;
3697                 }
3698         }
3699
3700         *out_blocks = res_blocks;
3701         *out_lines = res_lines;
3702         *enabled = true;
3703
3704         return 0;
3705 }
3706
3707 static int
3708 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3709                      struct skl_ddb_allocation *ddb,
3710                      struct intel_crtc_state *cstate,
3711                      struct intel_plane *intel_plane,
3712                      int level,
3713                      struct skl_wm_level *result)
3714 {
3715         struct drm_atomic_state *state = cstate->base.state;
3716         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3717         struct drm_plane *plane = &intel_plane->base;
3718         struct intel_plane_state *intel_pstate = NULL;
3719         uint16_t ddb_blocks;
3720         enum pipe pipe = intel_crtc->pipe;
3721         int ret;
3722
3723         if (state)
3724                 intel_pstate =
3725                         intel_atomic_get_existing_plane_state(state,
3726                                                               intel_plane);
3727
3728         /*
3729          * Note: If we start supporting multiple pending atomic commits against
3730          * the same planes/CRTC's in the future, plane->state will no longer be
3731          * the correct pre-state to use for the calculations here and we'll
3732          * need to change where we get the 'unchanged' plane data from.
3733          *
3734          * For now this is fine because we only allow one queued commit against
3735          * a CRTC.  Even if the plane isn't modified by this transaction and we
3736          * don't have a plane lock, we still have the CRTC's lock, so we know
3737          * that no other transactions are racing with us to update it.
3738          */
3739         if (!intel_pstate)
3740                 intel_pstate = to_intel_plane_state(plane->state);
3741
3742         WARN_ON(!intel_pstate->base.fb);
3743
3744         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
3745
3746         ret = skl_compute_plane_wm(dev_priv,
3747                                    cstate,
3748                                    intel_pstate,
3749                                    ddb_blocks,
3750                                    level,
3751                                    &result->plane_res_b,
3752                                    &result->plane_res_l,
3753                                    &result->plane_en);
3754         if (ret)
3755                 return ret;
3756
3757         return 0;
3758 }
3759
3760 static uint32_t
3761 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3762 {
3763         struct drm_atomic_state *state = cstate->base.state;
3764         struct drm_i915_private *dev_priv = to_i915(state->dev);
3765         uint32_t pixel_rate;
3766         uint32_t linetime_wm;
3767
3768         if (!cstate->base.active)
3769                 return 0;
3770
3771         pixel_rate = ilk_pipe_pixel_rate(cstate);
3772
3773         if (WARN_ON(pixel_rate == 0))
3774                 return 0;
3775
3776         linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
3777                                    1000, pixel_rate);
3778
3779         /* Display WA #1135: bxt. */
3780         if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
3781                 linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
3782
3783         return linetime_wm;
3784 }
3785
3786 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3787                                       struct skl_wm_level *trans_wm /* out */)
3788 {
3789         if (!cstate->base.active)
3790                 return;
3791
3792         /* Until we know more, just disable transition WMs */
3793         trans_wm->plane_en = false;
3794 }
3795
3796 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3797                              struct skl_ddb_allocation *ddb,
3798                              struct skl_pipe_wm *pipe_wm)
3799 {
3800         struct drm_device *dev = cstate->base.crtc->dev;
3801         const struct drm_i915_private *dev_priv = to_i915(dev);
3802         struct intel_plane *intel_plane;
3803         struct skl_plane_wm *wm;
3804         int level, max_level = ilk_wm_max_level(dev_priv);
3805         int ret;
3806
3807         /*
3808          * We'll only calculate watermarks for planes that are actually
3809          * enabled, so make sure all other planes are set as disabled.
3810          */
3811         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3812
3813         for_each_intel_plane_mask(&dev_priv->drm,
3814                                   intel_plane,
3815                                   cstate->base.plane_mask) {
3816                 wm = &pipe_wm->planes[intel_plane->id];
3817
3818                 for (level = 0; level <= max_level; level++) {
3819                         ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3820                                                    intel_plane, level,
3821                                                    &wm->wm[level]);
3822                         if (ret)
3823                                 return ret;
3824                 }
3825                 skl_compute_transition_wm(cstate, &wm->trans_wm);
3826         }
3827         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3828
3829         return 0;
3830 }
3831
3832 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3833                                 i915_reg_t reg,
3834                                 const struct skl_ddb_entry *entry)
3835 {
3836         if (entry->end)
3837                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3838         else
3839                 I915_WRITE(reg, 0);
3840 }
3841
3842 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3843                                i915_reg_t reg,
3844                                const struct skl_wm_level *level)
3845 {
3846         uint32_t val = 0;
3847
3848         if (level->plane_en) {
3849                 val |= PLANE_WM_EN;
3850                 val |= level->plane_res_b;
3851                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3852         }
3853
3854         I915_WRITE(reg, val);
3855 }
3856
3857 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3858                                const struct skl_plane_wm *wm,
3859                                const struct skl_ddb_allocation *ddb,
3860                                enum plane_id plane_id)
3861 {
3862         struct drm_crtc *crtc = &intel_crtc->base;
3863         struct drm_device *dev = crtc->dev;
3864         struct drm_i915_private *dev_priv = to_i915(dev);
3865         int level, max_level = ilk_wm_max_level(dev_priv);
3866         enum pipe pipe = intel_crtc->pipe;
3867
3868         for (level = 0; level <= max_level; level++) {
3869                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
3870                                    &wm->wm[level]);
3871         }
3872         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
3873                            &wm->trans_wm);
3874
3875         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
3876                             &ddb->plane[pipe][plane_id]);
3877         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
3878                             &ddb->y_plane[pipe][plane_id]);
3879 }
3880
3881 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3882                                 const struct skl_plane_wm *wm,
3883                                 const struct skl_ddb_allocation *ddb)
3884 {
3885         struct drm_crtc *crtc = &intel_crtc->base;
3886         struct drm_device *dev = crtc->dev;
3887         struct drm_i915_private *dev_priv = to_i915(dev);
3888         int level, max_level = ilk_wm_max_level(dev_priv);
3889         enum pipe pipe = intel_crtc->pipe;
3890
3891         for (level = 0; level <= max_level; level++) {
3892                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3893                                    &wm->wm[level]);
3894         }
3895         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3896
3897         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3898                             &ddb->plane[pipe][PLANE_CURSOR]);
3899 }
3900
3901 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3902                          const struct skl_wm_level *l2)
3903 {
3904         if (l1->plane_en != l2->plane_en)
3905                 return false;
3906
3907         /* If both planes aren't enabled, the rest shouldn't matter */
3908         if (!l1->plane_en)
3909                 return true;
3910
3911         return (l1->plane_res_l == l2->plane_res_l &&
3912                 l1->plane_res_b == l2->plane_res_b);
3913 }
3914
3915 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3916                                            const struct skl_ddb_entry *b)
3917 {
3918         return a->start < b->end && b->start < a->end;
3919 }
3920
3921 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3922                                  const struct skl_ddb_entry *ddb,
3923                                  int ignore)
3924 {
3925         int i;
3926
3927         for (i = 0; i < I915_MAX_PIPES; i++)
3928                 if (i != ignore && entries[i] &&
3929                     skl_ddb_entries_overlap(ddb, entries[i]))
3930                         return true;
3931
3932         return false;
3933 }
3934
3935 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3936                               const struct skl_pipe_wm *old_pipe_wm,
3937                               struct skl_pipe_wm *pipe_wm, /* out */
3938                               struct skl_ddb_allocation *ddb, /* out */
3939                               bool *changed /* out */)
3940 {
3941         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3942         int ret;
3943
3944         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3945         if (ret)
3946                 return ret;
3947
3948         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
3949                 *changed = false;
3950         else
3951                 *changed = true;
3952
3953         return 0;
3954 }
3955
3956 static uint32_t
3957 pipes_modified(struct drm_atomic_state *state)
3958 {
3959         struct drm_crtc *crtc;
3960         struct drm_crtc_state *cstate;
3961         uint32_t i, ret = 0;
3962
3963         for_each_crtc_in_state(state, crtc, cstate, i)
3964                 ret |= drm_crtc_mask(crtc);
3965
3966         return ret;
3967 }
3968
3969 static int
3970 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3971 {
3972         struct drm_atomic_state *state = cstate->base.state;
3973         struct drm_device *dev = state->dev;
3974         struct drm_crtc *crtc = cstate->base.crtc;
3975         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3976         struct drm_i915_private *dev_priv = to_i915(dev);
3977         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3978         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3979         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3980         struct drm_plane_state *plane_state;
3981         struct drm_plane *plane;
3982         enum pipe pipe = intel_crtc->pipe;
3983
3984         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3985
3986         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3987                 enum plane_id plane_id = to_intel_plane(plane)->id;
3988
3989                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
3990                                         &new_ddb->plane[pipe][plane_id]) &&
3991                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
3992                                         &new_ddb->y_plane[pipe][plane_id]))
3993                         continue;
3994
3995                 plane_state = drm_atomic_get_plane_state(state, plane);
3996                 if (IS_ERR(plane_state))
3997                         return PTR_ERR(plane_state);
3998         }
3999
4000         return 0;
4001 }
4002
4003 static int
4004 skl_compute_ddb(struct drm_atomic_state *state)
4005 {
4006         struct drm_device *dev = state->dev;
4007         struct drm_i915_private *dev_priv = to_i915(dev);
4008         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4009         struct intel_crtc *intel_crtc;
4010         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4011         uint32_t realloc_pipes = pipes_modified(state);
4012         int ret;
4013
4014         /*
4015          * If this is our first atomic update following hardware readout,
4016          * we can't trust the DDB that the BIOS programmed for us.  Let's
4017          * pretend that all pipes switched active status so that we'll
4018          * ensure a full DDB recompute.
4019          */
4020         if (dev_priv->wm.distrust_bios_wm) {
4021                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4022                                        state->acquire_ctx);
4023                 if (ret)
4024                         return ret;
4025
4026                 intel_state->active_pipe_changes = ~0;
4027
4028                 /*
4029                  * We usually only initialize intel_state->active_crtcs if we
4030                  * we're doing a modeset; make sure this field is always
4031                  * initialized during the sanitization process that happens
4032                  * on the first commit too.
4033                  */
4034                 if (!intel_state->modeset)
4035                         intel_state->active_crtcs = dev_priv->active_crtcs;
4036         }
4037
4038         /*
4039          * If the modeset changes which CRTC's are active, we need to
4040          * recompute the DDB allocation for *all* active pipes, even
4041          * those that weren't otherwise being modified in any way by this
4042          * atomic commit.  Due to the shrinking of the per-pipe allocations
4043          * when new active CRTC's are added, it's possible for a pipe that
4044          * we were already using and aren't changing at all here to suddenly
4045          * become invalid if its DDB needs exceeds its new allocation.
4046          *
4047          * Note that if we wind up doing a full DDB recompute, we can't let
4048          * any other display updates race with this transaction, so we need
4049          * to grab the lock on *all* CRTC's.
4050          */
4051         if (intel_state->active_pipe_changes) {
4052                 realloc_pipes = ~0;
4053                 intel_state->wm_results.dirty_pipes = ~0;
4054         }
4055
4056         /*
4057          * We're not recomputing for the pipes not included in the commit, so
4058          * make sure we start with the current state.
4059          */
4060         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4061
4062         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4063                 struct intel_crtc_state *cstate;
4064
4065                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4066                 if (IS_ERR(cstate))
4067                         return PTR_ERR(cstate);
4068
4069                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4070                 if (ret)
4071                         return ret;
4072
4073                 ret = skl_ddb_add_affected_planes(cstate);
4074                 if (ret)
4075                         return ret;
4076         }
4077
4078         return 0;
4079 }
4080
4081 static void
4082 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4083                      struct skl_wm_values *src,
4084                      enum pipe pipe)
4085 {
4086         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4087                sizeof(dst->ddb.y_plane[pipe]));
4088         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4089                sizeof(dst->ddb.plane[pipe]));
4090 }
4091
4092 static void
4093 skl_print_wm_changes(const struct drm_atomic_state *state)
4094 {
4095         const struct drm_device *dev = state->dev;
4096         const struct drm_i915_private *dev_priv = to_i915(dev);
4097         const struct intel_atomic_state *intel_state =
4098                 to_intel_atomic_state(state);
4099         const struct drm_crtc *crtc;
4100         const struct drm_crtc_state *cstate;
4101         const struct intel_plane *intel_plane;
4102         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4103         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4104         int i;
4105
4106         for_each_crtc_in_state(state, crtc, cstate, i) {
4107                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4108                 enum pipe pipe = intel_crtc->pipe;
4109
4110                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4111                         enum plane_id plane_id = intel_plane->id;
4112                         const struct skl_ddb_entry *old, *new;
4113
4114                         old = &old_ddb->plane[pipe][plane_id];
4115                         new = &new_ddb->plane[pipe][plane_id];
4116
4117                         if (skl_ddb_entry_equal(old, new))
4118                                 continue;
4119
4120                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4121                                          intel_plane->base.base.id,
4122                                          intel_plane->base.name,
4123                                          old->start, old->end,
4124                                          new->start, new->end);
4125                 }
4126         }
4127 }
4128
4129 static int
4130 skl_compute_wm(struct drm_atomic_state *state)
4131 {
4132         struct drm_crtc *crtc;
4133         struct drm_crtc_state *cstate;
4134         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4135         struct skl_wm_values *results = &intel_state->wm_results;
4136         struct skl_pipe_wm *pipe_wm;
4137         bool changed = false;
4138         int ret, i;
4139
4140         /*
4141          * If this transaction isn't actually touching any CRTC's, don't
4142          * bother with watermark calculation.  Note that if we pass this
4143          * test, we're guaranteed to hold at least one CRTC state mutex,
4144          * which means we can safely use values like dev_priv->active_crtcs
4145          * since any racing commits that want to update them would need to
4146          * hold _all_ CRTC state mutexes.
4147          */
4148         for_each_crtc_in_state(state, crtc, cstate, i)
4149                 changed = true;
4150         if (!changed)
4151                 return 0;
4152
4153         /* Clear all dirty flags */
4154         results->dirty_pipes = 0;
4155
4156         ret = skl_compute_ddb(state);
4157         if (ret)
4158                 return ret;
4159
4160         /*
4161          * Calculate WM's for all pipes that are part of this transaction.
4162          * Note that the DDB allocation above may have added more CRTC's that
4163          * weren't otherwise being modified (and set bits in dirty_pipes) if
4164          * pipe allocations had to change.
4165          *
4166          * FIXME:  Now that we're doing this in the atomic check phase, we
4167          * should allow skl_update_pipe_wm() to return failure in cases where
4168          * no suitable watermark values can be found.
4169          */
4170         for_each_crtc_in_state(state, crtc, cstate, i) {
4171                 struct intel_crtc_state *intel_cstate =
4172                         to_intel_crtc_state(cstate);
4173                 const struct skl_pipe_wm *old_pipe_wm =
4174                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4175
4176                 pipe_wm = &intel_cstate->wm.skl.optimal;
4177                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4178                                          &results->ddb, &changed);
4179                 if (ret)
4180                         return ret;
4181
4182                 if (changed)
4183                         results->dirty_pipes |= drm_crtc_mask(crtc);
4184
4185                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4186                         /* This pipe's WM's did not change */
4187                         continue;
4188
4189                 intel_cstate->update_wm_pre = true;
4190         }
4191
4192         skl_print_wm_changes(state);
4193
4194         return 0;
4195 }
4196
4197 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4198                                       struct intel_crtc_state *cstate)
4199 {
4200         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4201         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4202         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4203         const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
4204         enum pipe pipe = crtc->pipe;
4205         enum plane_id plane_id;
4206
4207         if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4208                 return;
4209
4210         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
4211
4212         for_each_plane_id_on_crtc(crtc, plane_id) {
4213                 if (plane_id != PLANE_CURSOR)
4214                         skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
4215                                            ddb, plane_id);
4216                 else
4217                         skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
4218                                             ddb);
4219         }
4220 }
4221
4222 static void skl_initial_wm(struct intel_atomic_state *state,
4223                            struct intel_crtc_state *cstate)
4224 {
4225         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4226         struct drm_device *dev = intel_crtc->base.dev;
4227         struct drm_i915_private *dev_priv = to_i915(dev);
4228         struct skl_wm_values *results = &state->wm_results;
4229         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4230         enum pipe pipe = intel_crtc->pipe;
4231
4232         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4233                 return;
4234
4235         mutex_lock(&dev_priv->wm.wm_mutex);
4236
4237         if (cstate->base.active_changed)
4238                 skl_atomic_update_crtc_wm(state, cstate);
4239
4240         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4241
4242         mutex_unlock(&dev_priv->wm.wm_mutex);
4243 }
4244
4245 static void ilk_compute_wm_config(struct drm_device *dev,
4246                                   struct intel_wm_config *config)
4247 {
4248         struct intel_crtc *crtc;
4249
4250         /* Compute the currently _active_ config */
4251         for_each_intel_crtc(dev, crtc) {
4252                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4253
4254                 if (!wm->pipe_enabled)
4255                         continue;
4256
4257                 config->sprites_enabled |= wm->sprites_enabled;
4258                 config->sprites_scaled |= wm->sprites_scaled;
4259                 config->num_pipes_active++;
4260         }
4261 }
4262
4263 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4264 {
4265         struct drm_device *dev = &dev_priv->drm;
4266         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4267         struct ilk_wm_maximums max;
4268         struct intel_wm_config config = {};
4269         struct ilk_wm_values results = {};
4270         enum intel_ddb_partitioning partitioning;
4271
4272         ilk_compute_wm_config(dev, &config);
4273
4274         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4275         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4276
4277         /* 5/6 split only in single pipe config on IVB+ */
4278         if (INTEL_GEN(dev_priv) >= 7 &&
4279             config.num_pipes_active == 1 && config.sprites_enabled) {
4280                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4281                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4282
4283                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4284         } else {
4285                 best_lp_wm = &lp_wm_1_2;
4286         }
4287
4288         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4289                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4290
4291         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4292
4293         ilk_write_wm_values(dev_priv, &results);
4294 }
4295
4296 static void ilk_initial_watermarks(struct intel_atomic_state *state,
4297                                    struct intel_crtc_state *cstate)
4298 {
4299         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4300         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4301
4302         mutex_lock(&dev_priv->wm.wm_mutex);
4303         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4304         ilk_program_watermarks(dev_priv);
4305         mutex_unlock(&dev_priv->wm.wm_mutex);
4306 }
4307
4308 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4309                                     struct intel_crtc_state *cstate)
4310 {
4311         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4312         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4313
4314         mutex_lock(&dev_priv->wm.wm_mutex);
4315         if (cstate->wm.need_postvbl_update) {
4316                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4317                 ilk_program_watermarks(dev_priv);
4318         }
4319         mutex_unlock(&dev_priv->wm.wm_mutex);
4320 }
4321
4322 static inline void skl_wm_level_from_reg_val(uint32_t val,
4323                                              struct skl_wm_level *level)
4324 {
4325         level->plane_en = val & PLANE_WM_EN;
4326         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4327         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4328                 PLANE_WM_LINES_MASK;
4329 }
4330
4331 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4332                               struct skl_pipe_wm *out)
4333 {
4334         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4336         enum pipe pipe = intel_crtc->pipe;
4337         int level, max_level;
4338         enum plane_id plane_id;
4339         uint32_t val;
4340
4341         max_level = ilk_wm_max_level(dev_priv);
4342
4343         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4344                 struct skl_plane_wm *wm = &out->planes[plane_id];
4345
4346                 for (level = 0; level <= max_level; level++) {
4347                         if (plane_id != PLANE_CURSOR)
4348                                 val = I915_READ(PLANE_WM(pipe, plane_id, level));
4349                         else
4350                                 val = I915_READ(CUR_WM(pipe, level));
4351
4352                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
4353                 }
4354
4355                 if (plane_id != PLANE_CURSOR)
4356                         val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
4357                 else
4358                         val = I915_READ(CUR_WM_TRANS(pipe));
4359
4360                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4361         }
4362
4363         if (!intel_crtc->active)
4364                 return;
4365
4366         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4367 }
4368
4369 void skl_wm_get_hw_state(struct drm_device *dev)
4370 {
4371         struct drm_i915_private *dev_priv = to_i915(dev);
4372         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4373         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4374         struct drm_crtc *crtc;
4375         struct intel_crtc *intel_crtc;
4376         struct intel_crtc_state *cstate;
4377
4378         skl_ddb_get_hw_state(dev_priv, ddb);
4379         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4380                 intel_crtc = to_intel_crtc(crtc);
4381                 cstate = to_intel_crtc_state(crtc->state);
4382
4383                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4384
4385                 if (intel_crtc->active)
4386                         hw->dirty_pipes |= drm_crtc_mask(crtc);
4387         }
4388
4389         if (dev_priv->active_crtcs) {
4390                 /* Fully recompute DDB on first atomic commit */
4391                 dev_priv->wm.distrust_bios_wm = true;
4392         } else {
4393                 /* Easy/common case; just sanitize DDB now if everything off */
4394                 memset(ddb, 0, sizeof(*ddb));
4395         }
4396 }
4397
4398 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4399 {
4400         struct drm_device *dev = crtc->dev;
4401         struct drm_i915_private *dev_priv = to_i915(dev);
4402         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4404         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4405         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4406         enum pipe pipe = intel_crtc->pipe;
4407         static const i915_reg_t wm0_pipe_reg[] = {
4408                 [PIPE_A] = WM0_PIPEA_ILK,
4409                 [PIPE_B] = WM0_PIPEB_ILK,
4410                 [PIPE_C] = WM0_PIPEC_IVB,
4411         };
4412
4413         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4414         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4415                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4416
4417         memset(active, 0, sizeof(*active));
4418
4419         active->pipe_enabled = intel_crtc->active;
4420
4421         if (active->pipe_enabled) {
4422                 u32 tmp = hw->wm_pipe[pipe];
4423
4424                 /*
4425                  * For active pipes LP0 watermark is marked as
4426                  * enabled, and LP1+ watermaks as disabled since
4427                  * we can't really reverse compute them in case
4428                  * multiple pipes are active.
4429                  */
4430                 active->wm[0].enable = true;
4431                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4432                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4433                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4434                 active->linetime = hw->wm_linetime[pipe];
4435         } else {
4436                 int level, max_level = ilk_wm_max_level(dev_priv);
4437
4438                 /*
4439                  * For inactive pipes, all watermark levels
4440                  * should be marked as enabled but zeroed,
4441                  * which is what we'd compute them to.
4442                  */
4443                 for (level = 0; level <= max_level; level++)
4444                         active->wm[level].enable = true;
4445         }
4446
4447         intel_crtc->wm.active.ilk = *active;
4448 }
4449
4450 #define _FW_WM(value, plane) \
4451         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4452 #define _FW_WM_VLV(value, plane) \
4453         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4454
4455 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4456                                struct vlv_wm_values *wm)
4457 {
4458         enum pipe pipe;
4459         uint32_t tmp;
4460
4461         for_each_pipe(dev_priv, pipe) {
4462                 tmp = I915_READ(VLV_DDL(pipe));
4463
4464                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
4465                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4466                 wm->ddl[pipe].plane[PLANE_CURSOR] =
4467                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4468                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
4469                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4470                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
4471                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4472         }
4473
4474         tmp = I915_READ(DSPFW1);
4475         wm->sr.plane = _FW_WM(tmp, SR);
4476         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
4477         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
4478         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
4479
4480         tmp = I915_READ(DSPFW2);
4481         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
4482         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
4483         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
4484
4485         tmp = I915_READ(DSPFW3);
4486         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4487
4488         if (IS_CHERRYVIEW(dev_priv)) {
4489                 tmp = I915_READ(DSPFW7_CHV);
4490                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4491                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
4492
4493                 tmp = I915_READ(DSPFW8_CHV);
4494                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
4495                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
4496
4497                 tmp = I915_READ(DSPFW9_CHV);
4498                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
4499                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
4500
4501                 tmp = I915_READ(DSPHOWM);
4502                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4503                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4504                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4505                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
4506                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4507                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4508                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4509                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4510                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4511                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
4512         } else {
4513                 tmp = I915_READ(DSPFW7);
4514                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4515                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
4516
4517                 tmp = I915_READ(DSPHOWM);
4518                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4519                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4520                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4521                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4522                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4523                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4524                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
4525         }
4526 }
4527
4528 #undef _FW_WM
4529 #undef _FW_WM_VLV
4530
4531 void vlv_wm_get_hw_state(struct drm_device *dev)
4532 {
4533         struct drm_i915_private *dev_priv = to_i915(dev);
4534         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4535         struct intel_plane *plane;
4536         enum pipe pipe;
4537         u32 val;
4538
4539         vlv_read_wm_values(dev_priv, wm);
4540
4541         for_each_intel_plane(dev, plane)
4542                 plane->wm.fifo_size = vlv_get_fifo_size(plane);
4543
4544         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4545         wm->level = VLV_WM_LEVEL_PM2;
4546
4547         if (IS_CHERRYVIEW(dev_priv)) {
4548                 mutex_lock(&dev_priv->rps.hw_lock);
4549
4550                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4551                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4552                         wm->level = VLV_WM_LEVEL_PM5;
4553
4554                 /*
4555                  * If DDR DVFS is disabled in the BIOS, Punit
4556                  * will never ack the request. So if that happens
4557                  * assume we don't have to enable/disable DDR DVFS
4558                  * dynamically. To test that just set the REQ_ACK
4559                  * bit to poke the Punit, but don't change the
4560                  * HIGH/LOW bits so that we don't actually change
4561                  * the current state.
4562                  */
4563                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4564                 val |= FORCE_DDR_FREQ_REQ_ACK;
4565                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4566
4567                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4568                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4569                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4570                                       "assuming DDR DVFS is disabled\n");
4571                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4572                 } else {
4573                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4574                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4575                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4576                 }
4577
4578                 mutex_unlock(&dev_priv->rps.hw_lock);
4579         }
4580
4581         for_each_pipe(dev_priv, pipe)
4582                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4583                               pipe_name(pipe),
4584                               wm->pipe[pipe].plane[PLANE_PRIMARY],
4585                               wm->pipe[pipe].plane[PLANE_CURSOR],
4586                               wm->pipe[pipe].plane[PLANE_SPRITE0],
4587                               wm->pipe[pipe].plane[PLANE_SPRITE1]);
4588
4589         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4590                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4591 }
4592
4593 void ilk_wm_get_hw_state(struct drm_device *dev)
4594 {
4595         struct drm_i915_private *dev_priv = to_i915(dev);
4596         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4597         struct drm_crtc *crtc;
4598
4599         for_each_crtc(dev, crtc)
4600                 ilk_pipe_wm_get_hw_state(crtc);
4601
4602         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4603         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4604         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4605
4606         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4607         if (INTEL_GEN(dev_priv) >= 7) {
4608                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4609                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4610         }
4611
4612         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4613                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4614                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4615         else if (IS_IVYBRIDGE(dev_priv))
4616                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4617                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4618
4619         hw->enable_fbc_wm =
4620                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4621 }
4622
4623 /**
4624  * intel_update_watermarks - update FIFO watermark values based on current modes
4625  *
4626  * Calculate watermark values for the various WM regs based on current mode
4627  * and plane configuration.
4628  *
4629  * There are several cases to deal with here:
4630  *   - normal (i.e. non-self-refresh)
4631  *   - self-refresh (SR) mode
4632  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4633  *   - lines are small relative to FIFO size (buffer can hold more than 2
4634  *     lines), so need to account for TLB latency
4635  *
4636  *   The normal calculation is:
4637  *     watermark = dotclock * bytes per pixel * latency
4638  *   where latency is platform & configuration dependent (we assume pessimal
4639  *   values here).
4640  *
4641  *   The SR calculation is:
4642  *     watermark = (trunc(latency/line time)+1) * surface width *
4643  *       bytes per pixel
4644  *   where
4645  *     line time = htotal / dotclock
4646  *     surface width = hdisplay for normal plane and 64 for cursor
4647  *   and latency is assumed to be high, as above.
4648  *
4649  * The final value programmed to the register should always be rounded up,
4650  * and include an extra 2 entries to account for clock crossings.
4651  *
4652  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4653  * to set the non-SR watermarks to 8.
4654  */
4655 void intel_update_watermarks(struct intel_crtc *crtc)
4656 {
4657         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4658
4659         if (dev_priv->display.update_wm)
4660                 dev_priv->display.update_wm(crtc);
4661 }
4662
4663 /*
4664  * Lock protecting IPS related data structures
4665  */
4666 DEFINE_SPINLOCK(mchdev_lock);
4667
4668 /* Global for IPS driver to get at the current i915 device. Protected by
4669  * mchdev_lock. */
4670 static struct drm_i915_private *i915_mch_dev;
4671
4672 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4673 {
4674         u16 rgvswctl;
4675
4676         assert_spin_locked(&mchdev_lock);
4677
4678         rgvswctl = I915_READ16(MEMSWCTL);
4679         if (rgvswctl & MEMCTL_CMD_STS) {
4680                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4681                 return false; /* still busy with another command */
4682         }
4683
4684         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4685                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4686         I915_WRITE16(MEMSWCTL, rgvswctl);
4687         POSTING_READ16(MEMSWCTL);
4688
4689         rgvswctl |= MEMCTL_CMD_STS;
4690         I915_WRITE16(MEMSWCTL, rgvswctl);
4691
4692         return true;
4693 }
4694
4695 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4696 {
4697         u32 rgvmodectl;
4698         u8 fmax, fmin, fstart, vstart;
4699
4700         spin_lock_irq(&mchdev_lock);
4701
4702         rgvmodectl = I915_READ(MEMMODECTL);
4703
4704         /* Enable temp reporting */
4705         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4706         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4707
4708         /* 100ms RC evaluation intervals */
4709         I915_WRITE(RCUPEI, 100000);
4710         I915_WRITE(RCDNEI, 100000);
4711
4712         /* Set max/min thresholds to 90ms and 80ms respectively */
4713         I915_WRITE(RCBMAXAVG, 90000);
4714         I915_WRITE(RCBMINAVG, 80000);
4715
4716         I915_WRITE(MEMIHYST, 1);
4717
4718         /* Set up min, max, and cur for interrupt handling */
4719         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4720         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4721         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4722                 MEMMODE_FSTART_SHIFT;
4723
4724         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4725                 PXVFREQ_PX_SHIFT;
4726
4727         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4728         dev_priv->ips.fstart = fstart;
4729
4730         dev_priv->ips.max_delay = fstart;
4731         dev_priv->ips.min_delay = fmin;
4732         dev_priv->ips.cur_delay = fstart;
4733
4734         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4735                          fmax, fmin, fstart);
4736
4737         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4738
4739         /*
4740          * Interrupts will be enabled in ironlake_irq_postinstall
4741          */
4742
4743         I915_WRITE(VIDSTART, vstart);
4744         POSTING_READ(VIDSTART);
4745
4746         rgvmodectl |= MEMMODE_SWMODE_EN;
4747         I915_WRITE(MEMMODECTL, rgvmodectl);
4748
4749         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4750                 DRM_ERROR("stuck trying to change perf mode\n");
4751         mdelay(1);
4752
4753         ironlake_set_drps(dev_priv, fstart);
4754
4755         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4756                 I915_READ(DDREC) + I915_READ(CSIEC);
4757         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4758         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4759         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4760
4761         spin_unlock_irq(&mchdev_lock);
4762 }
4763
4764 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4765 {
4766         u16 rgvswctl;
4767
4768         spin_lock_irq(&mchdev_lock);
4769
4770         rgvswctl = I915_READ16(MEMSWCTL);
4771
4772         /* Ack interrupts, disable EFC interrupt */
4773         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4774         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4775         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4776         I915_WRITE(DEIIR, DE_PCU_EVENT);
4777         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4778
4779         /* Go back to the starting frequency */
4780         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4781         mdelay(1);
4782         rgvswctl |= MEMCTL_CMD_STS;
4783         I915_WRITE(MEMSWCTL, rgvswctl);
4784         mdelay(1);
4785
4786         spin_unlock_irq(&mchdev_lock);
4787 }
4788
4789 /* There's a funny hw issue where the hw returns all 0 when reading from
4790  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4791  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4792  * all limits and the gpu stuck at whatever frequency it is at atm).
4793  */
4794 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4795 {
4796         u32 limits;
4797
4798         /* Only set the down limit when we've reached the lowest level to avoid
4799          * getting more interrupts, otherwise leave this clear. This prevents a
4800          * race in the hw when coming out of rc6: There's a tiny window where
4801          * the hw runs at the minimal clock before selecting the desired
4802          * frequency, if the down threshold expires in that window we will not
4803          * receive a down interrupt. */
4804         if (IS_GEN9(dev_priv)) {
4805                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4806                 if (val <= dev_priv->rps.min_freq_softlimit)
4807                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4808         } else {
4809                 limits = dev_priv->rps.max_freq_softlimit << 24;
4810                 if (val <= dev_priv->rps.min_freq_softlimit)
4811                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4812         }
4813
4814         return limits;
4815 }
4816
4817 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4818 {
4819         int new_power;
4820         u32 threshold_up = 0, threshold_down = 0; /* in % */
4821         u32 ei_up = 0, ei_down = 0;
4822
4823         new_power = dev_priv->rps.power;
4824         switch (dev_priv->rps.power) {
4825         case LOW_POWER:
4826                 if (val > dev_priv->rps.efficient_freq + 1 &&
4827                     val > dev_priv->rps.cur_freq)
4828                         new_power = BETWEEN;
4829                 break;
4830
4831         case BETWEEN:
4832                 if (val <= dev_priv->rps.efficient_freq &&
4833                     val < dev_priv->rps.cur_freq)
4834                         new_power = LOW_POWER;
4835                 else if (val >= dev_priv->rps.rp0_freq &&
4836                          val > dev_priv->rps.cur_freq)
4837                         new_power = HIGH_POWER;
4838                 break;
4839
4840         case HIGH_POWER:
4841                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4842                     val < dev_priv->rps.cur_freq)
4843                         new_power = BETWEEN;
4844                 break;
4845         }
4846         /* Max/min bins are special */
4847         if (val <= dev_priv->rps.min_freq_softlimit)
4848                 new_power = LOW_POWER;
4849         if (val >= dev_priv->rps.max_freq_softlimit)
4850                 new_power = HIGH_POWER;
4851         if (new_power == dev_priv->rps.power)
4852                 return;
4853
4854         /* Note the units here are not exactly 1us, but 1280ns. */
4855         switch (new_power) {
4856         case LOW_POWER:
4857                 /* Upclock if more than 95% busy over 16ms */
4858                 ei_up = 16000;
4859                 threshold_up = 95;
4860
4861                 /* Downclock if less than 85% busy over 32ms */
4862                 ei_down = 32000;
4863                 threshold_down = 85;
4864                 break;
4865
4866         case BETWEEN:
4867                 /* Upclock if more than 90% busy over 13ms */
4868                 ei_up = 13000;
4869                 threshold_up = 90;
4870
4871                 /* Downclock if less than 75% busy over 32ms */
4872                 ei_down = 32000;
4873                 threshold_down = 75;
4874                 break;
4875
4876         case HIGH_POWER:
4877                 /* Upclock if more than 85% busy over 10ms */
4878                 ei_up = 10000;
4879                 threshold_up = 85;
4880
4881                 /* Downclock if less than 60% busy over 32ms */
4882                 ei_down = 32000;
4883                 threshold_down = 60;
4884                 break;
4885         }
4886
4887         I915_WRITE(GEN6_RP_UP_EI,
4888                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4889         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4890                    GT_INTERVAL_FROM_US(dev_priv,
4891                                        ei_up * threshold_up / 100));
4892
4893         I915_WRITE(GEN6_RP_DOWN_EI,
4894                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4895         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4896                    GT_INTERVAL_FROM_US(dev_priv,
4897                                        ei_down * threshold_down / 100));
4898
4899         I915_WRITE(GEN6_RP_CONTROL,
4900                    GEN6_RP_MEDIA_TURBO |
4901                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4902                    GEN6_RP_MEDIA_IS_GFX |
4903                    GEN6_RP_ENABLE |
4904                    GEN6_RP_UP_BUSY_AVG |
4905                    GEN6_RP_DOWN_IDLE_AVG);
4906
4907         dev_priv->rps.power = new_power;
4908         dev_priv->rps.up_threshold = threshold_up;
4909         dev_priv->rps.down_threshold = threshold_down;
4910         dev_priv->rps.last_adj = 0;
4911 }
4912
4913 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4914 {
4915         u32 mask = 0;
4916
4917         if (val > dev_priv->rps.min_freq_softlimit)
4918                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4919         if (val < dev_priv->rps.max_freq_softlimit)
4920                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4921
4922         mask &= dev_priv->pm_rps_events;
4923
4924         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4925 }
4926
4927 /* gen6_set_rps is called to update the frequency request, but should also be
4928  * called when the range (min_delay and max_delay) is modified so that we can
4929  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4930 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4931 {
4932         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4933         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4934                 return;
4935
4936         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4937         WARN_ON(val > dev_priv->rps.max_freq);
4938         WARN_ON(val < dev_priv->rps.min_freq);
4939
4940         /* min/max delay may still have been modified so be sure to
4941          * write the limits value.
4942          */
4943         if (val != dev_priv->rps.cur_freq) {
4944                 gen6_set_rps_thresholds(dev_priv, val);
4945
4946                 if (IS_GEN9(dev_priv))
4947                         I915_WRITE(GEN6_RPNSWREQ,
4948                                    GEN9_FREQUENCY(val));
4949                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4950                         I915_WRITE(GEN6_RPNSWREQ,
4951                                    HSW_FREQUENCY(val));
4952                 else
4953                         I915_WRITE(GEN6_RPNSWREQ,
4954                                    GEN6_FREQUENCY(val) |
4955                                    GEN6_OFFSET(0) |
4956                                    GEN6_AGGRESSIVE_TURBO);
4957         }
4958
4959         /* Make sure we continue to get interrupts
4960          * until we hit the minimum or maximum frequencies.
4961          */
4962         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4963         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4964
4965         POSTING_READ(GEN6_RPNSWREQ);
4966
4967         dev_priv->rps.cur_freq = val;
4968         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4969 }
4970
4971 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4972 {
4973         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4974         WARN_ON(val > dev_priv->rps.max_freq);
4975         WARN_ON(val < dev_priv->rps.min_freq);
4976
4977         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4978                       "Odd GPU freq value\n"))
4979                 val &= ~1;
4980
4981         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4982
4983         if (val != dev_priv->rps.cur_freq) {
4984                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4985                 if (!IS_CHERRYVIEW(dev_priv))
4986                         gen6_set_rps_thresholds(dev_priv, val);
4987         }
4988
4989         dev_priv->rps.cur_freq = val;
4990         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4991 }
4992
4993 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4994  *
4995  * * If Gfx is Idle, then
4996  * 1. Forcewake Media well.
4997  * 2. Request idle freq.
4998  * 3. Release Forcewake of Media well.
4999 */
5000 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5001 {
5002         u32 val = dev_priv->rps.idle_freq;
5003
5004         if (dev_priv->rps.cur_freq <= val)
5005                 return;
5006
5007         /* Wake up the media well, as that takes a lot less
5008          * power than the Render well. */
5009         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5010         valleyview_set_rps(dev_priv, val);
5011         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5012 }
5013
5014 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5015 {
5016         mutex_lock(&dev_priv->rps.hw_lock);
5017         if (dev_priv->rps.enabled) {
5018                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5019                         gen6_rps_reset_ei(dev_priv);
5020                 I915_WRITE(GEN6_PMINTRMSK,
5021                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5022
5023                 gen6_enable_rps_interrupts(dev_priv);
5024
5025                 /* Ensure we start at the user's desired frequency */
5026                 intel_set_rps(dev_priv,
5027                               clamp(dev_priv->rps.cur_freq,
5028                                     dev_priv->rps.min_freq_softlimit,
5029                                     dev_priv->rps.max_freq_softlimit));
5030         }
5031         mutex_unlock(&dev_priv->rps.hw_lock);
5032 }
5033
5034 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5035 {
5036         /* Flush our bottom-half so that it does not race with us
5037          * setting the idle frequency and so that it is bounded by
5038          * our rpm wakeref. And then disable the interrupts to stop any
5039          * futher RPS reclocking whilst we are asleep.
5040          */
5041         gen6_disable_rps_interrupts(dev_priv);
5042
5043         mutex_lock(&dev_priv->rps.hw_lock);
5044         if (dev_priv->rps.enabled) {
5045                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5046                         vlv_set_rps_idle(dev_priv);
5047                 else
5048                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5049                 dev_priv->rps.last_adj = 0;
5050                 I915_WRITE(GEN6_PMINTRMSK,
5051                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5052         }
5053         mutex_unlock(&dev_priv->rps.hw_lock);
5054
5055         spin_lock(&dev_priv->rps.client_lock);
5056         while (!list_empty(&dev_priv->rps.clients))
5057                 list_del_init(dev_priv->rps.clients.next);
5058         spin_unlock(&dev_priv->rps.client_lock);
5059 }
5060
5061 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5062                     struct intel_rps_client *rps,
5063                     unsigned long submitted)
5064 {
5065         /* This is intentionally racy! We peek at the state here, then
5066          * validate inside the RPS worker.
5067          */
5068         if (!(dev_priv->gt.awake &&
5069               dev_priv->rps.enabled &&
5070               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5071                 return;
5072
5073         /* Force a RPS boost (and don't count it against the client) if
5074          * the GPU is severely congested.
5075          */
5076         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5077                 rps = NULL;
5078
5079         spin_lock(&dev_priv->rps.client_lock);
5080         if (rps == NULL || list_empty(&rps->link)) {
5081                 spin_lock_irq(&dev_priv->irq_lock);
5082                 if (dev_priv->rps.interrupts_enabled) {
5083                         dev_priv->rps.client_boost = true;
5084                         schedule_work(&dev_priv->rps.work);
5085                 }
5086                 spin_unlock_irq(&dev_priv->irq_lock);
5087
5088                 if (rps != NULL) {
5089                         list_add(&rps->link, &dev_priv->rps.clients);
5090                         rps->boosts++;
5091                 } else
5092                         dev_priv->rps.boosts++;
5093         }
5094         spin_unlock(&dev_priv->rps.client_lock);
5095 }
5096
5097 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5098 {
5099         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5100                 valleyview_set_rps(dev_priv, val);
5101         else
5102                 gen6_set_rps(dev_priv, val);
5103 }
5104
5105 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5106 {
5107         I915_WRITE(GEN6_RC_CONTROL, 0);
5108         I915_WRITE(GEN9_PG_ENABLE, 0);
5109 }
5110
5111 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5112 {
5113         I915_WRITE(GEN6_RP_CONTROL, 0);
5114 }
5115
5116 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5117 {
5118         I915_WRITE(GEN6_RC_CONTROL, 0);
5119         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5120         I915_WRITE(GEN6_RP_CONTROL, 0);
5121 }
5122
5123 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5124 {
5125         I915_WRITE(GEN6_RC_CONTROL, 0);
5126 }
5127
5128 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5129 {
5130         /* we're doing forcewake before Disabling RC6,
5131          * This what the BIOS expects when going into suspend */
5132         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5133
5134         I915_WRITE(GEN6_RC_CONTROL, 0);
5135
5136         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5137 }
5138
5139 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5140 {
5141         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5142                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5143                         mode = GEN6_RC_CTL_RC6_ENABLE;
5144                 else
5145                         mode = 0;
5146         }
5147         if (HAS_RC6p(dev_priv))
5148                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5149                                  "RC6 %s RC6p %s RC6pp %s\n",
5150                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5151                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5152                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5153
5154         else
5155                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5156                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5157 }
5158
5159 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5160 {
5161         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5162         bool enable_rc6 = true;
5163         unsigned long rc6_ctx_base;
5164         u32 rc_ctl;
5165         int rc_sw_target;
5166
5167         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5168         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5169                        RC_SW_TARGET_STATE_SHIFT;
5170         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5171                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5172                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5173                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5174                          rc_sw_target);
5175
5176         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5177                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5178                 enable_rc6 = false;
5179         }
5180
5181         /*
5182          * The exact context size is not known for BXT, so assume a page size
5183          * for this check.
5184          */
5185         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5186         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5187               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5188                                         ggtt->stolen_reserved_size))) {
5189                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5190                 enable_rc6 = false;
5191         }
5192
5193         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5194               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5195               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5196               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5197                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5198                 enable_rc6 = false;
5199         }
5200
5201         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5202             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5203             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5204                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5205                 enable_rc6 = false;
5206         }
5207
5208         if (!I915_READ(GEN6_GFXPAUSE)) {
5209                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5210                 enable_rc6 = false;
5211         }
5212
5213         if (!I915_READ(GEN8_MISC_CTRL0)) {
5214                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5215                 enable_rc6 = false;
5216         }
5217
5218         return enable_rc6;
5219 }
5220
5221 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5222 {
5223         /* No RC6 before Ironlake and code is gone for ilk. */
5224         if (INTEL_INFO(dev_priv)->gen < 6)
5225                 return 0;
5226
5227         if (!enable_rc6)
5228                 return 0;
5229
5230         if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5231                 DRM_INFO("RC6 disabled by BIOS\n");
5232                 return 0;
5233         }
5234
5235         /* Respect the kernel parameter if it is set */
5236         if (enable_rc6 >= 0) {
5237                 int mask;
5238
5239                 if (HAS_RC6p(dev_priv))
5240                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5241                                INTEL_RC6pp_ENABLE;
5242                 else
5243                         mask = INTEL_RC6_ENABLE;
5244
5245                 if ((enable_rc6 & mask) != enable_rc6)
5246                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5247                                          "(requested %d, valid %d)\n",
5248                                          enable_rc6 & mask, enable_rc6, mask);
5249
5250                 return enable_rc6 & mask;
5251         }
5252
5253         if (IS_IVYBRIDGE(dev_priv))
5254                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5255
5256         return INTEL_RC6_ENABLE;
5257 }
5258
5259 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5260 {
5261         /* All of these values are in units of 50MHz */
5262
5263         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5264         if (IS_GEN9_LP(dev_priv)) {
5265                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5266                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5267                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5268                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5269         } else {
5270                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5271                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5272                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5273                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5274         }
5275         /* hw_max = RP0 until we check for overclocking */
5276         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5277
5278         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5279         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5280             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5281                 u32 ddcc_status = 0;
5282
5283                 if (sandybridge_pcode_read(dev_priv,
5284                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5285                                            &ddcc_status) == 0)
5286                         dev_priv->rps.efficient_freq =
5287                                 clamp_t(u8,
5288                                         ((ddcc_status >> 8) & 0xff),
5289                                         dev_priv->rps.min_freq,
5290                                         dev_priv->rps.max_freq);
5291         }
5292
5293         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5294                 /* Store the frequency values in 16.66 MHZ units, which is
5295                  * the natural hardware unit for SKL
5296                  */
5297                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5298                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5299                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5300                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5301                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5302         }
5303 }
5304
5305 static void reset_rps(struct drm_i915_private *dev_priv,
5306                       void (*set)(struct drm_i915_private *, u8))
5307 {
5308         u8 freq = dev_priv->rps.cur_freq;
5309
5310         /* force a reset */
5311         dev_priv->rps.power = -1;
5312         dev_priv->rps.cur_freq = -1;
5313
5314         set(dev_priv, freq);
5315 }
5316
5317 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5318 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5319 {
5320         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5321
5322         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5323         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5324                 /*
5325                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5326                  * clear out the Control register just to avoid inconsitency
5327                  * with debugfs interface, which will show  Turbo as enabled
5328                  * only and that is not expected by the User after adding the
5329                  * WaGsvDisableTurbo. Apart from this there is no problem even
5330                  * if the Turbo is left enabled in the Control register, as the
5331                  * Up/Down interrupts would remain masked.
5332                  */
5333                 gen9_disable_rps(dev_priv);
5334                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5335                 return;
5336         }
5337
5338         /* Program defaults and thresholds for RPS*/
5339         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5340                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5341
5342         /* 1 second timeout*/
5343         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5344                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5345
5346         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5347
5348         /* Leaning on the below call to gen6_set_rps to program/setup the
5349          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5350          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5351         reset_rps(dev_priv, gen6_set_rps);
5352
5353         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5354 }
5355
5356 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5357 {
5358         struct intel_engine_cs *engine;
5359         enum intel_engine_id id;
5360         uint32_t rc6_mask = 0;
5361
5362         /* 1a: Software RC state - RC0 */
5363         I915_WRITE(GEN6_RC_STATE, 0);
5364
5365         /* 1b: Get forcewake during program sequence. Although the driver
5366          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5367         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5368
5369         /* 2a: Disable RC states. */
5370         I915_WRITE(GEN6_RC_CONTROL, 0);
5371
5372         /* 2b: Program RC6 thresholds.*/
5373
5374         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5375         if (IS_SKYLAKE(dev_priv))
5376                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5377         else
5378                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5379         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5380         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5381         for_each_engine(engine, dev_priv, id)
5382                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5383
5384         if (HAS_GUC(dev_priv))
5385                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5386
5387         I915_WRITE(GEN6_RC_SLEEP, 0);
5388
5389         /* 2c: Program Coarse Power Gating Policies. */
5390         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5391         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5392
5393         /* 3a: Enable RC6 */
5394         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5395                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5396         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5397         /* WaRsUseTimeoutMode:bxt */
5398         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5399                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5400                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5401                            GEN7_RC_CTL_TO_MODE |
5402                            rc6_mask);
5403         } else {
5404                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5405                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5406                            GEN6_RC_CTL_EI_MODE(1) |
5407                            rc6_mask);
5408         }
5409
5410         /*
5411          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5412          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5413          */
5414         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5415                 I915_WRITE(GEN9_PG_ENABLE, 0);
5416         else
5417                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5418                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5419
5420         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5421 }
5422
5423 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5424 {
5425         struct intel_engine_cs *engine;
5426         enum intel_engine_id id;
5427         uint32_t rc6_mask = 0;
5428
5429         /* 1a: Software RC state - RC0 */
5430         I915_WRITE(GEN6_RC_STATE, 0);
5431
5432         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5433          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5434         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5435
5436         /* 2a: Disable RC states. */
5437         I915_WRITE(GEN6_RC_CONTROL, 0);
5438
5439         /* 2b: Program RC6 thresholds.*/
5440         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5441         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5442         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5443         for_each_engine(engine, dev_priv, id)
5444                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5445         I915_WRITE(GEN6_RC_SLEEP, 0);
5446         if (IS_BROADWELL(dev_priv))
5447                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5448         else
5449                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5450
5451         /* 3: Enable RC6 */
5452         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5453                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5454         intel_print_rc6_info(dev_priv, rc6_mask);
5455         if (IS_BROADWELL(dev_priv))
5456                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5457                                 GEN7_RC_CTL_TO_MODE |
5458                                 rc6_mask);
5459         else
5460                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5461                                 GEN6_RC_CTL_EI_MODE(1) |
5462                                 rc6_mask);
5463
5464         /* 4 Program defaults and thresholds for RPS*/
5465         I915_WRITE(GEN6_RPNSWREQ,
5466                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5467         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5468                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5469         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5470         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5471
5472         /* Docs recommend 900MHz, and 300 MHz respectively */
5473         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5474                    dev_priv->rps.max_freq_softlimit << 24 |
5475                    dev_priv->rps.min_freq_softlimit << 16);
5476
5477         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5478         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5479         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5480         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5481
5482         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5483
5484         /* 5: Enable RPS */
5485         I915_WRITE(GEN6_RP_CONTROL,
5486                    GEN6_RP_MEDIA_TURBO |
5487                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5488                    GEN6_RP_MEDIA_IS_GFX |
5489                    GEN6_RP_ENABLE |
5490                    GEN6_RP_UP_BUSY_AVG |
5491                    GEN6_RP_DOWN_IDLE_AVG);
5492
5493         /* 6: Ring frequency + overclocking (our driver does this later */
5494
5495         reset_rps(dev_priv, gen6_set_rps);
5496
5497         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5498 }
5499
5500 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5501 {
5502         struct intel_engine_cs *engine;
5503         enum intel_engine_id id;
5504         u32 rc6vids, rc6_mask = 0;
5505         u32 gtfifodbg;
5506         int rc6_mode;
5507         int ret;
5508
5509         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5510
5511         /* Here begins a magic sequence of register writes to enable
5512          * auto-downclocking.
5513          *
5514          * Perhaps there might be some value in exposing these to
5515          * userspace...
5516          */
5517         I915_WRITE(GEN6_RC_STATE, 0);
5518
5519         /* Clear the DBG now so we don't confuse earlier errors */
5520         gtfifodbg = I915_READ(GTFIFODBG);
5521         if (gtfifodbg) {
5522                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5523                 I915_WRITE(GTFIFODBG, gtfifodbg);
5524         }
5525
5526         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5527
5528         /* disable the counters and set deterministic thresholds */
5529         I915_WRITE(GEN6_RC_CONTROL, 0);
5530
5531         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5532         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5533         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5534         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5535         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5536
5537         for_each_engine(engine, dev_priv, id)
5538                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5539
5540         I915_WRITE(GEN6_RC_SLEEP, 0);
5541         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5542         if (IS_IVYBRIDGE(dev_priv))
5543                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5544         else
5545                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5546         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5547         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5548
5549         /* Check if we are enabling RC6 */
5550         rc6_mode = intel_enable_rc6();
5551         if (rc6_mode & INTEL_RC6_ENABLE)
5552                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5553
5554         /* We don't use those on Haswell */
5555         if (!IS_HASWELL(dev_priv)) {
5556                 if (rc6_mode & INTEL_RC6p_ENABLE)
5557                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5558
5559                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5560                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5561         }
5562
5563         intel_print_rc6_info(dev_priv, rc6_mask);
5564
5565         I915_WRITE(GEN6_RC_CONTROL,
5566                    rc6_mask |
5567                    GEN6_RC_CTL_EI_MODE(1) |
5568                    GEN6_RC_CTL_HW_ENABLE);
5569
5570         /* Power down if completely idle for over 50ms */
5571         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5572         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5573
5574         reset_rps(dev_priv, gen6_set_rps);
5575
5576         rc6vids = 0;
5577         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5578         if (IS_GEN6(dev_priv) && ret) {
5579                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5580         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5581                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5582                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5583                 rc6vids &= 0xffff00;
5584                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5585                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5586                 if (ret)
5587                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5588         }
5589
5590         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5591 }
5592
5593 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5594 {
5595         int min_freq = 15;
5596         unsigned int gpu_freq;
5597         unsigned int max_ia_freq, min_ring_freq;
5598         unsigned int max_gpu_freq, min_gpu_freq;
5599         int scaling_factor = 180;
5600         struct cpufreq_policy *policy;
5601
5602         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5603
5604         policy = cpufreq_cpu_get(0);
5605         if (policy) {
5606                 max_ia_freq = policy->cpuinfo.max_freq;
5607                 cpufreq_cpu_put(policy);
5608         } else {
5609                 /*
5610                  * Default to measured freq if none found, PCU will ensure we
5611                  * don't go over
5612                  */
5613                 max_ia_freq = tsc_khz;
5614         }
5615
5616         /* Convert from kHz to MHz */
5617         max_ia_freq /= 1000;
5618
5619         min_ring_freq = I915_READ(DCLK) & 0xf;
5620         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5621         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5622
5623         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5624                 /* Convert GT frequency to 50 HZ units */
5625                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5626                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5627         } else {
5628                 min_gpu_freq = dev_priv->rps.min_freq;
5629                 max_gpu_freq = dev_priv->rps.max_freq;
5630         }
5631
5632         /*
5633          * For each potential GPU frequency, load a ring frequency we'd like
5634          * to use for memory access.  We do this by specifying the IA frequency
5635          * the PCU should use as a reference to determine the ring frequency.
5636          */
5637         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5638                 int diff = max_gpu_freq - gpu_freq;
5639                 unsigned int ia_freq = 0, ring_freq = 0;
5640
5641                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5642                         /*
5643                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5644                          * No floor required for ring frequency on SKL.
5645                          */
5646                         ring_freq = gpu_freq;
5647                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5648                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5649                         ring_freq = max(min_ring_freq, gpu_freq);
5650                 } else if (IS_HASWELL(dev_priv)) {
5651                         ring_freq = mult_frac(gpu_freq, 5, 4);
5652                         ring_freq = max(min_ring_freq, ring_freq);
5653                         /* leave ia_freq as the default, chosen by cpufreq */
5654                 } else {
5655                         /* On older processors, there is no separate ring
5656                          * clock domain, so in order to boost the bandwidth
5657                          * of the ring, we need to upclock the CPU (ia_freq).
5658                          *
5659                          * For GPU frequencies less than 750MHz,
5660                          * just use the lowest ring freq.
5661                          */
5662                         if (gpu_freq < min_freq)
5663                                 ia_freq = 800;
5664                         else
5665                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5666                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5667                 }
5668
5669                 sandybridge_pcode_write(dev_priv,
5670                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5671                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5672                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5673                                         gpu_freq);
5674         }
5675 }
5676
5677 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5678 {
5679         u32 val, rp0;
5680
5681         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5682
5683         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5684         case 8:
5685                 /* (2 * 4) config */
5686                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5687                 break;
5688         case 12:
5689                 /* (2 * 6) config */
5690                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5691                 break;
5692         case 16:
5693                 /* (2 * 8) config */
5694         default:
5695                 /* Setting (2 * 8) Min RP0 for any other combination */
5696                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5697                 break;
5698         }
5699
5700         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5701
5702         return rp0;
5703 }
5704
5705 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5706 {
5707         u32 val, rpe;
5708
5709         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5710         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5711
5712         return rpe;
5713 }
5714
5715 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5716 {
5717         u32 val, rp1;
5718
5719         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5720         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5721
5722         return rp1;
5723 }
5724
5725 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5726 {
5727         u32 val, rp1;
5728
5729         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5730
5731         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5732
5733         return rp1;
5734 }
5735
5736 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5737 {
5738         u32 val, rp0;
5739
5740         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5741
5742         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5743         /* Clamp to max */
5744         rp0 = min_t(u32, rp0, 0xea);
5745
5746         return rp0;
5747 }
5748
5749 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5750 {
5751         u32 val, rpe;
5752
5753         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5754         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5755         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5756         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5757
5758         return rpe;
5759 }
5760
5761 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5762 {
5763         u32 val;
5764
5765         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5766         /*
5767          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5768          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5769          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5770          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5771          * to make sure it matches what Punit accepts.
5772          */
5773         return max_t(u32, val, 0xc0);
5774 }
5775
5776 /* Check that the pctx buffer wasn't move under us. */
5777 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5778 {
5779         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5780
5781         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5782                              dev_priv->vlv_pctx->stolen->start);
5783 }
5784
5785
5786 /* Check that the pcbr address is not empty. */
5787 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5788 {
5789         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5790
5791         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5792 }
5793
5794 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5795 {
5796         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5797         unsigned long pctx_paddr, paddr;
5798         u32 pcbr;
5799         int pctx_size = 32*1024;
5800
5801         pcbr = I915_READ(VLV_PCBR);
5802         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5803                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5804                 paddr = (dev_priv->mm.stolen_base +
5805                          (ggtt->stolen_size - pctx_size));
5806
5807                 pctx_paddr = (paddr & (~4095));
5808                 I915_WRITE(VLV_PCBR, pctx_paddr);
5809         }
5810
5811         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5812 }
5813
5814 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5815 {
5816         struct drm_i915_gem_object *pctx;
5817         unsigned long pctx_paddr;
5818         u32 pcbr;
5819         int pctx_size = 24*1024;
5820
5821         pcbr = I915_READ(VLV_PCBR);
5822         if (pcbr) {
5823                 /* BIOS set it up already, grab the pre-alloc'd space */
5824                 int pcbr_offset;
5825
5826                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5827                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
5828                                                                       pcbr_offset,
5829                                                                       I915_GTT_OFFSET_NONE,
5830                                                                       pctx_size);
5831                 goto out;
5832         }
5833
5834         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5835
5836         /*
5837          * From the Gunit register HAS:
5838          * The Gfx driver is expected to program this register and ensure
5839          * proper allocation within Gfx stolen memory.  For example, this
5840          * register should be programmed such than the PCBR range does not
5841          * overlap with other ranges, such as the frame buffer, protected
5842          * memory, or any other relevant ranges.
5843          */
5844         pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
5845         if (!pctx) {
5846                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5847                 goto out;
5848         }
5849
5850         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5851         I915_WRITE(VLV_PCBR, pctx_paddr);
5852
5853 out:
5854         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5855         dev_priv->vlv_pctx = pctx;
5856 }
5857
5858 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5859 {
5860         if (WARN_ON(!dev_priv->vlv_pctx))
5861                 return;
5862
5863         i915_gem_object_put(dev_priv->vlv_pctx);
5864         dev_priv->vlv_pctx = NULL;
5865 }
5866
5867 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5868 {
5869         dev_priv->rps.gpll_ref_freq =
5870                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5871                                   CCK_GPLL_CLOCK_CONTROL,
5872                                   dev_priv->czclk_freq);
5873
5874         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5875                          dev_priv->rps.gpll_ref_freq);
5876 }
5877
5878 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5879 {
5880         u32 val;
5881
5882         valleyview_setup_pctx(dev_priv);
5883
5884         vlv_init_gpll_ref_freq(dev_priv);
5885
5886         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5887         switch ((val >> 6) & 3) {
5888         case 0:
5889         case 1:
5890                 dev_priv->mem_freq = 800;
5891                 break;
5892         case 2:
5893                 dev_priv->mem_freq = 1066;
5894                 break;
5895         case 3:
5896                 dev_priv->mem_freq = 1333;
5897                 break;
5898         }
5899         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5900
5901         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5902         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5903         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5904                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5905                          dev_priv->rps.max_freq);
5906
5907         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5908         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5909                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5910                          dev_priv->rps.efficient_freq);
5911
5912         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5913         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5914                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5915                          dev_priv->rps.rp1_freq);
5916
5917         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5918         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5919                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5920                          dev_priv->rps.min_freq);
5921 }
5922
5923 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5924 {
5925         u32 val;
5926
5927         cherryview_setup_pctx(dev_priv);
5928
5929         vlv_init_gpll_ref_freq(dev_priv);
5930
5931         mutex_lock(&dev_priv->sb_lock);
5932         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5933         mutex_unlock(&dev_priv->sb_lock);
5934
5935         switch ((val >> 2) & 0x7) {
5936         case 3:
5937                 dev_priv->mem_freq = 2000;
5938                 break;
5939         default:
5940                 dev_priv->mem_freq = 1600;
5941                 break;
5942         }
5943         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5944
5945         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5946         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5947         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5948                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5949                          dev_priv->rps.max_freq);
5950
5951         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5952         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5953                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5954                          dev_priv->rps.efficient_freq);
5955
5956         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5957         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5958                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5959                          dev_priv->rps.rp1_freq);
5960
5961         /* PUnit validated range is only [RPe, RP0] */
5962         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5963         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5964                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5965                          dev_priv->rps.min_freq);
5966
5967         WARN_ONCE((dev_priv->rps.max_freq |
5968                    dev_priv->rps.efficient_freq |
5969                    dev_priv->rps.rp1_freq |
5970                    dev_priv->rps.min_freq) & 1,
5971                   "Odd GPU freq values\n");
5972 }
5973
5974 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5975 {
5976         valleyview_cleanup_pctx(dev_priv);
5977 }
5978
5979 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5980 {
5981         struct intel_engine_cs *engine;
5982         enum intel_engine_id id;
5983         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5984
5985         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5986
5987         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5988                                              GT_FIFO_FREE_ENTRIES_CHV);
5989         if (gtfifodbg) {
5990                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5991                                  gtfifodbg);
5992                 I915_WRITE(GTFIFODBG, gtfifodbg);
5993         }
5994
5995         cherryview_check_pctx(dev_priv);
5996
5997         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5998          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5999         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6000
6001         /*  Disable RC states. */
6002         I915_WRITE(GEN6_RC_CONTROL, 0);
6003
6004         /* 2a: Program RC6 thresholds.*/
6005         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6006         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6007         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6008
6009         for_each_engine(engine, dev_priv, id)
6010                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6011         I915_WRITE(GEN6_RC_SLEEP, 0);
6012
6013         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6014         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6015
6016         /* allows RC6 residency counter to work */
6017         I915_WRITE(VLV_COUNTER_CONTROL,
6018                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6019                                       VLV_MEDIA_RC6_COUNT_EN |
6020                                       VLV_RENDER_RC6_COUNT_EN));
6021
6022         /* For now we assume BIOS is allocating and populating the PCBR  */
6023         pcbr = I915_READ(VLV_PCBR);
6024
6025         /* 3: Enable RC6 */
6026         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6027             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6028                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6029
6030         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6031
6032         /* 4 Program defaults and thresholds for RPS*/
6033         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6034         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6035         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6036         I915_WRITE(GEN6_RP_UP_EI, 66000);
6037         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6038
6039         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6040
6041         /* 5: Enable RPS */
6042         I915_WRITE(GEN6_RP_CONTROL,
6043                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6044                    GEN6_RP_MEDIA_IS_GFX |
6045                    GEN6_RP_ENABLE |
6046                    GEN6_RP_UP_BUSY_AVG |
6047                    GEN6_RP_DOWN_IDLE_AVG);
6048
6049         /* Setting Fixed Bias */
6050         val = VLV_OVERRIDE_EN |
6051                   VLV_SOC_TDP_EN |
6052                   CHV_BIAS_CPU_50_SOC_50;
6053         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6054
6055         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6056
6057         /* RPS code assumes GPLL is used */
6058         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6059
6060         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6061         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6062
6063         reset_rps(dev_priv, valleyview_set_rps);
6064
6065         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6066 }
6067
6068 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6069 {
6070         struct intel_engine_cs *engine;
6071         enum intel_engine_id id;
6072         u32 gtfifodbg, val, rc6_mode = 0;
6073
6074         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6075
6076         valleyview_check_pctx(dev_priv);
6077
6078         gtfifodbg = I915_READ(GTFIFODBG);
6079         if (gtfifodbg) {
6080                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6081                                  gtfifodbg);
6082                 I915_WRITE(GTFIFODBG, gtfifodbg);
6083         }
6084
6085         /* If VLV, Forcewake all wells, else re-direct to regular path */
6086         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6087
6088         /*  Disable RC states. */
6089         I915_WRITE(GEN6_RC_CONTROL, 0);
6090
6091         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6092         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6093         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6094         I915_WRITE(GEN6_RP_UP_EI, 66000);
6095         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6096
6097         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6098
6099         I915_WRITE(GEN6_RP_CONTROL,
6100                    GEN6_RP_MEDIA_TURBO |
6101                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6102                    GEN6_RP_MEDIA_IS_GFX |
6103                    GEN6_RP_ENABLE |
6104                    GEN6_RP_UP_BUSY_AVG |
6105                    GEN6_RP_DOWN_IDLE_CONT);
6106
6107         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6108         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6109         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6110
6111         for_each_engine(engine, dev_priv, id)
6112                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6113
6114         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6115
6116         /* allows RC6 residency counter to work */
6117         I915_WRITE(VLV_COUNTER_CONTROL,
6118                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6119                                       VLV_RENDER_RC0_COUNT_EN |
6120                                       VLV_MEDIA_RC6_COUNT_EN |
6121                                       VLV_RENDER_RC6_COUNT_EN));
6122
6123         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6124                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6125
6126         intel_print_rc6_info(dev_priv, rc6_mode);
6127
6128         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6129
6130         /* Setting Fixed Bias */
6131         val = VLV_OVERRIDE_EN |
6132                   VLV_SOC_TDP_EN |
6133                   VLV_BIAS_CPU_125_SOC_875;
6134         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6135
6136         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6137
6138         /* RPS code assumes GPLL is used */
6139         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6140
6141         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6142         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6143
6144         reset_rps(dev_priv, valleyview_set_rps);
6145
6146         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6147 }
6148
6149 static unsigned long intel_pxfreq(u32 vidfreq)
6150 {
6151         unsigned long freq;
6152         int div = (vidfreq & 0x3f0000) >> 16;
6153         int post = (vidfreq & 0x3000) >> 12;
6154         int pre = (vidfreq & 0x7);
6155
6156         if (!pre)
6157                 return 0;
6158
6159         freq = ((div * 133333) / ((1<<post) * pre));
6160
6161         return freq;
6162 }
6163
6164 static const struct cparams {
6165         u16 i;
6166         u16 t;
6167         u16 m;
6168         u16 c;
6169 } cparams[] = {
6170         { 1, 1333, 301, 28664 },
6171         { 1, 1066, 294, 24460 },
6172         { 1, 800, 294, 25192 },
6173         { 0, 1333, 276, 27605 },
6174         { 0, 1066, 276, 27605 },
6175         { 0, 800, 231, 23784 },
6176 };
6177
6178 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6179 {
6180         u64 total_count, diff, ret;
6181         u32 count1, count2, count3, m = 0, c = 0;
6182         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6183         int i;
6184
6185         assert_spin_locked(&mchdev_lock);
6186
6187         diff1 = now - dev_priv->ips.last_time1;
6188
6189         /* Prevent division-by-zero if we are asking too fast.
6190          * Also, we don't get interesting results if we are polling
6191          * faster than once in 10ms, so just return the saved value
6192          * in such cases.
6193          */
6194         if (diff1 <= 10)
6195                 return dev_priv->ips.chipset_power;
6196
6197         count1 = I915_READ(DMIEC);
6198         count2 = I915_READ(DDREC);
6199         count3 = I915_READ(CSIEC);
6200
6201         total_count = count1 + count2 + count3;
6202
6203         /* FIXME: handle per-counter overflow */
6204         if (total_count < dev_priv->ips.last_count1) {
6205                 diff = ~0UL - dev_priv->ips.last_count1;
6206                 diff += total_count;
6207         } else {
6208                 diff = total_count - dev_priv->ips.last_count1;
6209         }
6210
6211         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6212                 if (cparams[i].i == dev_priv->ips.c_m &&
6213                     cparams[i].t == dev_priv->ips.r_t) {
6214                         m = cparams[i].m;
6215                         c = cparams[i].c;
6216                         break;
6217                 }
6218         }
6219
6220         diff = div_u64(diff, diff1);
6221         ret = ((m * diff) + c);
6222         ret = div_u64(ret, 10);
6223
6224         dev_priv->ips.last_count1 = total_count;
6225         dev_priv->ips.last_time1 = now;
6226
6227         dev_priv->ips.chipset_power = ret;
6228
6229         return ret;
6230 }
6231
6232 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6233 {
6234         unsigned long val;
6235
6236         if (INTEL_INFO(dev_priv)->gen != 5)
6237                 return 0;
6238
6239         spin_lock_irq(&mchdev_lock);
6240
6241         val = __i915_chipset_val(dev_priv);
6242
6243         spin_unlock_irq(&mchdev_lock);
6244
6245         return val;
6246 }
6247
6248 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6249 {
6250         unsigned long m, x, b;
6251         u32 tsfs;
6252
6253         tsfs = I915_READ(TSFS);
6254
6255         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6256         x = I915_READ8(TR1);
6257
6258         b = tsfs & TSFS_INTR_MASK;
6259
6260         return ((m * x) / 127) - b;
6261 }
6262
6263 static int _pxvid_to_vd(u8 pxvid)
6264 {
6265         if (pxvid == 0)
6266                 return 0;
6267
6268         if (pxvid >= 8 && pxvid < 31)
6269                 pxvid = 31;
6270
6271         return (pxvid + 2) * 125;
6272 }
6273
6274 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6275 {
6276         const int vd = _pxvid_to_vd(pxvid);
6277         const int vm = vd - 1125;
6278
6279         if (INTEL_INFO(dev_priv)->is_mobile)
6280                 return vm > 0 ? vm : 0;
6281
6282         return vd;
6283 }
6284
6285 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6286 {
6287         u64 now, diff, diffms;
6288         u32 count;
6289
6290         assert_spin_locked(&mchdev_lock);
6291
6292         now = ktime_get_raw_ns();
6293         diffms = now - dev_priv->ips.last_time2;
6294         do_div(diffms, NSEC_PER_MSEC);
6295
6296         /* Don't divide by 0 */
6297         if (!diffms)
6298                 return;
6299
6300         count = I915_READ(GFXEC);
6301
6302         if (count < dev_priv->ips.last_count2) {
6303                 diff = ~0UL - dev_priv->ips.last_count2;
6304                 diff += count;
6305         } else {
6306                 diff = count - dev_priv->ips.last_count2;
6307         }
6308
6309         dev_priv->ips.last_count2 = count;
6310         dev_priv->ips.last_time2 = now;
6311
6312         /* More magic constants... */
6313         diff = diff * 1181;
6314         diff = div_u64(diff, diffms * 10);
6315         dev_priv->ips.gfx_power = diff;
6316 }
6317
6318 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6319 {
6320         if (INTEL_INFO(dev_priv)->gen != 5)
6321                 return;
6322
6323         spin_lock_irq(&mchdev_lock);
6324
6325         __i915_update_gfx_val(dev_priv);
6326
6327         spin_unlock_irq(&mchdev_lock);
6328 }
6329
6330 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6331 {
6332         unsigned long t, corr, state1, corr2, state2;
6333         u32 pxvid, ext_v;
6334
6335         assert_spin_locked(&mchdev_lock);
6336
6337         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6338         pxvid = (pxvid >> 24) & 0x7f;
6339         ext_v = pvid_to_extvid(dev_priv, pxvid);
6340
6341         state1 = ext_v;
6342
6343         t = i915_mch_val(dev_priv);
6344
6345         /* Revel in the empirically derived constants */
6346
6347         /* Correction factor in 1/100000 units */
6348         if (t > 80)
6349                 corr = ((t * 2349) + 135940);
6350         else if (t >= 50)
6351                 corr = ((t * 964) + 29317);
6352         else /* < 50 */
6353                 corr = ((t * 301) + 1004);
6354
6355         corr = corr * ((150142 * state1) / 10000 - 78642);
6356         corr /= 100000;
6357         corr2 = (corr * dev_priv->ips.corr);
6358
6359         state2 = (corr2 * state1) / 10000;
6360         state2 /= 100; /* convert to mW */
6361
6362         __i915_update_gfx_val(dev_priv);
6363
6364         return dev_priv->ips.gfx_power + state2;
6365 }
6366
6367 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6368 {
6369         unsigned long val;
6370
6371         if (INTEL_INFO(dev_priv)->gen != 5)
6372                 return 0;
6373
6374         spin_lock_irq(&mchdev_lock);
6375
6376         val = __i915_gfx_val(dev_priv);
6377
6378         spin_unlock_irq(&mchdev_lock);
6379
6380         return val;
6381 }
6382
6383 /**
6384  * i915_read_mch_val - return value for IPS use
6385  *
6386  * Calculate and return a value for the IPS driver to use when deciding whether
6387  * we have thermal and power headroom to increase CPU or GPU power budget.
6388  */
6389 unsigned long i915_read_mch_val(void)
6390 {
6391         struct drm_i915_private *dev_priv;
6392         unsigned long chipset_val, graphics_val, ret = 0;
6393
6394         spin_lock_irq(&mchdev_lock);
6395         if (!i915_mch_dev)
6396                 goto out_unlock;
6397         dev_priv = i915_mch_dev;
6398
6399         chipset_val = __i915_chipset_val(dev_priv);
6400         graphics_val = __i915_gfx_val(dev_priv);
6401
6402         ret = chipset_val + graphics_val;
6403
6404 out_unlock:
6405         spin_unlock_irq(&mchdev_lock);
6406
6407         return ret;
6408 }
6409 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6410
6411 /**
6412  * i915_gpu_raise - raise GPU frequency limit
6413  *
6414  * Raise the limit; IPS indicates we have thermal headroom.
6415  */
6416 bool i915_gpu_raise(void)
6417 {
6418         struct drm_i915_private *dev_priv;
6419         bool ret = true;
6420
6421         spin_lock_irq(&mchdev_lock);
6422         if (!i915_mch_dev) {
6423                 ret = false;
6424                 goto out_unlock;
6425         }
6426         dev_priv = i915_mch_dev;
6427
6428         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6429                 dev_priv->ips.max_delay--;
6430
6431 out_unlock:
6432         spin_unlock_irq(&mchdev_lock);
6433
6434         return ret;
6435 }
6436 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6437
6438 /**
6439  * i915_gpu_lower - lower GPU frequency limit
6440  *
6441  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6442  * frequency maximum.
6443  */
6444 bool i915_gpu_lower(void)
6445 {
6446         struct drm_i915_private *dev_priv;
6447         bool ret = true;
6448
6449         spin_lock_irq(&mchdev_lock);
6450         if (!i915_mch_dev) {
6451                 ret = false;
6452                 goto out_unlock;
6453         }
6454         dev_priv = i915_mch_dev;
6455
6456         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6457                 dev_priv->ips.max_delay++;
6458
6459 out_unlock:
6460         spin_unlock_irq(&mchdev_lock);
6461
6462         return ret;
6463 }
6464 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6465
6466 /**
6467  * i915_gpu_busy - indicate GPU business to IPS
6468  *
6469  * Tell the IPS driver whether or not the GPU is busy.
6470  */
6471 bool i915_gpu_busy(void)
6472 {
6473         bool ret = false;
6474
6475         spin_lock_irq(&mchdev_lock);
6476         if (i915_mch_dev)
6477                 ret = i915_mch_dev->gt.awake;
6478         spin_unlock_irq(&mchdev_lock);
6479
6480         return ret;
6481 }
6482 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6483
6484 /**
6485  * i915_gpu_turbo_disable - disable graphics turbo
6486  *
6487  * Disable graphics turbo by resetting the max frequency and setting the
6488  * current frequency to the default.
6489  */
6490 bool i915_gpu_turbo_disable(void)
6491 {
6492         struct drm_i915_private *dev_priv;
6493         bool ret = true;
6494
6495         spin_lock_irq(&mchdev_lock);
6496         if (!i915_mch_dev) {
6497                 ret = false;
6498                 goto out_unlock;
6499         }
6500         dev_priv = i915_mch_dev;
6501
6502         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6503
6504         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6505                 ret = false;
6506
6507 out_unlock:
6508         spin_unlock_irq(&mchdev_lock);
6509
6510         return ret;
6511 }
6512 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6513
6514 /**
6515  * Tells the intel_ips driver that the i915 driver is now loaded, if
6516  * IPS got loaded first.
6517  *
6518  * This awkward dance is so that neither module has to depend on the
6519  * other in order for IPS to do the appropriate communication of
6520  * GPU turbo limits to i915.
6521  */
6522 static void
6523 ips_ping_for_i915_load(void)
6524 {
6525         void (*link)(void);
6526
6527         link = symbol_get(ips_link_to_i915_driver);
6528         if (link) {
6529                 link();
6530                 symbol_put(ips_link_to_i915_driver);
6531         }
6532 }
6533
6534 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6535 {
6536         /* We only register the i915 ips part with intel-ips once everything is
6537          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6538         spin_lock_irq(&mchdev_lock);
6539         i915_mch_dev = dev_priv;
6540         spin_unlock_irq(&mchdev_lock);
6541
6542         ips_ping_for_i915_load();
6543 }
6544
6545 void intel_gpu_ips_teardown(void)
6546 {
6547         spin_lock_irq(&mchdev_lock);
6548         i915_mch_dev = NULL;
6549         spin_unlock_irq(&mchdev_lock);
6550 }
6551
6552 static void intel_init_emon(struct drm_i915_private *dev_priv)
6553 {
6554         u32 lcfuse;
6555         u8 pxw[16];
6556         int i;
6557
6558         /* Disable to program */
6559         I915_WRITE(ECR, 0);
6560         POSTING_READ(ECR);
6561
6562         /* Program energy weights for various events */
6563         I915_WRITE(SDEW, 0x15040d00);
6564         I915_WRITE(CSIEW0, 0x007f0000);
6565         I915_WRITE(CSIEW1, 0x1e220004);
6566         I915_WRITE(CSIEW2, 0x04000004);
6567
6568         for (i = 0; i < 5; i++)
6569                 I915_WRITE(PEW(i), 0);
6570         for (i = 0; i < 3; i++)
6571                 I915_WRITE(DEW(i), 0);
6572
6573         /* Program P-state weights to account for frequency power adjustment */
6574         for (i = 0; i < 16; i++) {
6575                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6576                 unsigned long freq = intel_pxfreq(pxvidfreq);
6577                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6578                         PXVFREQ_PX_SHIFT;
6579                 unsigned long val;
6580
6581                 val = vid * vid;
6582                 val *= (freq / 1000);
6583                 val *= 255;
6584                 val /= (127*127*900);
6585                 if (val > 0xff)
6586                         DRM_ERROR("bad pxval: %ld\n", val);
6587                 pxw[i] = val;
6588         }
6589         /* Render standby states get 0 weight */
6590         pxw[14] = 0;
6591         pxw[15] = 0;
6592
6593         for (i = 0; i < 4; i++) {
6594                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6595                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6596                 I915_WRITE(PXW(i), val);
6597         }
6598
6599         /* Adjust magic regs to magic values (more experimental results) */
6600         I915_WRITE(OGW0, 0);
6601         I915_WRITE(OGW1, 0);
6602         I915_WRITE(EG0, 0x00007f00);
6603         I915_WRITE(EG1, 0x0000000e);
6604         I915_WRITE(EG2, 0x000e0000);
6605         I915_WRITE(EG3, 0x68000300);
6606         I915_WRITE(EG4, 0x42000000);
6607         I915_WRITE(EG5, 0x00140031);
6608         I915_WRITE(EG6, 0);
6609         I915_WRITE(EG7, 0);
6610
6611         for (i = 0; i < 8; i++)
6612                 I915_WRITE(PXWL(i), 0);
6613
6614         /* Enable PMON + select events */
6615         I915_WRITE(ECR, 0x80000019);
6616
6617         lcfuse = I915_READ(LCFUSE02);
6618
6619         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6620 }
6621
6622 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6623 {
6624         /*
6625          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6626          * requirement.
6627          */
6628         if (!i915.enable_rc6) {
6629                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6630                 intel_runtime_pm_get(dev_priv);
6631         }
6632
6633         mutex_lock(&dev_priv->drm.struct_mutex);
6634         mutex_lock(&dev_priv->rps.hw_lock);
6635
6636         /* Initialize RPS limits (for userspace) */
6637         if (IS_CHERRYVIEW(dev_priv))
6638                 cherryview_init_gt_powersave(dev_priv);
6639         else if (IS_VALLEYVIEW(dev_priv))
6640                 valleyview_init_gt_powersave(dev_priv);
6641         else if (INTEL_GEN(dev_priv) >= 6)
6642                 gen6_init_rps_frequencies(dev_priv);
6643
6644         /* Derive initial user preferences/limits from the hardware limits */
6645         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6646         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6647
6648         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6649         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6650
6651         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6652                 dev_priv->rps.min_freq_softlimit =
6653                         max_t(int,
6654                               dev_priv->rps.efficient_freq,
6655                               intel_freq_opcode(dev_priv, 450));
6656
6657         /* After setting max-softlimit, find the overclock max freq */
6658         if (IS_GEN6(dev_priv) ||
6659             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6660                 u32 params = 0;
6661
6662                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6663                 if (params & BIT(31)) { /* OC supported */
6664                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6665                                          (dev_priv->rps.max_freq & 0xff) * 50,
6666                                          (params & 0xff) * 50);
6667                         dev_priv->rps.max_freq = params & 0xff;
6668                 }
6669         }
6670
6671         /* Finally allow us to boost to max by default */
6672         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6673
6674         mutex_unlock(&dev_priv->rps.hw_lock);
6675         mutex_unlock(&dev_priv->drm.struct_mutex);
6676
6677         intel_autoenable_gt_powersave(dev_priv);
6678 }
6679
6680 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6681 {
6682         if (IS_VALLEYVIEW(dev_priv))
6683                 valleyview_cleanup_gt_powersave(dev_priv);
6684
6685         if (!i915.enable_rc6)
6686                 intel_runtime_pm_put(dev_priv);
6687 }
6688
6689 /**
6690  * intel_suspend_gt_powersave - suspend PM work and helper threads
6691  * @dev_priv: i915 device
6692  *
6693  * We don't want to disable RC6 or other features here, we just want
6694  * to make sure any work we've queued has finished and won't bother
6695  * us while we're suspended.
6696  */
6697 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6698 {
6699         if (INTEL_GEN(dev_priv) < 6)
6700                 return;
6701
6702         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6703                 intel_runtime_pm_put(dev_priv);
6704
6705         /* gen6_rps_idle() will be called later to disable interrupts */
6706 }
6707
6708 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6709 {
6710         dev_priv->rps.enabled = true; /* force disabling */
6711         intel_disable_gt_powersave(dev_priv);
6712
6713         gen6_reset_rps_interrupts(dev_priv);
6714 }
6715
6716 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6717 {
6718         if (!READ_ONCE(dev_priv->rps.enabled))
6719                 return;
6720
6721         mutex_lock(&dev_priv->rps.hw_lock);
6722
6723         if (INTEL_GEN(dev_priv) >= 9) {
6724                 gen9_disable_rc6(dev_priv);
6725                 gen9_disable_rps(dev_priv);
6726         } else if (IS_CHERRYVIEW(dev_priv)) {
6727                 cherryview_disable_rps(dev_priv);
6728         } else if (IS_VALLEYVIEW(dev_priv)) {
6729                 valleyview_disable_rps(dev_priv);
6730         } else if (INTEL_GEN(dev_priv) >= 6) {
6731                 gen6_disable_rps(dev_priv);
6732         }  else if (IS_IRONLAKE_M(dev_priv)) {
6733                 ironlake_disable_drps(dev_priv);
6734         }
6735
6736         dev_priv->rps.enabled = false;
6737         mutex_unlock(&dev_priv->rps.hw_lock);
6738 }
6739
6740 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6741 {
6742         /* We shouldn't be disabling as we submit, so this should be less
6743          * racy than it appears!
6744          */
6745         if (READ_ONCE(dev_priv->rps.enabled))
6746                 return;
6747
6748         /* Powersaving is controlled by the host when inside a VM */
6749         if (intel_vgpu_active(dev_priv))
6750                 return;
6751
6752         mutex_lock(&dev_priv->rps.hw_lock);
6753
6754         if (IS_CHERRYVIEW(dev_priv)) {
6755                 cherryview_enable_rps(dev_priv);
6756         } else if (IS_VALLEYVIEW(dev_priv)) {
6757                 valleyview_enable_rps(dev_priv);
6758         } else if (INTEL_GEN(dev_priv) >= 9) {
6759                 gen9_enable_rc6(dev_priv);
6760                 gen9_enable_rps(dev_priv);
6761                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6762                         gen6_update_ring_freq(dev_priv);
6763         } else if (IS_BROADWELL(dev_priv)) {
6764                 gen8_enable_rps(dev_priv);
6765                 gen6_update_ring_freq(dev_priv);
6766         } else if (INTEL_GEN(dev_priv) >= 6) {
6767                 gen6_enable_rps(dev_priv);
6768                 gen6_update_ring_freq(dev_priv);
6769         } else if (IS_IRONLAKE_M(dev_priv)) {
6770                 ironlake_enable_drps(dev_priv);
6771                 intel_init_emon(dev_priv);
6772         }
6773
6774         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6775         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6776
6777         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6778         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6779
6780         dev_priv->rps.enabled = true;
6781         mutex_unlock(&dev_priv->rps.hw_lock);
6782 }
6783
6784 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6785 {
6786         struct drm_i915_private *dev_priv =
6787                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6788         struct intel_engine_cs *rcs;
6789         struct drm_i915_gem_request *req;
6790
6791         if (READ_ONCE(dev_priv->rps.enabled))
6792                 goto out;
6793
6794         rcs = dev_priv->engine[RCS];
6795         if (rcs->last_retired_context)
6796                 goto out;
6797
6798         if (!rcs->init_context)
6799                 goto out;
6800
6801         mutex_lock(&dev_priv->drm.struct_mutex);
6802
6803         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6804         if (IS_ERR(req))
6805                 goto unlock;
6806
6807         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6808                 rcs->init_context(req);
6809
6810         /* Mark the device busy, calling intel_enable_gt_powersave() */
6811         i915_add_request_no_flush(req);
6812
6813 unlock:
6814         mutex_unlock(&dev_priv->drm.struct_mutex);
6815 out:
6816         intel_runtime_pm_put(dev_priv);
6817 }
6818
6819 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6820 {
6821         if (READ_ONCE(dev_priv->rps.enabled))
6822                 return;
6823
6824         if (IS_IRONLAKE_M(dev_priv)) {
6825                 ironlake_enable_drps(dev_priv);
6826                 intel_init_emon(dev_priv);
6827         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6828                 /*
6829                  * PCU communication is slow and this doesn't need to be
6830                  * done at any specific time, so do this out of our fast path
6831                  * to make resume and init faster.
6832                  *
6833                  * We depend on the HW RC6 power context save/restore
6834                  * mechanism when entering D3 through runtime PM suspend. So
6835                  * disable RPM until RPS/RC6 is properly setup. We can only
6836                  * get here via the driver load/system resume/runtime resume
6837                  * paths, so the _noresume version is enough (and in case of
6838                  * runtime resume it's necessary).
6839                  */
6840                 if (queue_delayed_work(dev_priv->wq,
6841                                        &dev_priv->rps.autoenable_work,
6842                                        round_jiffies_up_relative(HZ)))
6843                         intel_runtime_pm_get_noresume(dev_priv);
6844         }
6845 }
6846
6847 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6848 {
6849         /*
6850          * On Ibex Peak and Cougar Point, we need to disable clock
6851          * gating for the panel power sequencer or it will fail to
6852          * start up when no ports are active.
6853          */
6854         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6855 }
6856
6857 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6858 {
6859         enum pipe pipe;
6860
6861         for_each_pipe(dev_priv, pipe) {
6862                 I915_WRITE(DSPCNTR(pipe),
6863                            I915_READ(DSPCNTR(pipe)) |
6864                            DISPPLANE_TRICKLE_FEED_DISABLE);
6865
6866                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6867                 POSTING_READ(DSPSURF(pipe));
6868         }
6869 }
6870
6871 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6872 {
6873         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6874         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6875         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6876
6877         /*
6878          * Don't touch WM1S_LP_EN here.
6879          * Doing so could cause underruns.
6880          */
6881 }
6882
6883 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6884 {
6885         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6886
6887         /*
6888          * Required for FBC
6889          * WaFbcDisableDpfcClockGating:ilk
6890          */
6891         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6892                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6893                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6894
6895         I915_WRITE(PCH_3DCGDIS0,
6896                    MARIUNIT_CLOCK_GATE_DISABLE |
6897                    SVSMUNIT_CLOCK_GATE_DISABLE);
6898         I915_WRITE(PCH_3DCGDIS1,
6899                    VFMUNIT_CLOCK_GATE_DISABLE);
6900
6901         /*
6902          * According to the spec the following bits should be set in
6903          * order to enable memory self-refresh
6904          * The bit 22/21 of 0x42004
6905          * The bit 5 of 0x42020
6906          * The bit 15 of 0x45000
6907          */
6908         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6909                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6910                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6911         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6912         I915_WRITE(DISP_ARB_CTL,
6913                    (I915_READ(DISP_ARB_CTL) |
6914                     DISP_FBC_WM_DIS));
6915
6916         ilk_init_lp_watermarks(dev_priv);
6917
6918         /*
6919          * Based on the document from hardware guys the following bits
6920          * should be set unconditionally in order to enable FBC.
6921          * The bit 22 of 0x42000
6922          * The bit 22 of 0x42004
6923          * The bit 7,8,9 of 0x42020.
6924          */
6925         if (IS_IRONLAKE_M(dev_priv)) {
6926                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6927                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6928                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6929                            ILK_FBCQ_DIS);
6930                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6931                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6932                            ILK_DPARB_GATE);
6933         }
6934
6935         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6936
6937         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6938                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6939                    ILK_ELPIN_409_SELECT);
6940         I915_WRITE(_3D_CHICKEN2,
6941                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6942                    _3D_CHICKEN2_WM_READ_PIPELINED);
6943
6944         /* WaDisableRenderCachePipelinedFlush:ilk */
6945         I915_WRITE(CACHE_MODE_0,
6946                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6947
6948         /* WaDisable_RenderCache_OperationalFlush:ilk */
6949         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6950
6951         g4x_disable_trickle_feed(dev_priv);
6952
6953         ibx_init_clock_gating(dev_priv);
6954 }
6955
6956 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6957 {
6958         int pipe;
6959         uint32_t val;
6960
6961         /*
6962          * On Ibex Peak and Cougar Point, we need to disable clock
6963          * gating for the panel power sequencer or it will fail to
6964          * start up when no ports are active.
6965          */
6966         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6967                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6968                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6969         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6970                    DPLS_EDP_PPS_FIX_DIS);
6971         /* The below fixes the weird display corruption, a few pixels shifted
6972          * downward, on (only) LVDS of some HP laptops with IVY.
6973          */
6974         for_each_pipe(dev_priv, pipe) {
6975                 val = I915_READ(TRANS_CHICKEN2(pipe));
6976                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6977                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6978                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6979                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6980                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6981                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6982                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6983                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6984         }
6985         /* WADP0ClockGatingDisable */
6986         for_each_pipe(dev_priv, pipe) {
6987                 I915_WRITE(TRANS_CHICKEN1(pipe),
6988                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6989         }
6990 }
6991
6992 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
6993 {
6994         uint32_t tmp;
6995
6996         tmp = I915_READ(MCH_SSKPD);
6997         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6998                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6999                               tmp);
7000 }
7001
7002 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7003 {
7004         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7005
7006         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7007
7008         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7009                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7010                    ILK_ELPIN_409_SELECT);
7011
7012         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7013         I915_WRITE(_3D_CHICKEN,
7014                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7015
7016         /* WaDisable_RenderCache_OperationalFlush:snb */
7017         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7018
7019         /*
7020          * BSpec recoomends 8x4 when MSAA is used,
7021          * however in practice 16x4 seems fastest.
7022          *
7023          * Note that PS/WM thread counts depend on the WIZ hashing
7024          * disable bit, which we don't touch here, but it's good
7025          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7026          */
7027         I915_WRITE(GEN6_GT_MODE,
7028                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7029
7030         ilk_init_lp_watermarks(dev_priv);
7031
7032         I915_WRITE(CACHE_MODE_0,
7033                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7034
7035         I915_WRITE(GEN6_UCGCTL1,
7036                    I915_READ(GEN6_UCGCTL1) |
7037                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7038                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7039
7040         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7041          * gating disable must be set.  Failure to set it results in
7042          * flickering pixels due to Z write ordering failures after
7043          * some amount of runtime in the Mesa "fire" demo, and Unigine
7044          * Sanctuary and Tropics, and apparently anything else with
7045          * alpha test or pixel discard.
7046          *
7047          * According to the spec, bit 11 (RCCUNIT) must also be set,
7048          * but we didn't debug actual testcases to find it out.
7049          *
7050          * WaDisableRCCUnitClockGating:snb
7051          * WaDisableRCPBUnitClockGating:snb
7052          */
7053         I915_WRITE(GEN6_UCGCTL2,
7054                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7055                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7056
7057         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7058         I915_WRITE(_3D_CHICKEN3,
7059                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7060
7061         /*
7062          * Bspec says:
7063          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7064          * 3DSTATE_SF number of SF output attributes is more than 16."
7065          */
7066         I915_WRITE(_3D_CHICKEN3,
7067                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7068
7069         /*
7070          * According to the spec the following bits should be
7071          * set in order to enable memory self-refresh and fbc:
7072          * The bit21 and bit22 of 0x42000
7073          * The bit21 and bit22 of 0x42004
7074          * The bit5 and bit7 of 0x42020
7075          * The bit14 of 0x70180
7076          * The bit14 of 0x71180
7077          *
7078          * WaFbcAsynchFlipDisableFbcQueue:snb
7079          */
7080         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7081                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7082                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7083         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7084                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7085                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7086         I915_WRITE(ILK_DSPCLK_GATE_D,
7087                    I915_READ(ILK_DSPCLK_GATE_D) |
7088                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7089                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7090
7091         g4x_disable_trickle_feed(dev_priv);
7092
7093         cpt_init_clock_gating(dev_priv);
7094
7095         gen6_check_mch_setup(dev_priv);
7096 }
7097
7098 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7099 {
7100         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7101
7102         /*
7103          * WaVSThreadDispatchOverride:ivb,vlv
7104          *
7105          * This actually overrides the dispatch
7106          * mode for all thread types.
7107          */
7108         reg &= ~GEN7_FF_SCHED_MASK;
7109         reg |= GEN7_FF_TS_SCHED_HW;
7110         reg |= GEN7_FF_VS_SCHED_HW;
7111         reg |= GEN7_FF_DS_SCHED_HW;
7112
7113         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7114 }
7115
7116 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7117 {
7118         /*
7119          * TODO: this bit should only be enabled when really needed, then
7120          * disabled when not needed anymore in order to save power.
7121          */
7122         if (HAS_PCH_LPT_LP(dev_priv))
7123                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7124                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7125                            PCH_LP_PARTITION_LEVEL_DISABLE);
7126
7127         /* WADPOClockGatingDisable:hsw */
7128         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7129                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7130                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7131 }
7132
7133 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7134 {
7135         if (HAS_PCH_LPT_LP(dev_priv)) {
7136                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7137
7138                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7139                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7140         }
7141 }
7142
7143 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7144                                    int general_prio_credits,
7145                                    int high_prio_credits)
7146 {
7147         u32 misccpctl;
7148
7149         /* WaTempDisableDOPClkGating:bdw */
7150         misccpctl = I915_READ(GEN7_MISCCPCTL);
7151         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7152
7153         I915_WRITE(GEN8_L3SQCREG1,
7154                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7155                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7156
7157         /*
7158          * Wait at least 100 clocks before re-enabling clock gating.
7159          * See the definition of L3SQCREG1 in BSpec.
7160          */
7161         POSTING_READ(GEN8_L3SQCREG1);
7162         udelay(1);
7163         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7164 }
7165
7166 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7167 {
7168         gen9_init_clock_gating(dev_priv);
7169
7170         /* WaDisableSDEUnitClockGating:kbl */
7171         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7172                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7173                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7174
7175         /* WaDisableGamClockGating:kbl */
7176         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7177                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7178                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7179
7180         /* WaFbcNukeOnHostModify:kbl */
7181         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7182                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7183 }
7184
7185 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7186 {
7187         gen9_init_clock_gating(dev_priv);
7188
7189         /* WAC6entrylatency:skl */
7190         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7191                    FBC_LLC_FULLY_OPEN);
7192
7193         /* WaFbcNukeOnHostModify:skl */
7194         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7195                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7196 }
7197
7198 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7199 {
7200         enum pipe pipe;
7201
7202         ilk_init_lp_watermarks(dev_priv);
7203
7204         /* WaSwitchSolVfFArbitrationPriority:bdw */
7205         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7206
7207         /* WaPsrDPAMaskVBlankInSRD:bdw */
7208         I915_WRITE(CHICKEN_PAR1_1,
7209                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7210
7211         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7212         for_each_pipe(dev_priv, pipe) {
7213                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7214                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7215                            BDW_DPRS_MASK_VBLANK_SRD);
7216         }
7217
7218         /* WaVSRefCountFullforceMissDisable:bdw */
7219         /* WaDSRefCountFullforceMissDisable:bdw */
7220         I915_WRITE(GEN7_FF_THREAD_MODE,
7221                    I915_READ(GEN7_FF_THREAD_MODE) &
7222                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7223
7224         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7225                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7226
7227         /* WaDisableSDEUnitClockGating:bdw */
7228         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7229                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7230
7231         /* WaProgramL3SqcReg1Default:bdw */
7232         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7233
7234         /*
7235          * WaGttCachingOffByDefault:bdw
7236          * GTT cache may not work with big pages, so if those
7237          * are ever enabled GTT cache may need to be disabled.
7238          */
7239         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7240
7241         /* WaKVMNotificationOnConfigChange:bdw */
7242         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7243                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7244
7245         lpt_init_clock_gating(dev_priv);
7246 }
7247
7248 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7249 {
7250         ilk_init_lp_watermarks(dev_priv);
7251
7252         /* L3 caching of data atomics doesn't work -- disable it. */
7253         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7254         I915_WRITE(HSW_ROW_CHICKEN3,
7255                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7256
7257         /* This is required by WaCatErrorRejectionIssue:hsw */
7258         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7259                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7260                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7261
7262         /* WaVSRefCountFullforceMissDisable:hsw */
7263         I915_WRITE(GEN7_FF_THREAD_MODE,
7264                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7265
7266         /* WaDisable_RenderCache_OperationalFlush:hsw */
7267         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7268
7269         /* enable HiZ Raw Stall Optimization */
7270         I915_WRITE(CACHE_MODE_0_GEN7,
7271                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7272
7273         /* WaDisable4x2SubspanOptimization:hsw */
7274         I915_WRITE(CACHE_MODE_1,
7275                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7276
7277         /*
7278          * BSpec recommends 8x4 when MSAA is used,
7279          * however in practice 16x4 seems fastest.
7280          *
7281          * Note that PS/WM thread counts depend on the WIZ hashing
7282          * disable bit, which we don't touch here, but it's good
7283          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7284          */
7285         I915_WRITE(GEN7_GT_MODE,
7286                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7287
7288         /* WaSampleCChickenBitEnable:hsw */
7289         I915_WRITE(HALF_SLICE_CHICKEN3,
7290                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7291
7292         /* WaSwitchSolVfFArbitrationPriority:hsw */
7293         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7294
7295         /* WaRsPkgCStateDisplayPMReq:hsw */
7296         I915_WRITE(CHICKEN_PAR1_1,
7297                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7298
7299         lpt_init_clock_gating(dev_priv);
7300 }
7301
7302 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7303 {
7304         uint32_t snpcr;
7305
7306         ilk_init_lp_watermarks(dev_priv);
7307
7308         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7309
7310         /* WaDisableEarlyCull:ivb */
7311         I915_WRITE(_3D_CHICKEN3,
7312                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7313
7314         /* WaDisableBackToBackFlipFix:ivb */
7315         I915_WRITE(IVB_CHICKEN3,
7316                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7317                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7318
7319         /* WaDisablePSDDualDispatchEnable:ivb */
7320         if (IS_IVB_GT1(dev_priv))
7321                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7322                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7323
7324         /* WaDisable_RenderCache_OperationalFlush:ivb */
7325         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7326
7327         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7328         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7329                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7330
7331         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7332         I915_WRITE(GEN7_L3CNTLREG1,
7333                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7334         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7335                    GEN7_WA_L3_CHICKEN_MODE);
7336         if (IS_IVB_GT1(dev_priv))
7337                 I915_WRITE(GEN7_ROW_CHICKEN2,
7338                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7339         else {
7340                 /* must write both registers */
7341                 I915_WRITE(GEN7_ROW_CHICKEN2,
7342                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7343                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7344                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7345         }
7346
7347         /* WaForceL3Serialization:ivb */
7348         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7349                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7350
7351         /*
7352          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7353          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7354          */
7355         I915_WRITE(GEN6_UCGCTL2,
7356                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7357
7358         /* This is required by WaCatErrorRejectionIssue:ivb */
7359         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7360                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7361                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7362
7363         g4x_disable_trickle_feed(dev_priv);
7364
7365         gen7_setup_fixed_func_scheduler(dev_priv);
7366
7367         if (0) { /* causes HiZ corruption on ivb:gt1 */
7368                 /* enable HiZ Raw Stall Optimization */
7369                 I915_WRITE(CACHE_MODE_0_GEN7,
7370                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7371         }
7372
7373         /* WaDisable4x2SubspanOptimization:ivb */
7374         I915_WRITE(CACHE_MODE_1,
7375                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7376
7377         /*
7378          * BSpec recommends 8x4 when MSAA is used,
7379          * however in practice 16x4 seems fastest.
7380          *
7381          * Note that PS/WM thread counts depend on the WIZ hashing
7382          * disable bit, which we don't touch here, but it's good
7383          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7384          */
7385         I915_WRITE(GEN7_GT_MODE,
7386                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7387
7388         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7389         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7390         snpcr |= GEN6_MBC_SNPCR_MED;
7391         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7392
7393         if (!HAS_PCH_NOP(dev_priv))
7394                 cpt_init_clock_gating(dev_priv);
7395
7396         gen6_check_mch_setup(dev_priv);
7397 }
7398
7399 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7400 {
7401         /* WaDisableEarlyCull:vlv */
7402         I915_WRITE(_3D_CHICKEN3,
7403                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7404
7405         /* WaDisableBackToBackFlipFix:vlv */
7406         I915_WRITE(IVB_CHICKEN3,
7407                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7408                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7409
7410         /* WaPsdDispatchEnable:vlv */
7411         /* WaDisablePSDDualDispatchEnable:vlv */
7412         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7413                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7414                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7415
7416         /* WaDisable_RenderCache_OperationalFlush:vlv */
7417         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7418
7419         /* WaForceL3Serialization:vlv */
7420         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7421                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7422
7423         /* WaDisableDopClockGating:vlv */
7424         I915_WRITE(GEN7_ROW_CHICKEN2,
7425                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7426
7427         /* This is required by WaCatErrorRejectionIssue:vlv */
7428         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7429                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7430                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7431
7432         gen7_setup_fixed_func_scheduler(dev_priv);
7433
7434         /*
7435          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7436          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7437          */
7438         I915_WRITE(GEN6_UCGCTL2,
7439                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7440
7441         /* WaDisableL3Bank2xClockGate:vlv
7442          * Disabling L3 clock gating- MMIO 940c[25] = 1
7443          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7444         I915_WRITE(GEN7_UCGCTL4,
7445                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7446
7447         /*
7448          * BSpec says this must be set, even though
7449          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7450          */
7451         I915_WRITE(CACHE_MODE_1,
7452                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7453
7454         /*
7455          * BSpec recommends 8x4 when MSAA is used,
7456          * however in practice 16x4 seems fastest.
7457          *
7458          * Note that PS/WM thread counts depend on the WIZ hashing
7459          * disable bit, which we don't touch here, but it's good
7460          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7461          */
7462         I915_WRITE(GEN7_GT_MODE,
7463                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7464
7465         /*
7466          * WaIncreaseL3CreditsForVLVB0:vlv
7467          * This is the hardware default actually.
7468          */
7469         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7470
7471         /*
7472          * WaDisableVLVClockGating_VBIIssue:vlv
7473          * Disable clock gating on th GCFG unit to prevent a delay
7474          * in the reporting of vblank events.
7475          */
7476         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7477 }
7478
7479 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7480 {
7481         /* WaVSRefCountFullforceMissDisable:chv */
7482         /* WaDSRefCountFullforceMissDisable:chv */
7483         I915_WRITE(GEN7_FF_THREAD_MODE,
7484                    I915_READ(GEN7_FF_THREAD_MODE) &
7485                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7486
7487         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7488         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7489                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7490
7491         /* WaDisableCSUnitClockGating:chv */
7492         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7493                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7494
7495         /* WaDisableSDEUnitClockGating:chv */
7496         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7497                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7498
7499         /*
7500          * WaProgramL3SqcReg1Default:chv
7501          * See gfxspecs/Related Documents/Performance Guide/
7502          * LSQC Setting Recommendations.
7503          */
7504         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7505
7506         /*
7507          * GTT cache may not work with big pages, so if those
7508          * are ever enabled GTT cache may need to be disabled.
7509          */
7510         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7511 }
7512
7513 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7514 {
7515         uint32_t dspclk_gate;
7516
7517         I915_WRITE(RENCLK_GATE_D1, 0);
7518         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7519                    GS_UNIT_CLOCK_GATE_DISABLE |
7520                    CL_UNIT_CLOCK_GATE_DISABLE);
7521         I915_WRITE(RAMCLK_GATE_D, 0);
7522         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7523                 OVRUNIT_CLOCK_GATE_DISABLE |
7524                 OVCUNIT_CLOCK_GATE_DISABLE;
7525         if (IS_GM45(dev_priv))
7526                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7527         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7528
7529         /* WaDisableRenderCachePipelinedFlush */
7530         I915_WRITE(CACHE_MODE_0,
7531                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7532
7533         /* WaDisable_RenderCache_OperationalFlush:g4x */
7534         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7535
7536         g4x_disable_trickle_feed(dev_priv);
7537 }
7538
7539 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7540 {
7541         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7542         I915_WRITE(RENCLK_GATE_D2, 0);
7543         I915_WRITE(DSPCLK_GATE_D, 0);
7544         I915_WRITE(RAMCLK_GATE_D, 0);
7545         I915_WRITE16(DEUC, 0);
7546         I915_WRITE(MI_ARB_STATE,
7547                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7548
7549         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7550         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7551 }
7552
7553 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7554 {
7555         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7556                    I965_RCC_CLOCK_GATE_DISABLE |
7557                    I965_RCPB_CLOCK_GATE_DISABLE |
7558                    I965_ISC_CLOCK_GATE_DISABLE |
7559                    I965_FBC_CLOCK_GATE_DISABLE);
7560         I915_WRITE(RENCLK_GATE_D2, 0);
7561         I915_WRITE(MI_ARB_STATE,
7562                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7563
7564         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7565         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7566 }
7567
7568 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7569 {
7570         u32 dstate = I915_READ(D_STATE);
7571
7572         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7573                 DSTATE_DOT_CLOCK_GATING;
7574         I915_WRITE(D_STATE, dstate);
7575
7576         if (IS_PINEVIEW(dev_priv))
7577                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7578
7579         /* IIR "flip pending" means done if this bit is set */
7580         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7581
7582         /* interrupts should cause a wake up from C3 */
7583         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7584
7585         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7586         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7587
7588         I915_WRITE(MI_ARB_STATE,
7589                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7590 }
7591
7592 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7593 {
7594         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7595
7596         /* interrupts should cause a wake up from C3 */
7597         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7598                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7599
7600         I915_WRITE(MEM_MODE,
7601                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7602 }
7603
7604 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7605 {
7606         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7607
7608         I915_WRITE(MEM_MODE,
7609                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7610                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7611 }
7612
7613 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7614 {
7615         dev_priv->display.init_clock_gating(dev_priv);
7616 }
7617
7618 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7619 {
7620         if (HAS_PCH_LPT(dev_priv))
7621                 lpt_suspend_hw(dev_priv);
7622 }
7623
7624 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7625 {
7626         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7627 }
7628
7629 /**
7630  * intel_init_clock_gating_hooks - setup the clock gating hooks
7631  * @dev_priv: device private
7632  *
7633  * Setup the hooks that configure which clocks of a given platform can be
7634  * gated and also apply various GT and display specific workarounds for these
7635  * platforms. Note that some GT specific workarounds are applied separately
7636  * when GPU contexts or batchbuffers start their execution.
7637  */
7638 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7639 {
7640         if (IS_SKYLAKE(dev_priv))
7641                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7642         else if (IS_KABYLAKE(dev_priv))
7643                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7644         else if (IS_GEN9_LP(dev_priv))
7645                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7646         else if (IS_BROADWELL(dev_priv))
7647                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7648         else if (IS_CHERRYVIEW(dev_priv))
7649                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7650         else if (IS_HASWELL(dev_priv))
7651                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7652         else if (IS_IVYBRIDGE(dev_priv))
7653                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7654         else if (IS_VALLEYVIEW(dev_priv))
7655                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7656         else if (IS_GEN6(dev_priv))
7657                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7658         else if (IS_GEN5(dev_priv))
7659                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7660         else if (IS_G4X(dev_priv))
7661                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7662         else if (IS_I965GM(dev_priv))
7663                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7664         else if (IS_I965G(dev_priv))
7665                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7666         else if (IS_GEN3(dev_priv))
7667                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7668         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7669                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7670         else if (IS_GEN2(dev_priv))
7671                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7672         else {
7673                 MISSING_CASE(INTEL_DEVID(dev_priv));
7674                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7675         }
7676 }
7677
7678 /* Set up chip specific power management-related functions */
7679 void intel_init_pm(struct drm_i915_private *dev_priv)
7680 {
7681         intel_fbc_init(dev_priv);
7682
7683         /* For cxsr */
7684         if (IS_PINEVIEW(dev_priv))
7685                 i915_pineview_get_mem_freq(dev_priv);
7686         else if (IS_GEN5(dev_priv))
7687                 i915_ironlake_get_mem_freq(dev_priv);
7688
7689         /* For FIFO watermark updates */
7690         if (INTEL_GEN(dev_priv) >= 9) {
7691                 skl_setup_wm_latency(dev_priv);
7692                 dev_priv->display.initial_watermarks = skl_initial_wm;
7693                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
7694                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7695         } else if (HAS_PCH_SPLIT(dev_priv)) {
7696                 ilk_setup_wm_latency(dev_priv);
7697
7698                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7699                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7700                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7701                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7702                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7703                         dev_priv->display.compute_intermediate_wm =
7704                                 ilk_compute_intermediate_wm;
7705                         dev_priv->display.initial_watermarks =
7706                                 ilk_initial_watermarks;
7707                         dev_priv->display.optimize_watermarks =
7708                                 ilk_optimize_watermarks;
7709                 } else {
7710                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7711                                       "Disable CxSR\n");
7712                 }
7713         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7714                 vlv_setup_wm_latency(dev_priv);
7715                 dev_priv->display.update_wm = vlv_update_wm;
7716         } else if (IS_PINEVIEW(dev_priv)) {
7717                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7718                                             dev_priv->is_ddr3,
7719                                             dev_priv->fsb_freq,
7720                                             dev_priv->mem_freq)) {
7721                         DRM_INFO("failed to find known CxSR latency "
7722                                  "(found ddr%s fsb freq %d, mem freq %d), "
7723                                  "disabling CxSR\n",
7724                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7725                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7726                         /* Disable CxSR and never update its watermark again */
7727                         intel_set_memory_cxsr(dev_priv, false);
7728                         dev_priv->display.update_wm = NULL;
7729                 } else
7730                         dev_priv->display.update_wm = pineview_update_wm;
7731         } else if (IS_G4X(dev_priv)) {
7732                 dev_priv->display.update_wm = g4x_update_wm;
7733         } else if (IS_GEN4(dev_priv)) {
7734                 dev_priv->display.update_wm = i965_update_wm;
7735         } else if (IS_GEN3(dev_priv)) {
7736                 dev_priv->display.update_wm = i9xx_update_wm;
7737                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7738         } else if (IS_GEN2(dev_priv)) {
7739                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
7740                         dev_priv->display.update_wm = i845_update_wm;
7741                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7742                 } else {
7743                         dev_priv->display.update_wm = i9xx_update_wm;
7744                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7745                 }
7746         } else {
7747                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7748         }
7749 }
7750
7751 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7752 {
7753         uint32_t flags =
7754                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7755
7756         switch (flags) {
7757         case GEN6_PCODE_SUCCESS:
7758                 return 0;
7759         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7760         case GEN6_PCODE_ILLEGAL_CMD:
7761                 return -ENXIO;
7762         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7763         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7764                 return -EOVERFLOW;
7765         case GEN6_PCODE_TIMEOUT:
7766                 return -ETIMEDOUT;
7767         default:
7768                 MISSING_CASE(flags)
7769                 return 0;
7770         }
7771 }
7772
7773 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7774 {
7775         uint32_t flags =
7776                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7777
7778         switch (flags) {
7779         case GEN6_PCODE_SUCCESS:
7780                 return 0;
7781         case GEN6_PCODE_ILLEGAL_CMD:
7782                 return -ENXIO;
7783         case GEN7_PCODE_TIMEOUT:
7784                 return -ETIMEDOUT;
7785         case GEN7_PCODE_ILLEGAL_DATA:
7786                 return -EINVAL;
7787         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7788                 return -EOVERFLOW;
7789         default:
7790                 MISSING_CASE(flags);
7791                 return 0;
7792         }
7793 }
7794
7795 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7796 {
7797         int status;
7798
7799         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7800
7801         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7802          * use te fw I915_READ variants to reduce the amount of work
7803          * required when reading/writing.
7804          */
7805
7806         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7807                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7808                 return -EAGAIN;
7809         }
7810
7811         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7812         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7813         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7814
7815         if (intel_wait_for_register_fw(dev_priv,
7816                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7817                                        500)) {
7818                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7819                 return -ETIMEDOUT;
7820         }
7821
7822         *val = I915_READ_FW(GEN6_PCODE_DATA);
7823         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7824
7825         if (INTEL_GEN(dev_priv) > 6)
7826                 status = gen7_check_mailbox_status(dev_priv);
7827         else
7828                 status = gen6_check_mailbox_status(dev_priv);
7829
7830         if (status) {
7831                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7832                                  status);
7833                 return status;
7834         }
7835
7836         return 0;
7837 }
7838
7839 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7840                             u32 mbox, u32 val)
7841 {
7842         int status;
7843
7844         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7845
7846         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7847          * use te fw I915_READ variants to reduce the amount of work
7848          * required when reading/writing.
7849          */
7850
7851         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7852                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7853                 return -EAGAIN;
7854         }
7855
7856         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7857         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7858         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7859
7860         if (intel_wait_for_register_fw(dev_priv,
7861                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7862                                        500)) {
7863                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7864                 return -ETIMEDOUT;
7865         }
7866
7867         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7868
7869         if (INTEL_GEN(dev_priv) > 6)
7870                 status = gen7_check_mailbox_status(dev_priv);
7871         else
7872                 status = gen6_check_mailbox_status(dev_priv);
7873
7874         if (status) {
7875                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7876                                  status);
7877                 return status;
7878         }
7879
7880         return 0;
7881 }
7882
7883 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
7884                                   u32 request, u32 reply_mask, u32 reply,
7885                                   u32 *status)
7886 {
7887         u32 val = request;
7888
7889         *status = sandybridge_pcode_read(dev_priv, mbox, &val);
7890
7891         return *status || ((val & reply_mask) == reply);
7892 }
7893
7894 /**
7895  * skl_pcode_request - send PCODE request until acknowledgment
7896  * @dev_priv: device private
7897  * @mbox: PCODE mailbox ID the request is targeted for
7898  * @request: request ID
7899  * @reply_mask: mask used to check for request acknowledgment
7900  * @reply: value used to check for request acknowledgment
7901  * @timeout_base_ms: timeout for polling with preemption enabled
7902  *
7903  * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
7904  * reports an error or an overall timeout of @timeout_base_ms+10 ms expires.
7905  * The request is acknowledged once the PCODE reply dword equals @reply after
7906  * applying @reply_mask. Polling is first attempted with preemption enabled
7907  * for @timeout_base_ms and if this times out for another 10 ms with
7908  * preemption disabled.
7909  *
7910  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
7911  * other error as reported by PCODE.
7912  */
7913 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
7914                       u32 reply_mask, u32 reply, int timeout_base_ms)
7915 {
7916         u32 status;
7917         int ret;
7918
7919         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7920
7921 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
7922                                    &status)
7923
7924         /*
7925          * Prime the PCODE by doing a request first. Normally it guarantees
7926          * that a subsequent request, at most @timeout_base_ms later, succeeds.
7927          * _wait_for() doesn't guarantee when its passed condition is evaluated
7928          * first, so send the first request explicitly.
7929          */
7930         if (COND) {
7931                 ret = 0;
7932                 goto out;
7933         }
7934         ret = _wait_for(COND, timeout_base_ms * 1000, 10);
7935         if (!ret)
7936                 goto out;
7937
7938         /*
7939          * The above can time out if the number of requests was low (2 in the
7940          * worst case) _and_ PCODE was busy for some reason even after a
7941          * (queued) request and @timeout_base_ms delay. As a workaround retry
7942          * the poll with preemption disabled to maximize the number of
7943          * requests. Increase the timeout from @timeout_base_ms to 10ms to
7944          * account for interrupts that could reduce the number of these
7945          * requests.
7946          */
7947         DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
7948         WARN_ON_ONCE(timeout_base_ms > 3);
7949         preempt_disable();
7950         ret = wait_for_atomic(COND, 10);
7951         preempt_enable();
7952
7953 out:
7954         return ret ? ret : status;
7955 #undef COND
7956 }
7957
7958 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7959 {
7960         /*
7961          * N = val - 0xb7
7962          * Slow = Fast = GPLL ref * N
7963          */
7964         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7965 }
7966
7967 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7968 {
7969         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7970 }
7971
7972 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7973 {
7974         /*
7975          * N = val / 2
7976          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7977          */
7978         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7979 }
7980
7981 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7982 {
7983         /* CHV needs even values */
7984         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7985 }
7986
7987 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7988 {
7989         if (IS_GEN9(dev_priv))
7990                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7991                                          GEN9_FREQ_SCALER);
7992         else if (IS_CHERRYVIEW(dev_priv))
7993                 return chv_gpu_freq(dev_priv, val);
7994         else if (IS_VALLEYVIEW(dev_priv))
7995                 return byt_gpu_freq(dev_priv, val);
7996         else
7997                 return val * GT_FREQUENCY_MULTIPLIER;
7998 }
7999
8000 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
8001 {
8002         if (IS_GEN9(dev_priv))
8003                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
8004                                          GT_FREQUENCY_MULTIPLIER);
8005         else if (IS_CHERRYVIEW(dev_priv))
8006                 return chv_freq_opcode(dev_priv, val);
8007         else if (IS_VALLEYVIEW(dev_priv))
8008                 return byt_freq_opcode(dev_priv, val);
8009         else
8010                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
8011 }
8012
8013 struct request_boost {
8014         struct work_struct work;
8015         struct drm_i915_gem_request *req;
8016 };
8017
8018 static void __intel_rps_boost_work(struct work_struct *work)
8019 {
8020         struct request_boost *boost = container_of(work, struct request_boost, work);
8021         struct drm_i915_gem_request *req = boost->req;
8022
8023         if (!i915_gem_request_completed(req))
8024                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
8025
8026         i915_gem_request_put(req);
8027         kfree(boost);
8028 }
8029
8030 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8031 {
8032         struct request_boost *boost;
8033
8034         if (req == NULL || INTEL_GEN(req->i915) < 6)
8035                 return;
8036
8037         if (i915_gem_request_completed(req))
8038                 return;
8039
8040         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8041         if (boost == NULL)
8042                 return;
8043
8044         boost->req = i915_gem_request_get(req);
8045
8046         INIT_WORK(&boost->work, __intel_rps_boost_work);
8047         queue_work(req->i915->wq, &boost->work);
8048 }
8049
8050 void intel_pm_setup(struct drm_i915_private *dev_priv)
8051 {
8052         mutex_init(&dev_priv->rps.hw_lock);
8053         spin_lock_init(&dev_priv->rps.client_lock);
8054
8055         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8056                           __intel_autoenable_gt_powersave);
8057         INIT_LIST_HEAD(&dev_priv->rps.clients);
8058
8059         dev_priv->pm.suspended = false;
8060         atomic_set(&dev_priv->pm.wakeref_count, 0);
8061 }