drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * DOC: RC6
  36  *
  37  * RC6 is a special power stage which allows the GPU to enter an very
  38  * low-voltage mode when idle, using down to 0V while at this stage.  This
  39  * stage is entered automatically when the GPU is idle when RC6 support is
  40  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  41  *
  42  * There are different RC6 modes available in Intel GPU, which differentiate
  43  * among each other with the latency required to enter and leave RC6 and
  44  * voltage consumed by the GPU in different states.
  45  *
  46  * The combination of the following flags define which states GPU is allowed
  47  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  48  * RC6pp is deepest RC6. Their support by hardware varies according to the
  49  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  50  * which brings the most power savings; deeper states save more power, but
  51  * require higher latency to switch to and wake up.
  52  */
  53 #define INTEL_RC6_ENABLE                        (1<<0)
  54 #define INTEL_RC6p_ENABLE                       (1<<1)
  55 #define INTEL_RC6pp_ENABLE                      (1<<2)
  56
  57 static void bxt_init_clock_gating(struct drm_device *dev)
  58 {
  59         struct drm_i915_private *dev_priv = dev->dev_private;
  60
  61         /* WaDisableSDEUnitClockGating:bxt */
  62         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  63                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  64
  65         /*
  66          * FIXME:
  67          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  68          */
  69         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  70                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  71
  72         /*
  73          * Wa: Backlight PWM may stop in the asserted state, causing backlight
  74          * to stay fully on.
  75          */
  76         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
  77                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
  78                            PWM1_GATING_DIS | PWM2_GATING_DIS);
  79 }
  80
  81 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84         u32 tmp;
  85
  86         tmp = I915_READ(CLKCFG);
  87
  88         switch (tmp & CLKCFG_FSB_MASK) {
  89         case CLKCFG_FSB_533:
  90                 dev_priv->fsb_freq = 533; /* 133*4 */
  91                 break;
  92         case CLKCFG_FSB_800:
  93                 dev_priv->fsb_freq = 800; /* 200*4 */
  94                 break;
  95         case CLKCFG_FSB_667:
  96                 dev_priv->fsb_freq =  667; /* 167*4 */
  97                 break;
  98         case CLKCFG_FSB_400:
  99                 dev_priv->fsb_freq = 400; /* 100*4 */
 100                 break;
 101         }
 102
 103         switch (tmp & CLKCFG_MEM_MASK) {
 104         case CLKCFG_MEM_533:
 105                 dev_priv->mem_freq = 533;
 106                 break;
 107         case CLKCFG_MEM_667:
 108                 dev_priv->mem_freq = 667;
 109                 break;
 110         case CLKCFG_MEM_800:
 111                 dev_priv->mem_freq = 800;
 112                 break;
 113         }
 114
 115         /* detect pineview DDR3 setting */
 116         tmp = I915_READ(CSHRDDR3CTL);
 117         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 118 }
 119
 120 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         u16 ddrpll, csipll;
 124
 125         ddrpll = I915_READ16(DDRMPLL1);
 126         csipll = I915_READ16(CSIPLL0);
 127
 128         switch (ddrpll & 0xff) {
 129         case 0xc:
 130                 dev_priv->mem_freq = 800;
 131                 break;
 132         case 0x10:
 133                 dev_priv->mem_freq = 1066;
 134                 break;
 135         case 0x14:
 136                 dev_priv->mem_freq = 1333;
 137                 break;
 138         case 0x18:
 139                 dev_priv->mem_freq = 1600;
 140                 break;
 141         default:
 142                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 143                                  ddrpll & 0xff);
 144                 dev_priv->mem_freq = 0;
 145                 break;
 146         }
 147
 148         dev_priv->ips.r_t = dev_priv->mem_freq;
 149
 150         switch (csipll & 0x3ff) {
 151         case 0x00c:
 152                 dev_priv->fsb_freq = 3200;
 153                 break;
 154         case 0x00e:
 155                 dev_priv->fsb_freq = 3733;
 156                 break;
 157         case 0x010:
 158                 dev_priv->fsb_freq = 4266;
 159                 break;
 160         case 0x012:
 161                 dev_priv->fsb_freq = 4800;
 162                 break;
 163         case 0x014:
 164                 dev_priv->fsb_freq = 5333;
 165                 break;
 166         case 0x016:
 167                 dev_priv->fsb_freq = 5866;
 168                 break;
 169         case 0x018:
 170                 dev_priv->fsb_freq = 6400;
 171                 break;
 172         default:
 173                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 174                                  csipll & 0x3ff);
 175                 dev_priv->fsb_freq = 0;
 176                 break;
 177         }
 178
 179         if (dev_priv->fsb_freq == 3200) {
 180                 dev_priv->ips.c_m = 0;
 181         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 182                 dev_priv->ips.c_m = 1;
 183         } else {
 184                 dev_priv->ips.c_m = 2;
 185         }
 186 }
 187
 188 static const struct cxsr_latency cxsr_latency_table[] = {
 189         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 190         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 191         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 192         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 193         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 194
 195         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 196         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 197         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 198         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 199         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 200
 201         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 202         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 203         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 204         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 205         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 206
 207         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 208         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 209         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 210         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 211         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 212
 213         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 214         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 215         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 216         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 217         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 218
 219         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 220         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 221         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 222         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 223         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 224 };
 225
 226 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 227                                                          int is_ddr3,
 228                                                          int fsb,
 229                                                          int mem)
 230 {
 231         const struct cxsr_latency *latency;
 232         int i;
 233
 234         if (fsb == 0 || mem == 0)
 235                 return NULL;
 236
 237         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 238                 latency = &cxsr_latency_table[i];
 239                 if (is_desktop == latency->is_desktop &&
 240                     is_ddr3 == latency->is_ddr3 &&
 241                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 242                         return latency;
 243         }
 244
 245         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 246
 247         return NULL;
 248 }
 249
 250 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 251 {
 252         u32 val;
 253
 254         mutex_lock(&dev_priv->rps.hw_lock);
 255
 256         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 257         if (enable)
 258                 val &= ~FORCE_DDR_HIGH_FREQ;
 259         else
 260                 val |= FORCE_DDR_HIGH_FREQ;
 261         val &= ~FORCE_DDR_LOW_FREQ;
 262         val |= FORCE_DDR_FREQ_REQ_ACK;
 263         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 264
 265         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 266                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 267                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 268
 269         mutex_unlock(&dev_priv->rps.hw_lock);
 270 }
 271
 272 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 273 {
 274         u32 val;
 275
 276         mutex_lock(&dev_priv->rps.hw_lock);
 277
 278         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 279         if (enable)
 280                 val |= DSP_MAXFIFO_PM5_ENABLE;
 281         else
 282                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 283         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 284
 285         mutex_unlock(&dev_priv->rps.hw_lock);
 286 }
 287
 288 #define FW_WM(value, plane) \
 289         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 290
 291 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 292 {
 293         struct drm_device *dev = dev_priv->dev;
 294         u32 val;
 295
 296         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 297                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 298                 POSTING_READ(FW_BLC_SELF_VLV);
 299                 dev_priv->wm.vlv.cxsr = enable;
 300         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 301                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 302                 POSTING_READ(FW_BLC_SELF);
 303         } else if (IS_PINEVIEW(dev)) {
 304                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 305                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 306                 I915_WRITE(DSPFW3, val);
 307                 POSTING_READ(DSPFW3);
 308         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 309                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 310                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 311                 I915_WRITE(FW_BLC_SELF, val);
 312                 POSTING_READ(FW_BLC_SELF);
 313         } else if (IS_I915GM(dev)) {
 314                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 315                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 316                 I915_WRITE(INSTPM, val);
 317                 POSTING_READ(INSTPM);
 318         } else {
 319                 return;
 320         }
 321
 322         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 323                       enable ? "enabled" : "disabled");
 324 }
 325
 326
 327 /*
 328  * Latency for FIFO fetches is dependent on several factors:
 329  *   - memory configuration (speed, channels)
 330  *   - chipset
 331  *   - current MCH state
 332  * It can be fairly high in some situations, so here we assume a fairly
 333  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 334  * set this value too high, the FIFO will fetch frequently to stay full)
 335  * and power consumption (set it too low to save power and we might see
 336  * FIFO underruns and display "flicker").
 337  *
 338  * A value of 5us seems to be a good balance; safe for very low end
 339  * platforms but not overly aggressive on lower latency configs.
 340  */
 341 static const int pessimal_latency_ns = 5000;
 342
 343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 344         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 345
 346 static int vlv_get_fifo_size(struct drm_device *dev,
 347                               enum pipe pipe, int plane)
 348 {
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         int sprite0_start, sprite1_start, size;
 351
 352         switch (pipe) {
 353                 uint32_t dsparb, dsparb2, dsparb3;
 354         case PIPE_A:
 355                 dsparb = I915_READ(DSPARB);
 356                 dsparb2 = I915_READ(DSPARB2);
 357                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 358                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 359                 break;
 360         case PIPE_B:
 361                 dsparb = I915_READ(DSPARB);
 362                 dsparb2 = I915_READ(DSPARB2);
 363                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 364                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 365                 break;
 366         case PIPE_C:
 367                 dsparb2 = I915_READ(DSPARB2);
 368                 dsparb3 = I915_READ(DSPARB3);
 369                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 370                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 371                 break;
 372         default:
 373                 return 0;
 374         }
 375
 376         switch (plane) {
 377         case 0:
 378                 size = sprite0_start;
 379                 break;
 380         case 1:
 381                 size = sprite1_start - sprite0_start;
 382                 break;
 383         case 2:
 384                 size = 512 - 1 - sprite1_start;
 385                 break;
 386         default:
 387                 return 0;
 388         }
 389
 390         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 391                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 392                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 393                       size);
 394
 395         return size;
 396 }
 397
 398 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 399 {
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         uint32_t dsparb = I915_READ(DSPARB);
 402         int size;
 403
 404         size = dsparb & 0x7f;
 405         if (plane)
 406                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 407
 408         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 409                       plane ? "B" : "A", size);
 410
 411         return size;
 412 }
 413
 414 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         uint32_t dsparb = I915_READ(DSPARB);
 418         int size;
 419
 420         size = dsparb & 0x1ff;
 421         if (plane)
 422                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 423         size >>= 1; /* Convert to cachelines */
 424
 425         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 426                       plane ? "B" : "A", size);
 427
 428         return size;
 429 }
 430
 431 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 432 {
 433         struct drm_i915_private *dev_priv = dev->dev_private;
 434         uint32_t dsparb = I915_READ(DSPARB);
 435         int size;
 436
 437         size = dsparb & 0x7f;
 438         size >>= 2; /* Convert to cachelines */
 439
 440         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 441                       plane ? "B" : "A",
 442                       size);
 443
 444         return size;
 445 }
 446
 447 /* Pineview has different values for various configs */
 448 static const struct intel_watermark_params pineview_display_wm = {
 449         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 450         .max_wm = PINEVIEW_MAX_WM,
 451         .default_wm = PINEVIEW_DFT_WM,
 452         .guard_size = PINEVIEW_GUARD_WM,
 453         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 454 };
 455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 456         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 457         .max_wm = PINEVIEW_MAX_WM,
 458         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 459         .guard_size = PINEVIEW_GUARD_WM,
 460         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 461 };
 462 static const struct intel_watermark_params pineview_cursor_wm = {
 463         .fifo_size = PINEVIEW_CURSOR_FIFO,
 464         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 465         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 466         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 467         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 468 };
 469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 470         .fifo_size = PINEVIEW_CURSOR_FIFO,
 471         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 472         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 473         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 474         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 475 };
 476 static const struct intel_watermark_params g4x_wm_info = {
 477         .fifo_size = G4X_FIFO_SIZE,
 478         .max_wm = G4X_MAX_WM,
 479         .default_wm = G4X_MAX_WM,
 480         .guard_size = 2,
 481         .cacheline_size = G4X_FIFO_LINE_SIZE,
 482 };
 483 static const struct intel_watermark_params g4x_cursor_wm_info = {
 484         .fifo_size = I965_CURSOR_FIFO,
 485         .max_wm = I965_CURSOR_MAX_WM,
 486         .default_wm = I965_CURSOR_DFT_WM,
 487         .guard_size = 2,
 488         .cacheline_size = G4X_FIFO_LINE_SIZE,
 489 };
 490 static const struct intel_watermark_params valleyview_wm_info = {
 491         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 492         .max_wm = VALLEYVIEW_MAX_WM,
 493         .default_wm = VALLEYVIEW_MAX_WM,
 494         .guard_size = 2,
 495         .cacheline_size = G4X_FIFO_LINE_SIZE,
 496 };
 497 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 498         .fifo_size = I965_CURSOR_FIFO,
 499         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 500         .default_wm = I965_CURSOR_DFT_WM,
 501         .guard_size = 2,
 502         .cacheline_size = G4X_FIFO_LINE_SIZE,
 503 };
 504 static const struct intel_watermark_params i965_cursor_wm_info = {
 505         .fifo_size = I965_CURSOR_FIFO,
 506         .max_wm = I965_CURSOR_MAX_WM,
 507         .default_wm = I965_CURSOR_DFT_WM,
 508         .guard_size = 2,
 509         .cacheline_size = I915_FIFO_LINE_SIZE,
 510 };
 511 static const struct intel_watermark_params i945_wm_info = {
 512         .fifo_size = I945_FIFO_SIZE,
 513         .max_wm = I915_MAX_WM,
 514         .default_wm = 1,
 515         .guard_size = 2,
 516         .cacheline_size = I915_FIFO_LINE_SIZE,
 517 };
 518 static const struct intel_watermark_params i915_wm_info = {
 519         .fifo_size = I915_FIFO_SIZE,
 520         .max_wm = I915_MAX_WM,
 521         .default_wm = 1,
 522         .guard_size = 2,
 523         .cacheline_size = I915_FIFO_LINE_SIZE,
 524 };
 525 static const struct intel_watermark_params i830_a_wm_info = {
 526         .fifo_size = I855GM_FIFO_SIZE,
 527         .max_wm = I915_MAX_WM,
 528         .default_wm = 1,
 529         .guard_size = 2,
 530         .cacheline_size = I830_FIFO_LINE_SIZE,
 531 };
 532 static const struct intel_watermark_params i830_bc_wm_info = {
 533         .fifo_size = I855GM_FIFO_SIZE,
 534         .max_wm = I915_MAX_WM/2,
 535         .default_wm = 1,
 536         .guard_size = 2,
 537         .cacheline_size = I830_FIFO_LINE_SIZE,
 538 };
 539 static const struct intel_watermark_params i845_wm_info = {
 540         .fifo_size = I830_FIFO_SIZE,
 541         .max_wm = I915_MAX_WM,
 542         .default_wm = 1,
 543         .guard_size = 2,
 544         .cacheline_size = I830_FIFO_LINE_SIZE,
 545 };
 546
 547 /**
 548  * intel_calculate_wm - calculate watermark level
 549  * @clock_in_khz: pixel clock
 550  * @wm: chip FIFO params
 551  * @pixel_size: display pixel size
 552  * @latency_ns: memory latency for the platform
 553  *
 554  * Calculate the watermark level (the level at which the display plane will
 555  * start fetching from memory again).  Each chip has a different display
 556  * FIFO size and allocation, so the caller needs to figure that out and pass
 557  * in the correct intel_watermark_params structure.
 558  *
 559  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 560  * on the pixel size.  When it reaches the watermark level, it'll start
 561  * fetching FIFO line sized based chunks from memory until the FIFO fills
 562  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 563  * will occur, and a display engine hang could result.
 564  */
 565 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 566                                         const struct intel_watermark_params *wm,
 567                                         int fifo_size,
 568                                         int pixel_size,
 569                                         unsigned long latency_ns)
 570 {
 571         long entries_required, wm_size;
 572
 573         /*
 574          * Note: we need to make sure we don't overflow for various clock &
 575          * latency values.
 576          * clocks go from a few thousand to several hundred thousand.
 577          * latency is usually a few thousand
 578          */
 579         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 580                 1000;
 581         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 582
 583         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 584
 585         wm_size = fifo_size - (entries_required + wm->guard_size);
 586
 587         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 588
 589         /* Don't promote wm_size to unsigned... */
 590         if (wm_size > (long)wm->max_wm)
 591                 wm_size = wm->max_wm;
 592         if (wm_size <= 0)
 593                 wm_size = wm->default_wm;
 594
 595         /*
 596          * Bspec seems to indicate that the value shouldn't be lower than
 597          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 598          * Lets go for 8 which is the burst size since certain platforms
 599          * already use a hardcoded 8 (which is what the spec says should be
 600          * done).
 601          */
 602         if (wm_size <= 8)
 603                 wm_size = 8;
 604
 605         return wm_size;
 606 }
 607
 608 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 609 {
 610         struct drm_crtc *crtc, *enabled = NULL;
 611
 612         for_each_crtc(dev, crtc) {
 613                 if (intel_crtc_active(crtc)) {
 614                         if (enabled)
 615                                 return NULL;
 616                         enabled = crtc;
 617                 }
 618         }
 619
 620         return enabled;
 621 }
 622
 623 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 624 {
 625         struct drm_device *dev = unused_crtc->dev;
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         struct drm_crtc *crtc;
 628         const struct cxsr_latency *latency;
 629         u32 reg;
 630         unsigned long wm;
 631
 632         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 633                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 634         if (!latency) {
 635                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 636                 intel_set_memory_cxsr(dev_priv, false);
 637                 return;
 638         }
 639
 640         crtc = single_enabled_crtc(dev);
 641         if (crtc) {
 642                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 643                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 644                 int clock = adjusted_mode->crtc_clock;
 645
 646                 /* Display SR */
 647                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 648                                         pineview_display_wm.fifo_size,
 649                                         pixel_size, latency->display_sr);
 650                 reg = I915_READ(DSPFW1);
 651                 reg &= ~DSPFW_SR_MASK;
 652                 reg |= FW_WM(wm, SR);
 653                 I915_WRITE(DSPFW1, reg);
 654                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 655
 656                 /* cursor SR */
 657                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 658                                         pineview_display_wm.fifo_size,
 659                                         pixel_size, latency->cursor_sr);
 660                 reg = I915_READ(DSPFW3);
 661                 reg &= ~DSPFW_CURSOR_SR_MASK;
 662                 reg |= FW_WM(wm, CURSOR_SR);
 663                 I915_WRITE(DSPFW3, reg);
 664
 665                 /* Display HPLL off SR */
 666                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 667                                         pineview_display_hplloff_wm.fifo_size,
 668                                         pixel_size, latency->display_hpll_disable);
 669                 reg = I915_READ(DSPFW3);
 670                 reg &= ~DSPFW_HPLL_SR_MASK;
 671                 reg |= FW_WM(wm, HPLL_SR);
 672                 I915_WRITE(DSPFW3, reg);
 673
 674                 /* cursor HPLL off SR */
 675                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 676                                         pineview_display_hplloff_wm.fifo_size,
 677                                         pixel_size, latency->cursor_hpll_disable);
 678                 reg = I915_READ(DSPFW3);
 679                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 680                 reg |= FW_WM(wm, HPLL_CURSOR);
 681                 I915_WRITE(DSPFW3, reg);
 682                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 683
 684                 intel_set_memory_cxsr(dev_priv, true);
 685         } else {
 686                 intel_set_memory_cxsr(dev_priv, false);
 687         }
 688 }
 689
 690 static bool g4x_compute_wm0(struct drm_device *dev,
 691                             int plane,
 692                             const struct intel_watermark_params *display,
 693                             int display_latency_ns,
 694                             const struct intel_watermark_params *cursor,
 695                             int cursor_latency_ns,
 696                             int *plane_wm,
 697                             int *cursor_wm)
 698 {
 699         struct drm_crtc *crtc;
 700         const struct drm_display_mode *adjusted_mode;
 701         int htotal, hdisplay, clock, pixel_size;
 702         int line_time_us, line_count;
 703         int entries, tlb_miss;
 704
 705         crtc = intel_get_crtc_for_plane(dev, plane);
 706         if (!intel_crtc_active(crtc)) {
 707                 *cursor_wm = cursor->guard_size;
 708                 *plane_wm = display->guard_size;
 709                 return false;
 710         }
 711
 712         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 713         clock = adjusted_mode->crtc_clock;
 714         htotal = adjusted_mode->crtc_htotal;
 715         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 716         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 717
 718         /* Use the small buffer method to calculate plane watermark */
 719         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 720         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 721         if (tlb_miss > 0)
 722                 entries += tlb_miss;
 723         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 724         *plane_wm = entries + display->guard_size;
 725         if (*plane_wm > (int)display->max_wm)
 726                 *plane_wm = display->max_wm;
 727
 728         /* Use the large buffer method to calculate cursor watermark */
 729         line_time_us = max(htotal * 1000 / clock, 1);
 730         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 731         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 732         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 733         if (tlb_miss > 0)
 734                 entries += tlb_miss;
 735         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 736         *cursor_wm = entries + cursor->guard_size;
 737         if (*cursor_wm > (int)cursor->max_wm)
 738                 *cursor_wm = (int)cursor->max_wm;
 739
 740         return true;
 741 }
 742
 743 /*
 744  * Check the wm result.
 745  *
 746  * If any calculated watermark values is larger than the maximum value that
 747  * can be programmed into the associated watermark register, that watermark
 748  * must be disabled.
 749  */
 750 static bool g4x_check_srwm(struct drm_device *dev,
 751                            int display_wm, int cursor_wm,
 752                            const struct intel_watermark_params *display,
 753                            const struct intel_watermark_params *cursor)
 754 {
 755         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 756                       display_wm, cursor_wm);
 757
 758         if (display_wm > display->max_wm) {
 759                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 760                               display_wm, display->max_wm);
 761                 return false;
 762         }
 763
 764         if (cursor_wm > cursor->max_wm) {
 765                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 766                               cursor_wm, cursor->max_wm);
 767                 return false;
 768         }
 769
 770         if (!(display_wm || cursor_wm)) {
 771                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 772                 return false;
 773         }
 774
 775         return true;
 776 }
 777
 778 static bool g4x_compute_srwm(struct drm_device *dev,
 779                              int plane,
 780                              int latency_ns,
 781                              const struct intel_watermark_params *display,
 782                              const struct intel_watermark_params *cursor,
 783                              int *display_wm, int *cursor_wm)
 784 {
 785         struct drm_crtc *crtc;
 786         const struct drm_display_mode *adjusted_mode;
 787         int hdisplay, htotal, pixel_size, clock;
 788         unsigned long line_time_us;
 789         int line_count, line_size;
 790         int small, large;
 791         int entries;
 792
 793         if (!latency_ns) {
 794                 *display_wm = *cursor_wm = 0;
 795                 return false;
 796         }
 797
 798         crtc = intel_get_crtc_for_plane(dev, plane);
 799         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 800         clock = adjusted_mode->crtc_clock;
 801         htotal = adjusted_mode->crtc_htotal;
 802         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 803         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 804
 805         line_time_us = max(htotal * 1000 / clock, 1);
 806         line_count = (latency_ns / line_time_us + 1000) / 1000;
 807         line_size = hdisplay * pixel_size;
 808
 809         /* Use the minimum of the small and large buffer method for primary */
 810         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 811         large = line_count * line_size;
 812
 813         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 814         *display_wm = entries + display->guard_size;
 815
 816         /* calculate the self-refresh watermark for display cursor */
 817         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 818         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 819         *cursor_wm = entries + cursor->guard_size;
 820
 821         return g4x_check_srwm(dev,
 822                               *display_wm, *cursor_wm,
 823                               display, cursor);
 824 }
 825
 826 #define FW_WM_VLV(value, plane) \
 827         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 828
 829 static void vlv_write_wm_values(struct intel_crtc *crtc,
 830                                 const struct vlv_wm_values *wm)
 831 {
 832         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 833         enum pipe pipe = crtc->pipe;
 834
 835         I915_WRITE(VLV_DDL(pipe),
 836                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 837                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 838                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 839                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 840
 841         I915_WRITE(DSPFW1,
 842                    FW_WM(wm->sr.plane, SR) |
 843                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 844                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 845                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 846         I915_WRITE(DSPFW2,
 847                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 848                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 849                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 850         I915_WRITE(DSPFW3,
 851                    FW_WM(wm->sr.cursor, CURSOR_SR));
 852
 853         if (IS_CHERRYVIEW(dev_priv)) {
 854                 I915_WRITE(DSPFW7_CHV,
 855                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 856                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 857                 I915_WRITE(DSPFW8_CHV,
 858                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 859                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 860                 I915_WRITE(DSPFW9_CHV,
 861                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 862                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 863                 I915_WRITE(DSPHOWM,
 864                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 865                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 866                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 867                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 868                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 869                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 870                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 871                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 872                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 873                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 874         } else {
 875                 I915_WRITE(DSPFW7,
 876                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 877                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 878                 I915_WRITE(DSPHOWM,
 879                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 880                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 881                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 882                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 883                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 884                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 885                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 886         }
 887
 888         /* zero (unused) WM1 watermarks */
 889         I915_WRITE(DSPFW4, 0);
 890         I915_WRITE(DSPFW5, 0);
 891         I915_WRITE(DSPFW6, 0);
 892         I915_WRITE(DSPHOWM1, 0);
 893
 894         POSTING_READ(DSPFW1);
 895 }
 896
 897 #undef FW_WM_VLV
 898
 899 enum vlv_wm_level {
 900         VLV_WM_LEVEL_PM2,
 901         VLV_WM_LEVEL_PM5,
 902         VLV_WM_LEVEL_DDR_DVFS,
 903 };
 904
 905 /* latency must be in 0.1us units. */
 906 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 907                                    unsigned int pipe_htotal,
 908                                    unsigned int horiz_pixels,
 909                                    unsigned int bytes_per_pixel,
 910                                    unsigned int latency)
 911 {
 912         unsigned int ret;
 913
 914         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 915         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 916         ret = DIV_ROUND_UP(ret, 64);
 917
 918         return ret;
 919 }
 920
 921 static void vlv_setup_wm_latency(struct drm_device *dev)
 922 {
 923         struct drm_i915_private *dev_priv = dev->dev_private;
 924
 925         /* all latencies in usec */
 926         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 927
 928         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 929
 930         if (IS_CHERRYVIEW(dev_priv)) {
 931                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 932                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 933
 934                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 935         }
 936 }
 937
 938 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 939                                      struct intel_crtc *crtc,
 940                                      const struct intel_plane_state *state,
 941                                      int level)
 942 {
 943         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 944         int clock, htotal, pixel_size, width, wm;
 945
 946         if (dev_priv->wm.pri_latency[level] == 0)
 947                 return USHRT_MAX;
 948
 949         if (!state->visible)
 950                 return 0;
 951
 952         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 953         clock = crtc->config->base.adjusted_mode.crtc_clock;
 954         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 955         width = crtc->config->pipe_src_w;
 956         if (WARN_ON(htotal == 0))
 957                 htotal = 1;
 958
 959         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 960                 /*
 961                  * FIXME the formula gives values that are
 962                  * too big for the cursor FIFO, and hence we
 963                  * would never be able to use cursors. For
 964                  * now just hardcode the watermark.
 965                  */
 966                 wm = 63;
 967         } else {
 968                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
 969                                     dev_priv->wm.pri_latency[level] * 10);
 970         }
 971
 972         return min_t(int, wm, USHRT_MAX);
 973 }
 974
 975 static void vlv_compute_fifo(struct intel_crtc *crtc)
 976 {
 977         struct drm_device *dev = crtc->base.dev;
 978         struct vlv_wm_state *wm_state = &crtc->wm_state;
 979         struct intel_plane *plane;
 980         unsigned int total_rate = 0;
 981         const int fifo_size = 512 - 1;
 982         int fifo_extra, fifo_left = fifo_size;
 983
 984         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 985                 struct intel_plane_state *state =
 986                         to_intel_plane_state(plane->base.state);
 987
 988                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 989                         continue;
 990
 991                 if (state->visible) {
 992                         wm_state->num_active_planes++;
 993                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 994                 }
 995         }
 996
 997         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 998                 struct intel_plane_state *state =
 999                         to_intel_plane_state(plane->base.state);
1000                 unsigned int rate;
1001
1002                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1003                         plane->wm.fifo_size = 63;
1004                         continue;
1005                 }
1006
1007                 if (!state->visible) {
1008                         plane->wm.fifo_size = 0;
1009                         continue;
1010                 }
1011
1012                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1014                 fifo_left -= plane->wm.fifo_size;
1015         }
1016
1017         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1018
1019         /* spread the remainder evenly */
1020         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1021                 int plane_extra;
1022
1023                 if (fifo_left == 0)
1024                         break;
1025
1026                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1027                         continue;
1028
1029                 /* give it all to the first plane if none are active */
1030                 if (plane->wm.fifo_size == 0 &&
1031                     wm_state->num_active_planes)
1032                         continue;
1033
1034                 plane_extra = min(fifo_extra, fifo_left);
1035                 plane->wm.fifo_size += plane_extra;
1036                 fifo_left -= plane_extra;
1037         }
1038
1039         WARN_ON(fifo_left != 0);
1040 }
1041
1042 static void vlv_invert_wms(struct intel_crtc *crtc)
1043 {
1044         struct vlv_wm_state *wm_state = &crtc->wm_state;
1045         int level;
1046
1047         for (level = 0; level < wm_state->num_levels; level++) {
1048                 struct drm_device *dev = crtc->base.dev;
1049                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1050                 struct intel_plane *plane;
1051
1052                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1053                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1054
1055                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1056                         switch (plane->base.type) {
1057                                 int sprite;
1058                         case DRM_PLANE_TYPE_CURSOR:
1059                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1060                                         wm_state->wm[level].cursor;
1061                                 break;
1062                         case DRM_PLANE_TYPE_PRIMARY:
1063                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1064                                         wm_state->wm[level].primary;
1065                                 break;
1066                         case DRM_PLANE_TYPE_OVERLAY:
1067                                 sprite = plane->plane;
1068                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1069                                         wm_state->wm[level].sprite[sprite];
1070                                 break;
1071                         }
1072                 }
1073         }
1074 }
1075
1076 static void vlv_compute_wm(struct intel_crtc *crtc)
1077 {
1078         struct drm_device *dev = crtc->base.dev;
1079         struct vlv_wm_state *wm_state = &crtc->wm_state;
1080         struct intel_plane *plane;
1081         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1082         int level;
1083
1084         memset(wm_state, 0, sizeof(*wm_state));
1085
1086         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1087         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1088
1089         wm_state->num_active_planes = 0;
1090
1091         vlv_compute_fifo(crtc);
1092
1093         if (wm_state->num_active_planes != 1)
1094                 wm_state->cxsr = false;
1095
1096         if (wm_state->cxsr) {
1097                 for (level = 0; level < wm_state->num_levels; level++) {
1098                         wm_state->sr[level].plane = sr_fifo_size;
1099                         wm_state->sr[level].cursor = 63;
1100                 }
1101         }
1102
1103         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1104                 struct intel_plane_state *state =
1105                         to_intel_plane_state(plane->base.state);
1106
1107                 if (!state->visible)
1108                         continue;
1109
1110                 /* normal watermarks */
1111                 for (level = 0; level < wm_state->num_levels; level++) {
1112                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1113                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1114
1115                         /* hack */
1116                         if (WARN_ON(level == 0 && wm > max_wm))
1117                                 wm = max_wm;
1118
1119                         if (wm > plane->wm.fifo_size)
1120                                 break;
1121
1122                         switch (plane->base.type) {
1123                                 int sprite;
1124                         case DRM_PLANE_TYPE_CURSOR:
1125                                 wm_state->wm[level].cursor = wm;
1126                                 break;
1127                         case DRM_PLANE_TYPE_PRIMARY:
1128                                 wm_state->wm[level].primary = wm;
1129                                 break;
1130                         case DRM_PLANE_TYPE_OVERLAY:
1131                                 sprite = plane->plane;
1132                                 wm_state->wm[level].sprite[sprite] = wm;
1133                                 break;
1134                         }
1135                 }
1136
1137                 wm_state->num_levels = level;
1138
1139                 if (!wm_state->cxsr)
1140                         continue;
1141
1142                 /* maxfifo watermarks */
1143                 switch (plane->base.type) {
1144                         int sprite, level;
1145                 case DRM_PLANE_TYPE_CURSOR:
1146                         for (level = 0; level < wm_state->num_levels; level++)
1147                                 wm_state->sr[level].cursor =
1148                                         wm_state->wm[level].cursor;
1149                         break;
1150                 case DRM_PLANE_TYPE_PRIMARY:
1151                         for (level = 0; level < wm_state->num_levels; level++)
1152                                 wm_state->sr[level].plane =
1153                                         min(wm_state->sr[level].plane,
1154                                             wm_state->wm[level].primary);
1155                         break;
1156                 case DRM_PLANE_TYPE_OVERLAY:
1157                         sprite = plane->plane;
1158                         for (level = 0; level < wm_state->num_levels; level++)
1159                                 wm_state->sr[level].plane =
1160                                         min(wm_state->sr[level].plane,
1161                                             wm_state->wm[level].sprite[sprite]);
1162                         break;
1163                 }
1164         }
1165
1166         /* clear any (partially) filled invalid levels */
1167         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1168                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1169                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1170         }
1171
1172         vlv_invert_wms(crtc);
1173 }
1174
1175 #define VLV_FIFO(plane, value) \
1176         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1177
1178 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1179 {
1180         struct drm_device *dev = crtc->base.dev;
1181         struct drm_i915_private *dev_priv = to_i915(dev);
1182         struct intel_plane *plane;
1183         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1184
1185         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1186                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1187                         WARN_ON(plane->wm.fifo_size != 63);
1188                         continue;
1189                 }
1190
1191                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1192                         sprite0_start = plane->wm.fifo_size;
1193                 else if (plane->plane == 0)
1194                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1195                 else
1196                         fifo_size = sprite1_start + plane->wm.fifo_size;
1197         }
1198
1199         WARN_ON(fifo_size != 512 - 1);
1200
1201         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1202                       pipe_name(crtc->pipe), sprite0_start,
1203                       sprite1_start, fifo_size);
1204
1205         switch (crtc->pipe) {
1206                 uint32_t dsparb, dsparb2, dsparb3;
1207         case PIPE_A:
1208                 dsparb = I915_READ(DSPARB);
1209                 dsparb2 = I915_READ(DSPARB2);
1210
1211                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1212                             VLV_FIFO(SPRITEB, 0xff));
1213                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1214                            VLV_FIFO(SPRITEB, sprite1_start));
1215
1216                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1217                              VLV_FIFO(SPRITEB_HI, 0x1));
1218                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1219                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1220
1221                 I915_WRITE(DSPARB, dsparb);
1222                 I915_WRITE(DSPARB2, dsparb2);
1223                 break;
1224         case PIPE_B:
1225                 dsparb = I915_READ(DSPARB);
1226                 dsparb2 = I915_READ(DSPARB2);
1227
1228                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1229                             VLV_FIFO(SPRITED, 0xff));
1230                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1231                            VLV_FIFO(SPRITED, sprite1_start));
1232
1233                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1234                              VLV_FIFO(SPRITED_HI, 0xff));
1235                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1236                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1237
1238                 I915_WRITE(DSPARB, dsparb);
1239                 I915_WRITE(DSPARB2, dsparb2);
1240                 break;
1241         case PIPE_C:
1242                 dsparb3 = I915_READ(DSPARB3);
1243                 dsparb2 = I915_READ(DSPARB2);
1244
1245                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1246                              VLV_FIFO(SPRITEF, 0xff));
1247                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1248                             VLV_FIFO(SPRITEF, sprite1_start));
1249
1250                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1251                              VLV_FIFO(SPRITEF_HI, 0xff));
1252                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1253                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1254
1255                 I915_WRITE(DSPARB3, dsparb3);
1256                 I915_WRITE(DSPARB2, dsparb2);
1257                 break;
1258         default:
1259                 break;
1260         }
1261 }
1262
1263 #undef VLV_FIFO
1264
1265 static void vlv_merge_wm(struct drm_device *dev,
1266                          struct vlv_wm_values *wm)
1267 {
1268         struct intel_crtc *crtc;
1269         int num_active_crtcs = 0;
1270
1271         wm->level = to_i915(dev)->wm.max_level;
1272         wm->cxsr = true;
1273
1274         for_each_intel_crtc(dev, crtc) {
1275                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1276
1277                 if (!crtc->active)
1278                         continue;
1279
1280                 if (!wm_state->cxsr)
1281                         wm->cxsr = false;
1282
1283                 num_active_crtcs++;
1284                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1285         }
1286
1287         if (num_active_crtcs != 1)
1288                 wm->cxsr = false;
1289
1290         if (num_active_crtcs > 1)
1291                 wm->level = VLV_WM_LEVEL_PM2;
1292
1293         for_each_intel_crtc(dev, crtc) {
1294                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1295                 enum pipe pipe = crtc->pipe;
1296
1297                 if (!crtc->active)
1298                         continue;
1299
1300                 wm->pipe[pipe] = wm_state->wm[wm->level];
1301                 if (wm->cxsr)
1302                         wm->sr = wm_state->sr[wm->level];
1303
1304                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1305                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1306                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1307                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1308         }
1309 }
1310
1311 static void vlv_update_wm(struct drm_crtc *crtc)
1312 {
1313         struct drm_device *dev = crtc->dev;
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1316         enum pipe pipe = intel_crtc->pipe;
1317         struct vlv_wm_values wm = {};
1318
1319         vlv_compute_wm(intel_crtc);
1320         vlv_merge_wm(dev, &wm);
1321
1322         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1323                 /* FIXME should be part of crtc atomic commit */
1324                 vlv_pipe_set_fifo_size(intel_crtc);
1325                 return;
1326         }
1327
1328         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1329             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1330                 chv_set_memory_dvfs(dev_priv, false);
1331
1332         if (wm.level < VLV_WM_LEVEL_PM5 &&
1333             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1334                 chv_set_memory_pm5(dev_priv, false);
1335
1336         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1337                 intel_set_memory_cxsr(dev_priv, false);
1338
1339         /* FIXME should be part of crtc atomic commit */
1340         vlv_pipe_set_fifo_size(intel_crtc);
1341
1342         vlv_write_wm_values(intel_crtc, &wm);
1343
1344         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1345                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1346                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1347                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1348                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1349
1350         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1351                 intel_set_memory_cxsr(dev_priv, true);
1352
1353         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1354             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1355                 chv_set_memory_pm5(dev_priv, true);
1356
1357         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1358             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1359                 chv_set_memory_dvfs(dev_priv, true);
1360
1361         dev_priv->wm.vlv = wm;
1362 }
1363
1364 #define single_plane_enabled(mask) is_power_of_2(mask)
1365
1366 static void g4x_update_wm(struct drm_crtc *crtc)
1367 {
1368         struct drm_device *dev = crtc->dev;
1369         static const int sr_latency_ns = 12000;
1370         struct drm_i915_private *dev_priv = dev->dev_private;
1371         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1372         int plane_sr, cursor_sr;
1373         unsigned int enabled = 0;
1374         bool cxsr_enabled;
1375
1376         if (g4x_compute_wm0(dev, PIPE_A,
1377                             &g4x_wm_info, pessimal_latency_ns,
1378                             &g4x_cursor_wm_info, pessimal_latency_ns,
1379                             &planea_wm, &cursora_wm))
1380                 enabled |= 1 << PIPE_A;
1381
1382         if (g4x_compute_wm0(dev, PIPE_B,
1383                             &g4x_wm_info, pessimal_latency_ns,
1384                             &g4x_cursor_wm_info, pessimal_latency_ns,
1385                             &planeb_wm, &cursorb_wm))
1386                 enabled |= 1 << PIPE_B;
1387
1388         if (single_plane_enabled(enabled) &&
1389             g4x_compute_srwm(dev, ffs(enabled) - 1,
1390                              sr_latency_ns,
1391                              &g4x_wm_info,
1392                              &g4x_cursor_wm_info,
1393                              &plane_sr, &cursor_sr)) {
1394                 cxsr_enabled = true;
1395         } else {
1396                 cxsr_enabled = false;
1397                 intel_set_memory_cxsr(dev_priv, false);
1398                 plane_sr = cursor_sr = 0;
1399         }
1400
1401         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1402                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1403                       planea_wm, cursora_wm,
1404                       planeb_wm, cursorb_wm,
1405                       plane_sr, cursor_sr);
1406
1407         I915_WRITE(DSPFW1,
1408                    FW_WM(plane_sr, SR) |
1409                    FW_WM(cursorb_wm, CURSORB) |
1410                    FW_WM(planeb_wm, PLANEB) |
1411                    FW_WM(planea_wm, PLANEA));
1412         I915_WRITE(DSPFW2,
1413                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1414                    FW_WM(cursora_wm, CURSORA));
1415         /* HPLL off in SR has some issues on G4x... disable it */
1416         I915_WRITE(DSPFW3,
1417                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1418                    FW_WM(cursor_sr, CURSOR_SR));
1419
1420         if (cxsr_enabled)
1421                 intel_set_memory_cxsr(dev_priv, true);
1422 }
1423
1424 static void i965_update_wm(struct drm_crtc *unused_crtc)
1425 {
1426         struct drm_device *dev = unused_crtc->dev;
1427         struct drm_i915_private *dev_priv = dev->dev_private;
1428         struct drm_crtc *crtc;
1429         int srwm = 1;
1430         int cursor_sr = 16;
1431         bool cxsr_enabled;
1432
1433         /* Calc sr entries for one plane configs */
1434         crtc = single_enabled_crtc(dev);
1435         if (crtc) {
1436                 /* self-refresh has much higher latency */
1437                 static const int sr_latency_ns = 12000;
1438                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1439                 int clock = adjusted_mode->crtc_clock;
1440                 int htotal = adjusted_mode->crtc_htotal;
1441                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1442                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1443                 unsigned long line_time_us;
1444                 int entries;
1445
1446                 line_time_us = max(htotal * 1000 / clock, 1);
1447
1448                 /* Use ns/us then divide to preserve precision */
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         pixel_size * hdisplay;
1451                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452                 srwm = I965_FIFO_SIZE - entries;
1453                 if (srwm < 0)
1454                         srwm = 1;
1455                 srwm &= 0x1ff;
1456                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457                               entries, srwm);
1458
1459                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1460                         pixel_size * crtc->cursor->state->crtc_w;
1461                 entries = DIV_ROUND_UP(entries,
1462                                           i965_cursor_wm_info.cacheline_size);
1463                 cursor_sr = i965_cursor_wm_info.fifo_size -
1464                         (entries + i965_cursor_wm_info.guard_size);
1465
1466                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467                         cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470                               "cursor %d\n", srwm, cursor_sr);
1471
1472                 cxsr_enabled = true;
1473         } else {
1474                 cxsr_enabled = false;
1475                 /* Turn off self refresh if both pipes are enabled */
1476                 intel_set_memory_cxsr(dev_priv, false);
1477         }
1478
1479         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1480                       srwm);
1481
1482         /* 965 has limitations... */
1483         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1484                    FW_WM(8, CURSORB) |
1485                    FW_WM(8, PLANEB) |
1486                    FW_WM(8, PLANEA));
1487         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1488                    FW_WM(8, PLANEC_OLD));
1489         /* update cursor SR watermark */
1490         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1491
1492         if (cxsr_enabled)
1493                 intel_set_memory_cxsr(dev_priv, true);
1494 }
1495
1496 #undef FW_WM
1497
1498 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1499 {
1500         struct drm_device *dev = unused_crtc->dev;
1501         struct drm_i915_private *dev_priv = dev->dev_private;
1502         const struct intel_watermark_params *wm_info;
1503         uint32_t fwater_lo;
1504         uint32_t fwater_hi;
1505         int cwm, srwm = 1;
1506         int fifo_size;
1507         int planea_wm, planeb_wm;
1508         struct drm_crtc *crtc, *enabled = NULL;
1509
1510         if (IS_I945GM(dev))
1511                 wm_info = &i945_wm_info;
1512         else if (!IS_GEN2(dev))
1513                 wm_info = &i915_wm_info;
1514         else
1515                 wm_info = &i830_a_wm_info;
1516
1517         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1518         crtc = intel_get_crtc_for_plane(dev, 0);
1519         if (intel_crtc_active(crtc)) {
1520                 const struct drm_display_mode *adjusted_mode;
1521                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1522                 if (IS_GEN2(dev))
1523                         cpp = 4;
1524
1525                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1526                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1527                                                wm_info, fifo_size, cpp,
1528                                                pessimal_latency_ns);
1529                 enabled = crtc;
1530         } else {
1531                 planea_wm = fifo_size - wm_info->guard_size;
1532                 if (planea_wm > (long)wm_info->max_wm)
1533                         planea_wm = wm_info->max_wm;
1534         }
1535
1536         if (IS_GEN2(dev))
1537                 wm_info = &i830_bc_wm_info;
1538
1539         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1540         crtc = intel_get_crtc_for_plane(dev, 1);
1541         if (intel_crtc_active(crtc)) {
1542                 const struct drm_display_mode *adjusted_mode;
1543                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1544                 if (IS_GEN2(dev))
1545                         cpp = 4;
1546
1547                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1548                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1549                                                wm_info, fifo_size, cpp,
1550                                                pessimal_latency_ns);
1551                 if (enabled == NULL)
1552                         enabled = crtc;
1553                 else
1554                         enabled = NULL;
1555         } else {
1556                 planeb_wm = fifo_size - wm_info->guard_size;
1557                 if (planeb_wm > (long)wm_info->max_wm)
1558                         planeb_wm = wm_info->max_wm;
1559         }
1560
1561         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1562
1563         if (IS_I915GM(dev) && enabled) {
1564                 struct drm_i915_gem_object *obj;
1565
1566                 obj = intel_fb_obj(enabled->primary->state->fb);
1567
1568                 /* self-refresh seems busted with untiled */
1569                 if (obj->tiling_mode == I915_TILING_NONE)
1570                         enabled = NULL;
1571         }
1572
1573         /*
1574          * Overlay gets an aggressive default since video jitter is bad.
1575          */
1576         cwm = 2;
1577
1578         /* Play safe and disable self-refresh before adjusting watermarks. */
1579         intel_set_memory_cxsr(dev_priv, false);
1580
1581         /* Calc sr entries for one plane configs */
1582         if (HAS_FW_BLC(dev) && enabled) {
1583                 /* self-refresh has much higher latency */
1584                 static const int sr_latency_ns = 6000;
1585                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1586                 int clock = adjusted_mode->crtc_clock;
1587                 int htotal = adjusted_mode->crtc_htotal;
1588                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1589                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1590                 unsigned long line_time_us;
1591                 int entries;
1592
1593                 line_time_us = max(htotal * 1000 / clock, 1);
1594
1595                 /* Use ns/us then divide to preserve precision */
1596                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1597                         pixel_size * hdisplay;
1598                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1599                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1600                 srwm = wm_info->fifo_size - entries;
1601                 if (srwm < 0)
1602                         srwm = 1;
1603
1604                 if (IS_I945G(dev) || IS_I945GM(dev))
1605                         I915_WRITE(FW_BLC_SELF,
1606                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1607                 else if (IS_I915GM(dev))
1608                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1609         }
1610
1611         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1612                       planea_wm, planeb_wm, cwm, srwm);
1613
1614         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1615         fwater_hi = (cwm & 0x1f);
1616
1617         /* Set request length to 8 cachelines per fetch */
1618         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1619         fwater_hi = fwater_hi | (1 << 8);
1620
1621         I915_WRITE(FW_BLC, fwater_lo);
1622         I915_WRITE(FW_BLC2, fwater_hi);
1623
1624         if (enabled)
1625                 intel_set_memory_cxsr(dev_priv, true);
1626 }
1627
1628 static void i845_update_wm(struct drm_crtc *unused_crtc)
1629 {
1630         struct drm_device *dev = unused_crtc->dev;
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         struct drm_crtc *crtc;
1633         const struct drm_display_mode *adjusted_mode;
1634         uint32_t fwater_lo;
1635         int planea_wm;
1636
1637         crtc = single_enabled_crtc(dev);
1638         if (crtc == NULL)
1639                 return;
1640
1641         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1642         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1643                                        &i845_wm_info,
1644                                        dev_priv->display.get_fifo_size(dev, 0),
1645                                        4, pessimal_latency_ns);
1646         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1647         fwater_lo |= (3<<8) | planea_wm;
1648
1649         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1650
1651         I915_WRITE(FW_BLC, fwater_lo);
1652 }
1653
1654 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1655 {
1656         uint32_t pixel_rate;
1657
1658         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1659
1660         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661          * adjust the pixel_rate here. */
1662
1663         if (pipe_config->pch_pfit.enabled) {
1664                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1665                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1666
1667                 pipe_w = pipe_config->pipe_src_w;
1668                 pipe_h = pipe_config->pipe_src_h;
1669
1670                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1671                 pfit_h = pfit_size & 0xFFFF;
1672                 if (pipe_w < pfit_w)
1673                         pipe_w = pfit_w;
1674                 if (pipe_h < pfit_h)
1675                         pipe_h = pfit_h;
1676
1677                 if (WARN_ON(!pfit_w || !pfit_h))
1678                         return pixel_rate;
1679
1680                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1681                                      pfit_w * pfit_h);
1682         }
1683
1684         return pixel_rate;
1685 }
1686
1687 /* latency must be in 0.1us units. */
1688 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1689                                uint32_t latency)
1690 {
1691         uint64_t ret;
1692
1693         if (WARN(latency == 0, "Latency value missing\n"))
1694                 return UINT_MAX;
1695
1696         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1697         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1698
1699         return ret;
1700 }
1701
1702 /* latency must be in 0.1us units. */
1703 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1704                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1705                                uint32_t latency)
1706 {
1707         uint32_t ret;
1708
1709         if (WARN(latency == 0, "Latency value missing\n"))
1710                 return UINT_MAX;
1711         if (WARN_ON(!pipe_htotal))
1712                 return UINT_MAX;
1713
1714         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1715         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1716         ret = DIV_ROUND_UP(ret, 64) + 2;
1717         return ret;
1718 }
1719
1720 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1721                            uint8_t bytes_per_pixel)
1722 {
1723         /*
1724          * Neither of these should be possible since this function shouldn't be
1725          * called if the CRTC is off or the plane is invisible.  But let's be
1726          * extra paranoid to avoid a potential divide-by-zero if we screw up
1727          * elsewhere in the driver.
1728          */
1729         if (WARN_ON(!bytes_per_pixel))
1730                 return 0;
1731         if (WARN_ON(!horiz_pixels))
1732                 return 0;
1733
1734         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1735 }
1736
1737 struct ilk_wm_maximums {
1738         uint16_t pri;
1739         uint16_t spr;
1740         uint16_t cur;
1741         uint16_t fbc;
1742 };
1743
1744 /*
1745  * For both WM_PIPE and WM_LP.
1746  * mem_value must be in 0.1us units.
1747  */
1748 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1749                                    const struct intel_plane_state *pstate,
1750                                    uint32_t mem_value,
1751                                    bool is_lp)
1752 {
1753         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1754         uint32_t method1, method2;
1755
1756         if (!cstate->base.active || !pstate->visible)
1757                 return 0;
1758
1759         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1760
1761         if (!is_lp)
1762                 return method1;
1763
1764         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1765                                  cstate->base.adjusted_mode.crtc_htotal,
1766                                  drm_rect_width(&pstate->dst),
1767                                  bpp,
1768                                  mem_value);
1769
1770         return min(method1, method2);
1771 }
1772
1773 /*
1774  * For both WM_PIPE and WM_LP.
1775  * mem_value must be in 0.1us units.
1776  */
1777 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1778                                    const struct intel_plane_state *pstate,
1779                                    uint32_t mem_value)
1780 {
1781         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1782         uint32_t method1, method2;
1783
1784         if (!cstate->base.active || !pstate->visible)
1785                 return 0;
1786
1787         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1788         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1789                                  cstate->base.adjusted_mode.crtc_htotal,
1790                                  drm_rect_width(&pstate->dst),
1791                                  bpp,
1792                                  mem_value);
1793         return min(method1, method2);
1794 }
1795
1796 /*
1797  * For both WM_PIPE and WM_LP.
1798  * mem_value must be in 0.1us units.
1799  */
1800 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1801                                    const struct intel_plane_state *pstate,
1802                                    uint32_t mem_value)
1803 {
1804         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1805
1806         if (!cstate->base.active || !pstate->visible)
1807                 return 0;
1808
1809         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1810                               cstate->base.adjusted_mode.crtc_htotal,
1811                               drm_rect_width(&pstate->dst),
1812                               bpp,
1813                               mem_value);
1814 }
1815
1816 /* Only for WM_LP. */
1817 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1818                                    const struct intel_plane_state *pstate,
1819                                    uint32_t pri_val)
1820 {
1821         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1822
1823         if (!cstate->base.active || !pstate->visible)
1824                 return 0;
1825
1826         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1827 }
1828
1829 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1830 {
1831         if (INTEL_INFO(dev)->gen >= 8)
1832                 return 3072;
1833         else if (INTEL_INFO(dev)->gen >= 7)
1834                 return 768;
1835         else
1836                 return 512;
1837 }
1838
1839 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1840                                          int level, bool is_sprite)
1841 {
1842         if (INTEL_INFO(dev)->gen >= 8)
1843                 /* BDW primary/sprite plane watermarks */
1844                 return level == 0 ? 255 : 2047;
1845         else if (INTEL_INFO(dev)->gen >= 7)
1846                 /* IVB/HSW primary/sprite plane watermarks */
1847                 return level == 0 ? 127 : 1023;
1848         else if (!is_sprite)
1849                 /* ILK/SNB primary plane watermarks */
1850                 return level == 0 ? 127 : 511;
1851         else
1852                 /* ILK/SNB sprite plane watermarks */
1853                 return level == 0 ? 63 : 255;
1854 }
1855
1856 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1857                                           int level)
1858 {
1859         if (INTEL_INFO(dev)->gen >= 7)
1860                 return level == 0 ? 63 : 255;
1861         else
1862                 return level == 0 ? 31 : 63;
1863 }
1864
1865 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1866 {
1867         if (INTEL_INFO(dev)->gen >= 8)
1868                 return 31;
1869         else
1870                 return 15;
1871 }
1872
1873 /* Calculate the maximum primary/sprite plane watermark */
1874 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1875                                      int level,
1876                                      const struct intel_wm_config *config,
1877                                      enum intel_ddb_partitioning ddb_partitioning,
1878                                      bool is_sprite)
1879 {
1880         unsigned int fifo_size = ilk_display_fifo_size(dev);
1881
1882         /* if sprites aren't enabled, sprites get nothing */
1883         if (is_sprite && !config->sprites_enabled)
1884                 return 0;
1885
1886         /* HSW allows LP1+ watermarks even with multiple pipes */
1887         if (level == 0 || config->num_pipes_active > 1) {
1888                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1889
1890                 /*
1891                  * For some reason the non self refresh
1892                  * FIFO size is only half of the self
1893                  * refresh FIFO size on ILK/SNB.
1894                  */
1895                 if (INTEL_INFO(dev)->gen <= 6)
1896                         fifo_size /= 2;
1897         }
1898
1899         if (config->sprites_enabled) {
1900                 /* level 0 is always calculated with 1:1 split */
1901                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1902                         if (is_sprite)
1903                                 fifo_size *= 5;
1904                         fifo_size /= 6;
1905                 } else {
1906                         fifo_size /= 2;
1907                 }
1908         }
1909
1910         /* clamp to max that the registers can hold */
1911         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1912 }
1913
1914 /* Calculate the maximum cursor plane watermark */
1915 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1916                                       int level,
1917                                       const struct intel_wm_config *config)
1918 {
1919         /* HSW LP1+ watermarks w/ multiple pipes */
1920         if (level > 0 && config->num_pipes_active > 1)
1921                 return 64;
1922
1923         /* otherwise just report max that registers can hold */
1924         return ilk_cursor_wm_reg_max(dev, level);
1925 }
1926
1927 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1928                                     int level,
1929                                     const struct intel_wm_config *config,
1930                                     enum intel_ddb_partitioning ddb_partitioning,
1931                                     struct ilk_wm_maximums *max)
1932 {
1933         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1934         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1935         max->cur = ilk_cursor_wm_max(dev, level, config);
1936         max->fbc = ilk_fbc_wm_reg_max(dev);
1937 }
1938
1939 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1940                                         int level,
1941                                         struct ilk_wm_maximums *max)
1942 {
1943         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1944         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1945         max->cur = ilk_cursor_wm_reg_max(dev, level);
1946         max->fbc = ilk_fbc_wm_reg_max(dev);
1947 }
1948
1949 static bool ilk_validate_wm_level(int level,
1950                                   const struct ilk_wm_maximums *max,
1951                                   struct intel_wm_level *result)
1952 {
1953         bool ret;
1954
1955         /* already determined to be invalid? */
1956         if (!result->enable)
1957                 return false;
1958
1959         result->enable = result->pri_val <= max->pri &&
1960                          result->spr_val <= max->spr &&
1961                          result->cur_val <= max->cur;
1962
1963         ret = result->enable;
1964
1965         /*
1966          * HACK until we can pre-compute everything,
1967          * and thus fail gracefully if LP0 watermarks
1968          * are exceeded...
1969          */
1970         if (level == 0 && !result->enable) {
1971                 if (result->pri_val > max->pri)
1972                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1973                                       level, result->pri_val, max->pri);
1974                 if (result->spr_val > max->spr)
1975                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1976                                       level, result->spr_val, max->spr);
1977                 if (result->cur_val > max->cur)
1978                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1979                                       level, result->cur_val, max->cur);
1980
1981                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1982                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1983                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1984                 result->enable = true;
1985         }
1986
1987         return ret;
1988 }
1989
1990 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1991                                  const struct intel_crtc *intel_crtc,
1992                                  int level,
1993                                  struct intel_crtc_state *cstate,
1994                                  struct intel_plane_state *pristate,
1995                                  struct intel_plane_state *sprstate,
1996                                  struct intel_plane_state *curstate,
1997                                  struct intel_wm_level *result)
1998 {
1999         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2000         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2001         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2002
2003         /* WM1+ latency values stored in 0.5us units */
2004         if (level > 0) {
2005                 pri_latency *= 5;
2006                 spr_latency *= 5;
2007                 cur_latency *= 5;
2008         }
2009
2010         result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2011                                              pri_latency, level);
2012         result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2013         result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2014         result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2015         result->enable = true;
2016 }
2017
2018 static uint32_t
2019 hsw_compute_linetime_wm(struct drm_device *dev,
2020                         struct intel_crtc_state *cstate)
2021 {
2022         struct drm_i915_private *dev_priv = dev->dev_private;
2023         const struct drm_display_mode *adjusted_mode =
2024                 &cstate->base.adjusted_mode;
2025         u32 linetime, ips_linetime;
2026
2027         if (!cstate->base.active)
2028                 return 0;
2029         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2030                 return 0;
2031         if (WARN_ON(dev_priv->cdclk_freq == 0))
2032                 return 0;
2033
2034         /* The WM are computed with base on how long it takes to fill a single
2035          * row at the given clock rate, multiplied by 8.
2036          * */
2037         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2038                                      adjusted_mode->crtc_clock);
2039         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2040                                          dev_priv->cdclk_freq);
2041
2042         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2043                PIPE_WM_LINETIME_TIME(linetime);
2044 }
2045
2046 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2047 {
2048         struct drm_i915_private *dev_priv = dev->dev_private;
2049
2050         if (IS_GEN9(dev)) {
2051                 uint32_t val;
2052                 int ret, i;
2053                 int level, max_level = ilk_wm_max_level(dev);
2054
2055                 /* read the first set of memory latencies[0:3] */
2056                 val = 0; /* data0 to be programmed to 0 for first set */
2057                 mutex_lock(&dev_priv->rps.hw_lock);
2058                 ret = sandybridge_pcode_read(dev_priv,
2059                                              GEN9_PCODE_READ_MEM_LATENCY,
2060                                              &val);
2061                 mutex_unlock(&dev_priv->rps.hw_lock);
2062
2063                 if (ret) {
2064                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2065                         return;
2066                 }
2067
2068                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2069                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2070                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2071                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2072                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2073                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2074                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2075
2076                 /* read the second set of memory latencies[4:7] */
2077                 val = 1; /* data0 to be programmed to 1 for second set */
2078                 mutex_lock(&dev_priv->rps.hw_lock);
2079                 ret = sandybridge_pcode_read(dev_priv,
2080                                              GEN9_PCODE_READ_MEM_LATENCY,
2081                                              &val);
2082                 mutex_unlock(&dev_priv->rps.hw_lock);
2083                 if (ret) {
2084                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2085                         return;
2086                 }
2087
2088                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2089                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2090                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2091                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2092                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2093                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2094                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2095
2096                 /*
2097                  * WaWmMemoryReadLatency:skl
2098                  *
2099                  * punit doesn't take into account the read latency so we need
2100                  * to add 2us to the various latency levels we retrieve from
2101                  * the punit.
2102                  *   - W0 is a bit special in that it's the only level that
2103                  *   can't be disabled if we want to have display working, so
2104                  *   we always add 2us there.
2105                  *   - For levels >=1, punit returns 0us latency when they are
2106                  *   disabled, so we respect that and don't add 2us then
2107                  *
2108                  * Additionally, if a level n (n > 1) has a 0us latency, all
2109                  * levels m (m >= n) need to be disabled. We make sure to
2110                  * sanitize the values out of the punit to satisfy this
2111                  * requirement.
2112                  */
2113                 wm[0] += 2;
2114                 for (level = 1; level <= max_level; level++)
2115                         if (wm[level] != 0)
2116                                 wm[level] += 2;
2117                         else {
2118                                 for (i = level + 1; i <= max_level; i++)
2119                                         wm[i] = 0;
2120
2121                                 break;
2122                         }
2123         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2124                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2125
2126                 wm[0] = (sskpd >> 56) & 0xFF;
2127                 if (wm[0] == 0)
2128                         wm[0] = sskpd & 0xF;
2129                 wm[1] = (sskpd >> 4) & 0xFF;
2130                 wm[2] = (sskpd >> 12) & 0xFF;
2131                 wm[3] = (sskpd >> 20) & 0x1FF;
2132                 wm[4] = (sskpd >> 32) & 0x1FF;
2133         } else if (INTEL_INFO(dev)->gen >= 6) {
2134                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2135
2136                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2137                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2138                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2139                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2140         } else if (INTEL_INFO(dev)->gen >= 5) {
2141                 uint32_t mltr = I915_READ(MLTR_ILK);
2142
2143                 /* ILK primary LP0 latency is 700 ns */
2144                 wm[0] = 7;
2145                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2146                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2147         }
2148 }
2149
2150 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2151 {
2152         /* ILK sprite LP0 latency is 1300 ns */
2153         if (INTEL_INFO(dev)->gen == 5)
2154                 wm[0] = 13;
2155 }
2156
2157 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2158 {
2159         /* ILK cursor LP0 latency is 1300 ns */
2160         if (INTEL_INFO(dev)->gen == 5)
2161                 wm[0] = 13;
2162
2163         /* WaDoubleCursorLP3Latency:ivb */
2164         if (IS_IVYBRIDGE(dev))
2165                 wm[3] *= 2;
2166 }
2167
2168 int ilk_wm_max_level(const struct drm_device *dev)
2169 {
2170         /* how many WM levels are we expecting */
2171         if (INTEL_INFO(dev)->gen >= 9)
2172                 return 7;
2173         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2174                 return 4;
2175         else if (INTEL_INFO(dev)->gen >= 6)
2176                 return 3;
2177         else
2178                 return 2;
2179 }
2180
2181 static void intel_print_wm_latency(struct drm_device *dev,
2182                                    const char *name,
2183                                    const uint16_t wm[8])
2184 {
2185         int level, max_level = ilk_wm_max_level(dev);
2186
2187         for (level = 0; level <= max_level; level++) {
2188                 unsigned int latency = wm[level];
2189
2190                 if (latency == 0) {
2191                         DRM_ERROR("%s WM%d latency not provided\n",
2192                                   name, level);
2193                         continue;
2194                 }
2195
2196                 /*
2197                  * - latencies are in us on gen9.
2198                  * - before then, WM1+ latency values are in 0.5us units
2199                  */
2200                 if (IS_GEN9(dev))
2201                         latency *= 10;
2202                 else if (level > 0)
2203                         latency *= 5;
2204
2205                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2206                               name, level, wm[level],
2207                               latency / 10, latency % 10);
2208         }
2209 }
2210
2211 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2212                                     uint16_t wm[5], uint16_t min)
2213 {
2214         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2215
2216         if (wm[0] >= min)
2217                 return false;
2218
2219         wm[0] = max(wm[0], min);
2220         for (level = 1; level <= max_level; level++)
2221                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2222
2223         return true;
2224 }
2225
2226 static void snb_wm_latency_quirk(struct drm_device *dev)
2227 {
2228         struct drm_i915_private *dev_priv = dev->dev_private;
2229         bool changed;
2230
2231         /*
2232          * The BIOS provided WM memory latency values are often
2233          * inadequate for high resolution displays. Adjust them.
2234          */
2235         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2236                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2237                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2238
2239         if (!changed)
2240                 return;
2241
2242         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2243         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2244         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2245         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2246 }
2247
2248 static void ilk_setup_wm_latency(struct drm_device *dev)
2249 {
2250         struct drm_i915_private *dev_priv = dev->dev_private;
2251
2252         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2253
2254         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2255                sizeof(dev_priv->wm.pri_latency));
2256         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2257                sizeof(dev_priv->wm.pri_latency));
2258
2259         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2260         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2261
2262         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2263         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2264         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2265
2266         if (IS_GEN6(dev))
2267                 snb_wm_latency_quirk(dev);
2268 }
2269
2270 static void skl_setup_wm_latency(struct drm_device *dev)
2271 {
2272         struct drm_i915_private *dev_priv = dev->dev_private;
2273
2274         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2275         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2276 }
2277
2278 /* Compute new watermarks for the pipe */
2279 static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2280                                struct drm_atomic_state *state)
2281 {
2282         struct intel_pipe_wm *pipe_wm;
2283         struct drm_device *dev = intel_crtc->base.dev;
2284         const struct drm_i915_private *dev_priv = dev->dev_private;
2285         struct intel_crtc_state *cstate = NULL;
2286         struct intel_plane *intel_plane;
2287         struct drm_plane_state *ps;
2288         struct intel_plane_state *pristate = NULL;
2289         struct intel_plane_state *sprstate = NULL;
2290         struct intel_plane_state *curstate = NULL;
2291         int level, max_level = ilk_wm_max_level(dev);
2292         /* LP0 watermark maximums depend on this pipe alone */
2293         struct intel_wm_config config = {
2294                 .num_pipes_active = 1,
2295         };
2296         struct ilk_wm_maximums max;
2297
2298         cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2299         if (IS_ERR(cstate))
2300                 return PTR_ERR(cstate);
2301
2302         pipe_wm = &cstate->wm.optimal.ilk;
2303         memset(pipe_wm, 0, sizeof(*pipe_wm));
2304
2305         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2306                 ps = drm_atomic_get_plane_state(state,
2307                                                 &intel_plane->base);
2308                 if (IS_ERR(ps))
2309                         return PTR_ERR(ps);
2310
2311                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2312                         pristate = to_intel_plane_state(ps);
2313                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2314                         sprstate = to_intel_plane_state(ps);
2315                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2316                         curstate = to_intel_plane_state(ps);
2317         }
2318
2319         config.sprites_enabled = sprstate->visible;
2320         config.sprites_scaled = sprstate->visible &&
2321                 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2322                 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2323
2324         pipe_wm->pipe_enabled = cstate->base.active;
2325         pipe_wm->sprites_enabled = config.sprites_enabled;
2326         pipe_wm->sprites_scaled = config.sprites_scaled;
2327
2328         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2329         if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2330                 max_level = 1;
2331
2332         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2333         if (config.sprites_scaled)
2334                 max_level = 0;
2335
2336         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2337                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
2338
2339         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2340                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
2341
2342         /* LP0 watermarks always use 1/2 DDB partitioning */
2343         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2344
2345         /* At least LP0 must be valid */
2346         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2347                 return -EINVAL;
2348
2349         ilk_compute_wm_reg_maximums(dev, 1, &max);
2350
2351         for (level = 1; level <= max_level; level++) {
2352                 struct intel_wm_level wm = {};
2353
2354                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2355                                      pristate, sprstate, curstate, &wm);
2356
2357                 /*
2358                  * Disable any watermark level that exceeds the
2359                  * register maximums since such watermarks are
2360                  * always invalid.
2361                  */
2362                 if (!ilk_validate_wm_level(level, &max, &wm))
2363                         break;
2364
2365                 pipe_wm->wm[level] = wm;
2366         }
2367
2368         return 0;
2369 }
2370
2371 /*
2372  * Merge the watermarks from all active pipes for a specific level.
2373  */
2374 static void ilk_merge_wm_level(struct drm_device *dev,
2375                                int level,
2376                                struct intel_wm_level *ret_wm)
2377 {
2378         const struct intel_crtc *intel_crtc;
2379
2380         ret_wm->enable = true;
2381
2382         for_each_intel_crtc(dev, intel_crtc) {
2383                 const struct intel_crtc_state *cstate =
2384                         to_intel_crtc_state(intel_crtc->base.state);
2385                 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
2386                 const struct intel_wm_level *wm = &active->wm[level];
2387
2388                 if (!active->pipe_enabled)
2389                         continue;
2390
2391                 /*
2392                  * The watermark values may have been used in the past,
2393                  * so we must maintain them in the registers for some
2394                  * time even if the level is now disabled.
2395                  */
2396                 if (!wm->enable)
2397                         ret_wm->enable = false;
2398
2399                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2400                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2401                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2402                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2403         }
2404 }
2405
2406 /*
2407  * Merge all low power watermarks for all active pipes.
2408  */
2409 static void ilk_wm_merge(struct drm_device *dev,
2410                          const struct intel_wm_config *config,
2411                          const struct ilk_wm_maximums *max,
2412                          struct intel_pipe_wm *merged)
2413 {
2414         struct drm_i915_private *dev_priv = dev->dev_private;
2415         int level, max_level = ilk_wm_max_level(dev);
2416         int last_enabled_level = max_level;
2417
2418         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2419         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2420             config->num_pipes_active > 1)
2421                 return;
2422
2423         /* ILK: FBC WM must be disabled always */
2424         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2425
2426         /* merge each WM1+ level */
2427         for (level = 1; level <= max_level; level++) {
2428                 struct intel_wm_level *wm = &merged->wm[level];
2429
2430                 ilk_merge_wm_level(dev, level, wm);
2431
2432                 if (level > last_enabled_level)
2433                         wm->enable = false;
2434                 else if (!ilk_validate_wm_level(level, max, wm))
2435                         /* make sure all following levels get disabled */
2436                         last_enabled_level = level - 1;
2437
2438                 /*
2439                  * The spec says it is preferred to disable
2440                  * FBC WMs instead of disabling a WM level.
2441                  */
2442                 if (wm->fbc_val > max->fbc) {
2443                         if (wm->enable)
2444                                 merged->fbc_wm_enabled = false;
2445                         wm->fbc_val = 0;
2446                 }
2447         }
2448
2449         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2450         /*
2451          * FIXME this is racy. FBC might get enabled later.
2452          * What we should check here is whether FBC can be
2453          * enabled sometime later.
2454          */
2455         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2456             intel_fbc_is_active(dev_priv)) {
2457                 for (level = 2; level <= max_level; level++) {
2458                         struct intel_wm_level *wm = &merged->wm[level];
2459
2460                         wm->enable = false;
2461                 }
2462         }
2463 }
2464
2465 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2466 {
2467         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2468         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2469 }
2470
2471 /* The value we need to program into the WM_LPx latency field */
2472 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2473 {
2474         struct drm_i915_private *dev_priv = dev->dev_private;
2475
2476         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2477                 return 2 * level;
2478         else
2479                 return dev_priv->wm.pri_latency[level];
2480 }
2481
2482 static void ilk_compute_wm_results(struct drm_device *dev,
2483                                    const struct intel_pipe_wm *merged,
2484                                    enum intel_ddb_partitioning partitioning,
2485                                    struct ilk_wm_values *results)
2486 {
2487         struct intel_crtc *intel_crtc;
2488         int level, wm_lp;
2489
2490         results->enable_fbc_wm = merged->fbc_wm_enabled;
2491         results->partitioning = partitioning;
2492
2493         /* LP1+ register values */
2494         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2495                 const struct intel_wm_level *r;
2496
2497                 level = ilk_wm_lp_to_level(wm_lp, merged);
2498
2499                 r = &merged->wm[level];
2500
2501                 /*
2502                  * Maintain the watermark values even if the level is
2503                  * disabled. Doing otherwise could cause underruns.
2504                  */
2505                 results->wm_lp[wm_lp - 1] =
2506                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2507                         (r->pri_val << WM1_LP_SR_SHIFT) |
2508                         r->cur_val;
2509
2510                 if (r->enable)
2511                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2512
2513                 if (INTEL_INFO(dev)->gen >= 8)
2514                         results->wm_lp[wm_lp - 1] |=
2515                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2516                 else
2517                         results->wm_lp[wm_lp - 1] |=
2518                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2519
2520                 /*
2521                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2522                  * level is disabled. Doing otherwise could cause underruns.
2523                  */
2524                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2525                         WARN_ON(wm_lp != 1);
2526                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2527                 } else
2528                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2529         }
2530
2531         /* LP0 register values */
2532         for_each_intel_crtc(dev, intel_crtc) {
2533                 const struct intel_crtc_state *cstate =
2534                         to_intel_crtc_state(intel_crtc->base.state);
2535                 enum pipe pipe = intel_crtc->pipe;
2536                 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
2537
2538                 if (WARN_ON(!r->enable))
2539                         continue;
2540
2541                 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
2542
2543                 results->wm_pipe[pipe] =
2544                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2545                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2546                         r->cur_val;
2547         }
2548 }
2549
2550 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2551  * case both are at the same level. Prefer r1 in case they're the same. */
2552 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2553                                                   struct intel_pipe_wm *r1,
2554                                                   struct intel_pipe_wm *r2)
2555 {
2556         int level, max_level = ilk_wm_max_level(dev);
2557         int level1 = 0, level2 = 0;
2558
2559         for (level = 1; level <= max_level; level++) {
2560                 if (r1->wm[level].enable)
2561                         level1 = level;
2562                 if (r2->wm[level].enable)
2563                         level2 = level;
2564         }
2565
2566         if (level1 == level2) {
2567                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2568                         return r2;
2569                 else
2570                         return r1;
2571         } else if (level1 > level2) {
2572                 return r1;
2573         } else {
2574                 return r2;
2575         }
2576 }
2577
2578 /* dirty bits used to track which watermarks need changes */
2579 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2580 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2581 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2582 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2583 #define WM_DIRTY_FBC (1 << 24)
2584 #define WM_DIRTY_DDB (1 << 25)
2585
2586 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2587                                          const struct ilk_wm_values *old,
2588                                          const struct ilk_wm_values *new)
2589 {
2590         unsigned int dirty = 0;
2591         enum pipe pipe;
2592         int wm_lp;
2593
2594         for_each_pipe(dev_priv, pipe) {
2595                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2596                         dirty |= WM_DIRTY_LINETIME(pipe);
2597                         /* Must disable LP1+ watermarks too */
2598                         dirty |= WM_DIRTY_LP_ALL;
2599                 }
2600
2601                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2602                         dirty |= WM_DIRTY_PIPE(pipe);
2603                         /* Must disable LP1+ watermarks too */
2604                         dirty |= WM_DIRTY_LP_ALL;
2605                 }
2606         }
2607
2608         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2609                 dirty |= WM_DIRTY_FBC;
2610                 /* Must disable LP1+ watermarks too */
2611                 dirty |= WM_DIRTY_LP_ALL;
2612         }
2613
2614         if (old->partitioning != new->partitioning) {
2615                 dirty |= WM_DIRTY_DDB;
2616                 /* Must disable LP1+ watermarks too */
2617                 dirty |= WM_DIRTY_LP_ALL;
2618         }
2619
2620         /* LP1+ watermarks already deemed dirty, no need to continue */
2621         if (dirty & WM_DIRTY_LP_ALL)
2622                 return dirty;
2623
2624         /* Find the lowest numbered LP1+ watermark in need of an update... */
2625         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2626                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2627                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2628                         break;
2629         }
2630
2631         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2632         for (; wm_lp <= 3; wm_lp++)
2633                 dirty |= WM_DIRTY_LP(wm_lp);
2634
2635         return dirty;
2636 }
2637
2638 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2639                                unsigned int dirty)
2640 {
2641         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2642         bool changed = false;
2643
2644         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2645                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2646                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2647                 changed = true;
2648         }
2649         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2650                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2651                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2652                 changed = true;
2653         }
2654         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2655                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2656                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2657                 changed = true;
2658         }
2659
2660         /*
2661          * Don't touch WM1S_LP_EN here.
2662          * Doing so could cause underruns.
2663          */
2664
2665         return changed;
2666 }
2667
2668 /*
2669  * The spec says we shouldn't write when we don't need, because every write
2670  * causes WMs to be re-evaluated, expending some power.
2671  */
2672 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2673                                 struct ilk_wm_values *results)
2674 {
2675         struct drm_device *dev = dev_priv->dev;
2676         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2677         unsigned int dirty;
2678         uint32_t val;
2679
2680         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2681         if (!dirty)
2682                 return;
2683
2684         _ilk_disable_lp_wm(dev_priv, dirty);
2685
2686         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2687                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2688         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2689                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2690         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2691                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2692
2693         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2694                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2695         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2696                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2697         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2698                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2699
2700         if (dirty & WM_DIRTY_DDB) {
2701                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2702                         val = I915_READ(WM_MISC);
2703                         if (results->partitioning == INTEL_DDB_PART_1_2)
2704                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2705                         else
2706                                 val |= WM_MISC_DATA_PARTITION_5_6;
2707                         I915_WRITE(WM_MISC, val);
2708                 } else {
2709                         val = I915_READ(DISP_ARB_CTL2);
2710                         if (results->partitioning == INTEL_DDB_PART_1_2)
2711                                 val &= ~DISP_DATA_PARTITION_5_6;
2712                         else
2713                                 val |= DISP_DATA_PARTITION_5_6;
2714                         I915_WRITE(DISP_ARB_CTL2, val);
2715                 }
2716         }
2717
2718         if (dirty & WM_DIRTY_FBC) {
2719                 val = I915_READ(DISP_ARB_CTL);
2720                 if (results->enable_fbc_wm)
2721                         val &= ~DISP_FBC_WM_DIS;
2722                 else
2723                         val |= DISP_FBC_WM_DIS;
2724                 I915_WRITE(DISP_ARB_CTL, val);
2725         }
2726
2727         if (dirty & WM_DIRTY_LP(1) &&
2728             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2729                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2730
2731         if (INTEL_INFO(dev)->gen >= 7) {
2732                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2733                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2734                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2735                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2736         }
2737
2738         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2739                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2740         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2741                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2742         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2743                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2744
2745         dev_priv->wm.hw = *results;
2746 }
2747
2748 static bool ilk_disable_lp_wm(struct drm_device *dev)
2749 {
2750         struct drm_i915_private *dev_priv = dev->dev_private;
2751
2752         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2753 }
2754
2755 /*
2756  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2757  * different active planes.
2758  */
2759
2760 #define SKL_DDB_SIZE            896     /* in blocks */
2761 #define BXT_DDB_SIZE            512
2762
2763 /*
2764  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2765  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2766  * other universal planes are in indices 1..n.  Note that this may leave unused
2767  * indices between the top "sprite" plane and the cursor.
2768  */
2769 static int
2770 skl_wm_plane_id(const struct intel_plane *plane)
2771 {
2772         switch (plane->base.type) {
2773         case DRM_PLANE_TYPE_PRIMARY:
2774                 return 0;
2775         case DRM_PLANE_TYPE_CURSOR:
2776                 return PLANE_CURSOR;
2777         case DRM_PLANE_TYPE_OVERLAY:
2778                 return plane->plane + 1;
2779         default:
2780                 MISSING_CASE(plane->base.type);
2781                 return plane->plane;
2782         }
2783 }
2784
2785 static void
2786 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2787                                    const struct intel_crtc_state *cstate,
2788                                    const struct intel_wm_config *config,
2789                                    struct skl_ddb_entry *alloc /* out */)
2790 {
2791         struct drm_crtc *for_crtc = cstate->base.crtc;
2792         struct drm_crtc *crtc;
2793         unsigned int pipe_size, ddb_size;
2794         int nth_active_pipe;
2795
2796         if (!cstate->base.active) {
2797                 alloc->start = 0;
2798                 alloc->end = 0;
2799                 return;
2800         }
2801
2802         if (IS_BROXTON(dev))
2803                 ddb_size = BXT_DDB_SIZE;
2804         else
2805                 ddb_size = SKL_DDB_SIZE;
2806
2807         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2808
2809         nth_active_pipe = 0;
2810         for_each_crtc(dev, crtc) {
2811                 if (!to_intel_crtc(crtc)->active)
2812                         continue;
2813
2814                 if (crtc == for_crtc)
2815                         break;
2816
2817                 nth_active_pipe++;
2818         }
2819
2820         pipe_size = ddb_size / config->num_pipes_active;
2821         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2822         alloc->end = alloc->start + pipe_size;
2823 }
2824
2825 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2826 {
2827         if (config->num_pipes_active == 1)
2828                 return 32;
2829
2830         return 8;
2831 }
2832
2833 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2834 {
2835         entry->start = reg & 0x3ff;
2836         entry->end = (reg >> 16) & 0x3ff;
2837         if (entry->end)
2838                 entry->end += 1;
2839 }
2840
2841 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2842                           struct skl_ddb_allocation *ddb /* out */)
2843 {
2844         enum pipe pipe;
2845         int plane;
2846         u32 val;
2847
2848         memset(ddb, 0, sizeof(*ddb));
2849
2850         for_each_pipe(dev_priv, pipe) {
2851                 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2852                         continue;
2853
2854                 for_each_plane(dev_priv, pipe, plane) {
2855                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2856                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2857                                                    val);
2858                 }
2859
2860                 val = I915_READ(CUR_BUF_CFG(pipe));
2861                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2862                                            val);
2863         }
2864 }
2865
2866 static unsigned int
2867 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2868                              const struct drm_plane_state *pstate,
2869                              int y)
2870 {
2871         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2872         struct drm_framebuffer *fb = pstate->fb;
2873
2874         /* for planar format */
2875         if (fb->pixel_format == DRM_FORMAT_NV12) {
2876                 if (y)  /* y-plane data rate */
2877                         return intel_crtc->config->pipe_src_w *
2878                                 intel_crtc->config->pipe_src_h *
2879                                 drm_format_plane_cpp(fb->pixel_format, 0);
2880                 else    /* uv-plane data rate */
2881                         return (intel_crtc->config->pipe_src_w/2) *
2882                                 (intel_crtc->config->pipe_src_h/2) *
2883                                 drm_format_plane_cpp(fb->pixel_format, 1);
2884         }
2885
2886         /* for packed formats */
2887         return intel_crtc->config->pipe_src_w *
2888                 intel_crtc->config->pipe_src_h *
2889                 drm_format_plane_cpp(fb->pixel_format, 0);
2890 }
2891
2892 /*
2893  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2894  * a 8192x4096@32bpp framebuffer:
2895  *   3 * 4096 * 8192  * 4 < 2^32
2896  */
2897 static unsigned int
2898 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2899 {
2900         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2901         struct drm_device *dev = intel_crtc->base.dev;
2902         const struct intel_plane *intel_plane;
2903         unsigned int total_data_rate = 0;
2904
2905         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2906                 const struct drm_plane_state *pstate = intel_plane->base.state;
2907
2908                 if (pstate->fb == NULL)
2909                         continue;
2910
2911                 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2912                         continue;
2913
2914                 /* packed/uv */
2915                 total_data_rate += skl_plane_relative_data_rate(cstate,
2916                                                                 pstate,
2917                                                                 0);
2918
2919                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2920                         /* y-plane */
2921                         total_data_rate += skl_plane_relative_data_rate(cstate,
2922                                                                         pstate,
2923                                                                         1);
2924         }
2925
2926         return total_data_rate;
2927 }
2928
2929 static void
2930 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
2931                       struct skl_ddb_allocation *ddb /* out */)
2932 {
2933         struct drm_crtc *crtc = cstate->base.crtc;
2934         struct drm_device *dev = crtc->dev;
2935         struct drm_i915_private *dev_priv = to_i915(dev);
2936         struct intel_wm_config *config = &dev_priv->wm.config;
2937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2938         struct intel_plane *intel_plane;
2939         enum pipe pipe = intel_crtc->pipe;
2940         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2941         uint16_t alloc_size, start, cursor_blocks;
2942         uint16_t minimum[I915_MAX_PLANES];
2943         uint16_t y_minimum[I915_MAX_PLANES];
2944         unsigned int total_data_rate;
2945
2946         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
2947         alloc_size = skl_ddb_entry_size(alloc);
2948         if (alloc_size == 0) {
2949                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2950                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2951                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2952                 return;
2953         }
2954
2955         cursor_blocks = skl_cursor_allocation(config);
2956         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2957         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2958
2959         alloc_size -= cursor_blocks;
2960         alloc->end -= cursor_blocks;
2961
2962         /* 1. Allocate the mininum required blocks for each active plane */
2963         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2964                 struct drm_plane *plane = &intel_plane->base;
2965                 struct drm_framebuffer *fb = plane->state->fb;
2966                 int id = skl_wm_plane_id(intel_plane);
2967
2968                 if (fb == NULL)
2969                         continue;
2970                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
2971                         continue;
2972
2973                 minimum[id] = 8;
2974                 alloc_size -= minimum[id];
2975                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2976                 alloc_size -= y_minimum[id];
2977         }
2978
2979         /*
2980          * 2. Distribute the remaining space in proportion to the amount of
2981          * data each plane needs to fetch from memory.
2982          *
2983          * FIXME: we may not allocate every single block here.
2984          */
2985         total_data_rate = skl_get_total_relative_data_rate(cstate);
2986
2987         start = alloc->start;
2988         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2989                 struct drm_plane *plane = &intel_plane->base;
2990                 struct drm_plane_state *pstate = intel_plane->base.state;
2991                 unsigned int data_rate, y_data_rate;
2992                 uint16_t plane_blocks, y_plane_blocks = 0;
2993                 int id = skl_wm_plane_id(intel_plane);
2994
2995                 if (pstate->fb == NULL)
2996                         continue;
2997                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
2998                         continue;
2999
3000                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3001
3002                 /*
3003                  * allocation for (packed formats) or (uv-plane part of planar format):
3004                  * promote the expression to 64 bits to avoid overflowing, the
3005                  * result is < available as data_rate / total_data_rate < 1
3006                  */
3007                 plane_blocks = minimum[id];
3008                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3009                                         total_data_rate);
3010
3011                 ddb->plane[pipe][id].start = start;
3012                 ddb->plane[pipe][id].end = start + plane_blocks;
3013
3014                 start += plane_blocks;
3015
3016                 /*
3017                  * allocation for y_plane part of planar format:
3018                  */
3019                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3020                         y_data_rate = skl_plane_relative_data_rate(cstate,
3021                                                                    pstate,
3022                                                                    1);
3023                         y_plane_blocks = y_minimum[id];
3024                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3025                                                 total_data_rate);
3026
3027                         ddb->y_plane[pipe][id].start = start;
3028                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3029
3030                         start += y_plane_blocks;
3031                 }
3032
3033         }
3034
3035 }
3036
3037 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3038 {
3039         /* TODO: Take into account the scalers once we support them */
3040         return config->base.adjusted_mode.crtc_clock;
3041 }
3042
3043 /*
3044  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3045  * for the read latency) and bytes_per_pixel should always be <= 8, so that
3046  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3047  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3048 */
3049 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3050                                uint32_t latency)
3051 {
3052         uint32_t wm_intermediate_val, ret;
3053
3054         if (latency == 0)
3055                 return UINT_MAX;
3056
3057         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3058         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3059
3060         return ret;
3061 }
3062
3063 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3064                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3065                                uint64_t tiling, uint32_t latency)
3066 {
3067         uint32_t ret;
3068         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3069         uint32_t wm_intermediate_val;
3070
3071         if (latency == 0)
3072                 return UINT_MAX;
3073
3074         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3075
3076         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3077             tiling == I915_FORMAT_MOD_Yf_TILED) {
3078                 plane_bytes_per_line *= 4;
3079                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3080                 plane_blocks_per_line /= 4;
3081         } else {
3082                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3083         }
3084
3085         wm_intermediate_val = latency * pixel_rate;
3086         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3087                                 plane_blocks_per_line;
3088
3089         return ret;
3090 }
3091
3092 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3093                                        const struct intel_crtc *intel_crtc)
3094 {
3095         struct drm_device *dev = intel_crtc->base.dev;
3096         struct drm_i915_private *dev_priv = dev->dev_private;
3097         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3098
3099         /*
3100          * If ddb allocation of pipes changed, it may require recalculation of
3101          * watermarks
3102          */
3103         if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3104                 return true;
3105
3106         return false;
3107 }
3108
3109 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3110                                  struct intel_crtc_state *cstate,
3111                                  struct intel_plane *intel_plane,
3112                                  uint16_t ddb_allocation,
3113                                  int level,
3114                                  uint16_t *out_blocks, /* out */
3115                                  uint8_t *out_lines /* out */)
3116 {
3117         struct drm_plane *plane = &intel_plane->base;
3118         struct drm_framebuffer *fb = plane->state->fb;
3119         uint32_t latency = dev_priv->wm.skl_latency[level];
3120         uint32_t method1, method2;
3121         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3122         uint32_t res_blocks, res_lines;
3123         uint32_t selected_result;
3124         uint8_t bytes_per_pixel;
3125
3126         if (latency == 0 || !cstate->base.active || !fb)
3127                 return false;
3128
3129         bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3130         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3131                                  bytes_per_pixel,
3132                                  latency);
3133         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3134                                  cstate->base.adjusted_mode.crtc_htotal,
3135                                  cstate->pipe_src_w,
3136                                  bytes_per_pixel,
3137                                  fb->modifier[0],
3138                                  latency);
3139
3140         plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
3141         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3142
3143         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3144             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3145                 uint32_t min_scanlines = 4;
3146                 uint32_t y_tile_minimum;
3147                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3148                         int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3149                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3150                                 drm_format_plane_cpp(fb->pixel_format, 0);
3151
3152                         switch (bpp) {
3153                         case 1:
3154                                 min_scanlines = 16;
3155                                 break;
3156                         case 2:
3157                                 min_scanlines = 8;
3158                                 break;
3159                         case 8:
3160                                 WARN(1, "Unsupported pixel depth for rotation");
3161                         }
3162                 }
3163                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3164                 selected_result = max(method2, y_tile_minimum);
3165         } else {
3166                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3167                         selected_result = min(method1, method2);
3168                 else
3169                         selected_result = method1;
3170         }
3171
3172         res_blocks = selected_result + 1;
3173         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3174
3175         if (level >= 1 && level <= 7) {
3176                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3177                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3178                         res_lines += 4;
3179                 else
3180                         res_blocks++;
3181         }
3182
3183         if (res_blocks >= ddb_allocation || res_lines > 31)
3184                 return false;
3185
3186         *out_blocks = res_blocks;
3187         *out_lines = res_lines;
3188
3189         return true;
3190 }
3191
3192 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3193                                  struct skl_ddb_allocation *ddb,
3194                                  struct intel_crtc_state *cstate,
3195                                  int level,
3196                                  struct skl_wm_level *result)
3197 {
3198         struct drm_device *dev = dev_priv->dev;
3199         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3200         struct intel_plane *intel_plane;
3201         uint16_t ddb_blocks;
3202         enum pipe pipe = intel_crtc->pipe;
3203
3204         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3205                 int i = skl_wm_plane_id(intel_plane);
3206
3207                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3208
3209                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3210                                                 cstate,
3211                                                 intel_plane,
3212                                                 ddb_blocks,
3213                                                 level,
3214                                                 &result->plane_res_b[i],
3215                                                 &result->plane_res_l[i]);
3216         }
3217 }
3218
3219 static uint32_t
3220 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3221 {
3222         if (!cstate->base.active)
3223                 return 0;
3224
3225         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3226                 return 0;
3227
3228         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3229                             skl_pipe_pixel_rate(cstate));
3230 }
3231
3232 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3233                                       struct skl_wm_level *trans_wm /* out */)
3234 {
3235         struct drm_crtc *crtc = cstate->base.crtc;
3236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3237         struct intel_plane *intel_plane;
3238
3239         if (!cstate->base.active)
3240                 return;
3241
3242         /* Until we know more, just disable transition WMs */
3243         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3244                 int i = skl_wm_plane_id(intel_plane);
3245
3246                 trans_wm->plane_en[i] = false;
3247         }
3248 }
3249
3250 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3251                                 struct skl_ddb_allocation *ddb,
3252                                 struct skl_pipe_wm *pipe_wm)
3253 {
3254         struct drm_device *dev = cstate->base.crtc->dev;
3255         const struct drm_i915_private *dev_priv = dev->dev_private;
3256         int level, max_level = ilk_wm_max_level(dev);
3257
3258         for (level = 0; level <= max_level; level++) {
3259                 skl_compute_wm_level(dev_priv, ddb, cstate,
3260                                      level, &pipe_wm->wm[level]);
3261         }
3262         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3263
3264         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3265 }
3266
3267 static void skl_compute_wm_results(struct drm_device *dev,
3268                                    struct skl_pipe_wm *p_wm,
3269                                    struct skl_wm_values *r,
3270                                    struct intel_crtc *intel_crtc)
3271 {
3272         int level, max_level = ilk_wm_max_level(dev);
3273         enum pipe pipe = intel_crtc->pipe;
3274         uint32_t temp;
3275         int i;
3276
3277         for (level = 0; level <= max_level; level++) {
3278                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3279                         temp = 0;
3280
3281                         temp |= p_wm->wm[level].plane_res_l[i] <<
3282                                         PLANE_WM_LINES_SHIFT;
3283                         temp |= p_wm->wm[level].plane_res_b[i];
3284                         if (p_wm->wm[level].plane_en[i])
3285                                 temp |= PLANE_WM_EN;
3286
3287                         r->plane[pipe][i][level] = temp;
3288                 }
3289
3290                 temp = 0;
3291
3292                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3293                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3294
3295                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3296                         temp |= PLANE_WM_EN;
3297
3298                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3299
3300         }
3301
3302         /* transition WMs */
3303         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3304                 temp = 0;
3305                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3306                 temp |= p_wm->trans_wm.plane_res_b[i];
3307                 if (p_wm->trans_wm.plane_en[i])
3308                         temp |= PLANE_WM_EN;
3309
3310                 r->plane_trans[pipe][i] = temp;
3311         }
3312
3313         temp = 0;
3314         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3315         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3316         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3317                 temp |= PLANE_WM_EN;
3318
3319         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3320
3321         r->wm_linetime[pipe] = p_wm->linetime;
3322 }
3323
3324 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3325                                 i915_reg_t reg,
3326                                 const struct skl_ddb_entry *entry)
3327 {
3328         if (entry->end)
3329                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3330         else
3331                 I915_WRITE(reg, 0);
3332 }
3333
3334 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3335                                 const struct skl_wm_values *new)
3336 {
3337         struct drm_device *dev = dev_priv->dev;
3338         struct intel_crtc *crtc;
3339
3340         for_each_intel_crtc(dev, crtc) {
3341                 int i, level, max_level = ilk_wm_max_level(dev);
3342                 enum pipe pipe = crtc->pipe;
3343
3344                 if (!new->dirty[pipe])
3345                         continue;
3346
3347                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3348
3349                 for (level = 0; level <= max_level; level++) {
3350                         for (i = 0; i < intel_num_planes(crtc); i++)
3351                                 I915_WRITE(PLANE_WM(pipe, i, level),
3352                                            new->plane[pipe][i][level]);
3353                         I915_WRITE(CUR_WM(pipe, level),
3354                                    new->plane[pipe][PLANE_CURSOR][level]);
3355                 }
3356                 for (i = 0; i < intel_num_planes(crtc); i++)
3357                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3358                                    new->plane_trans[pipe][i]);
3359                 I915_WRITE(CUR_WM_TRANS(pipe),
3360                            new->plane_trans[pipe][PLANE_CURSOR]);
3361
3362                 for (i = 0; i < intel_num_planes(crtc); i++) {
3363                         skl_ddb_entry_write(dev_priv,
3364                                             PLANE_BUF_CFG(pipe, i),
3365                                             &new->ddb.plane[pipe][i]);
3366                         skl_ddb_entry_write(dev_priv,
3367                                             PLANE_NV12_BUF_CFG(pipe, i),
3368                                             &new->ddb.y_plane[pipe][i]);
3369                 }
3370
3371                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3372                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3373         }
3374 }
3375
3376 /*
3377  * When setting up a new DDB allocation arrangement, we need to correctly
3378  * sequence the times at which the new allocations for the pipes are taken into
3379  * account or we'll have pipes fetching from space previously allocated to
3380  * another pipe.
3381  *
3382  * Roughly the sequence looks like:
3383  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3384  *     overlapping with a previous light-up pipe (another way to put it is:
3385  *     pipes with their new allocation strickly included into their old ones).
3386  *  2. re-allocate the other pipes that get their allocation reduced
3387  *  3. allocate the pipes having their allocation increased
3388  *
3389  * Steps 1. and 2. are here to take care of the following case:
3390  * - Initially DDB looks like this:
3391  *     |   B    |   C    |
3392  * - enable pipe A.
3393  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3394  *   allocation
3395  *     |  A  |  B  |  C  |
3396  *
3397  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3398  */
3399
3400 static void
3401 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3402 {
3403         int plane;
3404
3405         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3406
3407         for_each_plane(dev_priv, pipe, plane) {
3408                 I915_WRITE(PLANE_SURF(pipe, plane),
3409                            I915_READ(PLANE_SURF(pipe, plane)));
3410         }
3411         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3412 }
3413
3414 static bool
3415 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3416                             const struct skl_ddb_allocation *new,
3417                             enum pipe pipe)
3418 {
3419         uint16_t old_size, new_size;
3420
3421         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3422         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3423
3424         return old_size != new_size &&
3425                new->pipe[pipe].start >= old->pipe[pipe].start &&
3426                new->pipe[pipe].end <= old->pipe[pipe].end;
3427 }
3428
3429 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3430                                 struct skl_wm_values *new_values)
3431 {
3432         struct drm_device *dev = dev_priv->dev;
3433         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3434         bool reallocated[I915_MAX_PIPES] = {};
3435         struct intel_crtc *crtc;
3436         enum pipe pipe;
3437
3438         new_ddb = &new_values->ddb;
3439         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3440
3441         /*
3442          * First pass: flush the pipes with the new allocation contained into
3443          * the old space.
3444          *
3445          * We'll wait for the vblank on those pipes to ensure we can safely
3446          * re-allocate the freed space without this pipe fetching from it.
3447          */
3448         for_each_intel_crtc(dev, crtc) {
3449                 if (!crtc->active)
3450                         continue;
3451
3452                 pipe = crtc->pipe;
3453
3454                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3455                         continue;
3456
3457                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3458                 intel_wait_for_vblank(dev, pipe);
3459
3460                 reallocated[pipe] = true;
3461         }
3462
3463
3464         /*
3465          * Second pass: flush the pipes that are having their allocation
3466          * reduced, but overlapping with a previous allocation.
3467          *
3468          * Here as well we need to wait for the vblank to make sure the freed
3469          * space is not used anymore.
3470          */
3471         for_each_intel_crtc(dev, crtc) {
3472                 if (!crtc->active)
3473                         continue;
3474
3475                 pipe = crtc->pipe;
3476
3477                 if (reallocated[pipe])
3478                         continue;
3479
3480                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3481                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3482                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3483                         intel_wait_for_vblank(dev, pipe);
3484                         reallocated[pipe] = true;
3485                 }
3486         }
3487
3488         /*
3489          * Third pass: flush the pipes that got more space allocated.
3490          *
3491          * We don't need to actively wait for the update here, next vblank
3492          * will just get more DDB space with the correct WM values.
3493          */
3494         for_each_intel_crtc(dev, crtc) {
3495                 if (!crtc->active)
3496                         continue;
3497
3498                 pipe = crtc->pipe;
3499
3500                 /*
3501                  * At this point, only the pipes more space than before are
3502                  * left to re-allocate.
3503                  */
3504                 if (reallocated[pipe])
3505                         continue;
3506
3507                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3508         }
3509 }
3510
3511 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3512                                struct skl_ddb_allocation *ddb, /* out */
3513                                struct skl_pipe_wm *pipe_wm /* out */)
3514 {
3515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3517
3518         skl_allocate_pipe_ddb(cstate, ddb);
3519         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3520
3521         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3522                 return false;
3523
3524         intel_crtc->wm.active.skl = *pipe_wm;
3525
3526         return true;
3527 }
3528
3529 static void skl_update_other_pipe_wm(struct drm_device *dev,
3530                                      struct drm_crtc *crtc,
3531                                      struct skl_wm_values *r)
3532 {
3533         struct intel_crtc *intel_crtc;
3534         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3535
3536         /*
3537          * If the WM update hasn't changed the allocation for this_crtc (the
3538          * crtc we are currently computing the new WM values for), other
3539          * enabled crtcs will keep the same allocation and we don't need to
3540          * recompute anything for them.
3541          */
3542         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3543                 return;
3544
3545         /*
3546          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3547          * other active pipes need new DDB allocation and WM values.
3548          */
3549         for_each_intel_crtc(dev, intel_crtc) {
3550                 struct skl_pipe_wm pipe_wm = {};
3551                 bool wm_changed;
3552
3553                 if (this_crtc->pipe == intel_crtc->pipe)
3554                         continue;
3555
3556                 if (!intel_crtc->active)
3557                         continue;
3558
3559                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3560                                                 &r->ddb, &pipe_wm);
3561
3562                 /*
3563                  * If we end up re-computing the other pipe WM values, it's
3564                  * because it was really needed, so we expect the WM values to
3565                  * be different.
3566                  */
3567                 WARN_ON(!wm_changed);
3568
3569                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3570                 r->dirty[intel_crtc->pipe] = true;
3571         }
3572 }
3573
3574 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3575 {
3576         watermarks->wm_linetime[pipe] = 0;
3577         memset(watermarks->plane[pipe], 0,
3578                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3579         memset(watermarks->plane_trans[pipe],
3580                0, sizeof(uint32_t) * I915_MAX_PLANES);
3581         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3582
3583         /* Clear ddb entries for pipe */
3584         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3585         memset(&watermarks->ddb.plane[pipe], 0,
3586                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3587         memset(&watermarks->ddb.y_plane[pipe], 0,
3588                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3589         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3590                sizeof(struct skl_ddb_entry));
3591
3592 }
3593
3594 static void skl_update_wm(struct drm_crtc *crtc)
3595 {
3596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597         struct drm_device *dev = crtc->dev;
3598         struct drm_i915_private *dev_priv = dev->dev_private;
3599         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3600         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3601         struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3602
3603
3604         /* Clear all dirty flags */
3605         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3606
3607         skl_clear_wm(results, intel_crtc->pipe);
3608
3609         if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3610                 return;
3611
3612         skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3613         results->dirty[intel_crtc->pipe] = true;
3614
3615         skl_update_other_pipe_wm(dev, crtc, results);
3616         skl_write_wm_values(dev_priv, results);
3617         skl_flush_wm_values(dev_priv, results);
3618
3619         /* store the new configuration */
3620         dev_priv->wm.skl_hw = *results;
3621 }
3622
3623 static void ilk_compute_wm_config(struct drm_device *dev,
3624                                   struct intel_wm_config *config)
3625 {
3626         struct intel_crtc *crtc;
3627
3628         /* Compute the currently _active_ config */
3629         for_each_intel_crtc(dev, crtc) {
3630                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3631
3632                 if (!wm->pipe_enabled)
3633                         continue;
3634
3635                 config->sprites_enabled |= wm->sprites_enabled;
3636                 config->sprites_scaled |= wm->sprites_scaled;
3637                 config->num_pipes_active++;
3638         }
3639 }
3640
3641 static void ilk_program_watermarks(struct intel_crtc_state *cstate)
3642 {
3643         struct drm_crtc *crtc = cstate->base.crtc;
3644         struct drm_device *dev = crtc->dev;
3645         struct drm_i915_private *dev_priv = to_i915(dev);
3646         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3647         struct ilk_wm_maximums max;
3648         struct intel_wm_config config = {};
3649         struct ilk_wm_values results = {};
3650         enum intel_ddb_partitioning partitioning;
3651
3652         ilk_compute_wm_config(dev, &config);
3653
3654         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3655         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3656
3657         /* 5/6 split only in single pipe config on IVB+ */
3658         if (INTEL_INFO(dev)->gen >= 7 &&
3659             config.num_pipes_active == 1 && config.sprites_enabled) {
3660                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3661                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3662
3663                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3664         } else {
3665                 best_lp_wm = &lp_wm_1_2;
3666         }
3667
3668         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3669                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3670
3671         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3672
3673         ilk_write_wm_values(dev_priv, &results);
3674 }
3675
3676 static void ilk_update_wm(struct drm_crtc *crtc)
3677 {
3678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3679         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3680
3681         WARN_ON(cstate->base.active != intel_crtc->active);
3682
3683         /*
3684          * IVB workaround: must disable low power watermarks for at least
3685          * one frame before enabling scaling.  LP watermarks can be re-enabled
3686          * when scaling is disabled.
3687          *
3688          * WaCxSRDisabledForSpriteScaling:ivb
3689          */
3690         if (cstate->disable_lp_wm) {
3691                 ilk_disable_lp_wm(crtc->dev);
3692                 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3693         }
3694
3695         intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3696
3697         ilk_program_watermarks(cstate);
3698 }
3699
3700 static void skl_pipe_wm_active_state(uint32_t val,
3701                                      struct skl_pipe_wm *active,
3702                                      bool is_transwm,
3703                                      bool is_cursor,
3704                                      int i,
3705                                      int level)
3706 {
3707         bool is_enabled = (val & PLANE_WM_EN) != 0;
3708
3709         if (!is_transwm) {
3710                 if (!is_cursor) {
3711                         active->wm[level].plane_en[i] = is_enabled;
3712                         active->wm[level].plane_res_b[i] =
3713                                         val & PLANE_WM_BLOCKS_MASK;
3714                         active->wm[level].plane_res_l[i] =
3715                                         (val >> PLANE_WM_LINES_SHIFT) &
3716                                                 PLANE_WM_LINES_MASK;
3717                 } else {
3718                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3719                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3720                                         val & PLANE_WM_BLOCKS_MASK;
3721                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3722                                         (val >> PLANE_WM_LINES_SHIFT) &
3723                                                 PLANE_WM_LINES_MASK;
3724                 }
3725         } else {
3726                 if (!is_cursor) {
3727                         active->trans_wm.plane_en[i] = is_enabled;
3728                         active->trans_wm.plane_res_b[i] =
3729                                         val & PLANE_WM_BLOCKS_MASK;
3730                         active->trans_wm.plane_res_l[i] =
3731                                         (val >> PLANE_WM_LINES_SHIFT) &
3732                                                 PLANE_WM_LINES_MASK;
3733                 } else {
3734                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3735                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3736                                         val & PLANE_WM_BLOCKS_MASK;
3737                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3738                                         (val >> PLANE_WM_LINES_SHIFT) &
3739                                                 PLANE_WM_LINES_MASK;
3740                 }
3741         }
3742 }
3743
3744 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3745 {
3746         struct drm_device *dev = crtc->dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3750         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3751         struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3752         enum pipe pipe = intel_crtc->pipe;
3753         int level, i, max_level;
3754         uint32_t temp;
3755
3756         max_level = ilk_wm_max_level(dev);
3757
3758         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3759
3760         for (level = 0; level <= max_level; level++) {
3761                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3762                         hw->plane[pipe][i][level] =
3763                                         I915_READ(PLANE_WM(pipe, i, level));
3764                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3765         }
3766
3767         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3768                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3769         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3770
3771         if (!intel_crtc->active)
3772                 return;
3773
3774         hw->dirty[pipe] = true;
3775
3776         active->linetime = hw->wm_linetime[pipe];
3777
3778         for (level = 0; level <= max_level; level++) {
3779                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3780                         temp = hw->plane[pipe][i][level];
3781                         skl_pipe_wm_active_state(temp, active, false,
3782                                                 false, i, level);
3783                 }
3784                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3785                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3786         }
3787
3788         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3789                 temp = hw->plane_trans[pipe][i];
3790                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3791         }
3792
3793         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3794         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3795
3796         intel_crtc->wm.active.skl = *active;
3797 }
3798
3799 void skl_wm_get_hw_state(struct drm_device *dev)
3800 {
3801         struct drm_i915_private *dev_priv = dev->dev_private;
3802         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3803         struct drm_crtc *crtc;
3804
3805         skl_ddb_get_hw_state(dev_priv, ddb);
3806         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3807                 skl_pipe_wm_get_hw_state(crtc);
3808 }
3809
3810 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3811 {
3812         struct drm_device *dev = crtc->dev;
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3816         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3817         struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3818         enum pipe pipe = intel_crtc->pipe;
3819         static const i915_reg_t wm0_pipe_reg[] = {
3820                 [PIPE_A] = WM0_PIPEA_ILK,
3821                 [PIPE_B] = WM0_PIPEB_ILK,
3822                 [PIPE_C] = WM0_PIPEC_IVB,
3823         };
3824
3825         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3826         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3827                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3828
3829         active->pipe_enabled = intel_crtc->active;
3830
3831         if (active->pipe_enabled) {
3832                 u32 tmp = hw->wm_pipe[pipe];
3833
3834                 /*
3835                  * For active pipes LP0 watermark is marked as
3836                  * enabled, and LP1+ watermaks as disabled since
3837                  * we can't really reverse compute them in case
3838                  * multiple pipes are active.
3839                  */
3840                 active->wm[0].enable = true;
3841                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3842                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3843                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3844                 active->linetime = hw->wm_linetime[pipe];
3845         } else {
3846                 int level, max_level = ilk_wm_max_level(dev);
3847
3848                 /*
3849                  * For inactive pipes, all watermark levels
3850                  * should be marked as enabled but zeroed,
3851                  * which is what we'd compute them to.
3852                  */
3853                 for (level = 0; level <= max_level; level++)
3854                         active->wm[level].enable = true;
3855         }
3856
3857         intel_crtc->wm.active.ilk = *active;
3858 }
3859
3860 #define _FW_WM(value, plane) \
3861         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3862 #define _FW_WM_VLV(value, plane) \
3863         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3864
3865 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3866                                struct vlv_wm_values *wm)
3867 {
3868         enum pipe pipe;
3869         uint32_t tmp;
3870
3871         for_each_pipe(dev_priv, pipe) {
3872                 tmp = I915_READ(VLV_DDL(pipe));
3873
3874                 wm->ddl[pipe].primary =
3875                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3876                 wm->ddl[pipe].cursor =
3877                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3878                 wm->ddl[pipe].sprite[0] =
3879                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3880                 wm->ddl[pipe].sprite[1] =
3881                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3882         }
3883
3884         tmp = I915_READ(DSPFW1);
3885         wm->sr.plane = _FW_WM(tmp, SR);
3886         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3887         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3888         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3889
3890         tmp = I915_READ(DSPFW2);
3891         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3892         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3893         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3894
3895         tmp = I915_READ(DSPFW3);
3896         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3897
3898         if (IS_CHERRYVIEW(dev_priv)) {
3899                 tmp = I915_READ(DSPFW7_CHV);
3900                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3901                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3902
3903                 tmp = I915_READ(DSPFW8_CHV);
3904                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3905                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3906
3907                 tmp = I915_READ(DSPFW9_CHV);
3908                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3909                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3910
3911                 tmp = I915_READ(DSPHOWM);
3912                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3913                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3914                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3915                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3916                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3917                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3918                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3919                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3920                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3921                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3922         } else {
3923                 tmp = I915_READ(DSPFW7);
3924                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3925                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3926
3927                 tmp = I915_READ(DSPHOWM);
3928                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3929                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3930                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3931                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3932                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3933                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3934                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3935         }
3936 }
3937
3938 #undef _FW_WM
3939 #undef _FW_WM_VLV
3940
3941 void vlv_wm_get_hw_state(struct drm_device *dev)
3942 {
3943         struct drm_i915_private *dev_priv = to_i915(dev);
3944         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3945         struct intel_plane *plane;
3946         enum pipe pipe;
3947         u32 val;
3948
3949         vlv_read_wm_values(dev_priv, wm);
3950
3951         for_each_intel_plane(dev, plane) {
3952                 switch (plane->base.type) {
3953                         int sprite;
3954                 case DRM_PLANE_TYPE_CURSOR:
3955                         plane->wm.fifo_size = 63;
3956                         break;
3957                 case DRM_PLANE_TYPE_PRIMARY:
3958                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3959                         break;
3960                 case DRM_PLANE_TYPE_OVERLAY:
3961                         sprite = plane->plane;
3962                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3963                         break;
3964                 }
3965         }
3966
3967         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3968         wm->level = VLV_WM_LEVEL_PM2;
3969
3970         if (IS_CHERRYVIEW(dev_priv)) {
3971                 mutex_lock(&dev_priv->rps.hw_lock);
3972
3973                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3974                 if (val & DSP_MAXFIFO_PM5_ENABLE)
3975                         wm->level = VLV_WM_LEVEL_PM5;
3976
3977                 /*
3978                  * If DDR DVFS is disabled in the BIOS, Punit
3979                  * will never ack the request. So if that happens
3980                  * assume we don't have to enable/disable DDR DVFS
3981                  * dynamically. To test that just set the REQ_ACK
3982                  * bit to poke the Punit, but don't change the
3983                  * HIGH/LOW bits so that we don't actually change
3984                  * the current state.
3985                  */
3986                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3987                 val |= FORCE_DDR_FREQ_REQ_ACK;
3988                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3989
3990                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3991                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3992                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3993                                       "assuming DDR DVFS is disabled\n");
3994                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3995                 } else {
3996                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3997                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3998                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3999                 }
4000
4001                 mutex_unlock(&dev_priv->rps.hw_lock);
4002         }
4003
4004         for_each_pipe(dev_priv, pipe)
4005                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4006                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4007                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4008
4009         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4010                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4011 }
4012
4013 void ilk_wm_get_hw_state(struct drm_device *dev)
4014 {
4015         struct drm_i915_private *dev_priv = dev->dev_private;
4016         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4017         struct drm_crtc *crtc;
4018
4019         for_each_crtc(dev, crtc)
4020                 ilk_pipe_wm_get_hw_state(crtc);
4021
4022         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4023         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4024         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4025
4026         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4027         if (INTEL_INFO(dev)->gen >= 7) {
4028                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4029                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4030         }
4031
4032         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4033                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4034                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4035         else if (IS_IVYBRIDGE(dev))
4036                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4037                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4038
4039         hw->enable_fbc_wm =
4040                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4041 }
4042
4043 /**
4044  * intel_update_watermarks - update FIFO watermark values based on current modes
4045  *
4046  * Calculate watermark values for the various WM regs based on current mode
4047  * and plane configuration.
4048  *
4049  * There are several cases to deal with here:
4050  *   - normal (i.e. non-self-refresh)
4051  *   - self-refresh (SR) mode
4052  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4053  *   - lines are small relative to FIFO size (buffer can hold more than 2
4054  *     lines), so need to account for TLB latency
4055  *
4056  *   The normal calculation is:
4057  *     watermark = dotclock * bytes per pixel * latency
4058  *   where latency is platform & configuration dependent (we assume pessimal
4059  *   values here).
4060  *
4061  *   The SR calculation is:
4062  *     watermark = (trunc(latency/line time)+1) * surface width *
4063  *       bytes per pixel
4064  *   where
4065  *     line time = htotal / dotclock
4066  *     surface width = hdisplay for normal plane and 64 for cursor
4067  *   and latency is assumed to be high, as above.
4068  *
4069  * The final value programmed to the register should always be rounded up,
4070  * and include an extra 2 entries to account for clock crossings.
4071  *
4072  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4073  * to set the non-SR watermarks to 8.
4074  */
4075 void intel_update_watermarks(struct drm_crtc *crtc)
4076 {
4077         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4078
4079         if (dev_priv->display.update_wm)
4080                 dev_priv->display.update_wm(crtc);
4081 }
4082
4083 /*
4084  * Lock protecting IPS related data structures
4085  */
4086 DEFINE_SPINLOCK(mchdev_lock);
4087
4088 /* Global for IPS driver to get at the current i915 device. Protected by
4089  * mchdev_lock. */
4090 static struct drm_i915_private *i915_mch_dev;
4091
4092 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4093 {
4094         struct drm_i915_private *dev_priv = dev->dev_private;
4095         u16 rgvswctl;
4096
4097         assert_spin_locked(&mchdev_lock);
4098
4099         rgvswctl = I915_READ16(MEMSWCTL);
4100         if (rgvswctl & MEMCTL_CMD_STS) {
4101                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4102                 return false; /* still busy with another command */
4103         }
4104
4105         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4106                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4107         I915_WRITE16(MEMSWCTL, rgvswctl);
4108         POSTING_READ16(MEMSWCTL);
4109
4110         rgvswctl |= MEMCTL_CMD_STS;
4111         I915_WRITE16(MEMSWCTL, rgvswctl);
4112
4113         return true;
4114 }
4115
4116 static void ironlake_enable_drps(struct drm_device *dev)
4117 {
4118         struct drm_i915_private *dev_priv = dev->dev_private;
4119         u32 rgvmodectl = I915_READ(MEMMODECTL);
4120         u8 fmax, fmin, fstart, vstart;
4121
4122         spin_lock_irq(&mchdev_lock);
4123
4124         /* Enable temp reporting */
4125         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4126         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4127
4128         /* 100ms RC evaluation intervals */
4129         I915_WRITE(RCUPEI, 100000);
4130         I915_WRITE(RCDNEI, 100000);
4131
4132         /* Set max/min thresholds to 90ms and 80ms respectively */
4133         I915_WRITE(RCBMAXAVG, 90000);
4134         I915_WRITE(RCBMINAVG, 80000);
4135
4136         I915_WRITE(MEMIHYST, 1);
4137
4138         /* Set up min, max, and cur for interrupt handling */
4139         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4140         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4141         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4142                 MEMMODE_FSTART_SHIFT;
4143
4144         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4145                 PXVFREQ_PX_SHIFT;
4146
4147         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4148         dev_priv->ips.fstart = fstart;
4149
4150         dev_priv->ips.max_delay = fstart;
4151         dev_priv->ips.min_delay = fmin;
4152         dev_priv->ips.cur_delay = fstart;
4153
4154         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4155                          fmax, fmin, fstart);
4156
4157         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4158
4159         /*
4160          * Interrupts will be enabled in ironlake_irq_postinstall
4161          */
4162
4163         I915_WRITE(VIDSTART, vstart);
4164         POSTING_READ(VIDSTART);
4165
4166         rgvmodectl |= MEMMODE_SWMODE_EN;
4167         I915_WRITE(MEMMODECTL, rgvmodectl);
4168
4169         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4170                 DRM_ERROR("stuck trying to change perf mode\n");
4171         mdelay(1);
4172
4173         ironlake_set_drps(dev, fstart);
4174
4175         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4176                 I915_READ(DDREC) + I915_READ(CSIEC);
4177         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4178         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4179         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4180
4181         spin_unlock_irq(&mchdev_lock);
4182 }
4183
4184 static void ironlake_disable_drps(struct drm_device *dev)
4185 {
4186         struct drm_i915_private *dev_priv = dev->dev_private;
4187         u16 rgvswctl;
4188
4189         spin_lock_irq(&mchdev_lock);
4190
4191         rgvswctl = I915_READ16(MEMSWCTL);
4192
4193         /* Ack interrupts, disable EFC interrupt */
4194         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4195         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4196         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4197         I915_WRITE(DEIIR, DE_PCU_EVENT);
4198         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4199
4200         /* Go back to the starting frequency */
4201         ironlake_set_drps(dev, dev_priv->ips.fstart);
4202         mdelay(1);
4203         rgvswctl |= MEMCTL_CMD_STS;
4204         I915_WRITE(MEMSWCTL, rgvswctl);
4205         mdelay(1);
4206
4207         spin_unlock_irq(&mchdev_lock);
4208 }
4209
4210 /* There's a funny hw issue where the hw returns all 0 when reading from
4211  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4212  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4213  * all limits and the gpu stuck at whatever frequency it is at atm).
4214  */
4215 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4216 {
4217         u32 limits;
4218
4219         /* Only set the down limit when we've reached the lowest level to avoid
4220          * getting more interrupts, otherwise leave this clear. This prevents a
4221          * race in the hw when coming out of rc6: There's a tiny window where
4222          * the hw runs at the minimal clock before selecting the desired
4223          * frequency, if the down threshold expires in that window we will not
4224          * receive a down interrupt. */
4225         if (IS_GEN9(dev_priv->dev)) {
4226                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4227                 if (val <= dev_priv->rps.min_freq_softlimit)
4228                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4229         } else {
4230                 limits = dev_priv->rps.max_freq_softlimit << 24;
4231                 if (val <= dev_priv->rps.min_freq_softlimit)
4232                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4233         }
4234
4235         return limits;
4236 }
4237
4238 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4239 {
4240         int new_power;
4241         u32 threshold_up = 0, threshold_down = 0; /* in % */
4242         u32 ei_up = 0, ei_down = 0;
4243
4244         new_power = dev_priv->rps.power;
4245         switch (dev_priv->rps.power) {
4246         case LOW_POWER:
4247                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4248                         new_power = BETWEEN;
4249                 break;
4250
4251         case BETWEEN:
4252                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4253                         new_power = LOW_POWER;
4254                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4255                         new_power = HIGH_POWER;
4256                 break;
4257
4258         case HIGH_POWER:
4259                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4260                         new_power = BETWEEN;
4261                 break;
4262         }
4263         /* Max/min bins are special */
4264         if (val <= dev_priv->rps.min_freq_softlimit)
4265                 new_power = LOW_POWER;
4266         if (val >= dev_priv->rps.max_freq_softlimit)
4267                 new_power = HIGH_POWER;
4268         if (new_power == dev_priv->rps.power)
4269                 return;
4270
4271         /* Note the units here are not exactly 1us, but 1280ns. */
4272         switch (new_power) {
4273         case LOW_POWER:
4274                 /* Upclock if more than 95% busy over 16ms */
4275                 ei_up = 16000;
4276                 threshold_up = 95;
4277
4278                 /* Downclock if less than 85% busy over 32ms */
4279                 ei_down = 32000;
4280                 threshold_down = 85;
4281                 break;
4282
4283         case BETWEEN:
4284                 /* Upclock if more than 90% busy over 13ms */
4285                 ei_up = 13000;
4286                 threshold_up = 90;
4287
4288                 /* Downclock if less than 75% busy over 32ms */
4289                 ei_down = 32000;
4290                 threshold_down = 75;
4291                 break;
4292
4293         case HIGH_POWER:
4294                 /* Upclock if more than 85% busy over 10ms */
4295                 ei_up = 10000;
4296                 threshold_up = 85;
4297
4298                 /* Downclock if less than 60% busy over 32ms */
4299                 ei_down = 32000;
4300                 threshold_down = 60;
4301                 break;
4302         }
4303
4304         I915_WRITE(GEN6_RP_UP_EI,
4305                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4306         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4307                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4308
4309         I915_WRITE(GEN6_RP_DOWN_EI,
4310                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4311         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4312                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4313
4314          I915_WRITE(GEN6_RP_CONTROL,
4315                     GEN6_RP_MEDIA_TURBO |
4316                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4317                     GEN6_RP_MEDIA_IS_GFX |
4318                     GEN6_RP_ENABLE |
4319                     GEN6_RP_UP_BUSY_AVG |
4320                     GEN6_RP_DOWN_IDLE_AVG);
4321
4322         dev_priv->rps.power = new_power;
4323         dev_priv->rps.up_threshold = threshold_up;
4324         dev_priv->rps.down_threshold = threshold_down;
4325         dev_priv->rps.last_adj = 0;
4326 }
4327
4328 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4329 {
4330         u32 mask = 0;
4331
4332         if (val > dev_priv->rps.min_freq_softlimit)
4333                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4334         if (val < dev_priv->rps.max_freq_softlimit)
4335                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4336
4337         mask &= dev_priv->pm_rps_events;
4338
4339         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4340 }
4341
4342 /* gen6_set_rps is called to update the frequency request, but should also be
4343  * called when the range (min_delay and max_delay) is modified so that we can
4344  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4345 static void gen6_set_rps(struct drm_device *dev, u8 val)
4346 {
4347         struct drm_i915_private *dev_priv = dev->dev_private;
4348
4349         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4350         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4351                 return;
4352
4353         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4354         WARN_ON(val > dev_priv->rps.max_freq);
4355         WARN_ON(val < dev_priv->rps.min_freq);
4356
4357         /* min/max delay may still have been modified so be sure to
4358          * write the limits value.
4359          */
4360         if (val != dev_priv->rps.cur_freq) {
4361                 gen6_set_rps_thresholds(dev_priv, val);
4362
4363                 if (IS_GEN9(dev))
4364                         I915_WRITE(GEN6_RPNSWREQ,
4365                                    GEN9_FREQUENCY(val));
4366                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4367                         I915_WRITE(GEN6_RPNSWREQ,
4368                                    HSW_FREQUENCY(val));
4369                 else
4370                         I915_WRITE(GEN6_RPNSWREQ,
4371                                    GEN6_FREQUENCY(val) |
4372                                    GEN6_OFFSET(0) |
4373                                    GEN6_AGGRESSIVE_TURBO);
4374         }
4375
4376         /* Make sure we continue to get interrupts
4377          * until we hit the minimum or maximum frequencies.
4378          */
4379         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4380         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4381
4382         POSTING_READ(GEN6_RPNSWREQ);
4383
4384         dev_priv->rps.cur_freq = val;
4385         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4386 }
4387
4388 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4389 {
4390         struct drm_i915_private *dev_priv = dev->dev_private;
4391
4392         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4393         WARN_ON(val > dev_priv->rps.max_freq);
4394         WARN_ON(val < dev_priv->rps.min_freq);
4395
4396         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4397                       "Odd GPU freq value\n"))
4398                 val &= ~1;
4399
4400         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4401
4402         if (val != dev_priv->rps.cur_freq) {
4403                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4404                 if (!IS_CHERRYVIEW(dev_priv))
4405                         gen6_set_rps_thresholds(dev_priv, val);
4406         }
4407
4408         dev_priv->rps.cur_freq = val;
4409         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4410 }
4411
4412 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4413  *
4414  * * If Gfx is Idle, then
4415  * 1. Forcewake Media well.
4416  * 2. Request idle freq.
4417  * 3. Release Forcewake of Media well.
4418 */
4419 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4420 {
4421         u32 val = dev_priv->rps.idle_freq;
4422
4423         if (dev_priv->rps.cur_freq <= val)
4424                 return;
4425
4426         /* Wake up the media well, as that takes a lot less
4427          * power than the Render well. */
4428         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4429         valleyview_set_rps(dev_priv->dev, val);
4430         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4431 }
4432
4433 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4434 {
4435         mutex_lock(&dev_priv->rps.hw_lock);
4436         if (dev_priv->rps.enabled) {
4437                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4438                         gen6_rps_reset_ei(dev_priv);
4439                 I915_WRITE(GEN6_PMINTRMSK,
4440                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4441         }
4442         mutex_unlock(&dev_priv->rps.hw_lock);
4443 }
4444
4445 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4446 {
4447         struct drm_device *dev = dev_priv->dev;
4448
4449         mutex_lock(&dev_priv->rps.hw_lock);
4450         if (dev_priv->rps.enabled) {
4451                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4452                         vlv_set_rps_idle(dev_priv);
4453                 else
4454                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4455                 dev_priv->rps.last_adj = 0;
4456                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4457         }
4458         mutex_unlock(&dev_priv->rps.hw_lock);
4459
4460         spin_lock(&dev_priv->rps.client_lock);
4461         while (!list_empty(&dev_priv->rps.clients))
4462                 list_del_init(dev_priv->rps.clients.next);
4463         spin_unlock(&dev_priv->rps.client_lock);
4464 }
4465
4466 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4467                     struct intel_rps_client *rps,
4468                     unsigned long submitted)
4469 {
4470         /* This is intentionally racy! We peek at the state here, then
4471          * validate inside the RPS worker.
4472          */
4473         if (!(dev_priv->mm.busy &&
4474               dev_priv->rps.enabled &&
4475               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4476                 return;
4477
4478         /* Force a RPS boost (and don't count it against the client) if
4479          * the GPU is severely congested.
4480          */
4481         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4482                 rps = NULL;
4483
4484         spin_lock(&dev_priv->rps.client_lock);
4485         if (rps == NULL || list_empty(&rps->link)) {
4486                 spin_lock_irq(&dev_priv->irq_lock);
4487                 if (dev_priv->rps.interrupts_enabled) {
4488                         dev_priv->rps.client_boost = true;
4489                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4490                 }
4491                 spin_unlock_irq(&dev_priv->irq_lock);
4492
4493                 if (rps != NULL) {
4494                         list_add(&rps->link, &dev_priv->rps.clients);
4495                         rps->boosts++;
4496                 } else
4497                         dev_priv->rps.boosts++;
4498         }
4499         spin_unlock(&dev_priv->rps.client_lock);
4500 }
4501
4502 void intel_set_rps(struct drm_device *dev, u8 val)
4503 {
4504         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4505                 valleyview_set_rps(dev, val);
4506         else
4507                 gen6_set_rps(dev, val);
4508 }
4509
4510 static void gen9_disable_rps(struct drm_device *dev)
4511 {
4512         struct drm_i915_private *dev_priv = dev->dev_private;
4513
4514         I915_WRITE(GEN6_RC_CONTROL, 0);
4515         I915_WRITE(GEN9_PG_ENABLE, 0);
4516 }
4517
4518 static void gen6_disable_rps(struct drm_device *dev)
4519 {
4520         struct drm_i915_private *dev_priv = dev->dev_private;
4521
4522         I915_WRITE(GEN6_RC_CONTROL, 0);
4523         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4524 }
4525
4526 static void cherryview_disable_rps(struct drm_device *dev)
4527 {
4528         struct drm_i915_private *dev_priv = dev->dev_private;
4529
4530         I915_WRITE(GEN6_RC_CONTROL, 0);
4531 }
4532
4533 static void valleyview_disable_rps(struct drm_device *dev)
4534 {
4535         struct drm_i915_private *dev_priv = dev->dev_private;
4536
4537         /* we're doing forcewake before Disabling RC6,
4538          * This what the BIOS expects when going into suspend */
4539         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4540
4541         I915_WRITE(GEN6_RC_CONTROL, 0);
4542
4543         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4544 }
4545
4546 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4547 {
4548         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4549                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4550                         mode = GEN6_RC_CTL_RC6_ENABLE;
4551                 else
4552                         mode = 0;
4553         }
4554         if (HAS_RC6p(dev))
4555                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4556                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4557                               onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4558                               onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4559
4560         else
4561                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4562                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4563 }
4564
4565 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4566 {
4567         /* No RC6 before Ironlake and code is gone for ilk. */
4568         if (INTEL_INFO(dev)->gen < 6)
4569                 return 0;
4570
4571         /* Respect the kernel parameter if it is set */
4572         if (enable_rc6 >= 0) {
4573                 int mask;
4574
4575                 if (HAS_RC6p(dev))
4576                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4577                                INTEL_RC6pp_ENABLE;
4578                 else
4579                         mask = INTEL_RC6_ENABLE;
4580
4581                 if ((enable_rc6 & mask) != enable_rc6)
4582                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4583                                       enable_rc6 & mask, enable_rc6, mask);
4584
4585                 return enable_rc6 & mask;
4586         }
4587
4588         if (IS_IVYBRIDGE(dev))
4589                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4590
4591         return INTEL_RC6_ENABLE;
4592 }
4593
4594 int intel_enable_rc6(const struct drm_device *dev)
4595 {
4596         return i915.enable_rc6;
4597 }
4598
4599 static void gen6_init_rps_frequencies(struct drm_device *dev)
4600 {
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602         uint32_t rp_state_cap;
4603         u32 ddcc_status = 0;
4604         int ret;
4605
4606         /* All of these values are in units of 50MHz */
4607         dev_priv->rps.cur_freq          = 0;
4608         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4609         if (IS_BROXTON(dev)) {
4610                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4611                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4612                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4613                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4614         } else {
4615                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4616                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4617                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4618                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4619         }
4620
4621         /* hw_max = RP0 until we check for overclocking */
4622         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4623
4624         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4625         if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4626             IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4627                 ret = sandybridge_pcode_read(dev_priv,
4628                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4629                                         &ddcc_status);
4630                 if (0 == ret)
4631                         dev_priv->rps.efficient_freq =
4632                                 clamp_t(u8,
4633                                         ((ddcc_status >> 8) & 0xff),
4634                                         dev_priv->rps.min_freq,
4635                                         dev_priv->rps.max_freq);
4636         }
4637
4638         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4639                 /* Store the frequency values in 16.66 MHZ units, which is
4640                    the natural hardware unit for SKL */
4641                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4642                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4643                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4644                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4645                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4646         }
4647
4648         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4649
4650         /* Preserve min/max settings in case of re-init */
4651         if (dev_priv->rps.max_freq_softlimit == 0)
4652                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4653
4654         if (dev_priv->rps.min_freq_softlimit == 0) {
4655                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4656                         dev_priv->rps.min_freq_softlimit =
4657                                 max_t(int, dev_priv->rps.efficient_freq,
4658                                       intel_freq_opcode(dev_priv, 450));
4659                 else
4660                         dev_priv->rps.min_freq_softlimit =
4661                                 dev_priv->rps.min_freq;
4662         }
4663 }
4664
4665 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4666 static void gen9_enable_rps(struct drm_device *dev)
4667 {
4668         struct drm_i915_private *dev_priv = dev->dev_private;
4669
4670         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4671
4672         gen6_init_rps_frequencies(dev);
4673
4674         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4675         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4676                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4677                 return;
4678         }
4679
4680         /* Program defaults and thresholds for RPS*/
4681         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4682                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4683
4684         /* 1 second timeout*/
4685         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4686                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4687
4688         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4689
4690         /* Leaning on the below call to gen6_set_rps to program/setup the
4691          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4692          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4693         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4694         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4695
4696         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4697 }
4698
4699 static void gen9_enable_rc6(struct drm_device *dev)
4700 {
4701         struct drm_i915_private *dev_priv = dev->dev_private;
4702         struct intel_engine_cs *ring;
4703         uint32_t rc6_mask = 0;
4704         int unused;
4705
4706         /* 1a: Software RC state - RC0 */
4707         I915_WRITE(GEN6_RC_STATE, 0);
4708
4709         /* 1b: Get forcewake during program sequence. Although the driver
4710          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4711         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4712
4713         /* 2a: Disable RC states. */
4714         I915_WRITE(GEN6_RC_CONTROL, 0);
4715
4716         /* 2b: Program RC6 thresholds.*/
4717
4718         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4719         if (IS_SKYLAKE(dev))
4720                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4721         else
4722                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4723         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4724         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4725         for_each_ring(ring, dev_priv, unused)
4726                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4727
4728         if (HAS_GUC_UCODE(dev))
4729                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4730
4731         I915_WRITE(GEN6_RC_SLEEP, 0);
4732
4733         /* 2c: Program Coarse Power Gating Policies. */
4734         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4735         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4736
4737         /* 3a: Enable RC6 */
4738         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4739                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4740         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4741         /* WaRsUseTimeoutMode */
4742         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4743             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4744                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4745                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4746                            GEN7_RC_CTL_TO_MODE |
4747                            rc6_mask);
4748         } else {
4749                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4750                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4751                            GEN6_RC_CTL_EI_MODE(1) |
4752                            rc6_mask);
4753         }
4754
4755         /*
4756          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4757          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4758          */
4759         if (NEEDS_WaRsDisableCoarsePowerGating(dev))
4760                 I915_WRITE(GEN9_PG_ENABLE, 0);
4761         else
4762                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4763                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4764
4765         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4766
4767 }
4768
4769 static void gen8_enable_rps(struct drm_device *dev)
4770 {
4771         struct drm_i915_private *dev_priv = dev->dev_private;
4772         struct intel_engine_cs *ring;
4773         uint32_t rc6_mask = 0;
4774         int unused;
4775
4776         /* 1a: Software RC state - RC0 */
4777         I915_WRITE(GEN6_RC_STATE, 0);
4778
4779         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4780          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4781         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4782
4783         /* 2a: Disable RC states. */
4784         I915_WRITE(GEN6_RC_CONTROL, 0);
4785
4786         /* Initialize rps frequencies */
4787         gen6_init_rps_frequencies(dev);
4788
4789         /* 2b: Program RC6 thresholds.*/
4790         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4791         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4792         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4793         for_each_ring(ring, dev_priv, unused)
4794                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4795         I915_WRITE(GEN6_RC_SLEEP, 0);
4796         if (IS_BROADWELL(dev))
4797                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4798         else
4799                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4800
4801         /* 3: Enable RC6 */
4802         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4803                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4804         intel_print_rc6_info(dev, rc6_mask);
4805         if (IS_BROADWELL(dev))
4806                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4807                                 GEN7_RC_CTL_TO_MODE |
4808                                 rc6_mask);
4809         else
4810                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4811                                 GEN6_RC_CTL_EI_MODE(1) |
4812                                 rc6_mask);
4813
4814         /* 4 Program defaults and thresholds for RPS*/
4815         I915_WRITE(GEN6_RPNSWREQ,
4816                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4817         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4818                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4819         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4820         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4821
4822         /* Docs recommend 900MHz, and 300 MHz respectively */
4823         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4824                    dev_priv->rps.max_freq_softlimit << 24 |
4825                    dev_priv->rps.min_freq_softlimit << 16);
4826
4827         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4828         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4829         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4830         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4831
4832         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4833
4834         /* 5: Enable RPS */
4835         I915_WRITE(GEN6_RP_CONTROL,
4836                    GEN6_RP_MEDIA_TURBO |
4837                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4838                    GEN6_RP_MEDIA_IS_GFX |
4839                    GEN6_RP_ENABLE |
4840                    GEN6_RP_UP_BUSY_AVG |
4841                    GEN6_RP_DOWN_IDLE_AVG);
4842
4843         /* 6: Ring frequency + overclocking (our driver does this later */
4844
4845         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4846         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4847
4848         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4849 }
4850
4851 static void gen6_enable_rps(struct drm_device *dev)
4852 {
4853         struct drm_i915_private *dev_priv = dev->dev_private;
4854         struct intel_engine_cs *ring;
4855         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4856         u32 gtfifodbg;
4857         int rc6_mode;
4858         int i, ret;
4859
4860         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4861
4862         /* Here begins a magic sequence of register writes to enable
4863          * auto-downclocking.
4864          *
4865          * Perhaps there might be some value in exposing these to
4866          * userspace...
4867          */
4868         I915_WRITE(GEN6_RC_STATE, 0);
4869
4870         /* Clear the DBG now so we don't confuse earlier errors */
4871         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4872                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4873                 I915_WRITE(GTFIFODBG, gtfifodbg);
4874         }
4875
4876         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4877
4878         /* Initialize rps frequencies */
4879         gen6_init_rps_frequencies(dev);
4880
4881         /* disable the counters and set deterministic thresholds */
4882         I915_WRITE(GEN6_RC_CONTROL, 0);
4883
4884         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4885         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4886         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4887         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4888         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4889
4890         for_each_ring(ring, dev_priv, i)
4891                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4892
4893         I915_WRITE(GEN6_RC_SLEEP, 0);
4894         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4895         if (IS_IVYBRIDGE(dev))
4896                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4897         else
4898                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4899         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4900         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4901
4902         /* Check if we are enabling RC6 */
4903         rc6_mode = intel_enable_rc6(dev_priv->dev);
4904         if (rc6_mode & INTEL_RC6_ENABLE)
4905                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4906
4907         /* We don't use those on Haswell */
4908         if (!IS_HASWELL(dev)) {
4909                 if (rc6_mode & INTEL_RC6p_ENABLE)
4910                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4911
4912                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4913                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4914         }
4915
4916         intel_print_rc6_info(dev, rc6_mask);
4917
4918         I915_WRITE(GEN6_RC_CONTROL,
4919                    rc6_mask |
4920                    GEN6_RC_CTL_EI_MODE(1) |
4921                    GEN6_RC_CTL_HW_ENABLE);
4922
4923         /* Power down if completely idle for over 50ms */
4924         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4925         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4926
4927         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4928         if (ret)
4929                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4930
4931         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4932         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4933                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4934                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4935                                  (pcu_mbox & 0xff) * 50);
4936                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4937         }
4938
4939         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4940         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4941
4942         rc6vids = 0;
4943         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4944         if (IS_GEN6(dev) && ret) {
4945                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4946         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4947                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4948                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4949                 rc6vids &= 0xffff00;
4950                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4951                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4952                 if (ret)
4953                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4954         }
4955
4956         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4957 }
4958
4959 static void __gen6_update_ring_freq(struct drm_device *dev)
4960 {
4961         struct drm_i915_private *dev_priv = dev->dev_private;
4962         int min_freq = 15;
4963         unsigned int gpu_freq;
4964         unsigned int max_ia_freq, min_ring_freq;
4965         unsigned int max_gpu_freq, min_gpu_freq;
4966         int scaling_factor = 180;
4967         struct cpufreq_policy *policy;
4968
4969         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4970
4971         policy = cpufreq_cpu_get(0);
4972         if (policy) {
4973                 max_ia_freq = policy->cpuinfo.max_freq;
4974                 cpufreq_cpu_put(policy);
4975         } else {
4976                 /*
4977                  * Default to measured freq if none found, PCU will ensure we
4978                  * don't go over
4979                  */
4980                 max_ia_freq = tsc_khz;
4981         }
4982
4983         /* Convert from kHz to MHz */
4984         max_ia_freq /= 1000;
4985
4986         min_ring_freq = I915_READ(DCLK) & 0xf;
4987         /* convert DDR frequency from units of 266.6MHz to bandwidth */
4988         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4989
4990         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4991                 /* Convert GT frequency to 50 HZ units */
4992                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4993                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4994         } else {
4995                 min_gpu_freq = dev_priv->rps.min_freq;
4996                 max_gpu_freq = dev_priv->rps.max_freq;
4997         }
4998
4999         /*
5000          * For each potential GPU frequency, load a ring frequency we'd like
5001          * to use for memory access.  We do this by specifying the IA frequency
5002          * the PCU should use as a reference to determine the ring frequency.
5003          */
5004         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5005                 int diff = max_gpu_freq - gpu_freq;
5006                 unsigned int ia_freq = 0, ring_freq = 0;
5007
5008                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5009                         /*
5010                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5011                          * No floor required for ring frequency on SKL.
5012                          */
5013                         ring_freq = gpu_freq;
5014                 } else if (INTEL_INFO(dev)->gen >= 8) {
5015                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5016                         ring_freq = max(min_ring_freq, gpu_freq);
5017                 } else if (IS_HASWELL(dev)) {
5018                         ring_freq = mult_frac(gpu_freq, 5, 4);
5019                         ring_freq = max(min_ring_freq, ring_freq);
5020                         /* leave ia_freq as the default, chosen by cpufreq */
5021                 } else {
5022                         /* On older processors, there is no separate ring
5023                          * clock domain, so in order to boost the bandwidth
5024                          * of the ring, we need to upclock the CPU (ia_freq).
5025                          *
5026                          * For GPU frequencies less than 750MHz,
5027                          * just use the lowest ring freq.
5028                          */
5029                         if (gpu_freq < min_freq)
5030                                 ia_freq = 800;
5031                         else
5032                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5033                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5034                 }
5035
5036                 sandybridge_pcode_write(dev_priv,
5037                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5038                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5039                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5040                                         gpu_freq);
5041         }
5042 }
5043
5044 void gen6_update_ring_freq(struct drm_device *dev)
5045 {
5046         struct drm_i915_private *dev_priv = dev->dev_private;
5047
5048         if (!HAS_CORE_RING_FREQ(dev))
5049                 return;
5050
5051         mutex_lock(&dev_priv->rps.hw_lock);
5052         __gen6_update_ring_freq(dev);
5053         mutex_unlock(&dev_priv->rps.hw_lock);
5054 }
5055
5056 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5057 {
5058         struct drm_device *dev = dev_priv->dev;
5059         u32 val, rp0;
5060
5061         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5062
5063         switch (INTEL_INFO(dev)->eu_total) {
5064         case 8:
5065                 /* (2 * 4) config */
5066                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5067                 break;
5068         case 12:
5069                 /* (2 * 6) config */
5070                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5071                 break;
5072         case 16:
5073                 /* (2 * 8) config */
5074         default:
5075                 /* Setting (2 * 8) Min RP0 for any other combination */
5076                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5077                 break;
5078         }
5079
5080         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5081
5082         return rp0;
5083 }
5084
5085 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5086 {
5087         u32 val, rpe;
5088
5089         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5090         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5091
5092         return rpe;
5093 }
5094
5095 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5096 {
5097         u32 val, rp1;
5098
5099         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5100         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5101
5102         return rp1;
5103 }
5104
5105 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5106 {
5107         u32 val, rp1;
5108
5109         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5110
5111         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5112
5113         return rp1;
5114 }
5115
5116 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5117 {
5118         u32 val, rp0;
5119
5120         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5121
5122         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5123         /* Clamp to max */
5124         rp0 = min_t(u32, rp0, 0xea);
5125
5126         return rp0;
5127 }
5128
5129 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5130 {
5131         u32 val, rpe;
5132
5133         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5134         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5135         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5136         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5137
5138         return rpe;
5139 }
5140
5141 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5142 {
5143         u32 val;
5144
5145         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5146         /*
5147          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5148          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5149          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5150          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5151          * to make sure it matches what Punit accepts.
5152          */
5153         return max_t(u32, val, 0xc0);
5154 }
5155
5156 /* Check that the pctx buffer wasn't move under us. */
5157 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5158 {
5159         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5160
5161         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5162                              dev_priv->vlv_pctx->stolen->start);
5163 }
5164
5165
5166 /* Check that the pcbr address is not empty. */
5167 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5168 {
5169         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5170
5171         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5172 }
5173
5174 static void cherryview_setup_pctx(struct drm_device *dev)
5175 {
5176         struct drm_i915_private *dev_priv = dev->dev_private;
5177         unsigned long pctx_paddr, paddr;
5178         struct i915_gtt *gtt = &dev_priv->gtt;
5179         u32 pcbr;
5180         int pctx_size = 32*1024;
5181
5182         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5183
5184         pcbr = I915_READ(VLV_PCBR);
5185         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5186                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5187                 paddr = (dev_priv->mm.stolen_base +
5188                          (gtt->stolen_size - pctx_size));
5189
5190                 pctx_paddr = (paddr & (~4095));
5191                 I915_WRITE(VLV_PCBR, pctx_paddr);
5192         }
5193
5194         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5195 }
5196
5197 static void valleyview_setup_pctx(struct drm_device *dev)
5198 {
5199         struct drm_i915_private *dev_priv = dev->dev_private;
5200         struct drm_i915_gem_object *pctx;
5201         unsigned long pctx_paddr;
5202         u32 pcbr;
5203         int pctx_size = 24*1024;
5204
5205         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5206
5207         pcbr = I915_READ(VLV_PCBR);
5208         if (pcbr) {
5209                 /* BIOS set it up already, grab the pre-alloc'd space */
5210                 int pcbr_offset;
5211
5212                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5213                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5214                                                                       pcbr_offset,
5215                                                                       I915_GTT_OFFSET_NONE,
5216                                                                       pctx_size);
5217                 goto out;
5218         }
5219
5220         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5221
5222         /*
5223          * From the Gunit register HAS:
5224          * The Gfx driver is expected to program this register and ensure
5225          * proper allocation within Gfx stolen memory.  For example, this
5226          * register should be programmed such than the PCBR range does not
5227          * overlap with other ranges, such as the frame buffer, protected
5228          * memory, or any other relevant ranges.
5229          */
5230         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5231         if (!pctx) {
5232                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5233                 return;
5234         }
5235
5236         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5237         I915_WRITE(VLV_PCBR, pctx_paddr);
5238
5239 out:
5240         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5241         dev_priv->vlv_pctx = pctx;
5242 }
5243
5244 static void valleyview_cleanup_pctx(struct drm_device *dev)
5245 {
5246         struct drm_i915_private *dev_priv = dev->dev_private;
5247
5248         if (WARN_ON(!dev_priv->vlv_pctx))
5249                 return;
5250
5251         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5252         dev_priv->vlv_pctx = NULL;
5253 }
5254
5255 static void valleyview_init_gt_powersave(struct drm_device *dev)
5256 {
5257         struct drm_i915_private *dev_priv = dev->dev_private;
5258         u32 val;
5259
5260         valleyview_setup_pctx(dev);
5261
5262         mutex_lock(&dev_priv->rps.hw_lock);
5263
5264         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5265         switch ((val >> 6) & 3) {
5266         case 0:
5267         case 1:
5268                 dev_priv->mem_freq = 800;
5269                 break;
5270         case 2:
5271                 dev_priv->mem_freq = 1066;
5272                 break;
5273         case 3:
5274                 dev_priv->mem_freq = 1333;
5275                 break;
5276         }
5277         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5278
5279         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5280         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5281         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5282                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5283                          dev_priv->rps.max_freq);
5284
5285         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5286         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5287                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5288                          dev_priv->rps.efficient_freq);
5289
5290         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5291         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5292                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5293                          dev_priv->rps.rp1_freq);
5294
5295         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5296         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5297                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5298                          dev_priv->rps.min_freq);
5299
5300         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5301
5302         /* Preserve min/max settings in case of re-init */
5303         if (dev_priv->rps.max_freq_softlimit == 0)
5304                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5305
5306         if (dev_priv->rps.min_freq_softlimit == 0)
5307                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5308
5309         mutex_unlock(&dev_priv->rps.hw_lock);
5310 }
5311
5312 static void cherryview_init_gt_powersave(struct drm_device *dev)
5313 {
5314         struct drm_i915_private *dev_priv = dev->dev_private;
5315         u32 val;
5316
5317         cherryview_setup_pctx(dev);
5318
5319         mutex_lock(&dev_priv->rps.hw_lock);
5320
5321         mutex_lock(&dev_priv->sb_lock);
5322         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5323         mutex_unlock(&dev_priv->sb_lock);
5324
5325         switch ((val >> 2) & 0x7) {
5326         case 3:
5327                 dev_priv->mem_freq = 2000;
5328                 break;
5329         default:
5330                 dev_priv->mem_freq = 1600;
5331                 break;
5332         }
5333         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5334
5335         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5336         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5337         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5338                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5339                          dev_priv->rps.max_freq);
5340
5341         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5342         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5343                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5344                          dev_priv->rps.efficient_freq);
5345
5346         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5347         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5348                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5349                          dev_priv->rps.rp1_freq);
5350
5351         /* PUnit validated range is only [RPe, RP0] */
5352         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5353         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5354                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5355                          dev_priv->rps.min_freq);
5356
5357         WARN_ONCE((dev_priv->rps.max_freq |
5358                    dev_priv->rps.efficient_freq |
5359                    dev_priv->rps.rp1_freq |
5360                    dev_priv->rps.min_freq) & 1,
5361                   "Odd GPU freq values\n");
5362
5363         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5364
5365         /* Preserve min/max settings in case of re-init */
5366         if (dev_priv->rps.max_freq_softlimit == 0)
5367                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5368
5369         if (dev_priv->rps.min_freq_softlimit == 0)
5370                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5371
5372         mutex_unlock(&dev_priv->rps.hw_lock);
5373 }
5374
5375 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5376 {
5377         valleyview_cleanup_pctx(dev);
5378 }
5379
5380 static void cherryview_enable_rps(struct drm_device *dev)
5381 {
5382         struct drm_i915_private *dev_priv = dev->dev_private;
5383         struct intel_engine_cs *ring;
5384         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5385         int i;
5386
5387         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5388
5389         gtfifodbg = I915_READ(GTFIFODBG);
5390         if (gtfifodbg) {
5391                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5392                                  gtfifodbg);
5393                 I915_WRITE(GTFIFODBG, gtfifodbg);
5394         }
5395
5396         cherryview_check_pctx(dev_priv);
5397
5398         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5399          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5400         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5401
5402         /*  Disable RC states. */
5403         I915_WRITE(GEN6_RC_CONTROL, 0);
5404
5405         /* 2a: Program RC6 thresholds.*/
5406         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5407         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5408         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5409
5410         for_each_ring(ring, dev_priv, i)
5411                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5412         I915_WRITE(GEN6_RC_SLEEP, 0);
5413
5414         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5415         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5416
5417         /* allows RC6 residency counter to work */
5418         I915_WRITE(VLV_COUNTER_CONTROL,
5419                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5420                                       VLV_MEDIA_RC6_COUNT_EN |
5421                                       VLV_RENDER_RC6_COUNT_EN));
5422
5423         /* For now we assume BIOS is allocating and populating the PCBR  */
5424         pcbr = I915_READ(VLV_PCBR);
5425
5426         /* 3: Enable RC6 */
5427         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5428                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5429                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5430
5431         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5432
5433         /* 4 Program defaults and thresholds for RPS*/
5434         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5435         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5436         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5437         I915_WRITE(GEN6_RP_UP_EI, 66000);
5438         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5439
5440         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5441
5442         /* 5: Enable RPS */
5443         I915_WRITE(GEN6_RP_CONTROL,
5444                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5445                    GEN6_RP_MEDIA_IS_GFX |
5446                    GEN6_RP_ENABLE |
5447                    GEN6_RP_UP_BUSY_AVG |
5448                    GEN6_RP_DOWN_IDLE_AVG);
5449
5450         /* Setting Fixed Bias */
5451         val = VLV_OVERRIDE_EN |
5452                   VLV_SOC_TDP_EN |
5453                   CHV_BIAS_CPU_50_SOC_50;
5454         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5455
5456         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5457
5458         /* RPS code assumes GPLL is used */
5459         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5460
5461         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5462         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5463
5464         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5465         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5466                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5467                          dev_priv->rps.cur_freq);
5468
5469         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5470                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5471                          dev_priv->rps.efficient_freq);
5472
5473         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5474
5475         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5476 }
5477
5478 static void valleyview_enable_rps(struct drm_device *dev)
5479 {
5480         struct drm_i915_private *dev_priv = dev->dev_private;
5481         struct intel_engine_cs *ring;
5482         u32 gtfifodbg, val, rc6_mode = 0;
5483         int i;
5484
5485         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5486
5487         valleyview_check_pctx(dev_priv);
5488
5489         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5490                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5491                                  gtfifodbg);
5492                 I915_WRITE(GTFIFODBG, gtfifodbg);
5493         }
5494
5495         /* If VLV, Forcewake all wells, else re-direct to regular path */
5496         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5497
5498         /*  Disable RC states. */
5499         I915_WRITE(GEN6_RC_CONTROL, 0);
5500
5501         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5502         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5503         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5504         I915_WRITE(GEN6_RP_UP_EI, 66000);
5505         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5506
5507         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5508
5509         I915_WRITE(GEN6_RP_CONTROL,
5510                    GEN6_RP_MEDIA_TURBO |
5511                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5512                    GEN6_RP_MEDIA_IS_GFX |
5513                    GEN6_RP_ENABLE |
5514                    GEN6_RP_UP_BUSY_AVG |
5515                    GEN6_RP_DOWN_IDLE_CONT);
5516
5517         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5518         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5519         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5520
5521         for_each_ring(ring, dev_priv, i)
5522                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5523
5524         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5525
5526         /* allows RC6 residency counter to work */
5527         I915_WRITE(VLV_COUNTER_CONTROL,
5528                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5529                                       VLV_RENDER_RC0_COUNT_EN |
5530                                       VLV_MEDIA_RC6_COUNT_EN |
5531                                       VLV_RENDER_RC6_COUNT_EN));
5532
5533         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5534                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5535
5536         intel_print_rc6_info(dev, rc6_mode);
5537
5538         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5539
5540         /* Setting Fixed Bias */
5541         val = VLV_OVERRIDE_EN |
5542                   VLV_SOC_TDP_EN |
5543                   VLV_BIAS_CPU_125_SOC_875;
5544         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5545
5546         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5547
5548         /* RPS code assumes GPLL is used */
5549         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5550
5551         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5552         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5553
5554         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5555         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5556                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5557                          dev_priv->rps.cur_freq);
5558
5559         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5560                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5561                          dev_priv->rps.efficient_freq);
5562
5563         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5564
5565         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5566 }
5567
5568 static unsigned long intel_pxfreq(u32 vidfreq)
5569 {
5570         unsigned long freq;
5571         int div = (vidfreq & 0x3f0000) >> 16;
5572         int post = (vidfreq & 0x3000) >> 12;
5573         int pre = (vidfreq & 0x7);
5574
5575         if (!pre)
5576                 return 0;
5577
5578         freq = ((div * 133333) / ((1<<post) * pre));
5579
5580         return freq;
5581 }
5582
5583 static const struct cparams {
5584         u16 i;
5585         u16 t;
5586         u16 m;
5587         u16 c;
5588 } cparams[] = {
5589         { 1, 1333, 301, 28664 },
5590         { 1, 1066, 294, 24460 },
5591         { 1, 800, 294, 25192 },
5592         { 0, 1333, 276, 27605 },
5593         { 0, 1066, 276, 27605 },
5594         { 0, 800, 231, 23784 },
5595 };
5596
5597 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5598 {
5599         u64 total_count, diff, ret;
5600         u32 count1, count2, count3, m = 0, c = 0;
5601         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5602         int i;
5603
5604         assert_spin_locked(&mchdev_lock);
5605
5606         diff1 = now - dev_priv->ips.last_time1;
5607
5608         /* Prevent division-by-zero if we are asking too fast.
5609          * Also, we don't get interesting results if we are polling
5610          * faster than once in 10ms, so just return the saved value
5611          * in such cases.
5612          */
5613         if (diff1 <= 10)
5614                 return dev_priv->ips.chipset_power;
5615
5616         count1 = I915_READ(DMIEC);
5617         count2 = I915_READ(DDREC);
5618         count3 = I915_READ(CSIEC);
5619
5620         total_count = count1 + count2 + count3;
5621
5622         /* FIXME: handle per-counter overflow */
5623         if (total_count < dev_priv->ips.last_count1) {
5624                 diff = ~0UL - dev_priv->ips.last_count1;
5625                 diff += total_count;
5626         } else {
5627                 diff = total_count - dev_priv->ips.last_count1;
5628         }
5629
5630         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5631                 if (cparams[i].i == dev_priv->ips.c_m &&
5632                     cparams[i].t == dev_priv->ips.r_t) {
5633                         m = cparams[i].m;
5634                         c = cparams[i].c;
5635                         break;
5636                 }
5637         }
5638
5639         diff = div_u64(diff, diff1);
5640         ret = ((m * diff) + c);
5641         ret = div_u64(ret, 10);
5642
5643         dev_priv->ips.last_count1 = total_count;
5644         dev_priv->ips.last_time1 = now;
5645
5646         dev_priv->ips.chipset_power = ret;
5647
5648         return ret;
5649 }
5650
5651 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5652 {
5653         struct drm_device *dev = dev_priv->dev;
5654         unsigned long val;
5655
5656         if (INTEL_INFO(dev)->gen != 5)
5657                 return 0;
5658
5659         spin_lock_irq(&mchdev_lock);
5660
5661         val = __i915_chipset_val(dev_priv);
5662
5663         spin_unlock_irq(&mchdev_lock);
5664
5665         return val;
5666 }
5667
5668 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5669 {
5670         unsigned long m, x, b;
5671         u32 tsfs;
5672
5673         tsfs = I915_READ(TSFS);
5674
5675         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5676         x = I915_READ8(TR1);
5677
5678         b = tsfs & TSFS_INTR_MASK;
5679
5680         return ((m * x) / 127) - b;
5681 }
5682
5683 static int _pxvid_to_vd(u8 pxvid)
5684 {
5685         if (pxvid == 0)
5686                 return 0;
5687
5688         if (pxvid >= 8 && pxvid < 31)
5689                 pxvid = 31;
5690
5691         return (pxvid + 2) * 125;
5692 }
5693
5694 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5695 {
5696         struct drm_device *dev = dev_priv->dev;
5697         const int vd = _pxvid_to_vd(pxvid);
5698         const int vm = vd - 1125;
5699
5700         if (INTEL_INFO(dev)->is_mobile)
5701                 return vm > 0 ? vm : 0;
5702
5703         return vd;
5704 }
5705
5706 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5707 {
5708         u64 now, diff, diffms;
5709         u32 count;
5710
5711         assert_spin_locked(&mchdev_lock);
5712
5713         now = ktime_get_raw_ns();
5714         diffms = now - dev_priv->ips.last_time2;
5715         do_div(diffms, NSEC_PER_MSEC);
5716
5717         /* Don't divide by 0 */
5718         if (!diffms)
5719                 return;
5720
5721         count = I915_READ(GFXEC);
5722
5723         if (count < dev_priv->ips.last_count2) {
5724                 diff = ~0UL - dev_priv->ips.last_count2;
5725                 diff += count;
5726         } else {
5727                 diff = count - dev_priv->ips.last_count2;
5728         }
5729
5730         dev_priv->ips.last_count2 = count;
5731         dev_priv->ips.last_time2 = now;
5732
5733         /* More magic constants... */
5734         diff = diff * 1181;
5735         diff = div_u64(diff, diffms * 10);
5736         dev_priv->ips.gfx_power = diff;
5737 }
5738
5739 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5740 {
5741         struct drm_device *dev = dev_priv->dev;
5742
5743         if (INTEL_INFO(dev)->gen != 5)
5744                 return;
5745
5746         spin_lock_irq(&mchdev_lock);
5747
5748         __i915_update_gfx_val(dev_priv);
5749
5750         spin_unlock_irq(&mchdev_lock);
5751 }
5752
5753 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5754 {
5755         unsigned long t, corr, state1, corr2, state2;
5756         u32 pxvid, ext_v;
5757
5758         assert_spin_locked(&mchdev_lock);
5759
5760         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5761         pxvid = (pxvid >> 24) & 0x7f;
5762         ext_v = pvid_to_extvid(dev_priv, pxvid);
5763
5764         state1 = ext_v;
5765
5766         t = i915_mch_val(dev_priv);
5767
5768         /* Revel in the empirically derived constants */
5769
5770         /* Correction factor in 1/100000 units */
5771         if (t > 80)
5772                 corr = ((t * 2349) + 135940);
5773         else if (t >= 50)
5774                 corr = ((t * 964) + 29317);
5775         else /* < 50 */
5776                 corr = ((t * 301) + 1004);
5777
5778         corr = corr * ((150142 * state1) / 10000 - 78642);
5779         corr /= 100000;
5780         corr2 = (corr * dev_priv->ips.corr);
5781
5782         state2 = (corr2 * state1) / 10000;
5783         state2 /= 100; /* convert to mW */
5784
5785         __i915_update_gfx_val(dev_priv);
5786
5787         return dev_priv->ips.gfx_power + state2;
5788 }
5789
5790 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5791 {
5792         struct drm_device *dev = dev_priv->dev;
5793         unsigned long val;
5794
5795         if (INTEL_INFO(dev)->gen != 5)
5796                 return 0;
5797
5798         spin_lock_irq(&mchdev_lock);
5799
5800         val = __i915_gfx_val(dev_priv);
5801
5802         spin_unlock_irq(&mchdev_lock);
5803
5804         return val;
5805 }
5806
5807 /**
5808  * i915_read_mch_val - return value for IPS use
5809  *
5810  * Calculate and return a value for the IPS driver to use when deciding whether
5811  * we have thermal and power headroom to increase CPU or GPU power budget.
5812  */
5813 unsigned long i915_read_mch_val(void)
5814 {
5815         struct drm_i915_private *dev_priv;
5816         unsigned long chipset_val, graphics_val, ret = 0;
5817
5818         spin_lock_irq(&mchdev_lock);
5819         if (!i915_mch_dev)
5820                 goto out_unlock;
5821         dev_priv = i915_mch_dev;
5822
5823         chipset_val = __i915_chipset_val(dev_priv);
5824         graphics_val = __i915_gfx_val(dev_priv);
5825
5826         ret = chipset_val + graphics_val;
5827
5828 out_unlock:
5829         spin_unlock_irq(&mchdev_lock);
5830
5831         return ret;
5832 }
5833 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5834
5835 /**
5836  * i915_gpu_raise - raise GPU frequency limit
5837  *
5838  * Raise the limit; IPS indicates we have thermal headroom.
5839  */
5840 bool i915_gpu_raise(void)
5841 {
5842         struct drm_i915_private *dev_priv;
5843         bool ret = true;
5844
5845         spin_lock_irq(&mchdev_lock);
5846         if (!i915_mch_dev) {
5847                 ret = false;
5848                 goto out_unlock;
5849         }
5850         dev_priv = i915_mch_dev;
5851
5852         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5853                 dev_priv->ips.max_delay--;
5854
5855 out_unlock:
5856         spin_unlock_irq(&mchdev_lock);
5857
5858         return ret;
5859 }
5860 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5861
5862 /**
5863  * i915_gpu_lower - lower GPU frequency limit
5864  *
5865  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5866  * frequency maximum.
5867  */
5868 bool i915_gpu_lower(void)
5869 {
5870         struct drm_i915_private *dev_priv;
5871         bool ret = true;
5872
5873         spin_lock_irq(&mchdev_lock);
5874         if (!i915_mch_dev) {
5875                 ret = false;
5876                 goto out_unlock;
5877         }
5878         dev_priv = i915_mch_dev;
5879
5880         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5881                 dev_priv->ips.max_delay++;
5882
5883 out_unlock:
5884         spin_unlock_irq(&mchdev_lock);
5885
5886         return ret;
5887 }
5888 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5889
5890 /**
5891  * i915_gpu_busy - indicate GPU business to IPS
5892  *
5893  * Tell the IPS driver whether or not the GPU is busy.
5894  */
5895 bool i915_gpu_busy(void)
5896 {
5897         struct drm_i915_private *dev_priv;
5898         struct intel_engine_cs *ring;
5899         bool ret = false;
5900         int i;
5901
5902         spin_lock_irq(&mchdev_lock);
5903         if (!i915_mch_dev)
5904                 goto out_unlock;
5905         dev_priv = i915_mch_dev;
5906
5907         for_each_ring(ring, dev_priv, i)
5908                 ret |= !list_empty(&ring->request_list);
5909
5910 out_unlock:
5911         spin_unlock_irq(&mchdev_lock);
5912
5913         return ret;
5914 }
5915 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5916
5917 /**
5918  * i915_gpu_turbo_disable - disable graphics turbo
5919  *
5920  * Disable graphics turbo by resetting the max frequency and setting the
5921  * current frequency to the default.
5922  */
5923 bool i915_gpu_turbo_disable(void)
5924 {
5925         struct drm_i915_private *dev_priv;
5926         bool ret = true;
5927
5928         spin_lock_irq(&mchdev_lock);
5929         if (!i915_mch_dev) {
5930                 ret = false;
5931                 goto out_unlock;
5932         }
5933         dev_priv = i915_mch_dev;
5934
5935         dev_priv->ips.max_delay = dev_priv->ips.fstart;
5936
5937         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5938                 ret = false;
5939
5940 out_unlock:
5941         spin_unlock_irq(&mchdev_lock);
5942
5943         return ret;
5944 }
5945 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5946
5947 /**
5948  * Tells the intel_ips driver that the i915 driver is now loaded, if
5949  * IPS got loaded first.
5950  *
5951  * This awkward dance is so that neither module has to depend on the
5952  * other in order for IPS to do the appropriate communication of
5953  * GPU turbo limits to i915.
5954  */
5955 static void
5956 ips_ping_for_i915_load(void)
5957 {
5958         void (*link)(void);
5959
5960         link = symbol_get(ips_link_to_i915_driver);
5961         if (link) {
5962                 link();
5963                 symbol_put(ips_link_to_i915_driver);
5964         }
5965 }
5966
5967 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5968 {
5969         /* We only register the i915 ips part with intel-ips once everything is
5970          * set up, to avoid intel-ips sneaking in and reading bogus values. */
5971         spin_lock_irq(&mchdev_lock);
5972         i915_mch_dev = dev_priv;
5973         spin_unlock_irq(&mchdev_lock);
5974
5975         ips_ping_for_i915_load();
5976 }
5977
5978 void intel_gpu_ips_teardown(void)
5979 {
5980         spin_lock_irq(&mchdev_lock);
5981         i915_mch_dev = NULL;
5982         spin_unlock_irq(&mchdev_lock);
5983 }
5984
5985 static void intel_init_emon(struct drm_device *dev)
5986 {
5987         struct drm_i915_private *dev_priv = dev->dev_private;
5988         u32 lcfuse;
5989         u8 pxw[16];
5990         int i;
5991
5992         /* Disable to program */
5993         I915_WRITE(ECR, 0);
5994         POSTING_READ(ECR);
5995
5996         /* Program energy weights for various events */
5997         I915_WRITE(SDEW, 0x15040d00);
5998         I915_WRITE(CSIEW0, 0x007f0000);
5999         I915_WRITE(CSIEW1, 0x1e220004);
6000         I915_WRITE(CSIEW2, 0x04000004);
6001
6002         for (i = 0; i < 5; i++)
6003                 I915_WRITE(PEW(i), 0);
6004         for (i = 0; i < 3; i++)
6005                 I915_WRITE(DEW(i), 0);
6006
6007         /* Program P-state weights to account for frequency power adjustment */
6008         for (i = 0; i < 16; i++) {
6009                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6010                 unsigned long freq = intel_pxfreq(pxvidfreq);
6011                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6012                         PXVFREQ_PX_SHIFT;
6013                 unsigned long val;
6014
6015                 val = vid * vid;
6016                 val *= (freq / 1000);
6017                 val *= 255;
6018                 val /= (127*127*900);
6019                 if (val > 0xff)
6020                         DRM_ERROR("bad pxval: %ld\n", val);
6021                 pxw[i] = val;
6022         }
6023         /* Render standby states get 0 weight */
6024         pxw[14] = 0;
6025         pxw[15] = 0;
6026
6027         for (i = 0; i < 4; i++) {
6028                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6029                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6030                 I915_WRITE(PXW(i), val);
6031         }
6032
6033         /* Adjust magic regs to magic values (more experimental results) */
6034         I915_WRITE(OGW0, 0);
6035         I915_WRITE(OGW1, 0);
6036         I915_WRITE(EG0, 0x00007f00);
6037         I915_WRITE(EG1, 0x0000000e);
6038         I915_WRITE(EG2, 0x000e0000);
6039         I915_WRITE(EG3, 0x68000300);
6040         I915_WRITE(EG4, 0x42000000);
6041         I915_WRITE(EG5, 0x00140031);
6042         I915_WRITE(EG6, 0);
6043         I915_WRITE(EG7, 0);
6044
6045         for (i = 0; i < 8; i++)
6046                 I915_WRITE(PXWL(i), 0);
6047
6048         /* Enable PMON + select events */
6049         I915_WRITE(ECR, 0x80000019);
6050
6051         lcfuse = I915_READ(LCFUSE02);
6052
6053         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6054 }
6055
6056 void intel_init_gt_powersave(struct drm_device *dev)
6057 {
6058         struct drm_i915_private *dev_priv = dev->dev_private;
6059
6060         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6061         /*
6062          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6063          * requirement.
6064          */
6065         if (!i915.enable_rc6) {
6066                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6067                 intel_runtime_pm_get(dev_priv);
6068         }
6069
6070         if (IS_CHERRYVIEW(dev))
6071                 cherryview_init_gt_powersave(dev);
6072         else if (IS_VALLEYVIEW(dev))
6073                 valleyview_init_gt_powersave(dev);
6074 }
6075
6076 void intel_cleanup_gt_powersave(struct drm_device *dev)
6077 {
6078         struct drm_i915_private *dev_priv = dev->dev_private;
6079
6080         if (IS_CHERRYVIEW(dev))
6081                 return;
6082         else if (IS_VALLEYVIEW(dev))
6083                 valleyview_cleanup_gt_powersave(dev);
6084
6085         if (!i915.enable_rc6)
6086                 intel_runtime_pm_put(dev_priv);
6087 }
6088
6089 static void gen6_suspend_rps(struct drm_device *dev)
6090 {
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092
6093         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6094
6095         gen6_disable_rps_interrupts(dev);
6096 }
6097
6098 /**
6099  * intel_suspend_gt_powersave - suspend PM work and helper threads
6100  * @dev: drm device
6101  *
6102  * We don't want to disable RC6 or other features here, we just want
6103  * to make sure any work we've queued has finished and won't bother
6104  * us while we're suspended.
6105  */
6106 void intel_suspend_gt_powersave(struct drm_device *dev)
6107 {
6108         struct drm_i915_private *dev_priv = dev->dev_private;
6109
6110         if (INTEL_INFO(dev)->gen < 6)
6111                 return;
6112
6113         gen6_suspend_rps(dev);
6114
6115         /* Force GPU to min freq during suspend */
6116         gen6_rps_idle(dev_priv);
6117 }
6118
6119 void intel_disable_gt_powersave(struct drm_device *dev)
6120 {
6121         struct drm_i915_private *dev_priv = dev->dev_private;
6122
6123         if (IS_IRONLAKE_M(dev)) {
6124                 ironlake_disable_drps(dev);
6125         } else if (INTEL_INFO(dev)->gen >= 6) {
6126                 intel_suspend_gt_powersave(dev);
6127
6128                 mutex_lock(&dev_priv->rps.hw_lock);
6129                 if (INTEL_INFO(dev)->gen >= 9)
6130                         gen9_disable_rps(dev);
6131                 else if (IS_CHERRYVIEW(dev))
6132                         cherryview_disable_rps(dev);
6133                 else if (IS_VALLEYVIEW(dev))
6134                         valleyview_disable_rps(dev);
6135                 else
6136                         gen6_disable_rps(dev);
6137
6138                 dev_priv->rps.enabled = false;
6139                 mutex_unlock(&dev_priv->rps.hw_lock);
6140         }
6141 }
6142
6143 static void intel_gen6_powersave_work(struct work_struct *work)
6144 {
6145         struct drm_i915_private *dev_priv =
6146                 container_of(work, struct drm_i915_private,
6147                              rps.delayed_resume_work.work);
6148         struct drm_device *dev = dev_priv->dev;
6149
6150         mutex_lock(&dev_priv->rps.hw_lock);
6151
6152         gen6_reset_rps_interrupts(dev);
6153
6154         if (IS_CHERRYVIEW(dev)) {
6155                 cherryview_enable_rps(dev);
6156         } else if (IS_VALLEYVIEW(dev)) {
6157                 valleyview_enable_rps(dev);
6158         } else if (INTEL_INFO(dev)->gen >= 9) {
6159                 gen9_enable_rc6(dev);
6160                 gen9_enable_rps(dev);
6161                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6162                         __gen6_update_ring_freq(dev);
6163         } else if (IS_BROADWELL(dev)) {
6164                 gen8_enable_rps(dev);
6165                 __gen6_update_ring_freq(dev);
6166         } else {
6167                 gen6_enable_rps(dev);
6168                 __gen6_update_ring_freq(dev);
6169         }
6170
6171         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6172         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6173
6174         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6175         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6176
6177         dev_priv->rps.enabled = true;
6178
6179         gen6_enable_rps_interrupts(dev);
6180
6181         mutex_unlock(&dev_priv->rps.hw_lock);
6182
6183         intel_runtime_pm_put(dev_priv);
6184 }
6185
6186 void intel_enable_gt_powersave(struct drm_device *dev)
6187 {
6188         struct drm_i915_private *dev_priv = dev->dev_private;
6189
6190         /* Powersaving is controlled by the host when inside a VM */
6191         if (intel_vgpu_active(dev))
6192                 return;
6193
6194         if (IS_IRONLAKE_M(dev)) {
6195                 mutex_lock(&dev->struct_mutex);
6196                 ironlake_enable_drps(dev);
6197                 intel_init_emon(dev);
6198                 mutex_unlock(&dev->struct_mutex);
6199         } else if (INTEL_INFO(dev)->gen >= 6) {
6200                 /*
6201                  * PCU communication is slow and this doesn't need to be
6202                  * done at any specific time, so do this out of our fast path
6203                  * to make resume and init faster.
6204                  *
6205                  * We depend on the HW RC6 power context save/restore
6206                  * mechanism when entering D3 through runtime PM suspend. So
6207                  * disable RPM until RPS/RC6 is properly setup. We can only
6208                  * get here via the driver load/system resume/runtime resume
6209                  * paths, so the _noresume version is enough (and in case of
6210                  * runtime resume it's necessary).
6211                  */
6212                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6213                                            round_jiffies_up_relative(HZ)))
6214                         intel_runtime_pm_get_noresume(dev_priv);
6215         }
6216 }
6217
6218 void intel_reset_gt_powersave(struct drm_device *dev)
6219 {
6220         struct drm_i915_private *dev_priv = dev->dev_private;
6221
6222         if (INTEL_INFO(dev)->gen < 6)
6223                 return;
6224
6225         gen6_suspend_rps(dev);
6226         dev_priv->rps.enabled = false;
6227 }
6228
6229 static void ibx_init_clock_gating(struct drm_device *dev)
6230 {
6231         struct drm_i915_private *dev_priv = dev->dev_private;
6232
6233         /*
6234          * On Ibex Peak and Cougar Point, we need to disable clock
6235          * gating for the panel power sequencer or it will fail to
6236          * start up when no ports are active.
6237          */
6238         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6239 }
6240
6241 static void g4x_disable_trickle_feed(struct drm_device *dev)
6242 {
6243         struct drm_i915_private *dev_priv = dev->dev_private;
6244         enum pipe pipe;
6245
6246         for_each_pipe(dev_priv, pipe) {
6247                 I915_WRITE(DSPCNTR(pipe),
6248                            I915_READ(DSPCNTR(pipe)) |
6249                            DISPPLANE_TRICKLE_FEED_DISABLE);
6250
6251                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6252                 POSTING_READ(DSPSURF(pipe));
6253         }
6254 }
6255
6256 static void ilk_init_lp_watermarks(struct drm_device *dev)
6257 {
6258         struct drm_i915_private *dev_priv = dev->dev_private;
6259
6260         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6261         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6262         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6263
6264         /*
6265          * Don't touch WM1S_LP_EN here.
6266          * Doing so could cause underruns.
6267          */
6268 }
6269
6270 static void ironlake_init_clock_gating(struct drm_device *dev)
6271 {
6272         struct drm_i915_private *dev_priv = dev->dev_private;
6273         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6274
6275         /*
6276          * Required for FBC
6277          * WaFbcDisableDpfcClockGating:ilk
6278          */
6279         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6280                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6281                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6282
6283         I915_WRITE(PCH_3DCGDIS0,
6284                    MARIUNIT_CLOCK_GATE_DISABLE |
6285                    SVSMUNIT_CLOCK_GATE_DISABLE);
6286         I915_WRITE(PCH_3DCGDIS1,
6287                    VFMUNIT_CLOCK_GATE_DISABLE);
6288
6289         /*
6290          * According to the spec the following bits should be set in
6291          * order to enable memory self-refresh
6292          * The bit 22/21 of 0x42004
6293          * The bit 5 of 0x42020
6294          * The bit 15 of 0x45000
6295          */
6296         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6297                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6298                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6299         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6300         I915_WRITE(DISP_ARB_CTL,
6301                    (I915_READ(DISP_ARB_CTL) |
6302                     DISP_FBC_WM_DIS));
6303
6304         ilk_init_lp_watermarks(dev);
6305
6306         /*
6307          * Based on the document from hardware guys the following bits
6308          * should be set unconditionally in order to enable FBC.
6309          * The bit 22 of 0x42000
6310          * The bit 22 of 0x42004
6311          * The bit 7,8,9 of 0x42020.
6312          */
6313         if (IS_IRONLAKE_M(dev)) {
6314                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6315                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6316                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6317                            ILK_FBCQ_DIS);
6318                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6319                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6320                            ILK_DPARB_GATE);
6321         }
6322
6323         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6324
6325         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6326                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6327                    ILK_ELPIN_409_SELECT);
6328         I915_WRITE(_3D_CHICKEN2,
6329                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6330                    _3D_CHICKEN2_WM_READ_PIPELINED);
6331
6332         /* WaDisableRenderCachePipelinedFlush:ilk */
6333         I915_WRITE(CACHE_MODE_0,
6334                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6335
6336         /* WaDisable_RenderCache_OperationalFlush:ilk */
6337         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6338
6339         g4x_disable_trickle_feed(dev);
6340
6341         ibx_init_clock_gating(dev);
6342 }
6343
6344 static void cpt_init_clock_gating(struct drm_device *dev)
6345 {
6346         struct drm_i915_private *dev_priv = dev->dev_private;
6347         int pipe;
6348         uint32_t val;
6349
6350         /*
6351          * On Ibex Peak and Cougar Point, we need to disable clock
6352          * gating for the panel power sequencer or it will fail to
6353          * start up when no ports are active.
6354          */
6355         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6356                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6357                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6358         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6359                    DPLS_EDP_PPS_FIX_DIS);
6360         /* The below fixes the weird display corruption, a few pixels shifted
6361          * downward, on (only) LVDS of some HP laptops with IVY.
6362          */
6363         for_each_pipe(dev_priv, pipe) {
6364                 val = I915_READ(TRANS_CHICKEN2(pipe));
6365                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6366                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6367                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6368                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6369                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6370                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6371                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6372                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6373         }
6374         /* WADP0ClockGatingDisable */
6375         for_each_pipe(dev_priv, pipe) {
6376                 I915_WRITE(TRANS_CHICKEN1(pipe),
6377                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6378         }
6379 }
6380
6381 static void gen6_check_mch_setup(struct drm_device *dev)
6382 {
6383         struct drm_i915_private *dev_priv = dev->dev_private;
6384         uint32_t tmp;
6385
6386         tmp = I915_READ(MCH_SSKPD);
6387         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6388                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6389                               tmp);
6390 }
6391
6392 static void gen6_init_clock_gating(struct drm_device *dev)
6393 {
6394         struct drm_i915_private *dev_priv = dev->dev_private;
6395         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6396
6397         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6398
6399         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6400                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6401                    ILK_ELPIN_409_SELECT);
6402
6403         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6404         I915_WRITE(_3D_CHICKEN,
6405                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6406
6407         /* WaDisable_RenderCache_OperationalFlush:snb */
6408         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6409
6410         /*
6411          * BSpec recoomends 8x4 when MSAA is used,
6412          * however in practice 16x4 seems fastest.
6413          *
6414          * Note that PS/WM thread counts depend on the WIZ hashing
6415          * disable bit, which we don't touch here, but it's good
6416          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6417          */
6418         I915_WRITE(GEN6_GT_MODE,
6419                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6420
6421         ilk_init_lp_watermarks(dev);
6422
6423         I915_WRITE(CACHE_MODE_0,
6424                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6425
6426         I915_WRITE(GEN6_UCGCTL1,
6427                    I915_READ(GEN6_UCGCTL1) |
6428                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6429                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6430
6431         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6432          * gating disable must be set.  Failure to set it results in
6433          * flickering pixels due to Z write ordering failures after
6434          * some amount of runtime in the Mesa "fire" demo, and Unigine
6435          * Sanctuary and Tropics, and apparently anything else with
6436          * alpha test or pixel discard.
6437          *
6438          * According to the spec, bit 11 (RCCUNIT) must also be set,
6439          * but we didn't debug actual testcases to find it out.
6440          *
6441          * WaDisableRCCUnitClockGating:snb
6442          * WaDisableRCPBUnitClockGating:snb
6443          */
6444         I915_WRITE(GEN6_UCGCTL2,
6445                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6446                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6447
6448         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6449         I915_WRITE(_3D_CHICKEN3,
6450                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6451
6452         /*
6453          * Bspec says:
6454          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6455          * 3DSTATE_SF number of SF output attributes is more than 16."
6456          */
6457         I915_WRITE(_3D_CHICKEN3,
6458                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6459
6460         /*
6461          * According to the spec the following bits should be
6462          * set in order to enable memory self-refresh and fbc:
6463          * The bit21 and bit22 of 0x42000
6464          * The bit21 and bit22 of 0x42004
6465          * The bit5 and bit7 of 0x42020
6466          * The bit14 of 0x70180
6467          * The bit14 of 0x71180
6468          *
6469          * WaFbcAsynchFlipDisableFbcQueue:snb
6470          */
6471         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6472                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6473                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6474         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6475                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6476                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6477         I915_WRITE(ILK_DSPCLK_GATE_D,
6478                    I915_READ(ILK_DSPCLK_GATE_D) |
6479                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6480                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6481
6482         g4x_disable_trickle_feed(dev);
6483
6484         cpt_init_clock_gating(dev);
6485
6486         gen6_check_mch_setup(dev);
6487 }
6488
6489 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6490 {
6491         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6492
6493         /*
6494          * WaVSThreadDispatchOverride:ivb,vlv
6495          *
6496          * This actually overrides the dispatch
6497          * mode for all thread types.
6498          */
6499         reg &= ~GEN7_FF_SCHED_MASK;
6500         reg |= GEN7_FF_TS_SCHED_HW;
6501         reg |= GEN7_FF_VS_SCHED_HW;
6502         reg |= GEN7_FF_DS_SCHED_HW;
6503
6504         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6505 }
6506
6507 static void lpt_init_clock_gating(struct drm_device *dev)
6508 {
6509         struct drm_i915_private *dev_priv = dev->dev_private;
6510
6511         /*
6512          * TODO: this bit should only be enabled when really needed, then
6513          * disabled when not needed anymore in order to save power.
6514          */
6515         if (HAS_PCH_LPT_LP(dev))
6516                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6517                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6518                            PCH_LP_PARTITION_LEVEL_DISABLE);
6519
6520         /* WADPOClockGatingDisable:hsw */
6521         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6522                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6523                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6524 }
6525
6526 static void lpt_suspend_hw(struct drm_device *dev)
6527 {
6528         struct drm_i915_private *dev_priv = dev->dev_private;
6529
6530         if (HAS_PCH_LPT_LP(dev)) {
6531                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6532
6533                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6534                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6535         }
6536 }
6537
6538 static void broadwell_init_clock_gating(struct drm_device *dev)
6539 {
6540         struct drm_i915_private *dev_priv = dev->dev_private;
6541         enum pipe pipe;
6542         uint32_t misccpctl;
6543
6544         ilk_init_lp_watermarks(dev);
6545
6546         /* WaSwitchSolVfFArbitrationPriority:bdw */
6547         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6548
6549         /* WaPsrDPAMaskVBlankInSRD:bdw */
6550         I915_WRITE(CHICKEN_PAR1_1,
6551                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6552
6553         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6554         for_each_pipe(dev_priv, pipe) {
6555                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6556                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6557                            BDW_DPRS_MASK_VBLANK_SRD);
6558         }
6559
6560         /* WaVSRefCountFullforceMissDisable:bdw */
6561         /* WaDSRefCountFullforceMissDisable:bdw */
6562         I915_WRITE(GEN7_FF_THREAD_MODE,
6563                    I915_READ(GEN7_FF_THREAD_MODE) &
6564                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6565
6566         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6567                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6568
6569         /* WaDisableSDEUnitClockGating:bdw */
6570         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6571                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6572
6573         /*
6574          * WaProgramL3SqcReg1Default:bdw
6575          * WaTempDisableDOPClkGating:bdw
6576          */
6577         misccpctl = I915_READ(GEN7_MISCCPCTL);
6578         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6579         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6580         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6581
6582         /*
6583          * WaGttCachingOffByDefault:bdw
6584          * GTT cache may not work with big pages, so if those
6585          * are ever enabled GTT cache may need to be disabled.
6586          */
6587         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6588
6589         lpt_init_clock_gating(dev);
6590 }
6591
6592 static void haswell_init_clock_gating(struct drm_device *dev)
6593 {
6594         struct drm_i915_private *dev_priv = dev->dev_private;
6595
6596         ilk_init_lp_watermarks(dev);
6597
6598         /* L3 caching of data atomics doesn't work -- disable it. */
6599         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6600         I915_WRITE(HSW_ROW_CHICKEN3,
6601                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6602
6603         /* This is required by WaCatErrorRejectionIssue:hsw */
6604         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6605                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6606                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6607
6608         /* WaVSRefCountFullforceMissDisable:hsw */
6609         I915_WRITE(GEN7_FF_THREAD_MODE,
6610                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6611
6612         /* WaDisable_RenderCache_OperationalFlush:hsw */
6613         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6614
6615         /* enable HiZ Raw Stall Optimization */
6616         I915_WRITE(CACHE_MODE_0_GEN7,
6617                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6618
6619         /* WaDisable4x2SubspanOptimization:hsw */
6620         I915_WRITE(CACHE_MODE_1,
6621                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6622
6623         /*
6624          * BSpec recommends 8x4 when MSAA is used,
6625          * however in practice 16x4 seems fastest.
6626          *
6627          * Note that PS/WM thread counts depend on the WIZ hashing
6628          * disable bit, which we don't touch here, but it's good
6629          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6630          */
6631         I915_WRITE(GEN7_GT_MODE,
6632                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6633
6634         /* WaSampleCChickenBitEnable:hsw */
6635         I915_WRITE(HALF_SLICE_CHICKEN3,
6636                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6637
6638         /* WaSwitchSolVfFArbitrationPriority:hsw */
6639         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6640
6641         /* WaRsPkgCStateDisplayPMReq:hsw */
6642         I915_WRITE(CHICKEN_PAR1_1,
6643                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6644
6645         lpt_init_clock_gating(dev);
6646 }
6647
6648 static void ivybridge_init_clock_gating(struct drm_device *dev)
6649 {
6650         struct drm_i915_private *dev_priv = dev->dev_private;
6651         uint32_t snpcr;
6652
6653         ilk_init_lp_watermarks(dev);
6654
6655         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6656
6657         /* WaDisableEarlyCull:ivb */
6658         I915_WRITE(_3D_CHICKEN3,
6659                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6660
6661         /* WaDisableBackToBackFlipFix:ivb */
6662         I915_WRITE(IVB_CHICKEN3,
6663                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6664                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6665
6666         /* WaDisablePSDDualDispatchEnable:ivb */
6667         if (IS_IVB_GT1(dev))
6668                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6669                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6670
6671         /* WaDisable_RenderCache_OperationalFlush:ivb */
6672         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6673
6674         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6675         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6676                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6677
6678         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6679         I915_WRITE(GEN7_L3CNTLREG1,
6680                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6681         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6682                    GEN7_WA_L3_CHICKEN_MODE);
6683         if (IS_IVB_GT1(dev))
6684                 I915_WRITE(GEN7_ROW_CHICKEN2,
6685                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6686         else {
6687                 /* must write both registers */
6688                 I915_WRITE(GEN7_ROW_CHICKEN2,
6689                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6690                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6691                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6692         }
6693
6694         /* WaForceL3Serialization:ivb */
6695         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6696                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6697
6698         /*
6699          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6700          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6701          */
6702         I915_WRITE(GEN6_UCGCTL2,
6703                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6704
6705         /* This is required by WaCatErrorRejectionIssue:ivb */
6706         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6707                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6708                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6709
6710         g4x_disable_trickle_feed(dev);
6711
6712         gen7_setup_fixed_func_scheduler(dev_priv);
6713
6714         if (0) { /* causes HiZ corruption on ivb:gt1 */
6715                 /* enable HiZ Raw Stall Optimization */
6716                 I915_WRITE(CACHE_MODE_0_GEN7,
6717                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6718         }
6719
6720         /* WaDisable4x2SubspanOptimization:ivb */
6721         I915_WRITE(CACHE_MODE_1,
6722                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6723
6724         /*
6725          * BSpec recommends 8x4 when MSAA is used,
6726          * however in practice 16x4 seems fastest.
6727          *
6728          * Note that PS/WM thread counts depend on the WIZ hashing
6729          * disable bit, which we don't touch here, but it's good
6730          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6731          */
6732         I915_WRITE(GEN7_GT_MODE,
6733                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6734
6735         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6736         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6737         snpcr |= GEN6_MBC_SNPCR_MED;
6738         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6739
6740         if (!HAS_PCH_NOP(dev))
6741                 cpt_init_clock_gating(dev);
6742
6743         gen6_check_mch_setup(dev);
6744 }
6745
6746 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6747 {
6748         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6749
6750         /*
6751          * Disable trickle feed and enable pnd deadline calculation
6752          */
6753         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6754         I915_WRITE(CBR1_VLV, 0);
6755 }
6756
6757 static void valleyview_init_clock_gating(struct drm_device *dev)
6758 {
6759         struct drm_i915_private *dev_priv = dev->dev_private;
6760
6761         vlv_init_display_clock_gating(dev_priv);
6762
6763         /* WaDisableEarlyCull:vlv */
6764         I915_WRITE(_3D_CHICKEN3,
6765                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6766
6767         /* WaDisableBackToBackFlipFix:vlv */
6768         I915_WRITE(IVB_CHICKEN3,
6769                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6770                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6771
6772         /* WaPsdDispatchEnable:vlv */
6773         /* WaDisablePSDDualDispatchEnable:vlv */
6774         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6775                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6776                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6777
6778         /* WaDisable_RenderCache_OperationalFlush:vlv */
6779         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6780
6781         /* WaForceL3Serialization:vlv */
6782         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6783                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6784
6785         /* WaDisableDopClockGating:vlv */
6786         I915_WRITE(GEN7_ROW_CHICKEN2,
6787                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6788
6789         /* This is required by WaCatErrorRejectionIssue:vlv */
6790         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6791                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6792                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6793
6794         gen7_setup_fixed_func_scheduler(dev_priv);
6795
6796         /*
6797          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6798          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6799          */
6800         I915_WRITE(GEN6_UCGCTL2,
6801                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6802
6803         /* WaDisableL3Bank2xClockGate:vlv
6804          * Disabling L3 clock gating- MMIO 940c[25] = 1
6805          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6806         I915_WRITE(GEN7_UCGCTL4,
6807                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6808
6809         /*
6810          * BSpec says this must be set, even though
6811          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6812          */
6813         I915_WRITE(CACHE_MODE_1,
6814                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6815
6816         /*
6817          * BSpec recommends 8x4 when MSAA is used,
6818          * however in practice 16x4 seems fastest.
6819          *
6820          * Note that PS/WM thread counts depend on the WIZ hashing
6821          * disable bit, which we don't touch here, but it's good
6822          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6823          */
6824         I915_WRITE(GEN7_GT_MODE,
6825                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6826
6827         /*
6828          * WaIncreaseL3CreditsForVLVB0:vlv
6829          * This is the hardware default actually.
6830          */
6831         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6832
6833         /*
6834          * WaDisableVLVClockGating_VBIIssue:vlv
6835          * Disable clock gating on th GCFG unit to prevent a delay
6836          * in the reporting of vblank events.
6837          */
6838         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6839 }
6840
6841 static void cherryview_init_clock_gating(struct drm_device *dev)
6842 {
6843         struct drm_i915_private *dev_priv = dev->dev_private;
6844
6845         vlv_init_display_clock_gating(dev_priv);
6846
6847         /* WaVSRefCountFullforceMissDisable:chv */
6848         /* WaDSRefCountFullforceMissDisable:chv */
6849         I915_WRITE(GEN7_FF_THREAD_MODE,
6850                    I915_READ(GEN7_FF_THREAD_MODE) &
6851                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6852
6853         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6854         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6855                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6856
6857         /* WaDisableCSUnitClockGating:chv */
6858         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6859                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6860
6861         /* WaDisableSDEUnitClockGating:chv */
6862         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6863                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6864
6865         /*
6866          * GTT cache may not work with big pages, so if those
6867          * are ever enabled GTT cache may need to be disabled.
6868          */
6869         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6870 }
6871
6872 static void g4x_init_clock_gating(struct drm_device *dev)
6873 {
6874         struct drm_i915_private *dev_priv = dev->dev_private;
6875         uint32_t dspclk_gate;
6876
6877         I915_WRITE(RENCLK_GATE_D1, 0);
6878         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6879                    GS_UNIT_CLOCK_GATE_DISABLE |
6880                    CL_UNIT_CLOCK_GATE_DISABLE);
6881         I915_WRITE(RAMCLK_GATE_D, 0);
6882         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6883                 OVRUNIT_CLOCK_GATE_DISABLE |
6884                 OVCUNIT_CLOCK_GATE_DISABLE;
6885         if (IS_GM45(dev))
6886                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6887         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6888
6889         /* WaDisableRenderCachePipelinedFlush */
6890         I915_WRITE(CACHE_MODE_0,
6891                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6892
6893         /* WaDisable_RenderCache_OperationalFlush:g4x */
6894         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6895
6896         g4x_disable_trickle_feed(dev);
6897 }
6898
6899 static void crestline_init_clock_gating(struct drm_device *dev)
6900 {
6901         struct drm_i915_private *dev_priv = dev->dev_private;
6902
6903         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6904         I915_WRITE(RENCLK_GATE_D2, 0);
6905         I915_WRITE(DSPCLK_GATE_D, 0);
6906         I915_WRITE(RAMCLK_GATE_D, 0);
6907         I915_WRITE16(DEUC, 0);
6908         I915_WRITE(MI_ARB_STATE,
6909                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6910
6911         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6912         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6913 }
6914
6915 static void broadwater_init_clock_gating(struct drm_device *dev)
6916 {
6917         struct drm_i915_private *dev_priv = dev->dev_private;
6918
6919         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6920                    I965_RCC_CLOCK_GATE_DISABLE |
6921                    I965_RCPB_CLOCK_GATE_DISABLE |
6922                    I965_ISC_CLOCK_GATE_DISABLE |
6923                    I965_FBC_CLOCK_GATE_DISABLE);
6924         I915_WRITE(RENCLK_GATE_D2, 0);
6925         I915_WRITE(MI_ARB_STATE,
6926                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6927
6928         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6929         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6930 }
6931
6932 static void gen3_init_clock_gating(struct drm_device *dev)
6933 {
6934         struct drm_i915_private *dev_priv = dev->dev_private;
6935         u32 dstate = I915_READ(D_STATE);
6936
6937         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6938                 DSTATE_DOT_CLOCK_GATING;
6939         I915_WRITE(D_STATE, dstate);
6940
6941         if (IS_PINEVIEW(dev))
6942                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6943
6944         /* IIR "flip pending" means done if this bit is set */
6945         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6946
6947         /* interrupts should cause a wake up from C3 */
6948         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6949
6950         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6951         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6952
6953         I915_WRITE(MI_ARB_STATE,
6954                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6955 }
6956
6957 static void i85x_init_clock_gating(struct drm_device *dev)
6958 {
6959         struct drm_i915_private *dev_priv = dev->dev_private;
6960
6961         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6962
6963         /* interrupts should cause a wake up from C3 */
6964         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6965                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6966
6967         I915_WRITE(MEM_MODE,
6968                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6969 }
6970
6971 static void i830_init_clock_gating(struct drm_device *dev)
6972 {
6973         struct drm_i915_private *dev_priv = dev->dev_private;
6974
6975         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6976
6977         I915_WRITE(MEM_MODE,
6978                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6979                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6980 }
6981
6982 void intel_init_clock_gating(struct drm_device *dev)
6983 {
6984         struct drm_i915_private *dev_priv = dev->dev_private;
6985
6986         if (dev_priv->display.init_clock_gating)
6987                 dev_priv->display.init_clock_gating(dev);
6988 }
6989
6990 void intel_suspend_hw(struct drm_device *dev)
6991 {
6992         if (HAS_PCH_LPT(dev))
6993                 lpt_suspend_hw(dev);
6994 }
6995
6996 /* Set up chip specific power management-related functions */
6997 void intel_init_pm(struct drm_device *dev)
6998 {
6999         struct drm_i915_private *dev_priv = dev->dev_private;
7000
7001         intel_fbc_init(dev_priv);
7002
7003         /* For cxsr */
7004         if (IS_PINEVIEW(dev))
7005                 i915_pineview_get_mem_freq(dev);
7006         else if (IS_GEN5(dev))
7007                 i915_ironlake_get_mem_freq(dev);
7008
7009         /* For FIFO watermark updates */
7010         if (INTEL_INFO(dev)->gen >= 9) {
7011                 skl_setup_wm_latency(dev);
7012
7013                 if (IS_BROXTON(dev))
7014                         dev_priv->display.init_clock_gating =
7015                                 bxt_init_clock_gating;
7016                 dev_priv->display.update_wm = skl_update_wm;
7017         } else if (HAS_PCH_SPLIT(dev)) {
7018                 ilk_setup_wm_latency(dev);
7019
7020                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7021                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7022                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7023                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7024                         dev_priv->display.update_wm = ilk_update_wm;
7025                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7026                         dev_priv->display.program_watermarks = ilk_program_watermarks;
7027                 } else {
7028                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7029                                       "Disable CxSR\n");
7030                 }
7031
7032                 if (IS_GEN5(dev))
7033                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7034                 else if (IS_GEN6(dev))
7035                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7036                 else if (IS_IVYBRIDGE(dev))
7037                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7038                 else if (IS_HASWELL(dev))
7039                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7040                 else if (INTEL_INFO(dev)->gen == 8)
7041                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7042         } else if (IS_CHERRYVIEW(dev)) {
7043                 vlv_setup_wm_latency(dev);
7044
7045                 dev_priv->display.update_wm = vlv_update_wm;
7046                 dev_priv->display.init_clock_gating =
7047                         cherryview_init_clock_gating;
7048         } else if (IS_VALLEYVIEW(dev)) {
7049                 vlv_setup_wm_latency(dev);
7050
7051                 dev_priv->display.update_wm = vlv_update_wm;
7052                 dev_priv->display.init_clock_gating =
7053                         valleyview_init_clock_gating;
7054         } else if (IS_PINEVIEW(dev)) {
7055                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7056                                             dev_priv->is_ddr3,
7057                                             dev_priv->fsb_freq,
7058                                             dev_priv->mem_freq)) {
7059                         DRM_INFO("failed to find known CxSR latency "
7060                                  "(found ddr%s fsb freq %d, mem freq %d), "
7061                                  "disabling CxSR\n",
7062                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7063                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7064                         /* Disable CxSR and never update its watermark again */
7065                         intel_set_memory_cxsr(dev_priv, false);
7066                         dev_priv->display.update_wm = NULL;
7067                 } else
7068                         dev_priv->display.update_wm = pineview_update_wm;
7069                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7070         } else if (IS_G4X(dev)) {
7071                 dev_priv->display.update_wm = g4x_update_wm;
7072                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7073         } else if (IS_GEN4(dev)) {
7074                 dev_priv->display.update_wm = i965_update_wm;
7075                 if (IS_CRESTLINE(dev))
7076                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7077                 else if (IS_BROADWATER(dev))
7078                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7079         } else if (IS_GEN3(dev)) {
7080                 dev_priv->display.update_wm = i9xx_update_wm;
7081                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7082                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7083         } else if (IS_GEN2(dev)) {
7084                 if (INTEL_INFO(dev)->num_pipes == 1) {
7085                         dev_priv->display.update_wm = i845_update_wm;
7086                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7087                 } else {
7088                         dev_priv->display.update_wm = i9xx_update_wm;
7089                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7090                 }
7091
7092                 if (IS_I85X(dev) || IS_I865G(dev))
7093                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7094                 else
7095                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7096         } else {
7097                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7098         }
7099 }
7100
7101 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7102 {
7103         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7104
7105         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7106                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7107                 return -EAGAIN;
7108         }
7109
7110         I915_WRITE(GEN6_PCODE_DATA, *val);
7111         I915_WRITE(GEN6_PCODE_DATA1, 0);
7112         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7113
7114         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7115                      500)) {
7116                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7117                 return -ETIMEDOUT;
7118         }
7119
7120         *val = I915_READ(GEN6_PCODE_DATA);
7121         I915_WRITE(GEN6_PCODE_DATA, 0);
7122
7123         return 0;
7124 }
7125
7126 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7127 {
7128         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7129
7130         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7131                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7132                 return -EAGAIN;
7133         }
7134
7135         I915_WRITE(GEN6_PCODE_DATA, val);
7136         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7137
7138         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7139                      500)) {
7140                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7141                 return -ETIMEDOUT;
7142         }
7143
7144         I915_WRITE(GEN6_PCODE_DATA, 0);
7145
7146         return 0;
7147 }
7148
7149 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7150 {
7151         switch (czclk_freq) {
7152         case 200:
7153                 return 10;
7154         case 267:
7155                 return 12;
7156         case 320:
7157         case 333:
7158                 return 16;
7159         case 400:
7160                 return 20;
7161         default:
7162                 return -1;
7163         }
7164 }
7165
7166 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7167 {
7168         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7169
7170         div = vlv_gpu_freq_div(czclk_freq);
7171         if (div < 0)
7172                 return div;
7173
7174         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7175 }
7176
7177 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7178 {
7179         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7180
7181         mul = vlv_gpu_freq_div(czclk_freq);
7182         if (mul < 0)
7183                 return mul;
7184
7185         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7186 }
7187
7188 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7189 {
7190         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7191
7192         div = vlv_gpu_freq_div(czclk_freq) / 2;
7193         if (div < 0)
7194                 return div;
7195
7196         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7197 }
7198
7199 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7200 {
7201         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7202
7203         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7204         if (mul < 0)
7205                 return mul;
7206
7207         /* CHV needs even values */
7208         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7209 }
7210
7211 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7212 {
7213         if (IS_GEN9(dev_priv->dev))
7214                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7215                                          GEN9_FREQ_SCALER);
7216         else if (IS_CHERRYVIEW(dev_priv->dev))
7217                 return chv_gpu_freq(dev_priv, val);
7218         else if (IS_VALLEYVIEW(dev_priv->dev))
7219                 return byt_gpu_freq(dev_priv, val);
7220         else
7221                 return val * GT_FREQUENCY_MULTIPLIER;
7222 }
7223
7224 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7225 {
7226         if (IS_GEN9(dev_priv->dev))
7227                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7228                                          GT_FREQUENCY_MULTIPLIER);
7229         else if (IS_CHERRYVIEW(dev_priv->dev))
7230                 return chv_freq_opcode(dev_priv, val);
7231         else if (IS_VALLEYVIEW(dev_priv->dev))
7232                 return byt_freq_opcode(dev_priv, val);
7233         else
7234                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7235 }
7236
7237 struct request_boost {
7238         struct work_struct work;
7239         struct drm_i915_gem_request *req;
7240 };
7241
7242 static void __intel_rps_boost_work(struct work_struct *work)
7243 {
7244         struct request_boost *boost = container_of(work, struct request_boost, work);
7245         struct drm_i915_gem_request *req = boost->req;
7246
7247         if (!i915_gem_request_completed(req, true))
7248                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7249                                req->emitted_jiffies);
7250
7251         i915_gem_request_unreference__unlocked(req);
7252         kfree(boost);
7253 }
7254
7255 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7256                                        struct drm_i915_gem_request *req)
7257 {
7258         struct request_boost *boost;
7259
7260         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7261                 return;
7262
7263         if (i915_gem_request_completed(req, true))
7264                 return;
7265
7266         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7267         if (boost == NULL)
7268                 return;
7269
7270         i915_gem_request_reference(req);
7271         boost->req = req;
7272
7273         INIT_WORK(&boost->work, __intel_rps_boost_work);
7274         queue_work(to_i915(dev)->wq, &boost->work);
7275 }
7276
7277 void intel_pm_setup(struct drm_device *dev)
7278 {
7279         struct drm_i915_private *dev_priv = dev->dev_private;
7280
7281         mutex_init(&dev_priv->rps.hw_lock);
7282         spin_lock_init(&dev_priv->rps.client_lock);
7283
7284         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7285                           intel_gen6_powersave_work);
7286         INIT_LIST_HEAD(&dev_priv->rps.clients);
7287         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7288         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7289
7290         dev_priv->pm.suspended = false;
7291         atomic_set(&dev_priv->pm.wakeref_count, 0);
7292         atomic_set(&dev_priv->pm.atomic_seq, 0);
7293 }