drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         I915_WRITE(GEN8_CONFIG0,
  66                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  67
  68         /* WaEnableChickenDCPR:skl,bxt,kbl,glk */
  69         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  70                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  71
  72         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  73         /* WaFbcWakeMemOn:skl,bxt,kbl,glk */
  74         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  75                    DISP_FBC_WM_DIS |
  76                    DISP_FBC_MEMORY_WAKE);
  77
  78         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  79         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  80                    ILK_DPFC_DISABLE_DUMMY0);
  81 }
  82
  83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
  84 {
  85         gen9_init_clock_gating(dev_priv);
  86
  87         /* WaDisableSDEUnitClockGating:bxt */
  88         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  89                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  90
  91         /*
  92          * FIXME:
  93          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  94          */
  95         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  96                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  97
  98         /*
  99          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 100          * to stay fully on.
 101          */
 102         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 103                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 104 }
 105
 106 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 107 {
 108         gen9_init_clock_gating(dev_priv);
 109
 110         /*
 111          * WaDisablePWMClockGating:glk
 112          * Backlight PWM may stop in the asserted state, causing backlight
 113          * to stay fully on.
 114          */
 115         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 116                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 117
 118         /* WaDDIIOTimeout:glk */
 119         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
 120                 u32 val = I915_READ(CHICKEN_MISC_2);
 121                 val &= ~(GLK_CL0_PWR_DOWN |
 122                          GLK_CL1_PWR_DOWN |
 123                          GLK_CL2_PWR_DOWN);
 124                 I915_WRITE(CHICKEN_MISC_2, val);
 125         }
 126
 127 }
 128
 129 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 130 {
 131         u32 tmp;
 132
 133         tmp = I915_READ(CLKCFG);
 134
 135         switch (tmp & CLKCFG_FSB_MASK) {
 136         case CLKCFG_FSB_533:
 137                 dev_priv->fsb_freq = 533; /* 133*4 */
 138                 break;
 139         case CLKCFG_FSB_800:
 140                 dev_priv->fsb_freq = 800; /* 200*4 */
 141                 break;
 142         case CLKCFG_FSB_667:
 143                 dev_priv->fsb_freq =  667; /* 167*4 */
 144                 break;
 145         case CLKCFG_FSB_400:
 146                 dev_priv->fsb_freq = 400; /* 100*4 */
 147                 break;
 148         }
 149
 150         switch (tmp & CLKCFG_MEM_MASK) {
 151         case CLKCFG_MEM_533:
 152                 dev_priv->mem_freq = 533;
 153                 break;
 154         case CLKCFG_MEM_667:
 155                 dev_priv->mem_freq = 667;
 156                 break;
 157         case CLKCFG_MEM_800:
 158                 dev_priv->mem_freq = 800;
 159                 break;
 160         }
 161
 162         /* detect pineview DDR3 setting */
 163         tmp = I915_READ(CSHRDDR3CTL);
 164         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 165 }
 166
 167 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 168 {
 169         u16 ddrpll, csipll;
 170
 171         ddrpll = I915_READ16(DDRMPLL1);
 172         csipll = I915_READ16(CSIPLL0);
 173
 174         switch (ddrpll & 0xff) {
 175         case 0xc:
 176                 dev_priv->mem_freq = 800;
 177                 break;
 178         case 0x10:
 179                 dev_priv->mem_freq = 1066;
 180                 break;
 181         case 0x14:
 182                 dev_priv->mem_freq = 1333;
 183                 break;
 184         case 0x18:
 185                 dev_priv->mem_freq = 1600;
 186                 break;
 187         default:
 188                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 189                                  ddrpll & 0xff);
 190                 dev_priv->mem_freq = 0;
 191                 break;
 192         }
 193
 194         dev_priv->ips.r_t = dev_priv->mem_freq;
 195
 196         switch (csipll & 0x3ff) {
 197         case 0x00c:
 198                 dev_priv->fsb_freq = 3200;
 199                 break;
 200         case 0x00e:
 201                 dev_priv->fsb_freq = 3733;
 202                 break;
 203         case 0x010:
 204                 dev_priv->fsb_freq = 4266;
 205                 break;
 206         case 0x012:
 207                 dev_priv->fsb_freq = 4800;
 208                 break;
 209         case 0x014:
 210                 dev_priv->fsb_freq = 5333;
 211                 break;
 212         case 0x016:
 213                 dev_priv->fsb_freq = 5866;
 214                 break;
 215         case 0x018:
 216                 dev_priv->fsb_freq = 6400;
 217                 break;
 218         default:
 219                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 220                                  csipll & 0x3ff);
 221                 dev_priv->fsb_freq = 0;
 222                 break;
 223         }
 224
 225         if (dev_priv->fsb_freq == 3200) {
 226                 dev_priv->ips.c_m = 0;
 227         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 228                 dev_priv->ips.c_m = 1;
 229         } else {
 230                 dev_priv->ips.c_m = 2;
 231         }
 232 }
 233
 234 static const struct cxsr_latency cxsr_latency_table[] = {
 235         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 236         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 237         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 238         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 239         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 240
 241         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 242         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 243         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 244         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 245         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 246
 247         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 248         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 249         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 250         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 251         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 252
 253         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 254         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 255         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 256         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 257         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 258
 259         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 260         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 261         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 262         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 263         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 264
 265         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 266         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 267         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 268         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 269         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 270 };
 271
 272 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 273                                                          bool is_ddr3,
 274                                                          int fsb,
 275                                                          int mem)
 276 {
 277         const struct cxsr_latency *latency;
 278         int i;
 279
 280         if (fsb == 0 || mem == 0)
 281                 return NULL;
 282
 283         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 284                 latency = &cxsr_latency_table[i];
 285                 if (is_desktop == latency->is_desktop &&
 286                     is_ddr3 == latency->is_ddr3 &&
 287                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 288                         return latency;
 289         }
 290
 291         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 292
 293         return NULL;
 294 }
 295
 296 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 297 {
 298         u32 val;
 299
 300         mutex_lock(&dev_priv->rps.hw_lock);
 301
 302         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 303         if (enable)
 304                 val &= ~FORCE_DDR_HIGH_FREQ;
 305         else
 306                 val |= FORCE_DDR_HIGH_FREQ;
 307         val &= ~FORCE_DDR_LOW_FREQ;
 308         val |= FORCE_DDR_FREQ_REQ_ACK;
 309         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 310
 311         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 312                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 313                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 314
 315         mutex_unlock(&dev_priv->rps.hw_lock);
 316 }
 317
 318 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 319 {
 320         u32 val;
 321
 322         mutex_lock(&dev_priv->rps.hw_lock);
 323
 324         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 325         if (enable)
 326                 val |= DSP_MAXFIFO_PM5_ENABLE;
 327         else
 328                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 329         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 330
 331         mutex_unlock(&dev_priv->rps.hw_lock);
 332 }
 333
 334 #define FW_WM(value, plane) \
 335         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 336
 337 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 338 {
 339         bool was_enabled;
 340         u32 val;
 341
 342         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 343                 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 344                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 345                 POSTING_READ(FW_BLC_SELF_VLV);
 346         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 347                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 348                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 349                 POSTING_READ(FW_BLC_SELF);
 350         } else if (IS_PINEVIEW(dev_priv)) {
 351                 val = I915_READ(DSPFW3);
 352                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 353                 if (enable)
 354                         val |= PINEVIEW_SELF_REFRESH_EN;
 355                 else
 356                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 357                 I915_WRITE(DSPFW3, val);
 358                 POSTING_READ(DSPFW3);
 359         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 360                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 361                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 362                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 363                 I915_WRITE(FW_BLC_SELF, val);
 364                 POSTING_READ(FW_BLC_SELF);
 365         } else if (IS_I915GM(dev_priv)) {
 366                 /*
 367                  * FIXME can't find a bit like this for 915G, and
 368                  * and yet it does have the related watermark in
 369                  * FW_BLC_SELF. What's going on?
 370                  */
 371                 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 372                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 373                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 374                 I915_WRITE(INSTPM, val);
 375                 POSTING_READ(INSTPM);
 376         } else {
 377                 return false;
 378         }
 379
 380         trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
 381
 382         DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
 383                       enableddisabled(enable),
 384                       enableddisabled(was_enabled));
 385
 386         return was_enabled;
 387 }
 388
 389 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 390 {
 391         bool ret;
 392
 393         mutex_lock(&dev_priv->wm.wm_mutex);
 394         ret = _intel_set_memory_cxsr(dev_priv, enable);
 395         dev_priv->wm.vlv.cxsr = enable;
 396         mutex_unlock(&dev_priv->wm.wm_mutex);
 397
 398         return ret;
 399 }
 400
 401 /*
 402  * Latency for FIFO fetches is dependent on several factors:
 403  *   - memory configuration (speed, channels)
 404  *   - chipset
 405  *   - current MCH state
 406  * It can be fairly high in some situations, so here we assume a fairly
 407  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 408  * set this value too high, the FIFO will fetch frequently to stay full)
 409  * and power consumption (set it too low to save power and we might see
 410  * FIFO underruns and display "flicker").
 411  *
 412  * A value of 5us seems to be a good balance; safe for very low end
 413  * platforms but not overly aggressive on lower latency configs.
 414  */
 415 static const int pessimal_latency_ns = 5000;
 416
 417 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 418         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 419
 420 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 421 {
 422         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 423         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 424         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 425         enum pipe pipe = crtc->pipe;
 426         int sprite0_start, sprite1_start;
 427
 428         switch (pipe) {
 429                 uint32_t dsparb, dsparb2, dsparb3;
 430         case PIPE_A:
 431                 dsparb = I915_READ(DSPARB);
 432                 dsparb2 = I915_READ(DSPARB2);
 433                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 434                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 435                 break;
 436         case PIPE_B:
 437                 dsparb = I915_READ(DSPARB);
 438                 dsparb2 = I915_READ(DSPARB2);
 439                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 440                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 441                 break;
 442         case PIPE_C:
 443                 dsparb2 = I915_READ(DSPARB2);
 444                 dsparb3 = I915_READ(DSPARB3);
 445                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 446                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 447                 break;
 448         default:
 449                 MISSING_CASE(pipe);
 450                 return;
 451         }
 452
 453         fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
 454         fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
 455         fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
 456         fifo_state->plane[PLANE_CURSOR] = 63;
 457 }
 458
 459 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 460 {
 461         uint32_t dsparb = I915_READ(DSPARB);
 462         int size;
 463
 464         size = dsparb & 0x7f;
 465         if (plane)
 466                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 467
 468         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 469                       plane ? "B" : "A", size);
 470
 471         return size;
 472 }
 473
 474 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 475 {
 476         uint32_t dsparb = I915_READ(DSPARB);
 477         int size;
 478
 479         size = dsparb & 0x1ff;
 480         if (plane)
 481                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 482         size >>= 1; /* Convert to cachelines */
 483
 484         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 485                       plane ? "B" : "A", size);
 486
 487         return size;
 488 }
 489
 490 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 491 {
 492         uint32_t dsparb = I915_READ(DSPARB);
 493         int size;
 494
 495         size = dsparb & 0x7f;
 496         size >>= 2; /* Convert to cachelines */
 497
 498         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 499                       plane ? "B" : "A",
 500                       size);
 501
 502         return size;
 503 }
 504
 505 /* Pineview has different values for various configs */
 506 static const struct intel_watermark_params pineview_display_wm = {
 507         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 508         .max_wm = PINEVIEW_MAX_WM,
 509         .default_wm = PINEVIEW_DFT_WM,
 510         .guard_size = PINEVIEW_GUARD_WM,
 511         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 512 };
 513 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 514         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 515         .max_wm = PINEVIEW_MAX_WM,
 516         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 517         .guard_size = PINEVIEW_GUARD_WM,
 518         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 519 };
 520 static const struct intel_watermark_params pineview_cursor_wm = {
 521         .fifo_size = PINEVIEW_CURSOR_FIFO,
 522         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 523         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 524         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 525         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 526 };
 527 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 528         .fifo_size = PINEVIEW_CURSOR_FIFO,
 529         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 530         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 531         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 532         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 533 };
 534 static const struct intel_watermark_params g4x_wm_info = {
 535         .fifo_size = G4X_FIFO_SIZE,
 536         .max_wm = G4X_MAX_WM,
 537         .default_wm = G4X_MAX_WM,
 538         .guard_size = 2,
 539         .cacheline_size = G4X_FIFO_LINE_SIZE,
 540 };
 541 static const struct intel_watermark_params g4x_cursor_wm_info = {
 542         .fifo_size = I965_CURSOR_FIFO,
 543         .max_wm = I965_CURSOR_MAX_WM,
 544         .default_wm = I965_CURSOR_DFT_WM,
 545         .guard_size = 2,
 546         .cacheline_size = G4X_FIFO_LINE_SIZE,
 547 };
 548 static const struct intel_watermark_params i965_cursor_wm_info = {
 549         .fifo_size = I965_CURSOR_FIFO,
 550         .max_wm = I965_CURSOR_MAX_WM,
 551         .default_wm = I965_CURSOR_DFT_WM,
 552         .guard_size = 2,
 553         .cacheline_size = I915_FIFO_LINE_SIZE,
 554 };
 555 static const struct intel_watermark_params i945_wm_info = {
 556         .fifo_size = I945_FIFO_SIZE,
 557         .max_wm = I915_MAX_WM,
 558         .default_wm = 1,
 559         .guard_size = 2,
 560         .cacheline_size = I915_FIFO_LINE_SIZE,
 561 };
 562 static const struct intel_watermark_params i915_wm_info = {
 563         .fifo_size = I915_FIFO_SIZE,
 564         .max_wm = I915_MAX_WM,
 565         .default_wm = 1,
 566         .guard_size = 2,
 567         .cacheline_size = I915_FIFO_LINE_SIZE,
 568 };
 569 static const struct intel_watermark_params i830_a_wm_info = {
 570         .fifo_size = I855GM_FIFO_SIZE,
 571         .max_wm = I915_MAX_WM,
 572         .default_wm = 1,
 573         .guard_size = 2,
 574         .cacheline_size = I830_FIFO_LINE_SIZE,
 575 };
 576 static const struct intel_watermark_params i830_bc_wm_info = {
 577         .fifo_size = I855GM_FIFO_SIZE,
 578         .max_wm = I915_MAX_WM/2,
 579         .default_wm = 1,
 580         .guard_size = 2,
 581         .cacheline_size = I830_FIFO_LINE_SIZE,
 582 };
 583 static const struct intel_watermark_params i845_wm_info = {
 584         .fifo_size = I830_FIFO_SIZE,
 585         .max_wm = I915_MAX_WM,
 586         .default_wm = 1,
 587         .guard_size = 2,
 588         .cacheline_size = I830_FIFO_LINE_SIZE,
 589 };
 590
 591 /**
 592  * intel_calculate_wm - calculate watermark level
 593  * @clock_in_khz: pixel clock
 594  * @wm: chip FIFO params
 595  * @cpp: bytes per pixel
 596  * @latency_ns: memory latency for the platform
 597  *
 598  * Calculate the watermark level (the level at which the display plane will
 599  * start fetching from memory again).  Each chip has a different display
 600  * FIFO size and allocation, so the caller needs to figure that out and pass
 601  * in the correct intel_watermark_params structure.
 602  *
 603  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 604  * on the pixel size.  When it reaches the watermark level, it'll start
 605  * fetching FIFO line sized based chunks from memory until the FIFO fills
 606  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 607  * will occur, and a display engine hang could result.
 608  */
 609 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 610                                         const struct intel_watermark_params *wm,
 611                                         int fifo_size, int cpp,
 612                                         unsigned long latency_ns)
 613 {
 614         long entries_required, wm_size;
 615
 616         /*
 617          * Note: we need to make sure we don't overflow for various clock &
 618          * latency values.
 619          * clocks go from a few thousand to several hundred thousand.
 620          * latency is usually a few thousand
 621          */
 622         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 623                 1000;
 624         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 625
 626         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 627
 628         wm_size = fifo_size - (entries_required + wm->guard_size);
 629
 630         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 631
 632         /* Don't promote wm_size to unsigned... */
 633         if (wm_size > (long)wm->max_wm)
 634                 wm_size = wm->max_wm;
 635         if (wm_size <= 0)
 636                 wm_size = wm->default_wm;
 637
 638         /*
 639          * Bspec seems to indicate that the value shouldn't be lower than
 640          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 641          * Lets go for 8 which is the burst size since certain platforms
 642          * already use a hardcoded 8 (which is what the spec says should be
 643          * done).
 644          */
 645         if (wm_size <= 8)
 646                 wm_size = 8;
 647
 648         return wm_size;
 649 }
 650
 651 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 652                                    const struct intel_plane_state *plane_state)
 653 {
 654         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 655
 656         /* FIXME check the 'enable' instead */
 657         if (!crtc_state->base.active)
 658                 return false;
 659
 660         /*
 661          * Treat cursor with fb as always visible since cursor updates
 662          * can happen faster than the vrefresh rate, and the current
 663          * watermark code doesn't handle that correctly. Cursor updates
 664          * which set/clear the fb or change the cursor size are going
 665          * to get throttled by intel_legacy_cursor_update() to work
 666          * around this problem with the watermark code.
 667          */
 668         if (plane->id == PLANE_CURSOR)
 669                 return plane_state->base.fb != NULL;
 670         else
 671                 return plane_state->base.visible;
 672 }
 673
 674 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 675 {
 676         struct intel_crtc *crtc, *enabled = NULL;
 677
 678         for_each_intel_crtc(&dev_priv->drm, crtc) {
 679                 if (intel_crtc_active(crtc)) {
 680                         if (enabled)
 681                                 return NULL;
 682                         enabled = crtc;
 683                 }
 684         }
 685
 686         return enabled;
 687 }
 688
 689 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 690 {
 691         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 692         struct intel_crtc *crtc;
 693         const struct cxsr_latency *latency;
 694         u32 reg;
 695         unsigned long wm;
 696
 697         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 698                                          dev_priv->is_ddr3,
 699                                          dev_priv->fsb_freq,
 700                                          dev_priv->mem_freq);
 701         if (!latency) {
 702                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 703                 intel_set_memory_cxsr(dev_priv, false);
 704                 return;
 705         }
 706
 707         crtc = single_enabled_crtc(dev_priv);
 708         if (crtc) {
 709                 const struct drm_display_mode *adjusted_mode =
 710                         &crtc->config->base.adjusted_mode;
 711                 const struct drm_framebuffer *fb =
 712                         crtc->base.primary->state->fb;
 713                 int cpp = fb->format->cpp[0];
 714                 int clock = adjusted_mode->crtc_clock;
 715
 716                 /* Display SR */
 717                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 718                                         pineview_display_wm.fifo_size,
 719                                         cpp, latency->display_sr);
 720                 reg = I915_READ(DSPFW1);
 721                 reg &= ~DSPFW_SR_MASK;
 722                 reg |= FW_WM(wm, SR);
 723                 I915_WRITE(DSPFW1, reg);
 724                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 725
 726                 /* cursor SR */
 727                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 728                                         pineview_display_wm.fifo_size,
 729                                         cpp, latency->cursor_sr);
 730                 reg = I915_READ(DSPFW3);
 731                 reg &= ~DSPFW_CURSOR_SR_MASK;
 732                 reg |= FW_WM(wm, CURSOR_SR);
 733                 I915_WRITE(DSPFW3, reg);
 734
 735                 /* Display HPLL off SR */
 736                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 737                                         pineview_display_hplloff_wm.fifo_size,
 738                                         cpp, latency->display_hpll_disable);
 739                 reg = I915_READ(DSPFW3);
 740                 reg &= ~DSPFW_HPLL_SR_MASK;
 741                 reg |= FW_WM(wm, HPLL_SR);
 742                 I915_WRITE(DSPFW3, reg);
 743
 744                 /* cursor HPLL off SR */
 745                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 746                                         pineview_display_hplloff_wm.fifo_size,
 747                                         cpp, latency->cursor_hpll_disable);
 748                 reg = I915_READ(DSPFW3);
 749                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 750                 reg |= FW_WM(wm, HPLL_CURSOR);
 751                 I915_WRITE(DSPFW3, reg);
 752                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 753
 754                 intel_set_memory_cxsr(dev_priv, true);
 755         } else {
 756                 intel_set_memory_cxsr(dev_priv, false);
 757         }
 758 }
 759
 760 static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
 761                             int plane,
 762                             const struct intel_watermark_params *display,
 763                             int display_latency_ns,
 764                             const struct intel_watermark_params *cursor,
 765                             int cursor_latency_ns,
 766                             int *plane_wm,
 767                             int *cursor_wm)
 768 {
 769         struct intel_crtc *crtc;
 770         const struct drm_display_mode *adjusted_mode;
 771         const struct drm_framebuffer *fb;
 772         int htotal, hdisplay, clock, cpp;
 773         int line_time_us, line_count;
 774         int entries, tlb_miss;
 775
 776         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 777         if (!intel_crtc_active(crtc)) {
 778                 *cursor_wm = cursor->guard_size;
 779                 *plane_wm = display->guard_size;
 780                 return false;
 781         }
 782
 783         adjusted_mode = &crtc->config->base.adjusted_mode;
 784         fb = crtc->base.primary->state->fb;
 785         clock = adjusted_mode->crtc_clock;
 786         htotal = adjusted_mode->crtc_htotal;
 787         hdisplay = crtc->config->pipe_src_w;
 788         cpp = fb->format->cpp[0];
 789
 790         /* Use the small buffer method to calculate plane watermark */
 791         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 792         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 793         if (tlb_miss > 0)
 794                 entries += tlb_miss;
 795         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 796         *plane_wm = entries + display->guard_size;
 797         if (*plane_wm > (int)display->max_wm)
 798                 *plane_wm = display->max_wm;
 799
 800         /* Use the large buffer method to calculate cursor watermark */
 801         line_time_us = max(htotal * 1000 / clock, 1);
 802         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 803         entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
 804         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 805         if (tlb_miss > 0)
 806                 entries += tlb_miss;
 807         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 808         *cursor_wm = entries + cursor->guard_size;
 809         if (*cursor_wm > (int)cursor->max_wm)
 810                 *cursor_wm = (int)cursor->max_wm;
 811
 812         return true;
 813 }
 814
 815 /*
 816  * Check the wm result.
 817  *
 818  * If any calculated watermark values is larger than the maximum value that
 819  * can be programmed into the associated watermark register, that watermark
 820  * must be disabled.
 821  */
 822 static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
 823                            int display_wm, int cursor_wm,
 824                            const struct intel_watermark_params *display,
 825                            const struct intel_watermark_params *cursor)
 826 {
 827         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 828                       display_wm, cursor_wm);
 829
 830         if (display_wm > display->max_wm) {
 831                 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
 832                               display_wm, display->max_wm);
 833                 return false;
 834         }
 835
 836         if (cursor_wm > cursor->max_wm) {
 837                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
 838                               cursor_wm, cursor->max_wm);
 839                 return false;
 840         }
 841
 842         if (!(display_wm || cursor_wm)) {
 843                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 844                 return false;
 845         }
 846
 847         return true;
 848 }
 849
 850 static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
 851                              int plane,
 852                              int latency_ns,
 853                              const struct intel_watermark_params *display,
 854                              const struct intel_watermark_params *cursor,
 855                              int *display_wm, int *cursor_wm)
 856 {
 857         struct intel_crtc *crtc;
 858         const struct drm_display_mode *adjusted_mode;
 859         const struct drm_framebuffer *fb;
 860         int hdisplay, htotal, cpp, clock;
 861         unsigned long line_time_us;
 862         int line_count, line_size;
 863         int small, large;
 864         int entries;
 865
 866         if (!latency_ns) {
 867                 *display_wm = *cursor_wm = 0;
 868                 return false;
 869         }
 870
 871         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 872         adjusted_mode = &crtc->config->base.adjusted_mode;
 873         fb = crtc->base.primary->state->fb;
 874         clock = adjusted_mode->crtc_clock;
 875         htotal = adjusted_mode->crtc_htotal;
 876         hdisplay = crtc->config->pipe_src_w;
 877         cpp = fb->format->cpp[0];
 878
 879         line_time_us = max(htotal * 1000 / clock, 1);
 880         line_count = (latency_ns / line_time_us + 1000) / 1000;
 881         line_size = hdisplay * cpp;
 882
 883         /* Use the minimum of the small and large buffer method for primary */
 884         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 885         large = line_count * line_size;
 886
 887         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 888         *display_wm = entries + display->guard_size;
 889
 890         /* calculate the self-refresh watermark for display cursor */
 891         entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
 892         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 893         *cursor_wm = entries + cursor->guard_size;
 894
 895         return g4x_check_srwm(dev_priv,
 896                               *display_wm, *cursor_wm,
 897                               display, cursor);
 898 }
 899
 900 #define FW_WM_VLV(value, plane) \
 901         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 902
 903 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 904                                 const struct vlv_wm_values *wm)
 905 {
 906         enum pipe pipe;
 907
 908         for_each_pipe(dev_priv, pipe) {
 909                 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 910
 911                 I915_WRITE(VLV_DDL(pipe),
 912                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
 913                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
 914                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
 915                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
 916         }
 917
 918         /*
 919          * Zero the (unused) WM1 watermarks, and also clear all the
 920          * high order bits so that there are no out of bounds values
 921          * present in the registers during the reprogramming.
 922          */
 923         I915_WRITE(DSPHOWM, 0);
 924         I915_WRITE(DSPHOWM1, 0);
 925         I915_WRITE(DSPFW4, 0);
 926         I915_WRITE(DSPFW5, 0);
 927         I915_WRITE(DSPFW6, 0);
 928
 929         I915_WRITE(DSPFW1,
 930                    FW_WM(wm->sr.plane, SR) |
 931                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 932                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 933                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 934         I915_WRITE(DSPFW2,
 935                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
 936                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 937                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 938         I915_WRITE(DSPFW3,
 939                    FW_WM(wm->sr.cursor, CURSOR_SR));
 940
 941         if (IS_CHERRYVIEW(dev_priv)) {
 942                 I915_WRITE(DSPFW7_CHV,
 943                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
 944                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
 945                 I915_WRITE(DSPFW8_CHV,
 946                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
 947                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
 948                 I915_WRITE(DSPFW9_CHV,
 949                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
 950                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
 951                 I915_WRITE(DSPHOWM,
 952                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 953                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
 954                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
 955                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
 956                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
 957                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
 958                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
 959                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
 960                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
 961                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
 962         } else {
 963                 I915_WRITE(DSPFW7,
 964                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
 965                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
 966                 I915_WRITE(DSPHOWM,
 967                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 968                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
 969                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
 970                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
 971                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
 972                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
 973                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
 974         }
 975
 976         POSTING_READ(DSPFW1);
 977 }
 978
 979 #undef FW_WM_VLV
 980
 981 /* latency must be in 0.1us units. */
 982 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 983                                    unsigned int pipe_htotal,
 984                                    unsigned int horiz_pixels,
 985                                    unsigned int cpp,
 986                                    unsigned int latency)
 987 {
 988         unsigned int ret;
 989
 990         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 991         ret = (ret + 1) * horiz_pixels * cpp;
 992         ret = DIV_ROUND_UP(ret, 64);
 993
 994         return ret;
 995 }
 996
 997 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
 998 {
 999         /* all latencies in usec */
1000         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1001
1002         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1003
1004         if (IS_CHERRYVIEW(dev_priv)) {
1005                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1006                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1007
1008                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1009         }
1010 }
1011
1012 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1013                                      const struct intel_plane_state *plane_state,
1014                                      int level)
1015 {
1016         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1017         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1018         const struct drm_display_mode *adjusted_mode =
1019                 &crtc_state->base.adjusted_mode;
1020         int clock, htotal, cpp, width, wm;
1021
1022         if (dev_priv->wm.pri_latency[level] == 0)
1023                 return USHRT_MAX;
1024
1025         if (!intel_wm_plane_visible(crtc_state, plane_state))
1026                 return 0;
1027
1028         cpp = plane_state->base.fb->format->cpp[0];
1029         clock = adjusted_mode->crtc_clock;
1030         htotal = adjusted_mode->crtc_htotal;
1031         width = crtc_state->pipe_src_w;
1032         if (WARN_ON(htotal == 0))
1033                 htotal = 1;
1034
1035         if (plane->id == PLANE_CURSOR) {
1036                 /*
1037                  * FIXME the formula gives values that are
1038                  * too big for the cursor FIFO, and hence we
1039                  * would never be able to use cursors. For
1040                  * now just hardcode the watermark.
1041                  */
1042                 wm = 63;
1043         } else {
1044                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1045                                     dev_priv->wm.pri_latency[level] * 10);
1046         }
1047
1048         return min_t(int, wm, USHRT_MAX);
1049 }
1050
1051 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1052 {
1053         return (active_planes & (BIT(PLANE_SPRITE0) |
1054                                  BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1055 }
1056
1057 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1058 {
1059         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1060         const struct vlv_pipe_wm *raw =
1061                 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1062         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1063         unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1064         int num_active_planes = hweight32(active_planes);
1065         const int fifo_size = 511;
1066         int fifo_extra, fifo_left = fifo_size;
1067         int sprite0_fifo_extra = 0;
1068         unsigned int total_rate;
1069         enum plane_id plane_id;
1070
1071         /*
1072          * When enabling sprite0 after sprite1 has already been enabled
1073          * we tend to get an underrun unless sprite0 already has some
1074          * FIFO space allcoated. Hence we always allocate at least one
1075          * cacheline for sprite0 whenever sprite1 is enabled.
1076          *
1077          * All other plane enable sequences appear immune to this problem.
1078          */
1079         if (vlv_need_sprite0_fifo_workaround(active_planes))
1080                 sprite0_fifo_extra = 1;
1081
1082         total_rate = raw->plane[PLANE_PRIMARY] +
1083                 raw->plane[PLANE_SPRITE0] +
1084                 raw->plane[PLANE_SPRITE1] +
1085                 sprite0_fifo_extra;
1086
1087         if (total_rate > fifo_size)
1088                 return -EINVAL;
1089
1090         if (total_rate == 0)
1091                 total_rate = 1;
1092
1093         for_each_plane_id_on_crtc(crtc, plane_id) {
1094                 unsigned int rate;
1095
1096                 if ((active_planes & BIT(plane_id)) == 0) {
1097                         fifo_state->plane[plane_id] = 0;
1098                         continue;
1099                 }
1100
1101                 rate = raw->plane[plane_id];
1102                 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1103                 fifo_left -= fifo_state->plane[plane_id];
1104         }
1105
1106         fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1107         fifo_left -= sprite0_fifo_extra;
1108
1109         fifo_state->plane[PLANE_CURSOR] = 63;
1110
1111         fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1112
1113         /* spread the remainder evenly */
1114         for_each_plane_id_on_crtc(crtc, plane_id) {
1115                 int plane_extra;
1116
1117                 if (fifo_left == 0)
1118                         break;
1119
1120                 if ((active_planes & BIT(plane_id)) == 0)
1121                         continue;
1122
1123                 plane_extra = min(fifo_extra, fifo_left);
1124                 fifo_state->plane[plane_id] += plane_extra;
1125                 fifo_left -= plane_extra;
1126         }
1127
1128         WARN_ON(active_planes != 0 && fifo_left != 0);
1129
1130         /* give it all to the first plane if none are active */
1131         if (active_planes == 0) {
1132                 WARN_ON(fifo_left != fifo_size);
1133                 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1134         }
1135
1136         return 0;
1137 }
1138
1139 static int vlv_num_wm_levels(struct drm_i915_private *dev_priv)
1140 {
1141         return dev_priv->wm.max_level + 1;
1142 }
1143
1144 /* mark all levels starting from 'level' as invalid */
1145 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1146                                struct vlv_wm_state *wm_state, int level)
1147 {
1148         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1149
1150         for (; level < vlv_num_wm_levels(dev_priv); level++) {
1151                 enum plane_id plane_id;
1152
1153                 for_each_plane_id_on_crtc(crtc, plane_id)
1154                         wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1155
1156                 wm_state->sr[level].cursor = USHRT_MAX;
1157                 wm_state->sr[level].plane = USHRT_MAX;
1158         }
1159 }
1160
1161 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1162 {
1163         if (wm > fifo_size)
1164                 return USHRT_MAX;
1165         else
1166                 return fifo_size - wm;
1167 }
1168
1169 /*
1170  * Starting from 'level' set all higher
1171  * levels to 'value' in the "raw" watermarks.
1172  */
1173 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1174                                  int level, enum plane_id plane_id, u16 value)
1175 {
1176         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1177         int num_levels = vlv_num_wm_levels(dev_priv);
1178         bool dirty = false;
1179
1180         for (; level < num_levels; level++) {
1181                 struct vlv_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1182
1183                 dirty |= raw->plane[plane_id] != value;
1184                 raw->plane[plane_id] = value;
1185         }
1186
1187         return dirty;
1188 }
1189
1190 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1191                                      const struct intel_plane_state *plane_state)
1192 {
1193         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1194         enum plane_id plane_id = plane->id;
1195         int num_levels = vlv_num_wm_levels(to_i915(plane->base.dev));
1196         int level;
1197         bool dirty = false;
1198
1199         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1200                 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1201                 goto out;
1202         }
1203
1204         for (level = 0; level < num_levels; level++) {
1205                 struct vlv_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1206                 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1207                 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1208
1209                 if (wm > max_wm)
1210                         break;
1211
1212                 dirty |= raw->plane[plane_id] != wm;
1213                 raw->plane[plane_id] = wm;
1214         }
1215
1216         /* mark all higher levels as invalid */
1217         dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1218
1219 out:
1220         if (dirty)
1221                 DRM_DEBUG_KMS("%s wms: [0]=%d,[1]=%d,[2]=%d\n",
1222                               plane->base.name,
1223                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1224                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1225                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1226
1227         return dirty;
1228 }
1229
1230 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1231                                       enum plane_id plane_id, int level)
1232 {
1233         const struct vlv_pipe_wm *raw =
1234                 &crtc_state->wm.vlv.raw[level];
1235         const struct vlv_fifo_state *fifo_state =
1236                 &crtc_state->wm.vlv.fifo_state;
1237
1238         return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1239 }
1240
1241 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1242 {
1243         return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1244                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1245                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1246                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1247 }
1248
1249 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1250 {
1251         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1252         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1253         struct intel_atomic_state *state =
1254                 to_intel_atomic_state(crtc_state->base.state);
1255         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1256         const struct vlv_fifo_state *fifo_state =
1257                 &crtc_state->wm.vlv.fifo_state;
1258         int num_active_planes = hweight32(crtc_state->active_planes &
1259                                           ~BIT(PLANE_CURSOR));
1260         bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
1261         struct intel_plane_state *plane_state;
1262         struct intel_plane *plane;
1263         enum plane_id plane_id;
1264         int level, ret, i;
1265         unsigned int dirty = 0;
1266
1267         for_each_intel_plane_in_state(state, plane, plane_state, i) {
1268                 const struct intel_plane_state *old_plane_state =
1269                         to_intel_plane_state(plane->base.state);
1270
1271                 if (plane_state->base.crtc != &crtc->base &&
1272                     old_plane_state->base.crtc != &crtc->base)
1273                         continue;
1274
1275                 if (vlv_raw_plane_wm_compute(crtc_state, plane_state))
1276                         dirty |= BIT(plane->id);
1277         }
1278
1279         /*
1280          * DSPARB registers may have been reset due to the
1281          * power well being turned off. Make sure we restore
1282          * them to a consistent state even if no primary/sprite
1283          * planes are initially active.
1284          */
1285         if (needs_modeset)
1286                 crtc_state->fifo_changed = true;
1287
1288         if (!dirty)
1289                 return 0;
1290
1291         /* cursor changes don't warrant a FIFO recompute */
1292         if (dirty & ~BIT(PLANE_CURSOR)) {
1293                 const struct intel_crtc_state *old_crtc_state =
1294                         to_intel_crtc_state(crtc->base.state);
1295                 const struct vlv_fifo_state *old_fifo_state =
1296                         &old_crtc_state->wm.vlv.fifo_state;
1297
1298                 ret = vlv_compute_fifo(crtc_state);
1299                 if (ret)
1300                         return ret;
1301
1302                 if (needs_modeset ||
1303                     memcmp(old_fifo_state, fifo_state,
1304                            sizeof(*fifo_state)) != 0)
1305                         crtc_state->fifo_changed = true;
1306         }
1307
1308         /* initially allow all levels */
1309         wm_state->num_levels = vlv_num_wm_levels(dev_priv);
1310         /*
1311          * Note that enabling cxsr with no primary/sprite planes
1312          * enabled can wedge the pipe. Hence we only allow cxsr
1313          * with exactly one enabled primary/sprite plane.
1314          */
1315         wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1316
1317         for (level = 0; level < wm_state->num_levels; level++) {
1318                 const struct vlv_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1319                 const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1320
1321                 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1322                         break;
1323
1324                 for_each_plane_id_on_crtc(crtc, plane_id) {
1325                         wm_state->wm[level].plane[plane_id] =
1326                                 vlv_invert_wm_value(raw->plane[plane_id],
1327                                                     fifo_state->plane[plane_id]);
1328                 }
1329
1330                 wm_state->sr[level].plane =
1331                         vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1332                                                  raw->plane[PLANE_SPRITE0],
1333                                                  raw->plane[PLANE_SPRITE1]),
1334                                             sr_fifo_size);
1335
1336                 wm_state->sr[level].cursor =
1337                         vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1338                                             63);
1339         }
1340
1341         if (level == 0)
1342                 return -EINVAL;
1343
1344         /* limit to only levels we can actually handle */
1345         wm_state->num_levels = level;
1346
1347         /* invalidate the higher levels */
1348         vlv_invalidate_wms(crtc, wm_state, level);
1349
1350         return 0;
1351 }
1352
1353 #define VLV_FIFO(plane, value) \
1354         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1355
1356 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1357                                    struct intel_crtc_state *crtc_state)
1358 {
1359         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1360         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1361         const struct vlv_fifo_state *fifo_state =
1362                 &crtc_state->wm.vlv.fifo_state;
1363         int sprite0_start, sprite1_start, fifo_size;
1364
1365         if (!crtc_state->fifo_changed)
1366                 return;
1367
1368         sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1369         sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1370         fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
1371
1372         WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63);
1373         WARN_ON(fifo_size != 511);
1374
1375         trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
1376
1377         /*
1378          * uncore.lock serves a double purpose here. It allows us to
1379          * use the less expensive I915_{READ,WRITE}_FW() functions, and
1380          * it protects the DSPARB registers from getting clobbered by
1381          * parallel updates from multiple pipes.
1382          *
1383          * intel_pipe_update_start() has already disabled interrupts
1384          * for us, so a plain spin_lock() is sufficient here.
1385          */
1386         spin_lock(&dev_priv->uncore.lock);
1387
1388         switch (crtc->pipe) {
1389                 uint32_t dsparb, dsparb2, dsparb3;
1390         case PIPE_A:
1391                 dsparb = I915_READ_FW(DSPARB);
1392                 dsparb2 = I915_READ_FW(DSPARB2);
1393
1394                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1395                             VLV_FIFO(SPRITEB, 0xff));
1396                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1397                            VLV_FIFO(SPRITEB, sprite1_start));
1398
1399                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1400                              VLV_FIFO(SPRITEB_HI, 0x1));
1401                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1402                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1403
1404                 I915_WRITE_FW(DSPARB, dsparb);
1405                 I915_WRITE_FW(DSPARB2, dsparb2);
1406                 break;
1407         case PIPE_B:
1408                 dsparb = I915_READ_FW(DSPARB);
1409                 dsparb2 = I915_READ_FW(DSPARB2);
1410
1411                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1412                             VLV_FIFO(SPRITED, 0xff));
1413                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1414                            VLV_FIFO(SPRITED, sprite1_start));
1415
1416                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1417                              VLV_FIFO(SPRITED_HI, 0xff));
1418                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1419                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1420
1421                 I915_WRITE_FW(DSPARB, dsparb);
1422                 I915_WRITE_FW(DSPARB2, dsparb2);
1423                 break;
1424         case PIPE_C:
1425                 dsparb3 = I915_READ_FW(DSPARB3);
1426                 dsparb2 = I915_READ_FW(DSPARB2);
1427
1428                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1429                              VLV_FIFO(SPRITEF, 0xff));
1430                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1431                             VLV_FIFO(SPRITEF, sprite1_start));
1432
1433                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1434                              VLV_FIFO(SPRITEF_HI, 0xff));
1435                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1436                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1437
1438                 I915_WRITE_FW(DSPARB3, dsparb3);
1439                 I915_WRITE_FW(DSPARB2, dsparb2);
1440                 break;
1441         default:
1442                 break;
1443         }
1444
1445         POSTING_READ_FW(DSPARB);
1446
1447         spin_unlock(&dev_priv->uncore.lock);
1448 }
1449
1450 #undef VLV_FIFO
1451
1452 static int vlv_compute_intermediate_wm(struct drm_device *dev,
1453                                        struct intel_crtc *crtc,
1454                                        struct intel_crtc_state *crtc_state)
1455 {
1456         struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate;
1457         const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal;
1458         const struct vlv_wm_state *active = &crtc->wm.active.vlv;
1459         int level;
1460
1461         intermediate->num_levels = min(optimal->num_levels, active->num_levels);
1462         intermediate->cxsr = optimal->cxsr && active->cxsr &&
1463                 !crtc_state->disable_cxsr;
1464
1465         for (level = 0; level < intermediate->num_levels; level++) {
1466                 enum plane_id plane_id;
1467
1468                 for_each_plane_id_on_crtc(crtc, plane_id) {
1469                         intermediate->wm[level].plane[plane_id] =
1470                                 min(optimal->wm[level].plane[plane_id],
1471                                     active->wm[level].plane[plane_id]);
1472                 }
1473
1474                 intermediate->sr[level].plane = min(optimal->sr[level].plane,
1475                                                     active->sr[level].plane);
1476                 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
1477                                                      active->sr[level].cursor);
1478         }
1479
1480         vlv_invalidate_wms(crtc, intermediate, level);
1481
1482         /*
1483          * If our intermediate WM are identical to the final WM, then we can
1484          * omit the post-vblank programming; only update if it's different.
1485          */
1486         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1487                 crtc_state->wm.need_postvbl_update = true;
1488
1489         return 0;
1490 }
1491
1492 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
1493                          struct vlv_wm_values *wm)
1494 {
1495         struct intel_crtc *crtc;
1496         int num_active_crtcs = 0;
1497
1498         wm->level = dev_priv->wm.max_level;
1499         wm->cxsr = true;
1500
1501         for_each_intel_crtc(&dev_priv->drm, crtc) {
1502                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
1503
1504                 if (!crtc->active)
1505                         continue;
1506
1507                 if (!wm_state->cxsr)
1508                         wm->cxsr = false;
1509
1510                 num_active_crtcs++;
1511                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1512         }
1513
1514         if (num_active_crtcs != 1)
1515                 wm->cxsr = false;
1516
1517         if (num_active_crtcs > 1)
1518                 wm->level = VLV_WM_LEVEL_PM2;
1519
1520         for_each_intel_crtc(&dev_priv->drm, crtc) {
1521                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
1522                 enum pipe pipe = crtc->pipe;
1523
1524                 wm->pipe[pipe] = wm_state->wm[wm->level];
1525                 if (crtc->active && wm->cxsr)
1526                         wm->sr = wm_state->sr[wm->level];
1527
1528                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
1529                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
1530                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
1531                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
1532         }
1533 }
1534
1535 static bool is_disabling(int old, int new, int threshold)
1536 {
1537         return old >= threshold && new < threshold;
1538 }
1539
1540 static bool is_enabling(int old, int new, int threshold)
1541 {
1542         return old < threshold && new >= threshold;
1543 }
1544
1545 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
1546 {
1547         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
1548         struct vlv_wm_values new_wm = {};
1549
1550         vlv_merge_wm(dev_priv, &new_wm);
1551
1552         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1553                 return;
1554
1555         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
1556                 chv_set_memory_dvfs(dev_priv, false);
1557
1558         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
1559                 chv_set_memory_pm5(dev_priv, false);
1560
1561         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1562                 _intel_set_memory_cxsr(dev_priv, false);
1563
1564         vlv_write_wm_values(dev_priv, &new_wm);
1565
1566         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1567                 _intel_set_memory_cxsr(dev_priv, true);
1568
1569         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
1570                 chv_set_memory_pm5(dev_priv, true);
1571
1572         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
1573                 chv_set_memory_dvfs(dev_priv, true);
1574
1575         *old_wm = new_wm;
1576 }
1577
1578 static void vlv_initial_watermarks(struct intel_atomic_state *state,
1579                                    struct intel_crtc_state *crtc_state)
1580 {
1581         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1582         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1583
1584         mutex_lock(&dev_priv->wm.wm_mutex);
1585         crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
1586         vlv_program_watermarks(dev_priv);
1587         mutex_unlock(&dev_priv->wm.wm_mutex);
1588 }
1589
1590 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
1591                                     struct intel_crtc_state *crtc_state)
1592 {
1593         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1595
1596         if (!crtc_state->wm.need_postvbl_update)
1597                 return;
1598
1599         mutex_lock(&dev_priv->wm.wm_mutex);
1600         intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
1601         vlv_program_watermarks(dev_priv);
1602         mutex_unlock(&dev_priv->wm.wm_mutex);
1603 }
1604
1605 #define single_plane_enabled(mask) is_power_of_2(mask)
1606
1607 static void g4x_update_wm(struct intel_crtc *crtc)
1608 {
1609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610         static const int sr_latency_ns = 12000;
1611         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1612         int plane_sr, cursor_sr;
1613         unsigned int enabled = 0;
1614         bool cxsr_enabled;
1615
1616         if (g4x_compute_wm0(dev_priv, PIPE_A,
1617                             &g4x_wm_info, pessimal_latency_ns,
1618                             &g4x_cursor_wm_info, pessimal_latency_ns,
1619                             &planea_wm, &cursora_wm))
1620                 enabled |= 1 << PIPE_A;
1621
1622         if (g4x_compute_wm0(dev_priv, PIPE_B,
1623                             &g4x_wm_info, pessimal_latency_ns,
1624                             &g4x_cursor_wm_info, pessimal_latency_ns,
1625                             &planeb_wm, &cursorb_wm))
1626                 enabled |= 1 << PIPE_B;
1627
1628         if (single_plane_enabled(enabled) &&
1629             g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1630                              sr_latency_ns,
1631                              &g4x_wm_info,
1632                              &g4x_cursor_wm_info,
1633                              &plane_sr, &cursor_sr)) {
1634                 cxsr_enabled = true;
1635         } else {
1636                 cxsr_enabled = false;
1637                 intel_set_memory_cxsr(dev_priv, false);
1638                 plane_sr = cursor_sr = 0;
1639         }
1640
1641         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1642                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1643                       planea_wm, cursora_wm,
1644                       planeb_wm, cursorb_wm,
1645                       plane_sr, cursor_sr);
1646
1647         I915_WRITE(DSPFW1,
1648                    FW_WM(plane_sr, SR) |
1649                    FW_WM(cursorb_wm, CURSORB) |
1650                    FW_WM(planeb_wm, PLANEB) |
1651                    FW_WM(planea_wm, PLANEA));
1652         I915_WRITE(DSPFW2,
1653                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1654                    FW_WM(cursora_wm, CURSORA));
1655         /* HPLL off in SR has some issues on G4x... disable it */
1656         I915_WRITE(DSPFW3,
1657                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1658                    FW_WM(cursor_sr, CURSOR_SR));
1659
1660         if (cxsr_enabled)
1661                 intel_set_memory_cxsr(dev_priv, true);
1662 }
1663
1664 static void i965_update_wm(struct intel_crtc *unused_crtc)
1665 {
1666         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1667         struct intel_crtc *crtc;
1668         int srwm = 1;
1669         int cursor_sr = 16;
1670         bool cxsr_enabled;
1671
1672         /* Calc sr entries for one plane configs */
1673         crtc = single_enabled_crtc(dev_priv);
1674         if (crtc) {
1675                 /* self-refresh has much higher latency */
1676                 static const int sr_latency_ns = 12000;
1677                 const struct drm_display_mode *adjusted_mode =
1678                         &crtc->config->base.adjusted_mode;
1679                 const struct drm_framebuffer *fb =
1680                         crtc->base.primary->state->fb;
1681                 int clock = adjusted_mode->crtc_clock;
1682                 int htotal = adjusted_mode->crtc_htotal;
1683                 int hdisplay = crtc->config->pipe_src_w;
1684                 int cpp = fb->format->cpp[0];
1685                 unsigned long line_time_us;
1686                 int entries;
1687
1688                 line_time_us = max(htotal * 1000 / clock, 1);
1689
1690                 /* Use ns/us then divide to preserve precision */
1691                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1692                         cpp * hdisplay;
1693                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1694                 srwm = I965_FIFO_SIZE - entries;
1695                 if (srwm < 0)
1696                         srwm = 1;
1697                 srwm &= 0x1ff;
1698                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1699                               entries, srwm);
1700
1701                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1702                         cpp * crtc->base.cursor->state->crtc_w;
1703                 entries = DIV_ROUND_UP(entries,
1704                                           i965_cursor_wm_info.cacheline_size);
1705                 cursor_sr = i965_cursor_wm_info.fifo_size -
1706                         (entries + i965_cursor_wm_info.guard_size);
1707
1708                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1709                         cursor_sr = i965_cursor_wm_info.max_wm;
1710
1711                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1712                               "cursor %d\n", srwm, cursor_sr);
1713
1714                 cxsr_enabled = true;
1715         } else {
1716                 cxsr_enabled = false;
1717                 /* Turn off self refresh if both pipes are enabled */
1718                 intel_set_memory_cxsr(dev_priv, false);
1719         }
1720
1721         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1722                       srwm);
1723
1724         /* 965 has limitations... */
1725         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1726                    FW_WM(8, CURSORB) |
1727                    FW_WM(8, PLANEB) |
1728                    FW_WM(8, PLANEA));
1729         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1730                    FW_WM(8, PLANEC_OLD));
1731         /* update cursor SR watermark */
1732         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1733
1734         if (cxsr_enabled)
1735                 intel_set_memory_cxsr(dev_priv, true);
1736 }
1737
1738 #undef FW_WM
1739
1740 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1741 {
1742         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1743         const struct intel_watermark_params *wm_info;
1744         uint32_t fwater_lo;
1745         uint32_t fwater_hi;
1746         int cwm, srwm = 1;
1747         int fifo_size;
1748         int planea_wm, planeb_wm;
1749         struct intel_crtc *crtc, *enabled = NULL;
1750
1751         if (IS_I945GM(dev_priv))
1752                 wm_info = &i945_wm_info;
1753         else if (!IS_GEN2(dev_priv))
1754                 wm_info = &i915_wm_info;
1755         else
1756                 wm_info = &i830_a_wm_info;
1757
1758         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1759         crtc = intel_get_crtc_for_plane(dev_priv, 0);
1760         if (intel_crtc_active(crtc)) {
1761                 const struct drm_display_mode *adjusted_mode =
1762                         &crtc->config->base.adjusted_mode;
1763                 const struct drm_framebuffer *fb =
1764                         crtc->base.primary->state->fb;
1765                 int cpp;
1766
1767                 if (IS_GEN2(dev_priv))
1768                         cpp = 4;
1769                 else
1770                         cpp = fb->format->cpp[0];
1771
1772                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1773                                                wm_info, fifo_size, cpp,
1774                                                pessimal_latency_ns);
1775                 enabled = crtc;
1776         } else {
1777                 planea_wm = fifo_size - wm_info->guard_size;
1778                 if (planea_wm > (long)wm_info->max_wm)
1779                         planea_wm = wm_info->max_wm;
1780         }
1781
1782         if (IS_GEN2(dev_priv))
1783                 wm_info = &i830_bc_wm_info;
1784
1785         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1786         crtc = intel_get_crtc_for_plane(dev_priv, 1);
1787         if (intel_crtc_active(crtc)) {
1788                 const struct drm_display_mode *adjusted_mode =
1789                         &crtc->config->base.adjusted_mode;
1790                 const struct drm_framebuffer *fb =
1791                         crtc->base.primary->state->fb;
1792                 int cpp;
1793
1794                 if (IS_GEN2(dev_priv))
1795                         cpp = 4;
1796                 else
1797                         cpp = fb->format->cpp[0];
1798
1799                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1800                                                wm_info, fifo_size, cpp,
1801                                                pessimal_latency_ns);
1802                 if (enabled == NULL)
1803                         enabled = crtc;
1804                 else
1805                         enabled = NULL;
1806         } else {
1807                 planeb_wm = fifo_size - wm_info->guard_size;
1808                 if (planeb_wm > (long)wm_info->max_wm)
1809                         planeb_wm = wm_info->max_wm;
1810         }
1811
1812         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1813
1814         if (IS_I915GM(dev_priv) && enabled) {
1815                 struct drm_i915_gem_object *obj;
1816
1817                 obj = intel_fb_obj(enabled->base.primary->state->fb);
1818
1819                 /* self-refresh seems busted with untiled */
1820                 if (!i915_gem_object_is_tiled(obj))
1821                         enabled = NULL;
1822         }
1823
1824         /*
1825          * Overlay gets an aggressive default since video jitter is bad.
1826          */
1827         cwm = 2;
1828
1829         /* Play safe and disable self-refresh before adjusting watermarks. */
1830         intel_set_memory_cxsr(dev_priv, false);
1831
1832         /* Calc sr entries for one plane configs */
1833         if (HAS_FW_BLC(dev_priv) && enabled) {
1834                 /* self-refresh has much higher latency */
1835                 static const int sr_latency_ns = 6000;
1836                 const struct drm_display_mode *adjusted_mode =
1837                         &enabled->config->base.adjusted_mode;
1838                 const struct drm_framebuffer *fb =
1839                         enabled->base.primary->state->fb;
1840                 int clock = adjusted_mode->crtc_clock;
1841                 int htotal = adjusted_mode->crtc_htotal;
1842                 int hdisplay = enabled->config->pipe_src_w;
1843                 int cpp;
1844                 unsigned long line_time_us;
1845                 int entries;
1846
1847                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1848                         cpp = 4;
1849                 else
1850                         cpp = fb->format->cpp[0];
1851
1852                 line_time_us = max(htotal * 1000 / clock, 1);
1853
1854                 /* Use ns/us then divide to preserve precision */
1855                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1856                         cpp * hdisplay;
1857                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1858                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1859                 srwm = wm_info->fifo_size - entries;
1860                 if (srwm < 0)
1861                         srwm = 1;
1862
1863                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1864                         I915_WRITE(FW_BLC_SELF,
1865                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1866                 else
1867                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1868         }
1869
1870         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1871                       planea_wm, planeb_wm, cwm, srwm);
1872
1873         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1874         fwater_hi = (cwm & 0x1f);
1875
1876         /* Set request length to 8 cachelines per fetch */
1877         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1878         fwater_hi = fwater_hi | (1 << 8);
1879
1880         I915_WRITE(FW_BLC, fwater_lo);
1881         I915_WRITE(FW_BLC2, fwater_hi);
1882
1883         if (enabled)
1884                 intel_set_memory_cxsr(dev_priv, true);
1885 }
1886
1887 static void i845_update_wm(struct intel_crtc *unused_crtc)
1888 {
1889         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1890         struct intel_crtc *crtc;
1891         const struct drm_display_mode *adjusted_mode;
1892         uint32_t fwater_lo;
1893         int planea_wm;
1894
1895         crtc = single_enabled_crtc(dev_priv);
1896         if (crtc == NULL)
1897                 return;
1898
1899         adjusted_mode = &crtc->config->base.adjusted_mode;
1900         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1901                                        &i845_wm_info,
1902                                        dev_priv->display.get_fifo_size(dev_priv, 0),
1903                                        4, pessimal_latency_ns);
1904         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1905         fwater_lo |= (3<<8) | planea_wm;
1906
1907         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1908
1909         I915_WRITE(FW_BLC, fwater_lo);
1910 }
1911
1912 /* latency must be in 0.1us units. */
1913 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1914 {
1915         uint64_t ret;
1916
1917         if (WARN(latency == 0, "Latency value missing\n"))
1918                 return UINT_MAX;
1919
1920         ret = (uint64_t) pixel_rate * cpp * latency;
1921         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1922
1923         return ret;
1924 }
1925
1926 /* latency must be in 0.1us units. */
1927 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1928                                uint32_t horiz_pixels, uint8_t cpp,
1929                                uint32_t latency)
1930 {
1931         uint32_t ret;
1932
1933         if (WARN(latency == 0, "Latency value missing\n"))
1934                 return UINT_MAX;
1935         if (WARN_ON(!pipe_htotal))
1936                 return UINT_MAX;
1937
1938         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1939         ret = (ret + 1) * horiz_pixels * cpp;
1940         ret = DIV_ROUND_UP(ret, 64) + 2;
1941         return ret;
1942 }
1943
1944 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1945                            uint8_t cpp)
1946 {
1947         /*
1948          * Neither of these should be possible since this function shouldn't be
1949          * called if the CRTC is off or the plane is invisible.  But let's be
1950          * extra paranoid to avoid a potential divide-by-zero if we screw up
1951          * elsewhere in the driver.
1952          */
1953         if (WARN_ON(!cpp))
1954                 return 0;
1955         if (WARN_ON(!horiz_pixels))
1956                 return 0;
1957
1958         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1959 }
1960
1961 struct ilk_wm_maximums {
1962         uint16_t pri;
1963         uint16_t spr;
1964         uint16_t cur;
1965         uint16_t fbc;
1966 };
1967
1968 /*
1969  * For both WM_PIPE and WM_LP.
1970  * mem_value must be in 0.1us units.
1971  */
1972 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1973                                    const struct intel_plane_state *pstate,
1974                                    uint32_t mem_value,
1975                                    bool is_lp)
1976 {
1977         uint32_t method1, method2;
1978         int cpp;
1979
1980         if (!intel_wm_plane_visible(cstate, pstate))
1981                 return 0;
1982
1983         cpp = pstate->base.fb->format->cpp[0];
1984
1985         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
1986
1987         if (!is_lp)
1988                 return method1;
1989
1990         method2 = ilk_wm_method2(cstate->pixel_rate,
1991                                  cstate->base.adjusted_mode.crtc_htotal,
1992                                  drm_rect_width(&pstate->base.dst),
1993                                  cpp, mem_value);
1994
1995         return min(method1, method2);
1996 }
1997
1998 /*
1999  * For both WM_PIPE and WM_LP.
2000  * mem_value must be in 0.1us units.
2001  */
2002 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
2003                                    const struct intel_plane_state *pstate,
2004                                    uint32_t mem_value)
2005 {
2006         uint32_t method1, method2;
2007         int cpp;
2008
2009         if (!intel_wm_plane_visible(cstate, pstate))
2010                 return 0;
2011
2012         cpp = pstate->base.fb->format->cpp[0];
2013
2014         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2015         method2 = ilk_wm_method2(cstate->pixel_rate,
2016                                  cstate->base.adjusted_mode.crtc_htotal,
2017                                  drm_rect_width(&pstate->base.dst),
2018                                  cpp, mem_value);
2019         return min(method1, method2);
2020 }
2021
2022 /*
2023  * For both WM_PIPE and WM_LP.
2024  * mem_value must be in 0.1us units.
2025  */
2026 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
2027                                    const struct intel_plane_state *pstate,
2028                                    uint32_t mem_value)
2029 {
2030         int cpp;
2031
2032         if (!intel_wm_plane_visible(cstate, pstate))
2033                 return 0;
2034
2035         cpp = pstate->base.fb->format->cpp[0];
2036
2037         return ilk_wm_method2(cstate->pixel_rate,
2038                               cstate->base.adjusted_mode.crtc_htotal,
2039                               pstate->base.crtc_w, cpp, mem_value);
2040 }
2041
2042 /* Only for WM_LP. */
2043 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
2044                                    const struct intel_plane_state *pstate,
2045                                    uint32_t pri_val)
2046 {
2047         int cpp;
2048
2049         if (!intel_wm_plane_visible(cstate, pstate))
2050                 return 0;
2051
2052         cpp = pstate->base.fb->format->cpp[0];
2053
2054         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
2055 }
2056
2057 static unsigned int
2058 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2059 {
2060         if (INTEL_GEN(dev_priv) >= 8)
2061                 return 3072;
2062         else if (INTEL_GEN(dev_priv) >= 7)
2063                 return 768;
2064         else
2065                 return 512;
2066 }
2067
2068 static unsigned int
2069 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2070                      int level, bool is_sprite)
2071 {
2072         if (INTEL_GEN(dev_priv) >= 8)
2073                 /* BDW primary/sprite plane watermarks */
2074                 return level == 0 ? 255 : 2047;
2075         else if (INTEL_GEN(dev_priv) >= 7)
2076                 /* IVB/HSW primary/sprite plane watermarks */
2077                 return level == 0 ? 127 : 1023;
2078         else if (!is_sprite)
2079                 /* ILK/SNB primary plane watermarks */
2080                 return level == 0 ? 127 : 511;
2081         else
2082                 /* ILK/SNB sprite plane watermarks */
2083                 return level == 0 ? 63 : 255;
2084 }
2085
2086 static unsigned int
2087 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2088 {
2089         if (INTEL_GEN(dev_priv) >= 7)
2090                 return level == 0 ? 63 : 255;
2091         else
2092                 return level == 0 ? 31 : 63;
2093 }
2094
2095 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2096 {
2097         if (INTEL_GEN(dev_priv) >= 8)
2098                 return 31;
2099         else
2100                 return 15;
2101 }
2102
2103 /* Calculate the maximum primary/sprite plane watermark */
2104 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2105                                      int level,
2106                                      const struct intel_wm_config *config,
2107                                      enum intel_ddb_partitioning ddb_partitioning,
2108                                      bool is_sprite)
2109 {
2110         struct drm_i915_private *dev_priv = to_i915(dev);
2111         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2112
2113         /* if sprites aren't enabled, sprites get nothing */
2114         if (is_sprite && !config->sprites_enabled)
2115                 return 0;
2116
2117         /* HSW allows LP1+ watermarks even with multiple pipes */
2118         if (level == 0 || config->num_pipes_active > 1) {
2119                 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
2120
2121                 /*
2122                  * For some reason the non self refresh
2123                  * FIFO size is only half of the self
2124                  * refresh FIFO size on ILK/SNB.
2125                  */
2126                 if (INTEL_GEN(dev_priv) <= 6)
2127                         fifo_size /= 2;
2128         }
2129
2130         if (config->sprites_enabled) {
2131                 /* level 0 is always calculated with 1:1 split */
2132                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2133                         if (is_sprite)
2134                                 fifo_size *= 5;
2135                         fifo_size /= 6;
2136                 } else {
2137                         fifo_size /= 2;
2138                 }
2139         }
2140
2141         /* clamp to max that the registers can hold */
2142         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2143 }
2144
2145 /* Calculate the maximum cursor plane watermark */
2146 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2147                                       int level,
2148                                       const struct intel_wm_config *config)
2149 {
2150         /* HSW LP1+ watermarks w/ multiple pipes */
2151         if (level > 0 && config->num_pipes_active > 1)
2152                 return 64;
2153
2154         /* otherwise just report max that registers can hold */
2155         return ilk_cursor_wm_reg_max(to_i915(dev), level);
2156 }
2157
2158 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2159                                     int level,
2160                                     const struct intel_wm_config *config,
2161                                     enum intel_ddb_partitioning ddb_partitioning,
2162                                     struct ilk_wm_maximums *max)
2163 {
2164         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2165         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2166         max->cur = ilk_cursor_wm_max(dev, level, config);
2167         max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
2168 }
2169
2170 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2171                                         int level,
2172                                         struct ilk_wm_maximums *max)
2173 {
2174         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2175         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2176         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2177         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2178 }
2179
2180 static bool ilk_validate_wm_level(int level,
2181                                   const struct ilk_wm_maximums *max,
2182                                   struct intel_wm_level *result)
2183 {
2184         bool ret;
2185
2186         /* already determined to be invalid? */
2187         if (!result->enable)
2188                 return false;
2189
2190         result->enable = result->pri_val <= max->pri &&
2191                          result->spr_val <= max->spr &&
2192                          result->cur_val <= max->cur;
2193
2194         ret = result->enable;
2195
2196         /*
2197          * HACK until we can pre-compute everything,
2198          * and thus fail gracefully if LP0 watermarks
2199          * are exceeded...
2200          */
2201         if (level == 0 && !result->enable) {
2202                 if (result->pri_val > max->pri)
2203                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2204                                       level, result->pri_val, max->pri);
2205                 if (result->spr_val > max->spr)
2206                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2207                                       level, result->spr_val, max->spr);
2208                 if (result->cur_val > max->cur)
2209                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2210                                       level, result->cur_val, max->cur);
2211
2212                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2213                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2214                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2215                 result->enable = true;
2216         }
2217
2218         return ret;
2219 }
2220
2221 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2222                                  const struct intel_crtc *intel_crtc,
2223                                  int level,
2224                                  struct intel_crtc_state *cstate,
2225                                  struct intel_plane_state *pristate,
2226                                  struct intel_plane_state *sprstate,
2227                                  struct intel_plane_state *curstate,
2228                                  struct intel_wm_level *result)
2229 {
2230         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2231         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2232         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2233
2234         /* WM1+ latency values stored in 0.5us units */
2235         if (level > 0) {
2236                 pri_latency *= 5;
2237                 spr_latency *= 5;
2238                 cur_latency *= 5;
2239         }
2240
2241         if (pristate) {
2242                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2243                                                      pri_latency, level);
2244                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2245         }
2246
2247         if (sprstate)
2248                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2249
2250         if (curstate)
2251                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2252
2253         result->enable = true;
2254 }
2255
2256 static uint32_t
2257 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2258 {
2259         const struct intel_atomic_state *intel_state =
2260                 to_intel_atomic_state(cstate->base.state);
2261         const struct drm_display_mode *adjusted_mode =
2262                 &cstate->base.adjusted_mode;
2263         u32 linetime, ips_linetime;
2264
2265         if (!cstate->base.active)
2266                 return 0;
2267         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2268                 return 0;
2269         if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2270                 return 0;
2271
2272         /* The WM are computed with base on how long it takes to fill a single
2273          * row at the given clock rate, multiplied by 8.
2274          * */
2275         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2276                                      adjusted_mode->crtc_clock);
2277         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2278                                          intel_state->cdclk.logical.cdclk);
2279
2280         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2281                PIPE_WM_LINETIME_TIME(linetime);
2282 }
2283
2284 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2285                                   uint16_t wm[8])
2286 {
2287         if (IS_GEN9(dev_priv)) {
2288                 uint32_t val;
2289                 int ret, i;
2290                 int level, max_level = ilk_wm_max_level(dev_priv);
2291
2292                 /* read the first set of memory latencies[0:3] */
2293                 val = 0; /* data0 to be programmed to 0 for first set */
2294                 mutex_lock(&dev_priv->rps.hw_lock);
2295                 ret = sandybridge_pcode_read(dev_priv,
2296                                              GEN9_PCODE_READ_MEM_LATENCY,
2297                                              &val);
2298                 mutex_unlock(&dev_priv->rps.hw_lock);
2299
2300                 if (ret) {
2301                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2302                         return;
2303                 }
2304
2305                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2306                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2307                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2308                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2309                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2310                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2311                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2312
2313                 /* read the second set of memory latencies[4:7] */
2314                 val = 1; /* data0 to be programmed to 1 for second set */
2315                 mutex_lock(&dev_priv->rps.hw_lock);
2316                 ret = sandybridge_pcode_read(dev_priv,
2317                                              GEN9_PCODE_READ_MEM_LATENCY,
2318                                              &val);
2319                 mutex_unlock(&dev_priv->rps.hw_lock);
2320                 if (ret) {
2321                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2322                         return;
2323                 }
2324
2325                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2326                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2327                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2328                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2329                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2330                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2331                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2332
2333                 /*
2334                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2335                  * need to be disabled. We make sure to sanitize the values out
2336                  * of the punit to satisfy this requirement.
2337                  */
2338                 for (level = 1; level <= max_level; level++) {
2339                         if (wm[level] == 0) {
2340                                 for (i = level + 1; i <= max_level; i++)
2341                                         wm[i] = 0;
2342                                 break;
2343                         }
2344                 }
2345
2346                 /*
2347                  * WaWmMemoryReadLatency:skl,glk
2348                  *
2349                  * punit doesn't take into account the read latency so we need
2350                  * to add 2us to the various latency levels we retrieve from the
2351                  * punit when level 0 response data us 0us.
2352                  */
2353                 if (wm[0] == 0) {
2354                         wm[0] += 2;
2355                         for (level = 1; level <= max_level; level++) {
2356                                 if (wm[level] == 0)
2357                                         break;
2358                                 wm[level] += 2;
2359                         }
2360                 }
2361
2362         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2363                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2364
2365                 wm[0] = (sskpd >> 56) & 0xFF;
2366                 if (wm[0] == 0)
2367                         wm[0] = sskpd & 0xF;
2368                 wm[1] = (sskpd >> 4) & 0xFF;
2369                 wm[2] = (sskpd >> 12) & 0xFF;
2370                 wm[3] = (sskpd >> 20) & 0x1FF;
2371                 wm[4] = (sskpd >> 32) & 0x1FF;
2372         } else if (INTEL_GEN(dev_priv) >= 6) {
2373                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2374
2375                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2376                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2377                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2378                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2379         } else if (INTEL_GEN(dev_priv) >= 5) {
2380                 uint32_t mltr = I915_READ(MLTR_ILK);
2381
2382                 /* ILK primary LP0 latency is 700 ns */
2383                 wm[0] = 7;
2384                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2385                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2386         }
2387 }
2388
2389 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2390                                        uint16_t wm[5])
2391 {
2392         /* ILK sprite LP0 latency is 1300 ns */
2393         if (IS_GEN5(dev_priv))
2394                 wm[0] = 13;
2395 }
2396
2397 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2398                                        uint16_t wm[5])
2399 {
2400         /* ILK cursor LP0 latency is 1300 ns */
2401         if (IS_GEN5(dev_priv))
2402                 wm[0] = 13;
2403
2404         /* WaDoubleCursorLP3Latency:ivb */
2405         if (IS_IVYBRIDGE(dev_priv))
2406                 wm[3] *= 2;
2407 }
2408
2409 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2410 {
2411         /* how many WM levels are we expecting */
2412         if (INTEL_GEN(dev_priv) >= 9)
2413                 return 7;
2414         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2415                 return 4;
2416         else if (INTEL_GEN(dev_priv) >= 6)
2417                 return 3;
2418         else
2419                 return 2;
2420 }
2421
2422 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2423                                    const char *name,
2424                                    const uint16_t wm[8])
2425 {
2426         int level, max_level = ilk_wm_max_level(dev_priv);
2427
2428         for (level = 0; level <= max_level; level++) {
2429                 unsigned int latency = wm[level];
2430
2431                 if (latency == 0) {
2432                         DRM_ERROR("%s WM%d latency not provided\n",
2433                                   name, level);
2434                         continue;
2435                 }
2436
2437                 /*
2438                  * - latencies are in us on gen9.
2439                  * - before then, WM1+ latency values are in 0.5us units
2440                  */
2441                 if (IS_GEN9(dev_priv))
2442                         latency *= 10;
2443                 else if (level > 0)
2444                         latency *= 5;
2445
2446                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2447                               name, level, wm[level],
2448                               latency / 10, latency % 10);
2449         }
2450 }
2451
2452 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2453                                     uint16_t wm[5], uint16_t min)
2454 {
2455         int level, max_level = ilk_wm_max_level(dev_priv);
2456
2457         if (wm[0] >= min)
2458                 return false;
2459
2460         wm[0] = max(wm[0], min);
2461         for (level = 1; level <= max_level; level++)
2462                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2463
2464         return true;
2465 }
2466
2467 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2468 {
2469         bool changed;
2470
2471         /*
2472          * The BIOS provided WM memory latency values are often
2473          * inadequate for high resolution displays. Adjust them.
2474          */
2475         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2476                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2477                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2478
2479         if (!changed)
2480                 return;
2481
2482         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2483         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2484         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2485         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2486 }
2487
2488 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2489 {
2490         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2491
2492         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2493                sizeof(dev_priv->wm.pri_latency));
2494         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2495                sizeof(dev_priv->wm.pri_latency));
2496
2497         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2498         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2499
2500         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2501         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2502         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2503
2504         if (IS_GEN6(dev_priv))
2505                 snb_wm_latency_quirk(dev_priv);
2506 }
2507
2508 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2509 {
2510         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2511         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2512 }
2513
2514 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2515                                  struct intel_pipe_wm *pipe_wm)
2516 {
2517         /* LP0 watermark maximums depend on this pipe alone */
2518         const struct intel_wm_config config = {
2519                 .num_pipes_active = 1,
2520                 .sprites_enabled = pipe_wm->sprites_enabled,
2521                 .sprites_scaled = pipe_wm->sprites_scaled,
2522         };
2523         struct ilk_wm_maximums max;
2524
2525         /* LP0 watermarks always use 1/2 DDB partitioning */
2526         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2527
2528         /* At least LP0 must be valid */
2529         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2530                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2531                 return false;
2532         }
2533
2534         return true;
2535 }
2536
2537 /* Compute new watermarks for the pipe */
2538 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2539 {
2540         struct drm_atomic_state *state = cstate->base.state;
2541         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2542         struct intel_pipe_wm *pipe_wm;
2543         struct drm_device *dev = state->dev;
2544         const struct drm_i915_private *dev_priv = to_i915(dev);
2545         struct intel_plane *intel_plane;
2546         struct intel_plane_state *pristate = NULL;
2547         struct intel_plane_state *sprstate = NULL;
2548         struct intel_plane_state *curstate = NULL;
2549         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2550         struct ilk_wm_maximums max;
2551
2552         pipe_wm = &cstate->wm.ilk.optimal;
2553
2554         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2555                 struct intel_plane_state *ps;
2556
2557                 ps = intel_atomic_get_existing_plane_state(state,
2558                                                            intel_plane);
2559                 if (!ps)
2560                         continue;
2561
2562                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2563                         pristate = ps;
2564                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2565                         sprstate = ps;
2566                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2567                         curstate = ps;
2568         }
2569
2570         pipe_wm->pipe_enabled = cstate->base.active;
2571         if (sprstate) {
2572                 pipe_wm->sprites_enabled = sprstate->base.visible;
2573                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2574                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2575                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2576         }
2577
2578         usable_level = max_level;
2579
2580         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2581         if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
2582                 usable_level = 1;
2583
2584         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2585         if (pipe_wm->sprites_scaled)
2586                 usable_level = 0;
2587
2588         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2589                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2590
2591         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2592         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2593
2594         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2595                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2596
2597         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2598                 return -EINVAL;
2599
2600         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
2601
2602         for (level = 1; level <= max_level; level++) {
2603                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2604
2605                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2606                                      pristate, sprstate, curstate, wm);
2607
2608                 /*
2609                  * Disable any watermark level that exceeds the
2610                  * register maximums since such watermarks are
2611                  * always invalid.
2612                  */
2613                 if (level > usable_level)
2614                         continue;
2615
2616                 if (ilk_validate_wm_level(level, &max, wm))
2617                         pipe_wm->wm[level] = *wm;
2618                 else
2619                         usable_level = level;
2620         }
2621
2622         return 0;
2623 }
2624
2625 /*
2626  * Build a set of 'intermediate' watermark values that satisfy both the old
2627  * state and the new state.  These can be programmed to the hardware
2628  * immediately.
2629  */
2630 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2631                                        struct intel_crtc *intel_crtc,
2632                                        struct intel_crtc_state *newstate)
2633 {
2634         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2635         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2636         int level, max_level = ilk_wm_max_level(to_i915(dev));
2637
2638         /*
2639          * Start with the final, target watermarks, then combine with the
2640          * currently active watermarks to get values that are safe both before
2641          * and after the vblank.
2642          */
2643         *a = newstate->wm.ilk.optimal;
2644         a->pipe_enabled |= b->pipe_enabled;
2645         a->sprites_enabled |= b->sprites_enabled;
2646         a->sprites_scaled |= b->sprites_scaled;
2647
2648         for (level = 0; level <= max_level; level++) {
2649                 struct intel_wm_level *a_wm = &a->wm[level];
2650                 const struct intel_wm_level *b_wm = &b->wm[level];
2651
2652                 a_wm->enable &= b_wm->enable;
2653                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2654                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2655                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2656                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2657         }
2658
2659         /*
2660          * We need to make sure that these merged watermark values are
2661          * actually a valid configuration themselves.  If they're not,
2662          * there's no safe way to transition from the old state to
2663          * the new state, so we need to fail the atomic transaction.
2664          */
2665         if (!ilk_validate_pipe_wm(dev, a))
2666                 return -EINVAL;
2667
2668         /*
2669          * If our intermediate WM are identical to the final WM, then we can
2670          * omit the post-vblank programming; only update if it's different.
2671          */
2672         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
2673                 newstate->wm.need_postvbl_update = true;
2674
2675         return 0;
2676 }
2677
2678 /*
2679  * Merge the watermarks from all active pipes for a specific level.
2680  */
2681 static void ilk_merge_wm_level(struct drm_device *dev,
2682                                int level,
2683                                struct intel_wm_level *ret_wm)
2684 {
2685         const struct intel_crtc *intel_crtc;
2686
2687         ret_wm->enable = true;
2688
2689         for_each_intel_crtc(dev, intel_crtc) {
2690                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2691                 const struct intel_wm_level *wm = &active->wm[level];
2692
2693                 if (!active->pipe_enabled)
2694                         continue;
2695
2696                 /*
2697                  * The watermark values may have been used in the past,
2698                  * so we must maintain them in the registers for some
2699                  * time even if the level is now disabled.
2700                  */
2701                 if (!wm->enable)
2702                         ret_wm->enable = false;
2703
2704                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2705                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2706                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2707                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2708         }
2709 }
2710
2711 /*
2712  * Merge all low power watermarks for all active pipes.
2713  */
2714 static void ilk_wm_merge(struct drm_device *dev,
2715                          const struct intel_wm_config *config,
2716                          const struct ilk_wm_maximums *max,
2717                          struct intel_pipe_wm *merged)
2718 {
2719         struct drm_i915_private *dev_priv = to_i915(dev);
2720         int level, max_level = ilk_wm_max_level(dev_priv);
2721         int last_enabled_level = max_level;
2722
2723         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2724         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2725             config->num_pipes_active > 1)
2726                 last_enabled_level = 0;
2727
2728         /* ILK: FBC WM must be disabled always */
2729         merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
2730
2731         /* merge each WM1+ level */
2732         for (level = 1; level <= max_level; level++) {
2733                 struct intel_wm_level *wm = &merged->wm[level];
2734
2735                 ilk_merge_wm_level(dev, level, wm);
2736
2737                 if (level > last_enabled_level)
2738                         wm->enable = false;
2739                 else if (!ilk_validate_wm_level(level, max, wm))
2740                         /* make sure all following levels get disabled */
2741                         last_enabled_level = level - 1;
2742
2743                 /*
2744                  * The spec says it is preferred to disable
2745                  * FBC WMs instead of disabling a WM level.
2746                  */
2747                 if (wm->fbc_val > max->fbc) {
2748                         if (wm->enable)
2749                                 merged->fbc_wm_enabled = false;
2750                         wm->fbc_val = 0;
2751                 }
2752         }
2753
2754         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2755         /*
2756          * FIXME this is racy. FBC might get enabled later.
2757          * What we should check here is whether FBC can be
2758          * enabled sometime later.
2759          */
2760         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2761             intel_fbc_is_active(dev_priv)) {
2762                 for (level = 2; level <= max_level; level++) {
2763                         struct intel_wm_level *wm = &merged->wm[level];
2764
2765                         wm->enable = false;
2766                 }
2767         }
2768 }
2769
2770 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2771 {
2772         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2773         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2774 }
2775
2776 /* The value we need to program into the WM_LPx latency field */
2777 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2778 {
2779         struct drm_i915_private *dev_priv = to_i915(dev);
2780
2781         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2782                 return 2 * level;
2783         else
2784                 return dev_priv->wm.pri_latency[level];
2785 }
2786
2787 static void ilk_compute_wm_results(struct drm_device *dev,
2788                                    const struct intel_pipe_wm *merged,
2789                                    enum intel_ddb_partitioning partitioning,
2790                                    struct ilk_wm_values *results)
2791 {
2792         struct drm_i915_private *dev_priv = to_i915(dev);
2793         struct intel_crtc *intel_crtc;
2794         int level, wm_lp;
2795
2796         results->enable_fbc_wm = merged->fbc_wm_enabled;
2797         results->partitioning = partitioning;
2798
2799         /* LP1+ register values */
2800         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2801                 const struct intel_wm_level *r;
2802
2803                 level = ilk_wm_lp_to_level(wm_lp, merged);
2804
2805                 r = &merged->wm[level];
2806
2807                 /*
2808                  * Maintain the watermark values even if the level is
2809                  * disabled. Doing otherwise could cause underruns.
2810                  */
2811                 results->wm_lp[wm_lp - 1] =
2812                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2813                         (r->pri_val << WM1_LP_SR_SHIFT) |
2814                         r->cur_val;
2815
2816                 if (r->enable)
2817                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2818
2819                 if (INTEL_GEN(dev_priv) >= 8)
2820                         results->wm_lp[wm_lp - 1] |=
2821                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2822                 else
2823                         results->wm_lp[wm_lp - 1] |=
2824                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2825
2826                 /*
2827                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2828                  * level is disabled. Doing otherwise could cause underruns.
2829                  */
2830                 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
2831                         WARN_ON(wm_lp != 1);
2832                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2833                 } else
2834                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2835         }
2836
2837         /* LP0 register values */
2838         for_each_intel_crtc(dev, intel_crtc) {
2839                 enum pipe pipe = intel_crtc->pipe;
2840                 const struct intel_wm_level *r =
2841                         &intel_crtc->wm.active.ilk.wm[0];
2842
2843                 if (WARN_ON(!r->enable))
2844                         continue;
2845
2846                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2847
2848                 results->wm_pipe[pipe] =
2849                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2850                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2851                         r->cur_val;
2852         }
2853 }
2854
2855 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2856  * case both are at the same level. Prefer r1 in case they're the same. */
2857 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2858                                                   struct intel_pipe_wm *r1,
2859                                                   struct intel_pipe_wm *r2)
2860 {
2861         int level, max_level = ilk_wm_max_level(to_i915(dev));
2862         int level1 = 0, level2 = 0;
2863
2864         for (level = 1; level <= max_level; level++) {
2865                 if (r1->wm[level].enable)
2866                         level1 = level;
2867                 if (r2->wm[level].enable)
2868                         level2 = level;
2869         }
2870
2871         if (level1 == level2) {
2872                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2873                         return r2;
2874                 else
2875                         return r1;
2876         } else if (level1 > level2) {
2877                 return r1;
2878         } else {
2879                 return r2;
2880         }
2881 }
2882
2883 /* dirty bits used to track which watermarks need changes */
2884 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2885 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2886 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2887 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2888 #define WM_DIRTY_FBC (1 << 24)
2889 #define WM_DIRTY_DDB (1 << 25)
2890
2891 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2892                                          const struct ilk_wm_values *old,
2893                                          const struct ilk_wm_values *new)
2894 {
2895         unsigned int dirty = 0;
2896         enum pipe pipe;
2897         int wm_lp;
2898
2899         for_each_pipe(dev_priv, pipe) {
2900                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2901                         dirty |= WM_DIRTY_LINETIME(pipe);
2902                         /* Must disable LP1+ watermarks too */
2903                         dirty |= WM_DIRTY_LP_ALL;
2904                 }
2905
2906                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2907                         dirty |= WM_DIRTY_PIPE(pipe);
2908                         /* Must disable LP1+ watermarks too */
2909                         dirty |= WM_DIRTY_LP_ALL;
2910                 }
2911         }
2912
2913         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2914                 dirty |= WM_DIRTY_FBC;
2915                 /* Must disable LP1+ watermarks too */
2916                 dirty |= WM_DIRTY_LP_ALL;
2917         }
2918
2919         if (old->partitioning != new->partitioning) {
2920                 dirty |= WM_DIRTY_DDB;
2921                 /* Must disable LP1+ watermarks too */
2922                 dirty |= WM_DIRTY_LP_ALL;
2923         }
2924
2925         /* LP1+ watermarks already deemed dirty, no need to continue */
2926         if (dirty & WM_DIRTY_LP_ALL)
2927                 return dirty;
2928
2929         /* Find the lowest numbered LP1+ watermark in need of an update... */
2930         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2931                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2932                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2933                         break;
2934         }
2935
2936         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2937         for (; wm_lp <= 3; wm_lp++)
2938                 dirty |= WM_DIRTY_LP(wm_lp);
2939
2940         return dirty;
2941 }
2942
2943 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2944                                unsigned int dirty)
2945 {
2946         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2947         bool changed = false;
2948
2949         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2950                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2951                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2952                 changed = true;
2953         }
2954         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2955                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2956                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2957                 changed = true;
2958         }
2959         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2960                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2961                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2962                 changed = true;
2963         }
2964
2965         /*
2966          * Don't touch WM1S_LP_EN here.
2967          * Doing so could cause underruns.
2968          */
2969
2970         return changed;
2971 }
2972
2973 /*
2974  * The spec says we shouldn't write when we don't need, because every write
2975  * causes WMs to be re-evaluated, expending some power.
2976  */
2977 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2978                                 struct ilk_wm_values *results)
2979 {
2980         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2981         unsigned int dirty;
2982         uint32_t val;
2983
2984         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2985         if (!dirty)
2986                 return;
2987
2988         _ilk_disable_lp_wm(dev_priv, dirty);
2989
2990         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2991                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2992         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2993                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2994         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2995                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2996
2997         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2998                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2999         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
3000                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
3001         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
3002                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
3003
3004         if (dirty & WM_DIRTY_DDB) {
3005                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3006                         val = I915_READ(WM_MISC);
3007                         if (results->partitioning == INTEL_DDB_PART_1_2)
3008                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
3009                         else
3010                                 val |= WM_MISC_DATA_PARTITION_5_6;
3011                         I915_WRITE(WM_MISC, val);
3012                 } else {
3013                         val = I915_READ(DISP_ARB_CTL2);
3014                         if (results->partitioning == INTEL_DDB_PART_1_2)
3015                                 val &= ~DISP_DATA_PARTITION_5_6;
3016                         else
3017                                 val |= DISP_DATA_PARTITION_5_6;
3018                         I915_WRITE(DISP_ARB_CTL2, val);
3019                 }
3020         }
3021
3022         if (dirty & WM_DIRTY_FBC) {
3023                 val = I915_READ(DISP_ARB_CTL);
3024                 if (results->enable_fbc_wm)
3025                         val &= ~DISP_FBC_WM_DIS;
3026                 else
3027                         val |= DISP_FBC_WM_DIS;
3028                 I915_WRITE(DISP_ARB_CTL, val);
3029         }
3030
3031         if (dirty & WM_DIRTY_LP(1) &&
3032             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3033                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3034
3035         if (INTEL_GEN(dev_priv) >= 7) {
3036                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3037                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3038                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3039                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3040         }
3041
3042         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3043                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3044         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3045                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3046         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3047                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3048
3049         dev_priv->wm.hw = *results;
3050 }
3051
3052 bool ilk_disable_lp_wm(struct drm_device *dev)
3053 {
3054         struct drm_i915_private *dev_priv = to_i915(dev);
3055
3056         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3057 }
3058
3059 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
3060
3061 /*
3062  * FIXME: We still don't have the proper code detect if we need to apply the WA,
3063  * so assume we'll always need it in order to avoid underruns.
3064  */
3065 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
3066 {
3067         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3068
3069         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
3070                 return true;
3071
3072         return false;
3073 }
3074
3075 static bool
3076 intel_has_sagv(struct drm_i915_private *dev_priv)
3077 {
3078         if (IS_KABYLAKE(dev_priv))
3079                 return true;
3080
3081         if (IS_SKYLAKE(dev_priv) &&
3082             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
3083                 return true;
3084
3085         return false;
3086 }
3087
3088 /*
3089  * SAGV dynamically adjusts the system agent voltage and clock frequencies
3090  * depending on power and performance requirements. The display engine access
3091  * to system memory is blocked during the adjustment time. Because of the
3092  * blocking time, having this enabled can cause full system hangs and/or pipe
3093  * underruns if we don't meet all of the following requirements:
3094  *
3095  *  - <= 1 pipe enabled
3096  *  - All planes can enable watermarks for latencies >= SAGV engine block time
3097  *  - We're not using an interlaced display configuration
3098  */
3099 int
3100 intel_enable_sagv(struct drm_i915_private *dev_priv)
3101 {
3102         int ret;
3103
3104         if (!intel_has_sagv(dev_priv))
3105                 return 0;
3106
3107         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3108                 return 0;
3109
3110         DRM_DEBUG_KMS("Enabling the SAGV\n");
3111         mutex_lock(&dev_priv->rps.hw_lock);
3112
3113         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3114                                       GEN9_SAGV_ENABLE);
3115
3116         /* We don't need to wait for the SAGV when enabling */
3117         mutex_unlock(&dev_priv->rps.hw_lock);
3118
3119         /*
3120          * Some skl systems, pre-release machines in particular,
3121          * don't actually have an SAGV.
3122          */
3123         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3124                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3125                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3126                 return 0;
3127         } else if (ret < 0) {
3128                 DRM_ERROR("Failed to enable the SAGV\n");
3129                 return ret;
3130         }
3131
3132         dev_priv->sagv_status = I915_SAGV_ENABLED;
3133         return 0;
3134 }
3135
3136 int
3137 intel_disable_sagv(struct drm_i915_private *dev_priv)
3138 {
3139         int ret;
3140
3141         if (!intel_has_sagv(dev_priv))
3142                 return 0;
3143
3144         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3145                 return 0;
3146
3147         DRM_DEBUG_KMS("Disabling the SAGV\n");
3148         mutex_lock(&dev_priv->rps.hw_lock);
3149
3150         /* bspec says to keep retrying for at least 1 ms */
3151         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3152                                 GEN9_SAGV_DISABLE,
3153                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3154                                 1);
3155         mutex_unlock(&dev_priv->rps.hw_lock);
3156
3157         /*
3158          * Some skl systems, pre-release machines in particular,
3159          * don't actually have an SAGV.
3160          */
3161         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3162                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3163                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3164                 return 0;
3165         } else if (ret < 0) {
3166                 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
3167                 return ret;
3168         }
3169
3170         dev_priv->sagv_status = I915_SAGV_DISABLED;
3171         return 0;
3172 }
3173
3174 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3175 {
3176         struct drm_device *dev = state->dev;
3177         struct drm_i915_private *dev_priv = to_i915(dev);
3178         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3179         struct intel_crtc *crtc;
3180         struct intel_plane *plane;
3181         struct intel_crtc_state *cstate;
3182         enum pipe pipe;
3183         int level, latency;
3184
3185         if (!intel_has_sagv(dev_priv))
3186                 return false;
3187
3188         /*
3189          * SKL workaround: bspec recommends we disable the SAGV when we have
3190          * more then one pipe enabled
3191          *
3192          * If there are no active CRTCs, no additional checks need be performed
3193          */
3194         if (hweight32(intel_state->active_crtcs) == 0)
3195                 return true;
3196         else if (hweight32(intel_state->active_crtcs) > 1)
3197                 return false;
3198
3199         /* Since we're now guaranteed to only have one active CRTC... */
3200         pipe = ffs(intel_state->active_crtcs) - 1;
3201         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3202         cstate = to_intel_crtc_state(crtc->base.state);
3203
3204         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3205                 return false;
3206
3207         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3208                 struct skl_plane_wm *wm =
3209                         &cstate->wm.skl.optimal.planes[plane->id];
3210
3211                 /* Skip this plane if it's not enabled */
3212                 if (!wm->wm[0].plane_en)
3213                         continue;
3214
3215                 /* Find the highest enabled wm level for this plane */
3216                 for (level = ilk_wm_max_level(dev_priv);
3217                      !wm->wm[level].plane_en; --level)
3218                      { }
3219
3220                 latency = dev_priv->wm.skl_latency[level];
3221
3222                 if (skl_needs_memory_bw_wa(intel_state) &&
3223                     plane->base.state->fb->modifier ==
3224                     I915_FORMAT_MOD_X_TILED)
3225                         latency += 15;
3226
3227                 /*
3228                  * If any of the planes on this pipe don't enable wm levels
3229                  * that incur memory latencies higher then 30µs we can't enable
3230                  * the SAGV
3231                  */
3232                 if (latency < SKL_SAGV_BLOCK_TIME)
3233                         return false;
3234         }
3235
3236         return true;
3237 }
3238
3239 static void
3240 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3241                                    const struct intel_crtc_state *cstate,
3242                                    struct skl_ddb_entry *alloc, /* out */
3243                                    int *num_active /* out */)
3244 {
3245         struct drm_atomic_state *state = cstate->base.state;
3246         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3247         struct drm_i915_private *dev_priv = to_i915(dev);
3248         struct drm_crtc *for_crtc = cstate->base.crtc;
3249         unsigned int pipe_size, ddb_size;
3250         int nth_active_pipe;
3251
3252         if (WARN_ON(!state) || !cstate->base.active) {
3253                 alloc->start = 0;
3254                 alloc->end = 0;
3255                 *num_active = hweight32(dev_priv->active_crtcs);
3256                 return;
3257         }
3258
3259         if (intel_state->active_pipe_changes)
3260                 *num_active = hweight32(intel_state->active_crtcs);
3261         else
3262                 *num_active = hweight32(dev_priv->active_crtcs);
3263
3264         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3265         WARN_ON(ddb_size == 0);
3266
3267         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3268
3269         /*
3270          * If the state doesn't change the active CRTC's, then there's
3271          * no need to recalculate; the existing pipe allocation limits
3272          * should remain unchanged.  Note that we're safe from racing
3273          * commits since any racing commit that changes the active CRTC
3274          * list would need to grab _all_ crtc locks, including the one
3275          * we currently hold.
3276          */
3277         if (!intel_state->active_pipe_changes) {
3278                 /*
3279                  * alloc may be cleared by clear_intel_crtc_state,
3280                  * copy from old state to be sure
3281                  */
3282                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3283                 return;
3284         }
3285
3286         nth_active_pipe = hweight32(intel_state->active_crtcs &
3287                                     (drm_crtc_mask(for_crtc) - 1));
3288         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3289         alloc->start = nth_active_pipe * ddb_size / *num_active;
3290         alloc->end = alloc->start + pipe_size;
3291 }
3292
3293 static unsigned int skl_cursor_allocation(int num_active)
3294 {
3295         if (num_active == 1)
3296                 return 32;
3297
3298         return 8;
3299 }
3300
3301 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3302 {
3303         entry->start = reg & 0x3ff;
3304         entry->end = (reg >> 16) & 0x3ff;
3305         if (entry->end)
3306                 entry->end += 1;
3307 }
3308
3309 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3310                           struct skl_ddb_allocation *ddb /* out */)
3311 {
3312         struct intel_crtc *crtc;
3313
3314         memset(ddb, 0, sizeof(*ddb));
3315
3316         for_each_intel_crtc(&dev_priv->drm, crtc) {
3317                 enum intel_display_power_domain power_domain;
3318                 enum plane_id plane_id;
3319                 enum pipe pipe = crtc->pipe;
3320
3321                 power_domain = POWER_DOMAIN_PIPE(pipe);
3322                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3323                         continue;
3324
3325                 for_each_plane_id_on_crtc(crtc, plane_id) {
3326                         u32 val;
3327
3328                         if (plane_id != PLANE_CURSOR)
3329                                 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3330                         else
3331                                 val = I915_READ(CUR_BUF_CFG(pipe));
3332
3333                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3334                 }
3335
3336                 intel_display_power_put(dev_priv, power_domain);
3337         }
3338 }
3339
3340 /*
3341  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3342  * The bspec defines downscale amount as:
3343  *
3344  * """
3345  * Horizontal down scale amount = maximum[1, Horizontal source size /
3346  *                                           Horizontal destination size]
3347  * Vertical down scale amount = maximum[1, Vertical source size /
3348  *                                         Vertical destination size]
3349  * Total down scale amount = Horizontal down scale amount *
3350  *                           Vertical down scale amount
3351  * """
3352  *
3353  * Return value is provided in 16.16 fixed point form to retain fractional part.
3354  * Caller should take care of dividing & rounding off the value.
3355  */
3356 static uint32_t
3357 skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
3358                            const struct intel_plane_state *pstate)
3359 {
3360         struct intel_plane *plane = to_intel_plane(pstate->base.plane);
3361         uint32_t downscale_h, downscale_w;
3362         uint32_t src_w, src_h, dst_w, dst_h;
3363
3364         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
3365                 return DRM_PLANE_HELPER_NO_SCALING;
3366
3367         /* n.b., src is 16.16 fixed point, dst is whole integer */
3368         if (plane->id == PLANE_CURSOR) {
3369                 src_w = pstate->base.src_w;
3370                 src_h = pstate->base.src_h;
3371                 dst_w = pstate->base.crtc_w;
3372                 dst_h = pstate->base.crtc_h;
3373         } else {
3374                 src_w = drm_rect_width(&pstate->base.src);
3375                 src_h = drm_rect_height(&pstate->base.src);
3376                 dst_w = drm_rect_width(&pstate->base.dst);
3377                 dst_h = drm_rect_height(&pstate->base.dst);
3378         }
3379
3380         if (drm_rotation_90_or_270(pstate->base.rotation))
3381                 swap(dst_w, dst_h);
3382
3383         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3384         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3385
3386         /* Provide result in 16.16 fixed point */
3387         return (uint64_t)downscale_w * downscale_h >> 16;
3388 }
3389
3390 static unsigned int
3391 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3392                              const struct drm_plane_state *pstate,
3393                              int y)
3394 {
3395         struct intel_plane *plane = to_intel_plane(pstate->plane);
3396         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3397         uint32_t down_scale_amount, data_rate;
3398         uint32_t width = 0, height = 0;
3399         struct drm_framebuffer *fb;
3400         u32 format;
3401
3402         if (!intel_pstate->base.visible)
3403                 return 0;
3404
3405         fb = pstate->fb;
3406         format = fb->format->format;
3407
3408         if (plane->id == PLANE_CURSOR)
3409                 return 0;
3410         if (y && format != DRM_FORMAT_NV12)
3411                 return 0;
3412
3413         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3414         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3415
3416         if (drm_rotation_90_or_270(pstate->rotation))
3417                 swap(width, height);
3418
3419         /* for planar format */
3420         if (format == DRM_FORMAT_NV12) {
3421                 if (y)  /* y-plane data rate */
3422                         data_rate = width * height *
3423                                 fb->format->cpp[0];
3424                 else    /* uv-plane data rate */
3425                         data_rate = (width / 2) * (height / 2) *
3426                                 fb->format->cpp[1];
3427         } else {
3428                 /* for packed formats */
3429                 data_rate = width * height * fb->format->cpp[0];
3430         }
3431
3432         down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
3433
3434         return (uint64_t)data_rate * down_scale_amount >> 16;
3435 }
3436
3437 /*
3438  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3439  * a 8192x4096@32bpp framebuffer:
3440  *   3 * 4096 * 8192  * 4 < 2^32
3441  */
3442 static unsigned int
3443 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3444                                  unsigned *plane_data_rate,
3445                                  unsigned *plane_y_data_rate)
3446 {
3447         struct drm_crtc_state *cstate = &intel_cstate->base;
3448         struct drm_atomic_state *state = cstate->state;
3449         struct drm_plane *plane;
3450         const struct drm_plane_state *pstate;
3451         unsigned int total_data_rate = 0;
3452
3453         if (WARN_ON(!state))
3454                 return 0;
3455
3456         /* Calculate and cache data rate for each plane */
3457         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3458                 enum plane_id plane_id = to_intel_plane(plane)->id;
3459                 unsigned int rate;
3460
3461                 /* packed/uv */
3462                 rate = skl_plane_relative_data_rate(intel_cstate,
3463                                                     pstate, 0);
3464                 plane_data_rate[plane_id] = rate;
3465
3466                 total_data_rate += rate;
3467
3468                 /* y-plane */
3469                 rate = skl_plane_relative_data_rate(intel_cstate,
3470                                                     pstate, 1);
3471                 plane_y_data_rate[plane_id] = rate;
3472
3473                 total_data_rate += rate;
3474         }
3475
3476         return total_data_rate;
3477 }
3478
3479 static uint16_t
3480 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3481                   const int y)
3482 {
3483         struct drm_framebuffer *fb = pstate->fb;
3484         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3485         uint32_t src_w, src_h;
3486         uint32_t min_scanlines = 8;
3487         uint8_t plane_bpp;
3488
3489         if (WARN_ON(!fb))
3490                 return 0;
3491
3492         /* For packed formats, no y-plane, return 0 */
3493         if (y && fb->format->format != DRM_FORMAT_NV12)
3494                 return 0;
3495
3496         /* For Non Y-tile return 8-blocks */
3497         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3498             fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3499                 return 8;
3500
3501         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3502         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3503
3504         if (drm_rotation_90_or_270(pstate->rotation))
3505                 swap(src_w, src_h);
3506
3507         /* Halve UV plane width and height for NV12 */
3508         if (fb->format->format == DRM_FORMAT_NV12 && !y) {
3509                 src_w /= 2;
3510                 src_h /= 2;
3511         }
3512
3513         if (fb->format->format == DRM_FORMAT_NV12 && !y)
3514                 plane_bpp = fb->format->cpp[1];
3515         else
3516                 plane_bpp = fb->format->cpp[0];
3517
3518         if (drm_rotation_90_or_270(pstate->rotation)) {
3519                 switch (plane_bpp) {
3520                 case 1:
3521                         min_scanlines = 32;
3522                         break;
3523                 case 2:
3524                         min_scanlines = 16;
3525                         break;
3526                 case 4:
3527                         min_scanlines = 8;
3528                         break;
3529                 case 8:
3530                         min_scanlines = 4;
3531                         break;
3532                 default:
3533                         WARN(1, "Unsupported pixel depth %u for rotation",
3534                              plane_bpp);
3535                         min_scanlines = 32;
3536                 }
3537         }
3538
3539         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3540 }
3541
3542 static void
3543 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3544                  uint16_t *minimum, uint16_t *y_minimum)
3545 {
3546         const struct drm_plane_state *pstate;
3547         struct drm_plane *plane;
3548
3549         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3550                 enum plane_id plane_id = to_intel_plane(plane)->id;
3551
3552                 if (plane_id == PLANE_CURSOR)
3553                         continue;
3554
3555                 if (!pstate->visible)
3556                         continue;
3557
3558                 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
3559                 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
3560         }
3561
3562         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3563 }
3564
3565 static int
3566 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3567                       struct skl_ddb_allocation *ddb /* out */)
3568 {
3569         struct drm_atomic_state *state = cstate->base.state;
3570         struct drm_crtc *crtc = cstate->base.crtc;
3571         struct drm_device *dev = crtc->dev;
3572         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3573         enum pipe pipe = intel_crtc->pipe;
3574         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3575         uint16_t alloc_size, start;
3576         uint16_t minimum[I915_MAX_PLANES] = {};
3577         uint16_t y_minimum[I915_MAX_PLANES] = {};
3578         unsigned int total_data_rate;
3579         enum plane_id plane_id;
3580         int num_active;
3581         unsigned plane_data_rate[I915_MAX_PLANES] = {};
3582         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3583
3584         /* Clear the partitioning for disabled planes. */
3585         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3586         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3587
3588         if (WARN_ON(!state))
3589                 return 0;
3590
3591         if (!cstate->base.active) {
3592                 alloc->start = alloc->end = 0;
3593                 return 0;
3594         }
3595
3596         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3597         alloc_size = skl_ddb_entry_size(alloc);
3598         if (alloc_size == 0) {
3599                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3600                 return 0;
3601         }
3602
3603         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3604
3605         /*
3606          * 1. Allocate the mininum required blocks for each active plane
3607          * and allocate the cursor, it doesn't require extra allocation
3608          * proportional to the data rate.
3609          */
3610
3611         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3612                 alloc_size -= minimum[plane_id];
3613                 alloc_size -= y_minimum[plane_id];
3614         }
3615
3616         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3617         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3618
3619         /*
3620          * 2. Distribute the remaining space in proportion to the amount of
3621          * data each plane needs to fetch from memory.
3622          *
3623          * FIXME: we may not allocate every single block here.
3624          */
3625         total_data_rate = skl_get_total_relative_data_rate(cstate,
3626                                                            plane_data_rate,
3627                                                            plane_y_data_rate);
3628         if (total_data_rate == 0)
3629                 return 0;
3630
3631         start = alloc->start;
3632         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3633                 unsigned int data_rate, y_data_rate;
3634                 uint16_t plane_blocks, y_plane_blocks = 0;
3635
3636                 if (plane_id == PLANE_CURSOR)
3637                         continue;
3638
3639                 data_rate = plane_data_rate[plane_id];
3640
3641                 /*
3642                  * allocation for (packed formats) or (uv-plane part of planar format):
3643                  * promote the expression to 64 bits to avoid overflowing, the
3644                  * result is < available as data_rate / total_data_rate < 1
3645                  */
3646                 plane_blocks = minimum[plane_id];
3647                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3648                                         total_data_rate);
3649
3650                 /* Leave disabled planes at (0,0) */
3651                 if (data_rate) {
3652                         ddb->plane[pipe][plane_id].start = start;
3653                         ddb->plane[pipe][plane_id].end = start + plane_blocks;
3654                 }
3655
3656                 start += plane_blocks;
3657
3658                 /*
3659                  * allocation for y_plane part of planar format:
3660                  */
3661                 y_data_rate = plane_y_data_rate[plane_id];
3662
3663                 y_plane_blocks = y_minimum[plane_id];
3664                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3665                                         total_data_rate);
3666
3667                 if (y_data_rate) {
3668                         ddb->y_plane[pipe][plane_id].start = start;
3669                         ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
3670                 }
3671
3672                 start += y_plane_blocks;
3673         }
3674
3675         return 0;
3676 }
3677
3678 /*
3679  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3680  * for the read latency) and cpp should always be <= 8, so that
3681  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3682  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3683 */
3684 static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
3685                                          uint32_t latency)
3686 {
3687         uint32_t wm_intermediate_val;
3688         uint_fixed_16_16_t ret;
3689
3690         if (latency == 0)
3691                 return FP_16_16_MAX;
3692
3693         wm_intermediate_val = latency * pixel_rate * cpp;
3694         ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512);
3695         return ret;
3696 }
3697
3698 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
3699                         uint32_t pipe_htotal,
3700                         uint32_t latency,
3701                         uint_fixed_16_16_t plane_blocks_per_line)
3702 {
3703         uint32_t wm_intermediate_val;
3704         uint_fixed_16_16_t ret;
3705
3706         if (latency == 0)
3707                 return FP_16_16_MAX;
3708
3709         wm_intermediate_val = latency * pixel_rate;
3710         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
3711                                            pipe_htotal * 1000);
3712         ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line);
3713         return ret;
3714 }
3715
3716 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3717                                               struct intel_plane_state *pstate)
3718 {
3719         uint64_t adjusted_pixel_rate;
3720         uint64_t downscale_amount;
3721         uint64_t pixel_rate;
3722
3723         /* Shouldn't reach here on disabled planes... */
3724         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
3725                 return 0;
3726
3727         /*
3728          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3729          * with additional adjustments for plane-specific scaling.
3730          */
3731         adjusted_pixel_rate = cstate->pixel_rate;
3732         downscale_amount = skl_plane_downscale_amount(cstate, pstate);
3733
3734         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3735         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3736
3737         return pixel_rate;
3738 }
3739
3740 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3741                                 struct intel_crtc_state *cstate,
3742                                 struct intel_plane_state *intel_pstate,
3743                                 uint16_t ddb_allocation,
3744                                 int level,
3745                                 uint16_t *out_blocks, /* out */
3746                                 uint8_t *out_lines, /* out */
3747                                 bool *enabled /* out */)
3748 {
3749         struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
3750         struct drm_plane_state *pstate = &intel_pstate->base;
3751         struct drm_framebuffer *fb = pstate->fb;
3752         uint32_t latency = dev_priv->wm.skl_latency[level];
3753         uint_fixed_16_16_t method1, method2;
3754         uint_fixed_16_16_t plane_blocks_per_line;
3755         uint_fixed_16_16_t selected_result;
3756         uint32_t interm_pbpl;
3757         uint32_t plane_bytes_per_line;
3758         uint32_t res_blocks, res_lines;
3759         uint8_t cpp;
3760         uint32_t width = 0, height = 0;
3761         uint32_t plane_pixel_rate;
3762         uint_fixed_16_16_t y_tile_minimum;
3763         uint32_t y_min_scanlines;
3764         struct intel_atomic_state *state =
3765                 to_intel_atomic_state(cstate->base.state);
3766         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3767         bool y_tiled, x_tiled;
3768
3769         if (latency == 0 ||
3770             !intel_wm_plane_visible(cstate, intel_pstate)) {
3771                 *enabled = false;
3772                 return 0;
3773         }
3774
3775         y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3776                   fb->modifier == I915_FORMAT_MOD_Yf_TILED;
3777         x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
3778
3779         /* Display WA #1141: kbl. */
3780         if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
3781                 latency += 4;
3782
3783         if (apply_memory_bw_wa && x_tiled)
3784                 latency += 15;
3785
3786         if (plane->id == PLANE_CURSOR) {
3787                 width = intel_pstate->base.crtc_w;
3788                 height = intel_pstate->base.crtc_h;
3789         } else {
3790                 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3791                 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3792         }
3793
3794         if (drm_rotation_90_or_270(pstate->rotation))
3795                 swap(width, height);
3796
3797         cpp = fb->format->cpp[0];
3798         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3799
3800         if (drm_rotation_90_or_270(pstate->rotation)) {
3801                 int cpp = (fb->format->format == DRM_FORMAT_NV12) ?
3802                         fb->format->cpp[1] :
3803                         fb->format->cpp[0];
3804
3805                 switch (cpp) {
3806                 case 1:
3807                         y_min_scanlines = 16;
3808                         break;
3809                 case 2:
3810                         y_min_scanlines = 8;
3811                         break;
3812                 case 4:
3813                         y_min_scanlines = 4;
3814                         break;
3815                 default:
3816                         MISSING_CASE(cpp);
3817                         return -EINVAL;
3818                 }
3819         } else {
3820                 y_min_scanlines = 4;
3821         }
3822
3823         if (apply_memory_bw_wa)
3824                 y_min_scanlines *= 2;
3825
3826         plane_bytes_per_line = width * cpp;
3827         if (y_tiled) {
3828                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
3829                                            y_min_scanlines, 512);
3830                 plane_blocks_per_line =
3831                       fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines);
3832         } else if (x_tiled) {
3833                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
3834                 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
3835         } else {
3836                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
3837                 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
3838         }
3839
3840         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3841         method2 = skl_wm_method2(plane_pixel_rate,
3842                                  cstate->base.adjusted_mode.crtc_htotal,
3843                                  latency,
3844                                  plane_blocks_per_line);
3845
3846         y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines,
3847                                              plane_blocks_per_line);
3848
3849         if (y_tiled) {
3850                 selected_result = max_fixed_16_16(method2, y_tile_minimum);
3851         } else {
3852                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3853                     (plane_bytes_per_line / 512 < 1))
3854                         selected_result = method2;
3855                 else if ((ddb_allocation /
3856                         fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
3857                         selected_result = min_fixed_16_16(method1, method2);
3858                 else
3859                         selected_result = method1;
3860         }
3861
3862         res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1;
3863         res_lines = DIV_ROUND_UP(selected_result.val,
3864                                  plane_blocks_per_line.val);
3865
3866         if (level >= 1 && level <= 7) {
3867                 if (y_tiled) {
3868                         res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
3869                         res_lines += y_min_scanlines;
3870                 } else {
3871                         res_blocks++;
3872                 }
3873         }
3874
3875         if (res_blocks >= ddb_allocation || res_lines > 31) {
3876                 *enabled = false;
3877
3878                 /*
3879                  * If there are no valid level 0 watermarks, then we can't
3880                  * support this display configuration.
3881                  */
3882                 if (level) {
3883                         return 0;
3884                 } else {
3885                         struct drm_plane *plane = pstate->plane;
3886
3887                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3888                         DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
3889                                       plane->base.id, plane->name,
3890                                       res_blocks, ddb_allocation, res_lines);
3891                         return -EINVAL;
3892                 }
3893         }
3894
3895         *out_blocks = res_blocks;
3896         *out_lines = res_lines;
3897         *enabled = true;
3898
3899         return 0;
3900 }
3901
3902 static int
3903 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3904                      struct skl_ddb_allocation *ddb,
3905                      struct intel_crtc_state *cstate,
3906                      struct intel_plane *intel_plane,
3907                      int level,
3908                      struct skl_wm_level *result)
3909 {
3910         struct drm_atomic_state *state = cstate->base.state;
3911         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3912         struct drm_plane *plane = &intel_plane->base;
3913         struct intel_plane_state *intel_pstate = NULL;
3914         uint16_t ddb_blocks;
3915         enum pipe pipe = intel_crtc->pipe;
3916         int ret;
3917
3918         if (state)
3919                 intel_pstate =
3920                         intel_atomic_get_existing_plane_state(state,
3921                                                               intel_plane);
3922
3923         /*
3924          * Note: If we start supporting multiple pending atomic commits against
3925          * the same planes/CRTC's in the future, plane->state will no longer be
3926          * the correct pre-state to use for the calculations here and we'll
3927          * need to change where we get the 'unchanged' plane data from.
3928          *
3929          * For now this is fine because we only allow one queued commit against
3930          * a CRTC.  Even if the plane isn't modified by this transaction and we
3931          * don't have a plane lock, we still have the CRTC's lock, so we know
3932          * that no other transactions are racing with us to update it.
3933          */
3934         if (!intel_pstate)
3935                 intel_pstate = to_intel_plane_state(plane->state);
3936
3937         WARN_ON(!intel_pstate->base.fb);
3938
3939         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
3940
3941         ret = skl_compute_plane_wm(dev_priv,
3942                                    cstate,
3943                                    intel_pstate,
3944                                    ddb_blocks,
3945                                    level,
3946                                    &result->plane_res_b,
3947                                    &result->plane_res_l,
3948                                    &result->plane_en);
3949         if (ret)
3950                 return ret;
3951
3952         return 0;
3953 }
3954
3955 static uint32_t
3956 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3957 {
3958         struct drm_atomic_state *state = cstate->base.state;
3959         struct drm_i915_private *dev_priv = to_i915(state->dev);
3960         uint32_t pixel_rate;
3961         uint32_t linetime_wm;
3962
3963         if (!cstate->base.active)
3964                 return 0;
3965
3966         pixel_rate = cstate->pixel_rate;
3967
3968         if (WARN_ON(pixel_rate == 0))
3969                 return 0;
3970
3971         linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
3972                                    1000, pixel_rate);
3973
3974         /* Display WA #1135: bxt. */
3975         if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
3976                 linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
3977
3978         return linetime_wm;
3979 }
3980
3981 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3982                                       struct skl_wm_level *trans_wm /* out */)
3983 {
3984         if (!cstate->base.active)
3985                 return;
3986
3987         /* Until we know more, just disable transition WMs */
3988         trans_wm->plane_en = false;
3989 }
3990
3991 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3992                              struct skl_ddb_allocation *ddb,
3993                              struct skl_pipe_wm *pipe_wm)
3994 {
3995         struct drm_device *dev = cstate->base.crtc->dev;
3996         const struct drm_i915_private *dev_priv = to_i915(dev);
3997         struct intel_plane *intel_plane;
3998         struct skl_plane_wm *wm;
3999         int level, max_level = ilk_wm_max_level(dev_priv);
4000         int ret;
4001
4002         /*
4003          * We'll only calculate watermarks for planes that are actually
4004          * enabled, so make sure all other planes are set as disabled.
4005          */
4006         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
4007
4008         for_each_intel_plane_mask(&dev_priv->drm,
4009                                   intel_plane,
4010                                   cstate->base.plane_mask) {
4011                 wm = &pipe_wm->planes[intel_plane->id];
4012
4013                 for (level = 0; level <= max_level; level++) {
4014                         ret = skl_compute_wm_level(dev_priv, ddb, cstate,
4015                                                    intel_plane, level,
4016                                                    &wm->wm[level]);
4017                         if (ret)
4018                                 return ret;
4019                 }
4020                 skl_compute_transition_wm(cstate, &wm->trans_wm);
4021         }
4022         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
4023
4024         return 0;
4025 }
4026
4027 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
4028                                 i915_reg_t reg,
4029                                 const struct skl_ddb_entry *entry)
4030 {
4031         if (entry->end)
4032                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
4033         else
4034                 I915_WRITE(reg, 0);
4035 }
4036
4037 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
4038                                i915_reg_t reg,
4039                                const struct skl_wm_level *level)
4040 {
4041         uint32_t val = 0;
4042
4043         if (level->plane_en) {
4044                 val |= PLANE_WM_EN;
4045                 val |= level->plane_res_b;
4046                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
4047         }
4048
4049         I915_WRITE(reg, val);
4050 }
4051
4052 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
4053                                const struct skl_plane_wm *wm,
4054                                const struct skl_ddb_allocation *ddb,
4055                                enum plane_id plane_id)
4056 {
4057         struct drm_crtc *crtc = &intel_crtc->base;
4058         struct drm_device *dev = crtc->dev;
4059         struct drm_i915_private *dev_priv = to_i915(dev);
4060         int level, max_level = ilk_wm_max_level(dev_priv);
4061         enum pipe pipe = intel_crtc->pipe;
4062
4063         for (level = 0; level <= max_level; level++) {
4064                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
4065                                    &wm->wm[level]);
4066         }
4067         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
4068                            &wm->trans_wm);
4069
4070         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4071                             &ddb->plane[pipe][plane_id]);
4072         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
4073                             &ddb->y_plane[pipe][plane_id]);
4074 }
4075
4076 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
4077                                 const struct skl_plane_wm *wm,
4078                                 const struct skl_ddb_allocation *ddb)
4079 {
4080         struct drm_crtc *crtc = &intel_crtc->base;
4081         struct drm_device *dev = crtc->dev;
4082         struct drm_i915_private *dev_priv = to_i915(dev);
4083         int level, max_level = ilk_wm_max_level(dev_priv);
4084         enum pipe pipe = intel_crtc->pipe;
4085
4086         for (level = 0; level <= max_level; level++) {
4087                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
4088                                    &wm->wm[level]);
4089         }
4090         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
4091
4092         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4093                             &ddb->plane[pipe][PLANE_CURSOR]);
4094 }
4095
4096 bool skl_wm_level_equals(const struct skl_wm_level *l1,
4097                          const struct skl_wm_level *l2)
4098 {
4099         if (l1->plane_en != l2->plane_en)
4100                 return false;
4101
4102         /* If both planes aren't enabled, the rest shouldn't matter */
4103         if (!l1->plane_en)
4104                 return true;
4105
4106         return (l1->plane_res_l == l2->plane_res_l &&
4107                 l1->plane_res_b == l2->plane_res_b);
4108 }
4109
4110 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
4111                                            const struct skl_ddb_entry *b)
4112 {
4113         return a->start < b->end && b->start < a->end;
4114 }
4115
4116 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
4117                                  const struct skl_ddb_entry *ddb,
4118                                  int ignore)
4119 {
4120         int i;
4121
4122         for (i = 0; i < I915_MAX_PIPES; i++)
4123                 if (i != ignore && entries[i] &&
4124                     skl_ddb_entries_overlap(ddb, entries[i]))
4125                         return true;
4126
4127         return false;
4128 }
4129
4130 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
4131                               const struct skl_pipe_wm *old_pipe_wm,
4132                               struct skl_pipe_wm *pipe_wm, /* out */
4133                               struct skl_ddb_allocation *ddb, /* out */
4134                               bool *changed /* out */)
4135 {
4136         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
4137         int ret;
4138
4139         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
4140         if (ret)
4141                 return ret;
4142
4143         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
4144                 *changed = false;
4145         else
4146                 *changed = true;
4147
4148         return 0;
4149 }
4150
4151 static uint32_t
4152 pipes_modified(struct drm_atomic_state *state)
4153 {
4154         struct drm_crtc *crtc;
4155         struct drm_crtc_state *cstate;
4156         uint32_t i, ret = 0;
4157
4158         for_each_new_crtc_in_state(state, crtc, cstate, i)
4159                 ret |= drm_crtc_mask(crtc);
4160
4161         return ret;
4162 }
4163
4164 static int
4165 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
4166 {
4167         struct drm_atomic_state *state = cstate->base.state;
4168         struct drm_device *dev = state->dev;
4169         struct drm_crtc *crtc = cstate->base.crtc;
4170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4171         struct drm_i915_private *dev_priv = to_i915(dev);
4172         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4173         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4174         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
4175         struct drm_plane_state *plane_state;
4176         struct drm_plane *plane;
4177         enum pipe pipe = intel_crtc->pipe;
4178
4179         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
4180
4181         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
4182                 enum plane_id plane_id = to_intel_plane(plane)->id;
4183
4184                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
4185                                         &new_ddb->plane[pipe][plane_id]) &&
4186                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
4187                                         &new_ddb->y_plane[pipe][plane_id]))
4188                         continue;
4189
4190                 plane_state = drm_atomic_get_plane_state(state, plane);
4191                 if (IS_ERR(plane_state))
4192                         return PTR_ERR(plane_state);
4193         }
4194
4195         return 0;
4196 }
4197
4198 static int
4199 skl_compute_ddb(struct drm_atomic_state *state)
4200 {
4201         struct drm_device *dev = state->dev;
4202         struct drm_i915_private *dev_priv = to_i915(dev);
4203         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4204         struct intel_crtc *intel_crtc;
4205         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4206         uint32_t realloc_pipes = pipes_modified(state);
4207         int ret;
4208
4209         /*
4210          * If this is our first atomic update following hardware readout,
4211          * we can't trust the DDB that the BIOS programmed for us.  Let's
4212          * pretend that all pipes switched active status so that we'll
4213          * ensure a full DDB recompute.
4214          */
4215         if (dev_priv->wm.distrust_bios_wm) {
4216                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4217                                        state->acquire_ctx);
4218                 if (ret)
4219                         return ret;
4220
4221                 intel_state->active_pipe_changes = ~0;
4222
4223                 /*
4224                  * We usually only initialize intel_state->active_crtcs if we
4225                  * we're doing a modeset; make sure this field is always
4226                  * initialized during the sanitization process that happens
4227                  * on the first commit too.
4228                  */
4229                 if (!intel_state->modeset)
4230                         intel_state->active_crtcs = dev_priv->active_crtcs;
4231         }
4232
4233         /*
4234          * If the modeset changes which CRTC's are active, we need to
4235          * recompute the DDB allocation for *all* active pipes, even
4236          * those that weren't otherwise being modified in any way by this
4237          * atomic commit.  Due to the shrinking of the per-pipe allocations
4238          * when new active CRTC's are added, it's possible for a pipe that
4239          * we were already using and aren't changing at all here to suddenly
4240          * become invalid if its DDB needs exceeds its new allocation.
4241          *
4242          * Note that if we wind up doing a full DDB recompute, we can't let
4243          * any other display updates race with this transaction, so we need
4244          * to grab the lock on *all* CRTC's.
4245          */
4246         if (intel_state->active_pipe_changes) {
4247                 realloc_pipes = ~0;
4248                 intel_state->wm_results.dirty_pipes = ~0;
4249         }
4250
4251         /*
4252          * We're not recomputing for the pipes not included in the commit, so
4253          * make sure we start with the current state.
4254          */
4255         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4256
4257         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4258                 struct intel_crtc_state *cstate;
4259
4260                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4261                 if (IS_ERR(cstate))
4262                         return PTR_ERR(cstate);
4263
4264                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4265                 if (ret)
4266                         return ret;
4267
4268                 ret = skl_ddb_add_affected_planes(cstate);
4269                 if (ret)
4270                         return ret;
4271         }
4272
4273         return 0;
4274 }
4275
4276 static void
4277 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4278                      struct skl_wm_values *src,
4279                      enum pipe pipe)
4280 {
4281         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4282                sizeof(dst->ddb.y_plane[pipe]));
4283         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4284                sizeof(dst->ddb.plane[pipe]));
4285 }
4286
4287 static void
4288 skl_print_wm_changes(const struct drm_atomic_state *state)
4289 {
4290         const struct drm_device *dev = state->dev;
4291         const struct drm_i915_private *dev_priv = to_i915(dev);
4292         const struct intel_atomic_state *intel_state =
4293                 to_intel_atomic_state(state);
4294         const struct drm_crtc *crtc;
4295         const struct drm_crtc_state *cstate;
4296         const struct intel_plane *intel_plane;
4297         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4298         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4299         int i;
4300
4301         for_each_new_crtc_in_state(state, crtc, cstate, i) {
4302                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4303                 enum pipe pipe = intel_crtc->pipe;
4304
4305                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4306                         enum plane_id plane_id = intel_plane->id;
4307                         const struct skl_ddb_entry *old, *new;
4308
4309                         old = &old_ddb->plane[pipe][plane_id];
4310                         new = &new_ddb->plane[pipe][plane_id];
4311
4312                         if (skl_ddb_entry_equal(old, new))
4313                                 continue;
4314
4315                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4316                                          intel_plane->base.base.id,
4317                                          intel_plane->base.name,
4318                                          old->start, old->end,
4319                                          new->start, new->end);
4320                 }
4321         }
4322 }
4323
4324 static int
4325 skl_compute_wm(struct drm_atomic_state *state)
4326 {
4327         struct drm_crtc *crtc;
4328         struct drm_crtc_state *cstate;
4329         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4330         struct skl_wm_values *results = &intel_state->wm_results;
4331         struct skl_pipe_wm *pipe_wm;
4332         bool changed = false;
4333         int ret, i;
4334
4335         /*
4336          * If this transaction isn't actually touching any CRTC's, don't
4337          * bother with watermark calculation.  Note that if we pass this
4338          * test, we're guaranteed to hold at least one CRTC state mutex,
4339          * which means we can safely use values like dev_priv->active_crtcs
4340          * since any racing commits that want to update them would need to
4341          * hold _all_ CRTC state mutexes.
4342          */
4343         for_each_new_crtc_in_state(state, crtc, cstate, i)
4344                 changed = true;
4345         if (!changed)
4346                 return 0;
4347
4348         /* Clear all dirty flags */
4349         results->dirty_pipes = 0;
4350
4351         ret = skl_compute_ddb(state);
4352         if (ret)
4353                 return ret;
4354
4355         /*
4356          * Calculate WM's for all pipes that are part of this transaction.
4357          * Note that the DDB allocation above may have added more CRTC's that
4358          * weren't otherwise being modified (and set bits in dirty_pipes) if
4359          * pipe allocations had to change.
4360          *
4361          * FIXME:  Now that we're doing this in the atomic check phase, we
4362          * should allow skl_update_pipe_wm() to return failure in cases where
4363          * no suitable watermark values can be found.
4364          */
4365         for_each_new_crtc_in_state(state, crtc, cstate, i) {
4366                 struct intel_crtc_state *intel_cstate =
4367                         to_intel_crtc_state(cstate);
4368                 const struct skl_pipe_wm *old_pipe_wm =
4369                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4370
4371                 pipe_wm = &intel_cstate->wm.skl.optimal;
4372                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4373                                          &results->ddb, &changed);
4374                 if (ret)
4375                         return ret;
4376
4377                 if (changed)
4378                         results->dirty_pipes |= drm_crtc_mask(crtc);
4379
4380                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4381                         /* This pipe's WM's did not change */
4382                         continue;
4383
4384                 intel_cstate->update_wm_pre = true;
4385         }
4386
4387         skl_print_wm_changes(state);
4388
4389         return 0;
4390 }
4391
4392 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4393                                       struct intel_crtc_state *cstate)
4394 {
4395         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4396         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4397         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4398         const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
4399         enum pipe pipe = crtc->pipe;
4400         enum plane_id plane_id;
4401
4402         if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4403                 return;
4404
4405         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
4406
4407         for_each_plane_id_on_crtc(crtc, plane_id) {
4408                 if (plane_id != PLANE_CURSOR)
4409                         skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
4410                                            ddb, plane_id);
4411                 else
4412                         skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
4413                                             ddb);
4414         }
4415 }
4416
4417 static void skl_initial_wm(struct intel_atomic_state *state,
4418                            struct intel_crtc_state *cstate)
4419 {
4420         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4421         struct drm_device *dev = intel_crtc->base.dev;
4422         struct drm_i915_private *dev_priv = to_i915(dev);
4423         struct skl_wm_values *results = &state->wm_results;
4424         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4425         enum pipe pipe = intel_crtc->pipe;
4426
4427         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4428                 return;
4429
4430         mutex_lock(&dev_priv->wm.wm_mutex);
4431
4432         if (cstate->base.active_changed)
4433                 skl_atomic_update_crtc_wm(state, cstate);
4434
4435         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4436
4437         mutex_unlock(&dev_priv->wm.wm_mutex);
4438 }
4439
4440 static void ilk_compute_wm_config(struct drm_device *dev,
4441                                   struct intel_wm_config *config)
4442 {
4443         struct intel_crtc *crtc;
4444
4445         /* Compute the currently _active_ config */
4446         for_each_intel_crtc(dev, crtc) {
4447                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4448
4449                 if (!wm->pipe_enabled)
4450                         continue;
4451
4452                 config->sprites_enabled |= wm->sprites_enabled;
4453                 config->sprites_scaled |= wm->sprites_scaled;
4454                 config->num_pipes_active++;
4455         }
4456 }
4457
4458 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4459 {
4460         struct drm_device *dev = &dev_priv->drm;
4461         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4462         struct ilk_wm_maximums max;
4463         struct intel_wm_config config = {};
4464         struct ilk_wm_values results = {};
4465         enum intel_ddb_partitioning partitioning;
4466
4467         ilk_compute_wm_config(dev, &config);
4468
4469         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4470         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4471
4472         /* 5/6 split only in single pipe config on IVB+ */
4473         if (INTEL_GEN(dev_priv) >= 7 &&
4474             config.num_pipes_active == 1 && config.sprites_enabled) {
4475                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4476                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4477
4478                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4479         } else {
4480                 best_lp_wm = &lp_wm_1_2;
4481         }
4482
4483         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4484                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4485
4486         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4487
4488         ilk_write_wm_values(dev_priv, &results);
4489 }
4490
4491 static void ilk_initial_watermarks(struct intel_atomic_state *state,
4492                                    struct intel_crtc_state *cstate)
4493 {
4494         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4495         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4496
4497         mutex_lock(&dev_priv->wm.wm_mutex);
4498         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4499         ilk_program_watermarks(dev_priv);
4500         mutex_unlock(&dev_priv->wm.wm_mutex);
4501 }
4502
4503 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4504                                     struct intel_crtc_state *cstate)
4505 {
4506         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4507         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4508
4509         mutex_lock(&dev_priv->wm.wm_mutex);
4510         if (cstate->wm.need_postvbl_update) {
4511                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4512                 ilk_program_watermarks(dev_priv);
4513         }
4514         mutex_unlock(&dev_priv->wm.wm_mutex);
4515 }
4516
4517 static inline void skl_wm_level_from_reg_val(uint32_t val,
4518                                              struct skl_wm_level *level)
4519 {
4520         level->plane_en = val & PLANE_WM_EN;
4521         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4522         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4523                 PLANE_WM_LINES_MASK;
4524 }
4525
4526 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4527                               struct skl_pipe_wm *out)
4528 {
4529         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4531         enum pipe pipe = intel_crtc->pipe;
4532         int level, max_level;
4533         enum plane_id plane_id;
4534         uint32_t val;
4535
4536         max_level = ilk_wm_max_level(dev_priv);
4537
4538         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4539                 struct skl_plane_wm *wm = &out->planes[plane_id];
4540
4541                 for (level = 0; level <= max_level; level++) {
4542                         if (plane_id != PLANE_CURSOR)
4543                                 val = I915_READ(PLANE_WM(pipe, plane_id, level));
4544                         else
4545                                 val = I915_READ(CUR_WM(pipe, level));
4546
4547                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
4548                 }
4549
4550                 if (plane_id != PLANE_CURSOR)
4551                         val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
4552                 else
4553                         val = I915_READ(CUR_WM_TRANS(pipe));
4554
4555                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4556         }
4557
4558         if (!intel_crtc->active)
4559                 return;
4560
4561         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4562 }
4563
4564 void skl_wm_get_hw_state(struct drm_device *dev)
4565 {
4566         struct drm_i915_private *dev_priv = to_i915(dev);
4567         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4568         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4569         struct drm_crtc *crtc;
4570         struct intel_crtc *intel_crtc;
4571         struct intel_crtc_state *cstate;
4572
4573         skl_ddb_get_hw_state(dev_priv, ddb);
4574         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4575                 intel_crtc = to_intel_crtc(crtc);
4576                 cstate = to_intel_crtc_state(crtc->state);
4577
4578                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4579
4580                 if (intel_crtc->active)
4581                         hw->dirty_pipes |= drm_crtc_mask(crtc);
4582         }
4583
4584         if (dev_priv->active_crtcs) {
4585                 /* Fully recompute DDB on first atomic commit */
4586                 dev_priv->wm.distrust_bios_wm = true;
4587         } else {
4588                 /* Easy/common case; just sanitize DDB now if everything off */
4589                 memset(ddb, 0, sizeof(*ddb));
4590         }
4591 }
4592
4593 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4594 {
4595         struct drm_device *dev = crtc->dev;
4596         struct drm_i915_private *dev_priv = to_i915(dev);
4597         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4598         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4599         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4600         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4601         enum pipe pipe = intel_crtc->pipe;
4602         static const i915_reg_t wm0_pipe_reg[] = {
4603                 [PIPE_A] = WM0_PIPEA_ILK,
4604                 [PIPE_B] = WM0_PIPEB_ILK,
4605                 [PIPE_C] = WM0_PIPEC_IVB,
4606         };
4607
4608         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4609         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4610                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4611
4612         memset(active, 0, sizeof(*active));
4613
4614         active->pipe_enabled = intel_crtc->active;
4615
4616         if (active->pipe_enabled) {
4617                 u32 tmp = hw->wm_pipe[pipe];
4618
4619                 /*
4620                  * For active pipes LP0 watermark is marked as
4621                  * enabled, and LP1+ watermaks as disabled since
4622                  * we can't really reverse compute them in case
4623                  * multiple pipes are active.
4624                  */
4625                 active->wm[0].enable = true;
4626                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4627                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4628                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4629                 active->linetime = hw->wm_linetime[pipe];
4630         } else {
4631                 int level, max_level = ilk_wm_max_level(dev_priv);
4632
4633                 /*
4634                  * For inactive pipes, all watermark levels
4635                  * should be marked as enabled but zeroed,
4636                  * which is what we'd compute them to.
4637                  */
4638                 for (level = 0; level <= max_level; level++)
4639                         active->wm[level].enable = true;
4640         }
4641
4642         intel_crtc->wm.active.ilk = *active;
4643 }
4644
4645 #define _FW_WM(value, plane) \
4646         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4647 #define _FW_WM_VLV(value, plane) \
4648         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4649
4650 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4651                                struct vlv_wm_values *wm)
4652 {
4653         enum pipe pipe;
4654         uint32_t tmp;
4655
4656         for_each_pipe(dev_priv, pipe) {
4657                 tmp = I915_READ(VLV_DDL(pipe));
4658
4659                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
4660                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4661                 wm->ddl[pipe].plane[PLANE_CURSOR] =
4662                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4663                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
4664                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4665                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
4666                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4667         }
4668
4669         tmp = I915_READ(DSPFW1);
4670         wm->sr.plane = _FW_WM(tmp, SR);
4671         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
4672         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
4673         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
4674
4675         tmp = I915_READ(DSPFW2);
4676         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
4677         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
4678         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
4679
4680         tmp = I915_READ(DSPFW3);
4681         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4682
4683         if (IS_CHERRYVIEW(dev_priv)) {
4684                 tmp = I915_READ(DSPFW7_CHV);
4685                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4686                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
4687
4688                 tmp = I915_READ(DSPFW8_CHV);
4689                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
4690                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
4691
4692                 tmp = I915_READ(DSPFW9_CHV);
4693                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
4694                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
4695
4696                 tmp = I915_READ(DSPHOWM);
4697                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4698                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4699                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4700                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
4701                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4702                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4703                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4704                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4705                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4706                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
4707         } else {
4708                 tmp = I915_READ(DSPFW7);
4709                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4710                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
4711
4712                 tmp = I915_READ(DSPHOWM);
4713                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4714                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4715                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4716                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4717                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4718                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4719                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
4720         }
4721 }
4722
4723 #undef _FW_WM
4724 #undef _FW_WM_VLV
4725
4726 void vlv_wm_get_hw_state(struct drm_device *dev)
4727 {
4728         struct drm_i915_private *dev_priv = to_i915(dev);
4729         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4730         struct intel_crtc *crtc;
4731         u32 val;
4732
4733         vlv_read_wm_values(dev_priv, wm);
4734
4735         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4736         wm->level = VLV_WM_LEVEL_PM2;
4737
4738         if (IS_CHERRYVIEW(dev_priv)) {
4739                 mutex_lock(&dev_priv->rps.hw_lock);
4740
4741                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4742                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4743                         wm->level = VLV_WM_LEVEL_PM5;
4744
4745                 /*
4746                  * If DDR DVFS is disabled in the BIOS, Punit
4747                  * will never ack the request. So if that happens
4748                  * assume we don't have to enable/disable DDR DVFS
4749                  * dynamically. To test that just set the REQ_ACK
4750                  * bit to poke the Punit, but don't change the
4751                  * HIGH/LOW bits so that we don't actually change
4752                  * the current state.
4753                  */
4754                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4755                 val |= FORCE_DDR_FREQ_REQ_ACK;
4756                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4757
4758                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4759                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4760                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4761                                       "assuming DDR DVFS is disabled\n");
4762                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4763                 } else {
4764                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4765                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4766                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4767                 }
4768
4769                 mutex_unlock(&dev_priv->rps.hw_lock);
4770         }
4771
4772         for_each_intel_crtc(dev, crtc) {
4773                 struct intel_crtc_state *crtc_state =
4774                         to_intel_crtc_state(crtc->base.state);
4775                 struct vlv_wm_state *active = &crtc->wm.active.vlv;
4776                 const struct vlv_fifo_state *fifo_state =
4777                         &crtc_state->wm.vlv.fifo_state;
4778                 enum pipe pipe = crtc->pipe;
4779                 enum plane_id plane_id;
4780                 int level;
4781
4782                 vlv_get_fifo_size(crtc_state);
4783
4784                 active->num_levels = wm->level + 1;
4785                 active->cxsr = wm->cxsr;
4786
4787                 for (level = 0; level < active->num_levels; level++) {
4788                         struct vlv_pipe_wm *raw =
4789                                 &crtc_state->wm.vlv.raw[level];
4790
4791                         active->sr[level].plane = wm->sr.plane;
4792                         active->sr[level].cursor = wm->sr.cursor;
4793
4794                         for_each_plane_id_on_crtc(crtc, plane_id) {
4795                                 active->wm[level].plane[plane_id] =
4796                                         wm->pipe[pipe].plane[plane_id];
4797
4798                                 raw->plane[plane_id] =
4799                                         vlv_invert_wm_value(active->wm[level].plane[plane_id],
4800                                                             fifo_state->plane[plane_id]);
4801                         }
4802                 }
4803
4804                 for_each_plane_id_on_crtc(crtc, plane_id)
4805                         vlv_raw_plane_wm_set(crtc_state, level,
4806                                              plane_id, USHRT_MAX);
4807                 vlv_invalidate_wms(crtc, active, level);
4808
4809                 crtc_state->wm.vlv.optimal = *active;
4810                 crtc_state->wm.vlv.intermediate = *active;
4811
4812                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4813                               pipe_name(pipe),
4814                               wm->pipe[pipe].plane[PLANE_PRIMARY],
4815                               wm->pipe[pipe].plane[PLANE_CURSOR],
4816                               wm->pipe[pipe].plane[PLANE_SPRITE0],
4817                               wm->pipe[pipe].plane[PLANE_SPRITE1]);
4818         }
4819
4820         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4821                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4822 }
4823
4824 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
4825 {
4826         struct intel_plane *plane;
4827         struct intel_crtc *crtc;
4828
4829         mutex_lock(&dev_priv->wm.wm_mutex);
4830
4831         for_each_intel_plane(&dev_priv->drm, plane) {
4832                 struct intel_crtc *crtc =
4833                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
4834                 struct intel_crtc_state *crtc_state =
4835                         to_intel_crtc_state(crtc->base.state);
4836                 struct intel_plane_state *plane_state =
4837                         to_intel_plane_state(plane->base.state);
4838                 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
4839                 const struct vlv_fifo_state *fifo_state =
4840                         &crtc_state->wm.vlv.fifo_state;
4841                 enum plane_id plane_id = plane->id;
4842                 int level;
4843
4844                 if (plane_state->base.visible)
4845                         continue;
4846
4847                 for (level = 0; level < wm_state->num_levels; level++) {
4848                         struct vlv_pipe_wm *raw =
4849                                 &crtc_state->wm.vlv.raw[level];
4850
4851                         raw->plane[plane_id] = 0;
4852
4853                         wm_state->wm[level].plane[plane_id] =
4854                                 vlv_invert_wm_value(raw->plane[plane_id],
4855                                                     fifo_state->plane[plane_id]);
4856                 }
4857         }
4858
4859         for_each_intel_crtc(&dev_priv->drm, crtc) {
4860                 struct intel_crtc_state *crtc_state =
4861                         to_intel_crtc_state(crtc->base.state);
4862
4863                 crtc_state->wm.vlv.intermediate =
4864                         crtc_state->wm.vlv.optimal;
4865                 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
4866         }
4867
4868         vlv_program_watermarks(dev_priv);
4869
4870         mutex_unlock(&dev_priv->wm.wm_mutex);
4871 }
4872
4873 void ilk_wm_get_hw_state(struct drm_device *dev)
4874 {
4875         struct drm_i915_private *dev_priv = to_i915(dev);
4876         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4877         struct drm_crtc *crtc;
4878
4879         for_each_crtc(dev, crtc)
4880                 ilk_pipe_wm_get_hw_state(crtc);
4881
4882         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4883         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4884         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4885
4886         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4887         if (INTEL_GEN(dev_priv) >= 7) {
4888                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4889                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4890         }
4891
4892         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4893                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4894                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4895         else if (IS_IVYBRIDGE(dev_priv))
4896                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4897                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4898
4899         hw->enable_fbc_wm =
4900                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4901 }
4902
4903 /**
4904  * intel_update_watermarks - update FIFO watermark values based on current modes
4905  *
4906  * Calculate watermark values for the various WM regs based on current mode
4907  * and plane configuration.
4908  *
4909  * There are several cases to deal with here:
4910  *   - normal (i.e. non-self-refresh)
4911  *   - self-refresh (SR) mode
4912  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4913  *   - lines are small relative to FIFO size (buffer can hold more than 2
4914  *     lines), so need to account for TLB latency
4915  *
4916  *   The normal calculation is:
4917  *     watermark = dotclock * bytes per pixel * latency
4918  *   where latency is platform & configuration dependent (we assume pessimal
4919  *   values here).
4920  *
4921  *   The SR calculation is:
4922  *     watermark = (trunc(latency/line time)+1) * surface width *
4923  *       bytes per pixel
4924  *   where
4925  *     line time = htotal / dotclock
4926  *     surface width = hdisplay for normal plane and 64 for cursor
4927  *   and latency is assumed to be high, as above.
4928  *
4929  * The final value programmed to the register should always be rounded up,
4930  * and include an extra 2 entries to account for clock crossings.
4931  *
4932  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4933  * to set the non-SR watermarks to 8.
4934  */
4935 void intel_update_watermarks(struct intel_crtc *crtc)
4936 {
4937         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4938
4939         if (dev_priv->display.update_wm)
4940                 dev_priv->display.update_wm(crtc);
4941 }
4942
4943 /*
4944  * Lock protecting IPS related data structures
4945  */
4946 DEFINE_SPINLOCK(mchdev_lock);
4947
4948 /* Global for IPS driver to get at the current i915 device. Protected by
4949  * mchdev_lock. */
4950 static struct drm_i915_private *i915_mch_dev;
4951
4952 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4953 {
4954         u16 rgvswctl;
4955
4956         lockdep_assert_held(&mchdev_lock);
4957
4958         rgvswctl = I915_READ16(MEMSWCTL);
4959         if (rgvswctl & MEMCTL_CMD_STS) {
4960                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4961                 return false; /* still busy with another command */
4962         }
4963
4964         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4965                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4966         I915_WRITE16(MEMSWCTL, rgvswctl);
4967         POSTING_READ16(MEMSWCTL);
4968
4969         rgvswctl |= MEMCTL_CMD_STS;
4970         I915_WRITE16(MEMSWCTL, rgvswctl);
4971
4972         return true;
4973 }
4974
4975 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4976 {
4977         u32 rgvmodectl;
4978         u8 fmax, fmin, fstart, vstart;
4979
4980         spin_lock_irq(&mchdev_lock);
4981
4982         rgvmodectl = I915_READ(MEMMODECTL);
4983
4984         /* Enable temp reporting */
4985         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4986         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4987
4988         /* 100ms RC evaluation intervals */
4989         I915_WRITE(RCUPEI, 100000);
4990         I915_WRITE(RCDNEI, 100000);
4991
4992         /* Set max/min thresholds to 90ms and 80ms respectively */
4993         I915_WRITE(RCBMAXAVG, 90000);
4994         I915_WRITE(RCBMINAVG, 80000);
4995
4996         I915_WRITE(MEMIHYST, 1);
4997
4998         /* Set up min, max, and cur for interrupt handling */
4999         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5000         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5001         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5002                 MEMMODE_FSTART_SHIFT;
5003
5004         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
5005                 PXVFREQ_PX_SHIFT;
5006
5007         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
5008         dev_priv->ips.fstart = fstart;
5009
5010         dev_priv->ips.max_delay = fstart;
5011         dev_priv->ips.min_delay = fmin;
5012         dev_priv->ips.cur_delay = fstart;
5013
5014         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5015                          fmax, fmin, fstart);
5016
5017         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5018
5019         /*
5020          * Interrupts will be enabled in ironlake_irq_postinstall
5021          */
5022
5023         I915_WRITE(VIDSTART, vstart);
5024         POSTING_READ(VIDSTART);
5025
5026         rgvmodectl |= MEMMODE_SWMODE_EN;
5027         I915_WRITE(MEMMODECTL, rgvmodectl);
5028
5029         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5030                 DRM_ERROR("stuck trying to change perf mode\n");
5031         mdelay(1);
5032
5033         ironlake_set_drps(dev_priv, fstart);
5034
5035         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
5036                 I915_READ(DDREC) + I915_READ(CSIEC);
5037         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
5038         dev_priv->ips.last_count2 = I915_READ(GFXEC);
5039         dev_priv->ips.last_time2 = ktime_get_raw_ns();
5040
5041         spin_unlock_irq(&mchdev_lock);
5042 }
5043
5044 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
5045 {
5046         u16 rgvswctl;
5047
5048         spin_lock_irq(&mchdev_lock);
5049
5050         rgvswctl = I915_READ16(MEMSWCTL);
5051
5052         /* Ack interrupts, disable EFC interrupt */
5053         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5054         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5055         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5056         I915_WRITE(DEIIR, DE_PCU_EVENT);
5057         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5058
5059         /* Go back to the starting frequency */
5060         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
5061         mdelay(1);
5062         rgvswctl |= MEMCTL_CMD_STS;
5063         I915_WRITE(MEMSWCTL, rgvswctl);
5064         mdelay(1);
5065
5066         spin_unlock_irq(&mchdev_lock);
5067 }
5068
5069 /* There's a funny hw issue where the hw returns all 0 when reading from
5070  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
5071  * ourselves, instead of doing a rmw cycle (which might result in us clearing
5072  * all limits and the gpu stuck at whatever frequency it is at atm).
5073  */
5074 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
5075 {
5076         u32 limits;
5077
5078         /* Only set the down limit when we've reached the lowest level to avoid
5079          * getting more interrupts, otherwise leave this clear. This prevents a
5080          * race in the hw when coming out of rc6: There's a tiny window where
5081          * the hw runs at the minimal clock before selecting the desired
5082          * frequency, if the down threshold expires in that window we will not
5083          * receive a down interrupt. */
5084         if (IS_GEN9(dev_priv)) {
5085                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
5086                 if (val <= dev_priv->rps.min_freq_softlimit)
5087                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
5088         } else {
5089                 limits = dev_priv->rps.max_freq_softlimit << 24;
5090                 if (val <= dev_priv->rps.min_freq_softlimit)
5091                         limits |= dev_priv->rps.min_freq_softlimit << 16;
5092         }
5093
5094         return limits;
5095 }
5096
5097 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
5098 {
5099         int new_power;
5100         u32 threshold_up = 0, threshold_down = 0; /* in % */
5101         u32 ei_up = 0, ei_down = 0;
5102
5103         new_power = dev_priv->rps.power;
5104         switch (dev_priv->rps.power) {
5105         case LOW_POWER:
5106                 if (val > dev_priv->rps.efficient_freq + 1 &&
5107                     val > dev_priv->rps.cur_freq)
5108                         new_power = BETWEEN;
5109                 break;
5110
5111         case BETWEEN:
5112                 if (val <= dev_priv->rps.efficient_freq &&
5113                     val < dev_priv->rps.cur_freq)
5114                         new_power = LOW_POWER;
5115                 else if (val >= dev_priv->rps.rp0_freq &&
5116                          val > dev_priv->rps.cur_freq)
5117                         new_power = HIGH_POWER;
5118                 break;
5119
5120         case HIGH_POWER:
5121                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
5122                     val < dev_priv->rps.cur_freq)
5123                         new_power = BETWEEN;
5124                 break;
5125         }
5126         /* Max/min bins are special */
5127         if (val <= dev_priv->rps.min_freq_softlimit)
5128                 new_power = LOW_POWER;
5129         if (val >= dev_priv->rps.max_freq_softlimit)
5130                 new_power = HIGH_POWER;
5131         if (new_power == dev_priv->rps.power)
5132                 return;
5133
5134         /* Note the units here are not exactly 1us, but 1280ns. */
5135         switch (new_power) {
5136         case LOW_POWER:
5137                 /* Upclock if more than 95% busy over 16ms */
5138                 ei_up = 16000;
5139                 threshold_up = 95;
5140
5141                 /* Downclock if less than 85% busy over 32ms */
5142                 ei_down = 32000;
5143                 threshold_down = 85;
5144                 break;
5145
5146         case BETWEEN:
5147                 /* Upclock if more than 90% busy over 13ms */
5148                 ei_up = 13000;
5149                 threshold_up = 90;
5150
5151                 /* Downclock if less than 75% busy over 32ms */
5152                 ei_down = 32000;
5153                 threshold_down = 75;
5154                 break;
5155
5156         case HIGH_POWER:
5157                 /* Upclock if more than 85% busy over 10ms */
5158                 ei_up = 10000;
5159                 threshold_up = 85;
5160
5161                 /* Downclock if less than 60% busy over 32ms */
5162                 ei_down = 32000;
5163                 threshold_down = 60;
5164                 break;
5165         }
5166
5167         /* When byt can survive without system hang with dynamic
5168          * sw freq adjustments, this restriction can be lifted.
5169          */
5170         if (IS_VALLEYVIEW(dev_priv))
5171                 goto skip_hw_write;
5172
5173         I915_WRITE(GEN6_RP_UP_EI,
5174                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
5175         I915_WRITE(GEN6_RP_UP_THRESHOLD,
5176                    GT_INTERVAL_FROM_US(dev_priv,
5177                                        ei_up * threshold_up / 100));
5178
5179         I915_WRITE(GEN6_RP_DOWN_EI,
5180                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
5181         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
5182                    GT_INTERVAL_FROM_US(dev_priv,
5183                                        ei_down * threshold_down / 100));
5184
5185         I915_WRITE(GEN6_RP_CONTROL,
5186                    GEN6_RP_MEDIA_TURBO |
5187                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5188                    GEN6_RP_MEDIA_IS_GFX |
5189                    GEN6_RP_ENABLE |
5190                    GEN6_RP_UP_BUSY_AVG |
5191                    GEN6_RP_DOWN_IDLE_AVG);
5192
5193 skip_hw_write:
5194         dev_priv->rps.power = new_power;
5195         dev_priv->rps.up_threshold = threshold_up;
5196         dev_priv->rps.down_threshold = threshold_down;
5197         dev_priv->rps.last_adj = 0;
5198 }
5199
5200 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
5201 {
5202         u32 mask = 0;
5203
5204         /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
5205         if (val > dev_priv->rps.min_freq_softlimit)
5206                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
5207         if (val < dev_priv->rps.max_freq_softlimit)
5208                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
5209
5210         mask &= dev_priv->pm_rps_events;
5211
5212         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
5213 }
5214
5215 /* gen6_set_rps is called to update the frequency request, but should also be
5216  * called when the range (min_delay and max_delay) is modified so that we can
5217  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
5218 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
5219 {
5220         /* min/max delay may still have been modified so be sure to
5221          * write the limits value.
5222          */
5223         if (val != dev_priv->rps.cur_freq) {
5224                 gen6_set_rps_thresholds(dev_priv, val);
5225
5226                 if (IS_GEN9(dev_priv))
5227                         I915_WRITE(GEN6_RPNSWREQ,
5228                                    GEN9_FREQUENCY(val));
5229                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5230                         I915_WRITE(GEN6_RPNSWREQ,
5231                                    HSW_FREQUENCY(val));
5232                 else
5233                         I915_WRITE(GEN6_RPNSWREQ,
5234                                    GEN6_FREQUENCY(val) |
5235                                    GEN6_OFFSET(0) |
5236                                    GEN6_AGGRESSIVE_TURBO);
5237         }
5238
5239         /* Make sure we continue to get interrupts
5240          * until we hit the minimum or maximum frequencies.
5241          */
5242         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
5243         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
5244
5245         dev_priv->rps.cur_freq = val;
5246         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5247
5248         return 0;
5249 }
5250
5251 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
5252 {
5253         int err;
5254
5255         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
5256                       "Odd GPU freq value\n"))
5257                 val &= ~1;
5258
5259         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
5260
5261         if (val != dev_priv->rps.cur_freq) {
5262                 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
5263                 if (err)
5264                         return err;
5265
5266                 gen6_set_rps_thresholds(dev_priv, val);
5267         }
5268
5269         dev_priv->rps.cur_freq = val;
5270         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5271
5272         return 0;
5273 }
5274
5275 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
5276  *
5277  * * If Gfx is Idle, then
5278  * 1. Forcewake Media well.
5279  * 2. Request idle freq.
5280  * 3. Release Forcewake of Media well.
5281 */
5282 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5283 {
5284         u32 val = dev_priv->rps.idle_freq;
5285         int err;
5286
5287         if (dev_priv->rps.cur_freq <= val)
5288                 return;
5289
5290         /* The punit delays the write of the frequency and voltage until it
5291          * determines the GPU is awake. During normal usage we don't want to
5292          * waste power changing the frequency if the GPU is sleeping (rc6).
5293          * However, the GPU and driver is now idle and we do not want to delay
5294          * switching to minimum voltage (reducing power whilst idle) as we do
5295          * not expect to be woken in the near future and so must flush the
5296          * change by waking the device.
5297          *
5298          * We choose to take the media powerwell (either would do to trick the
5299          * punit into committing the voltage change) as that takes a lot less
5300          * power than the render powerwell.
5301          */
5302         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5303         err = valleyview_set_rps(dev_priv, val);
5304         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5305
5306         if (err)
5307                 DRM_ERROR("Failed to set RPS for idle\n");
5308 }
5309
5310 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5311 {
5312         mutex_lock(&dev_priv->rps.hw_lock);
5313         if (dev_priv->rps.enabled) {
5314                 u8 freq;
5315
5316                 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
5317                         gen6_rps_reset_ei(dev_priv);
5318                 I915_WRITE(GEN6_PMINTRMSK,
5319                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5320
5321                 gen6_enable_rps_interrupts(dev_priv);
5322
5323                 /* Use the user's desired frequency as a guide, but for better
5324                  * performance, jump directly to RPe as our starting frequency.
5325                  */
5326                 freq = max(dev_priv->rps.cur_freq,
5327                            dev_priv->rps.efficient_freq);
5328
5329                 if (intel_set_rps(dev_priv,
5330                                   clamp(freq,
5331                                         dev_priv->rps.min_freq_softlimit,
5332                                         dev_priv->rps.max_freq_softlimit)))
5333                         DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
5334         }
5335         mutex_unlock(&dev_priv->rps.hw_lock);
5336 }
5337
5338 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5339 {
5340         /* Flush our bottom-half so that it does not race with us
5341          * setting the idle frequency and so that it is bounded by
5342          * our rpm wakeref. And then disable the interrupts to stop any
5343          * futher RPS reclocking whilst we are asleep.
5344          */
5345         gen6_disable_rps_interrupts(dev_priv);
5346
5347         mutex_lock(&dev_priv->rps.hw_lock);
5348         if (dev_priv->rps.enabled) {
5349                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5350                         vlv_set_rps_idle(dev_priv);
5351                 else
5352                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5353                 dev_priv->rps.last_adj = 0;
5354                 I915_WRITE(GEN6_PMINTRMSK,
5355                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5356         }
5357         mutex_unlock(&dev_priv->rps.hw_lock);
5358
5359         spin_lock(&dev_priv->rps.client_lock);
5360         while (!list_empty(&dev_priv->rps.clients))
5361                 list_del_init(dev_priv->rps.clients.next);
5362         spin_unlock(&dev_priv->rps.client_lock);
5363 }
5364
5365 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5366                     struct intel_rps_client *rps,
5367                     unsigned long submitted)
5368 {
5369         /* This is intentionally racy! We peek at the state here, then
5370          * validate inside the RPS worker.
5371          */
5372         if (!(dev_priv->gt.awake &&
5373               dev_priv->rps.enabled &&
5374               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5375                 return;
5376
5377         /* Force a RPS boost (and don't count it against the client) if
5378          * the GPU is severely congested.
5379          */
5380         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5381                 rps = NULL;
5382
5383         spin_lock(&dev_priv->rps.client_lock);
5384         if (rps == NULL || list_empty(&rps->link)) {
5385                 spin_lock_irq(&dev_priv->irq_lock);
5386                 if (dev_priv->rps.interrupts_enabled) {
5387                         dev_priv->rps.client_boost = true;
5388                         schedule_work(&dev_priv->rps.work);
5389                 }
5390                 spin_unlock_irq(&dev_priv->irq_lock);
5391
5392                 if (rps != NULL) {
5393                         list_add(&rps->link, &dev_priv->rps.clients);
5394                         rps->boosts++;
5395                 } else
5396                         dev_priv->rps.boosts++;
5397         }
5398         spin_unlock(&dev_priv->rps.client_lock);
5399 }
5400
5401 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5402 {
5403         int err;
5404
5405         lockdep_assert_held(&dev_priv->rps.hw_lock);
5406         GEM_BUG_ON(val > dev_priv->rps.max_freq);
5407         GEM_BUG_ON(val < dev_priv->rps.min_freq);
5408
5409         if (!dev_priv->rps.enabled) {
5410                 dev_priv->rps.cur_freq = val;
5411                 return 0;
5412         }
5413
5414         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5415                 err = valleyview_set_rps(dev_priv, val);
5416         else
5417                 err = gen6_set_rps(dev_priv, val);
5418
5419         return err;
5420 }
5421
5422 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5423 {
5424         I915_WRITE(GEN6_RC_CONTROL, 0);
5425         I915_WRITE(GEN9_PG_ENABLE, 0);
5426 }
5427
5428 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5429 {
5430         I915_WRITE(GEN6_RP_CONTROL, 0);
5431 }
5432
5433 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5434 {
5435         I915_WRITE(GEN6_RC_CONTROL, 0);
5436         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5437         I915_WRITE(GEN6_RP_CONTROL, 0);
5438 }
5439
5440 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5441 {
5442         I915_WRITE(GEN6_RC_CONTROL, 0);
5443 }
5444
5445 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5446 {
5447         /* we're doing forcewake before Disabling RC6,
5448          * This what the BIOS expects when going into suspend */
5449         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5450
5451         I915_WRITE(GEN6_RC_CONTROL, 0);
5452
5453         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5454 }
5455
5456 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5457 {
5458         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5459                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5460                         mode = GEN6_RC_CTL_RC6_ENABLE;
5461                 else
5462                         mode = 0;
5463         }
5464         if (HAS_RC6p(dev_priv))
5465                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5466                                  "RC6 %s RC6p %s RC6pp %s\n",
5467                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5468                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5469                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5470
5471         else
5472                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5473                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5474 }
5475
5476 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5477 {
5478         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5479         bool enable_rc6 = true;
5480         unsigned long rc6_ctx_base;
5481         u32 rc_ctl;
5482         int rc_sw_target;
5483
5484         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5485         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5486                        RC_SW_TARGET_STATE_SHIFT;
5487         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5488                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5489                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5490                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5491                          rc_sw_target);
5492
5493         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5494                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5495                 enable_rc6 = false;
5496         }
5497
5498         /*
5499          * The exact context size is not known for BXT, so assume a page size
5500          * for this check.
5501          */
5502         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5503         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5504               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5505                                         ggtt->stolen_reserved_size))) {
5506                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5507                 enable_rc6 = false;
5508         }
5509
5510         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5511               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5512               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5513               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5514                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5515                 enable_rc6 = false;
5516         }
5517
5518         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5519             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5520             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5521                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5522                 enable_rc6 = false;
5523         }
5524
5525         if (!I915_READ(GEN6_GFXPAUSE)) {
5526                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5527                 enable_rc6 = false;
5528         }
5529
5530         if (!I915_READ(GEN8_MISC_CTRL0)) {
5531                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5532                 enable_rc6 = false;
5533         }
5534
5535         return enable_rc6;
5536 }
5537
5538 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5539 {
5540         /* No RC6 before Ironlake and code is gone for ilk. */
5541         if (INTEL_INFO(dev_priv)->gen < 6)
5542                 return 0;
5543
5544         if (!enable_rc6)
5545                 return 0;
5546
5547         if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5548                 DRM_INFO("RC6 disabled by BIOS\n");
5549                 return 0;
5550         }
5551
5552         /* Respect the kernel parameter if it is set */
5553         if (enable_rc6 >= 0) {
5554                 int mask;
5555
5556                 if (HAS_RC6p(dev_priv))
5557                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5558                                INTEL_RC6pp_ENABLE;
5559                 else
5560                         mask = INTEL_RC6_ENABLE;
5561
5562                 if ((enable_rc6 & mask) != enable_rc6)
5563                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5564                                          "(requested %d, valid %d)\n",
5565                                          enable_rc6 & mask, enable_rc6, mask);
5566
5567                 return enable_rc6 & mask;
5568         }
5569
5570         if (IS_IVYBRIDGE(dev_priv))
5571                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5572
5573         return INTEL_RC6_ENABLE;
5574 }
5575
5576 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5577 {
5578         /* All of these values are in units of 50MHz */
5579
5580         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5581         if (IS_GEN9_LP(dev_priv)) {
5582                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5583                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5584                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5585                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5586         } else {
5587                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5588                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5589                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5590                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5591         }
5592         /* hw_max = RP0 until we check for overclocking */
5593         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5594
5595         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5596         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5597             IS_GEN9_BC(dev_priv)) {
5598                 u32 ddcc_status = 0;
5599
5600                 if (sandybridge_pcode_read(dev_priv,
5601                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5602                                            &ddcc_status) == 0)
5603                         dev_priv->rps.efficient_freq =
5604                                 clamp_t(u8,
5605                                         ((ddcc_status >> 8) & 0xff),
5606                                         dev_priv->rps.min_freq,
5607                                         dev_priv->rps.max_freq);
5608         }
5609
5610         if (IS_GEN9_BC(dev_priv)) {
5611                 /* Store the frequency values in 16.66 MHZ units, which is
5612                  * the natural hardware unit for SKL
5613                  */
5614                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5615                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5616                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5617                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5618                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5619         }
5620 }
5621
5622 static void reset_rps(struct drm_i915_private *dev_priv,
5623                       int (*set)(struct drm_i915_private *, u8))
5624 {
5625         u8 freq = dev_priv->rps.cur_freq;
5626
5627         /* force a reset */
5628         dev_priv->rps.power = -1;
5629         dev_priv->rps.cur_freq = -1;
5630
5631         if (set(dev_priv, freq))
5632                 DRM_ERROR("Failed to reset RPS to initial values\n");
5633 }
5634
5635 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5636 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5637 {
5638         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5639
5640         /* Program defaults and thresholds for RPS*/
5641         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5642                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5643
5644         /* 1 second timeout*/
5645         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5646                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5647
5648         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5649
5650         /* Leaning on the below call to gen6_set_rps to program/setup the
5651          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5652          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5653         reset_rps(dev_priv, gen6_set_rps);
5654
5655         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5656 }
5657
5658 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5659 {
5660         struct intel_engine_cs *engine;
5661         enum intel_engine_id id;
5662         uint32_t rc6_mask = 0;
5663
5664         /* 1a: Software RC state - RC0 */
5665         I915_WRITE(GEN6_RC_STATE, 0);
5666
5667         /* 1b: Get forcewake during program sequence. Although the driver
5668          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5669         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5670
5671         /* 2a: Disable RC states. */
5672         I915_WRITE(GEN6_RC_CONTROL, 0);
5673
5674         /* 2b: Program RC6 thresholds.*/
5675
5676         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5677         if (IS_SKYLAKE(dev_priv))
5678                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5679         else
5680                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5681         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5682         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5683         for_each_engine(engine, dev_priv, id)
5684                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5685
5686         if (HAS_GUC(dev_priv))
5687                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5688
5689         I915_WRITE(GEN6_RC_SLEEP, 0);
5690
5691         /* 2c: Program Coarse Power Gating Policies. */
5692         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5693         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5694
5695         /* 3a: Enable RC6 */
5696         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5697                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5698         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5699         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5700         I915_WRITE(GEN6_RC_CONTROL,
5701                    GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
5702
5703         /*
5704          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5705          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5706          */
5707         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5708                 I915_WRITE(GEN9_PG_ENABLE, 0);
5709         else
5710                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5711                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5712
5713         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5714 }
5715
5716 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5717 {
5718         struct intel_engine_cs *engine;
5719         enum intel_engine_id id;
5720         uint32_t rc6_mask = 0;
5721
5722         /* 1a: Software RC state - RC0 */
5723         I915_WRITE(GEN6_RC_STATE, 0);
5724
5725         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5726          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5727         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5728
5729         /* 2a: Disable RC states. */
5730         I915_WRITE(GEN6_RC_CONTROL, 0);
5731
5732         /* 2b: Program RC6 thresholds.*/
5733         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5734         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5735         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5736         for_each_engine(engine, dev_priv, id)
5737                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5738         I915_WRITE(GEN6_RC_SLEEP, 0);
5739         if (IS_BROADWELL(dev_priv))
5740                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5741         else
5742                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5743
5744         /* 3: Enable RC6 */
5745         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5746                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5747         intel_print_rc6_info(dev_priv, rc6_mask);
5748         if (IS_BROADWELL(dev_priv))
5749                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5750                                 GEN7_RC_CTL_TO_MODE |
5751                                 rc6_mask);
5752         else
5753                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5754                                 GEN6_RC_CTL_EI_MODE(1) |
5755                                 rc6_mask);
5756
5757         /* 4 Program defaults and thresholds for RPS*/
5758         I915_WRITE(GEN6_RPNSWREQ,
5759                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5760         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5761                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5762         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5763         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5764
5765         /* Docs recommend 900MHz, and 300 MHz respectively */
5766         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5767                    dev_priv->rps.max_freq_softlimit << 24 |
5768                    dev_priv->rps.min_freq_softlimit << 16);
5769
5770         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5771         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5772         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5773         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5774
5775         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5776
5777         /* 5: Enable RPS */
5778         I915_WRITE(GEN6_RP_CONTROL,
5779                    GEN6_RP_MEDIA_TURBO |
5780                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5781                    GEN6_RP_MEDIA_IS_GFX |
5782                    GEN6_RP_ENABLE |
5783                    GEN6_RP_UP_BUSY_AVG |
5784                    GEN6_RP_DOWN_IDLE_AVG);
5785
5786         /* 6: Ring frequency + overclocking (our driver does this later */
5787
5788         reset_rps(dev_priv, gen6_set_rps);
5789
5790         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5791 }
5792
5793 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5794 {
5795         struct intel_engine_cs *engine;
5796         enum intel_engine_id id;
5797         u32 rc6vids, rc6_mask = 0;
5798         u32 gtfifodbg;
5799         int rc6_mode;
5800         int ret;
5801
5802         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5803
5804         /* Here begins a magic sequence of register writes to enable
5805          * auto-downclocking.
5806          *
5807          * Perhaps there might be some value in exposing these to
5808          * userspace...
5809          */
5810         I915_WRITE(GEN6_RC_STATE, 0);
5811
5812         /* Clear the DBG now so we don't confuse earlier errors */
5813         gtfifodbg = I915_READ(GTFIFODBG);
5814         if (gtfifodbg) {
5815                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5816                 I915_WRITE(GTFIFODBG, gtfifodbg);
5817         }
5818
5819         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5820
5821         /* disable the counters and set deterministic thresholds */
5822         I915_WRITE(GEN6_RC_CONTROL, 0);
5823
5824         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5825         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5826         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5827         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5828         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5829
5830         for_each_engine(engine, dev_priv, id)
5831                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5832
5833         I915_WRITE(GEN6_RC_SLEEP, 0);
5834         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5835         if (IS_IVYBRIDGE(dev_priv))
5836                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5837         else
5838                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5839         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5840         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5841
5842         /* Check if we are enabling RC6 */
5843         rc6_mode = intel_enable_rc6();
5844         if (rc6_mode & INTEL_RC6_ENABLE)
5845                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5846
5847         /* We don't use those on Haswell */
5848         if (!IS_HASWELL(dev_priv)) {
5849                 if (rc6_mode & INTEL_RC6p_ENABLE)
5850                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5851
5852                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5853                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5854         }
5855
5856         intel_print_rc6_info(dev_priv, rc6_mask);
5857
5858         I915_WRITE(GEN6_RC_CONTROL,
5859                    rc6_mask |
5860                    GEN6_RC_CTL_EI_MODE(1) |
5861                    GEN6_RC_CTL_HW_ENABLE);
5862
5863         /* Power down if completely idle for over 50ms */
5864         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5865         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5866
5867         reset_rps(dev_priv, gen6_set_rps);
5868
5869         rc6vids = 0;
5870         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5871         if (IS_GEN6(dev_priv) && ret) {
5872                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5873         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5874                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5875                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5876                 rc6vids &= 0xffff00;
5877                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5878                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5879                 if (ret)
5880                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5881         }
5882
5883         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5884 }
5885
5886 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5887 {
5888         int min_freq = 15;
5889         unsigned int gpu_freq;
5890         unsigned int max_ia_freq, min_ring_freq;
5891         unsigned int max_gpu_freq, min_gpu_freq;
5892         int scaling_factor = 180;
5893         struct cpufreq_policy *policy;
5894
5895         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5896
5897         policy = cpufreq_cpu_get(0);
5898         if (policy) {
5899                 max_ia_freq = policy->cpuinfo.max_freq;
5900                 cpufreq_cpu_put(policy);
5901         } else {
5902                 /*
5903                  * Default to measured freq if none found, PCU will ensure we
5904                  * don't go over
5905                  */
5906                 max_ia_freq = tsc_khz;
5907         }
5908
5909         /* Convert from kHz to MHz */
5910         max_ia_freq /= 1000;
5911
5912         min_ring_freq = I915_READ(DCLK) & 0xf;
5913         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5914         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5915
5916         if (IS_GEN9_BC(dev_priv)) {
5917                 /* Convert GT frequency to 50 HZ units */
5918                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5919                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5920         } else {
5921                 min_gpu_freq = dev_priv->rps.min_freq;
5922                 max_gpu_freq = dev_priv->rps.max_freq;
5923         }
5924
5925         /*
5926          * For each potential GPU frequency, load a ring frequency we'd like
5927          * to use for memory access.  We do this by specifying the IA frequency
5928          * the PCU should use as a reference to determine the ring frequency.
5929          */
5930         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5931                 int diff = max_gpu_freq - gpu_freq;
5932                 unsigned int ia_freq = 0, ring_freq = 0;
5933
5934                 if (IS_GEN9_BC(dev_priv)) {
5935                         /*
5936                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5937                          * No floor required for ring frequency on SKL.
5938                          */
5939                         ring_freq = gpu_freq;
5940                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5941                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5942                         ring_freq = max(min_ring_freq, gpu_freq);
5943                 } else if (IS_HASWELL(dev_priv)) {
5944                         ring_freq = mult_frac(gpu_freq, 5, 4);
5945                         ring_freq = max(min_ring_freq, ring_freq);
5946                         /* leave ia_freq as the default, chosen by cpufreq */
5947                 } else {
5948                         /* On older processors, there is no separate ring
5949                          * clock domain, so in order to boost the bandwidth
5950                          * of the ring, we need to upclock the CPU (ia_freq).
5951                          *
5952                          * For GPU frequencies less than 750MHz,
5953                          * just use the lowest ring freq.
5954                          */
5955                         if (gpu_freq < min_freq)
5956                                 ia_freq = 800;
5957                         else
5958                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5959                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5960                 }
5961
5962                 sandybridge_pcode_write(dev_priv,
5963                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5964                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5965                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5966                                         gpu_freq);
5967         }
5968 }
5969
5970 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5971 {
5972         u32 val, rp0;
5973
5974         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5975
5976         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5977         case 8:
5978                 /* (2 * 4) config */
5979                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5980                 break;
5981         case 12:
5982                 /* (2 * 6) config */
5983                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5984                 break;
5985         case 16:
5986                 /* (2 * 8) config */
5987         default:
5988                 /* Setting (2 * 8) Min RP0 for any other combination */
5989                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5990                 break;
5991         }
5992
5993         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5994
5995         return rp0;
5996 }
5997
5998 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5999 {
6000         u32 val, rpe;
6001
6002         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
6003         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
6004
6005         return rpe;
6006 }
6007
6008 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
6009 {
6010         u32 val, rp1;
6011
6012         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6013         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
6014
6015         return rp1;
6016 }
6017
6018 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
6019 {
6020         u32 val, rpn;
6021
6022         val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
6023         rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
6024                        FB_GFX_FREQ_FUSE_MASK);
6025
6026         return rpn;
6027 }
6028
6029 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
6030 {
6031         u32 val, rp1;
6032
6033         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
6034
6035         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
6036
6037         return rp1;
6038 }
6039
6040 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
6041 {
6042         u32 val, rp0;
6043
6044         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
6045
6046         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
6047         /* Clamp to max */
6048         rp0 = min_t(u32, rp0, 0xea);
6049
6050         return rp0;
6051 }
6052
6053 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
6054 {
6055         u32 val, rpe;
6056
6057         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
6058         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
6059         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
6060         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
6061
6062         return rpe;
6063 }
6064
6065 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
6066 {
6067         u32 val;
6068
6069         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
6070         /*
6071          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
6072          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
6073          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
6074          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
6075          * to make sure it matches what Punit accepts.
6076          */
6077         return max_t(u32, val, 0xc0);
6078 }
6079
6080 /* Check that the pctx buffer wasn't move under us. */
6081 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
6082 {
6083         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
6084
6085         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
6086                              dev_priv->vlv_pctx->stolen->start);
6087 }
6088
6089
6090 /* Check that the pcbr address is not empty. */
6091 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
6092 {
6093         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
6094
6095         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
6096 }
6097
6098 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
6099 {
6100         struct i915_ggtt *ggtt = &dev_priv->ggtt;
6101         unsigned long pctx_paddr, paddr;
6102         u32 pcbr;
6103         int pctx_size = 32*1024;
6104
6105         pcbr = I915_READ(VLV_PCBR);
6106         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
6107                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6108                 paddr = (dev_priv->mm.stolen_base +
6109                          (ggtt->stolen_size - pctx_size));
6110
6111                 pctx_paddr = (paddr & (~4095));
6112                 I915_WRITE(VLV_PCBR, pctx_paddr);
6113         }
6114
6115         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
6116 }
6117
6118 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
6119 {
6120         struct drm_i915_gem_object *pctx;
6121         unsigned long pctx_paddr;
6122         u32 pcbr;
6123         int pctx_size = 24*1024;
6124
6125         pcbr = I915_READ(VLV_PCBR);
6126         if (pcbr) {
6127                 /* BIOS set it up already, grab the pre-alloc'd space */
6128                 int pcbr_offset;
6129
6130                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
6131                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
6132                                                                       pcbr_offset,
6133                                                                       I915_GTT_OFFSET_NONE,
6134                                                                       pctx_size);
6135                 goto out;
6136         }
6137
6138         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6139
6140         /*
6141          * From the Gunit register HAS:
6142          * The Gfx driver is expected to program this register and ensure
6143          * proper allocation within Gfx stolen memory.  For example, this
6144          * register should be programmed such than the PCBR range does not
6145          * overlap with other ranges, such as the frame buffer, protected
6146          * memory, or any other relevant ranges.
6147          */
6148         pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
6149         if (!pctx) {
6150                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
6151                 goto out;
6152         }
6153
6154         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
6155         I915_WRITE(VLV_PCBR, pctx_paddr);
6156
6157 out:
6158         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
6159         dev_priv->vlv_pctx = pctx;
6160 }
6161
6162 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
6163 {
6164         if (WARN_ON(!dev_priv->vlv_pctx))
6165                 return;
6166
6167         i915_gem_object_put(dev_priv->vlv_pctx);
6168         dev_priv->vlv_pctx = NULL;
6169 }
6170
6171 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
6172 {
6173         dev_priv->rps.gpll_ref_freq =
6174                 vlv_get_cck_clock(dev_priv, "GPLL ref",
6175                                   CCK_GPLL_CLOCK_CONTROL,
6176                                   dev_priv->czclk_freq);
6177
6178         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
6179                          dev_priv->rps.gpll_ref_freq);
6180 }
6181
6182 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
6183 {
6184         u32 val;
6185
6186         valleyview_setup_pctx(dev_priv);
6187
6188         vlv_init_gpll_ref_freq(dev_priv);
6189
6190         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6191         switch ((val >> 6) & 3) {
6192         case 0:
6193         case 1:
6194                 dev_priv->mem_freq = 800;
6195                 break;
6196         case 2:
6197                 dev_priv->mem_freq = 1066;
6198                 break;
6199         case 3:
6200                 dev_priv->mem_freq = 1333;
6201                 break;
6202         }
6203         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
6204
6205         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
6206         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
6207         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
6208                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
6209                          dev_priv->rps.max_freq);
6210
6211         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
6212         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
6213                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
6214                          dev_priv->rps.efficient_freq);
6215
6216         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
6217         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
6218                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
6219                          dev_priv->rps.rp1_freq);
6220
6221         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
6222         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
6223                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
6224                          dev_priv->rps.min_freq);
6225 }
6226
6227 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
6228 {
6229         u32 val;
6230
6231         cherryview_setup_pctx(dev_priv);
6232
6233         vlv_init_gpll_ref_freq(dev_priv);
6234
6235         mutex_lock(&dev_priv->sb_lock);
6236         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
6237         mutex_unlock(&dev_priv->sb_lock);
6238
6239         switch ((val >> 2) & 0x7) {
6240         case 3:
6241                 dev_priv->mem_freq = 2000;
6242                 break;
6243         default:
6244                 dev_priv->mem_freq = 1600;
6245                 break;
6246         }
6247         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
6248
6249         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
6250         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
6251         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
6252                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
6253                          dev_priv->rps.max_freq);
6254
6255         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
6256         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
6257                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
6258                          dev_priv->rps.efficient_freq);
6259
6260         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
6261         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
6262                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
6263                          dev_priv->rps.rp1_freq);
6264
6265         dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
6266         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
6267                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
6268                          dev_priv->rps.min_freq);
6269
6270         WARN_ONCE((dev_priv->rps.max_freq |
6271                    dev_priv->rps.efficient_freq |
6272                    dev_priv->rps.rp1_freq |
6273                    dev_priv->rps.min_freq) & 1,
6274                   "Odd GPU freq values\n");
6275 }
6276
6277 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6278 {
6279         valleyview_cleanup_pctx(dev_priv);
6280 }
6281
6282 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
6283 {
6284         struct intel_engine_cs *engine;
6285         enum intel_engine_id id;
6286         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
6287
6288         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6289
6290         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6291                                              GT_FIFO_FREE_ENTRIES_CHV);
6292         if (gtfifodbg) {
6293                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6294                                  gtfifodbg);
6295                 I915_WRITE(GTFIFODBG, gtfifodbg);
6296         }
6297
6298         cherryview_check_pctx(dev_priv);
6299
6300         /* 1a & 1b: Get forcewake during program sequence. Although the driver
6301          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6302         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6303
6304         /*  Disable RC states. */
6305         I915_WRITE(GEN6_RC_CONTROL, 0);
6306
6307         /* 2a: Program RC6 thresholds.*/
6308         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6309         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6310         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6311
6312         for_each_engine(engine, dev_priv, id)
6313                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6314         I915_WRITE(GEN6_RC_SLEEP, 0);
6315
6316         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6317         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6318
6319         /* allows RC6 residency counter to work */
6320         I915_WRITE(VLV_COUNTER_CONTROL,
6321                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6322                                       VLV_MEDIA_RC6_COUNT_EN |
6323                                       VLV_RENDER_RC6_COUNT_EN));
6324
6325         /* For now we assume BIOS is allocating and populating the PCBR  */
6326         pcbr = I915_READ(VLV_PCBR);
6327
6328         /* 3: Enable RC6 */
6329         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6330             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6331                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6332
6333         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6334
6335         /* 4 Program defaults and thresholds for RPS*/
6336         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6337         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6338         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6339         I915_WRITE(GEN6_RP_UP_EI, 66000);
6340         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6341
6342         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6343
6344         /* 5: Enable RPS */
6345         I915_WRITE(GEN6_RP_CONTROL,
6346                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6347                    GEN6_RP_MEDIA_IS_GFX |
6348                    GEN6_RP_ENABLE |
6349                    GEN6_RP_UP_BUSY_AVG |
6350                    GEN6_RP_DOWN_IDLE_AVG);
6351
6352         /* Setting Fixed Bias */
6353         val = VLV_OVERRIDE_EN |
6354                   VLV_SOC_TDP_EN |
6355                   CHV_BIAS_CPU_50_SOC_50;
6356         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6357
6358         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6359
6360         /* RPS code assumes GPLL is used */
6361         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6362
6363         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6364         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6365
6366         reset_rps(dev_priv, valleyview_set_rps);
6367
6368         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6369 }
6370
6371 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6372 {
6373         struct intel_engine_cs *engine;
6374         enum intel_engine_id id;
6375         u32 gtfifodbg, val, rc6_mode = 0;
6376
6377         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6378
6379         valleyview_check_pctx(dev_priv);
6380
6381         gtfifodbg = I915_READ(GTFIFODBG);
6382         if (gtfifodbg) {
6383                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6384                                  gtfifodbg);
6385                 I915_WRITE(GTFIFODBG, gtfifodbg);
6386         }
6387
6388         /* If VLV, Forcewake all wells, else re-direct to regular path */
6389         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6390
6391         /*  Disable RC states. */
6392         I915_WRITE(GEN6_RC_CONTROL, 0);
6393
6394         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6395         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6396         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6397         I915_WRITE(GEN6_RP_UP_EI, 66000);
6398         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6399
6400         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6401
6402         I915_WRITE(GEN6_RP_CONTROL,
6403                    GEN6_RP_MEDIA_TURBO |
6404                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6405                    GEN6_RP_MEDIA_IS_GFX |
6406                    GEN6_RP_ENABLE |
6407                    GEN6_RP_UP_BUSY_AVG |
6408                    GEN6_RP_DOWN_IDLE_CONT);
6409
6410         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6411         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6412         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6413
6414         for_each_engine(engine, dev_priv, id)
6415                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6416
6417         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6418
6419         /* allows RC6 residency counter to work */
6420         I915_WRITE(VLV_COUNTER_CONTROL,
6421                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6422                                       VLV_MEDIA_RC0_COUNT_EN |
6423                                       VLV_RENDER_RC0_COUNT_EN |
6424                                       VLV_MEDIA_RC6_COUNT_EN |
6425                                       VLV_RENDER_RC6_COUNT_EN));
6426
6427         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6428                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6429
6430         intel_print_rc6_info(dev_priv, rc6_mode);
6431
6432         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6433
6434         /* Setting Fixed Bias */
6435         val = VLV_OVERRIDE_EN |
6436                   VLV_SOC_TDP_EN |
6437                   VLV_BIAS_CPU_125_SOC_875;
6438         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6439
6440         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6441
6442         /* RPS code assumes GPLL is used */
6443         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6444
6445         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6446         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6447
6448         reset_rps(dev_priv, valleyview_set_rps);
6449
6450         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6451 }
6452
6453 static unsigned long intel_pxfreq(u32 vidfreq)
6454 {
6455         unsigned long freq;
6456         int div = (vidfreq & 0x3f0000) >> 16;
6457         int post = (vidfreq & 0x3000) >> 12;
6458         int pre = (vidfreq & 0x7);
6459
6460         if (!pre)
6461                 return 0;
6462
6463         freq = ((div * 133333) / ((1<<post) * pre));
6464
6465         return freq;
6466 }
6467
6468 static const struct cparams {
6469         u16 i;
6470         u16 t;
6471         u16 m;
6472         u16 c;
6473 } cparams[] = {
6474         { 1, 1333, 301, 28664 },
6475         { 1, 1066, 294, 24460 },
6476         { 1, 800, 294, 25192 },
6477         { 0, 1333, 276, 27605 },
6478         { 0, 1066, 276, 27605 },
6479         { 0, 800, 231, 23784 },
6480 };
6481
6482 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6483 {
6484         u64 total_count, diff, ret;
6485         u32 count1, count2, count3, m = 0, c = 0;
6486         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6487         int i;
6488
6489         lockdep_assert_held(&mchdev_lock);
6490
6491         diff1 = now - dev_priv->ips.last_time1;
6492
6493         /* Prevent division-by-zero if we are asking too fast.
6494          * Also, we don't get interesting results if we are polling
6495          * faster than once in 10ms, so just return the saved value
6496          * in such cases.
6497          */
6498         if (diff1 <= 10)
6499                 return dev_priv->ips.chipset_power;
6500
6501         count1 = I915_READ(DMIEC);
6502         count2 = I915_READ(DDREC);
6503         count3 = I915_READ(CSIEC);
6504
6505         total_count = count1 + count2 + count3;
6506
6507         /* FIXME: handle per-counter overflow */
6508         if (total_count < dev_priv->ips.last_count1) {
6509                 diff = ~0UL - dev_priv->ips.last_count1;
6510                 diff += total_count;
6511         } else {
6512                 diff = total_count - dev_priv->ips.last_count1;
6513         }
6514
6515         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6516                 if (cparams[i].i == dev_priv->ips.c_m &&
6517                     cparams[i].t == dev_priv->ips.r_t) {
6518                         m = cparams[i].m;
6519                         c = cparams[i].c;
6520                         break;
6521                 }
6522         }
6523
6524         diff = div_u64(diff, diff1);
6525         ret = ((m * diff) + c);
6526         ret = div_u64(ret, 10);
6527
6528         dev_priv->ips.last_count1 = total_count;
6529         dev_priv->ips.last_time1 = now;
6530
6531         dev_priv->ips.chipset_power = ret;
6532
6533         return ret;
6534 }
6535
6536 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6537 {
6538         unsigned long val;
6539
6540         if (INTEL_INFO(dev_priv)->gen != 5)
6541                 return 0;
6542
6543         spin_lock_irq(&mchdev_lock);
6544
6545         val = __i915_chipset_val(dev_priv);
6546
6547         spin_unlock_irq(&mchdev_lock);
6548
6549         return val;
6550 }
6551
6552 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6553 {
6554         unsigned long m, x, b;
6555         u32 tsfs;
6556
6557         tsfs = I915_READ(TSFS);
6558
6559         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6560         x = I915_READ8(TR1);
6561
6562         b = tsfs & TSFS_INTR_MASK;
6563
6564         return ((m * x) / 127) - b;
6565 }
6566
6567 static int _pxvid_to_vd(u8 pxvid)
6568 {
6569         if (pxvid == 0)
6570                 return 0;
6571
6572         if (pxvid >= 8 && pxvid < 31)
6573                 pxvid = 31;
6574
6575         return (pxvid + 2) * 125;
6576 }
6577
6578 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6579 {
6580         const int vd = _pxvid_to_vd(pxvid);
6581         const int vm = vd - 1125;
6582
6583         if (INTEL_INFO(dev_priv)->is_mobile)
6584                 return vm > 0 ? vm : 0;
6585
6586         return vd;
6587 }
6588
6589 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6590 {
6591         u64 now, diff, diffms;
6592         u32 count;
6593
6594         lockdep_assert_held(&mchdev_lock);
6595
6596         now = ktime_get_raw_ns();
6597         diffms = now - dev_priv->ips.last_time2;
6598         do_div(diffms, NSEC_PER_MSEC);
6599
6600         /* Don't divide by 0 */
6601         if (!diffms)
6602                 return;
6603
6604         count = I915_READ(GFXEC);
6605
6606         if (count < dev_priv->ips.last_count2) {
6607                 diff = ~0UL - dev_priv->ips.last_count2;
6608                 diff += count;
6609         } else {
6610                 diff = count - dev_priv->ips.last_count2;
6611         }
6612
6613         dev_priv->ips.last_count2 = count;
6614         dev_priv->ips.last_time2 = now;
6615
6616         /* More magic constants... */
6617         diff = diff * 1181;
6618         diff = div_u64(diff, diffms * 10);
6619         dev_priv->ips.gfx_power = diff;
6620 }
6621
6622 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6623 {
6624         if (INTEL_INFO(dev_priv)->gen != 5)
6625                 return;
6626
6627         spin_lock_irq(&mchdev_lock);
6628
6629         __i915_update_gfx_val(dev_priv);
6630
6631         spin_unlock_irq(&mchdev_lock);
6632 }
6633
6634 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6635 {
6636         unsigned long t, corr, state1, corr2, state2;
6637         u32 pxvid, ext_v;
6638
6639         lockdep_assert_held(&mchdev_lock);
6640
6641         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6642         pxvid = (pxvid >> 24) & 0x7f;
6643         ext_v = pvid_to_extvid(dev_priv, pxvid);
6644
6645         state1 = ext_v;
6646
6647         t = i915_mch_val(dev_priv);
6648
6649         /* Revel in the empirically derived constants */
6650
6651         /* Correction factor in 1/100000 units */
6652         if (t > 80)
6653                 corr = ((t * 2349) + 135940);
6654         else if (t >= 50)
6655                 corr = ((t * 964) + 29317);
6656         else /* < 50 */
6657                 corr = ((t * 301) + 1004);
6658
6659         corr = corr * ((150142 * state1) / 10000 - 78642);
6660         corr /= 100000;
6661         corr2 = (corr * dev_priv->ips.corr);
6662
6663         state2 = (corr2 * state1) / 10000;
6664         state2 /= 100; /* convert to mW */
6665
6666         __i915_update_gfx_val(dev_priv);
6667
6668         return dev_priv->ips.gfx_power + state2;
6669 }
6670
6671 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6672 {
6673         unsigned long val;
6674
6675         if (INTEL_INFO(dev_priv)->gen != 5)
6676                 return 0;
6677
6678         spin_lock_irq(&mchdev_lock);
6679
6680         val = __i915_gfx_val(dev_priv);
6681
6682         spin_unlock_irq(&mchdev_lock);
6683
6684         return val;
6685 }
6686
6687 /**
6688  * i915_read_mch_val - return value for IPS use
6689  *
6690  * Calculate and return a value for the IPS driver to use when deciding whether
6691  * we have thermal and power headroom to increase CPU or GPU power budget.
6692  */
6693 unsigned long i915_read_mch_val(void)
6694 {
6695         struct drm_i915_private *dev_priv;
6696         unsigned long chipset_val, graphics_val, ret = 0;
6697
6698         spin_lock_irq(&mchdev_lock);
6699         if (!i915_mch_dev)
6700                 goto out_unlock;
6701         dev_priv = i915_mch_dev;
6702
6703         chipset_val = __i915_chipset_val(dev_priv);
6704         graphics_val = __i915_gfx_val(dev_priv);
6705
6706         ret = chipset_val + graphics_val;
6707
6708 out_unlock:
6709         spin_unlock_irq(&mchdev_lock);
6710
6711         return ret;
6712 }
6713 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6714
6715 /**
6716  * i915_gpu_raise - raise GPU frequency limit
6717  *
6718  * Raise the limit; IPS indicates we have thermal headroom.
6719  */
6720 bool i915_gpu_raise(void)
6721 {
6722         struct drm_i915_private *dev_priv;
6723         bool ret = true;
6724
6725         spin_lock_irq(&mchdev_lock);
6726         if (!i915_mch_dev) {
6727                 ret = false;
6728                 goto out_unlock;
6729         }
6730         dev_priv = i915_mch_dev;
6731
6732         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6733                 dev_priv->ips.max_delay--;
6734
6735 out_unlock:
6736         spin_unlock_irq(&mchdev_lock);
6737
6738         return ret;
6739 }
6740 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6741
6742 /**
6743  * i915_gpu_lower - lower GPU frequency limit
6744  *
6745  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6746  * frequency maximum.
6747  */
6748 bool i915_gpu_lower(void)
6749 {
6750         struct drm_i915_private *dev_priv;
6751         bool ret = true;
6752
6753         spin_lock_irq(&mchdev_lock);
6754         if (!i915_mch_dev) {
6755                 ret = false;
6756                 goto out_unlock;
6757         }
6758         dev_priv = i915_mch_dev;
6759
6760         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6761                 dev_priv->ips.max_delay++;
6762
6763 out_unlock:
6764         spin_unlock_irq(&mchdev_lock);
6765
6766         return ret;
6767 }
6768 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6769
6770 /**
6771  * i915_gpu_busy - indicate GPU business to IPS
6772  *
6773  * Tell the IPS driver whether or not the GPU is busy.
6774  */
6775 bool i915_gpu_busy(void)
6776 {
6777         bool ret = false;
6778
6779         spin_lock_irq(&mchdev_lock);
6780         if (i915_mch_dev)
6781                 ret = i915_mch_dev->gt.awake;
6782         spin_unlock_irq(&mchdev_lock);
6783
6784         return ret;
6785 }
6786 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6787
6788 /**
6789  * i915_gpu_turbo_disable - disable graphics turbo
6790  *
6791  * Disable graphics turbo by resetting the max frequency and setting the
6792  * current frequency to the default.
6793  */
6794 bool i915_gpu_turbo_disable(void)
6795 {
6796         struct drm_i915_private *dev_priv;
6797         bool ret = true;
6798
6799         spin_lock_irq(&mchdev_lock);
6800         if (!i915_mch_dev) {
6801                 ret = false;
6802                 goto out_unlock;
6803         }
6804         dev_priv = i915_mch_dev;
6805
6806         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6807
6808         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6809                 ret = false;
6810
6811 out_unlock:
6812         spin_unlock_irq(&mchdev_lock);
6813
6814         return ret;
6815 }
6816 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6817
6818 /**
6819  * Tells the intel_ips driver that the i915 driver is now loaded, if
6820  * IPS got loaded first.
6821  *
6822  * This awkward dance is so that neither module has to depend on the
6823  * other in order for IPS to do the appropriate communication of
6824  * GPU turbo limits to i915.
6825  */
6826 static void
6827 ips_ping_for_i915_load(void)
6828 {
6829         void (*link)(void);
6830
6831         link = symbol_get(ips_link_to_i915_driver);
6832         if (link) {
6833                 link();
6834                 symbol_put(ips_link_to_i915_driver);
6835         }
6836 }
6837
6838 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6839 {
6840         /* We only register the i915 ips part with intel-ips once everything is
6841          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6842         spin_lock_irq(&mchdev_lock);
6843         i915_mch_dev = dev_priv;
6844         spin_unlock_irq(&mchdev_lock);
6845
6846         ips_ping_for_i915_load();
6847 }
6848
6849 void intel_gpu_ips_teardown(void)
6850 {
6851         spin_lock_irq(&mchdev_lock);
6852         i915_mch_dev = NULL;
6853         spin_unlock_irq(&mchdev_lock);
6854 }
6855
6856 static void intel_init_emon(struct drm_i915_private *dev_priv)
6857 {
6858         u32 lcfuse;
6859         u8 pxw[16];
6860         int i;
6861
6862         /* Disable to program */
6863         I915_WRITE(ECR, 0);
6864         POSTING_READ(ECR);
6865
6866         /* Program energy weights for various events */
6867         I915_WRITE(SDEW, 0x15040d00);
6868         I915_WRITE(CSIEW0, 0x007f0000);
6869         I915_WRITE(CSIEW1, 0x1e220004);
6870         I915_WRITE(CSIEW2, 0x04000004);
6871
6872         for (i = 0; i < 5; i++)
6873                 I915_WRITE(PEW(i), 0);
6874         for (i = 0; i < 3; i++)
6875                 I915_WRITE(DEW(i), 0);
6876
6877         /* Program P-state weights to account for frequency power adjustment */
6878         for (i = 0; i < 16; i++) {
6879                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6880                 unsigned long freq = intel_pxfreq(pxvidfreq);
6881                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6882                         PXVFREQ_PX_SHIFT;
6883                 unsigned long val;
6884
6885                 val = vid * vid;
6886                 val *= (freq / 1000);
6887                 val *= 255;
6888                 val /= (127*127*900);
6889                 if (val > 0xff)
6890                         DRM_ERROR("bad pxval: %ld\n", val);
6891                 pxw[i] = val;
6892         }
6893         /* Render standby states get 0 weight */
6894         pxw[14] = 0;
6895         pxw[15] = 0;
6896
6897         for (i = 0; i < 4; i++) {
6898                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6899                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6900                 I915_WRITE(PXW(i), val);
6901         }
6902
6903         /* Adjust magic regs to magic values (more experimental results) */
6904         I915_WRITE(OGW0, 0);
6905         I915_WRITE(OGW1, 0);
6906         I915_WRITE(EG0, 0x00007f00);
6907         I915_WRITE(EG1, 0x0000000e);
6908         I915_WRITE(EG2, 0x000e0000);
6909         I915_WRITE(EG3, 0x68000300);
6910         I915_WRITE(EG4, 0x42000000);
6911         I915_WRITE(EG5, 0x00140031);
6912         I915_WRITE(EG6, 0);
6913         I915_WRITE(EG7, 0);
6914
6915         for (i = 0; i < 8; i++)
6916                 I915_WRITE(PXWL(i), 0);
6917
6918         /* Enable PMON + select events */
6919         I915_WRITE(ECR, 0x80000019);
6920
6921         lcfuse = I915_READ(LCFUSE02);
6922
6923         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6924 }
6925
6926 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6927 {
6928         /*
6929          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6930          * requirement.
6931          */
6932         if (!i915.enable_rc6) {
6933                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6934                 intel_runtime_pm_get(dev_priv);
6935         }
6936
6937         mutex_lock(&dev_priv->drm.struct_mutex);
6938         mutex_lock(&dev_priv->rps.hw_lock);
6939
6940         /* Initialize RPS limits (for userspace) */
6941         if (IS_CHERRYVIEW(dev_priv))
6942                 cherryview_init_gt_powersave(dev_priv);
6943         else if (IS_VALLEYVIEW(dev_priv))
6944                 valleyview_init_gt_powersave(dev_priv);
6945         else if (INTEL_GEN(dev_priv) >= 6)
6946                 gen6_init_rps_frequencies(dev_priv);
6947
6948         /* Derive initial user preferences/limits from the hardware limits */
6949         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6950         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6951
6952         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6953         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6954
6955         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6956                 dev_priv->rps.min_freq_softlimit =
6957                         max_t(int,
6958                               dev_priv->rps.efficient_freq,
6959                               intel_freq_opcode(dev_priv, 450));
6960
6961         /* After setting max-softlimit, find the overclock max freq */
6962         if (IS_GEN6(dev_priv) ||
6963             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6964                 u32 params = 0;
6965
6966                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6967                 if (params & BIT(31)) { /* OC supported */
6968                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6969                                          (dev_priv->rps.max_freq & 0xff) * 50,
6970                                          (params & 0xff) * 50);
6971                         dev_priv->rps.max_freq = params & 0xff;
6972                 }
6973         }
6974
6975         /* Finally allow us to boost to max by default */
6976         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6977
6978         mutex_unlock(&dev_priv->rps.hw_lock);
6979         mutex_unlock(&dev_priv->drm.struct_mutex);
6980
6981         intel_autoenable_gt_powersave(dev_priv);
6982 }
6983
6984 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6985 {
6986         if (IS_VALLEYVIEW(dev_priv))
6987                 valleyview_cleanup_gt_powersave(dev_priv);
6988
6989         if (!i915.enable_rc6)
6990                 intel_runtime_pm_put(dev_priv);
6991 }
6992
6993 /**
6994  * intel_suspend_gt_powersave - suspend PM work and helper threads
6995  * @dev_priv: i915 device
6996  *
6997  * We don't want to disable RC6 or other features here, we just want
6998  * to make sure any work we've queued has finished and won't bother
6999  * us while we're suspended.
7000  */
7001 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
7002 {
7003         if (INTEL_GEN(dev_priv) < 6)
7004                 return;
7005
7006         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
7007                 intel_runtime_pm_put(dev_priv);
7008
7009         /* gen6_rps_idle() will be called later to disable interrupts */
7010 }
7011
7012 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
7013 {
7014         dev_priv->rps.enabled = true; /* force disabling */
7015         intel_disable_gt_powersave(dev_priv);
7016
7017         gen6_reset_rps_interrupts(dev_priv);
7018 }
7019
7020 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
7021 {
7022         if (!READ_ONCE(dev_priv->rps.enabled))
7023                 return;
7024
7025         mutex_lock(&dev_priv->rps.hw_lock);
7026
7027         if (INTEL_GEN(dev_priv) >= 9) {
7028                 gen9_disable_rc6(dev_priv);
7029                 gen9_disable_rps(dev_priv);
7030         } else if (IS_CHERRYVIEW(dev_priv)) {
7031                 cherryview_disable_rps(dev_priv);
7032         } else if (IS_VALLEYVIEW(dev_priv)) {
7033                 valleyview_disable_rps(dev_priv);
7034         } else if (INTEL_GEN(dev_priv) >= 6) {
7035                 gen6_disable_rps(dev_priv);
7036         }  else if (IS_IRONLAKE_M(dev_priv)) {
7037                 ironlake_disable_drps(dev_priv);
7038         }
7039
7040         dev_priv->rps.enabled = false;
7041         mutex_unlock(&dev_priv->rps.hw_lock);
7042 }
7043
7044 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
7045 {
7046         /* We shouldn't be disabling as we submit, so this should be less
7047          * racy than it appears!
7048          */
7049         if (READ_ONCE(dev_priv->rps.enabled))
7050                 return;
7051
7052         /* Powersaving is controlled by the host when inside a VM */
7053         if (intel_vgpu_active(dev_priv))
7054                 return;
7055
7056         mutex_lock(&dev_priv->rps.hw_lock);
7057
7058         if (IS_CHERRYVIEW(dev_priv)) {
7059                 cherryview_enable_rps(dev_priv);
7060         } else if (IS_VALLEYVIEW(dev_priv)) {
7061                 valleyview_enable_rps(dev_priv);
7062         } else if (INTEL_GEN(dev_priv) >= 9) {
7063                 gen9_enable_rc6(dev_priv);
7064                 gen9_enable_rps(dev_priv);
7065                 if (IS_GEN9_BC(dev_priv))
7066                         gen6_update_ring_freq(dev_priv);
7067         } else if (IS_BROADWELL(dev_priv)) {
7068                 gen8_enable_rps(dev_priv);
7069                 gen6_update_ring_freq(dev_priv);
7070         } else if (INTEL_GEN(dev_priv) >= 6) {
7071                 gen6_enable_rps(dev_priv);
7072                 gen6_update_ring_freq(dev_priv);
7073         } else if (IS_IRONLAKE_M(dev_priv)) {
7074                 ironlake_enable_drps(dev_priv);
7075                 intel_init_emon(dev_priv);
7076         }
7077
7078         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
7079         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
7080
7081         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
7082         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
7083
7084         dev_priv->rps.enabled = true;
7085         mutex_unlock(&dev_priv->rps.hw_lock);
7086 }
7087
7088 static void __intel_autoenable_gt_powersave(struct work_struct *work)
7089 {
7090         struct drm_i915_private *dev_priv =
7091                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
7092         struct intel_engine_cs *rcs;
7093         struct drm_i915_gem_request *req;
7094
7095         if (READ_ONCE(dev_priv->rps.enabled))
7096                 goto out;
7097
7098         rcs = dev_priv->engine[RCS];
7099         if (rcs->last_retired_context)
7100                 goto out;
7101
7102         if (!rcs->init_context)
7103                 goto out;
7104
7105         mutex_lock(&dev_priv->drm.struct_mutex);
7106
7107         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
7108         if (IS_ERR(req))
7109                 goto unlock;
7110
7111         if (!i915.enable_execlists && i915_switch_context(req) == 0)
7112                 rcs->init_context(req);
7113
7114         /* Mark the device busy, calling intel_enable_gt_powersave() */
7115         i915_add_request(req);
7116
7117 unlock:
7118         mutex_unlock(&dev_priv->drm.struct_mutex);
7119 out:
7120         intel_runtime_pm_put(dev_priv);
7121 }
7122
7123 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
7124 {
7125         if (READ_ONCE(dev_priv->rps.enabled))
7126                 return;
7127
7128         if (IS_IRONLAKE_M(dev_priv)) {
7129                 ironlake_enable_drps(dev_priv);
7130                 intel_init_emon(dev_priv);
7131         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
7132                 /*
7133                  * PCU communication is slow and this doesn't need to be
7134                  * done at any specific time, so do this out of our fast path
7135                  * to make resume and init faster.
7136                  *
7137                  * We depend on the HW RC6 power context save/restore
7138                  * mechanism when entering D3 through runtime PM suspend. So
7139                  * disable RPM until RPS/RC6 is properly setup. We can only
7140                  * get here via the driver load/system resume/runtime resume
7141                  * paths, so the _noresume version is enough (and in case of
7142                  * runtime resume it's necessary).
7143                  */
7144                 if (queue_delayed_work(dev_priv->wq,
7145                                        &dev_priv->rps.autoenable_work,
7146                                        round_jiffies_up_relative(HZ)))
7147                         intel_runtime_pm_get_noresume(dev_priv);
7148         }
7149 }
7150
7151 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
7152 {
7153         /*
7154          * On Ibex Peak and Cougar Point, we need to disable clock
7155          * gating for the panel power sequencer or it will fail to
7156          * start up when no ports are active.
7157          */
7158         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7159 }
7160
7161 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
7162 {
7163         enum pipe pipe;
7164
7165         for_each_pipe(dev_priv, pipe) {
7166                 I915_WRITE(DSPCNTR(pipe),
7167                            I915_READ(DSPCNTR(pipe)) |
7168                            DISPPLANE_TRICKLE_FEED_DISABLE);
7169
7170                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
7171                 POSTING_READ(DSPSURF(pipe));
7172         }
7173 }
7174
7175 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
7176 {
7177         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
7178         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
7179         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
7180
7181         /*
7182          * Don't touch WM1S_LP_EN here.
7183          * Doing so could cause underruns.
7184          */
7185 }
7186
7187 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
7188 {
7189         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7190
7191         /*
7192          * Required for FBC
7193          * WaFbcDisableDpfcClockGating:ilk
7194          */
7195         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
7196                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
7197                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
7198
7199         I915_WRITE(PCH_3DCGDIS0,
7200                    MARIUNIT_CLOCK_GATE_DISABLE |
7201                    SVSMUNIT_CLOCK_GATE_DISABLE);
7202         I915_WRITE(PCH_3DCGDIS1,
7203                    VFMUNIT_CLOCK_GATE_DISABLE);
7204
7205         /*
7206          * According to the spec the following bits should be set in
7207          * order to enable memory self-refresh
7208          * The bit 22/21 of 0x42004
7209          * The bit 5 of 0x42020
7210          * The bit 15 of 0x45000
7211          */
7212         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7213                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
7214                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7215         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
7216         I915_WRITE(DISP_ARB_CTL,
7217                    (I915_READ(DISP_ARB_CTL) |
7218                     DISP_FBC_WM_DIS));
7219
7220         ilk_init_lp_watermarks(dev_priv);
7221
7222         /*
7223          * Based on the document from hardware guys the following bits
7224          * should be set unconditionally in order to enable FBC.
7225          * The bit 22 of 0x42000
7226          * The bit 22 of 0x42004
7227          * The bit 7,8,9 of 0x42020.
7228          */
7229         if (IS_IRONLAKE_M(dev_priv)) {
7230                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
7231                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7232                            I915_READ(ILK_DISPLAY_CHICKEN1) |
7233                            ILK_FBCQ_DIS);
7234                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7235                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7236                            ILK_DPARB_GATE);
7237         }
7238
7239         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7240
7241         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7242                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7243                    ILK_ELPIN_409_SELECT);
7244         I915_WRITE(_3D_CHICKEN2,
7245                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7246                    _3D_CHICKEN2_WM_READ_PIPELINED);
7247
7248         /* WaDisableRenderCachePipelinedFlush:ilk */
7249         I915_WRITE(CACHE_MODE_0,
7250                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7251
7252         /* WaDisable_RenderCache_OperationalFlush:ilk */
7253         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7254
7255         g4x_disable_trickle_feed(dev_priv);
7256
7257         ibx_init_clock_gating(dev_priv);
7258 }
7259
7260 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
7261 {
7262         int pipe;
7263         uint32_t val;
7264
7265         /*
7266          * On Ibex Peak and Cougar Point, we need to disable clock
7267          * gating for the panel power sequencer or it will fail to
7268          * start up when no ports are active.
7269          */
7270         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
7271                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
7272                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
7273         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7274                    DPLS_EDP_PPS_FIX_DIS);
7275         /* The below fixes the weird display corruption, a few pixels shifted
7276          * downward, on (only) LVDS of some HP laptops with IVY.
7277          */
7278         for_each_pipe(dev_priv, pipe) {
7279                 val = I915_READ(TRANS_CHICKEN2(pipe));
7280                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
7281                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7282                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
7283                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7284                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
7285                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7286                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
7287                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
7288         }
7289         /* WADP0ClockGatingDisable */
7290         for_each_pipe(dev_priv, pipe) {
7291                 I915_WRITE(TRANS_CHICKEN1(pipe),
7292                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7293         }
7294 }
7295
7296 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
7297 {
7298         uint32_t tmp;
7299
7300         tmp = I915_READ(MCH_SSKPD);
7301         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7302                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7303                               tmp);
7304 }
7305
7306 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7307 {
7308         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7309
7310         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7311
7312         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7313                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7314                    ILK_ELPIN_409_SELECT);
7315
7316         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7317         I915_WRITE(_3D_CHICKEN,
7318                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7319
7320         /* WaDisable_RenderCache_OperationalFlush:snb */
7321         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7322
7323         /*
7324          * BSpec recoomends 8x4 when MSAA is used,
7325          * however in practice 16x4 seems fastest.
7326          *
7327          * Note that PS/WM thread counts depend on the WIZ hashing
7328          * disable bit, which we don't touch here, but it's good
7329          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7330          */
7331         I915_WRITE(GEN6_GT_MODE,
7332                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7333
7334         ilk_init_lp_watermarks(dev_priv);
7335
7336         I915_WRITE(CACHE_MODE_0,
7337                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7338
7339         I915_WRITE(GEN6_UCGCTL1,
7340                    I915_READ(GEN6_UCGCTL1) |
7341                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7342                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7343
7344         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7345          * gating disable must be set.  Failure to set it results in
7346          * flickering pixels due to Z write ordering failures after
7347          * some amount of runtime in the Mesa "fire" demo, and Unigine
7348          * Sanctuary and Tropics, and apparently anything else with
7349          * alpha test or pixel discard.
7350          *
7351          * According to the spec, bit 11 (RCCUNIT) must also be set,
7352          * but we didn't debug actual testcases to find it out.
7353          *
7354          * WaDisableRCCUnitClockGating:snb
7355          * WaDisableRCPBUnitClockGating:snb
7356          */
7357         I915_WRITE(GEN6_UCGCTL2,
7358                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7359                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7360
7361         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7362         I915_WRITE(_3D_CHICKEN3,
7363                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7364
7365         /*
7366          * Bspec says:
7367          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7368          * 3DSTATE_SF number of SF output attributes is more than 16."
7369          */
7370         I915_WRITE(_3D_CHICKEN3,
7371                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7372
7373         /*
7374          * According to the spec the following bits should be
7375          * set in order to enable memory self-refresh and fbc:
7376          * The bit21 and bit22 of 0x42000
7377          * The bit21 and bit22 of 0x42004
7378          * The bit5 and bit7 of 0x42020
7379          * The bit14 of 0x70180
7380          * The bit14 of 0x71180
7381          *
7382          * WaFbcAsynchFlipDisableFbcQueue:snb
7383          */
7384         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7385                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7386                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7387         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7388                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7389                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7390         I915_WRITE(ILK_DSPCLK_GATE_D,
7391                    I915_READ(ILK_DSPCLK_GATE_D) |
7392                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7393                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7394
7395         g4x_disable_trickle_feed(dev_priv);
7396
7397         cpt_init_clock_gating(dev_priv);
7398
7399         gen6_check_mch_setup(dev_priv);
7400 }
7401
7402 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7403 {
7404         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7405
7406         /*
7407          * WaVSThreadDispatchOverride:ivb,vlv
7408          *
7409          * This actually overrides the dispatch
7410          * mode for all thread types.
7411          */
7412         reg &= ~GEN7_FF_SCHED_MASK;
7413         reg |= GEN7_FF_TS_SCHED_HW;
7414         reg |= GEN7_FF_VS_SCHED_HW;
7415         reg |= GEN7_FF_DS_SCHED_HW;
7416
7417         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7418 }
7419
7420 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7421 {
7422         /*
7423          * TODO: this bit should only be enabled when really needed, then
7424          * disabled when not needed anymore in order to save power.
7425          */
7426         if (HAS_PCH_LPT_LP(dev_priv))
7427                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7428                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7429                            PCH_LP_PARTITION_LEVEL_DISABLE);
7430
7431         /* WADPOClockGatingDisable:hsw */
7432         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7433                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7434                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7435 }
7436
7437 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7438 {
7439         if (HAS_PCH_LPT_LP(dev_priv)) {
7440                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7441
7442                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7443                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7444         }
7445 }
7446
7447 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7448                                    int general_prio_credits,
7449                                    int high_prio_credits)
7450 {
7451         u32 misccpctl;
7452
7453         /* WaTempDisableDOPClkGating:bdw */
7454         misccpctl = I915_READ(GEN7_MISCCPCTL);
7455         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7456
7457         I915_WRITE(GEN8_L3SQCREG1,
7458                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7459                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7460
7461         /*
7462          * Wait at least 100 clocks before re-enabling clock gating.
7463          * See the definition of L3SQCREG1 in BSpec.
7464          */
7465         POSTING_READ(GEN8_L3SQCREG1);
7466         udelay(1);
7467         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7468 }
7469
7470 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7471 {
7472         gen9_init_clock_gating(dev_priv);
7473
7474         /* WaDisableSDEUnitClockGating:kbl */
7475         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7476                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7477                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7478
7479         /* WaDisableGamClockGating:kbl */
7480         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7481                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7482                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7483
7484         /* WaFbcNukeOnHostModify:kbl */
7485         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7486                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7487 }
7488
7489 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7490 {
7491         gen9_init_clock_gating(dev_priv);
7492
7493         /* WAC6entrylatency:skl */
7494         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7495                    FBC_LLC_FULLY_OPEN);
7496
7497         /* WaFbcNukeOnHostModify:skl */
7498         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7499                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7500 }
7501
7502 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7503 {
7504         enum pipe pipe;
7505
7506         ilk_init_lp_watermarks(dev_priv);
7507
7508         /* WaSwitchSolVfFArbitrationPriority:bdw */
7509         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7510
7511         /* WaPsrDPAMaskVBlankInSRD:bdw */
7512         I915_WRITE(CHICKEN_PAR1_1,
7513                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7514
7515         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7516         for_each_pipe(dev_priv, pipe) {
7517                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7518                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7519                            BDW_DPRS_MASK_VBLANK_SRD);
7520         }
7521
7522         /* WaVSRefCountFullforceMissDisable:bdw */
7523         /* WaDSRefCountFullforceMissDisable:bdw */
7524         I915_WRITE(GEN7_FF_THREAD_MODE,
7525                    I915_READ(GEN7_FF_THREAD_MODE) &
7526                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7527
7528         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7529                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7530
7531         /* WaDisableSDEUnitClockGating:bdw */
7532         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7533                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7534
7535         /* WaProgramL3SqcReg1Default:bdw */
7536         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7537
7538         /*
7539          * WaGttCachingOffByDefault:bdw
7540          * GTT cache may not work with big pages, so if those
7541          * are ever enabled GTT cache may need to be disabled.
7542          */
7543         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7544
7545         /* WaKVMNotificationOnConfigChange:bdw */
7546         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7547                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7548
7549         lpt_init_clock_gating(dev_priv);
7550
7551         /* WaDisableDopClockGating:bdw
7552          *
7553          * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7554          * clock gating.
7555          */
7556         I915_WRITE(GEN6_UCGCTL1,
7557                    I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
7558 }
7559
7560 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7561 {
7562         ilk_init_lp_watermarks(dev_priv);
7563
7564         /* L3 caching of data atomics doesn't work -- disable it. */
7565         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7566         I915_WRITE(HSW_ROW_CHICKEN3,
7567                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7568
7569         /* This is required by WaCatErrorRejectionIssue:hsw */
7570         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7571                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7572                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7573
7574         /* WaVSRefCountFullforceMissDisable:hsw */
7575         I915_WRITE(GEN7_FF_THREAD_MODE,
7576                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7577
7578         /* WaDisable_RenderCache_OperationalFlush:hsw */
7579         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7580
7581         /* enable HiZ Raw Stall Optimization */
7582         I915_WRITE(CACHE_MODE_0_GEN7,
7583                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7584
7585         /* WaDisable4x2SubspanOptimization:hsw */
7586         I915_WRITE(CACHE_MODE_1,
7587                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7588
7589         /*
7590          * BSpec recommends 8x4 when MSAA is used,
7591          * however in practice 16x4 seems fastest.
7592          *
7593          * Note that PS/WM thread counts depend on the WIZ hashing
7594          * disable bit, which we don't touch here, but it's good
7595          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7596          */
7597         I915_WRITE(GEN7_GT_MODE,
7598                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7599
7600         /* WaSampleCChickenBitEnable:hsw */
7601         I915_WRITE(HALF_SLICE_CHICKEN3,
7602                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7603
7604         /* WaSwitchSolVfFArbitrationPriority:hsw */
7605         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7606
7607         /* WaRsPkgCStateDisplayPMReq:hsw */
7608         I915_WRITE(CHICKEN_PAR1_1,
7609                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7610
7611         lpt_init_clock_gating(dev_priv);
7612 }
7613
7614 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7615 {
7616         uint32_t snpcr;
7617
7618         ilk_init_lp_watermarks(dev_priv);
7619
7620         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7621
7622         /* WaDisableEarlyCull:ivb */
7623         I915_WRITE(_3D_CHICKEN3,
7624                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7625
7626         /* WaDisableBackToBackFlipFix:ivb */
7627         I915_WRITE(IVB_CHICKEN3,
7628                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7629                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7630
7631         /* WaDisablePSDDualDispatchEnable:ivb */
7632         if (IS_IVB_GT1(dev_priv))
7633                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7634                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7635
7636         /* WaDisable_RenderCache_OperationalFlush:ivb */
7637         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7638
7639         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7640         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7641                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7642
7643         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7644         I915_WRITE(GEN7_L3CNTLREG1,
7645                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7646         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7647                    GEN7_WA_L3_CHICKEN_MODE);
7648         if (IS_IVB_GT1(dev_priv))
7649                 I915_WRITE(GEN7_ROW_CHICKEN2,
7650                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7651         else {
7652                 /* must write both registers */
7653                 I915_WRITE(GEN7_ROW_CHICKEN2,
7654                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7655                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7656                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7657         }
7658
7659         /* WaForceL3Serialization:ivb */
7660         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7661                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7662
7663         /*
7664          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7665          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7666          */
7667         I915_WRITE(GEN6_UCGCTL2,
7668                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7669
7670         /* This is required by WaCatErrorRejectionIssue:ivb */
7671         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7672                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7673                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7674
7675         g4x_disable_trickle_feed(dev_priv);
7676
7677         gen7_setup_fixed_func_scheduler(dev_priv);
7678
7679         if (0) { /* causes HiZ corruption on ivb:gt1 */
7680                 /* enable HiZ Raw Stall Optimization */
7681                 I915_WRITE(CACHE_MODE_0_GEN7,
7682                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7683         }
7684
7685         /* WaDisable4x2SubspanOptimization:ivb */
7686         I915_WRITE(CACHE_MODE_1,
7687                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7688
7689         /*
7690          * BSpec recommends 8x4 when MSAA is used,
7691          * however in practice 16x4 seems fastest.
7692          *
7693          * Note that PS/WM thread counts depend on the WIZ hashing
7694          * disable bit, which we don't touch here, but it's good
7695          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7696          */
7697         I915_WRITE(GEN7_GT_MODE,
7698                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7699
7700         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7701         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7702         snpcr |= GEN6_MBC_SNPCR_MED;
7703         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7704
7705         if (!HAS_PCH_NOP(dev_priv))
7706                 cpt_init_clock_gating(dev_priv);
7707
7708         gen6_check_mch_setup(dev_priv);
7709 }
7710
7711 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7712 {
7713         /* WaDisableEarlyCull:vlv */
7714         I915_WRITE(_3D_CHICKEN3,
7715                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7716
7717         /* WaDisableBackToBackFlipFix:vlv */
7718         I915_WRITE(IVB_CHICKEN3,
7719                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7720                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7721
7722         /* WaPsdDispatchEnable:vlv */
7723         /* WaDisablePSDDualDispatchEnable:vlv */
7724         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7725                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7726                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7727
7728         /* WaDisable_RenderCache_OperationalFlush:vlv */
7729         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7730
7731         /* WaForceL3Serialization:vlv */
7732         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7733                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7734
7735         /* WaDisableDopClockGating:vlv */
7736         I915_WRITE(GEN7_ROW_CHICKEN2,
7737                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7738
7739         /* This is required by WaCatErrorRejectionIssue:vlv */
7740         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7741                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7742                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7743
7744         gen7_setup_fixed_func_scheduler(dev_priv);
7745
7746         /*
7747          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7748          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7749          */
7750         I915_WRITE(GEN6_UCGCTL2,
7751                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7752
7753         /* WaDisableL3Bank2xClockGate:vlv
7754          * Disabling L3 clock gating- MMIO 940c[25] = 1
7755          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7756         I915_WRITE(GEN7_UCGCTL4,
7757                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7758
7759         /*
7760          * BSpec says this must be set, even though
7761          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7762          */
7763         I915_WRITE(CACHE_MODE_1,
7764                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7765
7766         /*
7767          * BSpec recommends 8x4 when MSAA is used,
7768          * however in practice 16x4 seems fastest.
7769          *
7770          * Note that PS/WM thread counts depend on the WIZ hashing
7771          * disable bit, which we don't touch here, but it's good
7772          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7773          */
7774         I915_WRITE(GEN7_GT_MODE,
7775                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7776
7777         /*
7778          * WaIncreaseL3CreditsForVLVB0:vlv
7779          * This is the hardware default actually.
7780          */
7781         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7782
7783         /*
7784          * WaDisableVLVClockGating_VBIIssue:vlv
7785          * Disable clock gating on th GCFG unit to prevent a delay
7786          * in the reporting of vblank events.
7787          */
7788         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7789 }
7790
7791 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7792 {
7793         /* WaVSRefCountFullforceMissDisable:chv */
7794         /* WaDSRefCountFullforceMissDisable:chv */
7795         I915_WRITE(GEN7_FF_THREAD_MODE,
7796                    I915_READ(GEN7_FF_THREAD_MODE) &
7797                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7798
7799         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7800         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7801                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7802
7803         /* WaDisableCSUnitClockGating:chv */
7804         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7805                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7806
7807         /* WaDisableSDEUnitClockGating:chv */
7808         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7809                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7810
7811         /*
7812          * WaProgramL3SqcReg1Default:chv
7813          * See gfxspecs/Related Documents/Performance Guide/
7814          * LSQC Setting Recommendations.
7815          */
7816         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7817
7818         /*
7819          * GTT cache may not work with big pages, so if those
7820          * are ever enabled GTT cache may need to be disabled.
7821          */
7822         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7823 }
7824
7825 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7826 {
7827         uint32_t dspclk_gate;
7828
7829         I915_WRITE(RENCLK_GATE_D1, 0);
7830         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7831                    GS_UNIT_CLOCK_GATE_DISABLE |
7832                    CL_UNIT_CLOCK_GATE_DISABLE);
7833         I915_WRITE(RAMCLK_GATE_D, 0);
7834         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7835                 OVRUNIT_CLOCK_GATE_DISABLE |
7836                 OVCUNIT_CLOCK_GATE_DISABLE;
7837         if (IS_GM45(dev_priv))
7838                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7839         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7840
7841         /* WaDisableRenderCachePipelinedFlush */
7842         I915_WRITE(CACHE_MODE_0,
7843                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7844
7845         /* WaDisable_RenderCache_OperationalFlush:g4x */
7846         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7847
7848         g4x_disable_trickle_feed(dev_priv);
7849 }
7850
7851 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7852 {
7853         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7854         I915_WRITE(RENCLK_GATE_D2, 0);
7855         I915_WRITE(DSPCLK_GATE_D, 0);
7856         I915_WRITE(RAMCLK_GATE_D, 0);
7857         I915_WRITE16(DEUC, 0);
7858         I915_WRITE(MI_ARB_STATE,
7859                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7860
7861         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7862         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7863 }
7864
7865 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7866 {
7867         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7868                    I965_RCC_CLOCK_GATE_DISABLE |
7869                    I965_RCPB_CLOCK_GATE_DISABLE |
7870                    I965_ISC_CLOCK_GATE_DISABLE |
7871                    I965_FBC_CLOCK_GATE_DISABLE);
7872         I915_WRITE(RENCLK_GATE_D2, 0);
7873         I915_WRITE(MI_ARB_STATE,
7874                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7875
7876         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7877         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7878 }
7879
7880 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7881 {
7882         u32 dstate = I915_READ(D_STATE);
7883
7884         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7885                 DSTATE_DOT_CLOCK_GATING;
7886         I915_WRITE(D_STATE, dstate);
7887
7888         if (IS_PINEVIEW(dev_priv))
7889                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7890
7891         /* IIR "flip pending" means done if this bit is set */
7892         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7893
7894         /* interrupts should cause a wake up from C3 */
7895         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7896
7897         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7898         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7899
7900         I915_WRITE(MI_ARB_STATE,
7901                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7902 }
7903
7904 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7905 {
7906         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7907
7908         /* interrupts should cause a wake up from C3 */
7909         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7910                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7911
7912         I915_WRITE(MEM_MODE,
7913                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7914 }
7915
7916 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7917 {
7918         I915_WRITE(MEM_MODE,
7919                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7920                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7921 }
7922
7923 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7924 {
7925         dev_priv->display.init_clock_gating(dev_priv);
7926 }
7927
7928 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7929 {
7930         if (HAS_PCH_LPT(dev_priv))
7931                 lpt_suspend_hw(dev_priv);
7932 }
7933
7934 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7935 {
7936         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7937 }
7938
7939 /**
7940  * intel_init_clock_gating_hooks - setup the clock gating hooks
7941  * @dev_priv: device private
7942  *
7943  * Setup the hooks that configure which clocks of a given platform can be
7944  * gated and also apply various GT and display specific workarounds for these
7945  * platforms. Note that some GT specific workarounds are applied separately
7946  * when GPU contexts or batchbuffers start their execution.
7947  */
7948 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7949 {
7950         if (IS_SKYLAKE(dev_priv))
7951                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7952         else if (IS_KABYLAKE(dev_priv))
7953                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7954         else if (IS_BROXTON(dev_priv))
7955                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7956         else if (IS_GEMINILAKE(dev_priv))
7957                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
7958         else if (IS_BROADWELL(dev_priv))
7959                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7960         else if (IS_CHERRYVIEW(dev_priv))
7961                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7962         else if (IS_HASWELL(dev_priv))
7963                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7964         else if (IS_IVYBRIDGE(dev_priv))
7965                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7966         else if (IS_VALLEYVIEW(dev_priv))
7967                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7968         else if (IS_GEN6(dev_priv))
7969                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7970         else if (IS_GEN5(dev_priv))
7971                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7972         else if (IS_G4X(dev_priv))
7973                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7974         else if (IS_I965GM(dev_priv))
7975                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7976         else if (IS_I965G(dev_priv))
7977                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7978         else if (IS_GEN3(dev_priv))
7979                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7980         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7981                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7982         else if (IS_GEN2(dev_priv))
7983                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7984         else {
7985                 MISSING_CASE(INTEL_DEVID(dev_priv));
7986                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7987         }
7988 }
7989
7990 /* Set up chip specific power management-related functions */
7991 void intel_init_pm(struct drm_i915_private *dev_priv)
7992 {
7993         intel_fbc_init(dev_priv);
7994
7995         /* For cxsr */
7996         if (IS_PINEVIEW(dev_priv))
7997                 i915_pineview_get_mem_freq(dev_priv);
7998         else if (IS_GEN5(dev_priv))
7999                 i915_ironlake_get_mem_freq(dev_priv);
8000
8001         /* For FIFO watermark updates */
8002         if (INTEL_GEN(dev_priv) >= 9) {
8003                 skl_setup_wm_latency(dev_priv);
8004                 dev_priv->display.initial_watermarks = skl_initial_wm;
8005                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
8006                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
8007         } else if (HAS_PCH_SPLIT(dev_priv)) {
8008                 ilk_setup_wm_latency(dev_priv);
8009
8010                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
8011                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
8012                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
8013                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
8014                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
8015                         dev_priv->display.compute_intermediate_wm =
8016                                 ilk_compute_intermediate_wm;
8017                         dev_priv->display.initial_watermarks =
8018                                 ilk_initial_watermarks;
8019                         dev_priv->display.optimize_watermarks =
8020                                 ilk_optimize_watermarks;
8021                 } else {
8022                         DRM_DEBUG_KMS("Failed to read display plane latency. "
8023                                       "Disable CxSR\n");
8024                 }
8025         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8026                 vlv_setup_wm_latency(dev_priv);
8027                 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
8028                 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
8029                 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
8030                 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
8031                 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
8032         } else if (IS_PINEVIEW(dev_priv)) {
8033                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
8034                                             dev_priv->is_ddr3,
8035                                             dev_priv->fsb_freq,
8036                                             dev_priv->mem_freq)) {
8037                         DRM_INFO("failed to find known CxSR latency "
8038                                  "(found ddr%s fsb freq %d, mem freq %d), "
8039                                  "disabling CxSR\n",
8040                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8041                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8042                         /* Disable CxSR and never update its watermark again */
8043                         intel_set_memory_cxsr(dev_priv, false);
8044                         dev_priv->display.update_wm = NULL;
8045                 } else
8046                         dev_priv->display.update_wm = pineview_update_wm;
8047         } else if (IS_G4X(dev_priv)) {
8048                 dev_priv->display.update_wm = g4x_update_wm;
8049         } else if (IS_GEN4(dev_priv)) {
8050                 dev_priv->display.update_wm = i965_update_wm;
8051         } else if (IS_GEN3(dev_priv)) {
8052                 dev_priv->display.update_wm = i9xx_update_wm;
8053                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8054         } else if (IS_GEN2(dev_priv)) {
8055                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
8056                         dev_priv->display.update_wm = i845_update_wm;
8057                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8058                 } else {
8059                         dev_priv->display.update_wm = i9xx_update_wm;
8060                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8061                 }
8062         } else {
8063                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
8064         }
8065 }
8066
8067 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
8068 {
8069         uint32_t flags =
8070                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
8071
8072         switch (flags) {
8073         case GEN6_PCODE_SUCCESS:
8074                 return 0;
8075         case GEN6_PCODE_UNIMPLEMENTED_CMD:
8076         case GEN6_PCODE_ILLEGAL_CMD:
8077                 return -ENXIO;
8078         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8079         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8080                 return -EOVERFLOW;
8081         case GEN6_PCODE_TIMEOUT:
8082                 return -ETIMEDOUT;
8083         default:
8084                 MISSING_CASE(flags);
8085                 return 0;
8086         }
8087 }
8088
8089 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
8090 {
8091         uint32_t flags =
8092                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
8093
8094         switch (flags) {
8095         case GEN6_PCODE_SUCCESS:
8096                 return 0;
8097         case GEN6_PCODE_ILLEGAL_CMD:
8098                 return -ENXIO;
8099         case GEN7_PCODE_TIMEOUT:
8100                 return -ETIMEDOUT;
8101         case GEN7_PCODE_ILLEGAL_DATA:
8102                 return -EINVAL;
8103         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8104                 return -EOVERFLOW;
8105         default:
8106                 MISSING_CASE(flags);
8107                 return 0;
8108         }
8109 }
8110
8111 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
8112 {
8113         int status;
8114
8115         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
8116
8117         /* GEN6_PCODE_* are outside of the forcewake domain, we can
8118          * use te fw I915_READ variants to reduce the amount of work
8119          * required when reading/writing.
8120          */
8121
8122         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
8123                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
8124                 return -EAGAIN;
8125         }
8126
8127         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
8128         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
8129         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
8130
8131         if (__intel_wait_for_register_fw(dev_priv,
8132                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
8133                                          500, 0, NULL)) {
8134                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
8135                 return -ETIMEDOUT;
8136         }
8137
8138         *val = I915_READ_FW(GEN6_PCODE_DATA);
8139         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
8140
8141         if (INTEL_GEN(dev_priv) > 6)
8142                 status = gen7_check_mailbox_status(dev_priv);
8143         else
8144                 status = gen6_check_mailbox_status(dev_priv);
8145
8146         if (status) {
8147                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
8148                                  status);
8149                 return status;
8150         }
8151
8152         return 0;
8153 }
8154
8155 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
8156                             u32 mbox, u32 val)
8157 {
8158         int status;
8159
8160         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
8161
8162         /* GEN6_PCODE_* are outside of the forcewake domain, we can
8163          * use te fw I915_READ variants to reduce the amount of work
8164          * required when reading/writing.
8165          */
8166
8167         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
8168                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
8169                 return -EAGAIN;
8170         }
8171
8172         I915_WRITE_FW(GEN6_PCODE_DATA, val);
8173         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
8174         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
8175
8176         if (__intel_wait_for_register_fw(dev_priv,
8177                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
8178                                          500, 0, NULL)) {
8179                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
8180                 return -ETIMEDOUT;
8181         }
8182
8183         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
8184
8185         if (INTEL_GEN(dev_priv) > 6)
8186                 status = gen7_check_mailbox_status(dev_priv);
8187         else
8188                 status = gen6_check_mailbox_status(dev_priv);
8189
8190         if (status) {
8191                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
8192                                  status);
8193                 return status;
8194         }
8195
8196         return 0;
8197 }
8198
8199 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
8200                                   u32 request, u32 reply_mask, u32 reply,
8201                                   u32 *status)
8202 {
8203         u32 val = request;
8204
8205         *status = sandybridge_pcode_read(dev_priv, mbox, &val);
8206
8207         return *status || ((val & reply_mask) == reply);
8208 }
8209
8210 /**
8211  * skl_pcode_request - send PCODE request until acknowledgment
8212  * @dev_priv: device private
8213  * @mbox: PCODE mailbox ID the request is targeted for
8214  * @request: request ID
8215  * @reply_mask: mask used to check for request acknowledgment
8216  * @reply: value used to check for request acknowledgment
8217  * @timeout_base_ms: timeout for polling with preemption enabled
8218  *
8219  * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
8220  * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
8221  * The request is acknowledged once the PCODE reply dword equals @reply after
8222  * applying @reply_mask. Polling is first attempted with preemption enabled
8223  * for @timeout_base_ms and if this times out for another 50 ms with
8224  * preemption disabled.
8225  *
8226  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
8227  * other error as reported by PCODE.
8228  */
8229 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
8230                       u32 reply_mask, u32 reply, int timeout_base_ms)
8231 {
8232         u32 status;
8233         int ret;
8234
8235         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
8236
8237 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
8238                                    &status)
8239
8240         /*
8241          * Prime the PCODE by doing a request first. Normally it guarantees
8242          * that a subsequent request, at most @timeout_base_ms later, succeeds.
8243          * _wait_for() doesn't guarantee when its passed condition is evaluated
8244          * first, so send the first request explicitly.
8245          */
8246         if (COND) {
8247                 ret = 0;
8248                 goto out;
8249         }
8250         ret = _wait_for(COND, timeout_base_ms * 1000, 10);
8251         if (!ret)
8252                 goto out;
8253
8254         /*
8255          * The above can time out if the number of requests was low (2 in the
8256          * worst case) _and_ PCODE was busy for some reason even after a
8257          * (queued) request and @timeout_base_ms delay. As a workaround retry
8258          * the poll with preemption disabled to maximize the number of
8259          * requests. Increase the timeout from @timeout_base_ms to 50ms to
8260          * account for interrupts that could reduce the number of these
8261          * requests, and for any quirks of the PCODE firmware that delays
8262          * the request completion.
8263          */
8264         DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
8265         WARN_ON_ONCE(timeout_base_ms > 3);
8266         preempt_disable();
8267         ret = wait_for_atomic(COND, 50);
8268         preempt_enable();
8269
8270 out:
8271         return ret ? ret : status;
8272 #undef COND
8273 }
8274
8275 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
8276 {
8277         /*
8278          * N = val - 0xb7
8279          * Slow = Fast = GPLL ref * N
8280          */
8281         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
8282 }
8283
8284 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
8285 {
8286         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
8287 }
8288
8289 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
8290 {
8291         /*
8292          * N = val / 2
8293          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
8294          */
8295         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
8296 }
8297
8298 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
8299 {
8300         /* CHV needs even values */
8301         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
8302 }
8303
8304 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
8305 {
8306         if (IS_GEN9(dev_priv))
8307                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
8308                                          GEN9_FREQ_SCALER);
8309         else if (IS_CHERRYVIEW(dev_priv))
8310                 return chv_gpu_freq(dev_priv, val);
8311         else if (IS_VALLEYVIEW(dev_priv))
8312                 return byt_gpu_freq(dev_priv, val);
8313         else
8314                 return val * GT_FREQUENCY_MULTIPLIER;
8315 }
8316
8317 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
8318 {
8319         if (IS_GEN9(dev_priv))
8320                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
8321                                          GT_FREQUENCY_MULTIPLIER);
8322         else if (IS_CHERRYVIEW(dev_priv))
8323                 return chv_freq_opcode(dev_priv, val);
8324         else if (IS_VALLEYVIEW(dev_priv))
8325                 return byt_freq_opcode(dev_priv, val);
8326         else
8327                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
8328 }
8329
8330 struct request_boost {
8331         struct work_struct work;
8332         struct drm_i915_gem_request *req;
8333 };
8334
8335 static void __intel_rps_boost_work(struct work_struct *work)
8336 {
8337         struct request_boost *boost = container_of(work, struct request_boost, work);
8338         struct drm_i915_gem_request *req = boost->req;
8339
8340         if (!i915_gem_request_completed(req))
8341                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
8342
8343         i915_gem_request_put(req);
8344         kfree(boost);
8345 }
8346
8347 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8348 {
8349         struct request_boost *boost;
8350
8351         if (req == NULL || INTEL_GEN(req->i915) < 6)
8352                 return;
8353
8354         if (i915_gem_request_completed(req))
8355                 return;
8356
8357         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8358         if (boost == NULL)
8359                 return;
8360
8361         boost->req = i915_gem_request_get(req);
8362
8363         INIT_WORK(&boost->work, __intel_rps_boost_work);
8364         queue_work(req->i915->wq, &boost->work);
8365 }
8366
8367 void intel_pm_setup(struct drm_i915_private *dev_priv)
8368 {
8369         mutex_init(&dev_priv->rps.hw_lock);
8370         spin_lock_init(&dev_priv->rps.client_lock);
8371
8372         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8373                           __intel_autoenable_gt_powersave);
8374         INIT_LIST_HEAD(&dev_priv->rps.clients);
8375
8376         dev_priv->pm.suspended = false;
8377         atomic_set(&dev_priv->pm.wakeref_count, 0);
8378 }
8379
8380 static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
8381                              const i915_reg_t reg)
8382 {
8383         u32 lower, upper, tmp;
8384         int loop = 2;
8385
8386         /* The register accessed do not need forcewake. We borrow
8387          * uncore lock to prevent concurrent access to range reg.
8388          */
8389         spin_lock_irq(&dev_priv->uncore.lock);
8390
8391         /* vlv and chv residency counters are 40 bits in width.
8392          * With a control bit, we can choose between upper or lower
8393          * 32bit window into this counter.
8394          *
8395          * Although we always use the counter in high-range mode elsewhere,
8396          * userspace may attempt to read the value before rc6 is initialised,
8397          * before we have set the default VLV_COUNTER_CONTROL value. So always
8398          * set the high bit to be safe.
8399          */
8400         I915_WRITE_FW(VLV_COUNTER_CONTROL,
8401                       _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
8402         upper = I915_READ_FW(reg);
8403         do {
8404                 tmp = upper;
8405
8406                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
8407                               _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
8408                 lower = I915_READ_FW(reg);
8409
8410                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
8411                               _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
8412                 upper = I915_READ_FW(reg);
8413         } while (upper != tmp && --loop);
8414
8415         /* Everywhere else we always use VLV_COUNTER_CONTROL with the
8416          * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
8417          * now.
8418          */
8419
8420         spin_unlock_irq(&dev_priv->uncore.lock);
8421
8422         return lower | (u64)upper << 8;
8423 }
8424
8425 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
8426                            const i915_reg_t reg)
8427 {
8428         u64 time_hw, units, div;
8429
8430         if (!intel_enable_rc6())
8431                 return 0;
8432
8433         intel_runtime_pm_get(dev_priv);
8434
8435         /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
8436         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8437                 units = 1000;
8438                 div = dev_priv->czclk_freq;
8439
8440                 time_hw = vlv_residency_raw(dev_priv, reg);
8441         } else if (IS_GEN9_LP(dev_priv)) {
8442                 units = 1000;
8443                 div = 1200;             /* 833.33ns */
8444
8445                 time_hw = I915_READ(reg);
8446         } else {
8447                 units = 128000; /* 1.28us */
8448                 div = 100000;
8449
8450                 time_hw = I915_READ(reg);
8451         }
8452
8453         intel_runtime_pm_put(dev_priv);
8454         return DIV_ROUND_UP_ULL(time_hw * units, div);
8455 }