drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * DOC: RC6
  36  *
  37  * RC6 is a special power stage which allows the GPU to enter an very
  38  * low-voltage mode when idle, using down to 0V while at this stage.  This
  39  * stage is entered automatically when the GPU is idle when RC6 support is
  40  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  41  *
  42  * There are different RC6 modes available in Intel GPU, which differentiate
  43  * among each other with the latency required to enter and leave RC6 and
  44  * voltage consumed by the GPU in different states.
  45  *
  46  * The combination of the following flags define which states GPU is allowed
  47  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  48  * RC6pp is deepest RC6. Their support by hardware varies according to the
  49  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  50  * which brings the most power savings; deeper states save more power, but
  51  * require higher latency to switch to and wake up.
  52  */
  53 #define INTEL_RC6_ENABLE                        (1<<0)
  54 #define INTEL_RC6p_ENABLE                       (1<<1)
  55 #define INTEL_RC6pp_ENABLE                      (1<<2)
  56
  57 static void bxt_init_clock_gating(struct drm_device *dev)
  58 {
  59         struct drm_i915_private *dev_priv = dev->dev_private;
  60
  61         /* WaDisableSDEUnitClockGating:bxt */
  62         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  63                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  64
  65         /*
  66          * FIXME:
  67          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  68          */
  69         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  70                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  71
  72         /*
  73          * Wa: Backlight PWM may stop in the asserted state, causing backlight
  74          * to stay fully on.
  75          */
  76         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
  77                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
  78                            PWM1_GATING_DIS | PWM2_GATING_DIS);
  79 }
  80
  81 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84         u32 tmp;
  85
  86         tmp = I915_READ(CLKCFG);
  87
  88         switch (tmp & CLKCFG_FSB_MASK) {
  89         case CLKCFG_FSB_533:
  90                 dev_priv->fsb_freq = 533; /* 133*4 */
  91                 break;
  92         case CLKCFG_FSB_800:
  93                 dev_priv->fsb_freq = 800; /* 200*4 */
  94                 break;
  95         case CLKCFG_FSB_667:
  96                 dev_priv->fsb_freq =  667; /* 167*4 */
  97                 break;
  98         case CLKCFG_FSB_400:
  99                 dev_priv->fsb_freq = 400; /* 100*4 */
 100                 break;
 101         }
 102
 103         switch (tmp & CLKCFG_MEM_MASK) {
 104         case CLKCFG_MEM_533:
 105                 dev_priv->mem_freq = 533;
 106                 break;
 107         case CLKCFG_MEM_667:
 108                 dev_priv->mem_freq = 667;
 109                 break;
 110         case CLKCFG_MEM_800:
 111                 dev_priv->mem_freq = 800;
 112                 break;
 113         }
 114
 115         /* detect pineview DDR3 setting */
 116         tmp = I915_READ(CSHRDDR3CTL);
 117         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 118 }
 119
 120 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         u16 ddrpll, csipll;
 124
 125         ddrpll = I915_READ16(DDRMPLL1);
 126         csipll = I915_READ16(CSIPLL0);
 127
 128         switch (ddrpll & 0xff) {
 129         case 0xc:
 130                 dev_priv->mem_freq = 800;
 131                 break;
 132         case 0x10:
 133                 dev_priv->mem_freq = 1066;
 134                 break;
 135         case 0x14:
 136                 dev_priv->mem_freq = 1333;
 137                 break;
 138         case 0x18:
 139                 dev_priv->mem_freq = 1600;
 140                 break;
 141         default:
 142                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 143                                  ddrpll & 0xff);
 144                 dev_priv->mem_freq = 0;
 145                 break;
 146         }
 147
 148         dev_priv->ips.r_t = dev_priv->mem_freq;
 149
 150         switch (csipll & 0x3ff) {
 151         case 0x00c:
 152                 dev_priv->fsb_freq = 3200;
 153                 break;
 154         case 0x00e:
 155                 dev_priv->fsb_freq = 3733;
 156                 break;
 157         case 0x010:
 158                 dev_priv->fsb_freq = 4266;
 159                 break;
 160         case 0x012:
 161                 dev_priv->fsb_freq = 4800;
 162                 break;
 163         case 0x014:
 164                 dev_priv->fsb_freq = 5333;
 165                 break;
 166         case 0x016:
 167                 dev_priv->fsb_freq = 5866;
 168                 break;
 169         case 0x018:
 170                 dev_priv->fsb_freq = 6400;
 171                 break;
 172         default:
 173                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 174                                  csipll & 0x3ff);
 175                 dev_priv->fsb_freq = 0;
 176                 break;
 177         }
 178
 179         if (dev_priv->fsb_freq == 3200) {
 180                 dev_priv->ips.c_m = 0;
 181         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 182                 dev_priv->ips.c_m = 1;
 183         } else {
 184                 dev_priv->ips.c_m = 2;
 185         }
 186 }
 187
 188 static const struct cxsr_latency cxsr_latency_table[] = {
 189         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 190         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 191         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 192         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 193         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 194
 195         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 196         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 197         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 198         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 199         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 200
 201         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 202         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 203         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 204         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 205         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 206
 207         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 208         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 209         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 210         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 211         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 212
 213         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 214         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 215         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 216         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 217         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 218
 219         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 220         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 221         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 222         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 223         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 224 };
 225
 226 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 227                                                          int is_ddr3,
 228                                                          int fsb,
 229                                                          int mem)
 230 {
 231         const struct cxsr_latency *latency;
 232         int i;
 233
 234         if (fsb == 0 || mem == 0)
 235                 return NULL;
 236
 237         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 238                 latency = &cxsr_latency_table[i];
 239                 if (is_desktop == latency->is_desktop &&
 240                     is_ddr3 == latency->is_ddr3 &&
 241                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 242                         return latency;
 243         }
 244
 245         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 246
 247         return NULL;
 248 }
 249
 250 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 251 {
 252         u32 val;
 253
 254         mutex_lock(&dev_priv->rps.hw_lock);
 255
 256         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 257         if (enable)
 258                 val &= ~FORCE_DDR_HIGH_FREQ;
 259         else
 260                 val |= FORCE_DDR_HIGH_FREQ;
 261         val &= ~FORCE_DDR_LOW_FREQ;
 262         val |= FORCE_DDR_FREQ_REQ_ACK;
 263         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 264
 265         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 266                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 267                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 268
 269         mutex_unlock(&dev_priv->rps.hw_lock);
 270 }
 271
 272 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 273 {
 274         u32 val;
 275
 276         mutex_lock(&dev_priv->rps.hw_lock);
 277
 278         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 279         if (enable)
 280                 val |= DSP_MAXFIFO_PM5_ENABLE;
 281         else
 282                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 283         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 284
 285         mutex_unlock(&dev_priv->rps.hw_lock);
 286 }
 287
 288 #define FW_WM(value, plane) \
 289         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 290
 291 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 292 {
 293         struct drm_device *dev = dev_priv->dev;
 294         u32 val;
 295
 296         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 297                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 298                 POSTING_READ(FW_BLC_SELF_VLV);
 299                 dev_priv->wm.vlv.cxsr = enable;
 300         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 301                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 302                 POSTING_READ(FW_BLC_SELF);
 303         } else if (IS_PINEVIEW(dev)) {
 304                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 305                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 306                 I915_WRITE(DSPFW3, val);
 307                 POSTING_READ(DSPFW3);
 308         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 309                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 310                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 311                 I915_WRITE(FW_BLC_SELF, val);
 312                 POSTING_READ(FW_BLC_SELF);
 313         } else if (IS_I915GM(dev)) {
 314                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 315                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 316                 I915_WRITE(INSTPM, val);
 317                 POSTING_READ(INSTPM);
 318         } else {
 319                 return;
 320         }
 321
 322         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 323                       enable ? "enabled" : "disabled");
 324 }
 325
 326
 327 /*
 328  * Latency for FIFO fetches is dependent on several factors:
 329  *   - memory configuration (speed, channels)
 330  *   - chipset
 331  *   - current MCH state
 332  * It can be fairly high in some situations, so here we assume a fairly
 333  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 334  * set this value too high, the FIFO will fetch frequently to stay full)
 335  * and power consumption (set it too low to save power and we might see
 336  * FIFO underruns and display "flicker").
 337  *
 338  * A value of 5us seems to be a good balance; safe for very low end
 339  * platforms but not overly aggressive on lower latency configs.
 340  */
 341 static const int pessimal_latency_ns = 5000;
 342
 343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 344         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 345
 346 static int vlv_get_fifo_size(struct drm_device *dev,
 347                               enum pipe pipe, int plane)
 348 {
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         int sprite0_start, sprite1_start, size;
 351
 352         switch (pipe) {
 353                 uint32_t dsparb, dsparb2, dsparb3;
 354         case PIPE_A:
 355                 dsparb = I915_READ(DSPARB);
 356                 dsparb2 = I915_READ(DSPARB2);
 357                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 358                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 359                 break;
 360         case PIPE_B:
 361                 dsparb = I915_READ(DSPARB);
 362                 dsparb2 = I915_READ(DSPARB2);
 363                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 364                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 365                 break;
 366         case PIPE_C:
 367                 dsparb2 = I915_READ(DSPARB2);
 368                 dsparb3 = I915_READ(DSPARB3);
 369                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 370                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 371                 break;
 372         default:
 373                 return 0;
 374         }
 375
 376         switch (plane) {
 377         case 0:
 378                 size = sprite0_start;
 379                 break;
 380         case 1:
 381                 size = sprite1_start - sprite0_start;
 382                 break;
 383         case 2:
 384                 size = 512 - 1 - sprite1_start;
 385                 break;
 386         default:
 387                 return 0;
 388         }
 389
 390         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 391                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 392                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 393                       size);
 394
 395         return size;
 396 }
 397
 398 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 399 {
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         uint32_t dsparb = I915_READ(DSPARB);
 402         int size;
 403
 404         size = dsparb & 0x7f;
 405         if (plane)
 406                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 407
 408         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 409                       plane ? "B" : "A", size);
 410
 411         return size;
 412 }
 413
 414 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         uint32_t dsparb = I915_READ(DSPARB);
 418         int size;
 419
 420         size = dsparb & 0x1ff;
 421         if (plane)
 422                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 423         size >>= 1; /* Convert to cachelines */
 424
 425         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 426                       plane ? "B" : "A", size);
 427
 428         return size;
 429 }
 430
 431 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 432 {
 433         struct drm_i915_private *dev_priv = dev->dev_private;
 434         uint32_t dsparb = I915_READ(DSPARB);
 435         int size;
 436
 437         size = dsparb & 0x7f;
 438         size >>= 2; /* Convert to cachelines */
 439
 440         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 441                       plane ? "B" : "A",
 442                       size);
 443
 444         return size;
 445 }
 446
 447 /* Pineview has different values for various configs */
 448 static const struct intel_watermark_params pineview_display_wm = {
 449         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 450         .max_wm = PINEVIEW_MAX_WM,
 451         .default_wm = PINEVIEW_DFT_WM,
 452         .guard_size = PINEVIEW_GUARD_WM,
 453         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 454 };
 455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 456         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 457         .max_wm = PINEVIEW_MAX_WM,
 458         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 459         .guard_size = PINEVIEW_GUARD_WM,
 460         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 461 };
 462 static const struct intel_watermark_params pineview_cursor_wm = {
 463         .fifo_size = PINEVIEW_CURSOR_FIFO,
 464         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 465         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 466         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 467         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 468 };
 469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 470         .fifo_size = PINEVIEW_CURSOR_FIFO,
 471         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 472         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 473         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 474         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 475 };
 476 static const struct intel_watermark_params g4x_wm_info = {
 477         .fifo_size = G4X_FIFO_SIZE,
 478         .max_wm = G4X_MAX_WM,
 479         .default_wm = G4X_MAX_WM,
 480         .guard_size = 2,
 481         .cacheline_size = G4X_FIFO_LINE_SIZE,
 482 };
 483 static const struct intel_watermark_params g4x_cursor_wm_info = {
 484         .fifo_size = I965_CURSOR_FIFO,
 485         .max_wm = I965_CURSOR_MAX_WM,
 486         .default_wm = I965_CURSOR_DFT_WM,
 487         .guard_size = 2,
 488         .cacheline_size = G4X_FIFO_LINE_SIZE,
 489 };
 490 static const struct intel_watermark_params valleyview_wm_info = {
 491         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 492         .max_wm = VALLEYVIEW_MAX_WM,
 493         .default_wm = VALLEYVIEW_MAX_WM,
 494         .guard_size = 2,
 495         .cacheline_size = G4X_FIFO_LINE_SIZE,
 496 };
 497 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 498         .fifo_size = I965_CURSOR_FIFO,
 499         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 500         .default_wm = I965_CURSOR_DFT_WM,
 501         .guard_size = 2,
 502         .cacheline_size = G4X_FIFO_LINE_SIZE,
 503 };
 504 static const struct intel_watermark_params i965_cursor_wm_info = {
 505         .fifo_size = I965_CURSOR_FIFO,
 506         .max_wm = I965_CURSOR_MAX_WM,
 507         .default_wm = I965_CURSOR_DFT_WM,
 508         .guard_size = 2,
 509         .cacheline_size = I915_FIFO_LINE_SIZE,
 510 };
 511 static const struct intel_watermark_params i945_wm_info = {
 512         .fifo_size = I945_FIFO_SIZE,
 513         .max_wm = I915_MAX_WM,
 514         .default_wm = 1,
 515         .guard_size = 2,
 516         .cacheline_size = I915_FIFO_LINE_SIZE,
 517 };
 518 static const struct intel_watermark_params i915_wm_info = {
 519         .fifo_size = I915_FIFO_SIZE,
 520         .max_wm = I915_MAX_WM,
 521         .default_wm = 1,
 522         .guard_size = 2,
 523         .cacheline_size = I915_FIFO_LINE_SIZE,
 524 };
 525 static const struct intel_watermark_params i830_a_wm_info = {
 526         .fifo_size = I855GM_FIFO_SIZE,
 527         .max_wm = I915_MAX_WM,
 528         .default_wm = 1,
 529         .guard_size = 2,
 530         .cacheline_size = I830_FIFO_LINE_SIZE,
 531 };
 532 static const struct intel_watermark_params i830_bc_wm_info = {
 533         .fifo_size = I855GM_FIFO_SIZE,
 534         .max_wm = I915_MAX_WM/2,
 535         .default_wm = 1,
 536         .guard_size = 2,
 537         .cacheline_size = I830_FIFO_LINE_SIZE,
 538 };
 539 static const struct intel_watermark_params i845_wm_info = {
 540         .fifo_size = I830_FIFO_SIZE,
 541         .max_wm = I915_MAX_WM,
 542         .default_wm = 1,
 543         .guard_size = 2,
 544         .cacheline_size = I830_FIFO_LINE_SIZE,
 545 };
 546
 547 /**
 548  * intel_calculate_wm - calculate watermark level
 549  * @clock_in_khz: pixel clock
 550  * @wm: chip FIFO params
 551  * @cpp: bytes per pixel
 552  * @latency_ns: memory latency for the platform
 553  *
 554  * Calculate the watermark level (the level at which the display plane will
 555  * start fetching from memory again).  Each chip has a different display
 556  * FIFO size and allocation, so the caller needs to figure that out and pass
 557  * in the correct intel_watermark_params structure.
 558  *
 559  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 560  * on the pixel size.  When it reaches the watermark level, it'll start
 561  * fetching FIFO line sized based chunks from memory until the FIFO fills
 562  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 563  * will occur, and a display engine hang could result.
 564  */
 565 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 566                                         const struct intel_watermark_params *wm,
 567                                         int fifo_size, int cpp,
 568                                         unsigned long latency_ns)
 569 {
 570         long entries_required, wm_size;
 571
 572         /*
 573          * Note: we need to make sure we don't overflow for various clock &
 574          * latency values.
 575          * clocks go from a few thousand to several hundred thousand.
 576          * latency is usually a few thousand
 577          */
 578         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 579                 1000;
 580         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 581
 582         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 583
 584         wm_size = fifo_size - (entries_required + wm->guard_size);
 585
 586         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 587
 588         /* Don't promote wm_size to unsigned... */
 589         if (wm_size > (long)wm->max_wm)
 590                 wm_size = wm->max_wm;
 591         if (wm_size <= 0)
 592                 wm_size = wm->default_wm;
 593
 594         /*
 595          * Bspec seems to indicate that the value shouldn't be lower than
 596          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 597          * Lets go for 8 which is the burst size since certain platforms
 598          * already use a hardcoded 8 (which is what the spec says should be
 599          * done).
 600          */
 601         if (wm_size <= 8)
 602                 wm_size = 8;
 603
 604         return wm_size;
 605 }
 606
 607 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 608 {
 609         struct drm_crtc *crtc, *enabled = NULL;
 610
 611         for_each_crtc(dev, crtc) {
 612                 if (intel_crtc_active(crtc)) {
 613                         if (enabled)
 614                                 return NULL;
 615                         enabled = crtc;
 616                 }
 617         }
 618
 619         return enabled;
 620 }
 621
 622 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 623 {
 624         struct drm_device *dev = unused_crtc->dev;
 625         struct drm_i915_private *dev_priv = dev->dev_private;
 626         struct drm_crtc *crtc;
 627         const struct cxsr_latency *latency;
 628         u32 reg;
 629         unsigned long wm;
 630
 631         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 632                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 633         if (!latency) {
 634                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 635                 intel_set_memory_cxsr(dev_priv, false);
 636                 return;
 637         }
 638
 639         crtc = single_enabled_crtc(dev);
 640         if (crtc) {
 641                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 642                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 643                 int clock = adjusted_mode->crtc_clock;
 644
 645                 /* Display SR */
 646                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 647                                         pineview_display_wm.fifo_size,
 648                                         cpp, latency->display_sr);
 649                 reg = I915_READ(DSPFW1);
 650                 reg &= ~DSPFW_SR_MASK;
 651                 reg |= FW_WM(wm, SR);
 652                 I915_WRITE(DSPFW1, reg);
 653                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 654
 655                 /* cursor SR */
 656                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 657                                         pineview_display_wm.fifo_size,
 658                                         cpp, latency->cursor_sr);
 659                 reg = I915_READ(DSPFW3);
 660                 reg &= ~DSPFW_CURSOR_SR_MASK;
 661                 reg |= FW_WM(wm, CURSOR_SR);
 662                 I915_WRITE(DSPFW3, reg);
 663
 664                 /* Display HPLL off SR */
 665                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 666                                         pineview_display_hplloff_wm.fifo_size,
 667                                         cpp, latency->display_hpll_disable);
 668                 reg = I915_READ(DSPFW3);
 669                 reg &= ~DSPFW_HPLL_SR_MASK;
 670                 reg |= FW_WM(wm, HPLL_SR);
 671                 I915_WRITE(DSPFW3, reg);
 672
 673                 /* cursor HPLL off SR */
 674                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 675                                         pineview_display_hplloff_wm.fifo_size,
 676                                         cpp, latency->cursor_hpll_disable);
 677                 reg = I915_READ(DSPFW3);
 678                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 679                 reg |= FW_WM(wm, HPLL_CURSOR);
 680                 I915_WRITE(DSPFW3, reg);
 681                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 682
 683                 intel_set_memory_cxsr(dev_priv, true);
 684         } else {
 685                 intel_set_memory_cxsr(dev_priv, false);
 686         }
 687 }
 688
 689 static bool g4x_compute_wm0(struct drm_device *dev,
 690                             int plane,
 691                             const struct intel_watermark_params *display,
 692                             int display_latency_ns,
 693                             const struct intel_watermark_params *cursor,
 694                             int cursor_latency_ns,
 695                             int *plane_wm,
 696                             int *cursor_wm)
 697 {
 698         struct drm_crtc *crtc;
 699         const struct drm_display_mode *adjusted_mode;
 700         int htotal, hdisplay, clock, cpp;
 701         int line_time_us, line_count;
 702         int entries, tlb_miss;
 703
 704         crtc = intel_get_crtc_for_plane(dev, plane);
 705         if (!intel_crtc_active(crtc)) {
 706                 *cursor_wm = cursor->guard_size;
 707                 *plane_wm = display->guard_size;
 708                 return false;
 709         }
 710
 711         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 712         clock = adjusted_mode->crtc_clock;
 713         htotal = adjusted_mode->crtc_htotal;
 714         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 715         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 716
 717         /* Use the small buffer method to calculate plane watermark */
 718         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 719         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 720         if (tlb_miss > 0)
 721                 entries += tlb_miss;
 722         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 723         *plane_wm = entries + display->guard_size;
 724         if (*plane_wm > (int)display->max_wm)
 725                 *plane_wm = display->max_wm;
 726
 727         /* Use the large buffer method to calculate cursor watermark */
 728         line_time_us = max(htotal * 1000 / clock, 1);
 729         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 730         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 731         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 732         if (tlb_miss > 0)
 733                 entries += tlb_miss;
 734         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 735         *cursor_wm = entries + cursor->guard_size;
 736         if (*cursor_wm > (int)cursor->max_wm)
 737                 *cursor_wm = (int)cursor->max_wm;
 738
 739         return true;
 740 }
 741
 742 /*
 743  * Check the wm result.
 744  *
 745  * If any calculated watermark values is larger than the maximum value that
 746  * can be programmed into the associated watermark register, that watermark
 747  * must be disabled.
 748  */
 749 static bool g4x_check_srwm(struct drm_device *dev,
 750                            int display_wm, int cursor_wm,
 751                            const struct intel_watermark_params *display,
 752                            const struct intel_watermark_params *cursor)
 753 {
 754         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 755                       display_wm, cursor_wm);
 756
 757         if (display_wm > display->max_wm) {
 758                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 759                               display_wm, display->max_wm);
 760                 return false;
 761         }
 762
 763         if (cursor_wm > cursor->max_wm) {
 764                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 765                               cursor_wm, cursor->max_wm);
 766                 return false;
 767         }
 768
 769         if (!(display_wm || cursor_wm)) {
 770                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 771                 return false;
 772         }
 773
 774         return true;
 775 }
 776
 777 static bool g4x_compute_srwm(struct drm_device *dev,
 778                              int plane,
 779                              int latency_ns,
 780                              const struct intel_watermark_params *display,
 781                              const struct intel_watermark_params *cursor,
 782                              int *display_wm, int *cursor_wm)
 783 {
 784         struct drm_crtc *crtc;
 785         const struct drm_display_mode *adjusted_mode;
 786         int hdisplay, htotal, cpp, clock;
 787         unsigned long line_time_us;
 788         int line_count, line_size;
 789         int small, large;
 790         int entries;
 791
 792         if (!latency_ns) {
 793                 *display_wm = *cursor_wm = 0;
 794                 return false;
 795         }
 796
 797         crtc = intel_get_crtc_for_plane(dev, plane);
 798         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 799         clock = adjusted_mode->crtc_clock;
 800         htotal = adjusted_mode->crtc_htotal;
 801         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 802         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 803
 804         line_time_us = max(htotal * 1000 / clock, 1);
 805         line_count = (latency_ns / line_time_us + 1000) / 1000;
 806         line_size = hdisplay * cpp;
 807
 808         /* Use the minimum of the small and large buffer method for primary */
 809         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 810         large = line_count * line_size;
 811
 812         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 813         *display_wm = entries + display->guard_size;
 814
 815         /* calculate the self-refresh watermark for display cursor */
 816         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 817         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 818         *cursor_wm = entries + cursor->guard_size;
 819
 820         return g4x_check_srwm(dev,
 821                               *display_wm, *cursor_wm,
 822                               display, cursor);
 823 }
 824
 825 #define FW_WM_VLV(value, plane) \
 826         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 827
 828 static void vlv_write_wm_values(struct intel_crtc *crtc,
 829                                 const struct vlv_wm_values *wm)
 830 {
 831         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 832         enum pipe pipe = crtc->pipe;
 833
 834         I915_WRITE(VLV_DDL(pipe),
 835                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 836                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 837                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 838                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 839
 840         I915_WRITE(DSPFW1,
 841                    FW_WM(wm->sr.plane, SR) |
 842                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 843                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 844                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 845         I915_WRITE(DSPFW2,
 846                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 847                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 848                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 849         I915_WRITE(DSPFW3,
 850                    FW_WM(wm->sr.cursor, CURSOR_SR));
 851
 852         if (IS_CHERRYVIEW(dev_priv)) {
 853                 I915_WRITE(DSPFW7_CHV,
 854                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 855                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 856                 I915_WRITE(DSPFW8_CHV,
 857                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 858                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 859                 I915_WRITE(DSPFW9_CHV,
 860                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 861                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 862                 I915_WRITE(DSPHOWM,
 863                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 864                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 865                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 866                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 867                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 868                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 869                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 870                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 871                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 872                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 873         } else {
 874                 I915_WRITE(DSPFW7,
 875                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 876                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 877                 I915_WRITE(DSPHOWM,
 878                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 879                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 880                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 881                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 882                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 883                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 884                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 885         }
 886
 887         /* zero (unused) WM1 watermarks */
 888         I915_WRITE(DSPFW4, 0);
 889         I915_WRITE(DSPFW5, 0);
 890         I915_WRITE(DSPFW6, 0);
 891         I915_WRITE(DSPHOWM1, 0);
 892
 893         POSTING_READ(DSPFW1);
 894 }
 895
 896 #undef FW_WM_VLV
 897
 898 enum vlv_wm_level {
 899         VLV_WM_LEVEL_PM2,
 900         VLV_WM_LEVEL_PM5,
 901         VLV_WM_LEVEL_DDR_DVFS,
 902 };
 903
 904 /* latency must be in 0.1us units. */
 905 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 906                                    unsigned int pipe_htotal,
 907                                    unsigned int horiz_pixels,
 908                                    unsigned int cpp,
 909                                    unsigned int latency)
 910 {
 911         unsigned int ret;
 912
 913         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 914         ret = (ret + 1) * horiz_pixels * cpp;
 915         ret = DIV_ROUND_UP(ret, 64);
 916
 917         return ret;
 918 }
 919
 920 static void vlv_setup_wm_latency(struct drm_device *dev)
 921 {
 922         struct drm_i915_private *dev_priv = dev->dev_private;
 923
 924         /* all latencies in usec */
 925         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 926
 927         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 928
 929         if (IS_CHERRYVIEW(dev_priv)) {
 930                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 931                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 932
 933                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 934         }
 935 }
 936
 937 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 938                                      struct intel_crtc *crtc,
 939                                      const struct intel_plane_state *state,
 940                                      int level)
 941 {
 942         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 943         int clock, htotal, cpp, width, wm;
 944
 945         if (dev_priv->wm.pri_latency[level] == 0)
 946                 return USHRT_MAX;
 947
 948         if (!state->visible)
 949                 return 0;
 950
 951         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 952         clock = crtc->config->base.adjusted_mode.crtc_clock;
 953         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 954         width = crtc->config->pipe_src_w;
 955         if (WARN_ON(htotal == 0))
 956                 htotal = 1;
 957
 958         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 959                 /*
 960                  * FIXME the formula gives values that are
 961                  * too big for the cursor FIFO, and hence we
 962                  * would never be able to use cursors. For
 963                  * now just hardcode the watermark.
 964                  */
 965                 wm = 63;
 966         } else {
 967                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 968                                     dev_priv->wm.pri_latency[level] * 10);
 969         }
 970
 971         return min_t(int, wm, USHRT_MAX);
 972 }
 973
 974 static void vlv_compute_fifo(struct intel_crtc *crtc)
 975 {
 976         struct drm_device *dev = crtc->base.dev;
 977         struct vlv_wm_state *wm_state = &crtc->wm_state;
 978         struct intel_plane *plane;
 979         unsigned int total_rate = 0;
 980         const int fifo_size = 512 - 1;
 981         int fifo_extra, fifo_left = fifo_size;
 982
 983         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 984                 struct intel_plane_state *state =
 985                         to_intel_plane_state(plane->base.state);
 986
 987                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 988                         continue;
 989
 990                 if (state->visible) {
 991                         wm_state->num_active_planes++;
 992                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 993                 }
 994         }
 995
 996         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 997                 struct intel_plane_state *state =
 998                         to_intel_plane_state(plane->base.state);
 999                 unsigned int rate;
1000
1001                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1002                         plane->wm.fifo_size = 63;
1003                         continue;
1004                 }
1005
1006                 if (!state->visible) {
1007                         plane->wm.fifo_size = 0;
1008                         continue;
1009                 }
1010
1011                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1012                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1013                 fifo_left -= plane->wm.fifo_size;
1014         }
1015
1016         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1017
1018         /* spread the remainder evenly */
1019         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1020                 int plane_extra;
1021
1022                 if (fifo_left == 0)
1023                         break;
1024
1025                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1026                         continue;
1027
1028                 /* give it all to the first plane if none are active */
1029                 if (plane->wm.fifo_size == 0 &&
1030                     wm_state->num_active_planes)
1031                         continue;
1032
1033                 plane_extra = min(fifo_extra, fifo_left);
1034                 plane->wm.fifo_size += plane_extra;
1035                 fifo_left -= plane_extra;
1036         }
1037
1038         WARN_ON(fifo_left != 0);
1039 }
1040
1041 static void vlv_invert_wms(struct intel_crtc *crtc)
1042 {
1043         struct vlv_wm_state *wm_state = &crtc->wm_state;
1044         int level;
1045
1046         for (level = 0; level < wm_state->num_levels; level++) {
1047                 struct drm_device *dev = crtc->base.dev;
1048                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1049                 struct intel_plane *plane;
1050
1051                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1052                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1053
1054                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1055                         switch (plane->base.type) {
1056                                 int sprite;
1057                         case DRM_PLANE_TYPE_CURSOR:
1058                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1059                                         wm_state->wm[level].cursor;
1060                                 break;
1061                         case DRM_PLANE_TYPE_PRIMARY:
1062                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1063                                         wm_state->wm[level].primary;
1064                                 break;
1065                         case DRM_PLANE_TYPE_OVERLAY:
1066                                 sprite = plane->plane;
1067                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1068                                         wm_state->wm[level].sprite[sprite];
1069                                 break;
1070                         }
1071                 }
1072         }
1073 }
1074
1075 static void vlv_compute_wm(struct intel_crtc *crtc)
1076 {
1077         struct drm_device *dev = crtc->base.dev;
1078         struct vlv_wm_state *wm_state = &crtc->wm_state;
1079         struct intel_plane *plane;
1080         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1081         int level;
1082
1083         memset(wm_state, 0, sizeof(*wm_state));
1084
1085         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1086         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1087
1088         wm_state->num_active_planes = 0;
1089
1090         vlv_compute_fifo(crtc);
1091
1092         if (wm_state->num_active_planes != 1)
1093                 wm_state->cxsr = false;
1094
1095         if (wm_state->cxsr) {
1096                 for (level = 0; level < wm_state->num_levels; level++) {
1097                         wm_state->sr[level].plane = sr_fifo_size;
1098                         wm_state->sr[level].cursor = 63;
1099                 }
1100         }
1101
1102         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103                 struct intel_plane_state *state =
1104                         to_intel_plane_state(plane->base.state);
1105
1106                 if (!state->visible)
1107                         continue;
1108
1109                 /* normal watermarks */
1110                 for (level = 0; level < wm_state->num_levels; level++) {
1111                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1112                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1113
1114                         /* hack */
1115                         if (WARN_ON(level == 0 && wm > max_wm))
1116                                 wm = max_wm;
1117
1118                         if (wm > plane->wm.fifo_size)
1119                                 break;
1120
1121                         switch (plane->base.type) {
1122                                 int sprite;
1123                         case DRM_PLANE_TYPE_CURSOR:
1124                                 wm_state->wm[level].cursor = wm;
1125                                 break;
1126                         case DRM_PLANE_TYPE_PRIMARY:
1127                                 wm_state->wm[level].primary = wm;
1128                                 break;
1129                         case DRM_PLANE_TYPE_OVERLAY:
1130                                 sprite = plane->plane;
1131                                 wm_state->wm[level].sprite[sprite] = wm;
1132                                 break;
1133                         }
1134                 }
1135
1136                 wm_state->num_levels = level;
1137
1138                 if (!wm_state->cxsr)
1139                         continue;
1140
1141                 /* maxfifo watermarks */
1142                 switch (plane->base.type) {
1143                         int sprite, level;
1144                 case DRM_PLANE_TYPE_CURSOR:
1145                         for (level = 0; level < wm_state->num_levels; level++)
1146                                 wm_state->sr[level].cursor =
1147                                         wm_state->wm[level].cursor;
1148                         break;
1149                 case DRM_PLANE_TYPE_PRIMARY:
1150                         for (level = 0; level < wm_state->num_levels; level++)
1151                                 wm_state->sr[level].plane =
1152                                         min(wm_state->sr[level].plane,
1153                                             wm_state->wm[level].primary);
1154                         break;
1155                 case DRM_PLANE_TYPE_OVERLAY:
1156                         sprite = plane->plane;
1157                         for (level = 0; level < wm_state->num_levels; level++)
1158                                 wm_state->sr[level].plane =
1159                                         min(wm_state->sr[level].plane,
1160                                             wm_state->wm[level].sprite[sprite]);
1161                         break;
1162                 }
1163         }
1164
1165         /* clear any (partially) filled invalid levels */
1166         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1167                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1168                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1169         }
1170
1171         vlv_invert_wms(crtc);
1172 }
1173
1174 #define VLV_FIFO(plane, value) \
1175         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1176
1177 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1178 {
1179         struct drm_device *dev = crtc->base.dev;
1180         struct drm_i915_private *dev_priv = to_i915(dev);
1181         struct intel_plane *plane;
1182         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1183
1184         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1185                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1186                         WARN_ON(plane->wm.fifo_size != 63);
1187                         continue;
1188                 }
1189
1190                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1191                         sprite0_start = plane->wm.fifo_size;
1192                 else if (plane->plane == 0)
1193                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1194                 else
1195                         fifo_size = sprite1_start + plane->wm.fifo_size;
1196         }
1197
1198         WARN_ON(fifo_size != 512 - 1);
1199
1200         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1201                       pipe_name(crtc->pipe), sprite0_start,
1202                       sprite1_start, fifo_size);
1203
1204         switch (crtc->pipe) {
1205                 uint32_t dsparb, dsparb2, dsparb3;
1206         case PIPE_A:
1207                 dsparb = I915_READ(DSPARB);
1208                 dsparb2 = I915_READ(DSPARB2);
1209
1210                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1211                             VLV_FIFO(SPRITEB, 0xff));
1212                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1213                            VLV_FIFO(SPRITEB, sprite1_start));
1214
1215                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1216                              VLV_FIFO(SPRITEB_HI, 0x1));
1217                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1218                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1219
1220                 I915_WRITE(DSPARB, dsparb);
1221                 I915_WRITE(DSPARB2, dsparb2);
1222                 break;
1223         case PIPE_B:
1224                 dsparb = I915_READ(DSPARB);
1225                 dsparb2 = I915_READ(DSPARB2);
1226
1227                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1228                             VLV_FIFO(SPRITED, 0xff));
1229                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1230                            VLV_FIFO(SPRITED, sprite1_start));
1231
1232                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1233                              VLV_FIFO(SPRITED_HI, 0xff));
1234                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1235                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1236
1237                 I915_WRITE(DSPARB, dsparb);
1238                 I915_WRITE(DSPARB2, dsparb2);
1239                 break;
1240         case PIPE_C:
1241                 dsparb3 = I915_READ(DSPARB3);
1242                 dsparb2 = I915_READ(DSPARB2);
1243
1244                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1245                              VLV_FIFO(SPRITEF, 0xff));
1246                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1247                             VLV_FIFO(SPRITEF, sprite1_start));
1248
1249                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1250                              VLV_FIFO(SPRITEF_HI, 0xff));
1251                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1252                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1253
1254                 I915_WRITE(DSPARB3, dsparb3);
1255                 I915_WRITE(DSPARB2, dsparb2);
1256                 break;
1257         default:
1258                 break;
1259         }
1260 }
1261
1262 #undef VLV_FIFO
1263
1264 static void vlv_merge_wm(struct drm_device *dev,
1265                          struct vlv_wm_values *wm)
1266 {
1267         struct intel_crtc *crtc;
1268         int num_active_crtcs = 0;
1269
1270         wm->level = to_i915(dev)->wm.max_level;
1271         wm->cxsr = true;
1272
1273         for_each_intel_crtc(dev, crtc) {
1274                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1275
1276                 if (!crtc->active)
1277                         continue;
1278
1279                 if (!wm_state->cxsr)
1280                         wm->cxsr = false;
1281
1282                 num_active_crtcs++;
1283                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1284         }
1285
1286         if (num_active_crtcs != 1)
1287                 wm->cxsr = false;
1288
1289         if (num_active_crtcs > 1)
1290                 wm->level = VLV_WM_LEVEL_PM2;
1291
1292         for_each_intel_crtc(dev, crtc) {
1293                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1294                 enum pipe pipe = crtc->pipe;
1295
1296                 if (!crtc->active)
1297                         continue;
1298
1299                 wm->pipe[pipe] = wm_state->wm[wm->level];
1300                 if (wm->cxsr)
1301                         wm->sr = wm_state->sr[wm->level];
1302
1303                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1304                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1305                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1306                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1307         }
1308 }
1309
1310 static void vlv_update_wm(struct drm_crtc *crtc)
1311 {
1312         struct drm_device *dev = crtc->dev;
1313         struct drm_i915_private *dev_priv = dev->dev_private;
1314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1315         enum pipe pipe = intel_crtc->pipe;
1316         struct vlv_wm_values wm = {};
1317
1318         vlv_compute_wm(intel_crtc);
1319         vlv_merge_wm(dev, &wm);
1320
1321         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1322                 /* FIXME should be part of crtc atomic commit */
1323                 vlv_pipe_set_fifo_size(intel_crtc);
1324                 return;
1325         }
1326
1327         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1328             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1329                 chv_set_memory_dvfs(dev_priv, false);
1330
1331         if (wm.level < VLV_WM_LEVEL_PM5 &&
1332             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1333                 chv_set_memory_pm5(dev_priv, false);
1334
1335         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1336                 intel_set_memory_cxsr(dev_priv, false);
1337
1338         /* FIXME should be part of crtc atomic commit */
1339         vlv_pipe_set_fifo_size(intel_crtc);
1340
1341         vlv_write_wm_values(intel_crtc, &wm);
1342
1343         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1344                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1345                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1346                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1347                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1348
1349         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1350                 intel_set_memory_cxsr(dev_priv, true);
1351
1352         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1353             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1354                 chv_set_memory_pm5(dev_priv, true);
1355
1356         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1357             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1358                 chv_set_memory_dvfs(dev_priv, true);
1359
1360         dev_priv->wm.vlv = wm;
1361 }
1362
1363 #define single_plane_enabled(mask) is_power_of_2(mask)
1364
1365 static void g4x_update_wm(struct drm_crtc *crtc)
1366 {
1367         struct drm_device *dev = crtc->dev;
1368         static const int sr_latency_ns = 12000;
1369         struct drm_i915_private *dev_priv = dev->dev_private;
1370         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1371         int plane_sr, cursor_sr;
1372         unsigned int enabled = 0;
1373         bool cxsr_enabled;
1374
1375         if (g4x_compute_wm0(dev, PIPE_A,
1376                             &g4x_wm_info, pessimal_latency_ns,
1377                             &g4x_cursor_wm_info, pessimal_latency_ns,
1378                             &planea_wm, &cursora_wm))
1379                 enabled |= 1 << PIPE_A;
1380
1381         if (g4x_compute_wm0(dev, PIPE_B,
1382                             &g4x_wm_info, pessimal_latency_ns,
1383                             &g4x_cursor_wm_info, pessimal_latency_ns,
1384                             &planeb_wm, &cursorb_wm))
1385                 enabled |= 1 << PIPE_B;
1386
1387         if (single_plane_enabled(enabled) &&
1388             g4x_compute_srwm(dev, ffs(enabled) - 1,
1389                              sr_latency_ns,
1390                              &g4x_wm_info,
1391                              &g4x_cursor_wm_info,
1392                              &plane_sr, &cursor_sr)) {
1393                 cxsr_enabled = true;
1394         } else {
1395                 cxsr_enabled = false;
1396                 intel_set_memory_cxsr(dev_priv, false);
1397                 plane_sr = cursor_sr = 0;
1398         }
1399
1400         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1401                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1402                       planea_wm, cursora_wm,
1403                       planeb_wm, cursorb_wm,
1404                       plane_sr, cursor_sr);
1405
1406         I915_WRITE(DSPFW1,
1407                    FW_WM(plane_sr, SR) |
1408                    FW_WM(cursorb_wm, CURSORB) |
1409                    FW_WM(planeb_wm, PLANEB) |
1410                    FW_WM(planea_wm, PLANEA));
1411         I915_WRITE(DSPFW2,
1412                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1413                    FW_WM(cursora_wm, CURSORA));
1414         /* HPLL off in SR has some issues on G4x... disable it */
1415         I915_WRITE(DSPFW3,
1416                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1417                    FW_WM(cursor_sr, CURSOR_SR));
1418
1419         if (cxsr_enabled)
1420                 intel_set_memory_cxsr(dev_priv, true);
1421 }
1422
1423 static void i965_update_wm(struct drm_crtc *unused_crtc)
1424 {
1425         struct drm_device *dev = unused_crtc->dev;
1426         struct drm_i915_private *dev_priv = dev->dev_private;
1427         struct drm_crtc *crtc;
1428         int srwm = 1;
1429         int cursor_sr = 16;
1430         bool cxsr_enabled;
1431
1432         /* Calc sr entries for one plane configs */
1433         crtc = single_enabled_crtc(dev);
1434         if (crtc) {
1435                 /* self-refresh has much higher latency */
1436                 static const int sr_latency_ns = 12000;
1437                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1438                 int clock = adjusted_mode->crtc_clock;
1439                 int htotal = adjusted_mode->crtc_htotal;
1440                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1441                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1442                 unsigned long line_time_us;
1443                 int entries;
1444
1445                 line_time_us = max(htotal * 1000 / clock, 1);
1446
1447                 /* Use ns/us then divide to preserve precision */
1448                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1449                         cpp * hdisplay;
1450                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1451                 srwm = I965_FIFO_SIZE - entries;
1452                 if (srwm < 0)
1453                         srwm = 1;
1454                 srwm &= 0x1ff;
1455                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1456                               entries, srwm);
1457
1458                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1459                         cpp * crtc->cursor->state->crtc_w;
1460                 entries = DIV_ROUND_UP(entries,
1461                                           i965_cursor_wm_info.cacheline_size);
1462                 cursor_sr = i965_cursor_wm_info.fifo_size -
1463                         (entries + i965_cursor_wm_info.guard_size);
1464
1465                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1466                         cursor_sr = i965_cursor_wm_info.max_wm;
1467
1468                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1469                               "cursor %d\n", srwm, cursor_sr);
1470
1471                 cxsr_enabled = true;
1472         } else {
1473                 cxsr_enabled = false;
1474                 /* Turn off self refresh if both pipes are enabled */
1475                 intel_set_memory_cxsr(dev_priv, false);
1476         }
1477
1478         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1479                       srwm);
1480
1481         /* 965 has limitations... */
1482         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1483                    FW_WM(8, CURSORB) |
1484                    FW_WM(8, PLANEB) |
1485                    FW_WM(8, PLANEA));
1486         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1487                    FW_WM(8, PLANEC_OLD));
1488         /* update cursor SR watermark */
1489         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1490
1491         if (cxsr_enabled)
1492                 intel_set_memory_cxsr(dev_priv, true);
1493 }
1494
1495 #undef FW_WM
1496
1497 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1498 {
1499         struct drm_device *dev = unused_crtc->dev;
1500         struct drm_i915_private *dev_priv = dev->dev_private;
1501         const struct intel_watermark_params *wm_info;
1502         uint32_t fwater_lo;
1503         uint32_t fwater_hi;
1504         int cwm, srwm = 1;
1505         int fifo_size;
1506         int planea_wm, planeb_wm;
1507         struct drm_crtc *crtc, *enabled = NULL;
1508
1509         if (IS_I945GM(dev))
1510                 wm_info = &i945_wm_info;
1511         else if (!IS_GEN2(dev))
1512                 wm_info = &i915_wm_info;
1513         else
1514                 wm_info = &i830_a_wm_info;
1515
1516         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1517         crtc = intel_get_crtc_for_plane(dev, 0);
1518         if (intel_crtc_active(crtc)) {
1519                 const struct drm_display_mode *adjusted_mode;
1520                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1521                 if (IS_GEN2(dev))
1522                         cpp = 4;
1523
1524                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1525                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1526                                                wm_info, fifo_size, cpp,
1527                                                pessimal_latency_ns);
1528                 enabled = crtc;
1529         } else {
1530                 planea_wm = fifo_size - wm_info->guard_size;
1531                 if (planea_wm > (long)wm_info->max_wm)
1532                         planea_wm = wm_info->max_wm;
1533         }
1534
1535         if (IS_GEN2(dev))
1536                 wm_info = &i830_bc_wm_info;
1537
1538         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1539         crtc = intel_get_crtc_for_plane(dev, 1);
1540         if (intel_crtc_active(crtc)) {
1541                 const struct drm_display_mode *adjusted_mode;
1542                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1543                 if (IS_GEN2(dev))
1544                         cpp = 4;
1545
1546                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1547                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1548                                                wm_info, fifo_size, cpp,
1549                                                pessimal_latency_ns);
1550                 if (enabled == NULL)
1551                         enabled = crtc;
1552                 else
1553                         enabled = NULL;
1554         } else {
1555                 planeb_wm = fifo_size - wm_info->guard_size;
1556                 if (planeb_wm > (long)wm_info->max_wm)
1557                         planeb_wm = wm_info->max_wm;
1558         }
1559
1560         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1561
1562         if (IS_I915GM(dev) && enabled) {
1563                 struct drm_i915_gem_object *obj;
1564
1565                 obj = intel_fb_obj(enabled->primary->state->fb);
1566
1567                 /* self-refresh seems busted with untiled */
1568                 if (obj->tiling_mode == I915_TILING_NONE)
1569                         enabled = NULL;
1570         }
1571
1572         /*
1573          * Overlay gets an aggressive default since video jitter is bad.
1574          */
1575         cwm = 2;
1576
1577         /* Play safe and disable self-refresh before adjusting watermarks. */
1578         intel_set_memory_cxsr(dev_priv, false);
1579
1580         /* Calc sr entries for one plane configs */
1581         if (HAS_FW_BLC(dev) && enabled) {
1582                 /* self-refresh has much higher latency */
1583                 static const int sr_latency_ns = 6000;
1584                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1585                 int clock = adjusted_mode->crtc_clock;
1586                 int htotal = adjusted_mode->crtc_htotal;
1587                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1588                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1589                 unsigned long line_time_us;
1590                 int entries;
1591
1592                 line_time_us = max(htotal * 1000 / clock, 1);
1593
1594                 /* Use ns/us then divide to preserve precision */
1595                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1596                         cpp * hdisplay;
1597                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1598                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1599                 srwm = wm_info->fifo_size - entries;
1600                 if (srwm < 0)
1601                         srwm = 1;
1602
1603                 if (IS_I945G(dev) || IS_I945GM(dev))
1604                         I915_WRITE(FW_BLC_SELF,
1605                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1606                 else if (IS_I915GM(dev))
1607                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1608         }
1609
1610         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1611                       planea_wm, planeb_wm, cwm, srwm);
1612
1613         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1614         fwater_hi = (cwm & 0x1f);
1615
1616         /* Set request length to 8 cachelines per fetch */
1617         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1618         fwater_hi = fwater_hi | (1 << 8);
1619
1620         I915_WRITE(FW_BLC, fwater_lo);
1621         I915_WRITE(FW_BLC2, fwater_hi);
1622
1623         if (enabled)
1624                 intel_set_memory_cxsr(dev_priv, true);
1625 }
1626
1627 static void i845_update_wm(struct drm_crtc *unused_crtc)
1628 {
1629         struct drm_device *dev = unused_crtc->dev;
1630         struct drm_i915_private *dev_priv = dev->dev_private;
1631         struct drm_crtc *crtc;
1632         const struct drm_display_mode *adjusted_mode;
1633         uint32_t fwater_lo;
1634         int planea_wm;
1635
1636         crtc = single_enabled_crtc(dev);
1637         if (crtc == NULL)
1638                 return;
1639
1640         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1641         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1642                                        &i845_wm_info,
1643                                        dev_priv->display.get_fifo_size(dev, 0),
1644                                        4, pessimal_latency_ns);
1645         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1646         fwater_lo |= (3<<8) | planea_wm;
1647
1648         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1649
1650         I915_WRITE(FW_BLC, fwater_lo);
1651 }
1652
1653 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1654 {
1655         uint32_t pixel_rate;
1656
1657         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1658
1659         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1660          * adjust the pixel_rate here. */
1661
1662         if (pipe_config->pch_pfit.enabled) {
1663                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1664                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1665
1666                 pipe_w = pipe_config->pipe_src_w;
1667                 pipe_h = pipe_config->pipe_src_h;
1668
1669                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670                 pfit_h = pfit_size & 0xFFFF;
1671                 if (pipe_w < pfit_w)
1672                         pipe_w = pfit_w;
1673                 if (pipe_h < pfit_h)
1674                         pipe_h = pfit_h;
1675
1676                 if (WARN_ON(!pfit_w || !pfit_h))
1677                         return pixel_rate;
1678
1679                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1680                                      pfit_w * pfit_h);
1681         }
1682
1683         return pixel_rate;
1684 }
1685
1686 /* latency must be in 0.1us units. */
1687 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1688 {
1689         uint64_t ret;
1690
1691         if (WARN(latency == 0, "Latency value missing\n"))
1692                 return UINT_MAX;
1693
1694         ret = (uint64_t) pixel_rate * cpp * latency;
1695         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1696
1697         return ret;
1698 }
1699
1700 /* latency must be in 0.1us units. */
1701 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1702                                uint32_t horiz_pixels, uint8_t cpp,
1703                                uint32_t latency)
1704 {
1705         uint32_t ret;
1706
1707         if (WARN(latency == 0, "Latency value missing\n"))
1708                 return UINT_MAX;
1709         if (WARN_ON(!pipe_htotal))
1710                 return UINT_MAX;
1711
1712         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1713         ret = (ret + 1) * horiz_pixels * cpp;
1714         ret = DIV_ROUND_UP(ret, 64) + 2;
1715         return ret;
1716 }
1717
1718 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1719                            uint8_t cpp)
1720 {
1721         /*
1722          * Neither of these should be possible since this function shouldn't be
1723          * called if the CRTC is off or the plane is invisible.  But let's be
1724          * extra paranoid to avoid a potential divide-by-zero if we screw up
1725          * elsewhere in the driver.
1726          */
1727         if (WARN_ON(!cpp))
1728                 return 0;
1729         if (WARN_ON(!horiz_pixels))
1730                 return 0;
1731
1732         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1733 }
1734
1735 struct ilk_wm_maximums {
1736         uint16_t pri;
1737         uint16_t spr;
1738         uint16_t cur;
1739         uint16_t fbc;
1740 };
1741
1742 /*
1743  * For both WM_PIPE and WM_LP.
1744  * mem_value must be in 0.1us units.
1745  */
1746 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1747                                    const struct intel_plane_state *pstate,
1748                                    uint32_t mem_value,
1749                                    bool is_lp)
1750 {
1751         int cpp = pstate->base.fb ?
1752                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1753         uint32_t method1, method2;
1754
1755         if (!cstate->base.active || !pstate->visible)
1756                 return 0;
1757
1758         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1759
1760         if (!is_lp)
1761                 return method1;
1762
1763         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1764                                  cstate->base.adjusted_mode.crtc_htotal,
1765                                  drm_rect_width(&pstate->dst),
1766                                  cpp, mem_value);
1767
1768         return min(method1, method2);
1769 }
1770
1771 /*
1772  * For both WM_PIPE and WM_LP.
1773  * mem_value must be in 0.1us units.
1774  */
1775 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1776                                    const struct intel_plane_state *pstate,
1777                                    uint32_t mem_value)
1778 {
1779         int cpp = pstate->base.fb ?
1780                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1781         uint32_t method1, method2;
1782
1783         if (!cstate->base.active || !pstate->visible)
1784                 return 0;
1785
1786         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1787         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1788                                  cstate->base.adjusted_mode.crtc_htotal,
1789                                  drm_rect_width(&pstate->dst),
1790                                  cpp, mem_value);
1791         return min(method1, method2);
1792 }
1793
1794 /*
1795  * For both WM_PIPE and WM_LP.
1796  * mem_value must be in 0.1us units.
1797  */
1798 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1799                                    const struct intel_plane_state *pstate,
1800                                    uint32_t mem_value)
1801 {
1802         /*
1803          * We treat the cursor plane as always-on for the purposes of watermark
1804          * calculation.  Until we have two-stage watermark programming merged,
1805          * this is necessary to avoid flickering.
1806          */
1807         int cpp = 4;
1808         int width = pstate->visible ? pstate->base.crtc_w : 64;
1809
1810         if (!cstate->base.active)
1811                 return 0;
1812
1813         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1814                               cstate->base.adjusted_mode.crtc_htotal,
1815                               width, cpp, mem_value);
1816 }
1817
1818 /* Only for WM_LP. */
1819 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1820                                    const struct intel_plane_state *pstate,
1821                                    uint32_t pri_val)
1822 {
1823         int cpp = pstate->base.fb ?
1824                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1825
1826         if (!cstate->base.active || !pstate->visible)
1827                 return 0;
1828
1829         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1830 }
1831
1832 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1833 {
1834         if (INTEL_INFO(dev)->gen >= 8)
1835                 return 3072;
1836         else if (INTEL_INFO(dev)->gen >= 7)
1837                 return 768;
1838         else
1839                 return 512;
1840 }
1841
1842 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1843                                          int level, bool is_sprite)
1844 {
1845         if (INTEL_INFO(dev)->gen >= 8)
1846                 /* BDW primary/sprite plane watermarks */
1847                 return level == 0 ? 255 : 2047;
1848         else if (INTEL_INFO(dev)->gen >= 7)
1849                 /* IVB/HSW primary/sprite plane watermarks */
1850                 return level == 0 ? 127 : 1023;
1851         else if (!is_sprite)
1852                 /* ILK/SNB primary plane watermarks */
1853                 return level == 0 ? 127 : 511;
1854         else
1855                 /* ILK/SNB sprite plane watermarks */
1856                 return level == 0 ? 63 : 255;
1857 }
1858
1859 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1860                                           int level)
1861 {
1862         if (INTEL_INFO(dev)->gen >= 7)
1863                 return level == 0 ? 63 : 255;
1864         else
1865                 return level == 0 ? 31 : 63;
1866 }
1867
1868 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1869 {
1870         if (INTEL_INFO(dev)->gen >= 8)
1871                 return 31;
1872         else
1873                 return 15;
1874 }
1875
1876 /* Calculate the maximum primary/sprite plane watermark */
1877 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1878                                      int level,
1879                                      const struct intel_wm_config *config,
1880                                      enum intel_ddb_partitioning ddb_partitioning,
1881                                      bool is_sprite)
1882 {
1883         unsigned int fifo_size = ilk_display_fifo_size(dev);
1884
1885         /* if sprites aren't enabled, sprites get nothing */
1886         if (is_sprite && !config->sprites_enabled)
1887                 return 0;
1888
1889         /* HSW allows LP1+ watermarks even with multiple pipes */
1890         if (level == 0 || config->num_pipes_active > 1) {
1891                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1892
1893                 /*
1894                  * For some reason the non self refresh
1895                  * FIFO size is only half of the self
1896                  * refresh FIFO size on ILK/SNB.
1897                  */
1898                 if (INTEL_INFO(dev)->gen <= 6)
1899                         fifo_size /= 2;
1900         }
1901
1902         if (config->sprites_enabled) {
1903                 /* level 0 is always calculated with 1:1 split */
1904                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1905                         if (is_sprite)
1906                                 fifo_size *= 5;
1907                         fifo_size /= 6;
1908                 } else {
1909                         fifo_size /= 2;
1910                 }
1911         }
1912
1913         /* clamp to max that the registers can hold */
1914         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1915 }
1916
1917 /* Calculate the maximum cursor plane watermark */
1918 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1919                                       int level,
1920                                       const struct intel_wm_config *config)
1921 {
1922         /* HSW LP1+ watermarks w/ multiple pipes */
1923         if (level > 0 && config->num_pipes_active > 1)
1924                 return 64;
1925
1926         /* otherwise just report max that registers can hold */
1927         return ilk_cursor_wm_reg_max(dev, level);
1928 }
1929
1930 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1931                                     int level,
1932                                     const struct intel_wm_config *config,
1933                                     enum intel_ddb_partitioning ddb_partitioning,
1934                                     struct ilk_wm_maximums *max)
1935 {
1936         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1937         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1938         max->cur = ilk_cursor_wm_max(dev, level, config);
1939         max->fbc = ilk_fbc_wm_reg_max(dev);
1940 }
1941
1942 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1943                                         int level,
1944                                         struct ilk_wm_maximums *max)
1945 {
1946         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1947         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1948         max->cur = ilk_cursor_wm_reg_max(dev, level);
1949         max->fbc = ilk_fbc_wm_reg_max(dev);
1950 }
1951
1952 static bool ilk_validate_wm_level(int level,
1953                                   const struct ilk_wm_maximums *max,
1954                                   struct intel_wm_level *result)
1955 {
1956         bool ret;
1957
1958         /* already determined to be invalid? */
1959         if (!result->enable)
1960                 return false;
1961
1962         result->enable = result->pri_val <= max->pri &&
1963                          result->spr_val <= max->spr &&
1964                          result->cur_val <= max->cur;
1965
1966         ret = result->enable;
1967
1968         /*
1969          * HACK until we can pre-compute everything,
1970          * and thus fail gracefully if LP0 watermarks
1971          * are exceeded...
1972          */
1973         if (level == 0 && !result->enable) {
1974                 if (result->pri_val > max->pri)
1975                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1976                                       level, result->pri_val, max->pri);
1977                 if (result->spr_val > max->spr)
1978                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1979                                       level, result->spr_val, max->spr);
1980                 if (result->cur_val > max->cur)
1981                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1982                                       level, result->cur_val, max->cur);
1983
1984                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1985                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1986                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1987                 result->enable = true;
1988         }
1989
1990         return ret;
1991 }
1992
1993 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1994                                  const struct intel_crtc *intel_crtc,
1995                                  int level,
1996                                  struct intel_crtc_state *cstate,
1997                                  struct intel_plane_state *pristate,
1998                                  struct intel_plane_state *sprstate,
1999                                  struct intel_plane_state *curstate,
2000                                  struct intel_wm_level *result)
2001 {
2002         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2003         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2004         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2005
2006         /* WM1+ latency values stored in 0.5us units */
2007         if (level > 0) {
2008                 pri_latency *= 5;
2009                 spr_latency *= 5;
2010                 cur_latency *= 5;
2011         }
2012
2013         result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2014                                              pri_latency, level);
2015         result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2016         result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2017         result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2018         result->enable = true;
2019 }
2020
2021 static uint32_t
2022 hsw_compute_linetime_wm(struct drm_device *dev,
2023                         struct intel_crtc_state *cstate)
2024 {
2025         struct drm_i915_private *dev_priv = dev->dev_private;
2026         const struct drm_display_mode *adjusted_mode =
2027                 &cstate->base.adjusted_mode;
2028         u32 linetime, ips_linetime;
2029
2030         if (!cstate->base.active)
2031                 return 0;
2032         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2033                 return 0;
2034         if (WARN_ON(dev_priv->cdclk_freq == 0))
2035                 return 0;
2036
2037         /* The WM are computed with base on how long it takes to fill a single
2038          * row at the given clock rate, multiplied by 8.
2039          * */
2040         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2041                                      adjusted_mode->crtc_clock);
2042         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2043                                          dev_priv->cdclk_freq);
2044
2045         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2046                PIPE_WM_LINETIME_TIME(linetime);
2047 }
2048
2049 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2050 {
2051         struct drm_i915_private *dev_priv = dev->dev_private;
2052
2053         if (IS_GEN9(dev)) {
2054                 uint32_t val;
2055                 int ret, i;
2056                 int level, max_level = ilk_wm_max_level(dev);
2057
2058                 /* read the first set of memory latencies[0:3] */
2059                 val = 0; /* data0 to be programmed to 0 for first set */
2060                 mutex_lock(&dev_priv->rps.hw_lock);
2061                 ret = sandybridge_pcode_read(dev_priv,
2062                                              GEN9_PCODE_READ_MEM_LATENCY,
2063                                              &val);
2064                 mutex_unlock(&dev_priv->rps.hw_lock);
2065
2066                 if (ret) {
2067                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2068                         return;
2069                 }
2070
2071                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2072                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2073                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2074                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2075                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2076                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2077                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2078
2079                 /* read the second set of memory latencies[4:7] */
2080                 val = 1; /* data0 to be programmed to 1 for second set */
2081                 mutex_lock(&dev_priv->rps.hw_lock);
2082                 ret = sandybridge_pcode_read(dev_priv,
2083                                              GEN9_PCODE_READ_MEM_LATENCY,
2084                                              &val);
2085                 mutex_unlock(&dev_priv->rps.hw_lock);
2086                 if (ret) {
2087                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2088                         return;
2089                 }
2090
2091                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2092                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2093                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2094                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2095                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2096                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2097                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2098
2099                 /*
2100                  * WaWmMemoryReadLatency:skl
2101                  *
2102                  * punit doesn't take into account the read latency so we need
2103                  * to add 2us to the various latency levels we retrieve from
2104                  * the punit.
2105                  *   - W0 is a bit special in that it's the only level that
2106                  *   can't be disabled if we want to have display working, so
2107                  *   we always add 2us there.
2108                  *   - For levels >=1, punit returns 0us latency when they are
2109                  *   disabled, so we respect that and don't add 2us then
2110                  *
2111                  * Additionally, if a level n (n > 1) has a 0us latency, all
2112                  * levels m (m >= n) need to be disabled. We make sure to
2113                  * sanitize the values out of the punit to satisfy this
2114                  * requirement.
2115                  */
2116                 wm[0] += 2;
2117                 for (level = 1; level <= max_level; level++)
2118                         if (wm[level] != 0)
2119                                 wm[level] += 2;
2120                         else {
2121                                 for (i = level + 1; i <= max_level; i++)
2122                                         wm[i] = 0;
2123
2124                                 break;
2125                         }
2126         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2127                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2128
2129                 wm[0] = (sskpd >> 56) & 0xFF;
2130                 if (wm[0] == 0)
2131                         wm[0] = sskpd & 0xF;
2132                 wm[1] = (sskpd >> 4) & 0xFF;
2133                 wm[2] = (sskpd >> 12) & 0xFF;
2134                 wm[3] = (sskpd >> 20) & 0x1FF;
2135                 wm[4] = (sskpd >> 32) & 0x1FF;
2136         } else if (INTEL_INFO(dev)->gen >= 6) {
2137                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2138
2139                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2140                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2141                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2142                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2143         } else if (INTEL_INFO(dev)->gen >= 5) {
2144                 uint32_t mltr = I915_READ(MLTR_ILK);
2145
2146                 /* ILK primary LP0 latency is 700 ns */
2147                 wm[0] = 7;
2148                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2149                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2150         }
2151 }
2152
2153 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154 {
2155         /* ILK sprite LP0 latency is 1300 ns */
2156         if (INTEL_INFO(dev)->gen == 5)
2157                 wm[0] = 13;
2158 }
2159
2160 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2161 {
2162         /* ILK cursor LP0 latency is 1300 ns */
2163         if (INTEL_INFO(dev)->gen == 5)
2164                 wm[0] = 13;
2165
2166         /* WaDoubleCursorLP3Latency:ivb */
2167         if (IS_IVYBRIDGE(dev))
2168                 wm[3] *= 2;
2169 }
2170
2171 int ilk_wm_max_level(const struct drm_device *dev)
2172 {
2173         /* how many WM levels are we expecting */
2174         if (INTEL_INFO(dev)->gen >= 9)
2175                 return 7;
2176         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2177                 return 4;
2178         else if (INTEL_INFO(dev)->gen >= 6)
2179                 return 3;
2180         else
2181                 return 2;
2182 }
2183
2184 static void intel_print_wm_latency(struct drm_device *dev,
2185                                    const char *name,
2186                                    const uint16_t wm[8])
2187 {
2188         int level, max_level = ilk_wm_max_level(dev);
2189
2190         for (level = 0; level <= max_level; level++) {
2191                 unsigned int latency = wm[level];
2192
2193                 if (latency == 0) {
2194                         DRM_ERROR("%s WM%d latency not provided\n",
2195                                   name, level);
2196                         continue;
2197                 }
2198
2199                 /*
2200                  * - latencies are in us on gen9.
2201                  * - before then, WM1+ latency values are in 0.5us units
2202                  */
2203                 if (IS_GEN9(dev))
2204                         latency *= 10;
2205                 else if (level > 0)
2206                         latency *= 5;
2207
2208                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2209                               name, level, wm[level],
2210                               latency / 10, latency % 10);
2211         }
2212 }
2213
2214 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2215                                     uint16_t wm[5], uint16_t min)
2216 {
2217         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2218
2219         if (wm[0] >= min)
2220                 return false;
2221
2222         wm[0] = max(wm[0], min);
2223         for (level = 1; level <= max_level; level++)
2224                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2225
2226         return true;
2227 }
2228
2229 static void snb_wm_latency_quirk(struct drm_device *dev)
2230 {
2231         struct drm_i915_private *dev_priv = dev->dev_private;
2232         bool changed;
2233
2234         /*
2235          * The BIOS provided WM memory latency values are often
2236          * inadequate for high resolution displays. Adjust them.
2237          */
2238         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2239                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2240                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2241
2242         if (!changed)
2243                 return;
2244
2245         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2246         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2247         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2248         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2249 }
2250
2251 static void ilk_setup_wm_latency(struct drm_device *dev)
2252 {
2253         struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2256
2257         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2258                sizeof(dev_priv->wm.pri_latency));
2259         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2260                sizeof(dev_priv->wm.pri_latency));
2261
2262         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2263         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2264
2265         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2266         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2267         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2268
2269         if (IS_GEN6(dev))
2270                 snb_wm_latency_quirk(dev);
2271 }
2272
2273 static void skl_setup_wm_latency(struct drm_device *dev)
2274 {
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276
2277         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2278         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2279 }
2280
2281 /* Compute new watermarks for the pipe */
2282 static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2283                                struct drm_atomic_state *state)
2284 {
2285         struct intel_pipe_wm *pipe_wm;
2286         struct drm_device *dev = intel_crtc->base.dev;
2287         const struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct intel_crtc_state *cstate = NULL;
2289         struct intel_plane *intel_plane;
2290         struct drm_plane_state *ps;
2291         struct intel_plane_state *pristate = NULL;
2292         struct intel_plane_state *sprstate = NULL;
2293         struct intel_plane_state *curstate = NULL;
2294         int level, max_level = ilk_wm_max_level(dev);
2295         /* LP0 watermark maximums depend on this pipe alone */
2296         struct intel_wm_config config = {
2297                 .num_pipes_active = 1,
2298         };
2299         struct ilk_wm_maximums max;
2300
2301         cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2302         if (IS_ERR(cstate))
2303                 return PTR_ERR(cstate);
2304
2305         pipe_wm = &cstate->wm.optimal.ilk;
2306         memset(pipe_wm, 0, sizeof(*pipe_wm));
2307
2308         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2309                 ps = drm_atomic_get_plane_state(state,
2310                                                 &intel_plane->base);
2311                 if (IS_ERR(ps))
2312                         return PTR_ERR(ps);
2313
2314                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2315                         pristate = to_intel_plane_state(ps);
2316                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2317                         sprstate = to_intel_plane_state(ps);
2318                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2319                         curstate = to_intel_plane_state(ps);
2320         }
2321
2322         config.sprites_enabled = sprstate->visible;
2323         config.sprites_scaled = sprstate->visible &&
2324                 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2325                 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2326
2327         pipe_wm->pipe_enabled = cstate->base.active;
2328         pipe_wm->sprites_enabled = config.sprites_enabled;
2329         pipe_wm->sprites_scaled = config.sprites_scaled;
2330
2331         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2332         if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2333                 max_level = 1;
2334
2335         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2336         if (config.sprites_scaled)
2337                 max_level = 0;
2338
2339         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2340                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
2341
2342         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2343                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
2344
2345         /* LP0 watermarks always use 1/2 DDB partitioning */
2346         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2347
2348         /* At least LP0 must be valid */
2349         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2350                 return -EINVAL;
2351
2352         ilk_compute_wm_reg_maximums(dev, 1, &max);
2353
2354         for (level = 1; level <= max_level; level++) {
2355                 struct intel_wm_level wm = {};
2356
2357                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2358                                      pristate, sprstate, curstate, &wm);
2359
2360                 /*
2361                  * Disable any watermark level that exceeds the
2362                  * register maximums since such watermarks are
2363                  * always invalid.
2364                  */
2365                 if (!ilk_validate_wm_level(level, &max, &wm))
2366                         break;
2367
2368                 pipe_wm->wm[level] = wm;
2369         }
2370
2371         return 0;
2372 }
2373
2374 /*
2375  * Merge the watermarks from all active pipes for a specific level.
2376  */
2377 static void ilk_merge_wm_level(struct drm_device *dev,
2378                                int level,
2379                                struct intel_wm_level *ret_wm)
2380 {
2381         const struct intel_crtc *intel_crtc;
2382
2383         ret_wm->enable = true;
2384
2385         for_each_intel_crtc(dev, intel_crtc) {
2386                 const struct intel_crtc_state *cstate =
2387                         to_intel_crtc_state(intel_crtc->base.state);
2388                 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
2389                 const struct intel_wm_level *wm = &active->wm[level];
2390
2391                 if (!active->pipe_enabled)
2392                         continue;
2393
2394                 /*
2395                  * The watermark values may have been used in the past,
2396                  * so we must maintain them in the registers for some
2397                  * time even if the level is now disabled.
2398                  */
2399                 if (!wm->enable)
2400                         ret_wm->enable = false;
2401
2402                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2403                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2404                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2405                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2406         }
2407 }
2408
2409 /*
2410  * Merge all low power watermarks for all active pipes.
2411  */
2412 static void ilk_wm_merge(struct drm_device *dev,
2413                          const struct intel_wm_config *config,
2414                          const struct ilk_wm_maximums *max,
2415                          struct intel_pipe_wm *merged)
2416 {
2417         struct drm_i915_private *dev_priv = dev->dev_private;
2418         int level, max_level = ilk_wm_max_level(dev);
2419         int last_enabled_level = max_level;
2420
2421         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2422         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2423             config->num_pipes_active > 1)
2424                 return;
2425
2426         /* ILK: FBC WM must be disabled always */
2427         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2428
2429         /* merge each WM1+ level */
2430         for (level = 1; level <= max_level; level++) {
2431                 struct intel_wm_level *wm = &merged->wm[level];
2432
2433                 ilk_merge_wm_level(dev, level, wm);
2434
2435                 if (level > last_enabled_level)
2436                         wm->enable = false;
2437                 else if (!ilk_validate_wm_level(level, max, wm))
2438                         /* make sure all following levels get disabled */
2439                         last_enabled_level = level - 1;
2440
2441                 /*
2442                  * The spec says it is preferred to disable
2443                  * FBC WMs instead of disabling a WM level.
2444                  */
2445                 if (wm->fbc_val > max->fbc) {
2446                         if (wm->enable)
2447                                 merged->fbc_wm_enabled = false;
2448                         wm->fbc_val = 0;
2449                 }
2450         }
2451
2452         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2453         /*
2454          * FIXME this is racy. FBC might get enabled later.
2455          * What we should check here is whether FBC can be
2456          * enabled sometime later.
2457          */
2458         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2459             intel_fbc_is_active(dev_priv)) {
2460                 for (level = 2; level <= max_level; level++) {
2461                         struct intel_wm_level *wm = &merged->wm[level];
2462
2463                         wm->enable = false;
2464                 }
2465         }
2466 }
2467
2468 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2469 {
2470         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2471         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2472 }
2473
2474 /* The value we need to program into the WM_LPx latency field */
2475 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2476 {
2477         struct drm_i915_private *dev_priv = dev->dev_private;
2478
2479         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2480                 return 2 * level;
2481         else
2482                 return dev_priv->wm.pri_latency[level];
2483 }
2484
2485 static void ilk_compute_wm_results(struct drm_device *dev,
2486                                    const struct intel_pipe_wm *merged,
2487                                    enum intel_ddb_partitioning partitioning,
2488                                    struct ilk_wm_values *results)
2489 {
2490         struct intel_crtc *intel_crtc;
2491         int level, wm_lp;
2492
2493         results->enable_fbc_wm = merged->fbc_wm_enabled;
2494         results->partitioning = partitioning;
2495
2496         /* LP1+ register values */
2497         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2498                 const struct intel_wm_level *r;
2499
2500                 level = ilk_wm_lp_to_level(wm_lp, merged);
2501
2502                 r = &merged->wm[level];
2503
2504                 /*
2505                  * Maintain the watermark values even if the level is
2506                  * disabled. Doing otherwise could cause underruns.
2507                  */
2508                 results->wm_lp[wm_lp - 1] =
2509                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2510                         (r->pri_val << WM1_LP_SR_SHIFT) |
2511                         r->cur_val;
2512
2513                 if (r->enable)
2514                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2515
2516                 if (INTEL_INFO(dev)->gen >= 8)
2517                         results->wm_lp[wm_lp - 1] |=
2518                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2519                 else
2520                         results->wm_lp[wm_lp - 1] |=
2521                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2522
2523                 /*
2524                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2525                  * level is disabled. Doing otherwise could cause underruns.
2526                  */
2527                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2528                         WARN_ON(wm_lp != 1);
2529                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2530                 } else
2531                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2532         }
2533
2534         /* LP0 register values */
2535         for_each_intel_crtc(dev, intel_crtc) {
2536                 const struct intel_crtc_state *cstate =
2537                         to_intel_crtc_state(intel_crtc->base.state);
2538                 enum pipe pipe = intel_crtc->pipe;
2539                 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
2540
2541                 if (WARN_ON(!r->enable))
2542                         continue;
2543
2544                 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
2545
2546                 results->wm_pipe[pipe] =
2547                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2548                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2549                         r->cur_val;
2550         }
2551 }
2552
2553 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2554  * case both are at the same level. Prefer r1 in case they're the same. */
2555 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2556                                                   struct intel_pipe_wm *r1,
2557                                                   struct intel_pipe_wm *r2)
2558 {
2559         int level, max_level = ilk_wm_max_level(dev);
2560         int level1 = 0, level2 = 0;
2561
2562         for (level = 1; level <= max_level; level++) {
2563                 if (r1->wm[level].enable)
2564                         level1 = level;
2565                 if (r2->wm[level].enable)
2566                         level2 = level;
2567         }
2568
2569         if (level1 == level2) {
2570                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2571                         return r2;
2572                 else
2573                         return r1;
2574         } else if (level1 > level2) {
2575                 return r1;
2576         } else {
2577                 return r2;
2578         }
2579 }
2580
2581 /* dirty bits used to track which watermarks need changes */
2582 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2583 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2584 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2585 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2586 #define WM_DIRTY_FBC (1 << 24)
2587 #define WM_DIRTY_DDB (1 << 25)
2588
2589 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2590                                          const struct ilk_wm_values *old,
2591                                          const struct ilk_wm_values *new)
2592 {
2593         unsigned int dirty = 0;
2594         enum pipe pipe;
2595         int wm_lp;
2596
2597         for_each_pipe(dev_priv, pipe) {
2598                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2599                         dirty |= WM_DIRTY_LINETIME(pipe);
2600                         /* Must disable LP1+ watermarks too */
2601                         dirty |= WM_DIRTY_LP_ALL;
2602                 }
2603
2604                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2605                         dirty |= WM_DIRTY_PIPE(pipe);
2606                         /* Must disable LP1+ watermarks too */
2607                         dirty |= WM_DIRTY_LP_ALL;
2608                 }
2609         }
2610
2611         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2612                 dirty |= WM_DIRTY_FBC;
2613                 /* Must disable LP1+ watermarks too */
2614                 dirty |= WM_DIRTY_LP_ALL;
2615         }
2616
2617         if (old->partitioning != new->partitioning) {
2618                 dirty |= WM_DIRTY_DDB;
2619                 /* Must disable LP1+ watermarks too */
2620                 dirty |= WM_DIRTY_LP_ALL;
2621         }
2622
2623         /* LP1+ watermarks already deemed dirty, no need to continue */
2624         if (dirty & WM_DIRTY_LP_ALL)
2625                 return dirty;
2626
2627         /* Find the lowest numbered LP1+ watermark in need of an update... */
2628         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2629                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2630                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2631                         break;
2632         }
2633
2634         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2635         for (; wm_lp <= 3; wm_lp++)
2636                 dirty |= WM_DIRTY_LP(wm_lp);
2637
2638         return dirty;
2639 }
2640
2641 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2642                                unsigned int dirty)
2643 {
2644         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2645         bool changed = false;
2646
2647         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2648                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2649                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2650                 changed = true;
2651         }
2652         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2653                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2654                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2655                 changed = true;
2656         }
2657         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2658                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2659                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2660                 changed = true;
2661         }
2662
2663         /*
2664          * Don't touch WM1S_LP_EN here.
2665          * Doing so could cause underruns.
2666          */
2667
2668         return changed;
2669 }
2670
2671 /*
2672  * The spec says we shouldn't write when we don't need, because every write
2673  * causes WMs to be re-evaluated, expending some power.
2674  */
2675 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2676                                 struct ilk_wm_values *results)
2677 {
2678         struct drm_device *dev = dev_priv->dev;
2679         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2680         unsigned int dirty;
2681         uint32_t val;
2682
2683         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2684         if (!dirty)
2685                 return;
2686
2687         _ilk_disable_lp_wm(dev_priv, dirty);
2688
2689         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2690                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2691         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2692                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2693         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2694                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2695
2696         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2697                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2698         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2699                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2700         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2701                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2702
2703         if (dirty & WM_DIRTY_DDB) {
2704                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2705                         val = I915_READ(WM_MISC);
2706                         if (results->partitioning == INTEL_DDB_PART_1_2)
2707                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2708                         else
2709                                 val |= WM_MISC_DATA_PARTITION_5_6;
2710                         I915_WRITE(WM_MISC, val);
2711                 } else {
2712                         val = I915_READ(DISP_ARB_CTL2);
2713                         if (results->partitioning == INTEL_DDB_PART_1_2)
2714                                 val &= ~DISP_DATA_PARTITION_5_6;
2715                         else
2716                                 val |= DISP_DATA_PARTITION_5_6;
2717                         I915_WRITE(DISP_ARB_CTL2, val);
2718                 }
2719         }
2720
2721         if (dirty & WM_DIRTY_FBC) {
2722                 val = I915_READ(DISP_ARB_CTL);
2723                 if (results->enable_fbc_wm)
2724                         val &= ~DISP_FBC_WM_DIS;
2725                 else
2726                         val |= DISP_FBC_WM_DIS;
2727                 I915_WRITE(DISP_ARB_CTL, val);
2728         }
2729
2730         if (dirty & WM_DIRTY_LP(1) &&
2731             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2732                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2733
2734         if (INTEL_INFO(dev)->gen >= 7) {
2735                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2736                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2737                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2738                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2739         }
2740
2741         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2742                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2743         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2744                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2745         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2746                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2747
2748         dev_priv->wm.hw = *results;
2749 }
2750
2751 static bool ilk_disable_lp_wm(struct drm_device *dev)
2752 {
2753         struct drm_i915_private *dev_priv = dev->dev_private;
2754
2755         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2756 }
2757
2758 /*
2759  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2760  * different active planes.
2761  */
2762
2763 #define SKL_DDB_SIZE            896     /* in blocks */
2764 #define BXT_DDB_SIZE            512
2765
2766 /*
2767  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2768  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2769  * other universal planes are in indices 1..n.  Note that this may leave unused
2770  * indices between the top "sprite" plane and the cursor.
2771  */
2772 static int
2773 skl_wm_plane_id(const struct intel_plane *plane)
2774 {
2775         switch (plane->base.type) {
2776         case DRM_PLANE_TYPE_PRIMARY:
2777                 return 0;
2778         case DRM_PLANE_TYPE_CURSOR:
2779                 return PLANE_CURSOR;
2780         case DRM_PLANE_TYPE_OVERLAY:
2781                 return plane->plane + 1;
2782         default:
2783                 MISSING_CASE(plane->base.type);
2784                 return plane->plane;
2785         }
2786 }
2787
2788 static void
2789 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2790                                    const struct intel_crtc_state *cstate,
2791                                    const struct intel_wm_config *config,
2792                                    struct skl_ddb_entry *alloc /* out */)
2793 {
2794         struct drm_crtc *for_crtc = cstate->base.crtc;
2795         struct drm_crtc *crtc;
2796         unsigned int pipe_size, ddb_size;
2797         int nth_active_pipe;
2798
2799         if (!cstate->base.active) {
2800                 alloc->start = 0;
2801                 alloc->end = 0;
2802                 return;
2803         }
2804
2805         if (IS_BROXTON(dev))
2806                 ddb_size = BXT_DDB_SIZE;
2807         else
2808                 ddb_size = SKL_DDB_SIZE;
2809
2810         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2811
2812         nth_active_pipe = 0;
2813         for_each_crtc(dev, crtc) {
2814                 if (!to_intel_crtc(crtc)->active)
2815                         continue;
2816
2817                 if (crtc == for_crtc)
2818                         break;
2819
2820                 nth_active_pipe++;
2821         }
2822
2823         pipe_size = ddb_size / config->num_pipes_active;
2824         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2825         alloc->end = alloc->start + pipe_size;
2826 }
2827
2828 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2829 {
2830         if (config->num_pipes_active == 1)
2831                 return 32;
2832
2833         return 8;
2834 }
2835
2836 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2837 {
2838         entry->start = reg & 0x3ff;
2839         entry->end = (reg >> 16) & 0x3ff;
2840         if (entry->end)
2841                 entry->end += 1;
2842 }
2843
2844 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2845                           struct skl_ddb_allocation *ddb /* out */)
2846 {
2847         enum pipe pipe;
2848         int plane;
2849         u32 val;
2850
2851         memset(ddb, 0, sizeof(*ddb));
2852
2853         for_each_pipe(dev_priv, pipe) {
2854                 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2855                         continue;
2856
2857                 for_each_plane(dev_priv, pipe, plane) {
2858                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2859                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2860                                                    val);
2861                 }
2862
2863                 val = I915_READ(CUR_BUF_CFG(pipe));
2864                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2865                                            val);
2866         }
2867 }
2868
2869 static unsigned int
2870 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2871                              const struct drm_plane_state *pstate,
2872                              int y)
2873 {
2874         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2875         struct drm_framebuffer *fb = pstate->fb;
2876
2877         /* for planar format */
2878         if (fb->pixel_format == DRM_FORMAT_NV12) {
2879                 if (y)  /* y-plane data rate */
2880                         return intel_crtc->config->pipe_src_w *
2881                                 intel_crtc->config->pipe_src_h *
2882                                 drm_format_plane_cpp(fb->pixel_format, 0);
2883                 else    /* uv-plane data rate */
2884                         return (intel_crtc->config->pipe_src_w/2) *
2885                                 (intel_crtc->config->pipe_src_h/2) *
2886                                 drm_format_plane_cpp(fb->pixel_format, 1);
2887         }
2888
2889         /* for packed formats */
2890         return intel_crtc->config->pipe_src_w *
2891                 intel_crtc->config->pipe_src_h *
2892                 drm_format_plane_cpp(fb->pixel_format, 0);
2893 }
2894
2895 /*
2896  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2897  * a 8192x4096@32bpp framebuffer:
2898  *   3 * 4096 * 8192  * 4 < 2^32
2899  */
2900 static unsigned int
2901 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2902 {
2903         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2904         struct drm_device *dev = intel_crtc->base.dev;
2905         const struct intel_plane *intel_plane;
2906         unsigned int total_data_rate = 0;
2907
2908         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2909                 const struct drm_plane_state *pstate = intel_plane->base.state;
2910
2911                 if (pstate->fb == NULL)
2912                         continue;
2913
2914                 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2915                         continue;
2916
2917                 /* packed/uv */
2918                 total_data_rate += skl_plane_relative_data_rate(cstate,
2919                                                                 pstate,
2920                                                                 0);
2921
2922                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2923                         /* y-plane */
2924                         total_data_rate += skl_plane_relative_data_rate(cstate,
2925                                                                         pstate,
2926                                                                         1);
2927         }
2928
2929         return total_data_rate;
2930 }
2931
2932 static void
2933 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
2934                       struct skl_ddb_allocation *ddb /* out */)
2935 {
2936         struct drm_crtc *crtc = cstate->base.crtc;
2937         struct drm_device *dev = crtc->dev;
2938         struct drm_i915_private *dev_priv = to_i915(dev);
2939         struct intel_wm_config *config = &dev_priv->wm.config;
2940         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2941         struct intel_plane *intel_plane;
2942         enum pipe pipe = intel_crtc->pipe;
2943         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2944         uint16_t alloc_size, start, cursor_blocks;
2945         uint16_t minimum[I915_MAX_PLANES];
2946         uint16_t y_minimum[I915_MAX_PLANES];
2947         unsigned int total_data_rate;
2948
2949         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
2950         alloc_size = skl_ddb_entry_size(alloc);
2951         if (alloc_size == 0) {
2952                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2953                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2954                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2955                 return;
2956         }
2957
2958         cursor_blocks = skl_cursor_allocation(config);
2959         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2960         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2961
2962         alloc_size -= cursor_blocks;
2963         alloc->end -= cursor_blocks;
2964
2965         /* 1. Allocate the mininum required blocks for each active plane */
2966         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2967                 struct drm_plane *plane = &intel_plane->base;
2968                 struct drm_framebuffer *fb = plane->state->fb;
2969                 int id = skl_wm_plane_id(intel_plane);
2970
2971                 if (fb == NULL)
2972                         continue;
2973                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
2974                         continue;
2975
2976                 minimum[id] = 8;
2977                 alloc_size -= minimum[id];
2978                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2979                 alloc_size -= y_minimum[id];
2980         }
2981
2982         /*
2983          * 2. Distribute the remaining space in proportion to the amount of
2984          * data each plane needs to fetch from memory.
2985          *
2986          * FIXME: we may not allocate every single block here.
2987          */
2988         total_data_rate = skl_get_total_relative_data_rate(cstate);
2989
2990         start = alloc->start;
2991         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2992                 struct drm_plane *plane = &intel_plane->base;
2993                 struct drm_plane_state *pstate = intel_plane->base.state;
2994                 unsigned int data_rate, y_data_rate;
2995                 uint16_t plane_blocks, y_plane_blocks = 0;
2996                 int id = skl_wm_plane_id(intel_plane);
2997
2998                 if (pstate->fb == NULL)
2999                         continue;
3000                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3001                         continue;
3002
3003                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3004
3005                 /*
3006                  * allocation for (packed formats) or (uv-plane part of planar format):
3007                  * promote the expression to 64 bits to avoid overflowing, the
3008                  * result is < available as data_rate / total_data_rate < 1
3009                  */
3010                 plane_blocks = minimum[id];
3011                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3012                                         total_data_rate);
3013
3014                 ddb->plane[pipe][id].start = start;
3015                 ddb->plane[pipe][id].end = start + plane_blocks;
3016
3017                 start += plane_blocks;
3018
3019                 /*
3020                  * allocation for y_plane part of planar format:
3021                  */
3022                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3023                         y_data_rate = skl_plane_relative_data_rate(cstate,
3024                                                                    pstate,
3025                                                                    1);
3026                         y_plane_blocks = y_minimum[id];
3027                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3028                                                 total_data_rate);
3029
3030                         ddb->y_plane[pipe][id].start = start;
3031                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3032
3033                         start += y_plane_blocks;
3034                 }
3035
3036         }
3037
3038 }
3039
3040 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3041 {
3042         /* TODO: Take into account the scalers once we support them */
3043         return config->base.adjusted_mode.crtc_clock;
3044 }
3045
3046 /*
3047  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3048  * for the read latency) and cpp should always be <= 8, so that
3049  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3050  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3051 */
3052 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3053 {
3054         uint32_t wm_intermediate_val, ret;
3055
3056         if (latency == 0)
3057                 return UINT_MAX;
3058
3059         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3060         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3061
3062         return ret;
3063 }
3064
3065 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3066                                uint32_t horiz_pixels, uint8_t cpp,
3067                                uint64_t tiling, uint32_t latency)
3068 {
3069         uint32_t ret;
3070         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3071         uint32_t wm_intermediate_val;
3072
3073         if (latency == 0)
3074                 return UINT_MAX;
3075
3076         plane_bytes_per_line = horiz_pixels * cpp;
3077
3078         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3079             tiling == I915_FORMAT_MOD_Yf_TILED) {
3080                 plane_bytes_per_line *= 4;
3081                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3082                 plane_blocks_per_line /= 4;
3083         } else {
3084                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3085         }
3086
3087         wm_intermediate_val = latency * pixel_rate;
3088         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3089                                 plane_blocks_per_line;
3090
3091         return ret;
3092 }
3093
3094 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3095                                        const struct intel_crtc *intel_crtc)
3096 {
3097         struct drm_device *dev = intel_crtc->base.dev;
3098         struct drm_i915_private *dev_priv = dev->dev_private;
3099         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3100
3101         /*
3102          * If ddb allocation of pipes changed, it may require recalculation of
3103          * watermarks
3104          */
3105         if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3106                 return true;
3107
3108         return false;
3109 }
3110
3111 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3112                                  struct intel_crtc_state *cstate,
3113                                  struct intel_plane *intel_plane,
3114                                  uint16_t ddb_allocation,
3115                                  int level,
3116                                  uint16_t *out_blocks, /* out */
3117                                  uint8_t *out_lines /* out */)
3118 {
3119         struct drm_plane *plane = &intel_plane->base;
3120         struct drm_framebuffer *fb = plane->state->fb;
3121         uint32_t latency = dev_priv->wm.skl_latency[level];
3122         uint32_t method1, method2;
3123         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3124         uint32_t res_blocks, res_lines;
3125         uint32_t selected_result;
3126         uint8_t cpp;
3127
3128         if (latency == 0 || !cstate->base.active || !fb)
3129                 return false;
3130
3131         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3132         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3133                                  cpp, latency);
3134         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3135                                  cstate->base.adjusted_mode.crtc_htotal,
3136                                  cstate->pipe_src_w,
3137                                  cpp, fb->modifier[0],
3138                                  latency);
3139
3140         plane_bytes_per_line = cstate->pipe_src_w * cpp;
3141         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3142
3143         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3144             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3145                 uint32_t min_scanlines = 4;
3146                 uint32_t y_tile_minimum;
3147                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3148                         int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3149                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3150                                 drm_format_plane_cpp(fb->pixel_format, 0);
3151
3152                         switch (cpp) {
3153                         case 1:
3154                                 min_scanlines = 16;
3155                                 break;
3156                         case 2:
3157                                 min_scanlines = 8;
3158                                 break;
3159                         case 8:
3160                                 WARN(1, "Unsupported pixel depth for rotation");
3161                         }
3162                 }
3163                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3164                 selected_result = max(method2, y_tile_minimum);
3165         } else {
3166                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3167                         selected_result = min(method1, method2);
3168                 else
3169                         selected_result = method1;
3170         }
3171
3172         res_blocks = selected_result + 1;
3173         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3174
3175         if (level >= 1 && level <= 7) {
3176                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3177                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3178                         res_lines += 4;
3179                 else
3180                         res_blocks++;
3181         }
3182
3183         if (res_blocks >= ddb_allocation || res_lines > 31)
3184                 return false;
3185
3186         *out_blocks = res_blocks;
3187         *out_lines = res_lines;
3188
3189         return true;
3190 }
3191
3192 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3193                                  struct skl_ddb_allocation *ddb,
3194                                  struct intel_crtc_state *cstate,
3195                                  int level,
3196                                  struct skl_wm_level *result)
3197 {
3198         struct drm_device *dev = dev_priv->dev;
3199         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3200         struct intel_plane *intel_plane;
3201         uint16_t ddb_blocks;
3202         enum pipe pipe = intel_crtc->pipe;
3203
3204         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3205                 int i = skl_wm_plane_id(intel_plane);
3206
3207                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3208
3209                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3210                                                 cstate,
3211                                                 intel_plane,
3212                                                 ddb_blocks,
3213                                                 level,
3214                                                 &result->plane_res_b[i],
3215                                                 &result->plane_res_l[i]);
3216         }
3217 }
3218
3219 static uint32_t
3220 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3221 {
3222         if (!cstate->base.active)
3223                 return 0;
3224
3225         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3226                 return 0;
3227
3228         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3229                             skl_pipe_pixel_rate(cstate));
3230 }
3231
3232 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3233                                       struct skl_wm_level *trans_wm /* out */)
3234 {
3235         struct drm_crtc *crtc = cstate->base.crtc;
3236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3237         struct intel_plane *intel_plane;
3238
3239         if (!cstate->base.active)
3240                 return;
3241
3242         /* Until we know more, just disable transition WMs */
3243         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3244                 int i = skl_wm_plane_id(intel_plane);
3245
3246                 trans_wm->plane_en[i] = false;
3247         }
3248 }
3249
3250 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3251                                 struct skl_ddb_allocation *ddb,
3252                                 struct skl_pipe_wm *pipe_wm)
3253 {
3254         struct drm_device *dev = cstate->base.crtc->dev;
3255         const struct drm_i915_private *dev_priv = dev->dev_private;
3256         int level, max_level = ilk_wm_max_level(dev);
3257
3258         for (level = 0; level <= max_level; level++) {
3259                 skl_compute_wm_level(dev_priv, ddb, cstate,
3260                                      level, &pipe_wm->wm[level]);
3261         }
3262         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3263
3264         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3265 }
3266
3267 static void skl_compute_wm_results(struct drm_device *dev,
3268                                    struct skl_pipe_wm *p_wm,
3269                                    struct skl_wm_values *r,
3270                                    struct intel_crtc *intel_crtc)
3271 {
3272         int level, max_level = ilk_wm_max_level(dev);
3273         enum pipe pipe = intel_crtc->pipe;
3274         uint32_t temp;
3275         int i;
3276
3277         for (level = 0; level <= max_level; level++) {
3278                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3279                         temp = 0;
3280
3281                         temp |= p_wm->wm[level].plane_res_l[i] <<
3282                                         PLANE_WM_LINES_SHIFT;
3283                         temp |= p_wm->wm[level].plane_res_b[i];
3284                         if (p_wm->wm[level].plane_en[i])
3285                                 temp |= PLANE_WM_EN;
3286
3287                         r->plane[pipe][i][level] = temp;
3288                 }
3289
3290                 temp = 0;
3291
3292                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3293                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3294
3295                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3296                         temp |= PLANE_WM_EN;
3297
3298                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3299
3300         }
3301
3302         /* transition WMs */
3303         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3304                 temp = 0;
3305                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3306                 temp |= p_wm->trans_wm.plane_res_b[i];
3307                 if (p_wm->trans_wm.plane_en[i])
3308                         temp |= PLANE_WM_EN;
3309
3310                 r->plane_trans[pipe][i] = temp;
3311         }
3312
3313         temp = 0;
3314         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3315         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3316         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3317                 temp |= PLANE_WM_EN;
3318
3319         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3320
3321         r->wm_linetime[pipe] = p_wm->linetime;
3322 }
3323
3324 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3325                                 i915_reg_t reg,
3326                                 const struct skl_ddb_entry *entry)
3327 {
3328         if (entry->end)
3329                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3330         else
3331                 I915_WRITE(reg, 0);
3332 }
3333
3334 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3335                                 const struct skl_wm_values *new)
3336 {
3337         struct drm_device *dev = dev_priv->dev;
3338         struct intel_crtc *crtc;
3339
3340         for_each_intel_crtc(dev, crtc) {
3341                 int i, level, max_level = ilk_wm_max_level(dev);
3342                 enum pipe pipe = crtc->pipe;
3343
3344                 if (!new->dirty[pipe])
3345                         continue;
3346
3347                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3348
3349                 for (level = 0; level <= max_level; level++) {
3350                         for (i = 0; i < intel_num_planes(crtc); i++)
3351                                 I915_WRITE(PLANE_WM(pipe, i, level),
3352                                            new->plane[pipe][i][level]);
3353                         I915_WRITE(CUR_WM(pipe, level),
3354                                    new->plane[pipe][PLANE_CURSOR][level]);
3355                 }
3356                 for (i = 0; i < intel_num_planes(crtc); i++)
3357                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3358                                    new->plane_trans[pipe][i]);
3359                 I915_WRITE(CUR_WM_TRANS(pipe),
3360                            new->plane_trans[pipe][PLANE_CURSOR]);
3361
3362                 for (i = 0; i < intel_num_planes(crtc); i++) {
3363                         skl_ddb_entry_write(dev_priv,
3364                                             PLANE_BUF_CFG(pipe, i),
3365                                             &new->ddb.plane[pipe][i]);
3366                         skl_ddb_entry_write(dev_priv,
3367                                             PLANE_NV12_BUF_CFG(pipe, i),
3368                                             &new->ddb.y_plane[pipe][i]);
3369                 }
3370
3371                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3372                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3373         }
3374 }
3375
3376 /*
3377  * When setting up a new DDB allocation arrangement, we need to correctly
3378  * sequence the times at which the new allocations for the pipes are taken into
3379  * account or we'll have pipes fetching from space previously allocated to
3380  * another pipe.
3381  *
3382  * Roughly the sequence looks like:
3383  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3384  *     overlapping with a previous light-up pipe (another way to put it is:
3385  *     pipes with their new allocation strickly included into their old ones).
3386  *  2. re-allocate the other pipes that get their allocation reduced
3387  *  3. allocate the pipes having their allocation increased
3388  *
3389  * Steps 1. and 2. are here to take care of the following case:
3390  * - Initially DDB looks like this:
3391  *     |   B    |   C    |
3392  * - enable pipe A.
3393  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3394  *   allocation
3395  *     |  A  |  B  |  C  |
3396  *
3397  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3398  */
3399
3400 static void
3401 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3402 {
3403         int plane;
3404
3405         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3406
3407         for_each_plane(dev_priv, pipe, plane) {
3408                 I915_WRITE(PLANE_SURF(pipe, plane),
3409                            I915_READ(PLANE_SURF(pipe, plane)));
3410         }
3411         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3412 }
3413
3414 static bool
3415 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3416                             const struct skl_ddb_allocation *new,
3417                             enum pipe pipe)
3418 {
3419         uint16_t old_size, new_size;
3420
3421         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3422         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3423
3424         return old_size != new_size &&
3425                new->pipe[pipe].start >= old->pipe[pipe].start &&
3426                new->pipe[pipe].end <= old->pipe[pipe].end;
3427 }
3428
3429 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3430                                 struct skl_wm_values *new_values)
3431 {
3432         struct drm_device *dev = dev_priv->dev;
3433         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3434         bool reallocated[I915_MAX_PIPES] = {};
3435         struct intel_crtc *crtc;
3436         enum pipe pipe;
3437
3438         new_ddb = &new_values->ddb;
3439         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3440
3441         /*
3442          * First pass: flush the pipes with the new allocation contained into
3443          * the old space.
3444          *
3445          * We'll wait for the vblank on those pipes to ensure we can safely
3446          * re-allocate the freed space without this pipe fetching from it.
3447          */
3448         for_each_intel_crtc(dev, crtc) {
3449                 if (!crtc->active)
3450                         continue;
3451
3452                 pipe = crtc->pipe;
3453
3454                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3455                         continue;
3456
3457                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3458                 intel_wait_for_vblank(dev, pipe);
3459
3460                 reallocated[pipe] = true;
3461         }
3462
3463
3464         /*
3465          * Second pass: flush the pipes that are having their allocation
3466          * reduced, but overlapping with a previous allocation.
3467          *
3468          * Here as well we need to wait for the vblank to make sure the freed
3469          * space is not used anymore.
3470          */
3471         for_each_intel_crtc(dev, crtc) {
3472                 if (!crtc->active)
3473                         continue;
3474
3475                 pipe = crtc->pipe;
3476
3477                 if (reallocated[pipe])
3478                         continue;
3479
3480                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3481                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3482                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3483                         intel_wait_for_vblank(dev, pipe);
3484                         reallocated[pipe] = true;
3485                 }
3486         }
3487
3488         /*
3489          * Third pass: flush the pipes that got more space allocated.
3490          *
3491          * We don't need to actively wait for the update here, next vblank
3492          * will just get more DDB space with the correct WM values.
3493          */
3494         for_each_intel_crtc(dev, crtc) {
3495                 if (!crtc->active)
3496                         continue;
3497
3498                 pipe = crtc->pipe;
3499
3500                 /*
3501                  * At this point, only the pipes more space than before are
3502                  * left to re-allocate.
3503                  */
3504                 if (reallocated[pipe])
3505                         continue;
3506
3507                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3508         }
3509 }
3510
3511 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3512                                struct skl_ddb_allocation *ddb, /* out */
3513                                struct skl_pipe_wm *pipe_wm /* out */)
3514 {
3515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3517
3518         skl_allocate_pipe_ddb(cstate, ddb);
3519         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3520
3521         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3522                 return false;
3523
3524         intel_crtc->wm.active.skl = *pipe_wm;
3525
3526         return true;
3527 }
3528
3529 static void skl_update_other_pipe_wm(struct drm_device *dev,
3530                                      struct drm_crtc *crtc,
3531                                      struct skl_wm_values *r)
3532 {
3533         struct intel_crtc *intel_crtc;
3534         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3535
3536         /*
3537          * If the WM update hasn't changed the allocation for this_crtc (the
3538          * crtc we are currently computing the new WM values for), other
3539          * enabled crtcs will keep the same allocation and we don't need to
3540          * recompute anything for them.
3541          */
3542         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3543                 return;
3544
3545         /*
3546          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3547          * other active pipes need new DDB allocation and WM values.
3548          */
3549         for_each_intel_crtc(dev, intel_crtc) {
3550                 struct skl_pipe_wm pipe_wm = {};
3551                 bool wm_changed;
3552
3553                 if (this_crtc->pipe == intel_crtc->pipe)
3554                         continue;
3555
3556                 if (!intel_crtc->active)
3557                         continue;
3558
3559                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3560                                                 &r->ddb, &pipe_wm);
3561
3562                 /*
3563                  * If we end up re-computing the other pipe WM values, it's
3564                  * because it was really needed, so we expect the WM values to
3565                  * be different.
3566                  */
3567                 WARN_ON(!wm_changed);
3568
3569                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3570                 r->dirty[intel_crtc->pipe] = true;
3571         }
3572 }
3573
3574 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3575 {
3576         watermarks->wm_linetime[pipe] = 0;
3577         memset(watermarks->plane[pipe], 0,
3578                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3579         memset(watermarks->plane_trans[pipe],
3580                0, sizeof(uint32_t) * I915_MAX_PLANES);
3581         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3582
3583         /* Clear ddb entries for pipe */
3584         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3585         memset(&watermarks->ddb.plane[pipe], 0,
3586                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3587         memset(&watermarks->ddb.y_plane[pipe], 0,
3588                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3589         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3590                sizeof(struct skl_ddb_entry));
3591
3592 }
3593
3594 static void skl_update_wm(struct drm_crtc *crtc)
3595 {
3596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597         struct drm_device *dev = crtc->dev;
3598         struct drm_i915_private *dev_priv = dev->dev_private;
3599         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3600         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3601         struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3602
3603
3604         /* Clear all dirty flags */
3605         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3606
3607         skl_clear_wm(results, intel_crtc->pipe);
3608
3609         if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3610                 return;
3611
3612         skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3613         results->dirty[intel_crtc->pipe] = true;
3614
3615         skl_update_other_pipe_wm(dev, crtc, results);
3616         skl_write_wm_values(dev_priv, results);
3617         skl_flush_wm_values(dev_priv, results);
3618
3619         /* store the new configuration */
3620         dev_priv->wm.skl_hw = *results;
3621 }
3622
3623 static void ilk_compute_wm_config(struct drm_device *dev,
3624                                   struct intel_wm_config *config)
3625 {
3626         struct intel_crtc *crtc;
3627
3628         /* Compute the currently _active_ config */
3629         for_each_intel_crtc(dev, crtc) {
3630                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3631
3632                 if (!wm->pipe_enabled)
3633                         continue;
3634
3635                 config->sprites_enabled |= wm->sprites_enabled;
3636                 config->sprites_scaled |= wm->sprites_scaled;
3637                 config->num_pipes_active++;
3638         }
3639 }
3640
3641 static void ilk_program_watermarks(struct intel_crtc_state *cstate)
3642 {
3643         struct drm_crtc *crtc = cstate->base.crtc;
3644         struct drm_device *dev = crtc->dev;
3645         struct drm_i915_private *dev_priv = to_i915(dev);
3646         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3647         struct ilk_wm_maximums max;
3648         struct intel_wm_config config = {};
3649         struct ilk_wm_values results = {};
3650         enum intel_ddb_partitioning partitioning;
3651
3652         ilk_compute_wm_config(dev, &config);
3653
3654         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3655         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3656
3657         /* 5/6 split only in single pipe config on IVB+ */
3658         if (INTEL_INFO(dev)->gen >= 7 &&
3659             config.num_pipes_active == 1 && config.sprites_enabled) {
3660                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3661                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3662
3663                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3664         } else {
3665                 best_lp_wm = &lp_wm_1_2;
3666         }
3667
3668         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3669                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3670
3671         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3672
3673         ilk_write_wm_values(dev_priv, &results);
3674 }
3675
3676 static void ilk_update_wm(struct drm_crtc *crtc)
3677 {
3678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3679         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3680
3681         WARN_ON(cstate->base.active != intel_crtc->active);
3682
3683         /*
3684          * IVB workaround: must disable low power watermarks for at least
3685          * one frame before enabling scaling.  LP watermarks can be re-enabled
3686          * when scaling is disabled.
3687          *
3688          * WaCxSRDisabledForSpriteScaling:ivb
3689          */
3690         if (cstate->disable_lp_wm) {
3691                 ilk_disable_lp_wm(crtc->dev);
3692                 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3693         }
3694
3695         intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3696
3697         ilk_program_watermarks(cstate);
3698 }
3699
3700 static void skl_pipe_wm_active_state(uint32_t val,
3701                                      struct skl_pipe_wm *active,
3702                                      bool is_transwm,
3703                                      bool is_cursor,
3704                                      int i,
3705                                      int level)
3706 {
3707         bool is_enabled = (val & PLANE_WM_EN) != 0;
3708
3709         if (!is_transwm) {
3710                 if (!is_cursor) {
3711                         active->wm[level].plane_en[i] = is_enabled;
3712                         active->wm[level].plane_res_b[i] =
3713                                         val & PLANE_WM_BLOCKS_MASK;
3714                         active->wm[level].plane_res_l[i] =
3715                                         (val >> PLANE_WM_LINES_SHIFT) &
3716                                                 PLANE_WM_LINES_MASK;
3717                 } else {
3718                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3719                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3720                                         val & PLANE_WM_BLOCKS_MASK;
3721                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3722                                         (val >> PLANE_WM_LINES_SHIFT) &
3723                                                 PLANE_WM_LINES_MASK;
3724                 }
3725         } else {
3726                 if (!is_cursor) {
3727                         active->trans_wm.plane_en[i] = is_enabled;
3728                         active->trans_wm.plane_res_b[i] =
3729                                         val & PLANE_WM_BLOCKS_MASK;
3730                         active->trans_wm.plane_res_l[i] =
3731                                         (val >> PLANE_WM_LINES_SHIFT) &
3732                                                 PLANE_WM_LINES_MASK;
3733                 } else {
3734                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3735                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3736                                         val & PLANE_WM_BLOCKS_MASK;
3737                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3738                                         (val >> PLANE_WM_LINES_SHIFT) &
3739                                                 PLANE_WM_LINES_MASK;
3740                 }
3741         }
3742 }
3743
3744 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3745 {
3746         struct drm_device *dev = crtc->dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3750         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3751         struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3752         enum pipe pipe = intel_crtc->pipe;
3753         int level, i, max_level;
3754         uint32_t temp;
3755
3756         max_level = ilk_wm_max_level(dev);
3757
3758         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3759
3760         for (level = 0; level <= max_level; level++) {
3761                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3762                         hw->plane[pipe][i][level] =
3763                                         I915_READ(PLANE_WM(pipe, i, level));
3764                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3765         }
3766
3767         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3768                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3769         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3770
3771         if (!intel_crtc->active)
3772                 return;
3773
3774         hw->dirty[pipe] = true;
3775
3776         active->linetime = hw->wm_linetime[pipe];
3777
3778         for (level = 0; level <= max_level; level++) {
3779                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3780                         temp = hw->plane[pipe][i][level];
3781                         skl_pipe_wm_active_state(temp, active, false,
3782                                                 false, i, level);
3783                 }
3784                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3785                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3786         }
3787
3788         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3789                 temp = hw->plane_trans[pipe][i];
3790                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3791         }
3792
3793         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3794         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3795
3796         intel_crtc->wm.active.skl = *active;
3797 }
3798
3799 void skl_wm_get_hw_state(struct drm_device *dev)
3800 {
3801         struct drm_i915_private *dev_priv = dev->dev_private;
3802         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3803         struct drm_crtc *crtc;
3804
3805         skl_ddb_get_hw_state(dev_priv, ddb);
3806         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3807                 skl_pipe_wm_get_hw_state(crtc);
3808 }
3809
3810 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3811 {
3812         struct drm_device *dev = crtc->dev;
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3816         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3817         struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3818         enum pipe pipe = intel_crtc->pipe;
3819         static const i915_reg_t wm0_pipe_reg[] = {
3820                 [PIPE_A] = WM0_PIPEA_ILK,
3821                 [PIPE_B] = WM0_PIPEB_ILK,
3822                 [PIPE_C] = WM0_PIPEC_IVB,
3823         };
3824
3825         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3826         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3827                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3828
3829         active->pipe_enabled = intel_crtc->active;
3830
3831         if (active->pipe_enabled) {
3832                 u32 tmp = hw->wm_pipe[pipe];
3833
3834                 /*
3835                  * For active pipes LP0 watermark is marked as
3836                  * enabled, and LP1+ watermaks as disabled since
3837                  * we can't really reverse compute them in case
3838                  * multiple pipes are active.
3839                  */
3840                 active->wm[0].enable = true;
3841                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3842                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3843                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3844                 active->linetime = hw->wm_linetime[pipe];
3845         } else {
3846                 int level, max_level = ilk_wm_max_level(dev);
3847
3848                 /*
3849                  * For inactive pipes, all watermark levels
3850                  * should be marked as enabled but zeroed,
3851                  * which is what we'd compute them to.
3852                  */
3853                 for (level = 0; level <= max_level; level++)
3854                         active->wm[level].enable = true;
3855         }
3856
3857         intel_crtc->wm.active.ilk = *active;
3858 }
3859
3860 #define _FW_WM(value, plane) \
3861         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3862 #define _FW_WM_VLV(value, plane) \
3863         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3864
3865 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3866                                struct vlv_wm_values *wm)
3867 {
3868         enum pipe pipe;
3869         uint32_t tmp;
3870
3871         for_each_pipe(dev_priv, pipe) {
3872                 tmp = I915_READ(VLV_DDL(pipe));
3873
3874                 wm->ddl[pipe].primary =
3875                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3876                 wm->ddl[pipe].cursor =
3877                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3878                 wm->ddl[pipe].sprite[0] =
3879                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3880                 wm->ddl[pipe].sprite[1] =
3881                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3882         }
3883
3884         tmp = I915_READ(DSPFW1);
3885         wm->sr.plane = _FW_WM(tmp, SR);
3886         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3887         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3888         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3889
3890         tmp = I915_READ(DSPFW2);
3891         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3892         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3893         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3894
3895         tmp = I915_READ(DSPFW3);
3896         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3897
3898         if (IS_CHERRYVIEW(dev_priv)) {
3899                 tmp = I915_READ(DSPFW7_CHV);
3900                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3901                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3902
3903                 tmp = I915_READ(DSPFW8_CHV);
3904                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3905                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3906
3907                 tmp = I915_READ(DSPFW9_CHV);
3908                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3909                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3910
3911                 tmp = I915_READ(DSPHOWM);
3912                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3913                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3914                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3915                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3916                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3917                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3918                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3919                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3920                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3921                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3922         } else {
3923                 tmp = I915_READ(DSPFW7);
3924                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3925                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3926
3927                 tmp = I915_READ(DSPHOWM);
3928                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3929                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3930                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3931                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3932                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3933                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3934                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3935         }
3936 }
3937
3938 #undef _FW_WM
3939 #undef _FW_WM_VLV
3940
3941 void vlv_wm_get_hw_state(struct drm_device *dev)
3942 {
3943         struct drm_i915_private *dev_priv = to_i915(dev);
3944         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3945         struct intel_plane *plane;
3946         enum pipe pipe;
3947         u32 val;
3948
3949         vlv_read_wm_values(dev_priv, wm);
3950
3951         for_each_intel_plane(dev, plane) {
3952                 switch (plane->base.type) {
3953                         int sprite;
3954                 case DRM_PLANE_TYPE_CURSOR:
3955                         plane->wm.fifo_size = 63;
3956                         break;
3957                 case DRM_PLANE_TYPE_PRIMARY:
3958                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3959                         break;
3960                 case DRM_PLANE_TYPE_OVERLAY:
3961                         sprite = plane->plane;
3962                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3963                         break;
3964                 }
3965         }
3966
3967         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3968         wm->level = VLV_WM_LEVEL_PM2;
3969
3970         if (IS_CHERRYVIEW(dev_priv)) {
3971                 mutex_lock(&dev_priv->rps.hw_lock);
3972
3973                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3974                 if (val & DSP_MAXFIFO_PM5_ENABLE)
3975                         wm->level = VLV_WM_LEVEL_PM5;
3976
3977                 /*
3978                  * If DDR DVFS is disabled in the BIOS, Punit
3979                  * will never ack the request. So if that happens
3980                  * assume we don't have to enable/disable DDR DVFS
3981                  * dynamically. To test that just set the REQ_ACK
3982                  * bit to poke the Punit, but don't change the
3983                  * HIGH/LOW bits so that we don't actually change
3984                  * the current state.
3985                  */
3986                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3987                 val |= FORCE_DDR_FREQ_REQ_ACK;
3988                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3989
3990                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3991                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3992                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3993                                       "assuming DDR DVFS is disabled\n");
3994                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3995                 } else {
3996                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3997                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3998                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3999                 }
4000
4001                 mutex_unlock(&dev_priv->rps.hw_lock);
4002         }
4003
4004         for_each_pipe(dev_priv, pipe)
4005                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4006                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4007                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4008
4009         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4010                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4011 }
4012
4013 void ilk_wm_get_hw_state(struct drm_device *dev)
4014 {
4015         struct drm_i915_private *dev_priv = dev->dev_private;
4016         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4017         struct drm_crtc *crtc;
4018
4019         for_each_crtc(dev, crtc)
4020                 ilk_pipe_wm_get_hw_state(crtc);
4021
4022         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4023         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4024         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4025
4026         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4027         if (INTEL_INFO(dev)->gen >= 7) {
4028                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4029                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4030         }
4031
4032         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4033                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4034                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4035         else if (IS_IVYBRIDGE(dev))
4036                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4037                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4038
4039         hw->enable_fbc_wm =
4040                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4041 }
4042
4043 /**
4044  * intel_update_watermarks - update FIFO watermark values based on current modes
4045  *
4046  * Calculate watermark values for the various WM regs based on current mode
4047  * and plane configuration.
4048  *
4049  * There are several cases to deal with here:
4050  *   - normal (i.e. non-self-refresh)
4051  *   - self-refresh (SR) mode
4052  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4053  *   - lines are small relative to FIFO size (buffer can hold more than 2
4054  *     lines), so need to account for TLB latency
4055  *
4056  *   The normal calculation is:
4057  *     watermark = dotclock * bytes per pixel * latency
4058  *   where latency is platform & configuration dependent (we assume pessimal
4059  *   values here).
4060  *
4061  *   The SR calculation is:
4062  *     watermark = (trunc(latency/line time)+1) * surface width *
4063  *       bytes per pixel
4064  *   where
4065  *     line time = htotal / dotclock
4066  *     surface width = hdisplay for normal plane and 64 for cursor
4067  *   and latency is assumed to be high, as above.
4068  *
4069  * The final value programmed to the register should always be rounded up,
4070  * and include an extra 2 entries to account for clock crossings.
4071  *
4072  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4073  * to set the non-SR watermarks to 8.
4074  */
4075 void intel_update_watermarks(struct drm_crtc *crtc)
4076 {
4077         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4078
4079         if (dev_priv->display.update_wm)
4080                 dev_priv->display.update_wm(crtc);
4081 }
4082
4083 /*
4084  * Lock protecting IPS related data structures
4085  */
4086 DEFINE_SPINLOCK(mchdev_lock);
4087
4088 /* Global for IPS driver to get at the current i915 device. Protected by
4089  * mchdev_lock. */
4090 static struct drm_i915_private *i915_mch_dev;
4091
4092 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4093 {
4094         struct drm_i915_private *dev_priv = dev->dev_private;
4095         u16 rgvswctl;
4096
4097         assert_spin_locked(&mchdev_lock);
4098
4099         rgvswctl = I915_READ16(MEMSWCTL);
4100         if (rgvswctl & MEMCTL_CMD_STS) {
4101                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4102                 return false; /* still busy with another command */
4103         }
4104
4105         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4106                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4107         I915_WRITE16(MEMSWCTL, rgvswctl);
4108         POSTING_READ16(MEMSWCTL);
4109
4110         rgvswctl |= MEMCTL_CMD_STS;
4111         I915_WRITE16(MEMSWCTL, rgvswctl);
4112
4113         return true;
4114 }
4115
4116 static void ironlake_enable_drps(struct drm_device *dev)
4117 {
4118         struct drm_i915_private *dev_priv = dev->dev_private;
4119         u32 rgvmodectl = I915_READ(MEMMODECTL);
4120         u8 fmax, fmin, fstart, vstart;
4121
4122         spin_lock_irq(&mchdev_lock);
4123
4124         /* Enable temp reporting */
4125         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4126         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4127
4128         /* 100ms RC evaluation intervals */
4129         I915_WRITE(RCUPEI, 100000);
4130         I915_WRITE(RCDNEI, 100000);
4131
4132         /* Set max/min thresholds to 90ms and 80ms respectively */
4133         I915_WRITE(RCBMAXAVG, 90000);
4134         I915_WRITE(RCBMINAVG, 80000);
4135
4136         I915_WRITE(MEMIHYST, 1);
4137
4138         /* Set up min, max, and cur for interrupt handling */
4139         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4140         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4141         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4142                 MEMMODE_FSTART_SHIFT;
4143
4144         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4145                 PXVFREQ_PX_SHIFT;
4146
4147         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4148         dev_priv->ips.fstart = fstart;
4149
4150         dev_priv->ips.max_delay = fstart;
4151         dev_priv->ips.min_delay = fmin;
4152         dev_priv->ips.cur_delay = fstart;
4153
4154         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4155                          fmax, fmin, fstart);
4156
4157         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4158
4159         /*
4160          * Interrupts will be enabled in ironlake_irq_postinstall
4161          */
4162
4163         I915_WRITE(VIDSTART, vstart);
4164         POSTING_READ(VIDSTART);
4165
4166         rgvmodectl |= MEMMODE_SWMODE_EN;
4167         I915_WRITE(MEMMODECTL, rgvmodectl);
4168
4169         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4170                 DRM_ERROR("stuck trying to change perf mode\n");
4171         mdelay(1);
4172
4173         ironlake_set_drps(dev, fstart);
4174
4175         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4176                 I915_READ(DDREC) + I915_READ(CSIEC);
4177         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4178         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4179         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4180
4181         spin_unlock_irq(&mchdev_lock);
4182 }
4183
4184 static void ironlake_disable_drps(struct drm_device *dev)
4185 {
4186         struct drm_i915_private *dev_priv = dev->dev_private;
4187         u16 rgvswctl;
4188
4189         spin_lock_irq(&mchdev_lock);
4190
4191         rgvswctl = I915_READ16(MEMSWCTL);
4192
4193         /* Ack interrupts, disable EFC interrupt */
4194         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4195         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4196         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4197         I915_WRITE(DEIIR, DE_PCU_EVENT);
4198         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4199
4200         /* Go back to the starting frequency */
4201         ironlake_set_drps(dev, dev_priv->ips.fstart);
4202         mdelay(1);
4203         rgvswctl |= MEMCTL_CMD_STS;
4204         I915_WRITE(MEMSWCTL, rgvswctl);
4205         mdelay(1);
4206
4207         spin_unlock_irq(&mchdev_lock);
4208 }
4209
4210 /* There's a funny hw issue where the hw returns all 0 when reading from
4211  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4212  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4213  * all limits and the gpu stuck at whatever frequency it is at atm).
4214  */
4215 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4216 {
4217         u32 limits;
4218
4219         /* Only set the down limit when we've reached the lowest level to avoid
4220          * getting more interrupts, otherwise leave this clear. This prevents a
4221          * race in the hw when coming out of rc6: There's a tiny window where
4222          * the hw runs at the minimal clock before selecting the desired
4223          * frequency, if the down threshold expires in that window we will not
4224          * receive a down interrupt. */
4225         if (IS_GEN9(dev_priv->dev)) {
4226                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4227                 if (val <= dev_priv->rps.min_freq_softlimit)
4228                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4229         } else {
4230                 limits = dev_priv->rps.max_freq_softlimit << 24;
4231                 if (val <= dev_priv->rps.min_freq_softlimit)
4232                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4233         }
4234
4235         return limits;
4236 }
4237
4238 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4239 {
4240         int new_power;
4241         u32 threshold_up = 0, threshold_down = 0; /* in % */
4242         u32 ei_up = 0, ei_down = 0;
4243
4244         new_power = dev_priv->rps.power;
4245         switch (dev_priv->rps.power) {
4246         case LOW_POWER:
4247                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4248                         new_power = BETWEEN;
4249                 break;
4250
4251         case BETWEEN:
4252                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4253                         new_power = LOW_POWER;
4254                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4255                         new_power = HIGH_POWER;
4256                 break;
4257
4258         case HIGH_POWER:
4259                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4260                         new_power = BETWEEN;
4261                 break;
4262         }
4263         /* Max/min bins are special */
4264         if (val <= dev_priv->rps.min_freq_softlimit)
4265                 new_power = LOW_POWER;
4266         if (val >= dev_priv->rps.max_freq_softlimit)
4267                 new_power = HIGH_POWER;
4268         if (new_power == dev_priv->rps.power)
4269                 return;
4270
4271         /* Note the units here are not exactly 1us, but 1280ns. */
4272         switch (new_power) {
4273         case LOW_POWER:
4274                 /* Upclock if more than 95% busy over 16ms */
4275                 ei_up = 16000;
4276                 threshold_up = 95;
4277
4278                 /* Downclock if less than 85% busy over 32ms */
4279                 ei_down = 32000;
4280                 threshold_down = 85;
4281                 break;
4282
4283         case BETWEEN:
4284                 /* Upclock if more than 90% busy over 13ms */
4285                 ei_up = 13000;
4286                 threshold_up = 90;
4287
4288                 /* Downclock if less than 75% busy over 32ms */
4289                 ei_down = 32000;
4290                 threshold_down = 75;
4291                 break;
4292
4293         case HIGH_POWER:
4294                 /* Upclock if more than 85% busy over 10ms */
4295                 ei_up = 10000;
4296                 threshold_up = 85;
4297
4298                 /* Downclock if less than 60% busy over 32ms */
4299                 ei_down = 32000;
4300                 threshold_down = 60;
4301                 break;
4302         }
4303
4304         I915_WRITE(GEN6_RP_UP_EI,
4305                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4306         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4307                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4308
4309         I915_WRITE(GEN6_RP_DOWN_EI,
4310                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4311         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4312                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4313
4314          I915_WRITE(GEN6_RP_CONTROL,
4315                     GEN6_RP_MEDIA_TURBO |
4316                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4317                     GEN6_RP_MEDIA_IS_GFX |
4318                     GEN6_RP_ENABLE |
4319                     GEN6_RP_UP_BUSY_AVG |
4320                     GEN6_RP_DOWN_IDLE_AVG);
4321
4322         dev_priv->rps.power = new_power;
4323         dev_priv->rps.up_threshold = threshold_up;
4324         dev_priv->rps.down_threshold = threshold_down;
4325         dev_priv->rps.last_adj = 0;
4326 }
4327
4328 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4329 {
4330         u32 mask = 0;
4331
4332         if (val > dev_priv->rps.min_freq_softlimit)
4333                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4334         if (val < dev_priv->rps.max_freq_softlimit)
4335                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4336
4337         mask &= dev_priv->pm_rps_events;
4338
4339         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4340 }
4341
4342 /* gen6_set_rps is called to update the frequency request, but should also be
4343  * called when the range (min_delay and max_delay) is modified so that we can
4344  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4345 static void gen6_set_rps(struct drm_device *dev, u8 val)
4346 {
4347         struct drm_i915_private *dev_priv = dev->dev_private;
4348
4349         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4350         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4351                 return;
4352
4353         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4354         WARN_ON(val > dev_priv->rps.max_freq);
4355         WARN_ON(val < dev_priv->rps.min_freq);
4356
4357         /* min/max delay may still have been modified so be sure to
4358          * write the limits value.
4359          */
4360         if (val != dev_priv->rps.cur_freq) {
4361                 gen6_set_rps_thresholds(dev_priv, val);
4362
4363                 if (IS_GEN9(dev))
4364                         I915_WRITE(GEN6_RPNSWREQ,
4365                                    GEN9_FREQUENCY(val));
4366                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4367                         I915_WRITE(GEN6_RPNSWREQ,
4368                                    HSW_FREQUENCY(val));
4369                 else
4370                         I915_WRITE(GEN6_RPNSWREQ,
4371                                    GEN6_FREQUENCY(val) |
4372                                    GEN6_OFFSET(0) |
4373                                    GEN6_AGGRESSIVE_TURBO);
4374         }
4375
4376         /* Make sure we continue to get interrupts
4377          * until we hit the minimum or maximum frequencies.
4378          */
4379         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4380         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4381
4382         POSTING_READ(GEN6_RPNSWREQ);
4383
4384         dev_priv->rps.cur_freq = val;
4385         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4386 }
4387
4388 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4389 {
4390         struct drm_i915_private *dev_priv = dev->dev_private;
4391
4392         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4393         WARN_ON(val > dev_priv->rps.max_freq);
4394         WARN_ON(val < dev_priv->rps.min_freq);
4395
4396         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4397                       "Odd GPU freq value\n"))
4398                 val &= ~1;
4399
4400         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4401
4402         if (val != dev_priv->rps.cur_freq) {
4403                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4404                 if (!IS_CHERRYVIEW(dev_priv))
4405                         gen6_set_rps_thresholds(dev_priv, val);
4406         }
4407
4408         dev_priv->rps.cur_freq = val;
4409         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4410 }
4411
4412 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4413  *
4414  * * If Gfx is Idle, then
4415  * 1. Forcewake Media well.
4416  * 2. Request idle freq.
4417  * 3. Release Forcewake of Media well.
4418 */
4419 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4420 {
4421         u32 val = dev_priv->rps.idle_freq;
4422
4423         if (dev_priv->rps.cur_freq <= val)
4424                 return;
4425
4426         /* Wake up the media well, as that takes a lot less
4427          * power than the Render well. */
4428         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4429         valleyview_set_rps(dev_priv->dev, val);
4430         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4431 }
4432
4433 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4434 {
4435         mutex_lock(&dev_priv->rps.hw_lock);
4436         if (dev_priv->rps.enabled) {
4437                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4438                         gen6_rps_reset_ei(dev_priv);
4439                 I915_WRITE(GEN6_PMINTRMSK,
4440                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4441         }
4442         mutex_unlock(&dev_priv->rps.hw_lock);
4443 }
4444
4445 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4446 {
4447         struct drm_device *dev = dev_priv->dev;
4448
4449         mutex_lock(&dev_priv->rps.hw_lock);
4450         if (dev_priv->rps.enabled) {
4451                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4452                         vlv_set_rps_idle(dev_priv);
4453                 else
4454                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4455                 dev_priv->rps.last_adj = 0;
4456                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4457         }
4458         mutex_unlock(&dev_priv->rps.hw_lock);
4459
4460         spin_lock(&dev_priv->rps.client_lock);
4461         while (!list_empty(&dev_priv->rps.clients))
4462                 list_del_init(dev_priv->rps.clients.next);
4463         spin_unlock(&dev_priv->rps.client_lock);
4464 }
4465
4466 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4467                     struct intel_rps_client *rps,
4468                     unsigned long submitted)
4469 {
4470         /* This is intentionally racy! We peek at the state here, then
4471          * validate inside the RPS worker.
4472          */
4473         if (!(dev_priv->mm.busy &&
4474               dev_priv->rps.enabled &&
4475               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4476                 return;
4477
4478         /* Force a RPS boost (and don't count it against the client) if
4479          * the GPU is severely congested.
4480          */
4481         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4482                 rps = NULL;
4483
4484         spin_lock(&dev_priv->rps.client_lock);
4485         if (rps == NULL || list_empty(&rps->link)) {
4486                 spin_lock_irq(&dev_priv->irq_lock);
4487                 if (dev_priv->rps.interrupts_enabled) {
4488                         dev_priv->rps.client_boost = true;
4489                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4490                 }
4491                 spin_unlock_irq(&dev_priv->irq_lock);
4492
4493                 if (rps != NULL) {
4494                         list_add(&rps->link, &dev_priv->rps.clients);
4495                         rps->boosts++;
4496                 } else
4497                         dev_priv->rps.boosts++;
4498         }
4499         spin_unlock(&dev_priv->rps.client_lock);
4500 }
4501
4502 void intel_set_rps(struct drm_device *dev, u8 val)
4503 {
4504         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4505                 valleyview_set_rps(dev, val);
4506         else
4507                 gen6_set_rps(dev, val);
4508 }
4509
4510 static void gen9_disable_rps(struct drm_device *dev)
4511 {
4512         struct drm_i915_private *dev_priv = dev->dev_private;
4513
4514         I915_WRITE(GEN6_RC_CONTROL, 0);
4515         I915_WRITE(GEN9_PG_ENABLE, 0);
4516 }
4517
4518 static void gen6_disable_rps(struct drm_device *dev)
4519 {
4520         struct drm_i915_private *dev_priv = dev->dev_private;
4521
4522         I915_WRITE(GEN6_RC_CONTROL, 0);
4523         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4524 }
4525
4526 static void cherryview_disable_rps(struct drm_device *dev)
4527 {
4528         struct drm_i915_private *dev_priv = dev->dev_private;
4529
4530         I915_WRITE(GEN6_RC_CONTROL, 0);
4531 }
4532
4533 static void valleyview_disable_rps(struct drm_device *dev)
4534 {
4535         struct drm_i915_private *dev_priv = dev->dev_private;
4536
4537         /* we're doing forcewake before Disabling RC6,
4538          * This what the BIOS expects when going into suspend */
4539         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4540
4541         I915_WRITE(GEN6_RC_CONTROL, 0);
4542
4543         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4544 }
4545
4546 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4547 {
4548         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4549                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4550                         mode = GEN6_RC_CTL_RC6_ENABLE;
4551                 else
4552                         mode = 0;
4553         }
4554         if (HAS_RC6p(dev))
4555                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4556                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4557                               onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4558                               onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4559
4560         else
4561                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4562                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4563 }
4564
4565 static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4566 {
4567         struct drm_i915_private *dev_priv = dev->dev_private;
4568         bool enable_rc6 = true;
4569         unsigned long rc6_ctx_base;
4570
4571         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4572                 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4573                 enable_rc6 = false;
4574         }
4575
4576         /*
4577          * The exact context size is not known for BXT, so assume a page size
4578          * for this check.
4579          */
4580         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4581         if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) &&
4582               (rc6_ctx_base + PAGE_SIZE <= dev_priv->gtt.stolen_reserved_base +
4583                                         dev_priv->gtt.stolen_reserved_size))) {
4584                 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4585                 enable_rc6 = false;
4586         }
4587
4588         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4589               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4590               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4591               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4592                 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4593                 enable_rc6 = false;
4594         }
4595
4596         if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4597                                             GEN6_RC_CTL_HW_ENABLE)) &&
4598             ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4599              !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4600                 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4601                 enable_rc6 = false;
4602         }
4603
4604         return enable_rc6;
4605 }
4606
4607 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4608 {
4609         /* No RC6 before Ironlake and code is gone for ilk. */
4610         if (INTEL_INFO(dev)->gen < 6)
4611                 return 0;
4612
4613         if (!enable_rc6)
4614                 return 0;
4615
4616         if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4617                 DRM_INFO("RC6 disabled by BIOS\n");
4618                 return 0;
4619         }
4620
4621         /* Respect the kernel parameter if it is set */
4622         if (enable_rc6 >= 0) {
4623                 int mask;
4624
4625                 if (HAS_RC6p(dev))
4626                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4627                                INTEL_RC6pp_ENABLE;
4628                 else
4629                         mask = INTEL_RC6_ENABLE;
4630
4631                 if ((enable_rc6 & mask) != enable_rc6)
4632                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4633                                       enable_rc6 & mask, enable_rc6, mask);
4634
4635                 return enable_rc6 & mask;
4636         }
4637
4638         if (IS_IVYBRIDGE(dev))
4639                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4640
4641         return INTEL_RC6_ENABLE;
4642 }
4643
4644 int intel_enable_rc6(const struct drm_device *dev)
4645 {
4646         return i915.enable_rc6;
4647 }
4648
4649 static void gen6_init_rps_frequencies(struct drm_device *dev)
4650 {
4651         struct drm_i915_private *dev_priv = dev->dev_private;
4652         uint32_t rp_state_cap;
4653         u32 ddcc_status = 0;
4654         int ret;
4655
4656         /* All of these values are in units of 50MHz */
4657         dev_priv->rps.cur_freq          = 0;
4658         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4659         if (IS_BROXTON(dev)) {
4660                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4661                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4662                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4663                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4664         } else {
4665                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4666                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4667                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4668                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4669         }
4670
4671         /* hw_max = RP0 until we check for overclocking */
4672         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4673
4674         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4675         if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4676             IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4677                 ret = sandybridge_pcode_read(dev_priv,
4678                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4679                                         &ddcc_status);
4680                 if (0 == ret)
4681                         dev_priv->rps.efficient_freq =
4682                                 clamp_t(u8,
4683                                         ((ddcc_status >> 8) & 0xff),
4684                                         dev_priv->rps.min_freq,
4685                                         dev_priv->rps.max_freq);
4686         }
4687
4688         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4689                 /* Store the frequency values in 16.66 MHZ units, which is
4690                    the natural hardware unit for SKL */
4691                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4692                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4693                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4694                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4695                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4696         }
4697
4698         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4699
4700         /* Preserve min/max settings in case of re-init */
4701         if (dev_priv->rps.max_freq_softlimit == 0)
4702                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4703
4704         if (dev_priv->rps.min_freq_softlimit == 0) {
4705                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4706                         dev_priv->rps.min_freq_softlimit =
4707                                 max_t(int, dev_priv->rps.efficient_freq,
4708                                       intel_freq_opcode(dev_priv, 450));
4709                 else
4710                         dev_priv->rps.min_freq_softlimit =
4711                                 dev_priv->rps.min_freq;
4712         }
4713 }
4714
4715 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4716 static void gen9_enable_rps(struct drm_device *dev)
4717 {
4718         struct drm_i915_private *dev_priv = dev->dev_private;
4719
4720         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4721
4722         gen6_init_rps_frequencies(dev);
4723
4724         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4725         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4726                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4727                 return;
4728         }
4729
4730         /* Program defaults and thresholds for RPS*/
4731         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4732                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4733
4734         /* 1 second timeout*/
4735         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4736                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4737
4738         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4739
4740         /* Leaning on the below call to gen6_set_rps to program/setup the
4741          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4742          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4743         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4744         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4745
4746         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4747 }
4748
4749 static void gen9_enable_rc6(struct drm_device *dev)
4750 {
4751         struct drm_i915_private *dev_priv = dev->dev_private;
4752         struct intel_engine_cs *ring;
4753         uint32_t rc6_mask = 0;
4754         int unused;
4755
4756         /* 1a: Software RC state - RC0 */
4757         I915_WRITE(GEN6_RC_STATE, 0);
4758
4759         /* 1b: Get forcewake during program sequence. Although the driver
4760          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4761         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4762
4763         /* 2a: Disable RC states. */
4764         I915_WRITE(GEN6_RC_CONTROL, 0);
4765
4766         /* 2b: Program RC6 thresholds.*/
4767
4768         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4769         if (IS_SKYLAKE(dev))
4770                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4771         else
4772                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4773         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4774         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4775         for_each_ring(ring, dev_priv, unused)
4776                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4777
4778         if (HAS_GUC_UCODE(dev))
4779                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4780
4781         I915_WRITE(GEN6_RC_SLEEP, 0);
4782
4783         /* 2c: Program Coarse Power Gating Policies. */
4784         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4785         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4786
4787         /* 3a: Enable RC6 */
4788         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4789                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4790         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4791         /* WaRsUseTimeoutMode */
4792         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4793             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4794                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4795                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4796                            GEN7_RC_CTL_TO_MODE |
4797                            rc6_mask);
4798         } else {
4799                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4800                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4801                            GEN6_RC_CTL_EI_MODE(1) |
4802                            rc6_mask);
4803         }
4804
4805         /*
4806          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4807          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4808          */
4809         if (NEEDS_WaRsDisableCoarsePowerGating(dev))
4810                 I915_WRITE(GEN9_PG_ENABLE, 0);
4811         else
4812                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4813                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4814
4815         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4816
4817 }
4818
4819 static void gen8_enable_rps(struct drm_device *dev)
4820 {
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822         struct intel_engine_cs *ring;
4823         uint32_t rc6_mask = 0;
4824         int unused;
4825
4826         /* 1a: Software RC state - RC0 */
4827         I915_WRITE(GEN6_RC_STATE, 0);
4828
4829         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4830          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4831         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4832
4833         /* 2a: Disable RC states. */
4834         I915_WRITE(GEN6_RC_CONTROL, 0);
4835
4836         /* Initialize rps frequencies */
4837         gen6_init_rps_frequencies(dev);
4838
4839         /* 2b: Program RC6 thresholds.*/
4840         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4841         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4842         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4843         for_each_ring(ring, dev_priv, unused)
4844                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4845         I915_WRITE(GEN6_RC_SLEEP, 0);
4846         if (IS_BROADWELL(dev))
4847                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4848         else
4849                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4850
4851         /* 3: Enable RC6 */
4852         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4853                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4854         intel_print_rc6_info(dev, rc6_mask);
4855         if (IS_BROADWELL(dev))
4856                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4857                                 GEN7_RC_CTL_TO_MODE |
4858                                 rc6_mask);
4859         else
4860                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4861                                 GEN6_RC_CTL_EI_MODE(1) |
4862                                 rc6_mask);
4863
4864         /* 4 Program defaults and thresholds for RPS*/
4865         I915_WRITE(GEN6_RPNSWREQ,
4866                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4867         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4868                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4869         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4870         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4871
4872         /* Docs recommend 900MHz, and 300 MHz respectively */
4873         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4874                    dev_priv->rps.max_freq_softlimit << 24 |
4875                    dev_priv->rps.min_freq_softlimit << 16);
4876
4877         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4878         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4879         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4880         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4881
4882         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4883
4884         /* 5: Enable RPS */
4885         I915_WRITE(GEN6_RP_CONTROL,
4886                    GEN6_RP_MEDIA_TURBO |
4887                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4888                    GEN6_RP_MEDIA_IS_GFX |
4889                    GEN6_RP_ENABLE |
4890                    GEN6_RP_UP_BUSY_AVG |
4891                    GEN6_RP_DOWN_IDLE_AVG);
4892
4893         /* 6: Ring frequency + overclocking (our driver does this later */
4894
4895         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4896         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4897
4898         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4899 }
4900
4901 static void gen6_enable_rps(struct drm_device *dev)
4902 {
4903         struct drm_i915_private *dev_priv = dev->dev_private;
4904         struct intel_engine_cs *ring;
4905         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4906         u32 gtfifodbg;
4907         int rc6_mode;
4908         int i, ret;
4909
4910         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4911
4912         /* Here begins a magic sequence of register writes to enable
4913          * auto-downclocking.
4914          *
4915          * Perhaps there might be some value in exposing these to
4916          * userspace...
4917          */
4918         I915_WRITE(GEN6_RC_STATE, 0);
4919
4920         /* Clear the DBG now so we don't confuse earlier errors */
4921         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4922                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4923                 I915_WRITE(GTFIFODBG, gtfifodbg);
4924         }
4925
4926         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4927
4928         /* Initialize rps frequencies */
4929         gen6_init_rps_frequencies(dev);
4930
4931         /* disable the counters and set deterministic thresholds */
4932         I915_WRITE(GEN6_RC_CONTROL, 0);
4933
4934         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4935         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4936         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4937         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4938         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4939
4940         for_each_ring(ring, dev_priv, i)
4941                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4942
4943         I915_WRITE(GEN6_RC_SLEEP, 0);
4944         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4945         if (IS_IVYBRIDGE(dev))
4946                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4947         else
4948                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4949         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4950         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4951
4952         /* Check if we are enabling RC6 */
4953         rc6_mode = intel_enable_rc6(dev_priv->dev);
4954         if (rc6_mode & INTEL_RC6_ENABLE)
4955                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4956
4957         /* We don't use those on Haswell */
4958         if (!IS_HASWELL(dev)) {
4959                 if (rc6_mode & INTEL_RC6p_ENABLE)
4960                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4961
4962                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4963                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4964         }
4965
4966         intel_print_rc6_info(dev, rc6_mask);
4967
4968         I915_WRITE(GEN6_RC_CONTROL,
4969                    rc6_mask |
4970                    GEN6_RC_CTL_EI_MODE(1) |
4971                    GEN6_RC_CTL_HW_ENABLE);
4972
4973         /* Power down if completely idle for over 50ms */
4974         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4975         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4976
4977         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4978         if (ret)
4979                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4980
4981         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4982         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4983                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4984                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4985                                  (pcu_mbox & 0xff) * 50);
4986                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4987         }
4988
4989         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4990         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4991
4992         rc6vids = 0;
4993         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4994         if (IS_GEN6(dev) && ret) {
4995                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4996         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4997                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4998                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4999                 rc6vids &= 0xffff00;
5000                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5001                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5002                 if (ret)
5003                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5004         }
5005
5006         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5007 }
5008
5009 static void __gen6_update_ring_freq(struct drm_device *dev)
5010 {
5011         struct drm_i915_private *dev_priv = dev->dev_private;
5012         int min_freq = 15;
5013         unsigned int gpu_freq;
5014         unsigned int max_ia_freq, min_ring_freq;
5015         unsigned int max_gpu_freq, min_gpu_freq;
5016         int scaling_factor = 180;
5017         struct cpufreq_policy *policy;
5018
5019         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5020
5021         policy = cpufreq_cpu_get(0);
5022         if (policy) {
5023                 max_ia_freq = policy->cpuinfo.max_freq;
5024                 cpufreq_cpu_put(policy);
5025         } else {
5026                 /*
5027                  * Default to measured freq if none found, PCU will ensure we
5028                  * don't go over
5029                  */
5030                 max_ia_freq = tsc_khz;
5031         }
5032
5033         /* Convert from kHz to MHz */
5034         max_ia_freq /= 1000;
5035
5036         min_ring_freq = I915_READ(DCLK) & 0xf;
5037         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5038         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5039
5040         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5041                 /* Convert GT frequency to 50 HZ units */
5042                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5043                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5044         } else {
5045                 min_gpu_freq = dev_priv->rps.min_freq;
5046                 max_gpu_freq = dev_priv->rps.max_freq;
5047         }
5048
5049         /*
5050          * For each potential GPU frequency, load a ring frequency we'd like
5051          * to use for memory access.  We do this by specifying the IA frequency
5052          * the PCU should use as a reference to determine the ring frequency.
5053          */
5054         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5055                 int diff = max_gpu_freq - gpu_freq;
5056                 unsigned int ia_freq = 0, ring_freq = 0;
5057
5058                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5059                         /*
5060                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5061                          * No floor required for ring frequency on SKL.
5062                          */
5063                         ring_freq = gpu_freq;
5064                 } else if (INTEL_INFO(dev)->gen >= 8) {
5065                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5066                         ring_freq = max(min_ring_freq, gpu_freq);
5067                 } else if (IS_HASWELL(dev)) {
5068                         ring_freq = mult_frac(gpu_freq, 5, 4);
5069                         ring_freq = max(min_ring_freq, ring_freq);
5070                         /* leave ia_freq as the default, chosen by cpufreq */
5071                 } else {
5072                         /* On older processors, there is no separate ring
5073                          * clock domain, so in order to boost the bandwidth
5074                          * of the ring, we need to upclock the CPU (ia_freq).
5075                          *
5076                          * For GPU frequencies less than 750MHz,
5077                          * just use the lowest ring freq.
5078                          */
5079                         if (gpu_freq < min_freq)
5080                                 ia_freq = 800;
5081                         else
5082                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5083                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5084                 }
5085
5086                 sandybridge_pcode_write(dev_priv,
5087                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5088                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5089                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5090                                         gpu_freq);
5091         }
5092 }
5093
5094 void gen6_update_ring_freq(struct drm_device *dev)
5095 {
5096         struct drm_i915_private *dev_priv = dev->dev_private;
5097
5098         if (!HAS_CORE_RING_FREQ(dev))
5099                 return;
5100
5101         mutex_lock(&dev_priv->rps.hw_lock);
5102         __gen6_update_ring_freq(dev);
5103         mutex_unlock(&dev_priv->rps.hw_lock);
5104 }
5105
5106 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5107 {
5108         struct drm_device *dev = dev_priv->dev;
5109         u32 val, rp0;
5110
5111         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5112
5113         switch (INTEL_INFO(dev)->eu_total) {
5114         case 8:
5115                 /* (2 * 4) config */
5116                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5117                 break;
5118         case 12:
5119                 /* (2 * 6) config */
5120                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5121                 break;
5122         case 16:
5123                 /* (2 * 8) config */
5124         default:
5125                 /* Setting (2 * 8) Min RP0 for any other combination */
5126                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5127                 break;
5128         }
5129
5130         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5131
5132         return rp0;
5133 }
5134
5135 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5136 {
5137         u32 val, rpe;
5138
5139         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5140         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5141
5142         return rpe;
5143 }
5144
5145 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5146 {
5147         u32 val, rp1;
5148
5149         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5150         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5151
5152         return rp1;
5153 }
5154
5155 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5156 {
5157         u32 val, rp1;
5158
5159         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5160
5161         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5162
5163         return rp1;
5164 }
5165
5166 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5167 {
5168         u32 val, rp0;
5169
5170         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5171
5172         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5173         /* Clamp to max */
5174         rp0 = min_t(u32, rp0, 0xea);
5175
5176         return rp0;
5177 }
5178
5179 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5180 {
5181         u32 val, rpe;
5182
5183         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5184         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5185         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5186         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5187
5188         return rpe;
5189 }
5190
5191 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5192 {
5193         u32 val;
5194
5195         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5196         /*
5197          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5198          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5199          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5200          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5201          * to make sure it matches what Punit accepts.
5202          */
5203         return max_t(u32, val, 0xc0);
5204 }
5205
5206 /* Check that the pctx buffer wasn't move under us. */
5207 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5208 {
5209         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5210
5211         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5212                              dev_priv->vlv_pctx->stolen->start);
5213 }
5214
5215
5216 /* Check that the pcbr address is not empty. */
5217 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5218 {
5219         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5220
5221         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5222 }
5223
5224 static void cherryview_setup_pctx(struct drm_device *dev)
5225 {
5226         struct drm_i915_private *dev_priv = dev->dev_private;
5227         unsigned long pctx_paddr, paddr;
5228         struct i915_gtt *gtt = &dev_priv->gtt;
5229         u32 pcbr;
5230         int pctx_size = 32*1024;
5231
5232         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5233
5234         pcbr = I915_READ(VLV_PCBR);
5235         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5236                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5237                 paddr = (dev_priv->mm.stolen_base +
5238                          (gtt->stolen_size - pctx_size));
5239
5240                 pctx_paddr = (paddr & (~4095));
5241                 I915_WRITE(VLV_PCBR, pctx_paddr);
5242         }
5243
5244         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5245 }
5246
5247 static void valleyview_setup_pctx(struct drm_device *dev)
5248 {
5249         struct drm_i915_private *dev_priv = dev->dev_private;
5250         struct drm_i915_gem_object *pctx;
5251         unsigned long pctx_paddr;
5252         u32 pcbr;
5253         int pctx_size = 24*1024;
5254
5255         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5256
5257         pcbr = I915_READ(VLV_PCBR);
5258         if (pcbr) {
5259                 /* BIOS set it up already, grab the pre-alloc'd space */
5260                 int pcbr_offset;
5261
5262                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5263                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5264                                                                       pcbr_offset,
5265                                                                       I915_GTT_OFFSET_NONE,
5266                                                                       pctx_size);
5267                 goto out;
5268         }
5269
5270         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5271
5272         /*
5273          * From the Gunit register HAS:
5274          * The Gfx driver is expected to program this register and ensure
5275          * proper allocation within Gfx stolen memory.  For example, this
5276          * register should be programmed such than the PCBR range does not
5277          * overlap with other ranges, such as the frame buffer, protected
5278          * memory, or any other relevant ranges.
5279          */
5280         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5281         if (!pctx) {
5282                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5283                 return;
5284         }
5285
5286         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5287         I915_WRITE(VLV_PCBR, pctx_paddr);
5288
5289 out:
5290         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5291         dev_priv->vlv_pctx = pctx;
5292 }
5293
5294 static void valleyview_cleanup_pctx(struct drm_device *dev)
5295 {
5296         struct drm_i915_private *dev_priv = dev->dev_private;
5297
5298         if (WARN_ON(!dev_priv->vlv_pctx))
5299                 return;
5300
5301         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5302         dev_priv->vlv_pctx = NULL;
5303 }
5304
5305 static void valleyview_init_gt_powersave(struct drm_device *dev)
5306 {
5307         struct drm_i915_private *dev_priv = dev->dev_private;
5308         u32 val;
5309
5310         valleyview_setup_pctx(dev);
5311
5312         mutex_lock(&dev_priv->rps.hw_lock);
5313
5314         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5315         switch ((val >> 6) & 3) {
5316         case 0:
5317         case 1:
5318                 dev_priv->mem_freq = 800;
5319                 break;
5320         case 2:
5321                 dev_priv->mem_freq = 1066;
5322                 break;
5323         case 3:
5324                 dev_priv->mem_freq = 1333;
5325                 break;
5326         }
5327         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5328
5329         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5330         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5331         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5332                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5333                          dev_priv->rps.max_freq);
5334
5335         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5336         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5337                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5338                          dev_priv->rps.efficient_freq);
5339
5340         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5341         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5342                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5343                          dev_priv->rps.rp1_freq);
5344
5345         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5346         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5347                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5348                          dev_priv->rps.min_freq);
5349
5350         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5351
5352         /* Preserve min/max settings in case of re-init */
5353         if (dev_priv->rps.max_freq_softlimit == 0)
5354                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5355
5356         if (dev_priv->rps.min_freq_softlimit == 0)
5357                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5358
5359         mutex_unlock(&dev_priv->rps.hw_lock);
5360 }
5361
5362 static void cherryview_init_gt_powersave(struct drm_device *dev)
5363 {
5364         struct drm_i915_private *dev_priv = dev->dev_private;
5365         u32 val;
5366
5367         cherryview_setup_pctx(dev);
5368
5369         mutex_lock(&dev_priv->rps.hw_lock);
5370
5371         mutex_lock(&dev_priv->sb_lock);
5372         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5373         mutex_unlock(&dev_priv->sb_lock);
5374
5375         switch ((val >> 2) & 0x7) {
5376         case 3:
5377                 dev_priv->mem_freq = 2000;
5378                 break;
5379         default:
5380                 dev_priv->mem_freq = 1600;
5381                 break;
5382         }
5383         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5384
5385         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5386         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5387         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5388                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5389                          dev_priv->rps.max_freq);
5390
5391         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5392         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5393                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5394                          dev_priv->rps.efficient_freq);
5395
5396         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5397         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5398                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5399                          dev_priv->rps.rp1_freq);
5400
5401         /* PUnit validated range is only [RPe, RP0] */
5402         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5403         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5404                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5405                          dev_priv->rps.min_freq);
5406
5407         WARN_ONCE((dev_priv->rps.max_freq |
5408                    dev_priv->rps.efficient_freq |
5409                    dev_priv->rps.rp1_freq |
5410                    dev_priv->rps.min_freq) & 1,
5411                   "Odd GPU freq values\n");
5412
5413         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5414
5415         /* Preserve min/max settings in case of re-init */
5416         if (dev_priv->rps.max_freq_softlimit == 0)
5417                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5418
5419         if (dev_priv->rps.min_freq_softlimit == 0)
5420                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5421
5422         mutex_unlock(&dev_priv->rps.hw_lock);
5423 }
5424
5425 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5426 {
5427         valleyview_cleanup_pctx(dev);
5428 }
5429
5430 static void cherryview_enable_rps(struct drm_device *dev)
5431 {
5432         struct drm_i915_private *dev_priv = dev->dev_private;
5433         struct intel_engine_cs *ring;
5434         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5435         int i;
5436
5437         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5438
5439         gtfifodbg = I915_READ(GTFIFODBG);
5440         if (gtfifodbg) {
5441                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5442                                  gtfifodbg);
5443                 I915_WRITE(GTFIFODBG, gtfifodbg);
5444         }
5445
5446         cherryview_check_pctx(dev_priv);
5447
5448         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5449          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5450         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5451
5452         /*  Disable RC states. */
5453         I915_WRITE(GEN6_RC_CONTROL, 0);
5454
5455         /* 2a: Program RC6 thresholds.*/
5456         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5457         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5458         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5459
5460         for_each_ring(ring, dev_priv, i)
5461                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5462         I915_WRITE(GEN6_RC_SLEEP, 0);
5463
5464         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5465         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5466
5467         /* allows RC6 residency counter to work */
5468         I915_WRITE(VLV_COUNTER_CONTROL,
5469                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5470                                       VLV_MEDIA_RC6_COUNT_EN |
5471                                       VLV_RENDER_RC6_COUNT_EN));
5472
5473         /* For now we assume BIOS is allocating and populating the PCBR  */
5474         pcbr = I915_READ(VLV_PCBR);
5475
5476         /* 3: Enable RC6 */
5477         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5478                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5479                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5480
5481         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5482
5483         /* 4 Program defaults and thresholds for RPS*/
5484         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5485         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5486         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5487         I915_WRITE(GEN6_RP_UP_EI, 66000);
5488         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5489
5490         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5491
5492         /* 5: Enable RPS */
5493         I915_WRITE(GEN6_RP_CONTROL,
5494                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5495                    GEN6_RP_MEDIA_IS_GFX |
5496                    GEN6_RP_ENABLE |
5497                    GEN6_RP_UP_BUSY_AVG |
5498                    GEN6_RP_DOWN_IDLE_AVG);
5499
5500         /* Setting Fixed Bias */
5501         val = VLV_OVERRIDE_EN |
5502                   VLV_SOC_TDP_EN |
5503                   CHV_BIAS_CPU_50_SOC_50;
5504         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5505
5506         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5507
5508         /* RPS code assumes GPLL is used */
5509         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5510
5511         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5512         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5513
5514         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5515         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5516                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5517                          dev_priv->rps.cur_freq);
5518
5519         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5520                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5521                          dev_priv->rps.efficient_freq);
5522
5523         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5524
5525         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5526 }
5527
5528 static void valleyview_enable_rps(struct drm_device *dev)
5529 {
5530         struct drm_i915_private *dev_priv = dev->dev_private;
5531         struct intel_engine_cs *ring;
5532         u32 gtfifodbg, val, rc6_mode = 0;
5533         int i;
5534
5535         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5536
5537         valleyview_check_pctx(dev_priv);
5538
5539         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5540                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5541                                  gtfifodbg);
5542                 I915_WRITE(GTFIFODBG, gtfifodbg);
5543         }
5544
5545         /* If VLV, Forcewake all wells, else re-direct to regular path */
5546         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5547
5548         /*  Disable RC states. */
5549         I915_WRITE(GEN6_RC_CONTROL, 0);
5550
5551         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5552         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5553         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5554         I915_WRITE(GEN6_RP_UP_EI, 66000);
5555         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5556
5557         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5558
5559         I915_WRITE(GEN6_RP_CONTROL,
5560                    GEN6_RP_MEDIA_TURBO |
5561                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5562                    GEN6_RP_MEDIA_IS_GFX |
5563                    GEN6_RP_ENABLE |
5564                    GEN6_RP_UP_BUSY_AVG |
5565                    GEN6_RP_DOWN_IDLE_CONT);
5566
5567         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5568         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5569         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5570
5571         for_each_ring(ring, dev_priv, i)
5572                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5573
5574         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5575
5576         /* allows RC6 residency counter to work */
5577         I915_WRITE(VLV_COUNTER_CONTROL,
5578                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5579                                       VLV_RENDER_RC0_COUNT_EN |
5580                                       VLV_MEDIA_RC6_COUNT_EN |
5581                                       VLV_RENDER_RC6_COUNT_EN));
5582
5583         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5584                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5585
5586         intel_print_rc6_info(dev, rc6_mode);
5587
5588         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5589
5590         /* Setting Fixed Bias */
5591         val = VLV_OVERRIDE_EN |
5592                   VLV_SOC_TDP_EN |
5593                   VLV_BIAS_CPU_125_SOC_875;
5594         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5595
5596         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5597
5598         /* RPS code assumes GPLL is used */
5599         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5600
5601         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5602         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5603
5604         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5605         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5606                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5607                          dev_priv->rps.cur_freq);
5608
5609         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5610                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5611                          dev_priv->rps.efficient_freq);
5612
5613         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5614
5615         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5616 }
5617
5618 static unsigned long intel_pxfreq(u32 vidfreq)
5619 {
5620         unsigned long freq;
5621         int div = (vidfreq & 0x3f0000) >> 16;
5622         int post = (vidfreq & 0x3000) >> 12;
5623         int pre = (vidfreq & 0x7);
5624
5625         if (!pre)
5626                 return 0;
5627
5628         freq = ((div * 133333) / ((1<<post) * pre));
5629
5630         return freq;
5631 }
5632
5633 static const struct cparams {
5634         u16 i;
5635         u16 t;
5636         u16 m;
5637         u16 c;
5638 } cparams[] = {
5639         { 1, 1333, 301, 28664 },
5640         { 1, 1066, 294, 24460 },
5641         { 1, 800, 294, 25192 },
5642         { 0, 1333, 276, 27605 },
5643         { 0, 1066, 276, 27605 },
5644         { 0, 800, 231, 23784 },
5645 };
5646
5647 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5648 {
5649         u64 total_count, diff, ret;
5650         u32 count1, count2, count3, m = 0, c = 0;
5651         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5652         int i;
5653
5654         assert_spin_locked(&mchdev_lock);
5655
5656         diff1 = now - dev_priv->ips.last_time1;
5657
5658         /* Prevent division-by-zero if we are asking too fast.
5659          * Also, we don't get interesting results if we are polling
5660          * faster than once in 10ms, so just return the saved value
5661          * in such cases.
5662          */
5663         if (diff1 <= 10)
5664                 return dev_priv->ips.chipset_power;
5665
5666         count1 = I915_READ(DMIEC);
5667         count2 = I915_READ(DDREC);
5668         count3 = I915_READ(CSIEC);
5669
5670         total_count = count1 + count2 + count3;
5671
5672         /* FIXME: handle per-counter overflow */
5673         if (total_count < dev_priv->ips.last_count1) {
5674                 diff = ~0UL - dev_priv->ips.last_count1;
5675                 diff += total_count;
5676         } else {
5677                 diff = total_count - dev_priv->ips.last_count1;
5678         }
5679
5680         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5681                 if (cparams[i].i == dev_priv->ips.c_m &&
5682                     cparams[i].t == dev_priv->ips.r_t) {
5683                         m = cparams[i].m;
5684                         c = cparams[i].c;
5685                         break;
5686                 }
5687         }
5688
5689         diff = div_u64(diff, diff1);
5690         ret = ((m * diff) + c);
5691         ret = div_u64(ret, 10);
5692
5693         dev_priv->ips.last_count1 = total_count;
5694         dev_priv->ips.last_time1 = now;
5695
5696         dev_priv->ips.chipset_power = ret;
5697
5698         return ret;
5699 }
5700
5701 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5702 {
5703         struct drm_device *dev = dev_priv->dev;
5704         unsigned long val;
5705
5706         if (INTEL_INFO(dev)->gen != 5)
5707                 return 0;
5708
5709         spin_lock_irq(&mchdev_lock);
5710
5711         val = __i915_chipset_val(dev_priv);
5712
5713         spin_unlock_irq(&mchdev_lock);
5714
5715         return val;
5716 }
5717
5718 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5719 {
5720         unsigned long m, x, b;
5721         u32 tsfs;
5722
5723         tsfs = I915_READ(TSFS);
5724
5725         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5726         x = I915_READ8(TR1);
5727
5728         b = tsfs & TSFS_INTR_MASK;
5729
5730         return ((m * x) / 127) - b;
5731 }
5732
5733 static int _pxvid_to_vd(u8 pxvid)
5734 {
5735         if (pxvid == 0)
5736                 return 0;
5737
5738         if (pxvid >= 8 && pxvid < 31)
5739                 pxvid = 31;
5740
5741         return (pxvid + 2) * 125;
5742 }
5743
5744 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5745 {
5746         struct drm_device *dev = dev_priv->dev;
5747         const int vd = _pxvid_to_vd(pxvid);
5748         const int vm = vd - 1125;
5749
5750         if (INTEL_INFO(dev)->is_mobile)
5751                 return vm > 0 ? vm : 0;
5752
5753         return vd;
5754 }
5755
5756 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5757 {
5758         u64 now, diff, diffms;
5759         u32 count;
5760
5761         assert_spin_locked(&mchdev_lock);
5762
5763         now = ktime_get_raw_ns();
5764         diffms = now - dev_priv->ips.last_time2;
5765         do_div(diffms, NSEC_PER_MSEC);
5766
5767         /* Don't divide by 0 */
5768         if (!diffms)
5769                 return;
5770
5771         count = I915_READ(GFXEC);
5772
5773         if (count < dev_priv->ips.last_count2) {
5774                 diff = ~0UL - dev_priv->ips.last_count2;
5775                 diff += count;
5776         } else {
5777                 diff = count - dev_priv->ips.last_count2;
5778         }
5779
5780         dev_priv->ips.last_count2 = count;
5781         dev_priv->ips.last_time2 = now;
5782
5783         /* More magic constants... */
5784         diff = diff * 1181;
5785         diff = div_u64(diff, diffms * 10);
5786         dev_priv->ips.gfx_power = diff;
5787 }
5788
5789 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5790 {
5791         struct drm_device *dev = dev_priv->dev;
5792
5793         if (INTEL_INFO(dev)->gen != 5)
5794                 return;
5795
5796         spin_lock_irq(&mchdev_lock);
5797
5798         __i915_update_gfx_val(dev_priv);
5799
5800         spin_unlock_irq(&mchdev_lock);
5801 }
5802
5803 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5804 {
5805         unsigned long t, corr, state1, corr2, state2;
5806         u32 pxvid, ext_v;
5807
5808         assert_spin_locked(&mchdev_lock);
5809
5810         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5811         pxvid = (pxvid >> 24) & 0x7f;
5812         ext_v = pvid_to_extvid(dev_priv, pxvid);
5813
5814         state1 = ext_v;
5815
5816         t = i915_mch_val(dev_priv);
5817
5818         /* Revel in the empirically derived constants */
5819
5820         /* Correction factor in 1/100000 units */
5821         if (t > 80)
5822                 corr = ((t * 2349) + 135940);
5823         else if (t >= 50)
5824                 corr = ((t * 964) + 29317);
5825         else /* < 50 */
5826                 corr = ((t * 301) + 1004);
5827
5828         corr = corr * ((150142 * state1) / 10000 - 78642);
5829         corr /= 100000;
5830         corr2 = (corr * dev_priv->ips.corr);
5831
5832         state2 = (corr2 * state1) / 10000;
5833         state2 /= 100; /* convert to mW */
5834
5835         __i915_update_gfx_val(dev_priv);
5836
5837         return dev_priv->ips.gfx_power + state2;
5838 }
5839
5840 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5841 {
5842         struct drm_device *dev = dev_priv->dev;
5843         unsigned long val;
5844
5845         if (INTEL_INFO(dev)->gen != 5)
5846                 return 0;
5847
5848         spin_lock_irq(&mchdev_lock);
5849
5850         val = __i915_gfx_val(dev_priv);
5851
5852         spin_unlock_irq(&mchdev_lock);
5853
5854         return val;
5855 }
5856
5857 /**
5858  * i915_read_mch_val - return value for IPS use
5859  *
5860  * Calculate and return a value for the IPS driver to use when deciding whether
5861  * we have thermal and power headroom to increase CPU or GPU power budget.
5862  */
5863 unsigned long i915_read_mch_val(void)
5864 {
5865         struct drm_i915_private *dev_priv;
5866         unsigned long chipset_val, graphics_val, ret = 0;
5867
5868         spin_lock_irq(&mchdev_lock);
5869         if (!i915_mch_dev)
5870                 goto out_unlock;
5871         dev_priv = i915_mch_dev;
5872
5873         chipset_val = __i915_chipset_val(dev_priv);
5874         graphics_val = __i915_gfx_val(dev_priv);
5875
5876         ret = chipset_val + graphics_val;
5877
5878 out_unlock:
5879         spin_unlock_irq(&mchdev_lock);
5880
5881         return ret;
5882 }
5883 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5884
5885 /**
5886  * i915_gpu_raise - raise GPU frequency limit
5887  *
5888  * Raise the limit; IPS indicates we have thermal headroom.
5889  */
5890 bool i915_gpu_raise(void)
5891 {
5892         struct drm_i915_private *dev_priv;
5893         bool ret = true;
5894
5895         spin_lock_irq(&mchdev_lock);
5896         if (!i915_mch_dev) {
5897                 ret = false;
5898                 goto out_unlock;
5899         }
5900         dev_priv = i915_mch_dev;
5901
5902         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5903                 dev_priv->ips.max_delay--;
5904
5905 out_unlock:
5906         spin_unlock_irq(&mchdev_lock);
5907
5908         return ret;
5909 }
5910 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5911
5912 /**
5913  * i915_gpu_lower - lower GPU frequency limit
5914  *
5915  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5916  * frequency maximum.
5917  */
5918 bool i915_gpu_lower(void)
5919 {
5920         struct drm_i915_private *dev_priv;
5921         bool ret = true;
5922
5923         spin_lock_irq(&mchdev_lock);
5924         if (!i915_mch_dev) {
5925                 ret = false;
5926                 goto out_unlock;
5927         }
5928         dev_priv = i915_mch_dev;
5929
5930         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5931                 dev_priv->ips.max_delay++;
5932
5933 out_unlock:
5934         spin_unlock_irq(&mchdev_lock);
5935
5936         return ret;
5937 }
5938 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5939
5940 /**
5941  * i915_gpu_busy - indicate GPU business to IPS
5942  *
5943  * Tell the IPS driver whether or not the GPU is busy.
5944  */
5945 bool i915_gpu_busy(void)
5946 {
5947         struct drm_i915_private *dev_priv;
5948         struct intel_engine_cs *ring;
5949         bool ret = false;
5950         int i;
5951
5952         spin_lock_irq(&mchdev_lock);
5953         if (!i915_mch_dev)
5954                 goto out_unlock;
5955         dev_priv = i915_mch_dev;
5956
5957         for_each_ring(ring, dev_priv, i)
5958                 ret |= !list_empty(&ring->request_list);
5959
5960 out_unlock:
5961         spin_unlock_irq(&mchdev_lock);
5962
5963         return ret;
5964 }
5965 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5966
5967 /**
5968  * i915_gpu_turbo_disable - disable graphics turbo
5969  *
5970  * Disable graphics turbo by resetting the max frequency and setting the
5971  * current frequency to the default.
5972  */
5973 bool i915_gpu_turbo_disable(void)
5974 {
5975         struct drm_i915_private *dev_priv;
5976         bool ret = true;
5977
5978         spin_lock_irq(&mchdev_lock);
5979         if (!i915_mch_dev) {
5980                 ret = false;
5981                 goto out_unlock;
5982         }
5983         dev_priv = i915_mch_dev;
5984
5985         dev_priv->ips.max_delay = dev_priv->ips.fstart;
5986
5987         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5988                 ret = false;
5989
5990 out_unlock:
5991         spin_unlock_irq(&mchdev_lock);
5992
5993         return ret;
5994 }
5995 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5996
5997 /**
5998  * Tells the intel_ips driver that the i915 driver is now loaded, if
5999  * IPS got loaded first.
6000  *
6001  * This awkward dance is so that neither module has to depend on the
6002  * other in order for IPS to do the appropriate communication of
6003  * GPU turbo limits to i915.
6004  */
6005 static void
6006 ips_ping_for_i915_load(void)
6007 {
6008         void (*link)(void);
6009
6010         link = symbol_get(ips_link_to_i915_driver);
6011         if (link) {
6012                 link();
6013                 symbol_put(ips_link_to_i915_driver);
6014         }
6015 }
6016
6017 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6018 {
6019         /* We only register the i915 ips part with intel-ips once everything is
6020          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6021         spin_lock_irq(&mchdev_lock);
6022         i915_mch_dev = dev_priv;
6023         spin_unlock_irq(&mchdev_lock);
6024
6025         ips_ping_for_i915_load();
6026 }
6027
6028 void intel_gpu_ips_teardown(void)
6029 {
6030         spin_lock_irq(&mchdev_lock);
6031         i915_mch_dev = NULL;
6032         spin_unlock_irq(&mchdev_lock);
6033 }
6034
6035 static void intel_init_emon(struct drm_device *dev)
6036 {
6037         struct drm_i915_private *dev_priv = dev->dev_private;
6038         u32 lcfuse;
6039         u8 pxw[16];
6040         int i;
6041
6042         /* Disable to program */
6043         I915_WRITE(ECR, 0);
6044         POSTING_READ(ECR);
6045
6046         /* Program energy weights for various events */
6047         I915_WRITE(SDEW, 0x15040d00);
6048         I915_WRITE(CSIEW0, 0x007f0000);
6049         I915_WRITE(CSIEW1, 0x1e220004);
6050         I915_WRITE(CSIEW2, 0x04000004);
6051
6052         for (i = 0; i < 5; i++)
6053                 I915_WRITE(PEW(i), 0);
6054         for (i = 0; i < 3; i++)
6055                 I915_WRITE(DEW(i), 0);
6056
6057         /* Program P-state weights to account for frequency power adjustment */
6058         for (i = 0; i < 16; i++) {
6059                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6060                 unsigned long freq = intel_pxfreq(pxvidfreq);
6061                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6062                         PXVFREQ_PX_SHIFT;
6063                 unsigned long val;
6064
6065                 val = vid * vid;
6066                 val *= (freq / 1000);
6067                 val *= 255;
6068                 val /= (127*127*900);
6069                 if (val > 0xff)
6070                         DRM_ERROR("bad pxval: %ld\n", val);
6071                 pxw[i] = val;
6072         }
6073         /* Render standby states get 0 weight */
6074         pxw[14] = 0;
6075         pxw[15] = 0;
6076
6077         for (i = 0; i < 4; i++) {
6078                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6079                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6080                 I915_WRITE(PXW(i), val);
6081         }
6082
6083         /* Adjust magic regs to magic values (more experimental results) */
6084         I915_WRITE(OGW0, 0);
6085         I915_WRITE(OGW1, 0);
6086         I915_WRITE(EG0, 0x00007f00);
6087         I915_WRITE(EG1, 0x0000000e);
6088         I915_WRITE(EG2, 0x000e0000);
6089         I915_WRITE(EG3, 0x68000300);
6090         I915_WRITE(EG4, 0x42000000);
6091         I915_WRITE(EG5, 0x00140031);
6092         I915_WRITE(EG6, 0);
6093         I915_WRITE(EG7, 0);
6094
6095         for (i = 0; i < 8; i++)
6096                 I915_WRITE(PXWL(i), 0);
6097
6098         /* Enable PMON + select events */
6099         I915_WRITE(ECR, 0x80000019);
6100
6101         lcfuse = I915_READ(LCFUSE02);
6102
6103         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6104 }
6105
6106 void intel_init_gt_powersave(struct drm_device *dev)
6107 {
6108         struct drm_i915_private *dev_priv = dev->dev_private;
6109
6110         /*
6111          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6112          * requirement.
6113          */
6114         if (!i915.enable_rc6) {
6115                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6116                 intel_runtime_pm_get(dev_priv);
6117         }
6118
6119         if (IS_CHERRYVIEW(dev))
6120                 cherryview_init_gt_powersave(dev);
6121         else if (IS_VALLEYVIEW(dev))
6122                 valleyview_init_gt_powersave(dev);
6123 }
6124
6125 void intel_cleanup_gt_powersave(struct drm_device *dev)
6126 {
6127         struct drm_i915_private *dev_priv = dev->dev_private;
6128
6129         if (IS_CHERRYVIEW(dev))
6130                 return;
6131         else if (IS_VALLEYVIEW(dev))
6132                 valleyview_cleanup_gt_powersave(dev);
6133
6134         if (!i915.enable_rc6)
6135                 intel_runtime_pm_put(dev_priv);
6136 }
6137
6138 static void gen6_suspend_rps(struct drm_device *dev)
6139 {
6140         struct drm_i915_private *dev_priv = dev->dev_private;
6141
6142         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6143
6144         gen6_disable_rps_interrupts(dev);
6145 }
6146
6147 /**
6148  * intel_suspend_gt_powersave - suspend PM work and helper threads
6149  * @dev: drm device
6150  *
6151  * We don't want to disable RC6 or other features here, we just want
6152  * to make sure any work we've queued has finished and won't bother
6153  * us while we're suspended.
6154  */
6155 void intel_suspend_gt_powersave(struct drm_device *dev)
6156 {
6157         struct drm_i915_private *dev_priv = dev->dev_private;
6158
6159         if (INTEL_INFO(dev)->gen < 6)
6160                 return;
6161
6162         gen6_suspend_rps(dev);
6163
6164         /* Force GPU to min freq during suspend */
6165         gen6_rps_idle(dev_priv);
6166 }
6167
6168 void intel_disable_gt_powersave(struct drm_device *dev)
6169 {
6170         struct drm_i915_private *dev_priv = dev->dev_private;
6171
6172         if (IS_IRONLAKE_M(dev)) {
6173                 ironlake_disable_drps(dev);
6174         } else if (INTEL_INFO(dev)->gen >= 6) {
6175                 intel_suspend_gt_powersave(dev);
6176
6177                 mutex_lock(&dev_priv->rps.hw_lock);
6178                 if (INTEL_INFO(dev)->gen >= 9)
6179                         gen9_disable_rps(dev);
6180                 else if (IS_CHERRYVIEW(dev))
6181                         cherryview_disable_rps(dev);
6182                 else if (IS_VALLEYVIEW(dev))
6183                         valleyview_disable_rps(dev);
6184                 else
6185                         gen6_disable_rps(dev);
6186
6187                 dev_priv->rps.enabled = false;
6188                 mutex_unlock(&dev_priv->rps.hw_lock);
6189         }
6190 }
6191
6192 static void intel_gen6_powersave_work(struct work_struct *work)
6193 {
6194         struct drm_i915_private *dev_priv =
6195                 container_of(work, struct drm_i915_private,
6196                              rps.delayed_resume_work.work);
6197         struct drm_device *dev = dev_priv->dev;
6198
6199         mutex_lock(&dev_priv->rps.hw_lock);
6200
6201         gen6_reset_rps_interrupts(dev);
6202
6203         if (IS_CHERRYVIEW(dev)) {
6204                 cherryview_enable_rps(dev);
6205         } else if (IS_VALLEYVIEW(dev)) {
6206                 valleyview_enable_rps(dev);
6207         } else if (INTEL_INFO(dev)->gen >= 9) {
6208                 gen9_enable_rc6(dev);
6209                 gen9_enable_rps(dev);
6210                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6211                         __gen6_update_ring_freq(dev);
6212         } else if (IS_BROADWELL(dev)) {
6213                 gen8_enable_rps(dev);
6214                 __gen6_update_ring_freq(dev);
6215         } else {
6216                 gen6_enable_rps(dev);
6217                 __gen6_update_ring_freq(dev);
6218         }
6219
6220         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6221         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6222
6223         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6224         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6225
6226         dev_priv->rps.enabled = true;
6227
6228         gen6_enable_rps_interrupts(dev);
6229
6230         mutex_unlock(&dev_priv->rps.hw_lock);
6231
6232         intel_runtime_pm_put(dev_priv);
6233 }
6234
6235 void intel_enable_gt_powersave(struct drm_device *dev)
6236 {
6237         struct drm_i915_private *dev_priv = dev->dev_private;
6238
6239         /* Powersaving is controlled by the host when inside a VM */
6240         if (intel_vgpu_active(dev))
6241                 return;
6242
6243         if (IS_IRONLAKE_M(dev)) {
6244                 mutex_lock(&dev->struct_mutex);
6245                 ironlake_enable_drps(dev);
6246                 intel_init_emon(dev);
6247                 mutex_unlock(&dev->struct_mutex);
6248         } else if (INTEL_INFO(dev)->gen >= 6) {
6249                 /*
6250                  * PCU communication is slow and this doesn't need to be
6251                  * done at any specific time, so do this out of our fast path
6252                  * to make resume and init faster.
6253                  *
6254                  * We depend on the HW RC6 power context save/restore
6255                  * mechanism when entering D3 through runtime PM suspend. So
6256                  * disable RPM until RPS/RC6 is properly setup. We can only
6257                  * get here via the driver load/system resume/runtime resume
6258                  * paths, so the _noresume version is enough (and in case of
6259                  * runtime resume it's necessary).
6260                  */
6261                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6262                                            round_jiffies_up_relative(HZ)))
6263                         intel_runtime_pm_get_noresume(dev_priv);
6264         }
6265 }
6266
6267 void intel_reset_gt_powersave(struct drm_device *dev)
6268 {
6269         struct drm_i915_private *dev_priv = dev->dev_private;
6270
6271         if (INTEL_INFO(dev)->gen < 6)
6272                 return;
6273
6274         gen6_suspend_rps(dev);
6275         dev_priv->rps.enabled = false;
6276 }
6277
6278 static void ibx_init_clock_gating(struct drm_device *dev)
6279 {
6280         struct drm_i915_private *dev_priv = dev->dev_private;
6281
6282         /*
6283          * On Ibex Peak and Cougar Point, we need to disable clock
6284          * gating for the panel power sequencer or it will fail to
6285          * start up when no ports are active.
6286          */
6287         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6288 }
6289
6290 static void g4x_disable_trickle_feed(struct drm_device *dev)
6291 {
6292         struct drm_i915_private *dev_priv = dev->dev_private;
6293         enum pipe pipe;
6294
6295         for_each_pipe(dev_priv, pipe) {
6296                 I915_WRITE(DSPCNTR(pipe),
6297                            I915_READ(DSPCNTR(pipe)) |
6298                            DISPPLANE_TRICKLE_FEED_DISABLE);
6299
6300                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6301                 POSTING_READ(DSPSURF(pipe));
6302         }
6303 }
6304
6305 static void ilk_init_lp_watermarks(struct drm_device *dev)
6306 {
6307         struct drm_i915_private *dev_priv = dev->dev_private;
6308
6309         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6310         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6311         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6312
6313         /*
6314          * Don't touch WM1S_LP_EN here.
6315          * Doing so could cause underruns.
6316          */
6317 }
6318
6319 static void ironlake_init_clock_gating(struct drm_device *dev)
6320 {
6321         struct drm_i915_private *dev_priv = dev->dev_private;
6322         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6323
6324         /*
6325          * Required for FBC
6326          * WaFbcDisableDpfcClockGating:ilk
6327          */
6328         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6329                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6330                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6331
6332         I915_WRITE(PCH_3DCGDIS0,
6333                    MARIUNIT_CLOCK_GATE_DISABLE |
6334                    SVSMUNIT_CLOCK_GATE_DISABLE);
6335         I915_WRITE(PCH_3DCGDIS1,
6336                    VFMUNIT_CLOCK_GATE_DISABLE);
6337
6338         /*
6339          * According to the spec the following bits should be set in
6340          * order to enable memory self-refresh
6341          * The bit 22/21 of 0x42004
6342          * The bit 5 of 0x42020
6343          * The bit 15 of 0x45000
6344          */
6345         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6346                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6347                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6348         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6349         I915_WRITE(DISP_ARB_CTL,
6350                    (I915_READ(DISP_ARB_CTL) |
6351                     DISP_FBC_WM_DIS));
6352
6353         ilk_init_lp_watermarks(dev);
6354
6355         /*
6356          * Based on the document from hardware guys the following bits
6357          * should be set unconditionally in order to enable FBC.
6358          * The bit 22 of 0x42000
6359          * The bit 22 of 0x42004
6360          * The bit 7,8,9 of 0x42020.
6361          */
6362         if (IS_IRONLAKE_M(dev)) {
6363                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6364                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6365                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6366                            ILK_FBCQ_DIS);
6367                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6368                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6369                            ILK_DPARB_GATE);
6370         }
6371
6372         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6373
6374         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6375                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6376                    ILK_ELPIN_409_SELECT);
6377         I915_WRITE(_3D_CHICKEN2,
6378                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6379                    _3D_CHICKEN2_WM_READ_PIPELINED);
6380
6381         /* WaDisableRenderCachePipelinedFlush:ilk */
6382         I915_WRITE(CACHE_MODE_0,
6383                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6384
6385         /* WaDisable_RenderCache_OperationalFlush:ilk */
6386         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6387
6388         g4x_disable_trickle_feed(dev);
6389
6390         ibx_init_clock_gating(dev);
6391 }
6392
6393 static void cpt_init_clock_gating(struct drm_device *dev)
6394 {
6395         struct drm_i915_private *dev_priv = dev->dev_private;
6396         int pipe;
6397         uint32_t val;
6398
6399         /*
6400          * On Ibex Peak and Cougar Point, we need to disable clock
6401          * gating for the panel power sequencer or it will fail to
6402          * start up when no ports are active.
6403          */
6404         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6405                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6406                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6407         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6408                    DPLS_EDP_PPS_FIX_DIS);
6409         /* The below fixes the weird display corruption, a few pixels shifted
6410          * downward, on (only) LVDS of some HP laptops with IVY.
6411          */
6412         for_each_pipe(dev_priv, pipe) {
6413                 val = I915_READ(TRANS_CHICKEN2(pipe));
6414                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6415                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6416                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6417                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6418                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6419                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6420                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6421                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6422         }
6423         /* WADP0ClockGatingDisable */
6424         for_each_pipe(dev_priv, pipe) {
6425                 I915_WRITE(TRANS_CHICKEN1(pipe),
6426                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6427         }
6428 }
6429
6430 static void gen6_check_mch_setup(struct drm_device *dev)
6431 {
6432         struct drm_i915_private *dev_priv = dev->dev_private;
6433         uint32_t tmp;
6434
6435         tmp = I915_READ(MCH_SSKPD);
6436         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6437                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6438                               tmp);
6439 }
6440
6441 static void gen6_init_clock_gating(struct drm_device *dev)
6442 {
6443         struct drm_i915_private *dev_priv = dev->dev_private;
6444         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6445
6446         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6447
6448         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6449                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6450                    ILK_ELPIN_409_SELECT);
6451
6452         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6453         I915_WRITE(_3D_CHICKEN,
6454                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6455
6456         /* WaDisable_RenderCache_OperationalFlush:snb */
6457         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6458
6459         /*
6460          * BSpec recoomends 8x4 when MSAA is used,
6461          * however in practice 16x4 seems fastest.
6462          *
6463          * Note that PS/WM thread counts depend on the WIZ hashing
6464          * disable bit, which we don't touch here, but it's good
6465          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6466          */
6467         I915_WRITE(GEN6_GT_MODE,
6468                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6469
6470         ilk_init_lp_watermarks(dev);
6471
6472         I915_WRITE(CACHE_MODE_0,
6473                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6474
6475         I915_WRITE(GEN6_UCGCTL1,
6476                    I915_READ(GEN6_UCGCTL1) |
6477                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6478                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6479
6480         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6481          * gating disable must be set.  Failure to set it results in
6482          * flickering pixels due to Z write ordering failures after
6483          * some amount of runtime in the Mesa "fire" demo, and Unigine
6484          * Sanctuary and Tropics, and apparently anything else with
6485          * alpha test or pixel discard.
6486          *
6487          * According to the spec, bit 11 (RCCUNIT) must also be set,
6488          * but we didn't debug actual testcases to find it out.
6489          *
6490          * WaDisableRCCUnitClockGating:snb
6491          * WaDisableRCPBUnitClockGating:snb
6492          */
6493         I915_WRITE(GEN6_UCGCTL2,
6494                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6495                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6496
6497         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6498         I915_WRITE(_3D_CHICKEN3,
6499                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6500
6501         /*
6502          * Bspec says:
6503          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6504          * 3DSTATE_SF number of SF output attributes is more than 16."
6505          */
6506         I915_WRITE(_3D_CHICKEN3,
6507                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6508
6509         /*
6510          * According to the spec the following bits should be
6511          * set in order to enable memory self-refresh and fbc:
6512          * The bit21 and bit22 of 0x42000
6513          * The bit21 and bit22 of 0x42004
6514          * The bit5 and bit7 of 0x42020
6515          * The bit14 of 0x70180
6516          * The bit14 of 0x71180
6517          *
6518          * WaFbcAsynchFlipDisableFbcQueue:snb
6519          */
6520         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6521                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6522                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6523         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6524                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6525                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6526         I915_WRITE(ILK_DSPCLK_GATE_D,
6527                    I915_READ(ILK_DSPCLK_GATE_D) |
6528                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6529                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6530
6531         g4x_disable_trickle_feed(dev);
6532
6533         cpt_init_clock_gating(dev);
6534
6535         gen6_check_mch_setup(dev);
6536 }
6537
6538 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6539 {
6540         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6541
6542         /*
6543          * WaVSThreadDispatchOverride:ivb,vlv
6544          *
6545          * This actually overrides the dispatch
6546          * mode for all thread types.
6547          */
6548         reg &= ~GEN7_FF_SCHED_MASK;
6549         reg |= GEN7_FF_TS_SCHED_HW;
6550         reg |= GEN7_FF_VS_SCHED_HW;
6551         reg |= GEN7_FF_DS_SCHED_HW;
6552
6553         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6554 }
6555
6556 static void lpt_init_clock_gating(struct drm_device *dev)
6557 {
6558         struct drm_i915_private *dev_priv = dev->dev_private;
6559
6560         /*
6561          * TODO: this bit should only be enabled when really needed, then
6562          * disabled when not needed anymore in order to save power.
6563          */
6564         if (HAS_PCH_LPT_LP(dev))
6565                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6566                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6567                            PCH_LP_PARTITION_LEVEL_DISABLE);
6568
6569         /* WADPOClockGatingDisable:hsw */
6570         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6571                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6572                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6573 }
6574
6575 static void lpt_suspend_hw(struct drm_device *dev)
6576 {
6577         struct drm_i915_private *dev_priv = dev->dev_private;
6578
6579         if (HAS_PCH_LPT_LP(dev)) {
6580                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6581
6582                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6583                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6584         }
6585 }
6586
6587 static void broadwell_init_clock_gating(struct drm_device *dev)
6588 {
6589         struct drm_i915_private *dev_priv = dev->dev_private;
6590         enum pipe pipe;
6591         uint32_t misccpctl;
6592
6593         ilk_init_lp_watermarks(dev);
6594
6595         /* WaSwitchSolVfFArbitrationPriority:bdw */
6596         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6597
6598         /* WaPsrDPAMaskVBlankInSRD:bdw */
6599         I915_WRITE(CHICKEN_PAR1_1,
6600                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6601
6602         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6603         for_each_pipe(dev_priv, pipe) {
6604                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6605                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6606                            BDW_DPRS_MASK_VBLANK_SRD);
6607         }
6608
6609         /* WaVSRefCountFullforceMissDisable:bdw */
6610         /* WaDSRefCountFullforceMissDisable:bdw */
6611         I915_WRITE(GEN7_FF_THREAD_MODE,
6612                    I915_READ(GEN7_FF_THREAD_MODE) &
6613                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6614
6615         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6616                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6617
6618         /* WaDisableSDEUnitClockGating:bdw */
6619         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6620                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6621
6622         /*
6623          * WaProgramL3SqcReg1Default:bdw
6624          * WaTempDisableDOPClkGating:bdw
6625          */
6626         misccpctl = I915_READ(GEN7_MISCCPCTL);
6627         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6628         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6629         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6630
6631         /*
6632          * WaGttCachingOffByDefault:bdw
6633          * GTT cache may not work with big pages, so if those
6634          * are ever enabled GTT cache may need to be disabled.
6635          */
6636         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6637
6638         lpt_init_clock_gating(dev);
6639 }
6640
6641 static void haswell_init_clock_gating(struct drm_device *dev)
6642 {
6643         struct drm_i915_private *dev_priv = dev->dev_private;
6644
6645         ilk_init_lp_watermarks(dev);
6646
6647         /* L3 caching of data atomics doesn't work -- disable it. */
6648         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6649         I915_WRITE(HSW_ROW_CHICKEN3,
6650                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6651
6652         /* This is required by WaCatErrorRejectionIssue:hsw */
6653         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6654                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6655                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6656
6657         /* WaVSRefCountFullforceMissDisable:hsw */
6658         I915_WRITE(GEN7_FF_THREAD_MODE,
6659                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6660
6661         /* WaDisable_RenderCache_OperationalFlush:hsw */
6662         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6663
6664         /* enable HiZ Raw Stall Optimization */
6665         I915_WRITE(CACHE_MODE_0_GEN7,
6666                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6667
6668         /* WaDisable4x2SubspanOptimization:hsw */
6669         I915_WRITE(CACHE_MODE_1,
6670                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6671
6672         /*
6673          * BSpec recommends 8x4 when MSAA is used,
6674          * however in practice 16x4 seems fastest.
6675          *
6676          * Note that PS/WM thread counts depend on the WIZ hashing
6677          * disable bit, which we don't touch here, but it's good
6678          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6679          */
6680         I915_WRITE(GEN7_GT_MODE,
6681                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6682
6683         /* WaSampleCChickenBitEnable:hsw */
6684         I915_WRITE(HALF_SLICE_CHICKEN3,
6685                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6686
6687         /* WaSwitchSolVfFArbitrationPriority:hsw */
6688         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6689
6690         /* WaRsPkgCStateDisplayPMReq:hsw */
6691         I915_WRITE(CHICKEN_PAR1_1,
6692                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6693
6694         lpt_init_clock_gating(dev);
6695 }
6696
6697 static void ivybridge_init_clock_gating(struct drm_device *dev)
6698 {
6699         struct drm_i915_private *dev_priv = dev->dev_private;
6700         uint32_t snpcr;
6701
6702         ilk_init_lp_watermarks(dev);
6703
6704         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6705
6706         /* WaDisableEarlyCull:ivb */
6707         I915_WRITE(_3D_CHICKEN3,
6708                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6709
6710         /* WaDisableBackToBackFlipFix:ivb */
6711         I915_WRITE(IVB_CHICKEN3,
6712                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6713                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6714
6715         /* WaDisablePSDDualDispatchEnable:ivb */
6716         if (IS_IVB_GT1(dev))
6717                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6718                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6719
6720         /* WaDisable_RenderCache_OperationalFlush:ivb */
6721         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6722
6723         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6724         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6725                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6726
6727         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6728         I915_WRITE(GEN7_L3CNTLREG1,
6729                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6730         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6731                    GEN7_WA_L3_CHICKEN_MODE);
6732         if (IS_IVB_GT1(dev))
6733                 I915_WRITE(GEN7_ROW_CHICKEN2,
6734                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6735         else {
6736                 /* must write both registers */
6737                 I915_WRITE(GEN7_ROW_CHICKEN2,
6738                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6739                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6740                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6741         }
6742
6743         /* WaForceL3Serialization:ivb */
6744         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6745                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6746
6747         /*
6748          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6749          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6750          */
6751         I915_WRITE(GEN6_UCGCTL2,
6752                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6753
6754         /* This is required by WaCatErrorRejectionIssue:ivb */
6755         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6756                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6757                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6758
6759         g4x_disable_trickle_feed(dev);
6760
6761         gen7_setup_fixed_func_scheduler(dev_priv);
6762
6763         if (0) { /* causes HiZ corruption on ivb:gt1 */
6764                 /* enable HiZ Raw Stall Optimization */
6765                 I915_WRITE(CACHE_MODE_0_GEN7,
6766                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6767         }
6768
6769         /* WaDisable4x2SubspanOptimization:ivb */
6770         I915_WRITE(CACHE_MODE_1,
6771                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6772
6773         /*
6774          * BSpec recommends 8x4 when MSAA is used,
6775          * however in practice 16x4 seems fastest.
6776          *
6777          * Note that PS/WM thread counts depend on the WIZ hashing
6778          * disable bit, which we don't touch here, but it's good
6779          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6780          */
6781         I915_WRITE(GEN7_GT_MODE,
6782                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6783
6784         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6785         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6786         snpcr |= GEN6_MBC_SNPCR_MED;
6787         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6788
6789         if (!HAS_PCH_NOP(dev))
6790                 cpt_init_clock_gating(dev);
6791
6792         gen6_check_mch_setup(dev);
6793 }
6794
6795 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6796 {
6797         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6798
6799         /*
6800          * Disable trickle feed and enable pnd deadline calculation
6801          */
6802         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6803         I915_WRITE(CBR1_VLV, 0);
6804 }
6805
6806 static void valleyview_init_clock_gating(struct drm_device *dev)
6807 {
6808         struct drm_i915_private *dev_priv = dev->dev_private;
6809
6810         vlv_init_display_clock_gating(dev_priv);
6811
6812         /* WaDisableEarlyCull:vlv */
6813         I915_WRITE(_3D_CHICKEN3,
6814                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6815
6816         /* WaDisableBackToBackFlipFix:vlv */
6817         I915_WRITE(IVB_CHICKEN3,
6818                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6819                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6820
6821         /* WaPsdDispatchEnable:vlv */
6822         /* WaDisablePSDDualDispatchEnable:vlv */
6823         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6824                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6825                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6826
6827         /* WaDisable_RenderCache_OperationalFlush:vlv */
6828         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6829
6830         /* WaForceL3Serialization:vlv */
6831         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6832                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6833
6834         /* WaDisableDopClockGating:vlv */
6835         I915_WRITE(GEN7_ROW_CHICKEN2,
6836                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6837
6838         /* This is required by WaCatErrorRejectionIssue:vlv */
6839         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6840                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6841                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6842
6843         gen7_setup_fixed_func_scheduler(dev_priv);
6844
6845         /*
6846          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6847          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6848          */
6849         I915_WRITE(GEN6_UCGCTL2,
6850                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6851
6852         /* WaDisableL3Bank2xClockGate:vlv
6853          * Disabling L3 clock gating- MMIO 940c[25] = 1
6854          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6855         I915_WRITE(GEN7_UCGCTL4,
6856                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6857
6858         /*
6859          * BSpec says this must be set, even though
6860          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6861          */
6862         I915_WRITE(CACHE_MODE_1,
6863                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6864
6865         /*
6866          * BSpec recommends 8x4 when MSAA is used,
6867          * however in practice 16x4 seems fastest.
6868          *
6869          * Note that PS/WM thread counts depend on the WIZ hashing
6870          * disable bit, which we don't touch here, but it's good
6871          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6872          */
6873         I915_WRITE(GEN7_GT_MODE,
6874                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6875
6876         /*
6877          * WaIncreaseL3CreditsForVLVB0:vlv
6878          * This is the hardware default actually.
6879          */
6880         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6881
6882         /*
6883          * WaDisableVLVClockGating_VBIIssue:vlv
6884          * Disable clock gating on th GCFG unit to prevent a delay
6885          * in the reporting of vblank events.
6886          */
6887         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6888 }
6889
6890 static void cherryview_init_clock_gating(struct drm_device *dev)
6891 {
6892         struct drm_i915_private *dev_priv = dev->dev_private;
6893
6894         vlv_init_display_clock_gating(dev_priv);
6895
6896         /* WaVSRefCountFullforceMissDisable:chv */
6897         /* WaDSRefCountFullforceMissDisable:chv */
6898         I915_WRITE(GEN7_FF_THREAD_MODE,
6899                    I915_READ(GEN7_FF_THREAD_MODE) &
6900                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6901
6902         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6903         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6904                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6905
6906         /* WaDisableCSUnitClockGating:chv */
6907         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6908                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6909
6910         /* WaDisableSDEUnitClockGating:chv */
6911         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6912                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6913
6914         /*
6915          * GTT cache may not work with big pages, so if those
6916          * are ever enabled GTT cache may need to be disabled.
6917          */
6918         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6919 }
6920
6921 static void g4x_init_clock_gating(struct drm_device *dev)
6922 {
6923         struct drm_i915_private *dev_priv = dev->dev_private;
6924         uint32_t dspclk_gate;
6925
6926         I915_WRITE(RENCLK_GATE_D1, 0);
6927         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6928                    GS_UNIT_CLOCK_GATE_DISABLE |
6929                    CL_UNIT_CLOCK_GATE_DISABLE);
6930         I915_WRITE(RAMCLK_GATE_D, 0);
6931         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6932                 OVRUNIT_CLOCK_GATE_DISABLE |
6933                 OVCUNIT_CLOCK_GATE_DISABLE;
6934         if (IS_GM45(dev))
6935                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6936         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6937
6938         /* WaDisableRenderCachePipelinedFlush */
6939         I915_WRITE(CACHE_MODE_0,
6940                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6941
6942         /* WaDisable_RenderCache_OperationalFlush:g4x */
6943         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6944
6945         g4x_disable_trickle_feed(dev);
6946 }
6947
6948 static void crestline_init_clock_gating(struct drm_device *dev)
6949 {
6950         struct drm_i915_private *dev_priv = dev->dev_private;
6951
6952         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6953         I915_WRITE(RENCLK_GATE_D2, 0);
6954         I915_WRITE(DSPCLK_GATE_D, 0);
6955         I915_WRITE(RAMCLK_GATE_D, 0);
6956         I915_WRITE16(DEUC, 0);
6957         I915_WRITE(MI_ARB_STATE,
6958                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6959
6960         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6961         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6962 }
6963
6964 static void broadwater_init_clock_gating(struct drm_device *dev)
6965 {
6966         struct drm_i915_private *dev_priv = dev->dev_private;
6967
6968         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6969                    I965_RCC_CLOCK_GATE_DISABLE |
6970                    I965_RCPB_CLOCK_GATE_DISABLE |
6971                    I965_ISC_CLOCK_GATE_DISABLE |
6972                    I965_FBC_CLOCK_GATE_DISABLE);
6973         I915_WRITE(RENCLK_GATE_D2, 0);
6974         I915_WRITE(MI_ARB_STATE,
6975                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6976
6977         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6978         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6979 }
6980
6981 static void gen3_init_clock_gating(struct drm_device *dev)
6982 {
6983         struct drm_i915_private *dev_priv = dev->dev_private;
6984         u32 dstate = I915_READ(D_STATE);
6985
6986         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6987                 DSTATE_DOT_CLOCK_GATING;
6988         I915_WRITE(D_STATE, dstate);
6989
6990         if (IS_PINEVIEW(dev))
6991                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6992
6993         /* IIR "flip pending" means done if this bit is set */
6994         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6995
6996         /* interrupts should cause a wake up from C3 */
6997         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6998
6999         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7000         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7001
7002         I915_WRITE(MI_ARB_STATE,
7003                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7004 }
7005
7006 static void i85x_init_clock_gating(struct drm_device *dev)
7007 {
7008         struct drm_i915_private *dev_priv = dev->dev_private;
7009
7010         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7011
7012         /* interrupts should cause a wake up from C3 */
7013         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7014                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7015
7016         I915_WRITE(MEM_MODE,
7017                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7018 }
7019
7020 static void i830_init_clock_gating(struct drm_device *dev)
7021 {
7022         struct drm_i915_private *dev_priv = dev->dev_private;
7023
7024         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7025
7026         I915_WRITE(MEM_MODE,
7027                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7028                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7029 }
7030
7031 void intel_init_clock_gating(struct drm_device *dev)
7032 {
7033         struct drm_i915_private *dev_priv = dev->dev_private;
7034
7035         if (dev_priv->display.init_clock_gating)
7036                 dev_priv->display.init_clock_gating(dev);
7037 }
7038
7039 void intel_suspend_hw(struct drm_device *dev)
7040 {
7041         if (HAS_PCH_LPT(dev))
7042                 lpt_suspend_hw(dev);
7043 }
7044
7045 /* Set up chip specific power management-related functions */
7046 void intel_init_pm(struct drm_device *dev)
7047 {
7048         struct drm_i915_private *dev_priv = dev->dev_private;
7049
7050         intel_fbc_init(dev_priv);
7051
7052         /* For cxsr */
7053         if (IS_PINEVIEW(dev))
7054                 i915_pineview_get_mem_freq(dev);
7055         else if (IS_GEN5(dev))
7056                 i915_ironlake_get_mem_freq(dev);
7057
7058         /* For FIFO watermark updates */
7059         if (INTEL_INFO(dev)->gen >= 9) {
7060                 skl_setup_wm_latency(dev);
7061
7062                 if (IS_BROXTON(dev))
7063                         dev_priv->display.init_clock_gating =
7064                                 bxt_init_clock_gating;
7065                 dev_priv->display.update_wm = skl_update_wm;
7066         } else if (HAS_PCH_SPLIT(dev)) {
7067                 ilk_setup_wm_latency(dev);
7068
7069                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7070                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7071                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7072                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7073                         dev_priv->display.update_wm = ilk_update_wm;
7074                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7075                         dev_priv->display.program_watermarks = ilk_program_watermarks;
7076                 } else {
7077                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7078                                       "Disable CxSR\n");
7079                 }
7080
7081                 if (IS_GEN5(dev))
7082                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7083                 else if (IS_GEN6(dev))
7084                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7085                 else if (IS_IVYBRIDGE(dev))
7086                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7087                 else if (IS_HASWELL(dev))
7088                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7089                 else if (INTEL_INFO(dev)->gen == 8)
7090                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7091         } else if (IS_CHERRYVIEW(dev)) {
7092                 vlv_setup_wm_latency(dev);
7093
7094                 dev_priv->display.update_wm = vlv_update_wm;
7095                 dev_priv->display.init_clock_gating =
7096                         cherryview_init_clock_gating;
7097         } else if (IS_VALLEYVIEW(dev)) {
7098                 vlv_setup_wm_latency(dev);
7099
7100                 dev_priv->display.update_wm = vlv_update_wm;
7101                 dev_priv->display.init_clock_gating =
7102                         valleyview_init_clock_gating;
7103         } else if (IS_PINEVIEW(dev)) {
7104                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7105                                             dev_priv->is_ddr3,
7106                                             dev_priv->fsb_freq,
7107                                             dev_priv->mem_freq)) {
7108                         DRM_INFO("failed to find known CxSR latency "
7109                                  "(found ddr%s fsb freq %d, mem freq %d), "
7110                                  "disabling CxSR\n",
7111                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7112                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7113                         /* Disable CxSR and never update its watermark again */
7114                         intel_set_memory_cxsr(dev_priv, false);
7115                         dev_priv->display.update_wm = NULL;
7116                 } else
7117                         dev_priv->display.update_wm = pineview_update_wm;
7118                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7119         } else if (IS_G4X(dev)) {
7120                 dev_priv->display.update_wm = g4x_update_wm;
7121                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7122         } else if (IS_GEN4(dev)) {
7123                 dev_priv->display.update_wm = i965_update_wm;
7124                 if (IS_CRESTLINE(dev))
7125                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7126                 else if (IS_BROADWATER(dev))
7127                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7128         } else if (IS_GEN3(dev)) {
7129                 dev_priv->display.update_wm = i9xx_update_wm;
7130                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7131                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7132         } else if (IS_GEN2(dev)) {
7133                 if (INTEL_INFO(dev)->num_pipes == 1) {
7134                         dev_priv->display.update_wm = i845_update_wm;
7135                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7136                 } else {
7137                         dev_priv->display.update_wm = i9xx_update_wm;
7138                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7139                 }
7140
7141                 if (IS_I85X(dev) || IS_I865G(dev))
7142                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7143                 else
7144                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7145         } else {
7146                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7147         }
7148 }
7149
7150 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7151 {
7152         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7153
7154         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7155                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7156                 return -EAGAIN;
7157         }
7158
7159         I915_WRITE(GEN6_PCODE_DATA, *val);
7160         I915_WRITE(GEN6_PCODE_DATA1, 0);
7161         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7162
7163         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7164                      500)) {
7165                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7166                 return -ETIMEDOUT;
7167         }
7168
7169         *val = I915_READ(GEN6_PCODE_DATA);
7170         I915_WRITE(GEN6_PCODE_DATA, 0);
7171
7172         return 0;
7173 }
7174
7175 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7176 {
7177         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7178
7179         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7180                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7181                 return -EAGAIN;
7182         }
7183
7184         I915_WRITE(GEN6_PCODE_DATA, val);
7185         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7186
7187         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7188                      500)) {
7189                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7190                 return -ETIMEDOUT;
7191         }
7192
7193         I915_WRITE(GEN6_PCODE_DATA, 0);
7194
7195         return 0;
7196 }
7197
7198 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7199 {
7200         switch (czclk_freq) {
7201         case 200:
7202                 return 10;
7203         case 267:
7204                 return 12;
7205         case 320:
7206         case 333:
7207                 return 16;
7208         case 400:
7209                 return 20;
7210         default:
7211                 return -1;
7212         }
7213 }
7214
7215 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7216 {
7217         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7218
7219         div = vlv_gpu_freq_div(czclk_freq);
7220         if (div < 0)
7221                 return div;
7222
7223         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7224 }
7225
7226 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7227 {
7228         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7229
7230         mul = vlv_gpu_freq_div(czclk_freq);
7231         if (mul < 0)
7232                 return mul;
7233
7234         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7235 }
7236
7237 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7238 {
7239         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7240
7241         div = vlv_gpu_freq_div(czclk_freq);
7242         if (div < 0)
7243                 return div;
7244         div /= 2;
7245
7246         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7247 }
7248
7249 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7250 {
7251         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7252
7253         mul = vlv_gpu_freq_div(czclk_freq);
7254         if (mul < 0)
7255                 return mul;
7256         mul /= 2;
7257
7258         /* CHV needs even values */
7259         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7260 }
7261
7262 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7263 {
7264         if (IS_GEN9(dev_priv->dev))
7265                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7266                                          GEN9_FREQ_SCALER);
7267         else if (IS_CHERRYVIEW(dev_priv->dev))
7268                 return chv_gpu_freq(dev_priv, val);
7269         else if (IS_VALLEYVIEW(dev_priv->dev))
7270                 return byt_gpu_freq(dev_priv, val);
7271         else
7272                 return val * GT_FREQUENCY_MULTIPLIER;
7273 }
7274
7275 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7276 {
7277         if (IS_GEN9(dev_priv->dev))
7278                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7279                                          GT_FREQUENCY_MULTIPLIER);
7280         else if (IS_CHERRYVIEW(dev_priv->dev))
7281                 return chv_freq_opcode(dev_priv, val);
7282         else if (IS_VALLEYVIEW(dev_priv->dev))
7283                 return byt_freq_opcode(dev_priv, val);
7284         else
7285                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7286 }
7287
7288 struct request_boost {
7289         struct work_struct work;
7290         struct drm_i915_gem_request *req;
7291 };
7292
7293 static void __intel_rps_boost_work(struct work_struct *work)
7294 {
7295         struct request_boost *boost = container_of(work, struct request_boost, work);
7296         struct drm_i915_gem_request *req = boost->req;
7297
7298         if (!i915_gem_request_completed(req, true))
7299                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7300                                req->emitted_jiffies);
7301
7302         i915_gem_request_unreference__unlocked(req);
7303         kfree(boost);
7304 }
7305
7306 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7307                                        struct drm_i915_gem_request *req)
7308 {
7309         struct request_boost *boost;
7310
7311         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7312                 return;
7313
7314         if (i915_gem_request_completed(req, true))
7315                 return;
7316
7317         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7318         if (boost == NULL)
7319                 return;
7320
7321         i915_gem_request_reference(req);
7322         boost->req = req;
7323
7324         INIT_WORK(&boost->work, __intel_rps_boost_work);
7325         queue_work(to_i915(dev)->wq, &boost->work);
7326 }
7327
7328 void intel_pm_setup(struct drm_device *dev)
7329 {
7330         struct drm_i915_private *dev_priv = dev->dev_private;
7331
7332         mutex_init(&dev_priv->rps.hw_lock);
7333         spin_lock_init(&dev_priv->rps.client_lock);
7334
7335         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7336                           intel_gen6_powersave_work);
7337         INIT_LIST_HEAD(&dev_priv->rps.clients);
7338         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7339         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7340
7341         dev_priv->pm.suspended = false;
7342         atomic_set(&dev_priv->pm.wakeref_count, 0);
7343         atomic_set(&dev_priv->pm.atomic_seq, 0);
7344 }