2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
69 static void i8xx_disable_fbc(struct drm_device *dev)
71 struct drm_i915_private *dev_priv = dev->dev_private;
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
88 DRM_DEBUG_KMS("disabled FBC\n");
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->primary->fb;
96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
106 /* FBC_CTL wants 32B or 64B units */
108 cfb_pitch = (cfb_pitch / 32) - 1;
110 cfb_pitch = (cfb_pitch / 64) - 1;
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
140 static bool i8xx_fbc_enabled(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
147 static void g4x_enable_fbc(struct drm_crtc *crtc)
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_framebuffer *fb = crtc->primary->fb;
152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
171 static void g4x_disable_fbc(struct drm_device *dev)
173 struct drm_i915_private *dev_priv = dev->dev_private;
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
182 DRM_DEBUG_KMS("disabled FBC\n");
186 static bool g4x_fbc_enabled(struct drm_device *dev)
188 struct drm_i915_private *dev_priv = dev->dev_private;
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
193 static void sandybridge_blit_fbc_update(struct drm_device *dev)
195 struct drm_i915_private *dev_priv = dev->dev_private;
198 /* Make sure blitter notifies FBC of writes */
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
218 static void ironlake_enable_fbc(struct drm_crtc *crtc)
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
222 struct drm_framebuffer *fb = crtc->primary->fb;
223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
229 dev_priv->fbc.threshold++;
231 switch (dev_priv->fbc.threshold) {
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
245 dpfc_ctl |= obj->fence_reg;
247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
262 static void ironlake_disable_fbc(struct drm_device *dev)
264 struct drm_i915_private *dev_priv = dev->dev_private;
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
273 DRM_DEBUG_KMS("disabled FBC\n");
277 static bool ironlake_fbc_enabled(struct drm_device *dev)
279 struct drm_i915_private *dev_priv = dev->dev_private;
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
284 static void gen7_enable_fbc(struct drm_crtc *crtc)
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 struct drm_framebuffer *fb = crtc->primary->fb;
289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
295 dev_priv->fbc.threshold++;
297 switch (dev_priv->fbc.threshold) {
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
312 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
314 if (IS_IVYBRIDGE(dev)) {
315 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
316 I915_WRITE(ILK_DISPLAY_CHICKEN1,
317 I915_READ(ILK_DISPLAY_CHICKEN1) |
320 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
321 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
322 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
326 I915_WRITE(SNB_DPFC_CTL_SA,
327 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
328 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
330 sandybridge_blit_fbc_update(dev);
332 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
335 bool intel_fbc_enabled(struct drm_device *dev)
337 struct drm_i915_private *dev_priv = dev->dev_private;
339 if (!dev_priv->display.fbc_enabled)
342 return dev_priv->display.fbc_enabled(dev);
345 static void intel_fbc_work_fn(struct work_struct *__work)
347 struct intel_fbc_work *work =
348 container_of(to_delayed_work(__work),
349 struct intel_fbc_work, work);
350 struct drm_device *dev = work->crtc->dev;
351 struct drm_i915_private *dev_priv = dev->dev_private;
353 mutex_lock(&dev->struct_mutex);
354 if (work == dev_priv->fbc.fbc_work) {
355 /* Double check that we haven't switched fb without cancelling
358 if (work->crtc->primary->fb == work->fb) {
359 dev_priv->display.enable_fbc(work->crtc);
361 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
362 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
363 dev_priv->fbc.y = work->crtc->y;
366 dev_priv->fbc.fbc_work = NULL;
368 mutex_unlock(&dev->struct_mutex);
373 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
375 if (dev_priv->fbc.fbc_work == NULL)
378 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
380 /* Synchronisation is provided by struct_mutex and checking of
381 * dev_priv->fbc.fbc_work, so we can perform the cancellation
382 * entirely asynchronously.
384 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
385 /* tasklet was killed before being run, clean up */
386 kfree(dev_priv->fbc.fbc_work);
388 /* Mark the work as no longer wanted so that if it does
389 * wake-up (because the work was already running and waiting
390 * for our mutex), it will discover that is no longer
393 dev_priv->fbc.fbc_work = NULL;
396 static void intel_enable_fbc(struct drm_crtc *crtc)
398 struct intel_fbc_work *work;
399 struct drm_device *dev = crtc->dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
402 if (!dev_priv->display.enable_fbc)
405 intel_cancel_fbc_work(dev_priv);
407 work = kzalloc(sizeof(*work), GFP_KERNEL);
409 DRM_ERROR("Failed to allocate FBC work structure\n");
410 dev_priv->display.enable_fbc(crtc);
415 work->fb = crtc->primary->fb;
416 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
418 dev_priv->fbc.fbc_work = work;
420 /* Delay the actual enabling to let pageflipping cease and the
421 * display to settle before starting the compression. Note that
422 * this delay also serves a second purpose: it allows for a
423 * vblank to pass after disabling the FBC before we attempt
424 * to modify the control registers.
426 * A more complicated solution would involve tracking vblanks
427 * following the termination of the page-flipping sequence
428 * and indeed performing the enable as a co-routine and not
429 * waiting synchronously upon the vblank.
431 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
433 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
436 void intel_disable_fbc(struct drm_device *dev)
438 struct drm_i915_private *dev_priv = dev->dev_private;
440 intel_cancel_fbc_work(dev_priv);
442 if (!dev_priv->display.disable_fbc)
445 dev_priv->display.disable_fbc(dev);
446 dev_priv->fbc.plane = -1;
449 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
450 enum no_fbc_reason reason)
452 if (dev_priv->fbc.no_fbc_reason == reason)
455 dev_priv->fbc.no_fbc_reason = reason;
460 * intel_update_fbc - enable/disable FBC as needed
461 * @dev: the drm_device
463 * Set up the framebuffer compression hardware at mode set time. We
464 * enable it if possible:
465 * - plane A only (on pre-965)
466 * - no pixel mulitply/line duplication
467 * - no alpha buffer discard
469 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
471 * We can't assume that any compression will take place (worst case),
472 * so the compressed buffer has to be the same size as the uncompressed
473 * one. It also must reside (along with the line length buffer) in
476 * We need to enable/disable FBC on a global basis.
478 void intel_update_fbc(struct drm_device *dev)
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct drm_crtc *crtc = NULL, *tmp_crtc;
482 struct intel_crtc *intel_crtc;
483 struct drm_framebuffer *fb;
484 struct drm_i915_gem_object *obj;
485 const struct drm_display_mode *adjusted_mode;
486 unsigned int max_width, max_height;
489 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
493 if (!i915.powersave) {
494 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
495 DRM_DEBUG_KMS("fbc disabled per module param\n");
500 * If FBC is already on, we just have to verify that we can
501 * keep it that way...
502 * Need to disable if:
503 * - more than one pipe is active
504 * - changing FBC params (stride, fence, mode)
505 * - new fb is too large to fit in compressed buffer
506 * - going to an unsupported config (interlace, pixel multiply, etc.)
508 for_each_crtc(dev, tmp_crtc) {
509 if (intel_crtc_active(tmp_crtc) &&
510 to_intel_crtc(tmp_crtc)->primary_enabled) {
512 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
513 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
520 if (!crtc || crtc->primary->fb == NULL) {
521 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
522 DRM_DEBUG_KMS("no output, disabling\n");
526 intel_crtc = to_intel_crtc(crtc);
527 fb = crtc->primary->fb;
528 obj = intel_fb_obj(fb);
529 adjusted_mode = &intel_crtc->config.adjusted_mode;
531 if (i915.enable_fbc < 0) {
532 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
533 DRM_DEBUG_KMS("disabled per chip default\n");
536 if (!i915.enable_fbc) {
537 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
538 DRM_DEBUG_KMS("fbc disabled per module param\n");
541 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
542 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
543 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
544 DRM_DEBUG_KMS("mode incompatible with compression, "
549 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
552 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
559 if (intel_crtc->config.pipe_src_w > max_width ||
560 intel_crtc->config.pipe_src_h > max_height) {
561 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
562 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
565 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
566 intel_crtc->plane != PLANE_A) {
567 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
568 DRM_DEBUG_KMS("plane not A, disabling compression\n");
572 /* The use of a CPU fence is mandatory in order to detect writes
573 * by the CPU to the scanout and trigger updates to the FBC.
575 if (obj->tiling_mode != I915_TILING_X ||
576 obj->fence_reg == I915_FENCE_REG_NONE) {
577 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
578 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
582 /* If the kernel debugger is active, always disable compression */
586 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
587 drm_format_plane_cpp(fb->pixel_format, 0))) {
588 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
589 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
593 /* If the scanout has not changed, don't modify the FBC settings.
594 * Note that we make the fundamental assumption that the fb->obj
595 * cannot be unpinned (and have its GTT offset and fence revoked)
596 * without first being decoupled from the scanout and FBC disabled.
598 if (dev_priv->fbc.plane == intel_crtc->plane &&
599 dev_priv->fbc.fb_id == fb->base.id &&
600 dev_priv->fbc.y == crtc->y)
603 if (intel_fbc_enabled(dev)) {
604 /* We update FBC along two paths, after changing fb/crtc
605 * configuration (modeswitching) and after page-flipping
606 * finishes. For the latter, we know that not only did
607 * we disable the FBC at the start of the page-flip
608 * sequence, but also more than one vblank has passed.
610 * For the former case of modeswitching, it is possible
611 * to switch between two FBC valid configurations
612 * instantaneously so we do need to disable the FBC
613 * before we can modify its control registers. We also
614 * have to wait for the next vblank for that to take
615 * effect. However, since we delay enabling FBC we can
616 * assume that a vblank has passed since disabling and
617 * that we can safely alter the registers in the deferred
620 * In the scenario that we go from a valid to invalid
621 * and then back to valid FBC configuration we have
622 * no strict enforcement that a vblank occurred since
623 * disabling the FBC. However, along all current pipe
624 * disabling paths we do need to wait for a vblank at
625 * some point. And we wait before enabling FBC anyway.
627 DRM_DEBUG_KMS("disabling active FBC for update\n");
628 intel_disable_fbc(dev);
631 intel_enable_fbc(crtc);
632 dev_priv->fbc.no_fbc_reason = FBC_OK;
636 /* Multiple disables should be harmless */
637 if (intel_fbc_enabled(dev)) {
638 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
639 intel_disable_fbc(dev);
641 i915_gem_stolen_cleanup_compression(dev);
644 static void i915_pineview_get_mem_freq(struct drm_device *dev)
646 struct drm_i915_private *dev_priv = dev->dev_private;
649 tmp = I915_READ(CLKCFG);
651 switch (tmp & CLKCFG_FSB_MASK) {
653 dev_priv->fsb_freq = 533; /* 133*4 */
656 dev_priv->fsb_freq = 800; /* 200*4 */
659 dev_priv->fsb_freq = 667; /* 167*4 */
662 dev_priv->fsb_freq = 400; /* 100*4 */
666 switch (tmp & CLKCFG_MEM_MASK) {
668 dev_priv->mem_freq = 533;
671 dev_priv->mem_freq = 667;
674 dev_priv->mem_freq = 800;
678 /* detect pineview DDR3 setting */
679 tmp = I915_READ(CSHRDDR3CTL);
680 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
683 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
685 struct drm_i915_private *dev_priv = dev->dev_private;
688 ddrpll = I915_READ16(DDRMPLL1);
689 csipll = I915_READ16(CSIPLL0);
691 switch (ddrpll & 0xff) {
693 dev_priv->mem_freq = 800;
696 dev_priv->mem_freq = 1066;
699 dev_priv->mem_freq = 1333;
702 dev_priv->mem_freq = 1600;
705 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
707 dev_priv->mem_freq = 0;
711 dev_priv->ips.r_t = dev_priv->mem_freq;
713 switch (csipll & 0x3ff) {
715 dev_priv->fsb_freq = 3200;
718 dev_priv->fsb_freq = 3733;
721 dev_priv->fsb_freq = 4266;
724 dev_priv->fsb_freq = 4800;
727 dev_priv->fsb_freq = 5333;
730 dev_priv->fsb_freq = 5866;
733 dev_priv->fsb_freq = 6400;
736 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
738 dev_priv->fsb_freq = 0;
742 if (dev_priv->fsb_freq == 3200) {
743 dev_priv->ips.c_m = 0;
744 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
745 dev_priv->ips.c_m = 1;
747 dev_priv->ips.c_m = 2;
751 static const struct cxsr_latency cxsr_latency_table[] = {
752 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
753 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
754 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
755 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
756 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
758 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
759 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
760 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
761 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
762 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
764 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
765 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
766 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
767 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
768 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
770 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
771 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
772 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
773 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
774 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
776 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
777 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
778 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
779 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
780 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
782 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
783 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
784 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
785 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
786 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
789 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
794 const struct cxsr_latency *latency;
797 if (fsb == 0 || mem == 0)
800 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
801 latency = &cxsr_latency_table[i];
802 if (is_desktop == latency->is_desktop &&
803 is_ddr3 == latency->is_ddr3 &&
804 fsb == latency->fsb_freq && mem == latency->mem_freq)
808 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
813 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
815 struct drm_device *dev = dev_priv->dev;
818 if (IS_VALLEYVIEW(dev)) {
819 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
820 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
821 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
822 } else if (IS_PINEVIEW(dev)) {
823 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
824 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
825 I915_WRITE(DSPFW3, val);
826 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
827 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
828 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
829 I915_WRITE(FW_BLC_SELF, val);
830 } else if (IS_I915GM(dev)) {
831 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
832 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
833 I915_WRITE(INSTPM, val);
838 DRM_DEBUG_KMS("memory self-refresh is %s\n",
839 enable ? "enabled" : "disabled");
843 * Latency for FIFO fetches is dependent on several factors:
844 * - memory configuration (speed, channels)
846 * - current MCH state
847 * It can be fairly high in some situations, so here we assume a fairly
848 * pessimal value. It's a tradeoff between extra memory fetches (if we
849 * set this value too high, the FIFO will fetch frequently to stay full)
850 * and power consumption (set it too low to save power and we might see
851 * FIFO underruns and display "flicker").
853 * A value of 5us seems to be a good balance; safe for very low end
854 * platforms but not overly aggressive on lower latency configs.
856 static const int latency_ns = 5000;
858 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dsparb = I915_READ(DSPARB);
864 size = dsparb & 0x7f;
866 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
868 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
869 plane ? "B" : "A", size);
874 static int i830_get_fifo_size(struct drm_device *dev, int plane)
876 struct drm_i915_private *dev_priv = dev->dev_private;
877 uint32_t dsparb = I915_READ(DSPARB);
880 size = dsparb & 0x1ff;
882 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
883 size >>= 1; /* Convert to cachelines */
885 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
886 plane ? "B" : "A", size);
891 static int i845_get_fifo_size(struct drm_device *dev, int plane)
893 struct drm_i915_private *dev_priv = dev->dev_private;
894 uint32_t dsparb = I915_READ(DSPARB);
897 size = dsparb & 0x7f;
898 size >>= 2; /* Convert to cachelines */
900 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
907 /* Pineview has different values for various configs */
908 static const struct intel_watermark_params pineview_display_wm = {
909 .fifo_size = PINEVIEW_DISPLAY_FIFO,
910 .max_wm = PINEVIEW_MAX_WM,
911 .default_wm = PINEVIEW_DFT_WM,
912 .guard_size = PINEVIEW_GUARD_WM,
913 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
915 static const struct intel_watermark_params pineview_display_hplloff_wm = {
916 .fifo_size = PINEVIEW_DISPLAY_FIFO,
917 .max_wm = PINEVIEW_MAX_WM,
918 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
919 .guard_size = PINEVIEW_GUARD_WM,
920 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
922 static const struct intel_watermark_params pineview_cursor_wm = {
923 .fifo_size = PINEVIEW_CURSOR_FIFO,
924 .max_wm = PINEVIEW_CURSOR_MAX_WM,
925 .default_wm = PINEVIEW_CURSOR_DFT_WM,
926 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
927 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
929 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
930 .fifo_size = PINEVIEW_CURSOR_FIFO,
931 .max_wm = PINEVIEW_CURSOR_MAX_WM,
932 .default_wm = PINEVIEW_CURSOR_DFT_WM,
933 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
934 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
936 static const struct intel_watermark_params g4x_wm_info = {
937 .fifo_size = G4X_FIFO_SIZE,
938 .max_wm = G4X_MAX_WM,
939 .default_wm = G4X_MAX_WM,
941 .cacheline_size = G4X_FIFO_LINE_SIZE,
943 static const struct intel_watermark_params g4x_cursor_wm_info = {
944 .fifo_size = I965_CURSOR_FIFO,
945 .max_wm = I965_CURSOR_MAX_WM,
946 .default_wm = I965_CURSOR_DFT_WM,
948 .cacheline_size = G4X_FIFO_LINE_SIZE,
950 static const struct intel_watermark_params valleyview_wm_info = {
951 .fifo_size = VALLEYVIEW_FIFO_SIZE,
952 .max_wm = VALLEYVIEW_MAX_WM,
953 .default_wm = VALLEYVIEW_MAX_WM,
955 .cacheline_size = G4X_FIFO_LINE_SIZE,
957 static const struct intel_watermark_params valleyview_cursor_wm_info = {
958 .fifo_size = I965_CURSOR_FIFO,
959 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
960 .default_wm = I965_CURSOR_DFT_WM,
962 .cacheline_size = G4X_FIFO_LINE_SIZE,
964 static const struct intel_watermark_params i965_cursor_wm_info = {
965 .fifo_size = I965_CURSOR_FIFO,
966 .max_wm = I965_CURSOR_MAX_WM,
967 .default_wm = I965_CURSOR_DFT_WM,
969 .cacheline_size = I915_FIFO_LINE_SIZE,
971 static const struct intel_watermark_params i945_wm_info = {
972 .fifo_size = I945_FIFO_SIZE,
973 .max_wm = I915_MAX_WM,
976 .cacheline_size = I915_FIFO_LINE_SIZE,
978 static const struct intel_watermark_params i915_wm_info = {
979 .fifo_size = I915_FIFO_SIZE,
980 .max_wm = I915_MAX_WM,
983 .cacheline_size = I915_FIFO_LINE_SIZE,
985 static const struct intel_watermark_params i830_wm_info = {
986 .fifo_size = I855GM_FIFO_SIZE,
987 .max_wm = I915_MAX_WM,
990 .cacheline_size = I830_FIFO_LINE_SIZE,
992 static const struct intel_watermark_params i845_wm_info = {
993 .fifo_size = I830_FIFO_SIZE,
994 .max_wm = I915_MAX_WM,
997 .cacheline_size = I830_FIFO_LINE_SIZE,
1001 * intel_calculate_wm - calculate watermark level
1002 * @clock_in_khz: pixel clock
1003 * @wm: chip FIFO params
1004 * @pixel_size: display pixel size
1005 * @latency_ns: memory latency for the platform
1007 * Calculate the watermark level (the level at which the display plane will
1008 * start fetching from memory again). Each chip has a different display
1009 * FIFO size and allocation, so the caller needs to figure that out and pass
1010 * in the correct intel_watermark_params structure.
1012 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1013 * on the pixel size. When it reaches the watermark level, it'll start
1014 * fetching FIFO line sized based chunks from memory until the FIFO fills
1015 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1016 * will occur, and a display engine hang could result.
1018 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1019 const struct intel_watermark_params *wm,
1022 unsigned long latency_ns)
1024 long entries_required, wm_size;
1027 * Note: we need to make sure we don't overflow for various clock &
1029 * clocks go from a few thousand to several hundred thousand.
1030 * latency is usually a few thousand
1032 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1034 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1036 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1038 wm_size = fifo_size - (entries_required + wm->guard_size);
1040 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1042 /* Don't promote wm_size to unsigned... */
1043 if (wm_size > (long)wm->max_wm)
1044 wm_size = wm->max_wm;
1046 wm_size = wm->default_wm;
1050 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1052 struct drm_crtc *crtc, *enabled = NULL;
1054 for_each_crtc(dev, crtc) {
1055 if (intel_crtc_active(crtc)) {
1065 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1067 struct drm_device *dev = unused_crtc->dev;
1068 struct drm_i915_private *dev_priv = dev->dev_private;
1069 struct drm_crtc *crtc;
1070 const struct cxsr_latency *latency;
1074 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1075 dev_priv->fsb_freq, dev_priv->mem_freq);
1077 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1078 intel_set_memory_cxsr(dev_priv, false);
1082 crtc = single_enabled_crtc(dev);
1084 const struct drm_display_mode *adjusted_mode;
1085 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1088 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1089 clock = adjusted_mode->crtc_clock;
1092 wm = intel_calculate_wm(clock, &pineview_display_wm,
1093 pineview_display_wm.fifo_size,
1094 pixel_size, latency->display_sr);
1095 reg = I915_READ(DSPFW1);
1096 reg &= ~DSPFW_SR_MASK;
1097 reg |= wm << DSPFW_SR_SHIFT;
1098 I915_WRITE(DSPFW1, reg);
1099 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1102 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1103 pineview_display_wm.fifo_size,
1104 pixel_size, latency->cursor_sr);
1105 reg = I915_READ(DSPFW3);
1106 reg &= ~DSPFW_CURSOR_SR_MASK;
1107 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1108 I915_WRITE(DSPFW3, reg);
1110 /* Display HPLL off SR */
1111 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1112 pineview_display_hplloff_wm.fifo_size,
1113 pixel_size, latency->display_hpll_disable);
1114 reg = I915_READ(DSPFW3);
1115 reg &= ~DSPFW_HPLL_SR_MASK;
1116 reg |= wm & DSPFW_HPLL_SR_MASK;
1117 I915_WRITE(DSPFW3, reg);
1119 /* cursor HPLL off SR */
1120 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1121 pineview_display_hplloff_wm.fifo_size,
1122 pixel_size, latency->cursor_hpll_disable);
1123 reg = I915_READ(DSPFW3);
1124 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1125 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1126 I915_WRITE(DSPFW3, reg);
1127 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1129 intel_set_memory_cxsr(dev_priv, true);
1131 intel_set_memory_cxsr(dev_priv, false);
1135 static bool g4x_compute_wm0(struct drm_device *dev,
1137 const struct intel_watermark_params *display,
1138 int display_latency_ns,
1139 const struct intel_watermark_params *cursor,
1140 int cursor_latency_ns,
1144 struct drm_crtc *crtc;
1145 const struct drm_display_mode *adjusted_mode;
1146 int htotal, hdisplay, clock, pixel_size;
1147 int line_time_us, line_count;
1148 int entries, tlb_miss;
1150 crtc = intel_get_crtc_for_plane(dev, plane);
1151 if (!intel_crtc_active(crtc)) {
1152 *cursor_wm = cursor->guard_size;
1153 *plane_wm = display->guard_size;
1157 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1158 clock = adjusted_mode->crtc_clock;
1159 htotal = adjusted_mode->crtc_htotal;
1160 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1161 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1163 /* Use the small buffer method to calculate plane watermark */
1164 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1165 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1167 entries += tlb_miss;
1168 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1169 *plane_wm = entries + display->guard_size;
1170 if (*plane_wm > (int)display->max_wm)
1171 *plane_wm = display->max_wm;
1173 /* Use the large buffer method to calculate cursor watermark */
1174 line_time_us = max(htotal * 1000 / clock, 1);
1175 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1176 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1177 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1179 entries += tlb_miss;
1180 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1181 *cursor_wm = entries + cursor->guard_size;
1182 if (*cursor_wm > (int)cursor->max_wm)
1183 *cursor_wm = (int)cursor->max_wm;
1189 * Check the wm result.
1191 * If any calculated watermark values is larger than the maximum value that
1192 * can be programmed into the associated watermark register, that watermark
1195 static bool g4x_check_srwm(struct drm_device *dev,
1196 int display_wm, int cursor_wm,
1197 const struct intel_watermark_params *display,
1198 const struct intel_watermark_params *cursor)
1200 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1201 display_wm, cursor_wm);
1203 if (display_wm > display->max_wm) {
1204 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1205 display_wm, display->max_wm);
1209 if (cursor_wm > cursor->max_wm) {
1210 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1211 cursor_wm, cursor->max_wm);
1215 if (!(display_wm || cursor_wm)) {
1216 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1223 static bool g4x_compute_srwm(struct drm_device *dev,
1226 const struct intel_watermark_params *display,
1227 const struct intel_watermark_params *cursor,
1228 int *display_wm, int *cursor_wm)
1230 struct drm_crtc *crtc;
1231 const struct drm_display_mode *adjusted_mode;
1232 int hdisplay, htotal, pixel_size, clock;
1233 unsigned long line_time_us;
1234 int line_count, line_size;
1239 *display_wm = *cursor_wm = 0;
1243 crtc = intel_get_crtc_for_plane(dev, plane);
1244 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1245 clock = adjusted_mode->crtc_clock;
1246 htotal = adjusted_mode->crtc_htotal;
1247 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1248 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1250 line_time_us = max(htotal * 1000 / clock, 1);
1251 line_count = (latency_ns / line_time_us + 1000) / 1000;
1252 line_size = hdisplay * pixel_size;
1254 /* Use the minimum of the small and large buffer method for primary */
1255 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1256 large = line_count * line_size;
1258 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1259 *display_wm = entries + display->guard_size;
1261 /* calculate the self-refresh watermark for display cursor */
1262 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1263 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1264 *cursor_wm = entries + cursor->guard_size;
1266 return g4x_check_srwm(dev,
1267 *display_wm, *cursor_wm,
1271 static bool vlv_compute_drain_latency(struct drm_device *dev,
1273 int *plane_prec_mult,
1275 int *cursor_prec_mult,
1278 struct drm_crtc *crtc;
1279 int clock, pixel_size;
1282 crtc = intel_get_crtc_for_plane(dev, plane);
1283 if (!intel_crtc_active(crtc))
1286 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1287 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1289 entries = (clock / 1000) * pixel_size;
1290 *plane_prec_mult = (entries > 256) ?
1291 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1292 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1295 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1296 *cursor_prec_mult = (entries > 256) ?
1297 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1298 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1304 * Update drain latency registers of memory arbiter
1306 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1307 * to be programmed. Each plane has a drain latency multiplier and a drain
1311 static void vlv_update_drain_latency(struct drm_device *dev)
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1315 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1316 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1319 /* For plane A, Cursor A */
1320 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1321 &cursor_prec_mult, &cursora_dl)) {
1322 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1323 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1324 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1325 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1327 I915_WRITE(VLV_DDL1, cursora_prec |
1328 (cursora_dl << DDL_CURSORA_SHIFT) |
1329 planea_prec | planea_dl);
1332 /* For plane B, Cursor B */
1333 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1334 &cursor_prec_mult, &cursorb_dl)) {
1335 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1336 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1337 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1338 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1340 I915_WRITE(VLV_DDL2, cursorb_prec |
1341 (cursorb_dl << DDL_CURSORB_SHIFT) |
1342 planeb_prec | planeb_dl);
1346 #define single_plane_enabled(mask) is_power_of_2(mask)
1348 static void valleyview_update_wm(struct drm_crtc *crtc)
1350 struct drm_device *dev = crtc->dev;
1351 static const int sr_latency_ns = 12000;
1352 struct drm_i915_private *dev_priv = dev->dev_private;
1353 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1354 int plane_sr, cursor_sr;
1355 int ignore_plane_sr, ignore_cursor_sr;
1356 unsigned int enabled = 0;
1359 vlv_update_drain_latency(dev);
1361 if (g4x_compute_wm0(dev, PIPE_A,
1362 &valleyview_wm_info, latency_ns,
1363 &valleyview_cursor_wm_info, latency_ns,
1364 &planea_wm, &cursora_wm))
1365 enabled |= 1 << PIPE_A;
1367 if (g4x_compute_wm0(dev, PIPE_B,
1368 &valleyview_wm_info, latency_ns,
1369 &valleyview_cursor_wm_info, latency_ns,
1370 &planeb_wm, &cursorb_wm))
1371 enabled |= 1 << PIPE_B;
1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1376 &valleyview_wm_info,
1377 &valleyview_cursor_wm_info,
1378 &plane_sr, &ignore_cursor_sr) &&
1379 g4x_compute_srwm(dev, ffs(enabled) - 1,
1381 &valleyview_wm_info,
1382 &valleyview_cursor_wm_info,
1383 &ignore_plane_sr, &cursor_sr)) {
1384 cxsr_enabled = true;
1386 cxsr_enabled = false;
1387 intel_set_memory_cxsr(dev_priv, false);
1388 plane_sr = cursor_sr = 0;
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1392 planea_wm, cursora_wm,
1393 planeb_wm, cursorb_wm,
1394 plane_sr, cursor_sr);
1397 (plane_sr << DSPFW_SR_SHIFT) |
1398 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1399 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1402 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1403 (cursora_wm << DSPFW_CURSORA_SHIFT));
1405 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1406 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1409 intel_set_memory_cxsr(dev_priv, true);
1412 static void g4x_update_wm(struct drm_crtc *crtc)
1414 struct drm_device *dev = crtc->dev;
1415 static const int sr_latency_ns = 12000;
1416 struct drm_i915_private *dev_priv = dev->dev_private;
1417 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1418 int plane_sr, cursor_sr;
1419 unsigned int enabled = 0;
1422 if (g4x_compute_wm0(dev, PIPE_A,
1423 &g4x_wm_info, latency_ns,
1424 &g4x_cursor_wm_info, latency_ns,
1425 &planea_wm, &cursora_wm))
1426 enabled |= 1 << PIPE_A;
1428 if (g4x_compute_wm0(dev, PIPE_B,
1429 &g4x_wm_info, latency_ns,
1430 &g4x_cursor_wm_info, latency_ns,
1431 &planeb_wm, &cursorb_wm))
1432 enabled |= 1 << PIPE_B;
1434 if (single_plane_enabled(enabled) &&
1435 g4x_compute_srwm(dev, ffs(enabled) - 1,
1438 &g4x_cursor_wm_info,
1439 &plane_sr, &cursor_sr)) {
1440 cxsr_enabled = true;
1442 cxsr_enabled = false;
1443 intel_set_memory_cxsr(dev_priv, false);
1444 plane_sr = cursor_sr = 0;
1447 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1448 planea_wm, cursora_wm,
1449 planeb_wm, cursorb_wm,
1450 plane_sr, cursor_sr);
1453 (plane_sr << DSPFW_SR_SHIFT) |
1454 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1455 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1458 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1459 (cursora_wm << DSPFW_CURSORA_SHIFT));
1460 /* HPLL off in SR has some issues on G4x... disable it */
1462 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1463 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1466 intel_set_memory_cxsr(dev_priv, true);
1469 static void i965_update_wm(struct drm_crtc *unused_crtc)
1471 struct drm_device *dev = unused_crtc->dev;
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1473 struct drm_crtc *crtc;
1478 /* Calc sr entries for one plane configs */
1479 crtc = single_enabled_crtc(dev);
1481 /* self-refresh has much higher latency */
1482 static const int sr_latency_ns = 12000;
1483 const struct drm_display_mode *adjusted_mode =
1484 &to_intel_crtc(crtc)->config.adjusted_mode;
1485 int clock = adjusted_mode->crtc_clock;
1486 int htotal = adjusted_mode->crtc_htotal;
1487 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1488 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1489 unsigned long line_time_us;
1492 line_time_us = max(htotal * 1000 / clock, 1);
1494 /* Use ns/us then divide to preserve precision */
1495 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1496 pixel_size * hdisplay;
1497 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1498 srwm = I965_FIFO_SIZE - entries;
1502 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1505 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1506 pixel_size * to_intel_crtc(crtc)->cursor_width;
1507 entries = DIV_ROUND_UP(entries,
1508 i965_cursor_wm_info.cacheline_size);
1509 cursor_sr = i965_cursor_wm_info.fifo_size -
1510 (entries + i965_cursor_wm_info.guard_size);
1512 if (cursor_sr > i965_cursor_wm_info.max_wm)
1513 cursor_sr = i965_cursor_wm_info.max_wm;
1515 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1516 "cursor %d\n", srwm, cursor_sr);
1518 cxsr_enabled = true;
1520 cxsr_enabled = false;
1521 /* Turn off self refresh if both pipes are enabled */
1522 intel_set_memory_cxsr(dev_priv, false);
1525 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1528 /* 965 has limitations... */
1529 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1530 (8 << 16) | (8 << 8) | (8 << 0));
1531 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1532 /* update cursor SR watermark */
1533 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1536 intel_set_memory_cxsr(dev_priv, true);
1539 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1541 struct drm_device *dev = unused_crtc->dev;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 const struct intel_watermark_params *wm_info;
1548 int planea_wm, planeb_wm;
1549 struct drm_crtc *crtc, *enabled = NULL;
1552 wm_info = &i945_wm_info;
1553 else if (!IS_GEN2(dev))
1554 wm_info = &i915_wm_info;
1556 wm_info = &i830_wm_info;
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1559 crtc = intel_get_crtc_for_plane(dev, 0);
1560 if (intel_crtc_active(crtc)) {
1561 const struct drm_display_mode *adjusted_mode;
1562 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1566 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1567 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1568 wm_info, fifo_size, cpp,
1572 planea_wm = fifo_size - wm_info->guard_size;
1574 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1575 crtc = intel_get_crtc_for_plane(dev, 1);
1576 if (intel_crtc_active(crtc)) {
1577 const struct drm_display_mode *adjusted_mode;
1578 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1582 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1583 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1584 wm_info, fifo_size, cpp,
1586 if (enabled == NULL)
1591 planeb_wm = fifo_size - wm_info->guard_size;
1593 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1595 if (IS_I915GM(dev) && enabled) {
1596 struct drm_i915_gem_object *obj;
1598 obj = intel_fb_obj(enabled->primary->fb);
1600 /* self-refresh seems busted with untiled */
1601 if (obj->tiling_mode == I915_TILING_NONE)
1606 * Overlay gets an aggressive default since video jitter is bad.
1610 /* Play safe and disable self-refresh before adjusting watermarks. */
1611 intel_set_memory_cxsr(dev_priv, false);
1613 /* Calc sr entries for one plane configs */
1614 if (HAS_FW_BLC(dev) && enabled) {
1615 /* self-refresh has much higher latency */
1616 static const int sr_latency_ns = 6000;
1617 const struct drm_display_mode *adjusted_mode =
1618 &to_intel_crtc(enabled)->config.adjusted_mode;
1619 int clock = adjusted_mode->crtc_clock;
1620 int htotal = adjusted_mode->crtc_htotal;
1621 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1622 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1623 unsigned long line_time_us;
1626 line_time_us = max(htotal * 1000 / clock, 1);
1628 /* Use ns/us then divide to preserve precision */
1629 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1630 pixel_size * hdisplay;
1631 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1632 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1633 srwm = wm_info->fifo_size - entries;
1637 if (IS_I945G(dev) || IS_I945GM(dev))
1638 I915_WRITE(FW_BLC_SELF,
1639 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1640 else if (IS_I915GM(dev))
1641 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1644 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1645 planea_wm, planeb_wm, cwm, srwm);
1647 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1648 fwater_hi = (cwm & 0x1f);
1650 /* Set request length to 8 cachelines per fetch */
1651 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1652 fwater_hi = fwater_hi | (1 << 8);
1654 I915_WRITE(FW_BLC, fwater_lo);
1655 I915_WRITE(FW_BLC2, fwater_hi);
1658 intel_set_memory_cxsr(dev_priv, true);
1661 static void i845_update_wm(struct drm_crtc *unused_crtc)
1663 struct drm_device *dev = unused_crtc->dev;
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1665 struct drm_crtc *crtc;
1666 const struct drm_display_mode *adjusted_mode;
1670 crtc = single_enabled_crtc(dev);
1674 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1675 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1677 dev_priv->display.get_fifo_size(dev, 0),
1679 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1680 fwater_lo |= (3<<8) | planea_wm;
1682 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1684 I915_WRITE(FW_BLC, fwater_lo);
1687 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1688 struct drm_crtc *crtc)
1690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1691 uint32_t pixel_rate;
1693 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1695 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1696 * adjust the pixel_rate here. */
1698 if (intel_crtc->config.pch_pfit.enabled) {
1699 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1700 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1702 pipe_w = intel_crtc->config.pipe_src_w;
1703 pipe_h = intel_crtc->config.pipe_src_h;
1704 pfit_w = (pfit_size >> 16) & 0xFFFF;
1705 pfit_h = pfit_size & 0xFFFF;
1706 if (pipe_w < pfit_w)
1708 if (pipe_h < pfit_h)
1711 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1718 /* latency must be in 0.1us units. */
1719 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1724 if (WARN(latency == 0, "Latency value missing\n"))
1727 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1728 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1733 /* latency must be in 0.1us units. */
1734 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1735 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1740 if (WARN(latency == 0, "Latency value missing\n"))
1743 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1744 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1745 ret = DIV_ROUND_UP(ret, 64) + 2;
1749 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1750 uint8_t bytes_per_pixel)
1752 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1755 struct ilk_pipe_wm_parameters {
1757 uint32_t pipe_htotal;
1758 uint32_t pixel_rate;
1759 struct intel_plane_wm_parameters pri;
1760 struct intel_plane_wm_parameters spr;
1761 struct intel_plane_wm_parameters cur;
1764 struct ilk_wm_maximums {
1771 /* used in computing the new watermarks state */
1772 struct intel_wm_config {
1773 unsigned int num_pipes_active;
1774 bool sprites_enabled;
1775 bool sprites_scaled;
1779 * For both WM_PIPE and WM_LP.
1780 * mem_value must be in 0.1us units.
1782 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1786 uint32_t method1, method2;
1788 if (!params->active || !params->pri.enabled)
1791 method1 = ilk_wm_method1(params->pixel_rate,
1792 params->pri.bytes_per_pixel,
1798 method2 = ilk_wm_method2(params->pixel_rate,
1799 params->pipe_htotal,
1800 params->pri.horiz_pixels,
1801 params->pri.bytes_per_pixel,
1804 return min(method1, method2);
1808 * For both WM_PIPE and WM_LP.
1809 * mem_value must be in 0.1us units.
1811 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1814 uint32_t method1, method2;
1816 if (!params->active || !params->spr.enabled)
1819 method1 = ilk_wm_method1(params->pixel_rate,
1820 params->spr.bytes_per_pixel,
1822 method2 = ilk_wm_method2(params->pixel_rate,
1823 params->pipe_htotal,
1824 params->spr.horiz_pixels,
1825 params->spr.bytes_per_pixel,
1827 return min(method1, method2);
1831 * For both WM_PIPE and WM_LP.
1832 * mem_value must be in 0.1us units.
1834 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1837 if (!params->active || !params->cur.enabled)
1840 return ilk_wm_method2(params->pixel_rate,
1841 params->pipe_htotal,
1842 params->cur.horiz_pixels,
1843 params->cur.bytes_per_pixel,
1847 /* Only for WM_LP. */
1848 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1851 if (!params->active || !params->pri.enabled)
1854 return ilk_wm_fbc(pri_val,
1855 params->pri.horiz_pixels,
1856 params->pri.bytes_per_pixel);
1859 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1861 if (INTEL_INFO(dev)->gen >= 8)
1863 else if (INTEL_INFO(dev)->gen >= 7)
1869 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1870 int level, bool is_sprite)
1872 if (INTEL_INFO(dev)->gen >= 8)
1873 /* BDW primary/sprite plane watermarks */
1874 return level == 0 ? 255 : 2047;
1875 else if (INTEL_INFO(dev)->gen >= 7)
1876 /* IVB/HSW primary/sprite plane watermarks */
1877 return level == 0 ? 127 : 1023;
1878 else if (!is_sprite)
1879 /* ILK/SNB primary plane watermarks */
1880 return level == 0 ? 127 : 511;
1882 /* ILK/SNB sprite plane watermarks */
1883 return level == 0 ? 63 : 255;
1886 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1889 if (INTEL_INFO(dev)->gen >= 7)
1890 return level == 0 ? 63 : 255;
1892 return level == 0 ? 31 : 63;
1895 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1897 if (INTEL_INFO(dev)->gen >= 8)
1903 /* Calculate the maximum primary/sprite plane watermark */
1904 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1906 const struct intel_wm_config *config,
1907 enum intel_ddb_partitioning ddb_partitioning,
1910 unsigned int fifo_size = ilk_display_fifo_size(dev);
1912 /* if sprites aren't enabled, sprites get nothing */
1913 if (is_sprite && !config->sprites_enabled)
1916 /* HSW allows LP1+ watermarks even with multiple pipes */
1917 if (level == 0 || config->num_pipes_active > 1) {
1918 fifo_size /= INTEL_INFO(dev)->num_pipes;
1921 * For some reason the non self refresh
1922 * FIFO size is only half of the self
1923 * refresh FIFO size on ILK/SNB.
1925 if (INTEL_INFO(dev)->gen <= 6)
1929 if (config->sprites_enabled) {
1930 /* level 0 is always calculated with 1:1 split */
1931 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1940 /* clamp to max that the registers can hold */
1941 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1944 /* Calculate the maximum cursor plane watermark */
1945 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1947 const struct intel_wm_config *config)
1949 /* HSW LP1+ watermarks w/ multiple pipes */
1950 if (level > 0 && config->num_pipes_active > 1)
1953 /* otherwise just report max that registers can hold */
1954 return ilk_cursor_wm_reg_max(dev, level);
1957 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1959 const struct intel_wm_config *config,
1960 enum intel_ddb_partitioning ddb_partitioning,
1961 struct ilk_wm_maximums *max)
1963 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1964 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1965 max->cur = ilk_cursor_wm_max(dev, level, config);
1966 max->fbc = ilk_fbc_wm_reg_max(dev);
1969 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1971 struct ilk_wm_maximums *max)
1973 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1974 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1975 max->cur = ilk_cursor_wm_reg_max(dev, level);
1976 max->fbc = ilk_fbc_wm_reg_max(dev);
1979 static bool ilk_validate_wm_level(int level,
1980 const struct ilk_wm_maximums *max,
1981 struct intel_wm_level *result)
1985 /* already determined to be invalid? */
1986 if (!result->enable)
1989 result->enable = result->pri_val <= max->pri &&
1990 result->spr_val <= max->spr &&
1991 result->cur_val <= max->cur;
1993 ret = result->enable;
1996 * HACK until we can pre-compute everything,
1997 * and thus fail gracefully if LP0 watermarks
2000 if (level == 0 && !result->enable) {
2001 if (result->pri_val > max->pri)
2002 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2003 level, result->pri_val, max->pri);
2004 if (result->spr_val > max->spr)
2005 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2006 level, result->spr_val, max->spr);
2007 if (result->cur_val > max->cur)
2008 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2009 level, result->cur_val, max->cur);
2011 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2012 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2013 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2014 result->enable = true;
2020 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2022 const struct ilk_pipe_wm_parameters *p,
2023 struct intel_wm_level *result)
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2029 /* WM1+ latency values stored in 0.5us units */
2036 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2037 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2038 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2039 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2040 result->enable = true;
2044 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2048 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2049 u32 linetime, ips_linetime;
2051 if (!intel_crtc_active(crtc))
2054 /* The WM are computed with base on how long it takes to fill a single
2055 * row at the given clock rate, multiplied by 8.
2057 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2059 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2060 intel_ddi_get_cdclk_freq(dev_priv));
2062 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2063 PIPE_WM_LINETIME_TIME(linetime);
2066 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2070 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2071 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2073 wm[0] = (sskpd >> 56) & 0xFF;
2075 wm[0] = sskpd & 0xF;
2076 wm[1] = (sskpd >> 4) & 0xFF;
2077 wm[2] = (sskpd >> 12) & 0xFF;
2078 wm[3] = (sskpd >> 20) & 0x1FF;
2079 wm[4] = (sskpd >> 32) & 0x1FF;
2080 } else if (INTEL_INFO(dev)->gen >= 6) {
2081 uint32_t sskpd = I915_READ(MCH_SSKPD);
2083 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2084 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2085 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2086 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2087 } else if (INTEL_INFO(dev)->gen >= 5) {
2088 uint32_t mltr = I915_READ(MLTR_ILK);
2090 /* ILK primary LP0 latency is 700 ns */
2092 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2093 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2097 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2099 /* ILK sprite LP0 latency is 1300 ns */
2100 if (INTEL_INFO(dev)->gen == 5)
2104 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2106 /* ILK cursor LP0 latency is 1300 ns */
2107 if (INTEL_INFO(dev)->gen == 5)
2110 /* WaDoubleCursorLP3Latency:ivb */
2111 if (IS_IVYBRIDGE(dev))
2115 int ilk_wm_max_level(const struct drm_device *dev)
2117 /* how many WM levels are we expecting */
2118 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2120 else if (INTEL_INFO(dev)->gen >= 6)
2126 static void intel_print_wm_latency(struct drm_device *dev,
2128 const uint16_t wm[5])
2130 int level, max_level = ilk_wm_max_level(dev);
2132 for (level = 0; level <= max_level; level++) {
2133 unsigned int latency = wm[level];
2136 DRM_ERROR("%s WM%d latency not provided\n",
2141 /* WM1+ latency values in 0.5us units */
2145 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2146 name, level, wm[level],
2147 latency / 10, latency % 10);
2151 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2152 uint16_t wm[5], uint16_t min)
2154 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2159 wm[0] = max(wm[0], min);
2160 for (level = 1; level <= max_level; level++)
2161 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2166 static void snb_wm_latency_quirk(struct drm_device *dev)
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2172 * The BIOS provided WM memory latency values are often
2173 * inadequate for high resolution displays. Adjust them.
2175 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2176 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2177 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2182 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2183 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2184 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2185 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2188 static void ilk_setup_wm_latency(struct drm_device *dev)
2190 struct drm_i915_private *dev_priv = dev->dev_private;
2192 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2194 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2195 sizeof(dev_priv->wm.pri_latency));
2196 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2197 sizeof(dev_priv->wm.pri_latency));
2199 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2200 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2202 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2203 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2204 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2207 snb_wm_latency_quirk(dev);
2210 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2211 struct ilk_pipe_wm_parameters *p)
2213 struct drm_device *dev = crtc->dev;
2214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2215 enum pipe pipe = intel_crtc->pipe;
2216 struct drm_plane *plane;
2218 if (!intel_crtc_active(crtc))
2222 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2223 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2224 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2225 p->cur.bytes_per_pixel = 4;
2226 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2227 p->cur.horiz_pixels = intel_crtc->cursor_width;
2228 /* TODO: for now, assume primary and cursor planes are always enabled. */
2229 p->pri.enabled = true;
2230 p->cur.enabled = true;
2232 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2233 struct intel_plane *intel_plane = to_intel_plane(plane);
2235 if (intel_plane->pipe == pipe) {
2236 p->spr = intel_plane->wm;
2242 static void ilk_compute_wm_config(struct drm_device *dev,
2243 struct intel_wm_config *config)
2245 struct intel_crtc *intel_crtc;
2247 /* Compute the currently _active_ config */
2248 for_each_intel_crtc(dev, intel_crtc) {
2249 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2251 if (!wm->pipe_enabled)
2254 config->sprites_enabled |= wm->sprites_enabled;
2255 config->sprites_scaled |= wm->sprites_scaled;
2256 config->num_pipes_active++;
2260 /* Compute new watermarks for the pipe */
2261 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2262 const struct ilk_pipe_wm_parameters *params,
2263 struct intel_pipe_wm *pipe_wm)
2265 struct drm_device *dev = crtc->dev;
2266 const struct drm_i915_private *dev_priv = dev->dev_private;
2267 int level, max_level = ilk_wm_max_level(dev);
2268 /* LP0 watermark maximums depend on this pipe alone */
2269 struct intel_wm_config config = {
2270 .num_pipes_active = 1,
2271 .sprites_enabled = params->spr.enabled,
2272 .sprites_scaled = params->spr.scaled,
2274 struct ilk_wm_maximums max;
2276 pipe_wm->pipe_enabled = params->active;
2277 pipe_wm->sprites_enabled = params->spr.enabled;
2278 pipe_wm->sprites_scaled = params->spr.scaled;
2280 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2281 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2284 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2285 if (params->spr.scaled)
2288 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2290 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2291 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2293 /* LP0 watermarks always use 1/2 DDB partitioning */
2294 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2296 /* At least LP0 must be valid */
2297 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2300 ilk_compute_wm_reg_maximums(dev, 1, &max);
2302 for (level = 1; level <= max_level; level++) {
2303 struct intel_wm_level wm = {};
2305 ilk_compute_wm_level(dev_priv, level, params, &wm);
2308 * Disable any watermark level that exceeds the
2309 * register maximums since such watermarks are
2312 if (!ilk_validate_wm_level(level, &max, &wm))
2315 pipe_wm->wm[level] = wm;
2322 * Merge the watermarks from all active pipes for a specific level.
2324 static void ilk_merge_wm_level(struct drm_device *dev,
2326 struct intel_wm_level *ret_wm)
2328 const struct intel_crtc *intel_crtc;
2330 ret_wm->enable = true;
2332 for_each_intel_crtc(dev, intel_crtc) {
2333 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2334 const struct intel_wm_level *wm = &active->wm[level];
2336 if (!active->pipe_enabled)
2340 * The watermark values may have been used in the past,
2341 * so we must maintain them in the registers for some
2342 * time even if the level is now disabled.
2345 ret_wm->enable = false;
2347 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2348 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2349 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2350 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2355 * Merge all low power watermarks for all active pipes.
2357 static void ilk_wm_merge(struct drm_device *dev,
2358 const struct intel_wm_config *config,
2359 const struct ilk_wm_maximums *max,
2360 struct intel_pipe_wm *merged)
2362 int level, max_level = ilk_wm_max_level(dev);
2363 int last_enabled_level = max_level;
2365 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2366 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2367 config->num_pipes_active > 1)
2370 /* ILK: FBC WM must be disabled always */
2371 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2373 /* merge each WM1+ level */
2374 for (level = 1; level <= max_level; level++) {
2375 struct intel_wm_level *wm = &merged->wm[level];
2377 ilk_merge_wm_level(dev, level, wm);
2379 if (level > last_enabled_level)
2381 else if (!ilk_validate_wm_level(level, max, wm))
2382 /* make sure all following levels get disabled */
2383 last_enabled_level = level - 1;
2386 * The spec says it is preferred to disable
2387 * FBC WMs instead of disabling a WM level.
2389 if (wm->fbc_val > max->fbc) {
2391 merged->fbc_wm_enabled = false;
2396 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2398 * FIXME this is racy. FBC might get enabled later.
2399 * What we should check here is whether FBC can be
2400 * enabled sometime later.
2402 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2403 for (level = 2; level <= max_level; level++) {
2404 struct intel_wm_level *wm = &merged->wm[level];
2411 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2413 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2414 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2417 /* The value we need to program into the WM_LPx latency field */
2418 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2422 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2425 return dev_priv->wm.pri_latency[level];
2428 static void ilk_compute_wm_results(struct drm_device *dev,
2429 const struct intel_pipe_wm *merged,
2430 enum intel_ddb_partitioning partitioning,
2431 struct ilk_wm_values *results)
2433 struct intel_crtc *intel_crtc;
2436 results->enable_fbc_wm = merged->fbc_wm_enabled;
2437 results->partitioning = partitioning;
2439 /* LP1+ register values */
2440 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2441 const struct intel_wm_level *r;
2443 level = ilk_wm_lp_to_level(wm_lp, merged);
2445 r = &merged->wm[level];
2448 * Maintain the watermark values even if the level is
2449 * disabled. Doing otherwise could cause underruns.
2451 results->wm_lp[wm_lp - 1] =
2452 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2453 (r->pri_val << WM1_LP_SR_SHIFT) |
2457 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2459 if (INTEL_INFO(dev)->gen >= 8)
2460 results->wm_lp[wm_lp - 1] |=
2461 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2463 results->wm_lp[wm_lp - 1] |=
2464 r->fbc_val << WM1_LP_FBC_SHIFT;
2467 * Always set WM1S_LP_EN when spr_val != 0, even if the
2468 * level is disabled. Doing otherwise could cause underruns.
2470 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2471 WARN_ON(wm_lp != 1);
2472 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2474 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2477 /* LP0 register values */
2478 for_each_intel_crtc(dev, intel_crtc) {
2479 enum pipe pipe = intel_crtc->pipe;
2480 const struct intel_wm_level *r =
2481 &intel_crtc->wm.active.wm[0];
2483 if (WARN_ON(!r->enable))
2486 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2488 results->wm_pipe[pipe] =
2489 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2490 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2495 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2496 * case both are at the same level. Prefer r1 in case they're the same. */
2497 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2498 struct intel_pipe_wm *r1,
2499 struct intel_pipe_wm *r2)
2501 int level, max_level = ilk_wm_max_level(dev);
2502 int level1 = 0, level2 = 0;
2504 for (level = 1; level <= max_level; level++) {
2505 if (r1->wm[level].enable)
2507 if (r2->wm[level].enable)
2511 if (level1 == level2) {
2512 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2516 } else if (level1 > level2) {
2523 /* dirty bits used to track which watermarks need changes */
2524 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2525 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2526 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2527 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2528 #define WM_DIRTY_FBC (1 << 24)
2529 #define WM_DIRTY_DDB (1 << 25)
2531 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2532 const struct ilk_wm_values *old,
2533 const struct ilk_wm_values *new)
2535 unsigned int dirty = 0;
2539 for_each_pipe(pipe) {
2540 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2541 dirty |= WM_DIRTY_LINETIME(pipe);
2542 /* Must disable LP1+ watermarks too */
2543 dirty |= WM_DIRTY_LP_ALL;
2546 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2547 dirty |= WM_DIRTY_PIPE(pipe);
2548 /* Must disable LP1+ watermarks too */
2549 dirty |= WM_DIRTY_LP_ALL;
2553 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2554 dirty |= WM_DIRTY_FBC;
2555 /* Must disable LP1+ watermarks too */
2556 dirty |= WM_DIRTY_LP_ALL;
2559 if (old->partitioning != new->partitioning) {
2560 dirty |= WM_DIRTY_DDB;
2561 /* Must disable LP1+ watermarks too */
2562 dirty |= WM_DIRTY_LP_ALL;
2565 /* LP1+ watermarks already deemed dirty, no need to continue */
2566 if (dirty & WM_DIRTY_LP_ALL)
2569 /* Find the lowest numbered LP1+ watermark in need of an update... */
2570 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2571 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2572 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2576 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2577 for (; wm_lp <= 3; wm_lp++)
2578 dirty |= WM_DIRTY_LP(wm_lp);
2583 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2586 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2587 bool changed = false;
2589 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2590 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2591 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2594 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2595 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2596 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2599 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2600 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2601 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2606 * Don't touch WM1S_LP_EN here.
2607 * Doing so could cause underruns.
2614 * The spec says we shouldn't write when we don't need, because every write
2615 * causes WMs to be re-evaluated, expending some power.
2617 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2618 struct ilk_wm_values *results)
2620 struct drm_device *dev = dev_priv->dev;
2621 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2625 dirty = ilk_compute_wm_dirty(dev, previous, results);
2629 _ilk_disable_lp_wm(dev_priv, dirty);
2631 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2632 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2633 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2634 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2635 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2636 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2638 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2639 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2640 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2641 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2642 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2643 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2645 if (dirty & WM_DIRTY_DDB) {
2646 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2647 val = I915_READ(WM_MISC);
2648 if (results->partitioning == INTEL_DDB_PART_1_2)
2649 val &= ~WM_MISC_DATA_PARTITION_5_6;
2651 val |= WM_MISC_DATA_PARTITION_5_6;
2652 I915_WRITE(WM_MISC, val);
2654 val = I915_READ(DISP_ARB_CTL2);
2655 if (results->partitioning == INTEL_DDB_PART_1_2)
2656 val &= ~DISP_DATA_PARTITION_5_6;
2658 val |= DISP_DATA_PARTITION_5_6;
2659 I915_WRITE(DISP_ARB_CTL2, val);
2663 if (dirty & WM_DIRTY_FBC) {
2664 val = I915_READ(DISP_ARB_CTL);
2665 if (results->enable_fbc_wm)
2666 val &= ~DISP_FBC_WM_DIS;
2668 val |= DISP_FBC_WM_DIS;
2669 I915_WRITE(DISP_ARB_CTL, val);
2672 if (dirty & WM_DIRTY_LP(1) &&
2673 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2674 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2676 if (INTEL_INFO(dev)->gen >= 7) {
2677 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2678 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2679 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2680 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2683 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2684 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2685 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2686 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2687 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2688 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2690 dev_priv->wm.hw = *results;
2693 static bool ilk_disable_lp_wm(struct drm_device *dev)
2695 struct drm_i915_private *dev_priv = dev->dev_private;
2697 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2700 static void ilk_update_wm(struct drm_crtc *crtc)
2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703 struct drm_device *dev = crtc->dev;
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705 struct ilk_wm_maximums max;
2706 struct ilk_pipe_wm_parameters params = {};
2707 struct ilk_wm_values results = {};
2708 enum intel_ddb_partitioning partitioning;
2709 struct intel_pipe_wm pipe_wm = {};
2710 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2711 struct intel_wm_config config = {};
2713 ilk_compute_wm_parameters(crtc, ¶ms);
2715 intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm);
2717 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2720 intel_crtc->wm.active = pipe_wm;
2722 ilk_compute_wm_config(dev, &config);
2724 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2725 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2727 /* 5/6 split only in single pipe config on IVB+ */
2728 if (INTEL_INFO(dev)->gen >= 7 &&
2729 config.num_pipes_active == 1 && config.sprites_enabled) {
2730 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2731 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2733 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2735 best_lp_wm = &lp_wm_1_2;
2738 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2739 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2741 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2743 ilk_write_wm_values(dev_priv, &results);
2747 ilk_update_sprite_wm(struct drm_plane *plane,
2748 struct drm_crtc *crtc,
2749 uint32_t sprite_width, uint32_t sprite_height,
2750 int pixel_size, bool enabled, bool scaled)
2752 struct drm_device *dev = plane->dev;
2753 struct intel_plane *intel_plane = to_intel_plane(plane);
2755 intel_plane->wm.enabled = enabled;
2756 intel_plane->wm.scaled = scaled;
2757 intel_plane->wm.horiz_pixels = sprite_width;
2758 intel_plane->wm.vert_pixels = sprite_width;
2759 intel_plane->wm.bytes_per_pixel = pixel_size;
2762 * IVB workaround: must disable low power watermarks for at least
2763 * one frame before enabling scaling. LP watermarks can be re-enabled
2764 * when scaling is disabled.
2766 * WaCxSRDisabledForSpriteScaling:ivb
2768 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2769 intel_wait_for_vblank(dev, intel_plane->pipe);
2771 ilk_update_wm(crtc);
2774 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2776 struct drm_device *dev = crtc->dev;
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2780 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2781 enum pipe pipe = intel_crtc->pipe;
2782 static const unsigned int wm0_pipe_reg[] = {
2783 [PIPE_A] = WM0_PIPEA_ILK,
2784 [PIPE_B] = WM0_PIPEB_ILK,
2785 [PIPE_C] = WM0_PIPEC_IVB,
2788 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2789 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2790 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2792 active->pipe_enabled = intel_crtc_active(crtc);
2794 if (active->pipe_enabled) {
2795 u32 tmp = hw->wm_pipe[pipe];
2798 * For active pipes LP0 watermark is marked as
2799 * enabled, and LP1+ watermaks as disabled since
2800 * we can't really reverse compute them in case
2801 * multiple pipes are active.
2803 active->wm[0].enable = true;
2804 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2805 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2806 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2807 active->linetime = hw->wm_linetime[pipe];
2809 int level, max_level = ilk_wm_max_level(dev);
2812 * For inactive pipes, all watermark levels
2813 * should be marked as enabled but zeroed,
2814 * which is what we'd compute them to.
2816 for (level = 0; level <= max_level; level++)
2817 active->wm[level].enable = true;
2821 void ilk_wm_get_hw_state(struct drm_device *dev)
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct ilk_wm_values *hw = &dev_priv->wm.hw;
2825 struct drm_crtc *crtc;
2827 for_each_crtc(dev, crtc)
2828 ilk_pipe_wm_get_hw_state(crtc);
2830 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2831 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2832 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2834 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2835 if (INTEL_INFO(dev)->gen >= 7) {
2836 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2837 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2840 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2841 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2842 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2843 else if (IS_IVYBRIDGE(dev))
2844 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2845 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2848 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2852 * intel_update_watermarks - update FIFO watermark values based on current modes
2854 * Calculate watermark values for the various WM regs based on current mode
2855 * and plane configuration.
2857 * There are several cases to deal with here:
2858 * - normal (i.e. non-self-refresh)
2859 * - self-refresh (SR) mode
2860 * - lines are large relative to FIFO size (buffer can hold up to 2)
2861 * - lines are small relative to FIFO size (buffer can hold more than 2
2862 * lines), so need to account for TLB latency
2864 * The normal calculation is:
2865 * watermark = dotclock * bytes per pixel * latency
2866 * where latency is platform & configuration dependent (we assume pessimal
2869 * The SR calculation is:
2870 * watermark = (trunc(latency/line time)+1) * surface width *
2873 * line time = htotal / dotclock
2874 * surface width = hdisplay for normal plane and 64 for cursor
2875 * and latency is assumed to be high, as above.
2877 * The final value programmed to the register should always be rounded up,
2878 * and include an extra 2 entries to account for clock crossings.
2880 * We don't use the sprite, so we can ignore that. And on Crestline we have
2881 * to set the non-SR watermarks to 8.
2883 void intel_update_watermarks(struct drm_crtc *crtc)
2885 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2887 if (dev_priv->display.update_wm)
2888 dev_priv->display.update_wm(crtc);
2891 void intel_update_sprite_watermarks(struct drm_plane *plane,
2892 struct drm_crtc *crtc,
2893 uint32_t sprite_width,
2894 uint32_t sprite_height,
2896 bool enabled, bool scaled)
2898 struct drm_i915_private *dev_priv = plane->dev->dev_private;
2900 if (dev_priv->display.update_sprite_wm)
2901 dev_priv->display.update_sprite_wm(plane, crtc,
2902 sprite_width, sprite_height,
2903 pixel_size, enabled, scaled);
2906 static struct drm_i915_gem_object *
2907 intel_alloc_context_page(struct drm_device *dev)
2909 struct drm_i915_gem_object *ctx;
2912 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2914 ctx = i915_gem_alloc_object(dev, 4096);
2916 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2920 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2922 DRM_ERROR("failed to pin power context: %d\n", ret);
2926 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2928 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2935 i915_gem_object_ggtt_unpin(ctx);
2937 drm_gem_object_unreference(&ctx->base);
2942 * Lock protecting IPS related data structures
2944 DEFINE_SPINLOCK(mchdev_lock);
2946 /* Global for IPS driver to get at the current i915 device. Protected by
2948 static struct drm_i915_private *i915_mch_dev;
2950 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2952 struct drm_i915_private *dev_priv = dev->dev_private;
2955 assert_spin_locked(&mchdev_lock);
2957 rgvswctl = I915_READ16(MEMSWCTL);
2958 if (rgvswctl & MEMCTL_CMD_STS) {
2959 DRM_DEBUG("gpu busy, RCS change rejected\n");
2960 return false; /* still busy with another command */
2963 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2964 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2965 I915_WRITE16(MEMSWCTL, rgvswctl);
2966 POSTING_READ16(MEMSWCTL);
2968 rgvswctl |= MEMCTL_CMD_STS;
2969 I915_WRITE16(MEMSWCTL, rgvswctl);
2974 static void ironlake_enable_drps(struct drm_device *dev)
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 u32 rgvmodectl = I915_READ(MEMMODECTL);
2978 u8 fmax, fmin, fstart, vstart;
2980 spin_lock_irq(&mchdev_lock);
2982 /* Enable temp reporting */
2983 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2984 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2986 /* 100ms RC evaluation intervals */
2987 I915_WRITE(RCUPEI, 100000);
2988 I915_WRITE(RCDNEI, 100000);
2990 /* Set max/min thresholds to 90ms and 80ms respectively */
2991 I915_WRITE(RCBMAXAVG, 90000);
2992 I915_WRITE(RCBMINAVG, 80000);
2994 I915_WRITE(MEMIHYST, 1);
2996 /* Set up min, max, and cur for interrupt handling */
2997 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2998 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2999 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3000 MEMMODE_FSTART_SHIFT;
3002 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3005 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3006 dev_priv->ips.fstart = fstart;
3008 dev_priv->ips.max_delay = fstart;
3009 dev_priv->ips.min_delay = fmin;
3010 dev_priv->ips.cur_delay = fstart;
3012 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3013 fmax, fmin, fstart);
3015 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3018 * Interrupts will be enabled in ironlake_irq_postinstall
3021 I915_WRITE(VIDSTART, vstart);
3022 POSTING_READ(VIDSTART);
3024 rgvmodectl |= MEMMODE_SWMODE_EN;
3025 I915_WRITE(MEMMODECTL, rgvmodectl);
3027 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3028 DRM_ERROR("stuck trying to change perf mode\n");
3031 ironlake_set_drps(dev, fstart);
3033 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3035 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3036 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3037 getrawmonotonic(&dev_priv->ips.last_time2);
3039 spin_unlock_irq(&mchdev_lock);
3042 static void ironlake_disable_drps(struct drm_device *dev)
3044 struct drm_i915_private *dev_priv = dev->dev_private;
3047 spin_lock_irq(&mchdev_lock);
3049 rgvswctl = I915_READ16(MEMSWCTL);
3051 /* Ack interrupts, disable EFC interrupt */
3052 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3053 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3054 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3055 I915_WRITE(DEIIR, DE_PCU_EVENT);
3056 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3058 /* Go back to the starting frequency */
3059 ironlake_set_drps(dev, dev_priv->ips.fstart);
3061 rgvswctl |= MEMCTL_CMD_STS;
3062 I915_WRITE(MEMSWCTL, rgvswctl);
3065 spin_unlock_irq(&mchdev_lock);
3068 /* There's a funny hw issue where the hw returns all 0 when reading from
3069 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3070 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3071 * all limits and the gpu stuck at whatever frequency it is at atm).
3073 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3077 /* Only set the down limit when we've reached the lowest level to avoid
3078 * getting more interrupts, otherwise leave this clear. This prevents a
3079 * race in the hw when coming out of rc6: There's a tiny window where
3080 * the hw runs at the minimal clock before selecting the desired
3081 * frequency, if the down threshold expires in that window we will not
3082 * receive a down interrupt. */
3083 limits = dev_priv->rps.max_freq_softlimit << 24;
3084 if (val <= dev_priv->rps.min_freq_softlimit)
3085 limits |= dev_priv->rps.min_freq_softlimit << 16;
3090 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3094 new_power = dev_priv->rps.power;
3095 switch (dev_priv->rps.power) {
3097 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3098 new_power = BETWEEN;
3102 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3103 new_power = LOW_POWER;
3104 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3105 new_power = HIGH_POWER;
3109 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3110 new_power = BETWEEN;
3113 /* Max/min bins are special */
3114 if (val == dev_priv->rps.min_freq_softlimit)
3115 new_power = LOW_POWER;
3116 if (val == dev_priv->rps.max_freq_softlimit)
3117 new_power = HIGH_POWER;
3118 if (new_power == dev_priv->rps.power)
3121 /* Note the units here are not exactly 1us, but 1280ns. */
3122 switch (new_power) {
3124 /* Upclock if more than 95% busy over 16ms */
3125 I915_WRITE(GEN6_RP_UP_EI, 12500);
3126 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3128 /* Downclock if less than 85% busy over 32ms */
3129 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3130 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3132 I915_WRITE(GEN6_RP_CONTROL,
3133 GEN6_RP_MEDIA_TURBO |
3134 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3135 GEN6_RP_MEDIA_IS_GFX |
3137 GEN6_RP_UP_BUSY_AVG |
3138 GEN6_RP_DOWN_IDLE_AVG);
3142 /* Upclock if more than 90% busy over 13ms */
3143 I915_WRITE(GEN6_RP_UP_EI, 10250);
3144 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3146 /* Downclock if less than 75% busy over 32ms */
3147 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3148 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3150 I915_WRITE(GEN6_RP_CONTROL,
3151 GEN6_RP_MEDIA_TURBO |
3152 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3153 GEN6_RP_MEDIA_IS_GFX |
3155 GEN6_RP_UP_BUSY_AVG |
3156 GEN6_RP_DOWN_IDLE_AVG);
3160 /* Upclock if more than 85% busy over 10ms */
3161 I915_WRITE(GEN6_RP_UP_EI, 8000);
3162 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3164 /* Downclock if less than 60% busy over 32ms */
3165 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3166 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3168 I915_WRITE(GEN6_RP_CONTROL,
3169 GEN6_RP_MEDIA_TURBO |
3170 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3171 GEN6_RP_MEDIA_IS_GFX |
3173 GEN6_RP_UP_BUSY_AVG |
3174 GEN6_RP_DOWN_IDLE_AVG);
3178 dev_priv->rps.power = new_power;
3179 dev_priv->rps.last_adj = 0;
3182 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3186 if (val > dev_priv->rps.min_freq_softlimit)
3187 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3188 if (val < dev_priv->rps.max_freq_softlimit)
3189 mask |= GEN6_PM_RP_UP_THRESHOLD;
3191 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3192 mask &= dev_priv->pm_rps_events;
3194 /* IVB and SNB hard hangs on looping batchbuffer
3195 * if GEN6_PM_UP_EI_EXPIRED is masked.
3197 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3198 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3200 if (IS_GEN8(dev_priv->dev))
3201 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3206 /* gen6_set_rps is called to update the frequency request, but should also be
3207 * called when the range (min_delay and max_delay) is modified so that we can
3208 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3209 void gen6_set_rps(struct drm_device *dev, u8 val)
3211 struct drm_i915_private *dev_priv = dev->dev_private;
3213 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3214 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3215 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3217 /* min/max delay may still have been modified so be sure to
3218 * write the limits value.
3220 if (val != dev_priv->rps.cur_freq) {
3221 gen6_set_rps_thresholds(dev_priv, val);
3223 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3224 I915_WRITE(GEN6_RPNSWREQ,
3225 HSW_FREQUENCY(val));
3227 I915_WRITE(GEN6_RPNSWREQ,
3228 GEN6_FREQUENCY(val) |
3230 GEN6_AGGRESSIVE_TURBO);
3233 /* Make sure we continue to get interrupts
3234 * until we hit the minimum or maximum frequencies.
3236 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3237 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3239 POSTING_READ(GEN6_RPNSWREQ);
3241 dev_priv->rps.cur_freq = val;
3242 trace_intel_gpu_freq_change(val * 50);
3245 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3247 * * If Gfx is Idle, then
3248 * 1. Mask Turbo interrupts
3249 * 2. Bring up Gfx clock
3250 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3251 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3252 * 5. Unmask Turbo interrupts
3254 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3256 struct drm_device *dev = dev_priv->dev;
3258 /* Latest VLV doesn't need to force the gfx clock */
3259 if (dev->pdev->revision >= 0xd) {
3260 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3265 * When we are idle. Drop to min voltage state.
3268 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3271 /* Mask turbo interrupt so that they will not come in between */
3272 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3274 vlv_force_gfx_clock(dev_priv, true);
3276 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3278 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3279 dev_priv->rps.min_freq_softlimit);
3281 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3282 & GENFREQSTATUS) == 0, 5))
3283 DRM_ERROR("timed out waiting for Punit\n");
3285 vlv_force_gfx_clock(dev_priv, false);
3287 I915_WRITE(GEN6_PMINTRMSK,
3288 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3291 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3293 struct drm_device *dev = dev_priv->dev;
3295 mutex_lock(&dev_priv->rps.hw_lock);
3296 if (dev_priv->rps.enabled) {
3297 if (IS_CHERRYVIEW(dev))
3298 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3299 else if (IS_VALLEYVIEW(dev))
3300 vlv_set_rps_idle(dev_priv);
3302 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3303 dev_priv->rps.last_adj = 0;
3305 mutex_unlock(&dev_priv->rps.hw_lock);
3308 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3310 struct drm_device *dev = dev_priv->dev;
3312 mutex_lock(&dev_priv->rps.hw_lock);
3313 if (dev_priv->rps.enabled) {
3314 if (IS_VALLEYVIEW(dev))
3315 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3317 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3318 dev_priv->rps.last_adj = 0;
3320 mutex_unlock(&dev_priv->rps.hw_lock);
3323 void valleyview_set_rps(struct drm_device *dev, u8 val)
3325 struct drm_i915_private *dev_priv = dev->dev_private;
3327 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3328 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3329 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3331 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3332 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3333 dev_priv->rps.cur_freq,
3334 vlv_gpu_freq(dev_priv, val), val);
3336 if (val != dev_priv->rps.cur_freq)
3337 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3339 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3341 dev_priv->rps.cur_freq = val;
3342 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3345 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3347 struct drm_i915_private *dev_priv = dev->dev_private;
3349 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3350 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3351 ~dev_priv->pm_rps_events);
3352 /* Complete PM interrupt masking here doesn't race with the rps work
3353 * item again unmasking PM interrupts because that is using a different
3354 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3355 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3356 * gen8_enable_rps will clean up. */
3358 spin_lock_irq(&dev_priv->irq_lock);
3359 dev_priv->rps.pm_iir = 0;
3360 spin_unlock_irq(&dev_priv->irq_lock);
3362 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3365 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3369 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3370 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3371 ~dev_priv->pm_rps_events);
3372 /* Complete PM interrupt masking here doesn't race with the rps work
3373 * item again unmasking PM interrupts because that is using a different
3374 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3375 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3377 spin_lock_irq(&dev_priv->irq_lock);
3378 dev_priv->rps.pm_iir = 0;
3379 spin_unlock_irq(&dev_priv->irq_lock);
3381 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3384 static void gen6_disable_rps(struct drm_device *dev)
3386 struct drm_i915_private *dev_priv = dev->dev_private;
3388 I915_WRITE(GEN6_RC_CONTROL, 0);
3389 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3391 if (IS_BROADWELL(dev))
3392 gen8_disable_rps_interrupts(dev);
3394 gen6_disable_rps_interrupts(dev);
3397 static void cherryview_disable_rps(struct drm_device *dev)
3399 struct drm_i915_private *dev_priv = dev->dev_private;
3401 I915_WRITE(GEN6_RC_CONTROL, 0);
3403 gen8_disable_rps_interrupts(dev);
3406 static void valleyview_disable_rps(struct drm_device *dev)
3408 struct drm_i915_private *dev_priv = dev->dev_private;
3410 I915_WRITE(GEN6_RC_CONTROL, 0);
3412 gen6_disable_rps_interrupts(dev);
3415 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3417 if (IS_VALLEYVIEW(dev)) {
3418 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3419 mode = GEN6_RC_CTL_RC6_ENABLE;
3423 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3424 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3425 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3426 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3429 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3431 /* No RC6 before Ironlake */
3432 if (INTEL_INFO(dev)->gen < 5)
3435 /* RC6 is only on Ironlake mobile not on desktop */
3436 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3439 /* Respect the kernel parameter if it is set */
3440 if (enable_rc6 >= 0) {
3443 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3444 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3447 mask = INTEL_RC6_ENABLE;
3449 if ((enable_rc6 & mask) != enable_rc6)
3450 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3451 enable_rc6 & mask, enable_rc6, mask);
3453 return enable_rc6 & mask;
3456 /* Disable RC6 on Ironlake */
3457 if (INTEL_INFO(dev)->gen == 5)
3460 if (IS_IVYBRIDGE(dev))
3461 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3463 return INTEL_RC6_ENABLE;
3466 int intel_enable_rc6(const struct drm_device *dev)
3468 return i915.enable_rc6;
3471 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3473 struct drm_i915_private *dev_priv = dev->dev_private;
3475 spin_lock_irq(&dev_priv->irq_lock);
3476 WARN_ON(dev_priv->rps.pm_iir);
3477 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3478 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3479 spin_unlock_irq(&dev_priv->irq_lock);
3482 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3486 spin_lock_irq(&dev_priv->irq_lock);
3487 WARN_ON(dev_priv->rps.pm_iir);
3488 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3489 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3490 spin_unlock_irq(&dev_priv->irq_lock);
3493 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3495 /* All of these values are in units of 50MHz */
3496 dev_priv->rps.cur_freq = 0;
3497 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3498 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3499 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3500 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3501 /* XXX: only BYT has a special efficient freq */
3502 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3503 /* hw_max = RP0 until we check for overclocking */
3504 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3506 /* Preserve min/max settings in case of re-init */
3507 if (dev_priv->rps.max_freq_softlimit == 0)
3508 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3510 if (dev_priv->rps.min_freq_softlimit == 0)
3511 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3514 static void gen8_enable_rps(struct drm_device *dev)
3516 struct drm_i915_private *dev_priv = dev->dev_private;
3517 struct intel_engine_cs *ring;
3518 uint32_t rc6_mask = 0, rp_state_cap;
3521 /* 1a: Software RC state - RC0 */
3522 I915_WRITE(GEN6_RC_STATE, 0);
3524 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3525 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3526 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3528 /* 2a: Disable RC states. */
3529 I915_WRITE(GEN6_RC_CONTROL, 0);
3531 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3532 parse_rp_state_cap(dev_priv, rp_state_cap);
3534 /* 2b: Program RC6 thresholds.*/
3535 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3536 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3537 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3538 for_each_ring(ring, dev_priv, unused)
3539 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3540 I915_WRITE(GEN6_RC_SLEEP, 0);
3541 if (IS_BROADWELL(dev))
3542 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3544 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3547 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3548 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3549 intel_print_rc6_info(dev, rc6_mask);
3550 if (IS_BROADWELL(dev))
3551 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3552 GEN7_RC_CTL_TO_MODE |
3555 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3556 GEN6_RC_CTL_EI_MODE(1) |
3559 /* 4 Program defaults and thresholds for RPS*/
3560 I915_WRITE(GEN6_RPNSWREQ,
3561 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3562 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3563 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3564 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3565 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3567 /* Docs recommend 900MHz, and 300 MHz respectively */
3568 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3569 dev_priv->rps.max_freq_softlimit << 24 |
3570 dev_priv->rps.min_freq_softlimit << 16);
3572 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3573 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3574 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3575 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3577 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3580 I915_WRITE(GEN6_RP_CONTROL,
3581 GEN6_RP_MEDIA_TURBO |
3582 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3583 GEN6_RP_MEDIA_IS_GFX |
3585 GEN6_RP_UP_BUSY_AVG |
3586 GEN6_RP_DOWN_IDLE_AVG);
3588 /* 6: Ring frequency + overclocking (our driver does this later */
3590 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3592 gen8_enable_rps_interrupts(dev);
3594 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3597 static void gen6_enable_rps(struct drm_device *dev)
3599 struct drm_i915_private *dev_priv = dev->dev_private;
3600 struct intel_engine_cs *ring;
3603 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3608 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3610 /* Here begins a magic sequence of register writes to enable
3611 * auto-downclocking.
3613 * Perhaps there might be some value in exposing these to
3616 I915_WRITE(GEN6_RC_STATE, 0);
3618 /* Clear the DBG now so we don't confuse earlier errors */
3619 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3620 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3621 I915_WRITE(GTFIFODBG, gtfifodbg);
3624 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3626 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3627 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3629 parse_rp_state_cap(dev_priv, rp_state_cap);
3631 /* disable the counters and set deterministic thresholds */
3632 I915_WRITE(GEN6_RC_CONTROL, 0);
3634 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3635 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3636 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3637 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3638 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3640 for_each_ring(ring, dev_priv, i)
3641 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3643 I915_WRITE(GEN6_RC_SLEEP, 0);
3644 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3645 if (IS_IVYBRIDGE(dev))
3646 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3648 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3649 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3650 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3652 /* Check if we are enabling RC6 */
3653 rc6_mode = intel_enable_rc6(dev_priv->dev);
3654 if (rc6_mode & INTEL_RC6_ENABLE)
3655 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3657 /* We don't use those on Haswell */
3658 if (!IS_HASWELL(dev)) {
3659 if (rc6_mode & INTEL_RC6p_ENABLE)
3660 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3662 if (rc6_mode & INTEL_RC6pp_ENABLE)
3663 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3666 intel_print_rc6_info(dev, rc6_mask);
3668 I915_WRITE(GEN6_RC_CONTROL,
3670 GEN6_RC_CTL_EI_MODE(1) |
3671 GEN6_RC_CTL_HW_ENABLE);
3673 /* Power down if completely idle for over 50ms */
3674 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3675 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3677 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3679 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3681 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3682 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3683 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3684 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3685 (pcu_mbox & 0xff) * 50);
3686 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3689 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3690 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3692 gen6_enable_rps_interrupts(dev);
3695 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3696 if (IS_GEN6(dev) && ret) {
3697 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3698 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3699 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3700 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3701 rc6vids &= 0xffff00;
3702 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3703 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3705 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3708 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3711 static void __gen6_update_ring_freq(struct drm_device *dev)
3713 struct drm_i915_private *dev_priv = dev->dev_private;
3715 unsigned int gpu_freq;
3716 unsigned int max_ia_freq, min_ring_freq;
3717 int scaling_factor = 180;
3718 struct cpufreq_policy *policy;
3720 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3722 policy = cpufreq_cpu_get(0);
3724 max_ia_freq = policy->cpuinfo.max_freq;
3725 cpufreq_cpu_put(policy);
3728 * Default to measured freq if none found, PCU will ensure we
3731 max_ia_freq = tsc_khz;
3734 /* Convert from kHz to MHz */
3735 max_ia_freq /= 1000;
3737 min_ring_freq = I915_READ(DCLK) & 0xf;
3738 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3739 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3742 * For each potential GPU frequency, load a ring frequency we'd like
3743 * to use for memory access. We do this by specifying the IA frequency
3744 * the PCU should use as a reference to determine the ring frequency.
3746 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3748 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3749 unsigned int ia_freq = 0, ring_freq = 0;
3751 if (INTEL_INFO(dev)->gen >= 8) {
3752 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3753 ring_freq = max(min_ring_freq, gpu_freq);
3754 } else if (IS_HASWELL(dev)) {
3755 ring_freq = mult_frac(gpu_freq, 5, 4);
3756 ring_freq = max(min_ring_freq, ring_freq);
3757 /* leave ia_freq as the default, chosen by cpufreq */
3759 /* On older processors, there is no separate ring
3760 * clock domain, so in order to boost the bandwidth
3761 * of the ring, we need to upclock the CPU (ia_freq).
3763 * For GPU frequencies less than 750MHz,
3764 * just use the lowest ring freq.
3766 if (gpu_freq < min_freq)
3769 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3770 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3773 sandybridge_pcode_write(dev_priv,
3774 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3775 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3776 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3781 void gen6_update_ring_freq(struct drm_device *dev)
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3785 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3788 mutex_lock(&dev_priv->rps.hw_lock);
3789 __gen6_update_ring_freq(dev);
3790 mutex_unlock(&dev_priv->rps.hw_lock);
3793 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
3797 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3798 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3803 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3807 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3808 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3813 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
3817 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3818 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3823 static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
3827 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3828 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3832 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
3836 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3838 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
3843 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3847 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3849 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3851 rp0 = min_t(u32, rp0, 0xea);
3856 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3860 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3861 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3862 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3863 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3868 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3870 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3873 /* Check that the pctx buffer wasn't move under us. */
3874 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3876 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3878 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3879 dev_priv->vlv_pctx->stolen->start);
3883 /* Check that the pcbr address is not empty. */
3884 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
3886 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3888 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
3891 static void cherryview_setup_pctx(struct drm_device *dev)
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 unsigned long pctx_paddr, paddr;
3895 struct i915_gtt *gtt = &dev_priv->gtt;
3897 int pctx_size = 32*1024;
3899 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3901 pcbr = I915_READ(VLV_PCBR);
3902 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
3903 paddr = (dev_priv->mm.stolen_base +
3904 (gtt->stolen_size - pctx_size));
3906 pctx_paddr = (paddr & (~4095));
3907 I915_WRITE(VLV_PCBR, pctx_paddr);
3911 static void valleyview_setup_pctx(struct drm_device *dev)
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 struct drm_i915_gem_object *pctx;
3915 unsigned long pctx_paddr;
3917 int pctx_size = 24*1024;
3919 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3921 pcbr = I915_READ(VLV_PCBR);
3923 /* BIOS set it up already, grab the pre-alloc'd space */
3926 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3927 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3929 I915_GTT_OFFSET_NONE,
3935 * From the Gunit register HAS:
3936 * The Gfx driver is expected to program this register and ensure
3937 * proper allocation within Gfx stolen memory. For example, this
3938 * register should be programmed such than the PCBR range does not
3939 * overlap with other ranges, such as the frame buffer, protected
3940 * memory, or any other relevant ranges.
3942 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3944 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3948 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3949 I915_WRITE(VLV_PCBR, pctx_paddr);
3952 dev_priv->vlv_pctx = pctx;
3955 static void valleyview_cleanup_pctx(struct drm_device *dev)
3957 struct drm_i915_private *dev_priv = dev->dev_private;
3959 if (WARN_ON(!dev_priv->vlv_pctx))
3962 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3963 dev_priv->vlv_pctx = NULL;
3966 static void valleyview_init_gt_powersave(struct drm_device *dev)
3968 struct drm_i915_private *dev_priv = dev->dev_private;
3970 valleyview_setup_pctx(dev);
3972 mutex_lock(&dev_priv->rps.hw_lock);
3974 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3975 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3976 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3977 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3978 dev_priv->rps.max_freq);
3980 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3981 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3982 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3983 dev_priv->rps.efficient_freq);
3985 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
3986 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
3987 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
3988 dev_priv->rps.rp1_freq);
3990 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3991 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3992 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3993 dev_priv->rps.min_freq);
3995 /* Preserve min/max settings in case of re-init */
3996 if (dev_priv->rps.max_freq_softlimit == 0)
3997 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3999 if (dev_priv->rps.min_freq_softlimit == 0)
4000 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4002 mutex_unlock(&dev_priv->rps.hw_lock);
4005 static void cherryview_init_gt_powersave(struct drm_device *dev)
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4009 cherryview_setup_pctx(dev);
4011 mutex_lock(&dev_priv->rps.hw_lock);
4013 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4014 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4015 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4016 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4017 dev_priv->rps.max_freq);
4019 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4020 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4021 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4022 dev_priv->rps.efficient_freq);
4024 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4025 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4026 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4027 dev_priv->rps.rp1_freq);
4029 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4030 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4031 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4032 dev_priv->rps.min_freq);
4034 /* Preserve min/max settings in case of re-init */
4035 if (dev_priv->rps.max_freq_softlimit == 0)
4036 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4038 if (dev_priv->rps.min_freq_softlimit == 0)
4039 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4041 mutex_unlock(&dev_priv->rps.hw_lock);
4044 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4046 valleyview_cleanup_pctx(dev);
4049 static void cherryview_enable_rps(struct drm_device *dev)
4051 struct drm_i915_private *dev_priv = dev->dev_private;
4052 struct intel_engine_cs *ring;
4053 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
4056 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4058 gtfifodbg = I915_READ(GTFIFODBG);
4060 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4062 I915_WRITE(GTFIFODBG, gtfifodbg);
4065 cherryview_check_pctx(dev_priv);
4067 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4068 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4069 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4071 /* 2a: Program RC6 thresholds.*/
4072 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4073 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4074 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4076 for_each_ring(ring, dev_priv, i)
4077 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4078 I915_WRITE(GEN6_RC_SLEEP, 0);
4080 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4082 /* allows RC6 residency counter to work */
4083 I915_WRITE(VLV_COUNTER_CONTROL,
4084 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4085 VLV_MEDIA_RC6_COUNT_EN |
4086 VLV_RENDER_RC6_COUNT_EN));
4088 /* For now we assume BIOS is allocating and populating the PCBR */
4089 pcbr = I915_READ(VLV_PCBR);
4091 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4094 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4095 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4096 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4098 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4100 /* 4 Program defaults and thresholds for RPS*/
4101 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4102 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4103 I915_WRITE(GEN6_RP_UP_EI, 66000);
4104 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4106 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4108 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4109 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4110 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4113 I915_WRITE(GEN6_RP_CONTROL,
4114 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4115 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4117 GEN6_RP_UP_BUSY_AVG |
4118 GEN6_RP_DOWN_IDLE_AVG);
4120 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4122 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4123 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4125 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4126 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4127 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4128 dev_priv->rps.cur_freq);
4130 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4131 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4132 dev_priv->rps.efficient_freq);
4134 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4136 gen8_enable_rps_interrupts(dev);
4138 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4141 static void valleyview_enable_rps(struct drm_device *dev)
4143 struct drm_i915_private *dev_priv = dev->dev_private;
4144 struct intel_engine_cs *ring;
4145 u32 gtfifodbg, val, rc6_mode = 0;
4148 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4150 valleyview_check_pctx(dev_priv);
4152 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4153 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4155 I915_WRITE(GTFIFODBG, gtfifodbg);
4158 /* If VLV, Forcewake all wells, else re-direct to regular path */
4159 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4161 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4162 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4163 I915_WRITE(GEN6_RP_UP_EI, 66000);
4164 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4166 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4167 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4169 I915_WRITE(GEN6_RP_CONTROL,
4170 GEN6_RP_MEDIA_TURBO |
4171 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4172 GEN6_RP_MEDIA_IS_GFX |
4174 GEN6_RP_UP_BUSY_AVG |
4175 GEN6_RP_DOWN_IDLE_CONT);
4177 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4178 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4179 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4181 for_each_ring(ring, dev_priv, i)
4182 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4184 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4186 /* allows RC6 residency counter to work */
4187 I915_WRITE(VLV_COUNTER_CONTROL,
4188 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4189 VLV_RENDER_RC0_COUNT_EN |
4190 VLV_MEDIA_RC6_COUNT_EN |
4191 VLV_RENDER_RC6_COUNT_EN));
4193 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4194 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4196 intel_print_rc6_info(dev, rc6_mode);
4198 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4200 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4202 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4203 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4205 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4206 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4207 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4208 dev_priv->rps.cur_freq);
4210 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4211 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4212 dev_priv->rps.efficient_freq);
4214 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4216 gen6_enable_rps_interrupts(dev);
4218 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4221 void ironlake_teardown_rc6(struct drm_device *dev)
4223 struct drm_i915_private *dev_priv = dev->dev_private;
4225 if (dev_priv->ips.renderctx) {
4226 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
4227 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4228 dev_priv->ips.renderctx = NULL;
4231 if (dev_priv->ips.pwrctx) {
4232 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
4233 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4234 dev_priv->ips.pwrctx = NULL;
4238 static void ironlake_disable_rc6(struct drm_device *dev)
4240 struct drm_i915_private *dev_priv = dev->dev_private;
4242 if (I915_READ(PWRCTXA)) {
4243 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4244 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4245 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4248 I915_WRITE(PWRCTXA, 0);
4249 POSTING_READ(PWRCTXA);
4251 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4252 POSTING_READ(RSTDBYCTL);
4256 static int ironlake_setup_rc6(struct drm_device *dev)
4258 struct drm_i915_private *dev_priv = dev->dev_private;
4260 if (dev_priv->ips.renderctx == NULL)
4261 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4262 if (!dev_priv->ips.renderctx)
4265 if (dev_priv->ips.pwrctx == NULL)
4266 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4267 if (!dev_priv->ips.pwrctx) {
4268 ironlake_teardown_rc6(dev);
4275 static void ironlake_enable_rc6(struct drm_device *dev)
4277 struct drm_i915_private *dev_priv = dev->dev_private;
4278 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4279 bool was_interruptible;
4282 /* rc6 disabled by default due to repeated reports of hanging during
4285 if (!intel_enable_rc6(dev))
4288 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4290 ret = ironlake_setup_rc6(dev);
4294 was_interruptible = dev_priv->mm.interruptible;
4295 dev_priv->mm.interruptible = false;
4298 * GPU can automatically power down the render unit if given a page
4301 ret = intel_ring_begin(ring, 6);
4303 ironlake_teardown_rc6(dev);
4304 dev_priv->mm.interruptible = was_interruptible;
4308 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4309 intel_ring_emit(ring, MI_SET_CONTEXT);
4310 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4312 MI_SAVE_EXT_STATE_EN |
4313 MI_RESTORE_EXT_STATE_EN |
4314 MI_RESTORE_INHIBIT);
4315 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4316 intel_ring_emit(ring, MI_NOOP);
4317 intel_ring_emit(ring, MI_FLUSH);
4318 intel_ring_advance(ring);
4321 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4322 * does an implicit flush, combined with MI_FLUSH above, it should be
4323 * safe to assume that renderctx is valid
4325 ret = intel_ring_idle(ring);
4326 dev_priv->mm.interruptible = was_interruptible;
4328 DRM_ERROR("failed to enable ironlake power savings\n");
4329 ironlake_teardown_rc6(dev);
4333 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4334 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4336 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4339 static unsigned long intel_pxfreq(u32 vidfreq)
4342 int div = (vidfreq & 0x3f0000) >> 16;
4343 int post = (vidfreq & 0x3000) >> 12;
4344 int pre = (vidfreq & 0x7);
4349 freq = ((div * 133333) / ((1<<post) * pre));
4354 static const struct cparams {
4360 { 1, 1333, 301, 28664 },
4361 { 1, 1066, 294, 24460 },
4362 { 1, 800, 294, 25192 },
4363 { 0, 1333, 276, 27605 },
4364 { 0, 1066, 276, 27605 },
4365 { 0, 800, 231, 23784 },
4368 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4370 u64 total_count, diff, ret;
4371 u32 count1, count2, count3, m = 0, c = 0;
4372 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4375 assert_spin_locked(&mchdev_lock);
4377 diff1 = now - dev_priv->ips.last_time1;
4379 /* Prevent division-by-zero if we are asking too fast.
4380 * Also, we don't get interesting results if we are polling
4381 * faster than once in 10ms, so just return the saved value
4385 return dev_priv->ips.chipset_power;
4387 count1 = I915_READ(DMIEC);
4388 count2 = I915_READ(DDREC);
4389 count3 = I915_READ(CSIEC);
4391 total_count = count1 + count2 + count3;
4393 /* FIXME: handle per-counter overflow */
4394 if (total_count < dev_priv->ips.last_count1) {
4395 diff = ~0UL - dev_priv->ips.last_count1;
4396 diff += total_count;
4398 diff = total_count - dev_priv->ips.last_count1;
4401 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4402 if (cparams[i].i == dev_priv->ips.c_m &&
4403 cparams[i].t == dev_priv->ips.r_t) {
4410 diff = div_u64(diff, diff1);
4411 ret = ((m * diff) + c);
4412 ret = div_u64(ret, 10);
4414 dev_priv->ips.last_count1 = total_count;
4415 dev_priv->ips.last_time1 = now;
4417 dev_priv->ips.chipset_power = ret;
4422 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4424 struct drm_device *dev = dev_priv->dev;
4427 if (INTEL_INFO(dev)->gen != 5)
4430 spin_lock_irq(&mchdev_lock);
4432 val = __i915_chipset_val(dev_priv);
4434 spin_unlock_irq(&mchdev_lock);
4439 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4441 unsigned long m, x, b;
4444 tsfs = I915_READ(TSFS);
4446 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4447 x = I915_READ8(TR1);
4449 b = tsfs & TSFS_INTR_MASK;
4451 return ((m * x) / 127) - b;
4454 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4456 struct drm_device *dev = dev_priv->dev;
4457 static const struct v_table {
4458 u16 vd; /* in .1 mil */
4459 u16 vm; /* in .1 mil */
4590 if (INTEL_INFO(dev)->is_mobile)
4591 return v_table[pxvid].vm;
4593 return v_table[pxvid].vd;
4596 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4598 struct timespec now, diff1;
4600 unsigned long diffms;
4603 assert_spin_locked(&mchdev_lock);
4605 getrawmonotonic(&now);
4606 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4608 /* Don't divide by 0 */
4609 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4613 count = I915_READ(GFXEC);
4615 if (count < dev_priv->ips.last_count2) {
4616 diff = ~0UL - dev_priv->ips.last_count2;
4619 diff = count - dev_priv->ips.last_count2;
4622 dev_priv->ips.last_count2 = count;
4623 dev_priv->ips.last_time2 = now;
4625 /* More magic constants... */
4627 diff = div_u64(diff, diffms * 10);
4628 dev_priv->ips.gfx_power = diff;
4631 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4633 struct drm_device *dev = dev_priv->dev;
4635 if (INTEL_INFO(dev)->gen != 5)
4638 spin_lock_irq(&mchdev_lock);
4640 __i915_update_gfx_val(dev_priv);
4642 spin_unlock_irq(&mchdev_lock);
4645 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4647 unsigned long t, corr, state1, corr2, state2;
4650 assert_spin_locked(&mchdev_lock);
4652 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4653 pxvid = (pxvid >> 24) & 0x7f;
4654 ext_v = pvid_to_extvid(dev_priv, pxvid);
4658 t = i915_mch_val(dev_priv);
4660 /* Revel in the empirically derived constants */
4662 /* Correction factor in 1/100000 units */
4664 corr = ((t * 2349) + 135940);
4666 corr = ((t * 964) + 29317);
4668 corr = ((t * 301) + 1004);
4670 corr = corr * ((150142 * state1) / 10000 - 78642);
4672 corr2 = (corr * dev_priv->ips.corr);
4674 state2 = (corr2 * state1) / 10000;
4675 state2 /= 100; /* convert to mW */
4677 __i915_update_gfx_val(dev_priv);
4679 return dev_priv->ips.gfx_power + state2;
4682 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4684 struct drm_device *dev = dev_priv->dev;
4687 if (INTEL_INFO(dev)->gen != 5)
4690 spin_lock_irq(&mchdev_lock);
4692 val = __i915_gfx_val(dev_priv);
4694 spin_unlock_irq(&mchdev_lock);
4700 * i915_read_mch_val - return value for IPS use
4702 * Calculate and return a value for the IPS driver to use when deciding whether
4703 * we have thermal and power headroom to increase CPU or GPU power budget.
4705 unsigned long i915_read_mch_val(void)
4707 struct drm_i915_private *dev_priv;
4708 unsigned long chipset_val, graphics_val, ret = 0;
4710 spin_lock_irq(&mchdev_lock);
4713 dev_priv = i915_mch_dev;
4715 chipset_val = __i915_chipset_val(dev_priv);
4716 graphics_val = __i915_gfx_val(dev_priv);
4718 ret = chipset_val + graphics_val;
4721 spin_unlock_irq(&mchdev_lock);
4725 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4728 * i915_gpu_raise - raise GPU frequency limit
4730 * Raise the limit; IPS indicates we have thermal headroom.
4732 bool i915_gpu_raise(void)
4734 struct drm_i915_private *dev_priv;
4737 spin_lock_irq(&mchdev_lock);
4738 if (!i915_mch_dev) {
4742 dev_priv = i915_mch_dev;
4744 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4745 dev_priv->ips.max_delay--;
4748 spin_unlock_irq(&mchdev_lock);
4752 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4755 * i915_gpu_lower - lower GPU frequency limit
4757 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4758 * frequency maximum.
4760 bool i915_gpu_lower(void)
4762 struct drm_i915_private *dev_priv;
4765 spin_lock_irq(&mchdev_lock);
4766 if (!i915_mch_dev) {
4770 dev_priv = i915_mch_dev;
4772 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4773 dev_priv->ips.max_delay++;
4776 spin_unlock_irq(&mchdev_lock);
4780 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4783 * i915_gpu_busy - indicate GPU business to IPS
4785 * Tell the IPS driver whether or not the GPU is busy.
4787 bool i915_gpu_busy(void)
4789 struct drm_i915_private *dev_priv;
4790 struct intel_engine_cs *ring;
4794 spin_lock_irq(&mchdev_lock);
4797 dev_priv = i915_mch_dev;
4799 for_each_ring(ring, dev_priv, i)
4800 ret |= !list_empty(&ring->request_list);
4803 spin_unlock_irq(&mchdev_lock);
4807 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4810 * i915_gpu_turbo_disable - disable graphics turbo
4812 * Disable graphics turbo by resetting the max frequency and setting the
4813 * current frequency to the default.
4815 bool i915_gpu_turbo_disable(void)
4817 struct drm_i915_private *dev_priv;
4820 spin_lock_irq(&mchdev_lock);
4821 if (!i915_mch_dev) {
4825 dev_priv = i915_mch_dev;
4827 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4829 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4833 spin_unlock_irq(&mchdev_lock);
4837 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4840 * Tells the intel_ips driver that the i915 driver is now loaded, if
4841 * IPS got loaded first.
4843 * This awkward dance is so that neither module has to depend on the
4844 * other in order for IPS to do the appropriate communication of
4845 * GPU turbo limits to i915.
4848 ips_ping_for_i915_load(void)
4852 link = symbol_get(ips_link_to_i915_driver);
4855 symbol_put(ips_link_to_i915_driver);
4859 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4861 /* We only register the i915 ips part with intel-ips once everything is
4862 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4863 spin_lock_irq(&mchdev_lock);
4864 i915_mch_dev = dev_priv;
4865 spin_unlock_irq(&mchdev_lock);
4867 ips_ping_for_i915_load();
4870 void intel_gpu_ips_teardown(void)
4872 spin_lock_irq(&mchdev_lock);
4873 i915_mch_dev = NULL;
4874 spin_unlock_irq(&mchdev_lock);
4877 static void intel_init_emon(struct drm_device *dev)
4879 struct drm_i915_private *dev_priv = dev->dev_private;
4884 /* Disable to program */
4888 /* Program energy weights for various events */
4889 I915_WRITE(SDEW, 0x15040d00);
4890 I915_WRITE(CSIEW0, 0x007f0000);
4891 I915_WRITE(CSIEW1, 0x1e220004);
4892 I915_WRITE(CSIEW2, 0x04000004);
4894 for (i = 0; i < 5; i++)
4895 I915_WRITE(PEW + (i * 4), 0);
4896 for (i = 0; i < 3; i++)
4897 I915_WRITE(DEW + (i * 4), 0);
4899 /* Program P-state weights to account for frequency power adjustment */
4900 for (i = 0; i < 16; i++) {
4901 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4902 unsigned long freq = intel_pxfreq(pxvidfreq);
4903 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4908 val *= (freq / 1000);
4910 val /= (127*127*900);
4912 DRM_ERROR("bad pxval: %ld\n", val);
4915 /* Render standby states get 0 weight */
4919 for (i = 0; i < 4; i++) {
4920 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4921 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4922 I915_WRITE(PXW + (i * 4), val);
4925 /* Adjust magic regs to magic values (more experimental results) */
4926 I915_WRITE(OGW0, 0);
4927 I915_WRITE(OGW1, 0);
4928 I915_WRITE(EG0, 0x00007f00);
4929 I915_WRITE(EG1, 0x0000000e);
4930 I915_WRITE(EG2, 0x000e0000);
4931 I915_WRITE(EG3, 0x68000300);
4932 I915_WRITE(EG4, 0x42000000);
4933 I915_WRITE(EG5, 0x00140031);
4937 for (i = 0; i < 8; i++)
4938 I915_WRITE(PXWL + (i * 4), 0);
4940 /* Enable PMON + select events */
4941 I915_WRITE(ECR, 0x80000019);
4943 lcfuse = I915_READ(LCFUSE02);
4945 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4948 void intel_init_gt_powersave(struct drm_device *dev)
4950 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4952 if (IS_CHERRYVIEW(dev))
4953 cherryview_init_gt_powersave(dev);
4954 else if (IS_VALLEYVIEW(dev))
4955 valleyview_init_gt_powersave(dev);
4958 void intel_cleanup_gt_powersave(struct drm_device *dev)
4960 if (IS_CHERRYVIEW(dev))
4962 else if (IS_VALLEYVIEW(dev))
4963 valleyview_cleanup_gt_powersave(dev);
4967 * intel_suspend_gt_powersave - suspend PM work and helper threads
4970 * We don't want to disable RC6 or other features here, we just want
4971 * to make sure any work we've queued has finished and won't bother
4972 * us while we're suspended.
4974 void intel_suspend_gt_powersave(struct drm_device *dev)
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4978 /* Interrupts should be disabled already to avoid re-arming. */
4979 WARN_ON(intel_irqs_enabled(dev_priv));
4981 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4983 cancel_work_sync(&dev_priv->rps.work);
4985 /* Force GPU to min freq during suspend */
4986 gen6_rps_idle(dev_priv);
4989 void intel_disable_gt_powersave(struct drm_device *dev)
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4993 /* Interrupts should be disabled already to avoid re-arming. */
4994 WARN_ON(intel_irqs_enabled(dev_priv));
4996 if (IS_IRONLAKE_M(dev)) {
4997 ironlake_disable_drps(dev);
4998 ironlake_disable_rc6(dev);
4999 } else if (INTEL_INFO(dev)->gen >= 6) {
5000 intel_suspend_gt_powersave(dev);
5002 mutex_lock(&dev_priv->rps.hw_lock);
5003 if (IS_CHERRYVIEW(dev))
5004 cherryview_disable_rps(dev);
5005 else if (IS_VALLEYVIEW(dev))
5006 valleyview_disable_rps(dev);
5008 gen6_disable_rps(dev);
5009 dev_priv->rps.enabled = false;
5010 mutex_unlock(&dev_priv->rps.hw_lock);
5014 static void intel_gen6_powersave_work(struct work_struct *work)
5016 struct drm_i915_private *dev_priv =
5017 container_of(work, struct drm_i915_private,
5018 rps.delayed_resume_work.work);
5019 struct drm_device *dev = dev_priv->dev;
5021 mutex_lock(&dev_priv->rps.hw_lock);
5023 if (IS_CHERRYVIEW(dev)) {
5024 cherryview_enable_rps(dev);
5025 } else if (IS_VALLEYVIEW(dev)) {
5026 valleyview_enable_rps(dev);
5027 } else if (IS_BROADWELL(dev)) {
5028 gen8_enable_rps(dev);
5029 __gen6_update_ring_freq(dev);
5031 gen6_enable_rps(dev);
5032 __gen6_update_ring_freq(dev);
5034 dev_priv->rps.enabled = true;
5035 mutex_unlock(&dev_priv->rps.hw_lock);
5037 intel_runtime_pm_put(dev_priv);
5040 void intel_enable_gt_powersave(struct drm_device *dev)
5042 struct drm_i915_private *dev_priv = dev->dev_private;
5044 if (IS_IRONLAKE_M(dev)) {
5045 mutex_lock(&dev->struct_mutex);
5046 ironlake_enable_drps(dev);
5047 ironlake_enable_rc6(dev);
5048 intel_init_emon(dev);
5049 mutex_unlock(&dev->struct_mutex);
5050 } else if (INTEL_INFO(dev)->gen >= 6) {
5052 * PCU communication is slow and this doesn't need to be
5053 * done at any specific time, so do this out of our fast path
5054 * to make resume and init faster.
5056 * We depend on the HW RC6 power context save/restore
5057 * mechanism when entering D3 through runtime PM suspend. So
5058 * disable RPM until RPS/RC6 is properly setup. We can only
5059 * get here via the driver load/system resume/runtime resume
5060 * paths, so the _noresume version is enough (and in case of
5061 * runtime resume it's necessary).
5063 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5064 round_jiffies_up_relative(HZ)))
5065 intel_runtime_pm_get_noresume(dev_priv);
5069 void intel_reset_gt_powersave(struct drm_device *dev)
5071 struct drm_i915_private *dev_priv = dev->dev_private;
5073 dev_priv->rps.enabled = false;
5074 intel_enable_gt_powersave(dev);
5077 static void ibx_init_clock_gating(struct drm_device *dev)
5079 struct drm_i915_private *dev_priv = dev->dev_private;
5082 * On Ibex Peak and Cougar Point, we need to disable clock
5083 * gating for the panel power sequencer or it will fail to
5084 * start up when no ports are active.
5086 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5089 static void g4x_disable_trickle_feed(struct drm_device *dev)
5091 struct drm_i915_private *dev_priv = dev->dev_private;
5094 for_each_pipe(pipe) {
5095 I915_WRITE(DSPCNTR(pipe),
5096 I915_READ(DSPCNTR(pipe)) |
5097 DISPPLANE_TRICKLE_FEED_DISABLE);
5098 intel_flush_primary_plane(dev_priv, pipe);
5102 static void ilk_init_lp_watermarks(struct drm_device *dev)
5104 struct drm_i915_private *dev_priv = dev->dev_private;
5106 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5107 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5108 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5111 * Don't touch WM1S_LP_EN here.
5112 * Doing so could cause underruns.
5116 static void ironlake_init_clock_gating(struct drm_device *dev)
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5119 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5123 * WaFbcDisableDpfcClockGating:ilk
5125 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5126 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5127 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5129 I915_WRITE(PCH_3DCGDIS0,
5130 MARIUNIT_CLOCK_GATE_DISABLE |
5131 SVSMUNIT_CLOCK_GATE_DISABLE);
5132 I915_WRITE(PCH_3DCGDIS1,
5133 VFMUNIT_CLOCK_GATE_DISABLE);
5136 * According to the spec the following bits should be set in
5137 * order to enable memory self-refresh
5138 * The bit 22/21 of 0x42004
5139 * The bit 5 of 0x42020
5140 * The bit 15 of 0x45000
5142 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5143 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5144 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5145 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5146 I915_WRITE(DISP_ARB_CTL,
5147 (I915_READ(DISP_ARB_CTL) |
5150 ilk_init_lp_watermarks(dev);
5153 * Based on the document from hardware guys the following bits
5154 * should be set unconditionally in order to enable FBC.
5155 * The bit 22 of 0x42000
5156 * The bit 22 of 0x42004
5157 * The bit 7,8,9 of 0x42020.
5159 if (IS_IRONLAKE_M(dev)) {
5160 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5161 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5162 I915_READ(ILK_DISPLAY_CHICKEN1) |
5164 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5165 I915_READ(ILK_DISPLAY_CHICKEN2) |
5169 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5171 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5172 I915_READ(ILK_DISPLAY_CHICKEN2) |
5173 ILK_ELPIN_409_SELECT);
5174 I915_WRITE(_3D_CHICKEN2,
5175 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5176 _3D_CHICKEN2_WM_READ_PIPELINED);
5178 /* WaDisableRenderCachePipelinedFlush:ilk */
5179 I915_WRITE(CACHE_MODE_0,
5180 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5182 /* WaDisable_RenderCache_OperationalFlush:ilk */
5183 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5185 g4x_disable_trickle_feed(dev);
5187 ibx_init_clock_gating(dev);
5190 static void cpt_init_clock_gating(struct drm_device *dev)
5192 struct drm_i915_private *dev_priv = dev->dev_private;
5197 * On Ibex Peak and Cougar Point, we need to disable clock
5198 * gating for the panel power sequencer or it will fail to
5199 * start up when no ports are active.
5201 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5202 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5203 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5204 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5205 DPLS_EDP_PPS_FIX_DIS);
5206 /* The below fixes the weird display corruption, a few pixels shifted
5207 * downward, on (only) LVDS of some HP laptops with IVY.
5209 for_each_pipe(pipe) {
5210 val = I915_READ(TRANS_CHICKEN2(pipe));
5211 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5212 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5213 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5214 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5215 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5216 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5217 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5218 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5220 /* WADP0ClockGatingDisable */
5221 for_each_pipe(pipe) {
5222 I915_WRITE(TRANS_CHICKEN1(pipe),
5223 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5227 static void gen6_check_mch_setup(struct drm_device *dev)
5229 struct drm_i915_private *dev_priv = dev->dev_private;
5232 tmp = I915_READ(MCH_SSKPD);
5233 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5234 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5238 static void gen6_init_clock_gating(struct drm_device *dev)
5240 struct drm_i915_private *dev_priv = dev->dev_private;
5241 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5243 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5245 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5246 I915_READ(ILK_DISPLAY_CHICKEN2) |
5247 ILK_ELPIN_409_SELECT);
5249 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5250 I915_WRITE(_3D_CHICKEN,
5251 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5253 /* WaSetupGtModeTdRowDispatch:snb */
5254 if (IS_SNB_GT1(dev))
5255 I915_WRITE(GEN6_GT_MODE,
5256 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5258 /* WaDisable_RenderCache_OperationalFlush:snb */
5259 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5262 * BSpec recoomends 8x4 when MSAA is used,
5263 * however in practice 16x4 seems fastest.
5265 * Note that PS/WM thread counts depend on the WIZ hashing
5266 * disable bit, which we don't touch here, but it's good
5267 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5269 I915_WRITE(GEN6_GT_MODE,
5270 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5272 ilk_init_lp_watermarks(dev);
5274 I915_WRITE(CACHE_MODE_0,
5275 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5277 I915_WRITE(GEN6_UCGCTL1,
5278 I915_READ(GEN6_UCGCTL1) |
5279 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5280 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5282 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5283 * gating disable must be set. Failure to set it results in
5284 * flickering pixels due to Z write ordering failures after
5285 * some amount of runtime in the Mesa "fire" demo, and Unigine
5286 * Sanctuary and Tropics, and apparently anything else with
5287 * alpha test or pixel discard.
5289 * According to the spec, bit 11 (RCCUNIT) must also be set,
5290 * but we didn't debug actual testcases to find it out.
5292 * WaDisableRCCUnitClockGating:snb
5293 * WaDisableRCPBUnitClockGating:snb
5295 I915_WRITE(GEN6_UCGCTL2,
5296 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5297 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5299 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5300 I915_WRITE(_3D_CHICKEN3,
5301 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5305 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5306 * 3DSTATE_SF number of SF output attributes is more than 16."
5308 I915_WRITE(_3D_CHICKEN3,
5309 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5312 * According to the spec the following bits should be
5313 * set in order to enable memory self-refresh and fbc:
5314 * The bit21 and bit22 of 0x42000
5315 * The bit21 and bit22 of 0x42004
5316 * The bit5 and bit7 of 0x42020
5317 * The bit14 of 0x70180
5318 * The bit14 of 0x71180
5320 * WaFbcAsynchFlipDisableFbcQueue:snb
5322 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5323 I915_READ(ILK_DISPLAY_CHICKEN1) |
5324 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5325 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5326 I915_READ(ILK_DISPLAY_CHICKEN2) |
5327 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5328 I915_WRITE(ILK_DSPCLK_GATE_D,
5329 I915_READ(ILK_DSPCLK_GATE_D) |
5330 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5331 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5333 g4x_disable_trickle_feed(dev);
5335 cpt_init_clock_gating(dev);
5337 gen6_check_mch_setup(dev);
5340 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5342 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5345 * WaVSThreadDispatchOverride:ivb,vlv
5347 * This actually overrides the dispatch
5348 * mode for all thread types.
5350 reg &= ~GEN7_FF_SCHED_MASK;
5351 reg |= GEN7_FF_TS_SCHED_HW;
5352 reg |= GEN7_FF_VS_SCHED_HW;
5353 reg |= GEN7_FF_DS_SCHED_HW;
5355 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5358 static void lpt_init_clock_gating(struct drm_device *dev)
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5363 * TODO: this bit should only be enabled when really needed, then
5364 * disabled when not needed anymore in order to save power.
5366 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5367 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5368 I915_READ(SOUTH_DSPCLK_GATE_D) |
5369 PCH_LP_PARTITION_LEVEL_DISABLE);
5371 /* WADPOClockGatingDisable:hsw */
5372 I915_WRITE(_TRANSA_CHICKEN1,
5373 I915_READ(_TRANSA_CHICKEN1) |
5374 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5377 static void lpt_suspend_hw(struct drm_device *dev)
5379 struct drm_i915_private *dev_priv = dev->dev_private;
5381 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5382 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5384 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5385 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5389 static void gen8_init_clock_gating(struct drm_device *dev)
5391 struct drm_i915_private *dev_priv = dev->dev_private;
5394 I915_WRITE(WM3_LP_ILK, 0);
5395 I915_WRITE(WM2_LP_ILK, 0);
5396 I915_WRITE(WM1_LP_ILK, 0);
5398 /* FIXME(BDW): Check all the w/a, some might only apply to
5399 * pre-production hw. */
5401 /* WaDisablePartialInstShootdown:bdw */
5402 I915_WRITE(GEN8_ROW_CHICKEN,
5403 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5405 /* WaDisableThreadStallDopClockGating:bdw */
5406 /* FIXME: Unclear whether we really need this on production bdw. */
5407 I915_WRITE(GEN8_ROW_CHICKEN,
5408 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5411 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5412 * pre-production hardware
5414 I915_WRITE(HALF_SLICE_CHICKEN3,
5415 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5416 I915_WRITE(HALF_SLICE_CHICKEN3,
5417 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5418 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5420 I915_WRITE(_3D_CHICKEN3,
5421 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5423 I915_WRITE(COMMON_SLICE_CHICKEN2,
5424 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5426 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5427 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5429 /* WaDisableDopClockGating:bdw May not be needed for production */
5430 I915_WRITE(GEN7_ROW_CHICKEN2,
5431 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5433 /* WaSwitchSolVfFArbitrationPriority:bdw */
5434 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5436 /* WaPsrDPAMaskVBlankInSRD:bdw */
5437 I915_WRITE(CHICKEN_PAR1_1,
5438 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5440 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5441 for_each_pipe(pipe) {
5442 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5443 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5444 BDW_DPRS_MASK_VBLANK_SRD);
5447 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5448 * workaround for for a possible hang in the unlikely event a TLB
5449 * invalidation occurs during a PSD flush.
5451 I915_WRITE(HDC_CHICKEN0,
5452 I915_READ(HDC_CHICKEN0) |
5453 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5455 /* WaVSRefCountFullforceMissDisable:bdw */
5456 /* WaDSRefCountFullforceMissDisable:bdw */
5457 I915_WRITE(GEN7_FF_THREAD_MODE,
5458 I915_READ(GEN7_FF_THREAD_MODE) &
5459 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5462 * BSpec recommends 8x4 when MSAA is used,
5463 * however in practice 16x4 seems fastest.
5465 * Note that PS/WM thread counts depend on the WIZ hashing
5466 * disable bit, which we don't touch here, but it's good
5467 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5469 I915_WRITE(GEN7_GT_MODE,
5470 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5472 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5473 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5475 /* WaDisableSDEUnitClockGating:bdw */
5476 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5477 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5479 /* Wa4x4STCOptimizationDisable:bdw */
5480 I915_WRITE(CACHE_MODE_1,
5481 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5484 static void haswell_init_clock_gating(struct drm_device *dev)
5486 struct drm_i915_private *dev_priv = dev->dev_private;
5488 ilk_init_lp_watermarks(dev);
5490 /* L3 caching of data atomics doesn't work -- disable it. */
5491 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5492 I915_WRITE(HSW_ROW_CHICKEN3,
5493 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5495 /* This is required by WaCatErrorRejectionIssue:hsw */
5496 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5497 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5498 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5500 /* WaVSRefCountFullforceMissDisable:hsw */
5501 I915_WRITE(GEN7_FF_THREAD_MODE,
5502 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5504 /* WaDisable_RenderCache_OperationalFlush:hsw */
5505 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5507 /* enable HiZ Raw Stall Optimization */
5508 I915_WRITE(CACHE_MODE_0_GEN7,
5509 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5511 /* WaDisable4x2SubspanOptimization:hsw */
5512 I915_WRITE(CACHE_MODE_1,
5513 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5516 * BSpec recommends 8x4 when MSAA is used,
5517 * however in practice 16x4 seems fastest.
5519 * Note that PS/WM thread counts depend on the WIZ hashing
5520 * disable bit, which we don't touch here, but it's good
5521 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5523 I915_WRITE(GEN7_GT_MODE,
5524 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5526 /* WaSwitchSolVfFArbitrationPriority:hsw */
5527 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5529 /* WaRsPkgCStateDisplayPMReq:hsw */
5530 I915_WRITE(CHICKEN_PAR1_1,
5531 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5533 lpt_init_clock_gating(dev);
5536 static void ivybridge_init_clock_gating(struct drm_device *dev)
5538 struct drm_i915_private *dev_priv = dev->dev_private;
5541 ilk_init_lp_watermarks(dev);
5543 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5545 /* WaDisableEarlyCull:ivb */
5546 I915_WRITE(_3D_CHICKEN3,
5547 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5549 /* WaDisableBackToBackFlipFix:ivb */
5550 I915_WRITE(IVB_CHICKEN3,
5551 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5552 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5554 /* WaDisablePSDDualDispatchEnable:ivb */
5555 if (IS_IVB_GT1(dev))
5556 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5557 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5559 /* WaDisable_RenderCache_OperationalFlush:ivb */
5560 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5562 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5563 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5564 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5566 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5567 I915_WRITE(GEN7_L3CNTLREG1,
5568 GEN7_WA_FOR_GEN7_L3_CONTROL);
5569 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5570 GEN7_WA_L3_CHICKEN_MODE);
5571 if (IS_IVB_GT1(dev))
5572 I915_WRITE(GEN7_ROW_CHICKEN2,
5573 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5575 /* must write both registers */
5576 I915_WRITE(GEN7_ROW_CHICKEN2,
5577 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5578 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5579 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5582 /* WaForceL3Serialization:ivb */
5583 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5584 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5587 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5588 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5590 I915_WRITE(GEN6_UCGCTL2,
5591 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5593 /* This is required by WaCatErrorRejectionIssue:ivb */
5594 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5595 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5596 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5598 g4x_disable_trickle_feed(dev);
5600 gen7_setup_fixed_func_scheduler(dev_priv);
5602 if (0) { /* causes HiZ corruption on ivb:gt1 */
5603 /* enable HiZ Raw Stall Optimization */
5604 I915_WRITE(CACHE_MODE_0_GEN7,
5605 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5608 /* WaDisable4x2SubspanOptimization:ivb */
5609 I915_WRITE(CACHE_MODE_1,
5610 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5613 * BSpec recommends 8x4 when MSAA is used,
5614 * however in practice 16x4 seems fastest.
5616 * Note that PS/WM thread counts depend on the WIZ hashing
5617 * disable bit, which we don't touch here, but it's good
5618 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5620 I915_WRITE(GEN7_GT_MODE,
5621 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5623 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5624 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5625 snpcr |= GEN6_MBC_SNPCR_MED;
5626 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5628 if (!HAS_PCH_NOP(dev))
5629 cpt_init_clock_gating(dev);
5631 gen6_check_mch_setup(dev);
5634 static void valleyview_init_clock_gating(struct drm_device *dev)
5636 struct drm_i915_private *dev_priv = dev->dev_private;
5639 mutex_lock(&dev_priv->rps.hw_lock);
5640 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5641 mutex_unlock(&dev_priv->rps.hw_lock);
5642 switch ((val >> 6) & 3) {
5645 dev_priv->mem_freq = 800;
5648 dev_priv->mem_freq = 1066;
5651 dev_priv->mem_freq = 1333;
5654 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5656 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5658 /* WaDisableEarlyCull:vlv */
5659 I915_WRITE(_3D_CHICKEN3,
5660 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5662 /* WaDisableBackToBackFlipFix:vlv */
5663 I915_WRITE(IVB_CHICKEN3,
5664 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5665 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5667 /* WaPsdDispatchEnable:vlv */
5668 /* WaDisablePSDDualDispatchEnable:vlv */
5669 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5670 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5671 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5673 /* WaDisable_RenderCache_OperationalFlush:vlv */
5674 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5676 /* WaForceL3Serialization:vlv */
5677 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5678 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5680 /* WaDisableDopClockGating:vlv */
5681 I915_WRITE(GEN7_ROW_CHICKEN2,
5682 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5684 /* This is required by WaCatErrorRejectionIssue:vlv */
5685 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5686 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5687 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5689 gen7_setup_fixed_func_scheduler(dev_priv);
5692 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5693 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5695 I915_WRITE(GEN6_UCGCTL2,
5696 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5698 /* WaDisableL3Bank2xClockGate:vlv
5699 * Disabling L3 clock gating- MMIO 940c[25] = 1
5700 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5701 I915_WRITE(GEN7_UCGCTL4,
5702 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5704 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5707 * BSpec says this must be set, even though
5708 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5710 I915_WRITE(CACHE_MODE_1,
5711 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5714 * WaIncreaseL3CreditsForVLVB0:vlv
5715 * This is the hardware default actually.
5717 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5720 * WaDisableVLVClockGating_VBIIssue:vlv
5721 * Disable clock gating on th GCFG unit to prevent a delay
5722 * in the reporting of vblank events.
5724 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5727 static void cherryview_init_clock_gating(struct drm_device *dev)
5729 struct drm_i915_private *dev_priv = dev->dev_private;
5732 mutex_lock(&dev_priv->rps.hw_lock);
5733 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5734 mutex_unlock(&dev_priv->rps.hw_lock);
5735 switch ((val >> 2) & 0x7) {
5738 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
5739 dev_priv->mem_freq = 1600;
5742 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
5743 dev_priv->mem_freq = 1600;
5746 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
5747 dev_priv->mem_freq = 2000;
5750 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
5751 dev_priv->mem_freq = 1600;
5754 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
5755 dev_priv->mem_freq = 1600;
5758 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5760 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5762 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5764 /* WaDisablePartialInstShootdown:chv */
5765 I915_WRITE(GEN8_ROW_CHICKEN,
5766 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5768 /* WaDisableThreadStallDopClockGating:chv */
5769 I915_WRITE(GEN8_ROW_CHICKEN,
5770 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5772 /* WaVSRefCountFullforceMissDisable:chv */
5773 /* WaDSRefCountFullforceMissDisable:chv */
5774 I915_WRITE(GEN7_FF_THREAD_MODE,
5775 I915_READ(GEN7_FF_THREAD_MODE) &
5776 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5778 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5779 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5780 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5782 /* WaDisableCSUnitClockGating:chv */
5783 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5784 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5786 /* WaDisableSDEUnitClockGating:chv */
5787 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5788 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5790 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5791 I915_WRITE(HALF_SLICE_CHICKEN3,
5792 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5794 /* WaDisableGunitClockGating:chv (pre-production hw) */
5795 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5798 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5799 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5800 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5802 /* WaDisableDopClockGating:chv (pre-production hw) */
5803 I915_WRITE(GEN7_ROW_CHICKEN2,
5804 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5805 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5806 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5809 static void g4x_init_clock_gating(struct drm_device *dev)
5811 struct drm_i915_private *dev_priv = dev->dev_private;
5812 uint32_t dspclk_gate;
5814 I915_WRITE(RENCLK_GATE_D1, 0);
5815 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5816 GS_UNIT_CLOCK_GATE_DISABLE |
5817 CL_UNIT_CLOCK_GATE_DISABLE);
5818 I915_WRITE(RAMCLK_GATE_D, 0);
5819 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5820 OVRUNIT_CLOCK_GATE_DISABLE |
5821 OVCUNIT_CLOCK_GATE_DISABLE;
5823 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5824 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5826 /* WaDisableRenderCachePipelinedFlush */
5827 I915_WRITE(CACHE_MODE_0,
5828 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5830 /* WaDisable_RenderCache_OperationalFlush:g4x */
5831 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5833 g4x_disable_trickle_feed(dev);
5836 static void crestline_init_clock_gating(struct drm_device *dev)
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5840 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5841 I915_WRITE(RENCLK_GATE_D2, 0);
5842 I915_WRITE(DSPCLK_GATE_D, 0);
5843 I915_WRITE(RAMCLK_GATE_D, 0);
5844 I915_WRITE16(DEUC, 0);
5845 I915_WRITE(MI_ARB_STATE,
5846 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5848 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5849 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5852 static void broadwater_init_clock_gating(struct drm_device *dev)
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5856 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5857 I965_RCC_CLOCK_GATE_DISABLE |
5858 I965_RCPB_CLOCK_GATE_DISABLE |
5859 I965_ISC_CLOCK_GATE_DISABLE |
5860 I965_FBC_CLOCK_GATE_DISABLE);
5861 I915_WRITE(RENCLK_GATE_D2, 0);
5862 I915_WRITE(MI_ARB_STATE,
5863 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5865 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5866 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5869 static void gen3_init_clock_gating(struct drm_device *dev)
5871 struct drm_i915_private *dev_priv = dev->dev_private;
5872 u32 dstate = I915_READ(D_STATE);
5874 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5875 DSTATE_DOT_CLOCK_GATING;
5876 I915_WRITE(D_STATE, dstate);
5878 if (IS_PINEVIEW(dev))
5879 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5881 /* IIR "flip pending" means done if this bit is set */
5882 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5884 /* interrupts should cause a wake up from C3 */
5885 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
5887 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5888 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5891 static void i85x_init_clock_gating(struct drm_device *dev)
5893 struct drm_i915_private *dev_priv = dev->dev_private;
5895 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5897 /* interrupts should cause a wake up from C3 */
5898 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5899 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
5902 static void i830_init_clock_gating(struct drm_device *dev)
5904 struct drm_i915_private *dev_priv = dev->dev_private;
5906 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5909 void intel_init_clock_gating(struct drm_device *dev)
5911 struct drm_i915_private *dev_priv = dev->dev_private;
5913 dev_priv->display.init_clock_gating(dev);
5916 void intel_suspend_hw(struct drm_device *dev)
5918 if (HAS_PCH_LPT(dev))
5919 lpt_suspend_hw(dev);
5922 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5924 i < (power_domains)->power_well_count && \
5925 ((power_well) = &(power_domains)->power_wells[i]); \
5927 if ((power_well)->domains & (domain_mask))
5929 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5930 for (i = (power_domains)->power_well_count - 1; \
5931 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5933 if ((power_well)->domains & (domain_mask))
5936 * We should only use the power well if we explicitly asked the hardware to
5937 * enable it, so check if it's enabled and also check if we've requested it to
5940 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5941 struct i915_power_well *power_well)
5943 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5944 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5947 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
5948 enum intel_display_power_domain domain)
5950 struct i915_power_domains *power_domains;
5951 struct i915_power_well *power_well;
5955 if (dev_priv->pm.suspended)
5958 power_domains = &dev_priv->power_domains;
5962 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5963 if (power_well->always_on)
5966 if (!power_well->hw_enabled) {
5975 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5976 enum intel_display_power_domain domain)
5978 struct i915_power_domains *power_domains;
5981 power_domains = &dev_priv->power_domains;
5983 mutex_lock(&power_domains->lock);
5984 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
5985 mutex_unlock(&power_domains->lock);
5991 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5992 * when not needed anymore. We have 4 registers that can request the power well
5993 * to be enabled, and it will only be disabled if none of the registers is
5994 * requesting it to be enabled.
5996 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5998 struct drm_device *dev = dev_priv->dev;
6001 * After we re-enable the power well, if we touch VGA register 0x3d5
6002 * we'll get unclaimed register interrupts. This stops after we write
6003 * anything to the VGA MSR register. The vgacon module uses this
6004 * register all the time, so if we unbind our driver and, as a
6005 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6006 * console_unlock(). So make here we touch the VGA MSR register, making
6007 * sure vgacon can keep working normally without triggering interrupts
6008 * and error messages.
6010 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6011 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6012 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6014 if (IS_BROADWELL(dev))
6015 gen8_irq_power_well_post_enable(dev_priv);
6018 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
6019 struct i915_power_well *power_well, bool enable)
6021 bool is_enabled, enable_requested;
6024 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6025 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6026 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
6029 if (!enable_requested)
6030 I915_WRITE(HSW_PWR_WELL_DRIVER,
6031 HSW_PWR_WELL_ENABLE_REQUEST);
6034 DRM_DEBUG_KMS("Enabling power well\n");
6035 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6036 HSW_PWR_WELL_STATE_ENABLED), 20))
6037 DRM_ERROR("Timeout enabling power well\n");
6040 hsw_power_well_post_enable(dev_priv);
6042 if (enable_requested) {
6043 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
6044 POSTING_READ(HSW_PWR_WELL_DRIVER);
6045 DRM_DEBUG_KMS("Requesting to disable the power well\n");
6050 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6051 struct i915_power_well *power_well)
6053 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6056 * We're taking over the BIOS, so clear any requests made by it since
6057 * the driver is in charge now.
6059 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6060 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6063 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6064 struct i915_power_well *power_well)
6066 hsw_set_power_well(dev_priv, power_well, true);
6069 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6070 struct i915_power_well *power_well)
6072 hsw_set_power_well(dev_priv, power_well, false);
6075 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6076 struct i915_power_well *power_well)
6080 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6081 struct i915_power_well *power_well)
6086 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6087 struct i915_power_well *power_well, bool enable)
6089 enum punit_power_well power_well_id = power_well->data;
6094 mask = PUNIT_PWRGT_MASK(power_well_id);
6095 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6096 PUNIT_PWRGT_PWR_GATE(power_well_id);
6098 mutex_lock(&dev_priv->rps.hw_lock);
6101 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6106 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6109 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6111 if (wait_for(COND, 100))
6112 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6114 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6119 mutex_unlock(&dev_priv->rps.hw_lock);
6122 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6123 struct i915_power_well *power_well)
6125 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6128 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6129 struct i915_power_well *power_well)
6131 vlv_set_power_well(dev_priv, power_well, true);
6134 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6135 struct i915_power_well *power_well)
6137 vlv_set_power_well(dev_priv, power_well, false);
6140 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6141 struct i915_power_well *power_well)
6143 int power_well_id = power_well->data;
6144 bool enabled = false;
6149 mask = PUNIT_PWRGT_MASK(power_well_id);
6150 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6152 mutex_lock(&dev_priv->rps.hw_lock);
6154 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6156 * We only ever set the power-on and power-gate states, anything
6157 * else is unexpected.
6159 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6160 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6165 * A transient state at this point would mean some unexpected party
6166 * is poking at the power controls too.
6168 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6169 WARN_ON(ctrl != state);
6171 mutex_unlock(&dev_priv->rps.hw_lock);
6176 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6177 struct i915_power_well *power_well)
6179 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6181 vlv_set_power_well(dev_priv, power_well, true);
6183 spin_lock_irq(&dev_priv->irq_lock);
6184 valleyview_enable_display_irqs(dev_priv);
6185 spin_unlock_irq(&dev_priv->irq_lock);
6188 * During driver initialization/resume we can avoid restoring the
6189 * part of the HW/SW state that will be inited anyway explicitly.
6191 if (dev_priv->power_domains.initializing)
6194 intel_hpd_init(dev_priv->dev);
6196 i915_redisable_vga_power_on(dev_priv->dev);
6199 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6200 struct i915_power_well *power_well)
6202 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6204 spin_lock_irq(&dev_priv->irq_lock);
6205 valleyview_disable_display_irqs(dev_priv);
6206 spin_unlock_irq(&dev_priv->irq_lock);
6208 vlv_set_power_well(dev_priv, power_well, false);
6211 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6212 struct i915_power_well *power_well)
6214 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6217 * Enable the CRI clock source so we can get at the
6218 * display and the reference clock for VGA
6219 * hotplug / manual detection.
6221 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6222 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6223 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6225 vlv_set_power_well(dev_priv, power_well, true);
6228 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6229 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6230 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6231 * b. The other bits such as sfr settings / modesel may all
6234 * This should only be done on init and resume from S3 with
6235 * both PLLs disabled, or we risk losing DPIO and PLL
6238 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6241 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6242 struct i915_power_well *power_well)
6244 struct drm_device *dev = dev_priv->dev;
6247 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6250 assert_pll_disabled(dev_priv, pipe);
6252 /* Assert common reset */
6253 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6255 vlv_set_power_well(dev_priv, power_well, false);
6258 static void check_power_well_state(struct drm_i915_private *dev_priv,
6259 struct i915_power_well *power_well)
6261 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6263 if (power_well->always_on || !i915.disable_power_well) {
6270 if (enabled != (power_well->count > 0))
6276 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6277 power_well->name, power_well->always_on, enabled,
6278 power_well->count, i915.disable_power_well);
6281 void intel_display_power_get(struct drm_i915_private *dev_priv,
6282 enum intel_display_power_domain domain)
6284 struct i915_power_domains *power_domains;
6285 struct i915_power_well *power_well;
6288 intel_runtime_pm_get(dev_priv);
6290 power_domains = &dev_priv->power_domains;
6292 mutex_lock(&power_domains->lock);
6294 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6295 if (!power_well->count++) {
6296 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6297 power_well->ops->enable(dev_priv, power_well);
6298 power_well->hw_enabled = true;
6301 check_power_well_state(dev_priv, power_well);
6304 power_domains->domain_use_count[domain]++;
6306 mutex_unlock(&power_domains->lock);
6309 void intel_display_power_put(struct drm_i915_private *dev_priv,
6310 enum intel_display_power_domain domain)
6312 struct i915_power_domains *power_domains;
6313 struct i915_power_well *power_well;
6316 power_domains = &dev_priv->power_domains;
6318 mutex_lock(&power_domains->lock);
6320 WARN_ON(!power_domains->domain_use_count[domain]);
6321 power_domains->domain_use_count[domain]--;
6323 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6324 WARN_ON(!power_well->count);
6326 if (!--power_well->count && i915.disable_power_well) {
6327 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6328 power_well->hw_enabled = false;
6329 power_well->ops->disable(dev_priv, power_well);
6332 check_power_well_state(dev_priv, power_well);
6335 mutex_unlock(&power_domains->lock);
6337 intel_runtime_pm_put(dev_priv);
6340 static struct i915_power_domains *hsw_pwr;
6342 /* Display audio driver power well request */
6343 int i915_request_power_well(void)
6345 struct drm_i915_private *dev_priv;
6350 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6352 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6355 EXPORT_SYMBOL_GPL(i915_request_power_well);
6357 /* Display audio driver power well release */
6358 int i915_release_power_well(void)
6360 struct drm_i915_private *dev_priv;
6365 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6367 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6370 EXPORT_SYMBOL_GPL(i915_release_power_well);
6373 * Private interface for the audio driver to get CDCLK in kHz.
6375 * Caller must request power well using i915_request_power_well() prior to
6378 int i915_get_cdclk_freq(void)
6380 struct drm_i915_private *dev_priv;
6385 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6388 return intel_ddi_get_cdclk_freq(dev_priv);
6390 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6393 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6395 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6396 BIT(POWER_DOMAIN_PIPE_A) | \
6397 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6398 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6399 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6400 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6401 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6402 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6403 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6404 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6405 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6406 BIT(POWER_DOMAIN_PORT_CRT) | \
6407 BIT(POWER_DOMAIN_PLLS) | \
6408 BIT(POWER_DOMAIN_INIT))
6409 #define HSW_DISPLAY_POWER_DOMAINS ( \
6410 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6411 BIT(POWER_DOMAIN_INIT))
6413 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6414 HSW_ALWAYS_ON_POWER_DOMAINS | \
6415 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6416 #define BDW_DISPLAY_POWER_DOMAINS ( \
6417 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6418 BIT(POWER_DOMAIN_INIT))
6420 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6421 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6423 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6424 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6425 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6426 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6427 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6428 BIT(POWER_DOMAIN_PORT_CRT) | \
6429 BIT(POWER_DOMAIN_INIT))
6431 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6432 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6433 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6434 BIT(POWER_DOMAIN_INIT))
6436 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6437 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6438 BIT(POWER_DOMAIN_INIT))
6440 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6441 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6442 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6443 BIT(POWER_DOMAIN_INIT))
6445 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6446 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6447 BIT(POWER_DOMAIN_INIT))
6449 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6450 .sync_hw = i9xx_always_on_power_well_noop,
6451 .enable = i9xx_always_on_power_well_noop,
6452 .disable = i9xx_always_on_power_well_noop,
6453 .is_enabled = i9xx_always_on_power_well_enabled,
6456 static struct i915_power_well i9xx_always_on_power_well[] = {
6458 .name = "always-on",
6460 .domains = POWER_DOMAIN_MASK,
6461 .ops = &i9xx_always_on_power_well_ops,
6465 static const struct i915_power_well_ops hsw_power_well_ops = {
6466 .sync_hw = hsw_power_well_sync_hw,
6467 .enable = hsw_power_well_enable,
6468 .disable = hsw_power_well_disable,
6469 .is_enabled = hsw_power_well_enabled,
6472 static struct i915_power_well hsw_power_wells[] = {
6474 .name = "always-on",
6476 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6477 .ops = &i9xx_always_on_power_well_ops,
6481 .domains = HSW_DISPLAY_POWER_DOMAINS,
6482 .ops = &hsw_power_well_ops,
6486 static struct i915_power_well bdw_power_wells[] = {
6488 .name = "always-on",
6490 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6491 .ops = &i9xx_always_on_power_well_ops,
6495 .domains = BDW_DISPLAY_POWER_DOMAINS,
6496 .ops = &hsw_power_well_ops,
6500 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6501 .sync_hw = vlv_power_well_sync_hw,
6502 .enable = vlv_display_power_well_enable,
6503 .disable = vlv_display_power_well_disable,
6504 .is_enabled = vlv_power_well_enabled,
6507 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6508 .sync_hw = vlv_power_well_sync_hw,
6509 .enable = vlv_dpio_cmn_power_well_enable,
6510 .disable = vlv_dpio_cmn_power_well_disable,
6511 .is_enabled = vlv_power_well_enabled,
6514 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6515 .sync_hw = vlv_power_well_sync_hw,
6516 .enable = vlv_power_well_enable,
6517 .disable = vlv_power_well_disable,
6518 .is_enabled = vlv_power_well_enabled,
6521 static struct i915_power_well vlv_power_wells[] = {
6523 .name = "always-on",
6525 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6526 .ops = &i9xx_always_on_power_well_ops,
6530 .domains = VLV_DISPLAY_POWER_DOMAINS,
6531 .data = PUNIT_POWER_WELL_DISP2D,
6532 .ops = &vlv_display_power_well_ops,
6535 .name = "dpio-tx-b-01",
6536 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6537 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6538 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6539 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6540 .ops = &vlv_dpio_power_well_ops,
6541 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6544 .name = "dpio-tx-b-23",
6545 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6546 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6547 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6548 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6549 .ops = &vlv_dpio_power_well_ops,
6550 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6553 .name = "dpio-tx-c-01",
6554 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6555 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6556 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6557 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6558 .ops = &vlv_dpio_power_well_ops,
6559 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6562 .name = "dpio-tx-c-23",
6563 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6564 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6565 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6566 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6567 .ops = &vlv_dpio_power_well_ops,
6568 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6571 .name = "dpio-common",
6572 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6573 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6574 .ops = &vlv_dpio_cmn_power_well_ops,
6578 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
6579 enum punit_power_well power_well_id)
6581 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6582 struct i915_power_well *power_well;
6585 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6586 if (power_well->data == power_well_id)
6593 #define set_power_wells(power_domains, __power_wells) ({ \
6594 (power_domains)->power_wells = (__power_wells); \
6595 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6598 int intel_power_domains_init(struct drm_i915_private *dev_priv)
6600 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6602 mutex_init(&power_domains->lock);
6605 * The enabling order will be from lower to higher indexed wells,
6606 * the disabling order is reversed.
6608 if (IS_HASWELL(dev_priv->dev)) {
6609 set_power_wells(power_domains, hsw_power_wells);
6610 hsw_pwr = power_domains;
6611 } else if (IS_BROADWELL(dev_priv->dev)) {
6612 set_power_wells(power_domains, bdw_power_wells);
6613 hsw_pwr = power_domains;
6614 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6615 set_power_wells(power_domains, vlv_power_wells);
6617 set_power_wells(power_domains, i9xx_always_on_power_well);
6623 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
6628 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
6630 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6631 struct i915_power_well *power_well;
6634 mutex_lock(&power_domains->lock);
6635 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6636 power_well->ops->sync_hw(dev_priv, power_well);
6637 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
6640 mutex_unlock(&power_domains->lock);
6643 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
6645 struct i915_power_well *cmn =
6646 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
6647 struct i915_power_well *disp2d =
6648 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
6650 /* nothing to do if common lane is already off */
6651 if (!cmn->ops->is_enabled(dev_priv, cmn))
6654 /* If the display might be already active skip this */
6655 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
6656 I915_READ(DPIO_CTL) & DPIO_CMNRST)
6659 DRM_DEBUG_KMS("toggling display PHY side reset\n");
6661 /* cmnlane needs DPLL registers */
6662 disp2d->ops->enable(dev_priv, disp2d);
6665 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
6666 * Need to assert and de-assert PHY SB reset by gating the
6667 * common lane power, then un-gating it.
6668 * Simply ungating isn't enough to reset the PHY enough to get
6669 * ports and lanes running.
6671 cmn->ops->disable(dev_priv, cmn);
6674 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
6676 struct drm_device *dev = dev_priv->dev;
6677 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6679 power_domains->initializing = true;
6681 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
6682 mutex_lock(&power_domains->lock);
6683 vlv_cmnlane_wa(dev_priv);
6684 mutex_unlock(&power_domains->lock);
6687 /* For now, we need the power well to be always enabled. */
6688 intel_display_set_init_power(dev_priv, true);
6689 intel_power_domains_resume(dev_priv);
6690 power_domains->initializing = false;
6693 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6695 intel_runtime_pm_get(dev_priv);
6698 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6700 intel_runtime_pm_put(dev_priv);
6703 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6705 struct drm_device *dev = dev_priv->dev;
6706 struct device *device = &dev->pdev->dev;
6708 if (!HAS_RUNTIME_PM(dev))
6711 pm_runtime_get_sync(device);
6712 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6715 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6717 struct drm_device *dev = dev_priv->dev;
6718 struct device *device = &dev->pdev->dev;
6720 if (!HAS_RUNTIME_PM(dev))
6723 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6724 pm_runtime_get_noresume(device);
6727 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6729 struct drm_device *dev = dev_priv->dev;
6730 struct device *device = &dev->pdev->dev;
6732 if (!HAS_RUNTIME_PM(dev))
6735 pm_runtime_mark_last_busy(device);
6736 pm_runtime_put_autosuspend(device);
6739 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6741 struct drm_device *dev = dev_priv->dev;
6742 struct device *device = &dev->pdev->dev;
6744 if (!HAS_RUNTIME_PM(dev))
6747 pm_runtime_set_active(device);
6750 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6753 if (!intel_enable_rc6(dev)) {
6754 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6758 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6759 pm_runtime_mark_last_busy(device);
6760 pm_runtime_use_autosuspend(device);
6762 pm_runtime_put_autosuspend(device);
6765 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6767 struct drm_device *dev = dev_priv->dev;
6768 struct device *device = &dev->pdev->dev;
6770 if (!HAS_RUNTIME_PM(dev))
6773 if (!intel_enable_rc6(dev))
6776 /* Make sure we're not suspended first. */
6777 pm_runtime_get_sync(device);
6778 pm_runtime_disable(device);
6781 /* Set up chip specific power management-related functions */
6782 void intel_init_pm(struct drm_device *dev)
6784 struct drm_i915_private *dev_priv = dev->dev_private;
6787 if (INTEL_INFO(dev)->gen >= 7) {
6788 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6789 dev_priv->display.enable_fbc = gen7_enable_fbc;
6790 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6791 } else if (INTEL_INFO(dev)->gen >= 5) {
6792 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6793 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6794 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6795 } else if (IS_GM45(dev)) {
6796 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6797 dev_priv->display.enable_fbc = g4x_enable_fbc;
6798 dev_priv->display.disable_fbc = g4x_disable_fbc;
6800 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6801 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6802 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6804 /* This value was pulled out of someone's hat */
6805 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6810 if (IS_PINEVIEW(dev))
6811 i915_pineview_get_mem_freq(dev);
6812 else if (IS_GEN5(dev))
6813 i915_ironlake_get_mem_freq(dev);
6815 /* For FIFO watermark updates */
6816 if (HAS_PCH_SPLIT(dev)) {
6817 ilk_setup_wm_latency(dev);
6819 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6820 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6821 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6822 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6823 dev_priv->display.update_wm = ilk_update_wm;
6824 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6826 DRM_DEBUG_KMS("Failed to read display plane latency. "
6831 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6832 else if (IS_GEN6(dev))
6833 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6834 else if (IS_IVYBRIDGE(dev))
6835 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6836 else if (IS_HASWELL(dev))
6837 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6838 else if (INTEL_INFO(dev)->gen == 8)
6839 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6840 } else if (IS_CHERRYVIEW(dev)) {
6841 dev_priv->display.update_wm = valleyview_update_wm;
6842 dev_priv->display.init_clock_gating =
6843 cherryview_init_clock_gating;
6844 } else if (IS_VALLEYVIEW(dev)) {
6845 dev_priv->display.update_wm = valleyview_update_wm;
6846 dev_priv->display.init_clock_gating =
6847 valleyview_init_clock_gating;
6848 } else if (IS_PINEVIEW(dev)) {
6849 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6852 dev_priv->mem_freq)) {
6853 DRM_INFO("failed to find known CxSR latency "
6854 "(found ddr%s fsb freq %d, mem freq %d), "
6856 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6857 dev_priv->fsb_freq, dev_priv->mem_freq);
6858 /* Disable CxSR and never update its watermark again */
6859 intel_set_memory_cxsr(dev_priv, false);
6860 dev_priv->display.update_wm = NULL;
6862 dev_priv->display.update_wm = pineview_update_wm;
6863 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6864 } else if (IS_G4X(dev)) {
6865 dev_priv->display.update_wm = g4x_update_wm;
6866 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6867 } else if (IS_GEN4(dev)) {
6868 dev_priv->display.update_wm = i965_update_wm;
6869 if (IS_CRESTLINE(dev))
6870 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6871 else if (IS_BROADWATER(dev))
6872 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6873 } else if (IS_GEN3(dev)) {
6874 dev_priv->display.update_wm = i9xx_update_wm;
6875 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6876 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6877 } else if (IS_GEN2(dev)) {
6878 if (INTEL_INFO(dev)->num_pipes == 1) {
6879 dev_priv->display.update_wm = i845_update_wm;
6880 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6882 dev_priv->display.update_wm = i9xx_update_wm;
6883 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6886 if (IS_I85X(dev) || IS_I865G(dev))
6887 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6889 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6891 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6895 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6897 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6899 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6900 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6904 I915_WRITE(GEN6_PCODE_DATA, *val);
6905 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6907 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6909 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6913 *val = I915_READ(GEN6_PCODE_DATA);
6914 I915_WRITE(GEN6_PCODE_DATA, 0);
6919 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6921 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6923 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6924 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6928 I915_WRITE(GEN6_PCODE_DATA, val);
6929 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6931 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6933 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6937 I915_WRITE(GEN6_PCODE_DATA, 0);
6942 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6947 switch (dev_priv->mem_freq) {
6961 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6964 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
6969 switch (dev_priv->mem_freq) {
6983 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6986 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6990 switch (dev_priv->rps.cz_freq) {
7006 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7011 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7015 switch (dev_priv->rps.cz_freq) {
7031 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7036 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7040 if (IS_CHERRYVIEW(dev_priv->dev))
7041 ret = chv_gpu_freq(dev_priv, val);
7042 else if (IS_VALLEYVIEW(dev_priv->dev))
7043 ret = byt_gpu_freq(dev_priv, val);
7048 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7052 if (IS_CHERRYVIEW(dev_priv->dev))
7053 ret = chv_freq_opcode(dev_priv, val);
7054 else if (IS_VALLEYVIEW(dev_priv->dev))
7055 ret = byt_freq_opcode(dev_priv, val);
7060 void intel_pm_setup(struct drm_device *dev)
7062 struct drm_i915_private *dev_priv = dev->dev_private;
7064 mutex_init(&dev_priv->rps.hw_lock);
7066 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7067 intel_gen6_powersave_work);
7069 dev_priv->pm.suspended = false;
7070 dev_priv->pm._irqs_disabled = false;