drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void i8xx_disable_fbc(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         u32 fbc_ctl;
  73
  74         /* Disable compression */
  75         fbc_ctl = I915_READ(FBC_CONTROL);
  76         if ((fbc_ctl & FBC_CTL_EN) == 0)
  77                 return;
  78
  79         fbc_ctl &= ~FBC_CTL_EN;
  80         I915_WRITE(FBC_CONTROL, fbc_ctl);
  81
  82         /* Wait for compressing bit to clear */
  83         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  84                 DRM_DEBUG_KMS("FBC idle timed out\n");
  85                 return;
  86         }
  87
  88         DRM_DEBUG_KMS("disabled FBC\n");
  89 }
  90
  91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct drm_i915_private *dev_priv = dev->dev_private;
  95         struct drm_framebuffer *fb = crtc->primary->fb;
  96         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  97         struct drm_i915_gem_object *obj = intel_fb->obj;
  98         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  99         int cfb_pitch;
 100         int i;
 101         u32 fbc_ctl;
 102
 103         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 104         if (fb->pitches[0] < cfb_pitch)
 105                 cfb_pitch = fb->pitches[0];
 106
 107         /* FBC_CTL wants 32B or 64B units */
 108         if (IS_GEN2(dev))
 109                 cfb_pitch = (cfb_pitch / 32) - 1;
 110         else
 111                 cfb_pitch = (cfb_pitch / 64) - 1;
 112
 113         /* Clear old tags */
 114         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 115                 I915_WRITE(FBC_TAG + (i * 4), 0);
 116
 117         if (IS_GEN4(dev)) {
 118                 u32 fbc_ctl2;
 119
 120                 /* Set it up... */
 121                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 122                 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
 123                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 124                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 125         }
 126
 127         /* enable it... */
 128         fbc_ctl = I915_READ(FBC_CONTROL);
 129         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 130         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 131         if (IS_I945GM(dev))
 132                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 133         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 134         fbc_ctl |= obj->fence_reg;
 135         I915_WRITE(FBC_CONTROL, fbc_ctl);
 136
 137         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 138                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 139 }
 140
 141 static bool i8xx_fbc_enabled(struct drm_device *dev)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144
 145         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 146 }
 147
 148 static void g4x_enable_fbc(struct drm_crtc *crtc)
 149 {
 150         struct drm_device *dev = crtc->dev;
 151         struct drm_i915_private *dev_priv = dev->dev_private;
 152         struct drm_framebuffer *fb = crtc->primary->fb;
 153         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 154         struct drm_i915_gem_object *obj = intel_fb->obj;
 155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 156         u32 dpfc_ctl;
 157
 158         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
 159         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 160                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 161         else
 162                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 163         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 164
 165         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 166
 167         /* enable it... */
 168         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 169
 170         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 171 }
 172
 173 static void g4x_disable_fbc(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         u32 dpfc_ctl;
 177
 178         /* Disable compression */
 179         dpfc_ctl = I915_READ(DPFC_CONTROL);
 180         if (dpfc_ctl & DPFC_CTL_EN) {
 181                 dpfc_ctl &= ~DPFC_CTL_EN;
 182                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 183
 184                 DRM_DEBUG_KMS("disabled FBC\n");
 185         }
 186 }
 187
 188 static bool g4x_fbc_enabled(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191
 192         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 193 }
 194
 195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 196 {
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198         u32 blt_ecoskpd;
 199
 200         /* Make sure blitter notifies FBC of writes */
 201
 202         /* Blitter is part of Media powerwell on VLV. No impact of
 203          * his param in other platforms for now */
 204         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 205
 206         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 207         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 208                 GEN6_BLITTER_LOCK_SHIFT;
 209         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 210         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 211         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 212         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 213                          GEN6_BLITTER_LOCK_SHIFT);
 214         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 215         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 216
 217         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 218 }
 219
 220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 221 {
 222         struct drm_device *dev = crtc->dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct drm_framebuffer *fb = crtc->primary->fb;
 225         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 226         struct drm_i915_gem_object *obj = intel_fb->obj;
 227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 228         u32 dpfc_ctl;
 229
 230         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
 231         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 232                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 233         else
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 235         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236         if (IS_GEN5(dev))
 237                 dpfc_ctl |= obj->fence_reg;
 238
 239         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 240         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 241         /* enable it... */
 242         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 243
 244         if (IS_GEN6(dev)) {
 245                 I915_WRITE(SNB_DPFC_CTL_SA,
 246                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 247                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 248                 sandybridge_blit_fbc_update(dev);
 249         }
 250
 251         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 252 }
 253
 254 static void ironlake_disable_fbc(struct drm_device *dev)
 255 {
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         u32 dpfc_ctl;
 258
 259         /* Disable compression */
 260         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 261         if (dpfc_ctl & DPFC_CTL_EN) {
 262                 dpfc_ctl &= ~DPFC_CTL_EN;
 263                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 264
 265                 DRM_DEBUG_KMS("disabled FBC\n");
 266         }
 267 }
 268
 269 static bool ironlake_fbc_enabled(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272
 273         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 274 }
 275
 276 static void gen7_enable_fbc(struct drm_crtc *crtc)
 277 {
 278         struct drm_device *dev = crtc->dev;
 279         struct drm_i915_private *dev_priv = dev->dev_private;
 280         struct drm_framebuffer *fb = crtc->primary->fb;
 281         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 282         struct drm_i915_gem_object *obj = intel_fb->obj;
 283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 284         u32 dpfc_ctl;
 285
 286         dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
 287         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 288                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 289         else
 290                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 291         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 292
 293         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 294
 295         if (IS_IVYBRIDGE(dev)) {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 297                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 298                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 299                            ILK_FBCQ_DIS);
 300         } else {
 301                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 302                 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
 303                            I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
 304                            HSW_FBCQ_DIS);
 305         }
 306
 307         I915_WRITE(SNB_DPFC_CTL_SA,
 308                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 309         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 310
 311         sandybridge_blit_fbc_update(dev);
 312
 313         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 314 }
 315
 316 bool intel_fbc_enabled(struct drm_device *dev)
 317 {
 318         struct drm_i915_private *dev_priv = dev->dev_private;
 319
 320         if (!dev_priv->display.fbc_enabled)
 321                 return false;
 322
 323         return dev_priv->display.fbc_enabled(dev);
 324 }
 325
 326 static void intel_fbc_work_fn(struct work_struct *__work)
 327 {
 328         struct intel_fbc_work *work =
 329                 container_of(to_delayed_work(__work),
 330                              struct intel_fbc_work, work);
 331         struct drm_device *dev = work->crtc->dev;
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333
 334         mutex_lock(&dev->struct_mutex);
 335         if (work == dev_priv->fbc.fbc_work) {
 336                 /* Double check that we haven't switched fb without cancelling
 337                  * the prior work.
 338                  */
 339                 if (work->crtc->primary->fb == work->fb) {
 340                         dev_priv->display.enable_fbc(work->crtc);
 341
 342                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 343                         dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
 344                         dev_priv->fbc.y = work->crtc->y;
 345                 }
 346
 347                 dev_priv->fbc.fbc_work = NULL;
 348         }
 349         mutex_unlock(&dev->struct_mutex);
 350
 351         kfree(work);
 352 }
 353
 354 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 355 {
 356         if (dev_priv->fbc.fbc_work == NULL)
 357                 return;
 358
 359         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 360
 361         /* Synchronisation is provided by struct_mutex and checking of
 362          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 363          * entirely asynchronously.
 364          */
 365         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 366                 /* tasklet was killed before being run, clean up */
 367                 kfree(dev_priv->fbc.fbc_work);
 368
 369         /* Mark the work as no longer wanted so that if it does
 370          * wake-up (because the work was already running and waiting
 371          * for our mutex), it will discover that is no longer
 372          * necessary to run.
 373          */
 374         dev_priv->fbc.fbc_work = NULL;
 375 }
 376
 377 static void intel_enable_fbc(struct drm_crtc *crtc)
 378 {
 379         struct intel_fbc_work *work;
 380         struct drm_device *dev = crtc->dev;
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382
 383         if (!dev_priv->display.enable_fbc)
 384                 return;
 385
 386         intel_cancel_fbc_work(dev_priv);
 387
 388         work = kzalloc(sizeof(*work), GFP_KERNEL);
 389         if (work == NULL) {
 390                 DRM_ERROR("Failed to allocate FBC work structure\n");
 391                 dev_priv->display.enable_fbc(crtc);
 392                 return;
 393         }
 394
 395         work->crtc = crtc;
 396         work->fb = crtc->primary->fb;
 397         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 398
 399         dev_priv->fbc.fbc_work = work;
 400
 401         /* Delay the actual enabling to let pageflipping cease and the
 402          * display to settle before starting the compression. Note that
 403          * this delay also serves a second purpose: it allows for a
 404          * vblank to pass after disabling the FBC before we attempt
 405          * to modify the control registers.
 406          *
 407          * A more complicated solution would involve tracking vblanks
 408          * following the termination of the page-flipping sequence
 409          * and indeed performing the enable as a co-routine and not
 410          * waiting synchronously upon the vblank.
 411          *
 412          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 413          */
 414         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 415 }
 416
 417 void intel_disable_fbc(struct drm_device *dev)
 418 {
 419         struct drm_i915_private *dev_priv = dev->dev_private;
 420
 421         intel_cancel_fbc_work(dev_priv);
 422
 423         if (!dev_priv->display.disable_fbc)
 424                 return;
 425
 426         dev_priv->display.disable_fbc(dev);
 427         dev_priv->fbc.plane = -1;
 428 }
 429
 430 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 431                               enum no_fbc_reason reason)
 432 {
 433         if (dev_priv->fbc.no_fbc_reason == reason)
 434                 return false;
 435
 436         dev_priv->fbc.no_fbc_reason = reason;
 437         return true;
 438 }
 439
 440 /**
 441  * intel_update_fbc - enable/disable FBC as needed
 442  * @dev: the drm_device
 443  *
 444  * Set up the framebuffer compression hardware at mode set time.  We
 445  * enable it if possible:
 446  *   - plane A only (on pre-965)
 447  *   - no pixel mulitply/line duplication
 448  *   - no alpha buffer discard
 449  *   - no dual wide
 450  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 451  *
 452  * We can't assume that any compression will take place (worst case),
 453  * so the compressed buffer has to be the same size as the uncompressed
 454  * one.  It also must reside (along with the line length buffer) in
 455  * stolen memory.
 456  *
 457  * We need to enable/disable FBC on a global basis.
 458  */
 459 void intel_update_fbc(struct drm_device *dev)
 460 {
 461         struct drm_i915_private *dev_priv = dev->dev_private;
 462         struct drm_crtc *crtc = NULL, *tmp_crtc;
 463         struct intel_crtc *intel_crtc;
 464         struct drm_framebuffer *fb;
 465         struct intel_framebuffer *intel_fb;
 466         struct drm_i915_gem_object *obj;
 467         const struct drm_display_mode *adjusted_mode;
 468         unsigned int max_width, max_height;
 469
 470         if (!HAS_FBC(dev)) {
 471                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 472                 return;
 473         }
 474
 475         if (!i915.powersave) {
 476                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 477                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 478                 return;
 479         }
 480
 481         /*
 482          * If FBC is already on, we just have to verify that we can
 483          * keep it that way...
 484          * Need to disable if:
 485          *   - more than one pipe is active
 486          *   - changing FBC params (stride, fence, mode)
 487          *   - new fb is too large to fit in compressed buffer
 488          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 489          */
 490         for_each_crtc(dev, tmp_crtc) {
 491                 if (intel_crtc_active(tmp_crtc) &&
 492                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 493                         if (crtc) {
 494                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 495                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 496                                 goto out_disable;
 497                         }
 498                         crtc = tmp_crtc;
 499                 }
 500         }
 501
 502         if (!crtc || crtc->primary->fb == NULL) {
 503                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 504                         DRM_DEBUG_KMS("no output, disabling\n");
 505                 goto out_disable;
 506         }
 507
 508         intel_crtc = to_intel_crtc(crtc);
 509         fb = crtc->primary->fb;
 510         intel_fb = to_intel_framebuffer(fb);
 511         obj = intel_fb->obj;
 512         adjusted_mode = &intel_crtc->config.adjusted_mode;
 513
 514         if (i915.enable_fbc < 0 &&
 515             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 516                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 517                         DRM_DEBUG_KMS("disabled per chip default\n");
 518                 goto out_disable;
 519         }
 520         if (!i915.enable_fbc) {
 521                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 522                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 523                 goto out_disable;
 524         }
 525         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 526             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 527                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 528                         DRM_DEBUG_KMS("mode incompatible with compression, "
 529                                       "disabling\n");
 530                 goto out_disable;
 531         }
 532
 533         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 534                 max_width = 4096;
 535                 max_height = 2048;
 536         } else {
 537                 max_width = 2048;
 538                 max_height = 1536;
 539         }
 540         if (intel_crtc->config.pipe_src_w > max_width ||
 541             intel_crtc->config.pipe_src_h > max_height) {
 542                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 543                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 544                 goto out_disable;
 545         }
 546         if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 547             intel_crtc->plane != PLANE_A) {
 548                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 549                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 550                 goto out_disable;
 551         }
 552
 553         /* The use of a CPU fence is mandatory in order to detect writes
 554          * by the CPU to the scanout and trigger updates to the FBC.
 555          */
 556         if (obj->tiling_mode != I915_TILING_X ||
 557             obj->fence_reg == I915_FENCE_REG_NONE) {
 558                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 559                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 560                 goto out_disable;
 561         }
 562
 563         /* If the kernel debugger is active, always disable compression */
 564         if (in_dbg_master())
 565                 goto out_disable;
 566
 567         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 568                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 569                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 570                 goto out_disable;
 571         }
 572
 573         /* If the scanout has not changed, don't modify the FBC settings.
 574          * Note that we make the fundamental assumption that the fb->obj
 575          * cannot be unpinned (and have its GTT offset and fence revoked)
 576          * without first being decoupled from the scanout and FBC disabled.
 577          */
 578         if (dev_priv->fbc.plane == intel_crtc->plane &&
 579             dev_priv->fbc.fb_id == fb->base.id &&
 580             dev_priv->fbc.y == crtc->y)
 581                 return;
 582
 583         if (intel_fbc_enabled(dev)) {
 584                 /* We update FBC along two paths, after changing fb/crtc
 585                  * configuration (modeswitching) and after page-flipping
 586                  * finishes. For the latter, we know that not only did
 587                  * we disable the FBC at the start of the page-flip
 588                  * sequence, but also more than one vblank has passed.
 589                  *
 590                  * For the former case of modeswitching, it is possible
 591                  * to switch between two FBC valid configurations
 592                  * instantaneously so we do need to disable the FBC
 593                  * before we can modify its control registers. We also
 594                  * have to wait for the next vblank for that to take
 595                  * effect. However, since we delay enabling FBC we can
 596                  * assume that a vblank has passed since disabling and
 597                  * that we can safely alter the registers in the deferred
 598                  * callback.
 599                  *
 600                  * In the scenario that we go from a valid to invalid
 601                  * and then back to valid FBC configuration we have
 602                  * no strict enforcement that a vblank occurred since
 603                  * disabling the FBC. However, along all current pipe
 604                  * disabling paths we do need to wait for a vblank at
 605                  * some point. And we wait before enabling FBC anyway.
 606                  */
 607                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 608                 intel_disable_fbc(dev);
 609         }
 610
 611         intel_enable_fbc(crtc);
 612         dev_priv->fbc.no_fbc_reason = FBC_OK;
 613         return;
 614
 615 out_disable:
 616         /* Multiple disables should be harmless */
 617         if (intel_fbc_enabled(dev)) {
 618                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 619                 intel_disable_fbc(dev);
 620         }
 621         i915_gem_stolen_cleanup_compression(dev);
 622 }
 623
 624 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 625 {
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         u32 tmp;
 628
 629         tmp = I915_READ(CLKCFG);
 630
 631         switch (tmp & CLKCFG_FSB_MASK) {
 632         case CLKCFG_FSB_533:
 633                 dev_priv->fsb_freq = 533; /* 133*4 */
 634                 break;
 635         case CLKCFG_FSB_800:
 636                 dev_priv->fsb_freq = 800; /* 200*4 */
 637                 break;
 638         case CLKCFG_FSB_667:
 639                 dev_priv->fsb_freq =  667; /* 167*4 */
 640                 break;
 641         case CLKCFG_FSB_400:
 642                 dev_priv->fsb_freq = 400; /* 100*4 */
 643                 break;
 644         }
 645
 646         switch (tmp & CLKCFG_MEM_MASK) {
 647         case CLKCFG_MEM_533:
 648                 dev_priv->mem_freq = 533;
 649                 break;
 650         case CLKCFG_MEM_667:
 651                 dev_priv->mem_freq = 667;
 652                 break;
 653         case CLKCFG_MEM_800:
 654                 dev_priv->mem_freq = 800;
 655                 break;
 656         }
 657
 658         /* detect pineview DDR3 setting */
 659         tmp = I915_READ(CSHRDDR3CTL);
 660         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 661 }
 662
 663 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 664 {
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         u16 ddrpll, csipll;
 667
 668         ddrpll = I915_READ16(DDRMPLL1);
 669         csipll = I915_READ16(CSIPLL0);
 670
 671         switch (ddrpll & 0xff) {
 672         case 0xc:
 673                 dev_priv->mem_freq = 800;
 674                 break;
 675         case 0x10:
 676                 dev_priv->mem_freq = 1066;
 677                 break;
 678         case 0x14:
 679                 dev_priv->mem_freq = 1333;
 680                 break;
 681         case 0x18:
 682                 dev_priv->mem_freq = 1600;
 683                 break;
 684         default:
 685                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 686                                  ddrpll & 0xff);
 687                 dev_priv->mem_freq = 0;
 688                 break;
 689         }
 690
 691         dev_priv->ips.r_t = dev_priv->mem_freq;
 692
 693         switch (csipll & 0x3ff) {
 694         case 0x00c:
 695                 dev_priv->fsb_freq = 3200;
 696                 break;
 697         case 0x00e:
 698                 dev_priv->fsb_freq = 3733;
 699                 break;
 700         case 0x010:
 701                 dev_priv->fsb_freq = 4266;
 702                 break;
 703         case 0x012:
 704                 dev_priv->fsb_freq = 4800;
 705                 break;
 706         case 0x014:
 707                 dev_priv->fsb_freq = 5333;
 708                 break;
 709         case 0x016:
 710                 dev_priv->fsb_freq = 5866;
 711                 break;
 712         case 0x018:
 713                 dev_priv->fsb_freq = 6400;
 714                 break;
 715         default:
 716                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 717                                  csipll & 0x3ff);
 718                 dev_priv->fsb_freq = 0;
 719                 break;
 720         }
 721
 722         if (dev_priv->fsb_freq == 3200) {
 723                 dev_priv->ips.c_m = 0;
 724         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 725                 dev_priv->ips.c_m = 1;
 726         } else {
 727                 dev_priv->ips.c_m = 2;
 728         }
 729 }
 730
 731 static const struct cxsr_latency cxsr_latency_table[] = {
 732         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 733         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 734         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 735         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 736         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 737
 738         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 739         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 740         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 741         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 742         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 743
 744         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 745         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 746         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 747         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 748         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 749
 750         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 751         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 752         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 753         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 754         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 755
 756         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 757         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 758         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 759         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 760         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 761
 762         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 763         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 764         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 765         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 766         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 767 };
 768
 769 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 770                                                          int is_ddr3,
 771                                                          int fsb,
 772                                                          int mem)
 773 {
 774         const struct cxsr_latency *latency;
 775         int i;
 776
 777         if (fsb == 0 || mem == 0)
 778                 return NULL;
 779
 780         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 781                 latency = &cxsr_latency_table[i];
 782                 if (is_desktop == latency->is_desktop &&
 783                     is_ddr3 == latency->is_ddr3 &&
 784                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 785                         return latency;
 786         }
 787
 788         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 789
 790         return NULL;
 791 }
 792
 793 static void pineview_disable_cxsr(struct drm_device *dev)
 794 {
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796
 797         /* deactivate cxsr */
 798         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 799 }
 800
 801 /*
 802  * Latency for FIFO fetches is dependent on several factors:
 803  *   - memory configuration (speed, channels)
 804  *   - chipset
 805  *   - current MCH state
 806  * It can be fairly high in some situations, so here we assume a fairly
 807  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 808  * set this value too high, the FIFO will fetch frequently to stay full)
 809  * and power consumption (set it too low to save power and we might see
 810  * FIFO underruns and display "flicker").
 811  *
 812  * A value of 5us seems to be a good balance; safe for very low end
 813  * platforms but not overly aggressive on lower latency configs.
 814  */
 815 static const int latency_ns = 5000;
 816
 817 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 818 {
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         uint32_t dsparb = I915_READ(DSPARB);
 821         int size;
 822
 823         size = dsparb & 0x7f;
 824         if (plane)
 825                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 826
 827         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 828                       plane ? "B" : "A", size);
 829
 830         return size;
 831 }
 832
 833 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 834 {
 835         struct drm_i915_private *dev_priv = dev->dev_private;
 836         uint32_t dsparb = I915_READ(DSPARB);
 837         int size;
 838
 839         size = dsparb & 0x1ff;
 840         if (plane)
 841                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 842         size >>= 1; /* Convert to cachelines */
 843
 844         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 845                       plane ? "B" : "A", size);
 846
 847         return size;
 848 }
 849
 850 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         uint32_t dsparb = I915_READ(DSPARB);
 854         int size;
 855
 856         size = dsparb & 0x7f;
 857         size >>= 2; /* Convert to cachelines */
 858
 859         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 860                       plane ? "B" : "A",
 861                       size);
 862
 863         return size;
 864 }
 865
 866 /* Pineview has different values for various configs */
 867 static const struct intel_watermark_params pineview_display_wm = {
 868         PINEVIEW_DISPLAY_FIFO,
 869         PINEVIEW_MAX_WM,
 870         PINEVIEW_DFT_WM,
 871         PINEVIEW_GUARD_WM,
 872         PINEVIEW_FIFO_LINE_SIZE
 873 };
 874 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 875         PINEVIEW_DISPLAY_FIFO,
 876         PINEVIEW_MAX_WM,
 877         PINEVIEW_DFT_HPLLOFF_WM,
 878         PINEVIEW_GUARD_WM,
 879         PINEVIEW_FIFO_LINE_SIZE
 880 };
 881 static const struct intel_watermark_params pineview_cursor_wm = {
 882         PINEVIEW_CURSOR_FIFO,
 883         PINEVIEW_CURSOR_MAX_WM,
 884         PINEVIEW_CURSOR_DFT_WM,
 885         PINEVIEW_CURSOR_GUARD_WM,
 886         PINEVIEW_FIFO_LINE_SIZE,
 887 };
 888 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 889         PINEVIEW_CURSOR_FIFO,
 890         PINEVIEW_CURSOR_MAX_WM,
 891         PINEVIEW_CURSOR_DFT_WM,
 892         PINEVIEW_CURSOR_GUARD_WM,
 893         PINEVIEW_FIFO_LINE_SIZE
 894 };
 895 static const struct intel_watermark_params g4x_wm_info = {
 896         G4X_FIFO_SIZE,
 897         G4X_MAX_WM,
 898         G4X_MAX_WM,
 899         2,
 900         G4X_FIFO_LINE_SIZE,
 901 };
 902 static const struct intel_watermark_params g4x_cursor_wm_info = {
 903         I965_CURSOR_FIFO,
 904         I965_CURSOR_MAX_WM,
 905         I965_CURSOR_DFT_WM,
 906         2,
 907         G4X_FIFO_LINE_SIZE,
 908 };
 909 static const struct intel_watermark_params valleyview_wm_info = {
 910         VALLEYVIEW_FIFO_SIZE,
 911         VALLEYVIEW_MAX_WM,
 912         VALLEYVIEW_MAX_WM,
 913         2,
 914         G4X_FIFO_LINE_SIZE,
 915 };
 916 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 917         I965_CURSOR_FIFO,
 918         VALLEYVIEW_CURSOR_MAX_WM,
 919         I965_CURSOR_DFT_WM,
 920         2,
 921         G4X_FIFO_LINE_SIZE,
 922 };
 923 static const struct intel_watermark_params i965_cursor_wm_info = {
 924         I965_CURSOR_FIFO,
 925         I965_CURSOR_MAX_WM,
 926         I965_CURSOR_DFT_WM,
 927         2,
 928         I915_FIFO_LINE_SIZE,
 929 };
 930 static const struct intel_watermark_params i945_wm_info = {
 931         I945_FIFO_SIZE,
 932         I915_MAX_WM,
 933         1,
 934         2,
 935         I915_FIFO_LINE_SIZE
 936 };
 937 static const struct intel_watermark_params i915_wm_info = {
 938         I915_FIFO_SIZE,
 939         I915_MAX_WM,
 940         1,
 941         2,
 942         I915_FIFO_LINE_SIZE
 943 };
 944 static const struct intel_watermark_params i830_wm_info = {
 945         I855GM_FIFO_SIZE,
 946         I915_MAX_WM,
 947         1,
 948         2,
 949         I830_FIFO_LINE_SIZE
 950 };
 951 static const struct intel_watermark_params i845_wm_info = {
 952         I830_FIFO_SIZE,
 953         I915_MAX_WM,
 954         1,
 955         2,
 956         I830_FIFO_LINE_SIZE
 957 };
 958
 959 /**
 960  * intel_calculate_wm - calculate watermark level
 961  * @clock_in_khz: pixel clock
 962  * @wm: chip FIFO params
 963  * @pixel_size: display pixel size
 964  * @latency_ns: memory latency for the platform
 965  *
 966  * Calculate the watermark level (the level at which the display plane will
 967  * start fetching from memory again).  Each chip has a different display
 968  * FIFO size and allocation, so the caller needs to figure that out and pass
 969  * in the correct intel_watermark_params structure.
 970  *
 971  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 972  * on the pixel size.  When it reaches the watermark level, it'll start
 973  * fetching FIFO line sized based chunks from memory until the FIFO fills
 974  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 975  * will occur, and a display engine hang could result.
 976  */
 977 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 978                                         const struct intel_watermark_params *wm,
 979                                         int fifo_size,
 980                                         int pixel_size,
 981                                         unsigned long latency_ns)
 982 {
 983         long entries_required, wm_size;
 984
 985         /*
 986          * Note: we need to make sure we don't overflow for various clock &
 987          * latency values.
 988          * clocks go from a few thousand to several hundred thousand.
 989          * latency is usually a few thousand
 990          */
 991         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 992                 1000;
 993         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 994
 995         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 996
 997         wm_size = fifo_size - (entries_required + wm->guard_size);
 998
 999         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000
1001         /* Don't promote wm_size to unsigned... */
1002         if (wm_size > (long)wm->max_wm)
1003                 wm_size = wm->max_wm;
1004         if (wm_size <= 0)
1005                 wm_size = wm->default_wm;
1006         return wm_size;
1007 }
1008
1009 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010 {
1011         struct drm_crtc *crtc, *enabled = NULL;
1012
1013         for_each_crtc(dev, crtc) {
1014                 if (intel_crtc_active(crtc)) {
1015                         if (enabled)
1016                                 return NULL;
1017                         enabled = crtc;
1018                 }
1019         }
1020
1021         return enabled;
1022 }
1023
1024 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1025 {
1026         struct drm_device *dev = unused_crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         struct drm_crtc *crtc;
1029         const struct cxsr_latency *latency;
1030         u32 reg;
1031         unsigned long wm;
1032
1033         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1035         if (!latency) {
1036                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037                 pineview_disable_cxsr(dev);
1038                 return;
1039         }
1040
1041         crtc = single_enabled_crtc(dev);
1042         if (crtc) {
1043                 const struct drm_display_mode *adjusted_mode;
1044                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1045                 int clock;
1046
1047                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048                 clock = adjusted_mode->crtc_clock;
1049
1050                 /* Display SR */
1051                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052                                         pineview_display_wm.fifo_size,
1053                                         pixel_size, latency->display_sr);
1054                 reg = I915_READ(DSPFW1);
1055                 reg &= ~DSPFW_SR_MASK;
1056                 reg |= wm << DSPFW_SR_SHIFT;
1057                 I915_WRITE(DSPFW1, reg);
1058                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1059
1060                 /* cursor SR */
1061                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062                                         pineview_display_wm.fifo_size,
1063                                         pixel_size, latency->cursor_sr);
1064                 reg = I915_READ(DSPFW3);
1065                 reg &= ~DSPFW_CURSOR_SR_MASK;
1066                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067                 I915_WRITE(DSPFW3, reg);
1068
1069                 /* Display HPLL off SR */
1070                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071                                         pineview_display_hplloff_wm.fifo_size,
1072                                         pixel_size, latency->display_hpll_disable);
1073                 reg = I915_READ(DSPFW3);
1074                 reg &= ~DSPFW_HPLL_SR_MASK;
1075                 reg |= wm & DSPFW_HPLL_SR_MASK;
1076                 I915_WRITE(DSPFW3, reg);
1077
1078                 /* cursor HPLL off SR */
1079                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080                                         pineview_display_hplloff_wm.fifo_size,
1081                                         pixel_size, latency->cursor_hpll_disable);
1082                 reg = I915_READ(DSPFW3);
1083                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085                 I915_WRITE(DSPFW3, reg);
1086                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1087
1088                 /* activate cxsr */
1089                 I915_WRITE(DSPFW3,
1090                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092         } else {
1093                 pineview_disable_cxsr(dev);
1094                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1095         }
1096 }
1097
1098 static bool g4x_compute_wm0(struct drm_device *dev,
1099                             int plane,
1100                             const struct intel_watermark_params *display,
1101                             int display_latency_ns,
1102                             const struct intel_watermark_params *cursor,
1103                             int cursor_latency_ns,
1104                             int *plane_wm,
1105                             int *cursor_wm)
1106 {
1107         struct drm_crtc *crtc;
1108         const struct drm_display_mode *adjusted_mode;
1109         int htotal, hdisplay, clock, pixel_size;
1110         int line_time_us, line_count;
1111         int entries, tlb_miss;
1112
1113         crtc = intel_get_crtc_for_plane(dev, plane);
1114         if (!intel_crtc_active(crtc)) {
1115                 *cursor_wm = cursor->guard_size;
1116                 *plane_wm = display->guard_size;
1117                 return false;
1118         }
1119
1120         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1121         clock = adjusted_mode->crtc_clock;
1122         htotal = adjusted_mode->crtc_htotal;
1123         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1124         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1125
1126         /* Use the small buffer method to calculate plane watermark */
1127         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129         if (tlb_miss > 0)
1130                 entries += tlb_miss;
1131         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132         *plane_wm = entries + display->guard_size;
1133         if (*plane_wm > (int)display->max_wm)
1134                 *plane_wm = display->max_wm;
1135
1136         /* Use the large buffer method to calculate cursor watermark */
1137         line_time_us = max(htotal * 1000 / clock, 1);
1138         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1139         entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1140         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141         if (tlb_miss > 0)
1142                 entries += tlb_miss;
1143         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144         *cursor_wm = entries + cursor->guard_size;
1145         if (*cursor_wm > (int)cursor->max_wm)
1146                 *cursor_wm = (int)cursor->max_wm;
1147
1148         return true;
1149 }
1150
1151 /*
1152  * Check the wm result.
1153  *
1154  * If any calculated watermark values is larger than the maximum value that
1155  * can be programmed into the associated watermark register, that watermark
1156  * must be disabled.
1157  */
1158 static bool g4x_check_srwm(struct drm_device *dev,
1159                            int display_wm, int cursor_wm,
1160                            const struct intel_watermark_params *display,
1161                            const struct intel_watermark_params *cursor)
1162 {
1163         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164                       display_wm, cursor_wm);
1165
1166         if (display_wm > display->max_wm) {
1167                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168                               display_wm, display->max_wm);
1169                 return false;
1170         }
1171
1172         if (cursor_wm > cursor->max_wm) {
1173                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174                               cursor_wm, cursor->max_wm);
1175                 return false;
1176         }
1177
1178         if (!(display_wm || cursor_wm)) {
1179                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1180                 return false;
1181         }
1182
1183         return true;
1184 }
1185
1186 static bool g4x_compute_srwm(struct drm_device *dev,
1187                              int plane,
1188                              int latency_ns,
1189                              const struct intel_watermark_params *display,
1190                              const struct intel_watermark_params *cursor,
1191                              int *display_wm, int *cursor_wm)
1192 {
1193         struct drm_crtc *crtc;
1194         const struct drm_display_mode *adjusted_mode;
1195         int hdisplay, htotal, pixel_size, clock;
1196         unsigned long line_time_us;
1197         int line_count, line_size;
1198         int small, large;
1199         int entries;
1200
1201         if (!latency_ns) {
1202                 *display_wm = *cursor_wm = 0;
1203                 return false;
1204         }
1205
1206         crtc = intel_get_crtc_for_plane(dev, plane);
1207         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1208         clock = adjusted_mode->crtc_clock;
1209         htotal = adjusted_mode->crtc_htotal;
1210         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1211         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1212
1213         line_time_us = max(htotal * 1000 / clock, 1);
1214         line_count = (latency_ns / line_time_us + 1000) / 1000;
1215         line_size = hdisplay * pixel_size;
1216
1217         /* Use the minimum of the small and large buffer method for primary */
1218         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219         large = line_count * line_size;
1220
1221         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222         *display_wm = entries + display->guard_size;
1223
1224         /* calculate the self-refresh watermark for display cursor */
1225         entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1226         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227         *cursor_wm = entries + cursor->guard_size;
1228
1229         return g4x_check_srwm(dev,
1230                               *display_wm, *cursor_wm,
1231                               display, cursor);
1232 }
1233
1234 static bool vlv_compute_drain_latency(struct drm_device *dev,
1235                                      int plane,
1236                                      int *plane_prec_mult,
1237                                      int *plane_dl,
1238                                      int *cursor_prec_mult,
1239                                      int *cursor_dl)
1240 {
1241         struct drm_crtc *crtc;
1242         int clock, pixel_size;
1243         int entries;
1244
1245         crtc = intel_get_crtc_for_plane(dev, plane);
1246         if (!intel_crtc_active(crtc))
1247                 return false;
1248
1249         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1250         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
1251
1252         entries = (clock / 1000) * pixel_size;
1253         *plane_prec_mult = (entries > 256) ?
1254                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1256                                                      pixel_size);
1257
1258         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1259         *cursor_prec_mult = (entries > 256) ?
1260                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1262
1263         return true;
1264 }
1265
1266 /*
1267  * Update drain latency registers of memory arbiter
1268  *
1269  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270  * to be programmed. Each plane has a drain latency multiplier and a drain
1271  * latency value.
1272  */
1273
1274 static void vlv_update_drain_latency(struct drm_device *dev)
1275 {
1276         struct drm_i915_private *dev_priv = dev->dev_private;
1277         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1280                                                         either 16 or 32 */
1281
1282         /* For plane A, Cursor A */
1283         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284                                       &cursor_prec_mult, &cursora_dl)) {
1285                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289
1290                 I915_WRITE(VLV_DDL1, cursora_prec |
1291                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1292                                 planea_prec | planea_dl);
1293         }
1294
1295         /* For plane B, Cursor B */
1296         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297                                       &cursor_prec_mult, &cursorb_dl)) {
1298                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302
1303                 I915_WRITE(VLV_DDL2, cursorb_prec |
1304                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305                                 planeb_prec | planeb_dl);
1306         }
1307 }
1308
1309 #define single_plane_enabled(mask) is_power_of_2(mask)
1310
1311 static void valleyview_update_wm(struct drm_crtc *crtc)
1312 {
1313         struct drm_device *dev = crtc->dev;
1314         static const int sr_latency_ns = 12000;
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317         int plane_sr, cursor_sr;
1318         int ignore_plane_sr, ignore_cursor_sr;
1319         unsigned int enabled = 0;
1320
1321         vlv_update_drain_latency(dev);
1322
1323         if (g4x_compute_wm0(dev, PIPE_A,
1324                             &valleyview_wm_info, latency_ns,
1325                             &valleyview_cursor_wm_info, latency_ns,
1326                             &planea_wm, &cursora_wm))
1327                 enabled |= 1 << PIPE_A;
1328
1329         if (g4x_compute_wm0(dev, PIPE_B,
1330                             &valleyview_wm_info, latency_ns,
1331                             &valleyview_cursor_wm_info, latency_ns,
1332                             &planeb_wm, &cursorb_wm))
1333                 enabled |= 1 << PIPE_B;
1334
1335         if (single_plane_enabled(enabled) &&
1336             g4x_compute_srwm(dev, ffs(enabled) - 1,
1337                              sr_latency_ns,
1338                              &valleyview_wm_info,
1339                              &valleyview_cursor_wm_info,
1340                              &plane_sr, &ignore_cursor_sr) &&
1341             g4x_compute_srwm(dev, ffs(enabled) - 1,
1342                              2*sr_latency_ns,
1343                              &valleyview_wm_info,
1344                              &valleyview_cursor_wm_info,
1345                              &ignore_plane_sr, &cursor_sr)) {
1346                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1347         } else {
1348                 I915_WRITE(FW_BLC_SELF_VLV,
1349                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1350                 plane_sr = cursor_sr = 0;
1351         }
1352
1353         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354                       planea_wm, cursora_wm,
1355                       planeb_wm, cursorb_wm,
1356                       plane_sr, cursor_sr);
1357
1358         I915_WRITE(DSPFW1,
1359                    (plane_sr << DSPFW_SR_SHIFT) |
1360                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1362                    planea_wm);
1363         I915_WRITE(DSPFW2,
1364                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1365                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1366         I915_WRITE(DSPFW3,
1367                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1369 }
1370
1371 static void g4x_update_wm(struct drm_crtc *crtc)
1372 {
1373         struct drm_device *dev = crtc->dev;
1374         static const int sr_latency_ns = 12000;
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377         int plane_sr, cursor_sr;
1378         unsigned int enabled = 0;
1379
1380         if (g4x_compute_wm0(dev, PIPE_A,
1381                             &g4x_wm_info, latency_ns,
1382                             &g4x_cursor_wm_info, latency_ns,
1383                             &planea_wm, &cursora_wm))
1384                 enabled |= 1 << PIPE_A;
1385
1386         if (g4x_compute_wm0(dev, PIPE_B,
1387                             &g4x_wm_info, latency_ns,
1388                             &g4x_cursor_wm_info, latency_ns,
1389                             &planeb_wm, &cursorb_wm))
1390                 enabled |= 1 << PIPE_B;
1391
1392         if (single_plane_enabled(enabled) &&
1393             g4x_compute_srwm(dev, ffs(enabled) - 1,
1394                              sr_latency_ns,
1395                              &g4x_wm_info,
1396                              &g4x_cursor_wm_info,
1397                              &plane_sr, &cursor_sr)) {
1398                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1399         } else {
1400                 I915_WRITE(FW_BLC_SELF,
1401                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1402                 plane_sr = cursor_sr = 0;
1403         }
1404
1405         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406                       planea_wm, cursora_wm,
1407                       planeb_wm, cursorb_wm,
1408                       plane_sr, cursor_sr);
1409
1410         I915_WRITE(DSPFW1,
1411                    (plane_sr << DSPFW_SR_SHIFT) |
1412                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1414                    planea_wm);
1415         I915_WRITE(DSPFW2,
1416                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1417                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1418         /* HPLL off in SR has some issues on G4x... disable it */
1419         I915_WRITE(DSPFW3,
1420                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1421                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1422 }
1423
1424 static void i965_update_wm(struct drm_crtc *unused_crtc)
1425 {
1426         struct drm_device *dev = unused_crtc->dev;
1427         struct drm_i915_private *dev_priv = dev->dev_private;
1428         struct drm_crtc *crtc;
1429         int srwm = 1;
1430         int cursor_sr = 16;
1431
1432         /* Calc sr entries for one plane configs */
1433         crtc = single_enabled_crtc(dev);
1434         if (crtc) {
1435                 /* self-refresh has much higher latency */
1436                 static const int sr_latency_ns = 12000;
1437                 const struct drm_display_mode *adjusted_mode =
1438                         &to_intel_crtc(crtc)->config.adjusted_mode;
1439                 int clock = adjusted_mode->crtc_clock;
1440                 int htotal = adjusted_mode->crtc_htotal;
1441                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1442                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1443                 unsigned long line_time_us;
1444                 int entries;
1445
1446                 line_time_us = max(htotal * 1000 / clock, 1);
1447
1448                 /* Use ns/us then divide to preserve precision */
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         pixel_size * hdisplay;
1451                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452                 srwm = I965_FIFO_SIZE - entries;
1453                 if (srwm < 0)
1454                         srwm = 1;
1455                 srwm &= 0x1ff;
1456                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457                               entries, srwm);
1458
1459                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1460                         pixel_size * to_intel_crtc(crtc)->cursor_width;
1461                 entries = DIV_ROUND_UP(entries,
1462                                           i965_cursor_wm_info.cacheline_size);
1463                 cursor_sr = i965_cursor_wm_info.fifo_size -
1464                         (entries + i965_cursor_wm_info.guard_size);
1465
1466                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467                         cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470                               "cursor %d\n", srwm, cursor_sr);
1471
1472                 if (IS_CRESTLINE(dev))
1473                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474         } else {
1475                 /* Turn off self refresh if both pipes are enabled */
1476                 if (IS_CRESTLINE(dev))
1477                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1478                                    & ~FW_BLC_SELF_EN);
1479         }
1480
1481         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482                       srwm);
1483
1484         /* 965 has limitations... */
1485         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486                    (8 << 16) | (8 << 8) | (8 << 0));
1487         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488         /* update cursor SR watermark */
1489         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490 }
1491
1492 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1493 {
1494         struct drm_device *dev = unused_crtc->dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         const struct intel_watermark_params *wm_info;
1497         uint32_t fwater_lo;
1498         uint32_t fwater_hi;
1499         int cwm, srwm = 1;
1500         int fifo_size;
1501         int planea_wm, planeb_wm;
1502         struct drm_crtc *crtc, *enabled = NULL;
1503
1504         if (IS_I945GM(dev))
1505                 wm_info = &i945_wm_info;
1506         else if (!IS_GEN2(dev))
1507                 wm_info = &i915_wm_info;
1508         else
1509                 wm_info = &i830_wm_info;
1510
1511         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512         crtc = intel_get_crtc_for_plane(dev, 0);
1513         if (intel_crtc_active(crtc)) {
1514                 const struct drm_display_mode *adjusted_mode;
1515                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1516                 if (IS_GEN2(dev))
1517                         cpp = 4;
1518
1519                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1521                                                wm_info, fifo_size, cpp,
1522                                                latency_ns);
1523                 enabled = crtc;
1524         } else
1525                 planea_wm = fifo_size - wm_info->guard_size;
1526
1527         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528         crtc = intel_get_crtc_for_plane(dev, 1);
1529         if (intel_crtc_active(crtc)) {
1530                 const struct drm_display_mode *adjusted_mode;
1531                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1532                 if (IS_GEN2(dev))
1533                         cpp = 4;
1534
1535                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1537                                                wm_info, fifo_size, cpp,
1538                                                latency_ns);
1539                 if (enabled == NULL)
1540                         enabled = crtc;
1541                 else
1542                         enabled = NULL;
1543         } else
1544                 planeb_wm = fifo_size - wm_info->guard_size;
1545
1546         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548         if (IS_I915GM(dev) && enabled) {
1549                 struct intel_framebuffer *fb;
1550
1551                 fb = to_intel_framebuffer(enabled->primary->fb);
1552
1553                 /* self-refresh seems busted with untiled */
1554                 if (fb->obj->tiling_mode == I915_TILING_NONE)
1555                         enabled = NULL;
1556         }
1557
1558         /*
1559          * Overlay gets an aggressive default since video jitter is bad.
1560          */
1561         cwm = 2;
1562
1563         /* Play safe and disable self-refresh before adjusting watermarks. */
1564         if (IS_I945G(dev) || IS_I945GM(dev))
1565                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1566         else if (IS_I915GM(dev))
1567                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1568
1569         /* Calc sr entries for one plane configs */
1570         if (HAS_FW_BLC(dev) && enabled) {
1571                 /* self-refresh has much higher latency */
1572                 static const int sr_latency_ns = 6000;
1573                 const struct drm_display_mode *adjusted_mode =
1574                         &to_intel_crtc(enabled)->config.adjusted_mode;
1575                 int clock = adjusted_mode->crtc_clock;
1576                 int htotal = adjusted_mode->crtc_htotal;
1577                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1578                 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1579                 unsigned long line_time_us;
1580                 int entries;
1581
1582                 line_time_us = max(htotal * 1000 / clock, 1);
1583
1584                 /* Use ns/us then divide to preserve precision */
1585                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586                         pixel_size * hdisplay;
1587                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589                 srwm = wm_info->fifo_size - entries;
1590                 if (srwm < 0)
1591                         srwm = 1;
1592
1593                 if (IS_I945G(dev) || IS_I945GM(dev))
1594                         I915_WRITE(FW_BLC_SELF,
1595                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596                 else if (IS_I915GM(dev))
1597                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1598         }
1599
1600         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601                       planea_wm, planeb_wm, cwm, srwm);
1602
1603         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604         fwater_hi = (cwm & 0x1f);
1605
1606         /* Set request length to 8 cachelines per fetch */
1607         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608         fwater_hi = fwater_hi | (1 << 8);
1609
1610         I915_WRITE(FW_BLC, fwater_lo);
1611         I915_WRITE(FW_BLC2, fwater_hi);
1612
1613         if (HAS_FW_BLC(dev)) {
1614                 if (enabled) {
1615                         if (IS_I945G(dev) || IS_I945GM(dev))
1616                                 I915_WRITE(FW_BLC_SELF,
1617                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1618                         else if (IS_I915GM(dev))
1619                                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1620                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1621                 } else
1622                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1623         }
1624 }
1625
1626 static void i845_update_wm(struct drm_crtc *unused_crtc)
1627 {
1628         struct drm_device *dev = unused_crtc->dev;
1629         struct drm_i915_private *dev_priv = dev->dev_private;
1630         struct drm_crtc *crtc;
1631         const struct drm_display_mode *adjusted_mode;
1632         uint32_t fwater_lo;
1633         int planea_wm;
1634
1635         crtc = single_enabled_crtc(dev);
1636         if (crtc == NULL)
1637                 return;
1638
1639         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1641                                        &i845_wm_info,
1642                                        dev_priv->display.get_fifo_size(dev, 0),
1643                                        4, latency_ns);
1644         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645         fwater_lo |= (3<<8) | planea_wm;
1646
1647         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649         I915_WRITE(FW_BLC, fwater_lo);
1650 }
1651
1652 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1653                                     struct drm_crtc *crtc)
1654 {
1655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1656         uint32_t pixel_rate;
1657
1658         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1659
1660         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661          * adjust the pixel_rate here. */
1662
1663         if (intel_crtc->config.pch_pfit.enabled) {
1664                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1665                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1666
1667                 pipe_w = intel_crtc->config.pipe_src_w;
1668                 pipe_h = intel_crtc->config.pipe_src_h;
1669                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670                 pfit_h = pfit_size & 0xFFFF;
1671                 if (pipe_w < pfit_w)
1672                         pipe_w = pfit_w;
1673                 if (pipe_h < pfit_h)
1674                         pipe_h = pfit_h;
1675
1676                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1677                                      pfit_w * pfit_h);
1678         }
1679
1680         return pixel_rate;
1681 }
1682
1683 /* latency must be in 0.1us units. */
1684 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1685                                uint32_t latency)
1686 {
1687         uint64_t ret;
1688
1689         if (WARN(latency == 0, "Latency value missing\n"))
1690                 return UINT_MAX;
1691
1692         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1693         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1694
1695         return ret;
1696 }
1697
1698 /* latency must be in 0.1us units. */
1699 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1700                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1701                                uint32_t latency)
1702 {
1703         uint32_t ret;
1704
1705         if (WARN(latency == 0, "Latency value missing\n"))
1706                 return UINT_MAX;
1707
1708         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1709         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1710         ret = DIV_ROUND_UP(ret, 64) + 2;
1711         return ret;
1712 }
1713
1714 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1715                            uint8_t bytes_per_pixel)
1716 {
1717         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1718 }
1719
1720 struct ilk_pipe_wm_parameters {
1721         bool active;
1722         uint32_t pipe_htotal;
1723         uint32_t pixel_rate;
1724         struct intel_plane_wm_parameters pri;
1725         struct intel_plane_wm_parameters spr;
1726         struct intel_plane_wm_parameters cur;
1727 };
1728
1729 struct ilk_wm_maximums {
1730         uint16_t pri;
1731         uint16_t spr;
1732         uint16_t cur;
1733         uint16_t fbc;
1734 };
1735
1736 /* used in computing the new watermarks state */
1737 struct intel_wm_config {
1738         unsigned int num_pipes_active;
1739         bool sprites_enabled;
1740         bool sprites_scaled;
1741 };
1742
1743 /*
1744  * For both WM_PIPE and WM_LP.
1745  * mem_value must be in 0.1us units.
1746  */
1747 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1748                                    uint32_t mem_value,
1749                                    bool is_lp)
1750 {
1751         uint32_t method1, method2;
1752
1753         if (!params->active || !params->pri.enabled)
1754                 return 0;
1755
1756         method1 = ilk_wm_method1(params->pixel_rate,
1757                                  params->pri.bytes_per_pixel,
1758                                  mem_value);
1759
1760         if (!is_lp)
1761                 return method1;
1762
1763         method2 = ilk_wm_method2(params->pixel_rate,
1764                                  params->pipe_htotal,
1765                                  params->pri.horiz_pixels,
1766                                  params->pri.bytes_per_pixel,
1767                                  mem_value);
1768
1769         return min(method1, method2);
1770 }
1771
1772 /*
1773  * For both WM_PIPE and WM_LP.
1774  * mem_value must be in 0.1us units.
1775  */
1776 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1777                                    uint32_t mem_value)
1778 {
1779         uint32_t method1, method2;
1780
1781         if (!params->active || !params->spr.enabled)
1782                 return 0;
1783
1784         method1 = ilk_wm_method1(params->pixel_rate,
1785                                  params->spr.bytes_per_pixel,
1786                                  mem_value);
1787         method2 = ilk_wm_method2(params->pixel_rate,
1788                                  params->pipe_htotal,
1789                                  params->spr.horiz_pixels,
1790                                  params->spr.bytes_per_pixel,
1791                                  mem_value);
1792         return min(method1, method2);
1793 }
1794
1795 /*
1796  * For both WM_PIPE and WM_LP.
1797  * mem_value must be in 0.1us units.
1798  */
1799 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1800                                    uint32_t mem_value)
1801 {
1802         if (!params->active || !params->cur.enabled)
1803                 return 0;
1804
1805         return ilk_wm_method2(params->pixel_rate,
1806                               params->pipe_htotal,
1807                               params->cur.horiz_pixels,
1808                               params->cur.bytes_per_pixel,
1809                               mem_value);
1810 }
1811
1812 /* Only for WM_LP. */
1813 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1814                                    uint32_t pri_val)
1815 {
1816         if (!params->active || !params->pri.enabled)
1817                 return 0;
1818
1819         return ilk_wm_fbc(pri_val,
1820                           params->pri.horiz_pixels,
1821                           params->pri.bytes_per_pixel);
1822 }
1823
1824 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1825 {
1826         if (INTEL_INFO(dev)->gen >= 8)
1827                 return 3072;
1828         else if (INTEL_INFO(dev)->gen >= 7)
1829                 return 768;
1830         else
1831                 return 512;
1832 }
1833
1834 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1835                                          int level, bool is_sprite)
1836 {
1837         if (INTEL_INFO(dev)->gen >= 8)
1838                 /* BDW primary/sprite plane watermarks */
1839                 return level == 0 ? 255 : 2047;
1840         else if (INTEL_INFO(dev)->gen >= 7)
1841                 /* IVB/HSW primary/sprite plane watermarks */
1842                 return level == 0 ? 127 : 1023;
1843         else if (!is_sprite)
1844                 /* ILK/SNB primary plane watermarks */
1845                 return level == 0 ? 127 : 511;
1846         else
1847                 /* ILK/SNB sprite plane watermarks */
1848                 return level == 0 ? 63 : 255;
1849 }
1850
1851 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1852                                           int level)
1853 {
1854         if (INTEL_INFO(dev)->gen >= 7)
1855                 return level == 0 ? 63 : 255;
1856         else
1857                 return level == 0 ? 31 : 63;
1858 }
1859
1860 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1861 {
1862         if (INTEL_INFO(dev)->gen >= 8)
1863                 return 31;
1864         else
1865                 return 15;
1866 }
1867
1868 /* Calculate the maximum primary/sprite plane watermark */
1869 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1870                                      int level,
1871                                      const struct intel_wm_config *config,
1872                                      enum intel_ddb_partitioning ddb_partitioning,
1873                                      bool is_sprite)
1874 {
1875         unsigned int fifo_size = ilk_display_fifo_size(dev);
1876
1877         /* if sprites aren't enabled, sprites get nothing */
1878         if (is_sprite && !config->sprites_enabled)
1879                 return 0;
1880
1881         /* HSW allows LP1+ watermarks even with multiple pipes */
1882         if (level == 0 || config->num_pipes_active > 1) {
1883                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1884
1885                 /*
1886                  * For some reason the non self refresh
1887                  * FIFO size is only half of the self
1888                  * refresh FIFO size on ILK/SNB.
1889                  */
1890                 if (INTEL_INFO(dev)->gen <= 6)
1891                         fifo_size /= 2;
1892         }
1893
1894         if (config->sprites_enabled) {
1895                 /* level 0 is always calculated with 1:1 split */
1896                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1897                         if (is_sprite)
1898                                 fifo_size *= 5;
1899                         fifo_size /= 6;
1900                 } else {
1901                         fifo_size /= 2;
1902                 }
1903         }
1904
1905         /* clamp to max that the registers can hold */
1906         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1907 }
1908
1909 /* Calculate the maximum cursor plane watermark */
1910 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1911                                       int level,
1912                                       const struct intel_wm_config *config)
1913 {
1914         /* HSW LP1+ watermarks w/ multiple pipes */
1915         if (level > 0 && config->num_pipes_active > 1)
1916                 return 64;
1917
1918         /* otherwise just report max that registers can hold */
1919         return ilk_cursor_wm_reg_max(dev, level);
1920 }
1921
1922 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1923                                     int level,
1924                                     const struct intel_wm_config *config,
1925                                     enum intel_ddb_partitioning ddb_partitioning,
1926                                     struct ilk_wm_maximums *max)
1927 {
1928         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1929         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1930         max->cur = ilk_cursor_wm_max(dev, level, config);
1931         max->fbc = ilk_fbc_wm_reg_max(dev);
1932 }
1933
1934 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1935                                         int level,
1936                                         struct ilk_wm_maximums *max)
1937 {
1938         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1939         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1940         max->cur = ilk_cursor_wm_reg_max(dev, level);
1941         max->fbc = ilk_fbc_wm_reg_max(dev);
1942 }
1943
1944 static bool ilk_validate_wm_level(int level,
1945                                   const struct ilk_wm_maximums *max,
1946                                   struct intel_wm_level *result)
1947 {
1948         bool ret;
1949
1950         /* already determined to be invalid? */
1951         if (!result->enable)
1952                 return false;
1953
1954         result->enable = result->pri_val <= max->pri &&
1955                          result->spr_val <= max->spr &&
1956                          result->cur_val <= max->cur;
1957
1958         ret = result->enable;
1959
1960         /*
1961          * HACK until we can pre-compute everything,
1962          * and thus fail gracefully if LP0 watermarks
1963          * are exceeded...
1964          */
1965         if (level == 0 && !result->enable) {
1966                 if (result->pri_val > max->pri)
1967                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1968                                       level, result->pri_val, max->pri);
1969                 if (result->spr_val > max->spr)
1970                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1971                                       level, result->spr_val, max->spr);
1972                 if (result->cur_val > max->cur)
1973                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1974                                       level, result->cur_val, max->cur);
1975
1976                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1977                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1978                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1979                 result->enable = true;
1980         }
1981
1982         return ret;
1983 }
1984
1985 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1986                                  int level,
1987                                  const struct ilk_pipe_wm_parameters *p,
1988                                  struct intel_wm_level *result)
1989 {
1990         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1991         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1992         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1993
1994         /* WM1+ latency values stored in 0.5us units */
1995         if (level > 0) {
1996                 pri_latency *= 5;
1997                 spr_latency *= 5;
1998                 cur_latency *= 5;
1999         }
2000
2001         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2002         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2003         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2004         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2005         result->enable = true;
2006 }
2007
2008 static uint32_t
2009 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2010 {
2011         struct drm_i915_private *dev_priv = dev->dev_private;
2012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2013         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2014         u32 linetime, ips_linetime;
2015
2016         if (!intel_crtc_active(crtc))
2017                 return 0;
2018
2019         /* The WM are computed with base on how long it takes to fill a single
2020          * row at the given clock rate, multiplied by 8.
2021          * */
2022         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2023                                      mode->crtc_clock);
2024         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2025                                          intel_ddi_get_cdclk_freq(dev_priv));
2026
2027         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2028                PIPE_WM_LINETIME_TIME(linetime);
2029 }
2030
2031 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2032 {
2033         struct drm_i915_private *dev_priv = dev->dev_private;
2034
2035         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2036                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2037
2038                 wm[0] = (sskpd >> 56) & 0xFF;
2039                 if (wm[0] == 0)
2040                         wm[0] = sskpd & 0xF;
2041                 wm[1] = (sskpd >> 4) & 0xFF;
2042                 wm[2] = (sskpd >> 12) & 0xFF;
2043                 wm[3] = (sskpd >> 20) & 0x1FF;
2044                 wm[4] = (sskpd >> 32) & 0x1FF;
2045         } else if (INTEL_INFO(dev)->gen >= 6) {
2046                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2047
2048                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2049                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2050                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2051                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2052         } else if (INTEL_INFO(dev)->gen >= 5) {
2053                 uint32_t mltr = I915_READ(MLTR_ILK);
2054
2055                 /* ILK primary LP0 latency is 700 ns */
2056                 wm[0] = 7;
2057                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2058                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2059         }
2060 }
2061
2062 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2063 {
2064         /* ILK sprite LP0 latency is 1300 ns */
2065         if (INTEL_INFO(dev)->gen == 5)
2066                 wm[0] = 13;
2067 }
2068
2069 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2070 {
2071         /* ILK cursor LP0 latency is 1300 ns */
2072         if (INTEL_INFO(dev)->gen == 5)
2073                 wm[0] = 13;
2074
2075         /* WaDoubleCursorLP3Latency:ivb */
2076         if (IS_IVYBRIDGE(dev))
2077                 wm[3] *= 2;
2078 }
2079
2080 int ilk_wm_max_level(const struct drm_device *dev)
2081 {
2082         /* how many WM levels are we expecting */
2083         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2084                 return 4;
2085         else if (INTEL_INFO(dev)->gen >= 6)
2086                 return 3;
2087         else
2088                 return 2;
2089 }
2090
2091 static void intel_print_wm_latency(struct drm_device *dev,
2092                                    const char *name,
2093                                    const uint16_t wm[5])
2094 {
2095         int level, max_level = ilk_wm_max_level(dev);
2096
2097         for (level = 0; level <= max_level; level++) {
2098                 unsigned int latency = wm[level];
2099
2100                 if (latency == 0) {
2101                         DRM_ERROR("%s WM%d latency not provided\n",
2102                                   name, level);
2103                         continue;
2104                 }
2105
2106                 /* WM1+ latency values in 0.5us units */
2107                 if (level > 0)
2108                         latency *= 5;
2109
2110                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2111                               name, level, wm[level],
2112                               latency / 10, latency % 10);
2113         }
2114 }
2115
2116 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2117                                     uint16_t wm[5], uint16_t min)
2118 {
2119         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2120
2121         if (wm[0] >= min)
2122                 return false;
2123
2124         wm[0] = max(wm[0], min);
2125         for (level = 1; level <= max_level; level++)
2126                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2127
2128         return true;
2129 }
2130
2131 static void snb_wm_latency_quirk(struct drm_device *dev)
2132 {
2133         struct drm_i915_private *dev_priv = dev->dev_private;
2134         bool changed;
2135
2136         /*
2137          * The BIOS provided WM memory latency values are often
2138          * inadequate for high resolution displays. Adjust them.
2139          */
2140         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2141                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2142                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2143
2144         if (!changed)
2145                 return;
2146
2147         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2148         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2149         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2150         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2151 }
2152
2153 static void ilk_setup_wm_latency(struct drm_device *dev)
2154 {
2155         struct drm_i915_private *dev_priv = dev->dev_private;
2156
2157         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2158
2159         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2160                sizeof(dev_priv->wm.pri_latency));
2161         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2162                sizeof(dev_priv->wm.pri_latency));
2163
2164         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2165         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2166
2167         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2168         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2169         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2170
2171         if (IS_GEN6(dev))
2172                 snb_wm_latency_quirk(dev);
2173 }
2174
2175 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2176                                       struct ilk_pipe_wm_parameters *p)
2177 {
2178         struct drm_device *dev = crtc->dev;
2179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180         enum pipe pipe = intel_crtc->pipe;
2181         struct drm_plane *plane;
2182
2183         if (!intel_crtc_active(crtc))
2184                 return;
2185
2186         p->active = true;
2187         p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2188         p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2189         p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2190         p->cur.bytes_per_pixel = 4;
2191         p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2192         p->cur.horiz_pixels = intel_crtc->cursor_width;
2193         /* TODO: for now, assume primary and cursor planes are always enabled. */
2194         p->pri.enabled = true;
2195         p->cur.enabled = true;
2196
2197         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2198                 struct intel_plane *intel_plane = to_intel_plane(plane);
2199
2200                 if (intel_plane->pipe == pipe) {
2201                         p->spr = intel_plane->wm;
2202                         break;
2203                 }
2204         }
2205 }
2206
2207 static void ilk_compute_wm_config(struct drm_device *dev,
2208                                   struct intel_wm_config *config)
2209 {
2210         struct intel_crtc *intel_crtc;
2211
2212         /* Compute the currently _active_ config */
2213         for_each_intel_crtc(dev, intel_crtc) {
2214                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2215
2216                 if (!wm->pipe_enabled)
2217                         continue;
2218
2219                 config->sprites_enabled |= wm->sprites_enabled;
2220                 config->sprites_scaled |= wm->sprites_scaled;
2221                 config->num_pipes_active++;
2222         }
2223 }
2224
2225 /* Compute new watermarks for the pipe */
2226 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2227                                   const struct ilk_pipe_wm_parameters *params,
2228                                   struct intel_pipe_wm *pipe_wm)
2229 {
2230         struct drm_device *dev = crtc->dev;
2231         const struct drm_i915_private *dev_priv = dev->dev_private;
2232         int level, max_level = ilk_wm_max_level(dev);
2233         /* LP0 watermark maximums depend on this pipe alone */
2234         struct intel_wm_config config = {
2235                 .num_pipes_active = 1,
2236                 .sprites_enabled = params->spr.enabled,
2237                 .sprites_scaled = params->spr.scaled,
2238         };
2239         struct ilk_wm_maximums max;
2240
2241         pipe_wm->pipe_enabled = params->active;
2242         pipe_wm->sprites_enabled = params->spr.enabled;
2243         pipe_wm->sprites_scaled = params->spr.scaled;
2244
2245         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2246         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2247                 max_level = 1;
2248
2249         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2250         if (params->spr.scaled)
2251                 max_level = 0;
2252
2253         ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2254
2255         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2256                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2257
2258         /* LP0 watermarks always use 1/2 DDB partitioning */
2259         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2260
2261         /* At least LP0 must be valid */
2262         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2263                 return false;
2264
2265         ilk_compute_wm_reg_maximums(dev, 1, &max);
2266
2267         for (level = 1; level <= max_level; level++) {
2268                 struct intel_wm_level wm = {};
2269
2270                 ilk_compute_wm_level(dev_priv, level, params, &wm);
2271
2272                 /*
2273                  * Disable any watermark level that exceeds the
2274                  * register maximums since such watermarks are
2275                  * always invalid.
2276                  */
2277                 if (!ilk_validate_wm_level(level, &max, &wm))
2278                         break;
2279
2280                 pipe_wm->wm[level] = wm;
2281         }
2282
2283         return true;
2284 }
2285
2286 /*
2287  * Merge the watermarks from all active pipes for a specific level.
2288  */
2289 static void ilk_merge_wm_level(struct drm_device *dev,
2290                                int level,
2291                                struct intel_wm_level *ret_wm)
2292 {
2293         const struct intel_crtc *intel_crtc;
2294
2295         ret_wm->enable = true;
2296
2297         for_each_intel_crtc(dev, intel_crtc) {
2298                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2299                 const struct intel_wm_level *wm = &active->wm[level];
2300
2301                 if (!active->pipe_enabled)
2302                         continue;
2303
2304                 /*
2305                  * The watermark values may have been used in the past,
2306                  * so we must maintain them in the registers for some
2307                  * time even if the level is now disabled.
2308                  */
2309                 if (!wm->enable)
2310                         ret_wm->enable = false;
2311
2312                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2313                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2314                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2315                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2316         }
2317 }
2318
2319 /*
2320  * Merge all low power watermarks for all active pipes.
2321  */
2322 static void ilk_wm_merge(struct drm_device *dev,
2323                          const struct intel_wm_config *config,
2324                          const struct ilk_wm_maximums *max,
2325                          struct intel_pipe_wm *merged)
2326 {
2327         int level, max_level = ilk_wm_max_level(dev);
2328         int last_enabled_level = max_level;
2329
2330         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2331         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2332             config->num_pipes_active > 1)
2333                 return;
2334
2335         /* ILK: FBC WM must be disabled always */
2336         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2337
2338         /* merge each WM1+ level */
2339         for (level = 1; level <= max_level; level++) {
2340                 struct intel_wm_level *wm = &merged->wm[level];
2341
2342                 ilk_merge_wm_level(dev, level, wm);
2343
2344                 if (level > last_enabled_level)
2345                         wm->enable = false;
2346                 else if (!ilk_validate_wm_level(level, max, wm))
2347                         /* make sure all following levels get disabled */
2348                         last_enabled_level = level - 1;
2349
2350                 /*
2351                  * The spec says it is preferred to disable
2352                  * FBC WMs instead of disabling a WM level.
2353                  */
2354                 if (wm->fbc_val > max->fbc) {
2355                         if (wm->enable)
2356                                 merged->fbc_wm_enabled = false;
2357                         wm->fbc_val = 0;
2358                 }
2359         }
2360
2361         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2362         /*
2363          * FIXME this is racy. FBC might get enabled later.
2364          * What we should check here is whether FBC can be
2365          * enabled sometime later.
2366          */
2367         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2368                 for (level = 2; level <= max_level; level++) {
2369                         struct intel_wm_level *wm = &merged->wm[level];
2370
2371                         wm->enable = false;
2372                 }
2373         }
2374 }
2375
2376 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2377 {
2378         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2379         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2380 }
2381
2382 /* The value we need to program into the WM_LPx latency field */
2383 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2384 {
2385         struct drm_i915_private *dev_priv = dev->dev_private;
2386
2387         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2388                 return 2 * level;
2389         else
2390                 return dev_priv->wm.pri_latency[level];
2391 }
2392
2393 static void ilk_compute_wm_results(struct drm_device *dev,
2394                                    const struct intel_pipe_wm *merged,
2395                                    enum intel_ddb_partitioning partitioning,
2396                                    struct ilk_wm_values *results)
2397 {
2398         struct intel_crtc *intel_crtc;
2399         int level, wm_lp;
2400
2401         results->enable_fbc_wm = merged->fbc_wm_enabled;
2402         results->partitioning = partitioning;
2403
2404         /* LP1+ register values */
2405         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2406                 const struct intel_wm_level *r;
2407
2408                 level = ilk_wm_lp_to_level(wm_lp, merged);
2409
2410                 r = &merged->wm[level];
2411
2412                 /*
2413                  * Maintain the watermark values even if the level is
2414                  * disabled. Doing otherwise could cause underruns.
2415                  */
2416                 results->wm_lp[wm_lp - 1] =
2417                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2418                         (r->pri_val << WM1_LP_SR_SHIFT) |
2419                         r->cur_val;
2420
2421                 if (r->enable)
2422                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2423
2424                 if (INTEL_INFO(dev)->gen >= 8)
2425                         results->wm_lp[wm_lp - 1] |=
2426                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2427                 else
2428                         results->wm_lp[wm_lp - 1] |=
2429                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2430
2431                 /*
2432                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2433                  * level is disabled. Doing otherwise could cause underruns.
2434                  */
2435                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2436                         WARN_ON(wm_lp != 1);
2437                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2438                 } else
2439                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2440         }
2441
2442         /* LP0 register values */
2443         for_each_intel_crtc(dev, intel_crtc) {
2444                 enum pipe pipe = intel_crtc->pipe;
2445                 const struct intel_wm_level *r =
2446                         &intel_crtc->wm.active.wm[0];
2447
2448                 if (WARN_ON(!r->enable))
2449                         continue;
2450
2451                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2452
2453                 results->wm_pipe[pipe] =
2454                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2455                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2456                         r->cur_val;
2457         }
2458 }
2459
2460 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2461  * case both are at the same level. Prefer r1 in case they're the same. */
2462 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2463                                                   struct intel_pipe_wm *r1,
2464                                                   struct intel_pipe_wm *r2)
2465 {
2466         int level, max_level = ilk_wm_max_level(dev);
2467         int level1 = 0, level2 = 0;
2468
2469         for (level = 1; level <= max_level; level++) {
2470                 if (r1->wm[level].enable)
2471                         level1 = level;
2472                 if (r2->wm[level].enable)
2473                         level2 = level;
2474         }
2475
2476         if (level1 == level2) {
2477                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2478                         return r2;
2479                 else
2480                         return r1;
2481         } else if (level1 > level2) {
2482                 return r1;
2483         } else {
2484                 return r2;
2485         }
2486 }
2487
2488 /* dirty bits used to track which watermarks need changes */
2489 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2490 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2491 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2492 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2493 #define WM_DIRTY_FBC (1 << 24)
2494 #define WM_DIRTY_DDB (1 << 25)
2495
2496 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2497                                          const struct ilk_wm_values *old,
2498                                          const struct ilk_wm_values *new)
2499 {
2500         unsigned int dirty = 0;
2501         enum pipe pipe;
2502         int wm_lp;
2503
2504         for_each_pipe(pipe) {
2505                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2506                         dirty |= WM_DIRTY_LINETIME(pipe);
2507                         /* Must disable LP1+ watermarks too */
2508                         dirty |= WM_DIRTY_LP_ALL;
2509                 }
2510
2511                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2512                         dirty |= WM_DIRTY_PIPE(pipe);
2513                         /* Must disable LP1+ watermarks too */
2514                         dirty |= WM_DIRTY_LP_ALL;
2515                 }
2516         }
2517
2518         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2519                 dirty |= WM_DIRTY_FBC;
2520                 /* Must disable LP1+ watermarks too */
2521                 dirty |= WM_DIRTY_LP_ALL;
2522         }
2523
2524         if (old->partitioning != new->partitioning) {
2525                 dirty |= WM_DIRTY_DDB;
2526                 /* Must disable LP1+ watermarks too */
2527                 dirty |= WM_DIRTY_LP_ALL;
2528         }
2529
2530         /* LP1+ watermarks already deemed dirty, no need to continue */
2531         if (dirty & WM_DIRTY_LP_ALL)
2532                 return dirty;
2533
2534         /* Find the lowest numbered LP1+ watermark in need of an update... */
2535         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2536                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2537                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2538                         break;
2539         }
2540
2541         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2542         for (; wm_lp <= 3; wm_lp++)
2543                 dirty |= WM_DIRTY_LP(wm_lp);
2544
2545         return dirty;
2546 }
2547
2548 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2549                                unsigned int dirty)
2550 {
2551         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2552         bool changed = false;
2553
2554         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2555                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2556                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2557                 changed = true;
2558         }
2559         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2560                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2561                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2562                 changed = true;
2563         }
2564         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2565                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2566                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2567                 changed = true;
2568         }
2569
2570         /*
2571          * Don't touch WM1S_LP_EN here.
2572          * Doing so could cause underruns.
2573          */
2574
2575         return changed;
2576 }
2577
2578 /*
2579  * The spec says we shouldn't write when we don't need, because every write
2580  * causes WMs to be re-evaluated, expending some power.
2581  */
2582 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2583                                 struct ilk_wm_values *results)
2584 {
2585         struct drm_device *dev = dev_priv->dev;
2586         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2587         unsigned int dirty;
2588         uint32_t val;
2589
2590         dirty = ilk_compute_wm_dirty(dev, previous, results);
2591         if (!dirty)
2592                 return;
2593
2594         _ilk_disable_lp_wm(dev_priv, dirty);
2595
2596         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2597                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2598         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2599                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2600         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2601                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2602
2603         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2604                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2605         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2606                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2607         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2608                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2609
2610         if (dirty & WM_DIRTY_DDB) {
2611                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2612                         val = I915_READ(WM_MISC);
2613                         if (results->partitioning == INTEL_DDB_PART_1_2)
2614                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2615                         else
2616                                 val |= WM_MISC_DATA_PARTITION_5_6;
2617                         I915_WRITE(WM_MISC, val);
2618                 } else {
2619                         val = I915_READ(DISP_ARB_CTL2);
2620                         if (results->partitioning == INTEL_DDB_PART_1_2)
2621                                 val &= ~DISP_DATA_PARTITION_5_6;
2622                         else
2623                                 val |= DISP_DATA_PARTITION_5_6;
2624                         I915_WRITE(DISP_ARB_CTL2, val);
2625                 }
2626         }
2627
2628         if (dirty & WM_DIRTY_FBC) {
2629                 val = I915_READ(DISP_ARB_CTL);
2630                 if (results->enable_fbc_wm)
2631                         val &= ~DISP_FBC_WM_DIS;
2632                 else
2633                         val |= DISP_FBC_WM_DIS;
2634                 I915_WRITE(DISP_ARB_CTL, val);
2635         }
2636
2637         if (dirty & WM_DIRTY_LP(1) &&
2638             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2639                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2640
2641         if (INTEL_INFO(dev)->gen >= 7) {
2642                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2643                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2644                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2645                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2646         }
2647
2648         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2649                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2650         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2651                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2652         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2653                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2654
2655         dev_priv->wm.hw = *results;
2656 }
2657
2658 static bool ilk_disable_lp_wm(struct drm_device *dev)
2659 {
2660         struct drm_i915_private *dev_priv = dev->dev_private;
2661
2662         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2663 }
2664
2665 static void ilk_update_wm(struct drm_crtc *crtc)
2666 {
2667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2668         struct drm_device *dev = crtc->dev;
2669         struct drm_i915_private *dev_priv = dev->dev_private;
2670         struct ilk_wm_maximums max;
2671         struct ilk_pipe_wm_parameters params = {};
2672         struct ilk_wm_values results = {};
2673         enum intel_ddb_partitioning partitioning;
2674         struct intel_pipe_wm pipe_wm = {};
2675         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2676         struct intel_wm_config config = {};
2677
2678         ilk_compute_wm_parameters(crtc, &params);
2679
2680         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2681
2682         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2683                 return;
2684
2685         intel_crtc->wm.active = pipe_wm;
2686
2687         ilk_compute_wm_config(dev, &config);
2688
2689         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2690         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2691
2692         /* 5/6 split only in single pipe config on IVB+ */
2693         if (INTEL_INFO(dev)->gen >= 7 &&
2694             config.num_pipes_active == 1 && config.sprites_enabled) {
2695                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2696                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2697
2698                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2699         } else {
2700                 best_lp_wm = &lp_wm_1_2;
2701         }
2702
2703         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2704                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2705
2706         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2707
2708         ilk_write_wm_values(dev_priv, &results);
2709 }
2710
2711 static void ilk_update_sprite_wm(struct drm_plane *plane,
2712                                      struct drm_crtc *crtc,
2713                                      uint32_t sprite_width, int pixel_size,
2714                                      bool enabled, bool scaled)
2715 {
2716         struct drm_device *dev = plane->dev;
2717         struct intel_plane *intel_plane = to_intel_plane(plane);
2718
2719         intel_plane->wm.enabled = enabled;
2720         intel_plane->wm.scaled = scaled;
2721         intel_plane->wm.horiz_pixels = sprite_width;
2722         intel_plane->wm.bytes_per_pixel = pixel_size;
2723
2724         /*
2725          * IVB workaround: must disable low power watermarks for at least
2726          * one frame before enabling scaling.  LP watermarks can be re-enabled
2727          * when scaling is disabled.
2728          *
2729          * WaCxSRDisabledForSpriteScaling:ivb
2730          */
2731         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2732                 intel_wait_for_vblank(dev, intel_plane->pipe);
2733
2734         ilk_update_wm(crtc);
2735 }
2736
2737 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2738 {
2739         struct drm_device *dev = crtc->dev;
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2743         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2744         enum pipe pipe = intel_crtc->pipe;
2745         static const unsigned int wm0_pipe_reg[] = {
2746                 [PIPE_A] = WM0_PIPEA_ILK,
2747                 [PIPE_B] = WM0_PIPEB_ILK,
2748                 [PIPE_C] = WM0_PIPEC_IVB,
2749         };
2750
2751         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2752         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2753                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2754
2755         active->pipe_enabled = intel_crtc_active(crtc);
2756
2757         if (active->pipe_enabled) {
2758                 u32 tmp = hw->wm_pipe[pipe];
2759
2760                 /*
2761                  * For active pipes LP0 watermark is marked as
2762                  * enabled, and LP1+ watermaks as disabled since
2763                  * we can't really reverse compute them in case
2764                  * multiple pipes are active.
2765                  */
2766                 active->wm[0].enable = true;
2767                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2768                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2769                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2770                 active->linetime = hw->wm_linetime[pipe];
2771         } else {
2772                 int level, max_level = ilk_wm_max_level(dev);
2773
2774                 /*
2775                  * For inactive pipes, all watermark levels
2776                  * should be marked as enabled but zeroed,
2777                  * which is what we'd compute them to.
2778                  */
2779                 for (level = 0; level <= max_level; level++)
2780                         active->wm[level].enable = true;
2781         }
2782 }
2783
2784 void ilk_wm_get_hw_state(struct drm_device *dev)
2785 {
2786         struct drm_i915_private *dev_priv = dev->dev_private;
2787         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2788         struct drm_crtc *crtc;
2789
2790         for_each_crtc(dev, crtc)
2791                 ilk_pipe_wm_get_hw_state(crtc);
2792
2793         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2794         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2795         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2796
2797         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2798         if (INTEL_INFO(dev)->gen >= 7) {
2799                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2800                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2801         }
2802
2803         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2804                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2805                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2806         else if (IS_IVYBRIDGE(dev))
2807                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2808                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2809
2810         hw->enable_fbc_wm =
2811                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2812 }
2813
2814 /**
2815  * intel_update_watermarks - update FIFO watermark values based on current modes
2816  *
2817  * Calculate watermark values for the various WM regs based on current mode
2818  * and plane configuration.
2819  *
2820  * There are several cases to deal with here:
2821  *   - normal (i.e. non-self-refresh)
2822  *   - self-refresh (SR) mode
2823  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2824  *   - lines are small relative to FIFO size (buffer can hold more than 2
2825  *     lines), so need to account for TLB latency
2826  *
2827  *   The normal calculation is:
2828  *     watermark = dotclock * bytes per pixel * latency
2829  *   where latency is platform & configuration dependent (we assume pessimal
2830  *   values here).
2831  *
2832  *   The SR calculation is:
2833  *     watermark = (trunc(latency/line time)+1) * surface width *
2834  *       bytes per pixel
2835  *   where
2836  *     line time = htotal / dotclock
2837  *     surface width = hdisplay for normal plane and 64 for cursor
2838  *   and latency is assumed to be high, as above.
2839  *
2840  * The final value programmed to the register should always be rounded up,
2841  * and include an extra 2 entries to account for clock crossings.
2842  *
2843  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2844  * to set the non-SR watermarks to 8.
2845  */
2846 void intel_update_watermarks(struct drm_crtc *crtc)
2847 {
2848         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2849
2850         if (dev_priv->display.update_wm)
2851                 dev_priv->display.update_wm(crtc);
2852 }
2853
2854 void intel_update_sprite_watermarks(struct drm_plane *plane,
2855                                     struct drm_crtc *crtc,
2856                                     uint32_t sprite_width, int pixel_size,
2857                                     bool enabled, bool scaled)
2858 {
2859         struct drm_i915_private *dev_priv = plane->dev->dev_private;
2860
2861         if (dev_priv->display.update_sprite_wm)
2862                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2863                                                    pixel_size, enabled, scaled);
2864 }
2865
2866 static struct drm_i915_gem_object *
2867 intel_alloc_context_page(struct drm_device *dev)
2868 {
2869         struct drm_i915_gem_object *ctx;
2870         int ret;
2871
2872         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2873
2874         ctx = i915_gem_alloc_object(dev, 4096);
2875         if (!ctx) {
2876                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2877                 return NULL;
2878         }
2879
2880         ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2881         if (ret) {
2882                 DRM_ERROR("failed to pin power context: %d\n", ret);
2883                 goto err_unref;
2884         }
2885
2886         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2887         if (ret) {
2888                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2889                 goto err_unpin;
2890         }
2891
2892         return ctx;
2893
2894 err_unpin:
2895         i915_gem_object_ggtt_unpin(ctx);
2896 err_unref:
2897         drm_gem_object_unreference(&ctx->base);
2898         return NULL;
2899 }
2900
2901 /**
2902  * Lock protecting IPS related data structures
2903  */
2904 DEFINE_SPINLOCK(mchdev_lock);
2905
2906 /* Global for IPS driver to get at the current i915 device. Protected by
2907  * mchdev_lock. */
2908 static struct drm_i915_private *i915_mch_dev;
2909
2910 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2911 {
2912         struct drm_i915_private *dev_priv = dev->dev_private;
2913         u16 rgvswctl;
2914
2915         assert_spin_locked(&mchdev_lock);
2916
2917         rgvswctl = I915_READ16(MEMSWCTL);
2918         if (rgvswctl & MEMCTL_CMD_STS) {
2919                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2920                 return false; /* still busy with another command */
2921         }
2922
2923         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2924                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2925         I915_WRITE16(MEMSWCTL, rgvswctl);
2926         POSTING_READ16(MEMSWCTL);
2927
2928         rgvswctl |= MEMCTL_CMD_STS;
2929         I915_WRITE16(MEMSWCTL, rgvswctl);
2930
2931         return true;
2932 }
2933
2934 static void ironlake_enable_drps(struct drm_device *dev)
2935 {
2936         struct drm_i915_private *dev_priv = dev->dev_private;
2937         u32 rgvmodectl = I915_READ(MEMMODECTL);
2938         u8 fmax, fmin, fstart, vstart;
2939
2940         spin_lock_irq(&mchdev_lock);
2941
2942         /* Enable temp reporting */
2943         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2944         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2945
2946         /* 100ms RC evaluation intervals */
2947         I915_WRITE(RCUPEI, 100000);
2948         I915_WRITE(RCDNEI, 100000);
2949
2950         /* Set max/min thresholds to 90ms and 80ms respectively */
2951         I915_WRITE(RCBMAXAVG, 90000);
2952         I915_WRITE(RCBMINAVG, 80000);
2953
2954         I915_WRITE(MEMIHYST, 1);
2955
2956         /* Set up min, max, and cur for interrupt handling */
2957         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2958         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2959         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2960                 MEMMODE_FSTART_SHIFT;
2961
2962         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2963                 PXVFREQ_PX_SHIFT;
2964
2965         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2966         dev_priv->ips.fstart = fstart;
2967
2968         dev_priv->ips.max_delay = fstart;
2969         dev_priv->ips.min_delay = fmin;
2970         dev_priv->ips.cur_delay = fstart;
2971
2972         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2973                          fmax, fmin, fstart);
2974
2975         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2976
2977         /*
2978          * Interrupts will be enabled in ironlake_irq_postinstall
2979          */
2980
2981         I915_WRITE(VIDSTART, vstart);
2982         POSTING_READ(VIDSTART);
2983
2984         rgvmodectl |= MEMMODE_SWMODE_EN;
2985         I915_WRITE(MEMMODECTL, rgvmodectl);
2986
2987         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2988                 DRM_ERROR("stuck trying to change perf mode\n");
2989         mdelay(1);
2990
2991         ironlake_set_drps(dev, fstart);
2992
2993         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2994                 I915_READ(0x112e0);
2995         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2996         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2997         getrawmonotonic(&dev_priv->ips.last_time2);
2998
2999         spin_unlock_irq(&mchdev_lock);
3000 }
3001
3002 static void ironlake_disable_drps(struct drm_device *dev)
3003 {
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         u16 rgvswctl;
3006
3007         spin_lock_irq(&mchdev_lock);
3008
3009         rgvswctl = I915_READ16(MEMSWCTL);
3010
3011         /* Ack interrupts, disable EFC interrupt */
3012         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3013         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3014         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3015         I915_WRITE(DEIIR, DE_PCU_EVENT);
3016         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3017
3018         /* Go back to the starting frequency */
3019         ironlake_set_drps(dev, dev_priv->ips.fstart);
3020         mdelay(1);
3021         rgvswctl |= MEMCTL_CMD_STS;
3022         I915_WRITE(MEMSWCTL, rgvswctl);
3023         mdelay(1);
3024
3025         spin_unlock_irq(&mchdev_lock);
3026 }
3027
3028 /* There's a funny hw issue where the hw returns all 0 when reading from
3029  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3030  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3031  * all limits and the gpu stuck at whatever frequency it is at atm).
3032  */
3033 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3034 {
3035         u32 limits;
3036
3037         /* Only set the down limit when we've reached the lowest level to avoid
3038          * getting more interrupts, otherwise leave this clear. This prevents a
3039          * race in the hw when coming out of rc6: There's a tiny window where
3040          * the hw runs at the minimal clock before selecting the desired
3041          * frequency, if the down threshold expires in that window we will not
3042          * receive a down interrupt. */
3043         limits = dev_priv->rps.max_freq_softlimit << 24;
3044         if (val <= dev_priv->rps.min_freq_softlimit)
3045                 limits |= dev_priv->rps.min_freq_softlimit << 16;
3046
3047         return limits;
3048 }
3049
3050 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3051 {
3052         int new_power;
3053
3054         new_power = dev_priv->rps.power;
3055         switch (dev_priv->rps.power) {
3056         case LOW_POWER:
3057                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3058                         new_power = BETWEEN;
3059                 break;
3060
3061         case BETWEEN:
3062                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3063                         new_power = LOW_POWER;
3064                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3065                         new_power = HIGH_POWER;
3066                 break;
3067
3068         case HIGH_POWER:
3069                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3070                         new_power = BETWEEN;
3071                 break;
3072         }
3073         /* Max/min bins are special */
3074         if (val == dev_priv->rps.min_freq_softlimit)
3075                 new_power = LOW_POWER;
3076         if (val == dev_priv->rps.max_freq_softlimit)
3077                 new_power = HIGH_POWER;
3078         if (new_power == dev_priv->rps.power)
3079                 return;
3080
3081         /* Note the units here are not exactly 1us, but 1280ns. */
3082         switch (new_power) {
3083         case LOW_POWER:
3084                 /* Upclock if more than 95% busy over 16ms */
3085                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3086                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3087
3088                 /* Downclock if less than 85% busy over 32ms */
3089                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3090                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3091
3092                 I915_WRITE(GEN6_RP_CONTROL,
3093                            GEN6_RP_MEDIA_TURBO |
3094                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3095                            GEN6_RP_MEDIA_IS_GFX |
3096                            GEN6_RP_ENABLE |
3097                            GEN6_RP_UP_BUSY_AVG |
3098                            GEN6_RP_DOWN_IDLE_AVG);
3099                 break;
3100
3101         case BETWEEN:
3102                 /* Upclock if more than 90% busy over 13ms */
3103                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3104                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3105
3106                 /* Downclock if less than 75% busy over 32ms */
3107                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3108                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3109
3110                 I915_WRITE(GEN6_RP_CONTROL,
3111                            GEN6_RP_MEDIA_TURBO |
3112                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3113                            GEN6_RP_MEDIA_IS_GFX |
3114                            GEN6_RP_ENABLE |
3115                            GEN6_RP_UP_BUSY_AVG |
3116                            GEN6_RP_DOWN_IDLE_AVG);
3117                 break;
3118
3119         case HIGH_POWER:
3120                 /* Upclock if more than 85% busy over 10ms */
3121                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3122                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3123
3124                 /* Downclock if less than 60% busy over 32ms */
3125                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3126                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3127
3128                 I915_WRITE(GEN6_RP_CONTROL,
3129                            GEN6_RP_MEDIA_TURBO |
3130                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3131                            GEN6_RP_MEDIA_IS_GFX |
3132                            GEN6_RP_ENABLE |
3133                            GEN6_RP_UP_BUSY_AVG |
3134                            GEN6_RP_DOWN_IDLE_AVG);
3135                 break;
3136         }
3137
3138         dev_priv->rps.power = new_power;
3139         dev_priv->rps.last_adj = 0;
3140 }
3141
3142 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3143 {
3144         u32 mask = 0;
3145
3146         if (val > dev_priv->rps.min_freq_softlimit)
3147                 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3148         if (val < dev_priv->rps.max_freq_softlimit)
3149                 mask |= GEN6_PM_RP_UP_THRESHOLD;
3150
3151         /* IVB and SNB hard hangs on looping batchbuffer
3152          * if GEN6_PM_UP_EI_EXPIRED is masked.
3153          */
3154         if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3155                 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3156
3157         if (IS_GEN8(dev_priv->dev))
3158                 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3159
3160         return ~mask;
3161 }
3162
3163 /* gen6_set_rps is called to update the frequency request, but should also be
3164  * called when the range (min_delay and max_delay) is modified so that we can
3165  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3166 void gen6_set_rps(struct drm_device *dev, u8 val)
3167 {
3168         struct drm_i915_private *dev_priv = dev->dev_private;
3169
3170         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3171         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3172         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3173
3174         /* min/max delay may still have been modified so be sure to
3175          * write the limits value.
3176          */
3177         if (val != dev_priv->rps.cur_freq) {
3178                 gen6_set_rps_thresholds(dev_priv, val);
3179
3180                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3181                         I915_WRITE(GEN6_RPNSWREQ,
3182                                    HSW_FREQUENCY(val));
3183                 else
3184                         I915_WRITE(GEN6_RPNSWREQ,
3185                                    GEN6_FREQUENCY(val) |
3186                                    GEN6_OFFSET(0) |
3187                                    GEN6_AGGRESSIVE_TURBO);
3188         }
3189
3190         /* Make sure we continue to get interrupts
3191          * until we hit the minimum or maximum frequencies.
3192          */
3193         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3194         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3195
3196         POSTING_READ(GEN6_RPNSWREQ);
3197
3198         dev_priv->rps.cur_freq = val;
3199         trace_intel_gpu_freq_change(val * 50);
3200 }
3201
3202 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3203  *
3204  * * If Gfx is Idle, then
3205  * 1. Mask Turbo interrupts
3206  * 2. Bring up Gfx clock
3207  * 3. Change the freq to Rpn and wait till P-Unit updates freq
3208  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3209  * 5. Unmask Turbo interrupts
3210 */
3211 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3212 {
3213         /*
3214          * When we are idle.  Drop to min voltage state.
3215          */
3216
3217         if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3218                 return;
3219
3220         /* Mask turbo interrupt so that they will not come in between */
3221         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3222
3223         vlv_force_gfx_clock(dev_priv, true);
3224
3225         dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3226
3227         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3228                                         dev_priv->rps.min_freq_softlimit);
3229
3230         if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3231                                 & GENFREQSTATUS) == 0, 5))
3232                 DRM_ERROR("timed out waiting for Punit\n");
3233
3234         vlv_force_gfx_clock(dev_priv, false);
3235
3236         I915_WRITE(GEN6_PMINTRMSK,
3237                    gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3238 }
3239
3240 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3241 {
3242         struct drm_device *dev = dev_priv->dev;
3243
3244         mutex_lock(&dev_priv->rps.hw_lock);
3245         if (dev_priv->rps.enabled) {
3246                 if (IS_VALLEYVIEW(dev))
3247                         vlv_set_rps_idle(dev_priv);
3248                 else
3249                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3250                 dev_priv->rps.last_adj = 0;
3251         }
3252         mutex_unlock(&dev_priv->rps.hw_lock);
3253 }
3254
3255 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3256 {
3257         struct drm_device *dev = dev_priv->dev;
3258
3259         mutex_lock(&dev_priv->rps.hw_lock);
3260         if (dev_priv->rps.enabled) {
3261                 if (IS_VALLEYVIEW(dev))
3262                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3263                 else
3264                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3265                 dev_priv->rps.last_adj = 0;
3266         }
3267         mutex_unlock(&dev_priv->rps.hw_lock);
3268 }
3269
3270 void valleyview_set_rps(struct drm_device *dev, u8 val)
3271 {
3272         struct drm_i915_private *dev_priv = dev->dev_private;
3273
3274         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3275         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3276         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3277
3278         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3279                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3280                          dev_priv->rps.cur_freq,
3281                          vlv_gpu_freq(dev_priv, val), val);
3282
3283         if (val != dev_priv->rps.cur_freq)
3284                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3285
3286         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3287
3288         dev_priv->rps.cur_freq = val;
3289         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3290 }
3291
3292 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3293 {
3294         struct drm_i915_private *dev_priv = dev->dev_private;
3295
3296         I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3297         I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3298                                    ~dev_priv->pm_rps_events);
3299         /* Complete PM interrupt masking here doesn't race with the rps work
3300          * item again unmasking PM interrupts because that is using a different
3301          * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3302          * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3303          * gen8_enable_rps will clean up. */
3304
3305         spin_lock_irq(&dev_priv->irq_lock);
3306         dev_priv->rps.pm_iir = 0;
3307         spin_unlock_irq(&dev_priv->irq_lock);
3308
3309         I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3310 }
3311
3312 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3313 {
3314         struct drm_i915_private *dev_priv = dev->dev_private;
3315
3316         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3317         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3318                                 ~dev_priv->pm_rps_events);
3319         /* Complete PM interrupt masking here doesn't race with the rps work
3320          * item again unmasking PM interrupts because that is using a different
3321          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3322          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3323
3324         spin_lock_irq(&dev_priv->irq_lock);
3325         dev_priv->rps.pm_iir = 0;
3326         spin_unlock_irq(&dev_priv->irq_lock);
3327
3328         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3329 }
3330
3331 static void gen6_disable_rps(struct drm_device *dev)
3332 {
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334
3335         I915_WRITE(GEN6_RC_CONTROL, 0);
3336         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3337
3338         if (IS_BROADWELL(dev))
3339                 gen8_disable_rps_interrupts(dev);
3340         else
3341                 gen6_disable_rps_interrupts(dev);
3342 }
3343
3344 static void valleyview_disable_rps(struct drm_device *dev)
3345 {
3346         struct drm_i915_private *dev_priv = dev->dev_private;
3347
3348         I915_WRITE(GEN6_RC_CONTROL, 0);
3349
3350         gen6_disable_rps_interrupts(dev);
3351 }
3352
3353 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3354 {
3355         if (IS_VALLEYVIEW(dev)) {
3356                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3357                         mode = GEN6_RC_CTL_RC6_ENABLE;
3358                 else
3359                         mode = 0;
3360         }
3361         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3362                  (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3363                  (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3364                  (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3365 }
3366
3367 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3368 {
3369         /* No RC6 before Ironlake */
3370         if (INTEL_INFO(dev)->gen < 5)
3371                 return 0;
3372
3373         /* RC6 is only on Ironlake mobile not on desktop */
3374         if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3375                 return 0;
3376
3377         /* Respect the kernel parameter if it is set */
3378         if (enable_rc6 >= 0) {
3379                 int mask;
3380
3381                 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3382                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3383                                INTEL_RC6pp_ENABLE;
3384                 else
3385                         mask = INTEL_RC6_ENABLE;
3386
3387                 if ((enable_rc6 & mask) != enable_rc6)
3388                         DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3389                                  enable_rc6 & mask, enable_rc6, mask);
3390
3391                 return enable_rc6 & mask;
3392         }
3393
3394         /* Disable RC6 on Ironlake */
3395         if (INTEL_INFO(dev)->gen == 5)
3396                 return 0;
3397
3398         if (IS_IVYBRIDGE(dev))
3399                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3400
3401         return INTEL_RC6_ENABLE;
3402 }
3403
3404 int intel_enable_rc6(const struct drm_device *dev)
3405 {
3406         return i915.enable_rc6;
3407 }
3408
3409 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3410 {
3411         struct drm_i915_private *dev_priv = dev->dev_private;
3412
3413         spin_lock_irq(&dev_priv->irq_lock);
3414         WARN_ON(dev_priv->rps.pm_iir);
3415         bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3416         I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3417         spin_unlock_irq(&dev_priv->irq_lock);
3418 }
3419
3420 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3421 {
3422         struct drm_i915_private *dev_priv = dev->dev_private;
3423
3424         spin_lock_irq(&dev_priv->irq_lock);
3425         WARN_ON(dev_priv->rps.pm_iir);
3426         snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3427         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3428         spin_unlock_irq(&dev_priv->irq_lock);
3429 }
3430
3431 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3432 {
3433         /* All of these values are in units of 50MHz */
3434         dev_priv->rps.cur_freq          = 0;
3435         /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3436         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
3437         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
3438         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
3439         /* XXX: only BYT has a special efficient freq */
3440         dev_priv->rps.efficient_freq    = dev_priv->rps.rp1_freq;
3441         /* hw_max = RP0 until we check for overclocking */
3442         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
3443
3444         /* Preserve min/max settings in case of re-init */
3445         if (dev_priv->rps.max_freq_softlimit == 0)
3446                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3447
3448         if (dev_priv->rps.min_freq_softlimit == 0)
3449                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3450 }
3451
3452 static void gen8_enable_rps(struct drm_device *dev)
3453 {
3454         struct drm_i915_private *dev_priv = dev->dev_private;
3455         struct intel_engine_cs *ring;
3456         uint32_t rc6_mask = 0, rp_state_cap;
3457         int unused;
3458
3459         /* 1a: Software RC state - RC0 */
3460         I915_WRITE(GEN6_RC_STATE, 0);
3461
3462         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3463          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3464         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3465
3466         /* 2a: Disable RC states. */
3467         I915_WRITE(GEN6_RC_CONTROL, 0);
3468
3469         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3470         parse_rp_state_cap(dev_priv, rp_state_cap);
3471
3472         /* 2b: Program RC6 thresholds.*/
3473         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3474         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3475         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3476         for_each_ring(ring, dev_priv, unused)
3477                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3478         I915_WRITE(GEN6_RC_SLEEP, 0);
3479         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3480
3481         /* 3: Enable RC6 */
3482         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3483                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3484         intel_print_rc6_info(dev, rc6_mask);
3485         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3486                                     GEN6_RC_CTL_EI_MODE(1) |
3487                                     rc6_mask);
3488
3489         /* 4 Program defaults and thresholds for RPS*/
3490         I915_WRITE(GEN6_RPNSWREQ,
3491                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3492         I915_WRITE(GEN6_RC_VIDEO_FREQ,
3493                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3494         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3495         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3496
3497         /* Docs recommend 900MHz, and 300 MHz respectively */
3498         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3499                    dev_priv->rps.max_freq_softlimit << 24 |
3500                    dev_priv->rps.min_freq_softlimit << 16);
3501
3502         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3503         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3504         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3505         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3506
3507         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3508
3509         /* WaDisablePwrmtrEvent:chv (pre-production hw) */
3510         I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
3511         I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
3512
3513         /* 5: Enable RPS */
3514         I915_WRITE(GEN6_RP_CONTROL,
3515                    GEN6_RP_MEDIA_TURBO |
3516                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3517                    GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
3518                    GEN6_RP_ENABLE |
3519                    GEN6_RP_UP_BUSY_AVG |
3520                    GEN6_RP_DOWN_IDLE_AVG);
3521
3522         /* 6: Ring frequency + overclocking (our driver does this later */
3523
3524         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3525
3526         gen8_enable_rps_interrupts(dev);
3527
3528         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3529 }
3530
3531 static void gen6_enable_rps(struct drm_device *dev)
3532 {
3533         struct drm_i915_private *dev_priv = dev->dev_private;
3534         struct intel_engine_cs *ring;
3535         u32 rp_state_cap;
3536         u32 gt_perf_status;
3537         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3538         u32 gtfifodbg;
3539         int rc6_mode;
3540         int i, ret;
3541
3542         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3543
3544         /* Here begins a magic sequence of register writes to enable
3545          * auto-downclocking.
3546          *
3547          * Perhaps there might be some value in exposing these to
3548          * userspace...
3549          */
3550         I915_WRITE(GEN6_RC_STATE, 0);
3551
3552         /* Clear the DBG now so we don't confuse earlier errors */
3553         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3554                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3555                 I915_WRITE(GTFIFODBG, gtfifodbg);
3556         }
3557
3558         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3559
3560         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3561         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3562
3563         parse_rp_state_cap(dev_priv, rp_state_cap);
3564
3565         /* disable the counters and set deterministic thresholds */
3566         I915_WRITE(GEN6_RC_CONTROL, 0);
3567
3568         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3569         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3570         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3571         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3572         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3573
3574         for_each_ring(ring, dev_priv, i)
3575                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3576
3577         I915_WRITE(GEN6_RC_SLEEP, 0);
3578         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3579         if (IS_IVYBRIDGE(dev))
3580                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3581         else
3582                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3583         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3584         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3585
3586         /* Check if we are enabling RC6 */
3587         rc6_mode = intel_enable_rc6(dev_priv->dev);
3588         if (rc6_mode & INTEL_RC6_ENABLE)
3589                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3590
3591         /* We don't use those on Haswell */
3592         if (!IS_HASWELL(dev)) {
3593                 if (rc6_mode & INTEL_RC6p_ENABLE)
3594                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3595
3596                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3597                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3598         }
3599
3600         intel_print_rc6_info(dev, rc6_mask);
3601
3602         I915_WRITE(GEN6_RC_CONTROL,
3603                    rc6_mask |
3604                    GEN6_RC_CTL_EI_MODE(1) |
3605                    GEN6_RC_CTL_HW_ENABLE);
3606
3607         /* Power down if completely idle for over 50ms */
3608         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3609         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3610
3611         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3612         if (ret)
3613                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3614
3615         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3616         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3617                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3618                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3619                                  (pcu_mbox & 0xff) * 50);
3620                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3621         }
3622
3623         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3624         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3625
3626         gen6_enable_rps_interrupts(dev);
3627
3628         rc6vids = 0;
3629         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3630         if (IS_GEN6(dev) && ret) {
3631                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3632         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3633                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3634                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3635                 rc6vids &= 0xffff00;
3636                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3637                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3638                 if (ret)
3639                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3640         }
3641
3642         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3643 }
3644
3645 static void __gen6_update_ring_freq(struct drm_device *dev)
3646 {
3647         struct drm_i915_private *dev_priv = dev->dev_private;
3648         int min_freq = 15;
3649         unsigned int gpu_freq;
3650         unsigned int max_ia_freq, min_ring_freq;
3651         int scaling_factor = 180;
3652         struct cpufreq_policy *policy;
3653
3654         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3655
3656         policy = cpufreq_cpu_get(0);
3657         if (policy) {
3658                 max_ia_freq = policy->cpuinfo.max_freq;
3659                 cpufreq_cpu_put(policy);
3660         } else {
3661                 /*
3662                  * Default to measured freq if none found, PCU will ensure we
3663                  * don't go over
3664                  */
3665                 max_ia_freq = tsc_khz;
3666         }
3667
3668         /* Convert from kHz to MHz */
3669         max_ia_freq /= 1000;
3670
3671         min_ring_freq = I915_READ(DCLK) & 0xf;
3672         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3673         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3674
3675         /*
3676          * For each potential GPU frequency, load a ring frequency we'd like
3677          * to use for memory access.  We do this by specifying the IA frequency
3678          * the PCU should use as a reference to determine the ring frequency.
3679          */
3680         for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3681              gpu_freq--) {
3682                 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3683                 unsigned int ia_freq = 0, ring_freq = 0;
3684
3685                 if (INTEL_INFO(dev)->gen >= 8) {
3686                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3687                         ring_freq = max(min_ring_freq, gpu_freq);
3688                 } else if (IS_HASWELL(dev)) {
3689                         ring_freq = mult_frac(gpu_freq, 5, 4);
3690                         ring_freq = max(min_ring_freq, ring_freq);
3691                         /* leave ia_freq as the default, chosen by cpufreq */
3692                 } else {
3693                         /* On older processors, there is no separate ring
3694                          * clock domain, so in order to boost the bandwidth
3695                          * of the ring, we need to upclock the CPU (ia_freq).
3696                          *
3697                          * For GPU frequencies less than 750MHz,
3698                          * just use the lowest ring freq.
3699                          */
3700                         if (gpu_freq < min_freq)
3701                                 ia_freq = 800;
3702                         else
3703                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3704                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3705                 }
3706
3707                 sandybridge_pcode_write(dev_priv,
3708                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3709                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3710                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3711                                         gpu_freq);
3712         }
3713 }
3714
3715 void gen6_update_ring_freq(struct drm_device *dev)
3716 {
3717         struct drm_i915_private *dev_priv = dev->dev_private;
3718
3719         if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3720                 return;
3721
3722         mutex_lock(&dev_priv->rps.hw_lock);
3723         __gen6_update_ring_freq(dev);
3724         mutex_unlock(&dev_priv->rps.hw_lock);
3725 }
3726
3727 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3728 {
3729         u32 val, rp0;
3730
3731         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3732
3733         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3734         /* Clamp to max */
3735         rp0 = min_t(u32, rp0, 0xea);
3736
3737         return rp0;
3738 }
3739
3740 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3741 {
3742         u32 val, rpe;
3743
3744         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3745         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3746         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3747         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3748
3749         return rpe;
3750 }
3751
3752 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3753 {
3754         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3755 }
3756
3757 /* Check that the pctx buffer wasn't move under us. */
3758 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3759 {
3760         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3761
3762         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3763                              dev_priv->vlv_pctx->stolen->start);
3764 }
3765
3766 static void valleyview_setup_pctx(struct drm_device *dev)
3767 {
3768         struct drm_i915_private *dev_priv = dev->dev_private;
3769         struct drm_i915_gem_object *pctx;
3770         unsigned long pctx_paddr;
3771         u32 pcbr;
3772         int pctx_size = 24*1024;
3773
3774         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3775
3776         pcbr = I915_READ(VLV_PCBR);
3777         if (pcbr) {
3778                 /* BIOS set it up already, grab the pre-alloc'd space */
3779                 int pcbr_offset;
3780
3781                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3782                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3783                                                                       pcbr_offset,
3784                                                                       I915_GTT_OFFSET_NONE,
3785                                                                       pctx_size);
3786                 goto out;
3787         }
3788
3789         /*
3790          * From the Gunit register HAS:
3791          * The Gfx driver is expected to program this register and ensure
3792          * proper allocation within Gfx stolen memory.  For example, this
3793          * register should be programmed such than the PCBR range does not
3794          * overlap with other ranges, such as the frame buffer, protected
3795          * memory, or any other relevant ranges.
3796          */
3797         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3798         if (!pctx) {
3799                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3800                 return;
3801         }
3802
3803         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3804         I915_WRITE(VLV_PCBR, pctx_paddr);
3805
3806 out:
3807         dev_priv->vlv_pctx = pctx;
3808 }
3809
3810 static void valleyview_cleanup_pctx(struct drm_device *dev)
3811 {
3812         struct drm_i915_private *dev_priv = dev->dev_private;
3813
3814         if (WARN_ON(!dev_priv->vlv_pctx))
3815                 return;
3816
3817         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3818         dev_priv->vlv_pctx = NULL;
3819 }
3820
3821 static void valleyview_init_gt_powersave(struct drm_device *dev)
3822 {
3823         struct drm_i915_private *dev_priv = dev->dev_private;
3824
3825         valleyview_setup_pctx(dev);
3826
3827         mutex_lock(&dev_priv->rps.hw_lock);
3828
3829         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3830         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3831         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3832                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3833                          dev_priv->rps.max_freq);
3834
3835         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3836         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3837                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3838                          dev_priv->rps.efficient_freq);
3839
3840         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3841         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3842                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3843                          dev_priv->rps.min_freq);
3844
3845         /* Preserve min/max settings in case of re-init */
3846         if (dev_priv->rps.max_freq_softlimit == 0)
3847                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3848
3849         if (dev_priv->rps.min_freq_softlimit == 0)
3850                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3851
3852         mutex_unlock(&dev_priv->rps.hw_lock);
3853 }
3854
3855 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3856 {
3857         valleyview_cleanup_pctx(dev);
3858 }
3859
3860 static void valleyview_enable_rps(struct drm_device *dev)
3861 {
3862         struct drm_i915_private *dev_priv = dev->dev_private;
3863         struct intel_engine_cs *ring;
3864         u32 gtfifodbg, val, rc6_mode = 0;
3865         int i;
3866
3867         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3868
3869         valleyview_check_pctx(dev_priv);
3870
3871         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3872                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3873                                  gtfifodbg);
3874                 I915_WRITE(GTFIFODBG, gtfifodbg);
3875         }
3876
3877         /* If VLV, Forcewake all wells, else re-direct to regular path */
3878         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3879
3880         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3881         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3882         I915_WRITE(GEN6_RP_UP_EI, 66000);
3883         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3884
3885         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3886
3887         I915_WRITE(GEN6_RP_CONTROL,
3888                    GEN6_RP_MEDIA_TURBO |
3889                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3890                    GEN6_RP_MEDIA_IS_GFX |
3891                    GEN6_RP_ENABLE |
3892                    GEN6_RP_UP_BUSY_AVG |
3893                    GEN6_RP_DOWN_IDLE_CONT);
3894
3895         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3896         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3897         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3898
3899         for_each_ring(ring, dev_priv, i)
3900                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3901
3902         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3903
3904         /* allows RC6 residency counter to work */
3905         I915_WRITE(VLV_COUNTER_CONTROL,
3906                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3907                                       VLV_MEDIA_RC6_COUNT_EN |
3908                                       VLV_RENDER_RC6_COUNT_EN));
3909         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3910                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3911
3912         intel_print_rc6_info(dev, rc6_mode);
3913
3914         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3915
3916         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3917
3918         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3919         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3920
3921         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
3922         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3923                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3924                          dev_priv->rps.cur_freq);
3925
3926         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3927                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3928                          dev_priv->rps.efficient_freq);
3929
3930         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
3931
3932         gen6_enable_rps_interrupts(dev);
3933
3934         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3935 }
3936
3937 void ironlake_teardown_rc6(struct drm_device *dev)
3938 {
3939         struct drm_i915_private *dev_priv = dev->dev_private;
3940
3941         if (dev_priv->ips.renderctx) {
3942                 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3943                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3944                 dev_priv->ips.renderctx = NULL;
3945         }
3946
3947         if (dev_priv->ips.pwrctx) {
3948                 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3949                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3950                 dev_priv->ips.pwrctx = NULL;
3951         }
3952 }
3953
3954 static void ironlake_disable_rc6(struct drm_device *dev)
3955 {
3956         struct drm_i915_private *dev_priv = dev->dev_private;
3957
3958         if (I915_READ(PWRCTXA)) {
3959                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3960                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3961                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3962                          50);
3963
3964                 I915_WRITE(PWRCTXA, 0);
3965                 POSTING_READ(PWRCTXA);
3966
3967                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3968                 POSTING_READ(RSTDBYCTL);
3969         }
3970 }
3971
3972 static int ironlake_setup_rc6(struct drm_device *dev)
3973 {
3974         struct drm_i915_private *dev_priv = dev->dev_private;
3975
3976         if (dev_priv->ips.renderctx == NULL)
3977                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3978         if (!dev_priv->ips.renderctx)
3979                 return -ENOMEM;
3980
3981         if (dev_priv->ips.pwrctx == NULL)
3982                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3983         if (!dev_priv->ips.pwrctx) {
3984                 ironlake_teardown_rc6(dev);
3985                 return -ENOMEM;
3986         }
3987
3988         return 0;
3989 }
3990
3991 static void ironlake_enable_rc6(struct drm_device *dev)
3992 {
3993         struct drm_i915_private *dev_priv = dev->dev_private;
3994         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3995         bool was_interruptible;
3996         int ret;
3997
3998         /* rc6 disabled by default due to repeated reports of hanging during
3999          * boot and resume.
4000          */
4001         if (!intel_enable_rc6(dev))
4002                 return;
4003
4004         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4005
4006         ret = ironlake_setup_rc6(dev);
4007         if (ret)
4008                 return;
4009
4010         was_interruptible = dev_priv->mm.interruptible;
4011         dev_priv->mm.interruptible = false;
4012
4013         /*
4014          * GPU can automatically power down the render unit if given a page
4015          * to save state.
4016          */
4017         ret = intel_ring_begin(ring, 6);
4018         if (ret) {
4019                 ironlake_teardown_rc6(dev);
4020                 dev_priv->mm.interruptible = was_interruptible;
4021                 return;
4022         }
4023
4024         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4025         intel_ring_emit(ring, MI_SET_CONTEXT);
4026         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4027                         MI_MM_SPACE_GTT |
4028                         MI_SAVE_EXT_STATE_EN |
4029                         MI_RESTORE_EXT_STATE_EN |
4030                         MI_RESTORE_INHIBIT);
4031         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4032         intel_ring_emit(ring, MI_NOOP);
4033         intel_ring_emit(ring, MI_FLUSH);
4034         intel_ring_advance(ring);
4035
4036         /*
4037          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4038          * does an implicit flush, combined with MI_FLUSH above, it should be
4039          * safe to assume that renderctx is valid
4040          */
4041         ret = intel_ring_idle(ring);
4042         dev_priv->mm.interruptible = was_interruptible;
4043         if (ret) {
4044                 DRM_ERROR("failed to enable ironlake power savings\n");
4045                 ironlake_teardown_rc6(dev);
4046                 return;
4047         }
4048
4049         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4050         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4051
4052         intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4053 }
4054
4055 static unsigned long intel_pxfreq(u32 vidfreq)
4056 {
4057         unsigned long freq;
4058         int div = (vidfreq & 0x3f0000) >> 16;
4059         int post = (vidfreq & 0x3000) >> 12;
4060         int pre = (vidfreq & 0x7);
4061
4062         if (!pre)
4063                 return 0;
4064
4065         freq = ((div * 133333) / ((1<<post) * pre));
4066
4067         return freq;
4068 }
4069
4070 static const struct cparams {
4071         u16 i;
4072         u16 t;
4073         u16 m;
4074         u16 c;
4075 } cparams[] = {
4076         { 1, 1333, 301, 28664 },
4077         { 1, 1066, 294, 24460 },
4078         { 1, 800, 294, 25192 },
4079         { 0, 1333, 276, 27605 },
4080         { 0, 1066, 276, 27605 },
4081         { 0, 800, 231, 23784 },
4082 };
4083
4084 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4085 {
4086         u64 total_count, diff, ret;
4087         u32 count1, count2, count3, m = 0, c = 0;
4088         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4089         int i;
4090
4091         assert_spin_locked(&mchdev_lock);
4092
4093         diff1 = now - dev_priv->ips.last_time1;
4094
4095         /* Prevent division-by-zero if we are asking too fast.
4096          * Also, we don't get interesting results if we are polling
4097          * faster than once in 10ms, so just return the saved value
4098          * in such cases.
4099          */
4100         if (diff1 <= 10)
4101                 return dev_priv->ips.chipset_power;
4102
4103         count1 = I915_READ(DMIEC);
4104         count2 = I915_READ(DDREC);
4105         count3 = I915_READ(CSIEC);
4106
4107         total_count = count1 + count2 + count3;
4108
4109         /* FIXME: handle per-counter overflow */
4110         if (total_count < dev_priv->ips.last_count1) {
4111                 diff = ~0UL - dev_priv->ips.last_count1;
4112                 diff += total_count;
4113         } else {
4114                 diff = total_count - dev_priv->ips.last_count1;
4115         }
4116
4117         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4118                 if (cparams[i].i == dev_priv->ips.c_m &&
4119                     cparams[i].t == dev_priv->ips.r_t) {
4120                         m = cparams[i].m;
4121                         c = cparams[i].c;
4122                         break;
4123                 }
4124         }
4125
4126         diff = div_u64(diff, diff1);
4127         ret = ((m * diff) + c);
4128         ret = div_u64(ret, 10);
4129
4130         dev_priv->ips.last_count1 = total_count;
4131         dev_priv->ips.last_time1 = now;
4132
4133         dev_priv->ips.chipset_power = ret;
4134
4135         return ret;
4136 }
4137
4138 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4139 {
4140         struct drm_device *dev = dev_priv->dev;
4141         unsigned long val;
4142
4143         if (INTEL_INFO(dev)->gen != 5)
4144                 return 0;
4145
4146         spin_lock_irq(&mchdev_lock);
4147
4148         val = __i915_chipset_val(dev_priv);
4149
4150         spin_unlock_irq(&mchdev_lock);
4151
4152         return val;
4153 }
4154
4155 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4156 {
4157         unsigned long m, x, b;
4158         u32 tsfs;
4159
4160         tsfs = I915_READ(TSFS);
4161
4162         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4163         x = I915_READ8(TR1);
4164
4165         b = tsfs & TSFS_INTR_MASK;
4166
4167         return ((m * x) / 127) - b;
4168 }
4169
4170 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4171 {
4172         struct drm_device *dev = dev_priv->dev;
4173         static const struct v_table {
4174                 u16 vd; /* in .1 mil */
4175                 u16 vm; /* in .1 mil */
4176         } v_table[] = {
4177                 { 0, 0, },
4178                 { 375, 0, },
4179                 { 500, 0, },
4180                 { 625, 0, },
4181                 { 750, 0, },
4182                 { 875, 0, },
4183                 { 1000, 0, },
4184                 { 1125, 0, },
4185                 { 4125, 3000, },
4186                 { 4125, 3000, },
4187                 { 4125, 3000, },
4188                 { 4125, 3000, },
4189                 { 4125, 3000, },
4190                 { 4125, 3000, },
4191                 { 4125, 3000, },
4192                 { 4125, 3000, },
4193                 { 4125, 3000, },
4194                 { 4125, 3000, },
4195                 { 4125, 3000, },
4196                 { 4125, 3000, },
4197                 { 4125, 3000, },
4198                 { 4125, 3000, },
4199                 { 4125, 3000, },
4200                 { 4125, 3000, },
4201                 { 4125, 3000, },
4202                 { 4125, 3000, },
4203                 { 4125, 3000, },
4204                 { 4125, 3000, },
4205                 { 4125, 3000, },
4206                 { 4125, 3000, },
4207                 { 4125, 3000, },
4208                 { 4125, 3000, },
4209                 { 4250, 3125, },
4210                 { 4375, 3250, },
4211                 { 4500, 3375, },
4212                 { 4625, 3500, },
4213                 { 4750, 3625, },
4214                 { 4875, 3750, },
4215                 { 5000, 3875, },
4216                 { 5125, 4000, },
4217                 { 5250, 4125, },
4218                 { 5375, 4250, },
4219                 { 5500, 4375, },
4220                 { 5625, 4500, },
4221                 { 5750, 4625, },
4222                 { 5875, 4750, },
4223                 { 6000, 4875, },
4224                 { 6125, 5000, },
4225                 { 6250, 5125, },
4226                 { 6375, 5250, },
4227                 { 6500, 5375, },
4228                 { 6625, 5500, },
4229                 { 6750, 5625, },
4230                 { 6875, 5750, },
4231                 { 7000, 5875, },
4232                 { 7125, 6000, },
4233                 { 7250, 6125, },
4234                 { 7375, 6250, },
4235                 { 7500, 6375, },
4236                 { 7625, 6500, },
4237                 { 7750, 6625, },
4238                 { 7875, 6750, },
4239                 { 8000, 6875, },
4240                 { 8125, 7000, },
4241                 { 8250, 7125, },
4242                 { 8375, 7250, },
4243                 { 8500, 7375, },
4244                 { 8625, 7500, },
4245                 { 8750, 7625, },
4246                 { 8875, 7750, },
4247                 { 9000, 7875, },
4248                 { 9125, 8000, },
4249                 { 9250, 8125, },
4250                 { 9375, 8250, },
4251                 { 9500, 8375, },
4252                 { 9625, 8500, },
4253                 { 9750, 8625, },
4254                 { 9875, 8750, },
4255                 { 10000, 8875, },
4256                 { 10125, 9000, },
4257                 { 10250, 9125, },
4258                 { 10375, 9250, },
4259                 { 10500, 9375, },
4260                 { 10625, 9500, },
4261                 { 10750, 9625, },
4262                 { 10875, 9750, },
4263                 { 11000, 9875, },
4264                 { 11125, 10000, },
4265                 { 11250, 10125, },
4266                 { 11375, 10250, },
4267                 { 11500, 10375, },
4268                 { 11625, 10500, },
4269                 { 11750, 10625, },
4270                 { 11875, 10750, },
4271                 { 12000, 10875, },
4272                 { 12125, 11000, },
4273                 { 12250, 11125, },
4274                 { 12375, 11250, },
4275                 { 12500, 11375, },
4276                 { 12625, 11500, },
4277                 { 12750, 11625, },
4278                 { 12875, 11750, },
4279                 { 13000, 11875, },
4280                 { 13125, 12000, },
4281                 { 13250, 12125, },
4282                 { 13375, 12250, },
4283                 { 13500, 12375, },
4284                 { 13625, 12500, },
4285                 { 13750, 12625, },
4286                 { 13875, 12750, },
4287                 { 14000, 12875, },
4288                 { 14125, 13000, },
4289                 { 14250, 13125, },
4290                 { 14375, 13250, },
4291                 { 14500, 13375, },
4292                 { 14625, 13500, },
4293                 { 14750, 13625, },
4294                 { 14875, 13750, },
4295                 { 15000, 13875, },
4296                 { 15125, 14000, },
4297                 { 15250, 14125, },
4298                 { 15375, 14250, },
4299                 { 15500, 14375, },
4300                 { 15625, 14500, },
4301                 { 15750, 14625, },
4302                 { 15875, 14750, },
4303                 { 16000, 14875, },
4304                 { 16125, 15000, },
4305         };
4306         if (INTEL_INFO(dev)->is_mobile)
4307                 return v_table[pxvid].vm;
4308         else
4309                 return v_table[pxvid].vd;
4310 }
4311
4312 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4313 {
4314         struct timespec now, diff1;
4315         u64 diff;
4316         unsigned long diffms;
4317         u32 count;
4318
4319         assert_spin_locked(&mchdev_lock);
4320
4321         getrawmonotonic(&now);
4322         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4323
4324         /* Don't divide by 0 */
4325         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4326         if (!diffms)
4327                 return;
4328
4329         count = I915_READ(GFXEC);
4330
4331         if (count < dev_priv->ips.last_count2) {
4332                 diff = ~0UL - dev_priv->ips.last_count2;
4333                 diff += count;
4334         } else {
4335                 diff = count - dev_priv->ips.last_count2;
4336         }
4337
4338         dev_priv->ips.last_count2 = count;
4339         dev_priv->ips.last_time2 = now;
4340
4341         /* More magic constants... */
4342         diff = diff * 1181;
4343         diff = div_u64(diff, diffms * 10);
4344         dev_priv->ips.gfx_power = diff;
4345 }
4346
4347 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4348 {
4349         struct drm_device *dev = dev_priv->dev;
4350
4351         if (INTEL_INFO(dev)->gen != 5)
4352                 return;
4353
4354         spin_lock_irq(&mchdev_lock);
4355
4356         __i915_update_gfx_val(dev_priv);
4357
4358         spin_unlock_irq(&mchdev_lock);
4359 }
4360
4361 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4362 {
4363         unsigned long t, corr, state1, corr2, state2;
4364         u32 pxvid, ext_v;
4365
4366         assert_spin_locked(&mchdev_lock);
4367
4368         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4369         pxvid = (pxvid >> 24) & 0x7f;
4370         ext_v = pvid_to_extvid(dev_priv, pxvid);
4371
4372         state1 = ext_v;
4373
4374         t = i915_mch_val(dev_priv);
4375
4376         /* Revel in the empirically derived constants */
4377
4378         /* Correction factor in 1/100000 units */
4379         if (t > 80)
4380                 corr = ((t * 2349) + 135940);
4381         else if (t >= 50)
4382                 corr = ((t * 964) + 29317);
4383         else /* < 50 */
4384                 corr = ((t * 301) + 1004);
4385
4386         corr = corr * ((150142 * state1) / 10000 - 78642);
4387         corr /= 100000;
4388         corr2 = (corr * dev_priv->ips.corr);
4389
4390         state2 = (corr2 * state1) / 10000;
4391         state2 /= 100; /* convert to mW */
4392
4393         __i915_update_gfx_val(dev_priv);
4394
4395         return dev_priv->ips.gfx_power + state2;
4396 }
4397
4398 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4399 {
4400         struct drm_device *dev = dev_priv->dev;
4401         unsigned long val;
4402
4403         if (INTEL_INFO(dev)->gen != 5)
4404                 return 0;
4405
4406         spin_lock_irq(&mchdev_lock);
4407
4408         val = __i915_gfx_val(dev_priv);
4409
4410         spin_unlock_irq(&mchdev_lock);
4411
4412         return val;
4413 }
4414
4415 /**
4416  * i915_read_mch_val - return value for IPS use
4417  *
4418  * Calculate and return a value for the IPS driver to use when deciding whether
4419  * we have thermal and power headroom to increase CPU or GPU power budget.
4420  */
4421 unsigned long i915_read_mch_val(void)
4422 {
4423         struct drm_i915_private *dev_priv;
4424         unsigned long chipset_val, graphics_val, ret = 0;
4425
4426         spin_lock_irq(&mchdev_lock);
4427         if (!i915_mch_dev)
4428                 goto out_unlock;
4429         dev_priv = i915_mch_dev;
4430
4431         chipset_val = __i915_chipset_val(dev_priv);
4432         graphics_val = __i915_gfx_val(dev_priv);
4433
4434         ret = chipset_val + graphics_val;
4435
4436 out_unlock:
4437         spin_unlock_irq(&mchdev_lock);
4438
4439         return ret;
4440 }
4441 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4442
4443 /**
4444  * i915_gpu_raise - raise GPU frequency limit
4445  *
4446  * Raise the limit; IPS indicates we have thermal headroom.
4447  */
4448 bool i915_gpu_raise(void)
4449 {
4450         struct drm_i915_private *dev_priv;
4451         bool ret = true;
4452
4453         spin_lock_irq(&mchdev_lock);
4454         if (!i915_mch_dev) {
4455                 ret = false;
4456                 goto out_unlock;
4457         }
4458         dev_priv = i915_mch_dev;
4459
4460         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4461                 dev_priv->ips.max_delay--;
4462
4463 out_unlock:
4464         spin_unlock_irq(&mchdev_lock);
4465
4466         return ret;
4467 }
4468 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4469
4470 /**
4471  * i915_gpu_lower - lower GPU frequency limit
4472  *
4473  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4474  * frequency maximum.
4475  */
4476 bool i915_gpu_lower(void)
4477 {
4478         struct drm_i915_private *dev_priv;
4479         bool ret = true;
4480
4481         spin_lock_irq(&mchdev_lock);
4482         if (!i915_mch_dev) {
4483                 ret = false;
4484                 goto out_unlock;
4485         }
4486         dev_priv = i915_mch_dev;
4487
4488         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4489                 dev_priv->ips.max_delay++;
4490
4491 out_unlock:
4492         spin_unlock_irq(&mchdev_lock);
4493
4494         return ret;
4495 }
4496 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4497
4498 /**
4499  * i915_gpu_busy - indicate GPU business to IPS
4500  *
4501  * Tell the IPS driver whether or not the GPU is busy.
4502  */
4503 bool i915_gpu_busy(void)
4504 {
4505         struct drm_i915_private *dev_priv;
4506         struct intel_engine_cs *ring;
4507         bool ret = false;
4508         int i;
4509
4510         spin_lock_irq(&mchdev_lock);
4511         if (!i915_mch_dev)
4512                 goto out_unlock;
4513         dev_priv = i915_mch_dev;
4514
4515         for_each_ring(ring, dev_priv, i)
4516                 ret |= !list_empty(&ring->request_list);
4517
4518 out_unlock:
4519         spin_unlock_irq(&mchdev_lock);
4520
4521         return ret;
4522 }
4523 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4524
4525 /**
4526  * i915_gpu_turbo_disable - disable graphics turbo
4527  *
4528  * Disable graphics turbo by resetting the max frequency and setting the
4529  * current frequency to the default.
4530  */
4531 bool i915_gpu_turbo_disable(void)
4532 {
4533         struct drm_i915_private *dev_priv;
4534         bool ret = true;
4535
4536         spin_lock_irq(&mchdev_lock);
4537         if (!i915_mch_dev) {
4538                 ret = false;
4539                 goto out_unlock;
4540         }
4541         dev_priv = i915_mch_dev;
4542
4543         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4544
4545         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4546                 ret = false;
4547
4548 out_unlock:
4549         spin_unlock_irq(&mchdev_lock);
4550
4551         return ret;
4552 }
4553 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4554
4555 /**
4556  * Tells the intel_ips driver that the i915 driver is now loaded, if
4557  * IPS got loaded first.
4558  *
4559  * This awkward dance is so that neither module has to depend on the
4560  * other in order for IPS to do the appropriate communication of
4561  * GPU turbo limits to i915.
4562  */
4563 static void
4564 ips_ping_for_i915_load(void)
4565 {
4566         void (*link)(void);
4567
4568         link = symbol_get(ips_link_to_i915_driver);
4569         if (link) {
4570                 link();
4571                 symbol_put(ips_link_to_i915_driver);
4572         }
4573 }
4574
4575 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4576 {
4577         /* We only register the i915 ips part with intel-ips once everything is
4578          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4579         spin_lock_irq(&mchdev_lock);
4580         i915_mch_dev = dev_priv;
4581         spin_unlock_irq(&mchdev_lock);
4582
4583         ips_ping_for_i915_load();
4584 }
4585
4586 void intel_gpu_ips_teardown(void)
4587 {
4588         spin_lock_irq(&mchdev_lock);
4589         i915_mch_dev = NULL;
4590         spin_unlock_irq(&mchdev_lock);
4591 }
4592
4593 static void intel_init_emon(struct drm_device *dev)
4594 {
4595         struct drm_i915_private *dev_priv = dev->dev_private;
4596         u32 lcfuse;
4597         u8 pxw[16];
4598         int i;
4599
4600         /* Disable to program */
4601         I915_WRITE(ECR, 0);
4602         POSTING_READ(ECR);
4603
4604         /* Program energy weights for various events */
4605         I915_WRITE(SDEW, 0x15040d00);
4606         I915_WRITE(CSIEW0, 0x007f0000);
4607         I915_WRITE(CSIEW1, 0x1e220004);
4608         I915_WRITE(CSIEW2, 0x04000004);
4609
4610         for (i = 0; i < 5; i++)
4611                 I915_WRITE(PEW + (i * 4), 0);
4612         for (i = 0; i < 3; i++)
4613                 I915_WRITE(DEW + (i * 4), 0);
4614
4615         /* Program P-state weights to account for frequency power adjustment */
4616         for (i = 0; i < 16; i++) {
4617                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4618                 unsigned long freq = intel_pxfreq(pxvidfreq);
4619                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4620                         PXVFREQ_PX_SHIFT;
4621                 unsigned long val;
4622
4623                 val = vid * vid;
4624                 val *= (freq / 1000);
4625                 val *= 255;
4626                 val /= (127*127*900);
4627                 if (val > 0xff)
4628                         DRM_ERROR("bad pxval: %ld\n", val);
4629                 pxw[i] = val;
4630         }
4631         /* Render standby states get 0 weight */
4632         pxw[14] = 0;
4633         pxw[15] = 0;
4634
4635         for (i = 0; i < 4; i++) {
4636                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4637                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4638                 I915_WRITE(PXW + (i * 4), val);
4639         }
4640
4641         /* Adjust magic regs to magic values (more experimental results) */
4642         I915_WRITE(OGW0, 0);
4643         I915_WRITE(OGW1, 0);
4644         I915_WRITE(EG0, 0x00007f00);
4645         I915_WRITE(EG1, 0x0000000e);
4646         I915_WRITE(EG2, 0x000e0000);
4647         I915_WRITE(EG3, 0x68000300);
4648         I915_WRITE(EG4, 0x42000000);
4649         I915_WRITE(EG5, 0x00140031);
4650         I915_WRITE(EG6, 0);
4651         I915_WRITE(EG7, 0);
4652
4653         for (i = 0; i < 8; i++)
4654                 I915_WRITE(PXWL + (i * 4), 0);
4655
4656         /* Enable PMON + select events */
4657         I915_WRITE(ECR, 0x80000019);
4658
4659         lcfuse = I915_READ(LCFUSE02);
4660
4661         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4662 }
4663
4664 void intel_init_gt_powersave(struct drm_device *dev)
4665 {
4666         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4667
4668         if (IS_VALLEYVIEW(dev))
4669                 valleyview_init_gt_powersave(dev);
4670 }
4671
4672 void intel_cleanup_gt_powersave(struct drm_device *dev)
4673 {
4674         if (IS_VALLEYVIEW(dev))
4675                 valleyview_cleanup_gt_powersave(dev);
4676 }
4677
4678 void intel_disable_gt_powersave(struct drm_device *dev)
4679 {
4680         struct drm_i915_private *dev_priv = dev->dev_private;
4681
4682         /* Interrupts should be disabled already to avoid re-arming. */
4683         WARN_ON(dev->irq_enabled);
4684
4685         if (IS_IRONLAKE_M(dev)) {
4686                 ironlake_disable_drps(dev);
4687                 ironlake_disable_rc6(dev);
4688         } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
4689                 if (cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work))
4690                         intel_runtime_pm_put(dev_priv);
4691
4692                 cancel_work_sync(&dev_priv->rps.work);
4693                 mutex_lock(&dev_priv->rps.hw_lock);
4694                 if (IS_VALLEYVIEW(dev))
4695                         valleyview_disable_rps(dev);
4696                 else
4697                         gen6_disable_rps(dev);
4698                 dev_priv->rps.enabled = false;
4699                 mutex_unlock(&dev_priv->rps.hw_lock);
4700         }
4701 }
4702
4703 static void intel_gen6_powersave_work(struct work_struct *work)
4704 {
4705         struct drm_i915_private *dev_priv =
4706                 container_of(work, struct drm_i915_private,
4707                              rps.delayed_resume_work.work);
4708         struct drm_device *dev = dev_priv->dev;
4709
4710         mutex_lock(&dev_priv->rps.hw_lock);
4711
4712         if (IS_VALLEYVIEW(dev)) {
4713                 valleyview_enable_rps(dev);
4714         } else if (IS_BROADWELL(dev)) {
4715                 gen8_enable_rps(dev);
4716                 __gen6_update_ring_freq(dev);
4717         } else {
4718                 gen6_enable_rps(dev);
4719                 __gen6_update_ring_freq(dev);
4720         }
4721         dev_priv->rps.enabled = true;
4722         mutex_unlock(&dev_priv->rps.hw_lock);
4723
4724         intel_runtime_pm_put(dev_priv);
4725 }
4726
4727 void intel_enable_gt_powersave(struct drm_device *dev)
4728 {
4729         struct drm_i915_private *dev_priv = dev->dev_private;
4730
4731         if (IS_IRONLAKE_M(dev)) {
4732                 mutex_lock(&dev->struct_mutex);
4733                 ironlake_enable_drps(dev);
4734                 ironlake_enable_rc6(dev);
4735                 intel_init_emon(dev);
4736                 mutex_unlock(&dev->struct_mutex);
4737         } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
4738                 /*
4739                  * PCU communication is slow and this doesn't need to be
4740                  * done at any specific time, so do this out of our fast path
4741                  * to make resume and init faster.
4742                  *
4743                  * We depend on the HW RC6 power context save/restore
4744                  * mechanism when entering D3 through runtime PM suspend. So
4745                  * disable RPM until RPS/RC6 is properly setup. We can only
4746                  * get here via the driver load/system resume/runtime resume
4747                  * paths, so the _noresume version is enough (and in case of
4748                  * runtime resume it's necessary).
4749                  */
4750                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4751                                            round_jiffies_up_relative(HZ)))
4752                         intel_runtime_pm_get_noresume(dev_priv);
4753         }
4754 }
4755
4756 void intel_reset_gt_powersave(struct drm_device *dev)
4757 {
4758         struct drm_i915_private *dev_priv = dev->dev_private;
4759
4760         dev_priv->rps.enabled = false;
4761         intel_enable_gt_powersave(dev);
4762 }
4763
4764 static void ibx_init_clock_gating(struct drm_device *dev)
4765 {
4766         struct drm_i915_private *dev_priv = dev->dev_private;
4767
4768         /*
4769          * On Ibex Peak and Cougar Point, we need to disable clock
4770          * gating for the panel power sequencer or it will fail to
4771          * start up when no ports are active.
4772          */
4773         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4774 }
4775
4776 static void g4x_disable_trickle_feed(struct drm_device *dev)
4777 {
4778         struct drm_i915_private *dev_priv = dev->dev_private;
4779         int pipe;
4780
4781         for_each_pipe(pipe) {
4782                 I915_WRITE(DSPCNTR(pipe),
4783                            I915_READ(DSPCNTR(pipe)) |
4784                            DISPPLANE_TRICKLE_FEED_DISABLE);
4785                 intel_flush_primary_plane(dev_priv, pipe);
4786         }
4787 }
4788
4789 static void ilk_init_lp_watermarks(struct drm_device *dev)
4790 {
4791         struct drm_i915_private *dev_priv = dev->dev_private;
4792
4793         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4794         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4795         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4796
4797         /*
4798          * Don't touch WM1S_LP_EN here.
4799          * Doing so could cause underruns.
4800          */
4801 }
4802
4803 static void ironlake_init_clock_gating(struct drm_device *dev)
4804 {
4805         struct drm_i915_private *dev_priv = dev->dev_private;
4806         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4807
4808         /*
4809          * Required for FBC
4810          * WaFbcDisableDpfcClockGating:ilk
4811          */
4812         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4813                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4814                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4815
4816         I915_WRITE(PCH_3DCGDIS0,
4817                    MARIUNIT_CLOCK_GATE_DISABLE |
4818                    SVSMUNIT_CLOCK_GATE_DISABLE);
4819         I915_WRITE(PCH_3DCGDIS1,
4820                    VFMUNIT_CLOCK_GATE_DISABLE);
4821
4822         /*
4823          * According to the spec the following bits should be set in
4824          * order to enable memory self-refresh
4825          * The bit 22/21 of 0x42004
4826          * The bit 5 of 0x42020
4827          * The bit 15 of 0x45000
4828          */
4829         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4830                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4831                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4832         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4833         I915_WRITE(DISP_ARB_CTL,
4834                    (I915_READ(DISP_ARB_CTL) |
4835                     DISP_FBC_WM_DIS));
4836
4837         ilk_init_lp_watermarks(dev);
4838
4839         /*
4840          * Based on the document from hardware guys the following bits
4841          * should be set unconditionally in order to enable FBC.
4842          * The bit 22 of 0x42000
4843          * The bit 22 of 0x42004
4844          * The bit 7,8,9 of 0x42020.
4845          */
4846         if (IS_IRONLAKE_M(dev)) {
4847                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4848                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4849                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4850                            ILK_FBCQ_DIS);
4851                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4852                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4853                            ILK_DPARB_GATE);
4854         }
4855
4856         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4857
4858         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4859                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4860                    ILK_ELPIN_409_SELECT);
4861         I915_WRITE(_3D_CHICKEN2,
4862                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4863                    _3D_CHICKEN2_WM_READ_PIPELINED);
4864
4865         /* WaDisableRenderCachePipelinedFlush:ilk */
4866         I915_WRITE(CACHE_MODE_0,
4867                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4868
4869         /* WaDisable_RenderCache_OperationalFlush:ilk */
4870         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4871
4872         g4x_disable_trickle_feed(dev);
4873
4874         ibx_init_clock_gating(dev);
4875 }
4876
4877 static void cpt_init_clock_gating(struct drm_device *dev)
4878 {
4879         struct drm_i915_private *dev_priv = dev->dev_private;
4880         int pipe;
4881         uint32_t val;
4882
4883         /*
4884          * On Ibex Peak and Cougar Point, we need to disable clock
4885          * gating for the panel power sequencer or it will fail to
4886          * start up when no ports are active.
4887          */
4888         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4889                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4890                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
4891         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4892                    DPLS_EDP_PPS_FIX_DIS);
4893         /* The below fixes the weird display corruption, a few pixels shifted
4894          * downward, on (only) LVDS of some HP laptops with IVY.
4895          */
4896         for_each_pipe(pipe) {
4897                 val = I915_READ(TRANS_CHICKEN2(pipe));
4898                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4899                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4900                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4901                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4902                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4903                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4904                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4905                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4906         }
4907         /* WADP0ClockGatingDisable */
4908         for_each_pipe(pipe) {
4909                 I915_WRITE(TRANS_CHICKEN1(pipe),
4910                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4911         }
4912 }
4913
4914 static void gen6_check_mch_setup(struct drm_device *dev)
4915 {
4916         struct drm_i915_private *dev_priv = dev->dev_private;
4917         uint32_t tmp;
4918
4919         tmp = I915_READ(MCH_SSKPD);
4920         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4921                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4922                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4923                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4924         }
4925 }
4926
4927 static void gen6_init_clock_gating(struct drm_device *dev)
4928 {
4929         struct drm_i915_private *dev_priv = dev->dev_private;
4930         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4931
4932         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4933
4934         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4935                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4936                    ILK_ELPIN_409_SELECT);
4937
4938         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4939         I915_WRITE(_3D_CHICKEN,
4940                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4941
4942         /* WaSetupGtModeTdRowDispatch:snb */
4943         if (IS_SNB_GT1(dev))
4944                 I915_WRITE(GEN6_GT_MODE,
4945                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4946
4947         /* WaDisable_RenderCache_OperationalFlush:snb */
4948         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4949
4950         /*
4951          * BSpec recoomends 8x4 when MSAA is used,
4952          * however in practice 16x4 seems fastest.
4953          *
4954          * Note that PS/WM thread counts depend on the WIZ hashing
4955          * disable bit, which we don't touch here, but it's good
4956          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4957          */
4958         I915_WRITE(GEN6_GT_MODE,
4959                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4960
4961         ilk_init_lp_watermarks(dev);
4962
4963         I915_WRITE(CACHE_MODE_0,
4964                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4965
4966         I915_WRITE(GEN6_UCGCTL1,
4967                    I915_READ(GEN6_UCGCTL1) |
4968                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4969                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4970
4971         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4972          * gating disable must be set.  Failure to set it results in
4973          * flickering pixels due to Z write ordering failures after
4974          * some amount of runtime in the Mesa "fire" demo, and Unigine
4975          * Sanctuary and Tropics, and apparently anything else with
4976          * alpha test or pixel discard.
4977          *
4978          * According to the spec, bit 11 (RCCUNIT) must also be set,
4979          * but we didn't debug actual testcases to find it out.
4980          *
4981          * WaDisableRCCUnitClockGating:snb
4982          * WaDisableRCPBUnitClockGating:snb
4983          */
4984         I915_WRITE(GEN6_UCGCTL2,
4985                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4986                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4987
4988         /* WaStripsFansDisableFastClipPerformanceFix:snb */
4989         I915_WRITE(_3D_CHICKEN3,
4990                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4991
4992         /*
4993          * Bspec says:
4994          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4995          * 3DSTATE_SF number of SF output attributes is more than 16."
4996          */
4997         I915_WRITE(_3D_CHICKEN3,
4998                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4999
5000         /*
5001          * According to the spec the following bits should be
5002          * set in order to enable memory self-refresh and fbc:
5003          * The bit21 and bit22 of 0x42000
5004          * The bit21 and bit22 of 0x42004
5005          * The bit5 and bit7 of 0x42020
5006          * The bit14 of 0x70180
5007          * The bit14 of 0x71180
5008          *
5009          * WaFbcAsynchFlipDisableFbcQueue:snb
5010          */
5011         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5012                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5013                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5014         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5015                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5016                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5017         I915_WRITE(ILK_DSPCLK_GATE_D,
5018                    I915_READ(ILK_DSPCLK_GATE_D) |
5019                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
5020                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5021
5022         g4x_disable_trickle_feed(dev);
5023
5024         cpt_init_clock_gating(dev);
5025
5026         gen6_check_mch_setup(dev);
5027 }
5028
5029 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5030 {
5031         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5032
5033         /*
5034          * WaVSThreadDispatchOverride:ivb,vlv
5035          *
5036          * This actually overrides the dispatch
5037          * mode for all thread types.
5038          */
5039         reg &= ~GEN7_FF_SCHED_MASK;
5040         reg |= GEN7_FF_TS_SCHED_HW;
5041         reg |= GEN7_FF_VS_SCHED_HW;
5042         reg |= GEN7_FF_DS_SCHED_HW;
5043
5044         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5045 }
5046
5047 static void lpt_init_clock_gating(struct drm_device *dev)
5048 {
5049         struct drm_i915_private *dev_priv = dev->dev_private;
5050
5051         /*
5052          * TODO: this bit should only be enabled when really needed, then
5053          * disabled when not needed anymore in order to save power.
5054          */
5055         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5056                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5057                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5058                            PCH_LP_PARTITION_LEVEL_DISABLE);
5059
5060         /* WADPOClockGatingDisable:hsw */
5061         I915_WRITE(_TRANSA_CHICKEN1,
5062                    I915_READ(_TRANSA_CHICKEN1) |
5063                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5064 }
5065
5066 static void lpt_suspend_hw(struct drm_device *dev)
5067 {
5068         struct drm_i915_private *dev_priv = dev->dev_private;
5069
5070         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5071                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5072
5073                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5074                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5075         }
5076 }
5077
5078 static void gen8_init_clock_gating(struct drm_device *dev)
5079 {
5080         struct drm_i915_private *dev_priv = dev->dev_private;
5081         enum pipe pipe;
5082
5083         I915_WRITE(WM3_LP_ILK, 0);
5084         I915_WRITE(WM2_LP_ILK, 0);
5085         I915_WRITE(WM1_LP_ILK, 0);
5086
5087         /* FIXME(BDW): Check all the w/a, some might only apply to
5088          * pre-production hw. */
5089
5090         /* WaDisablePartialInstShootdown:bdw */
5091         I915_WRITE(GEN8_ROW_CHICKEN,
5092                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5093
5094         /* WaDisableThreadStallDopClockGating:bdw */
5095         /* FIXME: Unclear whether we really need this on production bdw. */
5096         I915_WRITE(GEN8_ROW_CHICKEN,
5097                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5098
5099         /*
5100          * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5101          * pre-production hardware
5102          */
5103         I915_WRITE(HALF_SLICE_CHICKEN3,
5104                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5105         I915_WRITE(HALF_SLICE_CHICKEN3,
5106                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5107         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5108
5109         I915_WRITE(_3D_CHICKEN3,
5110                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5111
5112         I915_WRITE(COMMON_SLICE_CHICKEN2,
5113                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5114
5115         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5116                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5117
5118         /* WaDisableDopClockGating:bdw May not be needed for production */
5119         I915_WRITE(GEN7_ROW_CHICKEN2,
5120                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5121
5122         /* WaSwitchSolVfFArbitrationPriority:bdw */
5123         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5124
5125         /* WaPsrDPAMaskVBlankInSRD:bdw */
5126         I915_WRITE(CHICKEN_PAR1_1,
5127                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5128
5129         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5130         for_each_pipe(pipe) {
5131                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5132                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
5133                            BDW_DPRS_MASK_VBLANK_SRD);
5134         }
5135
5136         /* Use Force Non-Coherent whenever executing a 3D context. This is a
5137          * workaround for for a possible hang in the unlikely event a TLB
5138          * invalidation occurs during a PSD flush.
5139          */
5140         I915_WRITE(HDC_CHICKEN0,
5141                    I915_READ(HDC_CHICKEN0) |
5142                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5143
5144         /* WaVSRefCountFullforceMissDisable:bdw */
5145         /* WaDSRefCountFullforceMissDisable:bdw */
5146         I915_WRITE(GEN7_FF_THREAD_MODE,
5147                    I915_READ(GEN7_FF_THREAD_MODE) &
5148                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5149
5150         /*
5151          * BSpec recommends 8x4 when MSAA is used,
5152          * however in practice 16x4 seems fastest.
5153          *
5154          * Note that PS/WM thread counts depend on the WIZ hashing
5155          * disable bit, which we don't touch here, but it's good
5156          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5157          */
5158         I915_WRITE(GEN7_GT_MODE,
5159                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5160
5161         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5162                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5163
5164         /* WaDisableSDEUnitClockGating:bdw */
5165         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5166                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5167
5168         /* Wa4x4STCOptimizationDisable:bdw */
5169         I915_WRITE(CACHE_MODE_1,
5170                    _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5171 }
5172
5173 static void haswell_init_clock_gating(struct drm_device *dev)
5174 {
5175         struct drm_i915_private *dev_priv = dev->dev_private;
5176
5177         ilk_init_lp_watermarks(dev);
5178
5179         /* L3 caching of data atomics doesn't work -- disable it. */
5180         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5181         I915_WRITE(HSW_ROW_CHICKEN3,
5182                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5183
5184         /* This is required by WaCatErrorRejectionIssue:hsw */
5185         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5186                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5187                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5188
5189         /* WaVSRefCountFullforceMissDisable:hsw */
5190         I915_WRITE(GEN7_FF_THREAD_MODE,
5191                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5192
5193         /* WaDisable_RenderCache_OperationalFlush:hsw */
5194         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5195
5196         /* enable HiZ Raw Stall Optimization */
5197         I915_WRITE(CACHE_MODE_0_GEN7,
5198                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5199
5200         /* WaDisable4x2SubspanOptimization:hsw */
5201         I915_WRITE(CACHE_MODE_1,
5202                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5203
5204         /*
5205          * BSpec recommends 8x4 when MSAA is used,
5206          * however in practice 16x4 seems fastest.
5207          *
5208          * Note that PS/WM thread counts depend on the WIZ hashing
5209          * disable bit, which we don't touch here, but it's good
5210          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5211          */
5212         I915_WRITE(GEN7_GT_MODE,
5213                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5214
5215         /* WaSwitchSolVfFArbitrationPriority:hsw */
5216         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5217
5218         /* WaRsPkgCStateDisplayPMReq:hsw */
5219         I915_WRITE(CHICKEN_PAR1_1,
5220                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5221
5222         lpt_init_clock_gating(dev);
5223 }
5224
5225 static void ivybridge_init_clock_gating(struct drm_device *dev)
5226 {
5227         struct drm_i915_private *dev_priv = dev->dev_private;
5228         uint32_t snpcr;
5229
5230         ilk_init_lp_watermarks(dev);
5231
5232         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5233
5234         /* WaDisableEarlyCull:ivb */
5235         I915_WRITE(_3D_CHICKEN3,
5236                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5237
5238         /* WaDisableBackToBackFlipFix:ivb */
5239         I915_WRITE(IVB_CHICKEN3,
5240                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5241                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5242
5243         /* WaDisablePSDDualDispatchEnable:ivb */
5244         if (IS_IVB_GT1(dev))
5245                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5246                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5247
5248         /* WaDisable_RenderCache_OperationalFlush:ivb */
5249         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5250
5251         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5252         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5253                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5254
5255         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5256         I915_WRITE(GEN7_L3CNTLREG1,
5257                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5258         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5259                    GEN7_WA_L3_CHICKEN_MODE);
5260         if (IS_IVB_GT1(dev))
5261                 I915_WRITE(GEN7_ROW_CHICKEN2,
5262                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5263         else {
5264                 /* must write both registers */
5265                 I915_WRITE(GEN7_ROW_CHICKEN2,
5266                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5267                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5268                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5269         }
5270
5271         /* WaForceL3Serialization:ivb */
5272         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5273                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5274
5275         /*
5276          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5277          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5278          */
5279         I915_WRITE(GEN6_UCGCTL2,
5280                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5281
5282         /* This is required by WaCatErrorRejectionIssue:ivb */
5283         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5284                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5285                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5286
5287         g4x_disable_trickle_feed(dev);
5288
5289         gen7_setup_fixed_func_scheduler(dev_priv);
5290
5291         if (0) { /* causes HiZ corruption on ivb:gt1 */
5292                 /* enable HiZ Raw Stall Optimization */
5293                 I915_WRITE(CACHE_MODE_0_GEN7,
5294                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5295         }
5296
5297         /* WaDisable4x2SubspanOptimization:ivb */
5298         I915_WRITE(CACHE_MODE_1,
5299                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5300
5301         /*
5302          * BSpec recommends 8x4 when MSAA is used,
5303          * however in practice 16x4 seems fastest.
5304          *
5305          * Note that PS/WM thread counts depend on the WIZ hashing
5306          * disable bit, which we don't touch here, but it's good
5307          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5308          */
5309         I915_WRITE(GEN7_GT_MODE,
5310                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5311
5312         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5313         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5314         snpcr |= GEN6_MBC_SNPCR_MED;
5315         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5316
5317         if (!HAS_PCH_NOP(dev))
5318                 cpt_init_clock_gating(dev);
5319
5320         gen6_check_mch_setup(dev);
5321 }
5322
5323 static void valleyview_init_clock_gating(struct drm_device *dev)
5324 {
5325         struct drm_i915_private *dev_priv = dev->dev_private;
5326         u32 val;
5327
5328         mutex_lock(&dev_priv->rps.hw_lock);
5329         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5330         mutex_unlock(&dev_priv->rps.hw_lock);
5331         switch ((val >> 6) & 3) {
5332         case 0:
5333         case 1:
5334                 dev_priv->mem_freq = 800;
5335                 break;
5336         case 2:
5337                 dev_priv->mem_freq = 1066;
5338                 break;
5339         case 3:
5340                 dev_priv->mem_freq = 1333;
5341                 break;
5342         }
5343         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5344
5345         dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5346         DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5347                          dev_priv->vlv_cdclk_freq);
5348
5349         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5350
5351         /* WaDisableEarlyCull:vlv */
5352         I915_WRITE(_3D_CHICKEN3,
5353                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5354
5355         /* WaDisableBackToBackFlipFix:vlv */
5356         I915_WRITE(IVB_CHICKEN3,
5357                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5358                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5359
5360         /* WaPsdDispatchEnable:vlv */
5361         /* WaDisablePSDDualDispatchEnable:vlv */
5362         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5363                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5364                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5365
5366         /* WaDisable_RenderCache_OperationalFlush:vlv */
5367         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5368
5369         /* WaForceL3Serialization:vlv */
5370         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5371                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5372
5373         /* WaDisableDopClockGating:vlv */
5374         I915_WRITE(GEN7_ROW_CHICKEN2,
5375                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5376
5377         /* This is required by WaCatErrorRejectionIssue:vlv */
5378         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5379                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5380                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5381
5382         gen7_setup_fixed_func_scheduler(dev_priv);
5383
5384         /*
5385          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5386          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5387          */
5388         I915_WRITE(GEN6_UCGCTL2,
5389                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5390
5391         /* WaDisableL3Bank2xClockGate:vlv
5392          * Disabling L3 clock gating- MMIO 940c[25] = 1
5393          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5394         I915_WRITE(GEN7_UCGCTL4,
5395                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5396
5397         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5398
5399         /*
5400          * BSpec says this must be set, even though
5401          * WaDisable4x2SubspanOptimization isn't listed for VLV.
5402          */
5403         I915_WRITE(CACHE_MODE_1,
5404                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5405
5406         /*
5407          * WaIncreaseL3CreditsForVLVB0:vlv
5408          * This is the hardware default actually.
5409          */
5410         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5411
5412         /*
5413          * WaDisableVLVClockGating_VBIIssue:vlv
5414          * Disable clock gating on th GCFG unit to prevent a delay
5415          * in the reporting of vblank events.
5416          */
5417         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5418 }
5419
5420 static void cherryview_init_clock_gating(struct drm_device *dev)
5421 {
5422         struct drm_i915_private *dev_priv = dev->dev_private;
5423
5424         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5425
5426         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5427
5428         /* WaDisablePartialInstShootdown:chv */
5429         I915_WRITE(GEN8_ROW_CHICKEN,
5430                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5431
5432         /* WaDisableThreadStallDopClockGating:chv */
5433         I915_WRITE(GEN8_ROW_CHICKEN,
5434                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5435
5436         /* WaVSRefCountFullforceMissDisable:chv */
5437         /* WaDSRefCountFullforceMissDisable:chv */
5438         I915_WRITE(GEN7_FF_THREAD_MODE,
5439                    I915_READ(GEN7_FF_THREAD_MODE) &
5440                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5441
5442         /* WaDisableSemaphoreAndSyncFlipWait:chv */
5443         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5444                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5445
5446         /* WaDisableCSUnitClockGating:chv */
5447         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5448                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5449
5450         /* WaDisableSDEUnitClockGating:chv */
5451         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5452                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5453
5454         /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5455         I915_WRITE(HALF_SLICE_CHICKEN3,
5456                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5457
5458         /* WaDisableGunitClockGating:chv (pre-production hw) */
5459         I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5460                    GINT_DIS);
5461
5462         /* WaDisableFfDopClockGating:chv (pre-production hw) */
5463         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5464                    _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5465
5466         /* WaDisableDopClockGating:chv (pre-production hw) */
5467         I915_WRITE(GEN7_ROW_CHICKEN2,
5468                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5469         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5470                    GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5471 }
5472
5473 static void g4x_init_clock_gating(struct drm_device *dev)
5474 {
5475         struct drm_i915_private *dev_priv = dev->dev_private;
5476         uint32_t dspclk_gate;
5477
5478         I915_WRITE(RENCLK_GATE_D1, 0);
5479         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5480                    GS_UNIT_CLOCK_GATE_DISABLE |
5481                    CL_UNIT_CLOCK_GATE_DISABLE);
5482         I915_WRITE(RAMCLK_GATE_D, 0);
5483         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5484                 OVRUNIT_CLOCK_GATE_DISABLE |
5485                 OVCUNIT_CLOCK_GATE_DISABLE;
5486         if (IS_GM45(dev))
5487                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5488         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5489
5490         /* WaDisableRenderCachePipelinedFlush */
5491         I915_WRITE(CACHE_MODE_0,
5492                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5493
5494         /* WaDisable_RenderCache_OperationalFlush:g4x */
5495         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5496
5497         g4x_disable_trickle_feed(dev);
5498 }
5499
5500 static void crestline_init_clock_gating(struct drm_device *dev)
5501 {
5502         struct drm_i915_private *dev_priv = dev->dev_private;
5503
5504         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5505         I915_WRITE(RENCLK_GATE_D2, 0);
5506         I915_WRITE(DSPCLK_GATE_D, 0);
5507         I915_WRITE(RAMCLK_GATE_D, 0);
5508         I915_WRITE16(DEUC, 0);
5509         I915_WRITE(MI_ARB_STATE,
5510                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5511
5512         /* WaDisable_RenderCache_OperationalFlush:gen4 */
5513         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5514 }
5515
5516 static void broadwater_init_clock_gating(struct drm_device *dev)
5517 {
5518         struct drm_i915_private *dev_priv = dev->dev_private;
5519
5520         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5521                    I965_RCC_CLOCK_GATE_DISABLE |
5522                    I965_RCPB_CLOCK_GATE_DISABLE |
5523                    I965_ISC_CLOCK_GATE_DISABLE |
5524                    I965_FBC_CLOCK_GATE_DISABLE);
5525         I915_WRITE(RENCLK_GATE_D2, 0);
5526         I915_WRITE(MI_ARB_STATE,
5527                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5528
5529         /* WaDisable_RenderCache_OperationalFlush:gen4 */
5530         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5531 }
5532
5533 static void gen3_init_clock_gating(struct drm_device *dev)
5534 {
5535         struct drm_i915_private *dev_priv = dev->dev_private;
5536         u32 dstate = I915_READ(D_STATE);
5537
5538         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5539                 DSTATE_DOT_CLOCK_GATING;
5540         I915_WRITE(D_STATE, dstate);
5541
5542         if (IS_PINEVIEW(dev))
5543                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5544
5545         /* IIR "flip pending" means done if this bit is set */
5546         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5547
5548         /* interrupts should cause a wake up from C3 */
5549         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
5550
5551         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5552         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5553 }
5554
5555 static void i85x_init_clock_gating(struct drm_device *dev)
5556 {
5557         struct drm_i915_private *dev_priv = dev->dev_private;
5558
5559         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5560
5561         /* interrupts should cause a wake up from C3 */
5562         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5563                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
5564 }
5565
5566 static void i830_init_clock_gating(struct drm_device *dev)
5567 {
5568         struct drm_i915_private *dev_priv = dev->dev_private;
5569
5570         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5571 }
5572
5573 void intel_init_clock_gating(struct drm_device *dev)
5574 {
5575         struct drm_i915_private *dev_priv = dev->dev_private;
5576
5577         dev_priv->display.init_clock_gating(dev);
5578 }
5579
5580 void intel_suspend_hw(struct drm_device *dev)
5581 {
5582         if (HAS_PCH_LPT(dev))
5583                 lpt_suspend_hw(dev);
5584 }
5585
5586 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5587         for (i = 0;                                                     \
5588              i < (power_domains)->power_well_count &&                   \
5589                  ((power_well) = &(power_domains)->power_wells[i]);     \
5590              i++)                                                       \
5591                 if ((power_well)->domains & (domain_mask))
5592
5593 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5594         for (i = (power_domains)->power_well_count - 1;                  \
5595              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5596              i--)                                                        \
5597                 if ((power_well)->domains & (domain_mask))
5598
5599 /**
5600  * We should only use the power well if we explicitly asked the hardware to
5601  * enable it, so check if it's enabled and also check if we've requested it to
5602  * be enabled.
5603  */
5604 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5605                                    struct i915_power_well *power_well)
5606 {
5607         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5608                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5609 }
5610
5611 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
5612                                     enum intel_display_power_domain domain)
5613 {
5614         struct i915_power_domains *power_domains;
5615         struct i915_power_well *power_well;
5616         bool is_enabled;
5617         int i;
5618
5619         if (dev_priv->pm.suspended)
5620                 return false;
5621
5622         power_domains = &dev_priv->power_domains;
5623         is_enabled = true;
5624         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5625                 if (power_well->always_on)
5626                         continue;
5627
5628                 if (!power_well->count) {
5629                         is_enabled = false;
5630                         break;
5631                 }
5632         }
5633         return is_enabled;
5634 }
5635
5636 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5637                                  enum intel_display_power_domain domain)
5638 {
5639         struct i915_power_domains *power_domains;
5640         struct i915_power_well *power_well;
5641         bool is_enabled;
5642         int i;
5643
5644         if (dev_priv->pm.suspended)
5645                 return false;
5646
5647         power_domains = &dev_priv->power_domains;
5648
5649         is_enabled = true;
5650
5651         mutex_lock(&power_domains->lock);
5652         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5653                 if (power_well->always_on)
5654                         continue;
5655
5656                 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
5657                         is_enabled = false;
5658                         break;
5659                 }
5660         }
5661         mutex_unlock(&power_domains->lock);
5662
5663         return is_enabled;
5664 }
5665
5666 /*
5667  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5668  * when not needed anymore. We have 4 registers that can request the power well
5669  * to be enabled, and it will only be disabled if none of the registers is
5670  * requesting it to be enabled.
5671  */
5672 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5673 {
5674         struct drm_device *dev = dev_priv->dev;
5675         unsigned long irqflags;
5676
5677         /*
5678          * After we re-enable the power well, if we touch VGA register 0x3d5
5679          * we'll get unclaimed register interrupts. This stops after we write
5680          * anything to the VGA MSR register. The vgacon module uses this
5681          * register all the time, so if we unbind our driver and, as a
5682          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5683          * console_unlock(). So make here we touch the VGA MSR register, making
5684          * sure vgacon can keep working normally without triggering interrupts
5685          * and error messages.
5686          */
5687         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5688         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5689         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5690
5691         if (IS_BROADWELL(dev)) {
5692                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5693                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5694                            dev_priv->de_irq_mask[PIPE_B]);
5695                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5696                            ~dev_priv->de_irq_mask[PIPE_B] |
5697                            GEN8_PIPE_VBLANK);
5698                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5699                            dev_priv->de_irq_mask[PIPE_C]);
5700                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5701                            ~dev_priv->de_irq_mask[PIPE_C] |
5702                            GEN8_PIPE_VBLANK);
5703                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5704                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5705         }
5706 }
5707
5708 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5709                                struct i915_power_well *power_well, bool enable)
5710 {
5711         bool is_enabled, enable_requested;
5712         uint32_t tmp;
5713
5714         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5715         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5716         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5717
5718         if (enable) {
5719                 if (!enable_requested)
5720                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5721                                    HSW_PWR_WELL_ENABLE_REQUEST);
5722
5723                 if (!is_enabled) {
5724                         DRM_DEBUG_KMS("Enabling power well\n");
5725                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5726                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5727                                 DRM_ERROR("Timeout enabling power well\n");
5728                 }
5729
5730                 hsw_power_well_post_enable(dev_priv);
5731         } else {
5732                 if (enable_requested) {
5733                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5734                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5735                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5736                 }
5737         }
5738 }
5739
5740 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5741                                    struct i915_power_well *power_well)
5742 {
5743         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5744
5745         /*
5746          * We're taking over the BIOS, so clear any requests made by it since
5747          * the driver is in charge now.
5748          */
5749         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5750                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5751 }
5752
5753 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5754                                   struct i915_power_well *power_well)
5755 {
5756         hsw_set_power_well(dev_priv, power_well, true);
5757 }
5758
5759 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5760                                    struct i915_power_well *power_well)
5761 {
5762         hsw_set_power_well(dev_priv, power_well, false);
5763 }
5764
5765 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5766                                            struct i915_power_well *power_well)
5767 {
5768 }
5769
5770 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5771                                              struct i915_power_well *power_well)
5772 {
5773         return true;
5774 }
5775
5776 void __vlv_set_power_well(struct drm_i915_private *dev_priv,
5777                           enum punit_power_well power_well_id, bool enable)
5778 {
5779         struct drm_device *dev = dev_priv->dev;
5780         u32 mask;
5781         u32 state;
5782         u32 ctrl;
5783         enum pipe pipe;
5784
5785         if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
5786                 if (enable) {
5787                         /*
5788                          * Enable the CRI clock source so we can get at the
5789                          * display and the reference clock for VGA
5790                          * hotplug / manual detection.
5791                          */
5792                         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
5793                                    DPLL_REFA_CLK_ENABLE_VLV |
5794                                    DPLL_INTEGRATED_CRI_CLK_VLV);
5795                         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
5796                 } else {
5797                         for_each_pipe(pipe)
5798                                 assert_pll_disabled(dev_priv, pipe);
5799                         /* Assert common reset */
5800                         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
5801                                    ~DPIO_CMNRST);
5802                 }
5803         }
5804
5805         mask = PUNIT_PWRGT_MASK(power_well_id);
5806         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5807                          PUNIT_PWRGT_PWR_GATE(power_well_id);
5808
5809         mutex_lock(&dev_priv->rps.hw_lock);
5810
5811 #define COND \
5812         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5813
5814         if (COND)
5815                 goto out;
5816
5817         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5818         ctrl &= ~mask;
5819         ctrl |= state;
5820         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5821
5822         if (wait_for(COND, 100))
5823                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5824                           state,
5825                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5826
5827 #undef COND
5828
5829 out:
5830         mutex_unlock(&dev_priv->rps.hw_lock);
5831
5832         /*
5833          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
5834          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
5835          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
5836          *   b. The other bits such as sfr settings / modesel may all
5837          *      be set to 0.
5838          *
5839          * This should only be done on init and resume from S3 with
5840          * both PLLs disabled, or we risk losing DPIO and PLL
5841          * synchronization.
5842          */
5843         if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable)
5844                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
5845 }
5846
5847 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5848                                struct i915_power_well *power_well, bool enable)
5849 {
5850         enum punit_power_well power_well_id = power_well->data;
5851
5852         __vlv_set_power_well(dev_priv, power_well_id, enable);
5853 }
5854
5855 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5856                                    struct i915_power_well *power_well)
5857 {
5858         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5859 }
5860
5861 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5862                                   struct i915_power_well *power_well)
5863 {
5864         vlv_set_power_well(dev_priv, power_well, true);
5865 }
5866
5867 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5868                                    struct i915_power_well *power_well)
5869 {
5870         vlv_set_power_well(dev_priv, power_well, false);
5871 }
5872
5873 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5874                                    struct i915_power_well *power_well)
5875 {
5876         int power_well_id = power_well->data;
5877         bool enabled = false;
5878         u32 mask;
5879         u32 state;
5880         u32 ctrl;
5881
5882         mask = PUNIT_PWRGT_MASK(power_well_id);
5883         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5884
5885         mutex_lock(&dev_priv->rps.hw_lock);
5886
5887         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5888         /*
5889          * We only ever set the power-on and power-gate states, anything
5890          * else is unexpected.
5891          */
5892         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5893                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5894         if (state == ctrl)
5895                 enabled = true;
5896
5897         /*
5898          * A transient state at this point would mean some unexpected party
5899          * is poking at the power controls too.
5900          */
5901         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5902         WARN_ON(ctrl != state);
5903
5904         mutex_unlock(&dev_priv->rps.hw_lock);
5905
5906         return enabled;
5907 }
5908
5909 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5910                                           struct i915_power_well *power_well)
5911 {
5912         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5913
5914         vlv_set_power_well(dev_priv, power_well, true);
5915
5916         spin_lock_irq(&dev_priv->irq_lock);
5917         valleyview_enable_display_irqs(dev_priv);
5918         spin_unlock_irq(&dev_priv->irq_lock);
5919
5920         /*
5921          * During driver initialization/resume we can avoid restoring the
5922          * part of the HW/SW state that will be inited anyway explicitly.
5923          */
5924         if (dev_priv->power_domains.initializing)
5925                 return;
5926
5927         intel_hpd_init(dev_priv->dev);
5928
5929         i915_redisable_vga_power_on(dev_priv->dev);
5930 }
5931
5932 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5933                                            struct i915_power_well *power_well)
5934 {
5935         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5936
5937         spin_lock_irq(&dev_priv->irq_lock);
5938         valleyview_disable_display_irqs(dev_priv);
5939         spin_unlock_irq(&dev_priv->irq_lock);
5940
5941         vlv_set_power_well(dev_priv, power_well, false);
5942 }
5943
5944 static void check_power_well_state(struct drm_i915_private *dev_priv,
5945                                    struct i915_power_well *power_well)
5946 {
5947         bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5948
5949         if (power_well->always_on || !i915.disable_power_well) {
5950                 if (!enabled)
5951                         goto mismatch;
5952
5953                 return;
5954         }
5955
5956         if (enabled != (power_well->count > 0))
5957                 goto mismatch;
5958
5959         return;
5960
5961 mismatch:
5962         WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5963                   power_well->name, power_well->always_on, enabled,
5964                   power_well->count, i915.disable_power_well);
5965 }
5966
5967 void intel_display_power_get(struct drm_i915_private *dev_priv,
5968                              enum intel_display_power_domain domain)
5969 {
5970         struct i915_power_domains *power_domains;
5971         struct i915_power_well *power_well;
5972         int i;
5973
5974         intel_runtime_pm_get(dev_priv);
5975
5976         power_domains = &dev_priv->power_domains;
5977
5978         mutex_lock(&power_domains->lock);
5979
5980         for_each_power_well(i, power_well, BIT(domain), power_domains) {
5981                 if (!power_well->count++) {
5982                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
5983                         power_well->ops->enable(dev_priv, power_well);
5984                 }
5985
5986                 check_power_well_state(dev_priv, power_well);
5987         }
5988
5989         power_domains->domain_use_count[domain]++;
5990
5991         mutex_unlock(&power_domains->lock);
5992 }
5993
5994 void intel_display_power_put(struct drm_i915_private *dev_priv,
5995                              enum intel_display_power_domain domain)
5996 {
5997         struct i915_power_domains *power_domains;
5998         struct i915_power_well *power_well;
5999         int i;
6000
6001         power_domains = &dev_priv->power_domains;
6002
6003         mutex_lock(&power_domains->lock);
6004
6005         WARN_ON(!power_domains->domain_use_count[domain]);
6006         power_domains->domain_use_count[domain]--;
6007
6008         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6009                 WARN_ON(!power_well->count);
6010
6011                 if (!--power_well->count && i915.disable_power_well) {
6012                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6013                         power_well->ops->disable(dev_priv, power_well);
6014                 }
6015
6016                 check_power_well_state(dev_priv, power_well);
6017         }
6018
6019         mutex_unlock(&power_domains->lock);
6020
6021         intel_runtime_pm_put(dev_priv);
6022 }
6023
6024 static struct i915_power_domains *hsw_pwr;
6025
6026 /* Display audio driver power well request */
6027 void i915_request_power_well(void)
6028 {
6029         struct drm_i915_private *dev_priv;
6030
6031         if (WARN_ON(!hsw_pwr))
6032                 return;
6033
6034         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6035                                 power_domains);
6036         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6037 }
6038 EXPORT_SYMBOL_GPL(i915_request_power_well);
6039
6040 /* Display audio driver power well release */
6041 void i915_release_power_well(void)
6042 {
6043         struct drm_i915_private *dev_priv;
6044
6045         if (WARN_ON(!hsw_pwr))
6046                 return;
6047
6048         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6049                                 power_domains);
6050         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6051 }
6052 EXPORT_SYMBOL_GPL(i915_release_power_well);
6053
6054 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6055
6056 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
6057         BIT(POWER_DOMAIN_PIPE_A) |                      \
6058         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
6059         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
6060         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
6061         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
6062         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
6063         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
6064         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
6065         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
6066         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
6067         BIT(POWER_DOMAIN_PORT_CRT) |                    \
6068         BIT(POWER_DOMAIN_INIT))
6069 #define HSW_DISPLAY_POWER_DOMAINS (                             \
6070         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
6071         BIT(POWER_DOMAIN_INIT))
6072
6073 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
6074         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
6075         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6076 #define BDW_DISPLAY_POWER_DOMAINS (                             \
6077         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
6078         BIT(POWER_DOMAIN_INIT))
6079
6080 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
6081 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
6082
6083 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
6084         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
6085         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6086         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
6087         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6088         BIT(POWER_DOMAIN_PORT_CRT) |            \
6089         BIT(POWER_DOMAIN_INIT))
6090
6091 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
6092         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
6093         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6094         BIT(POWER_DOMAIN_INIT))
6095
6096 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
6097         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6098         BIT(POWER_DOMAIN_INIT))
6099
6100 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
6101         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
6102         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6103         BIT(POWER_DOMAIN_INIT))
6104
6105 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
6106         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6107         BIT(POWER_DOMAIN_INIT))
6108
6109 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6110         .sync_hw = i9xx_always_on_power_well_noop,
6111         .enable = i9xx_always_on_power_well_noop,
6112         .disable = i9xx_always_on_power_well_noop,
6113         .is_enabled = i9xx_always_on_power_well_enabled,
6114 };
6115
6116 static struct i915_power_well i9xx_always_on_power_well[] = {
6117         {
6118                 .name = "always-on",
6119                 .always_on = 1,
6120                 .domains = POWER_DOMAIN_MASK,
6121                 .ops = &i9xx_always_on_power_well_ops,
6122         },
6123 };
6124
6125 static const struct i915_power_well_ops hsw_power_well_ops = {
6126         .sync_hw = hsw_power_well_sync_hw,
6127         .enable = hsw_power_well_enable,
6128         .disable = hsw_power_well_disable,
6129         .is_enabled = hsw_power_well_enabled,
6130 };
6131
6132 static struct i915_power_well hsw_power_wells[] = {
6133         {
6134                 .name = "always-on",
6135                 .always_on = 1,
6136                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6137                 .ops = &i9xx_always_on_power_well_ops,
6138         },
6139         {
6140                 .name = "display",
6141                 .domains = HSW_DISPLAY_POWER_DOMAINS,
6142                 .ops = &hsw_power_well_ops,
6143         },
6144 };
6145
6146 static struct i915_power_well bdw_power_wells[] = {
6147         {
6148                 .name = "always-on",
6149                 .always_on = 1,
6150                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6151                 .ops = &i9xx_always_on_power_well_ops,
6152         },
6153         {
6154                 .name = "display",
6155                 .domains = BDW_DISPLAY_POWER_DOMAINS,
6156                 .ops = &hsw_power_well_ops,
6157         },
6158 };
6159
6160 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6161         .sync_hw = vlv_power_well_sync_hw,
6162         .enable = vlv_display_power_well_enable,
6163         .disable = vlv_display_power_well_disable,
6164         .is_enabled = vlv_power_well_enabled,
6165 };
6166
6167 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6168         .sync_hw = vlv_power_well_sync_hw,
6169         .enable = vlv_power_well_enable,
6170         .disable = vlv_power_well_disable,
6171         .is_enabled = vlv_power_well_enabled,
6172 };
6173
6174 static struct i915_power_well vlv_power_wells[] = {
6175         {
6176                 .name = "always-on",
6177                 .always_on = 1,
6178                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6179                 .ops = &i9xx_always_on_power_well_ops,
6180         },
6181         {
6182                 .name = "display",
6183                 .domains = VLV_DISPLAY_POWER_DOMAINS,
6184                 .data = PUNIT_POWER_WELL_DISP2D,
6185                 .ops = &vlv_display_power_well_ops,
6186         },
6187         {
6188                 .name = "dpio-tx-b-01",
6189                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6190                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6191                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6192                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6193                 .ops = &vlv_dpio_power_well_ops,
6194                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6195         },
6196         {
6197                 .name = "dpio-tx-b-23",
6198                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6199                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6200                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6201                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6202                 .ops = &vlv_dpio_power_well_ops,
6203                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6204         },
6205         {
6206                 .name = "dpio-tx-c-01",
6207                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6208                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6209                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6210                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6211                 .ops = &vlv_dpio_power_well_ops,
6212                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6213         },
6214         {
6215                 .name = "dpio-tx-c-23",
6216                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6217                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6218                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6219                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6220                 .ops = &vlv_dpio_power_well_ops,
6221                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6222         },
6223         {
6224                 .name = "dpio-common",
6225                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6226                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6227                 .ops = &vlv_dpio_power_well_ops,
6228         },
6229 };
6230
6231 #define set_power_wells(power_domains, __power_wells) ({                \
6232         (power_domains)->power_wells = (__power_wells);                 \
6233         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
6234 })
6235
6236 int intel_power_domains_init(struct drm_i915_private *dev_priv)
6237 {
6238         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6239
6240         mutex_init(&power_domains->lock);
6241
6242         /*
6243          * The enabling order will be from lower to higher indexed wells,
6244          * the disabling order is reversed.
6245          */
6246         if (IS_HASWELL(dev_priv->dev)) {
6247                 set_power_wells(power_domains, hsw_power_wells);
6248                 hsw_pwr = power_domains;
6249         } else if (IS_BROADWELL(dev_priv->dev)) {
6250                 set_power_wells(power_domains, bdw_power_wells);
6251                 hsw_pwr = power_domains;
6252         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6253                 set_power_wells(power_domains, vlv_power_wells);
6254         } else {
6255                 set_power_wells(power_domains, i9xx_always_on_power_well);
6256         }
6257
6258         return 0;
6259 }
6260
6261 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
6262 {
6263         hsw_pwr = NULL;
6264 }
6265
6266 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
6267 {
6268         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6269         struct i915_power_well *power_well;
6270         int i;
6271
6272         mutex_lock(&power_domains->lock);
6273         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
6274                 power_well->ops->sync_hw(dev_priv, power_well);
6275         mutex_unlock(&power_domains->lock);
6276 }
6277
6278 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
6279 {
6280         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6281
6282         power_domains->initializing = true;
6283         /* For now, we need the power well to be always enabled. */
6284         intel_display_set_init_power(dev_priv, true);
6285         intel_power_domains_resume(dev_priv);
6286         power_domains->initializing = false;
6287 }
6288
6289 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6290 {
6291         intel_runtime_pm_get(dev_priv);
6292 }
6293
6294 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6295 {
6296         intel_runtime_pm_put(dev_priv);
6297 }
6298
6299 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6300 {
6301         struct drm_device *dev = dev_priv->dev;
6302         struct device *device = &dev->pdev->dev;
6303
6304         if (!HAS_RUNTIME_PM(dev))
6305                 return;
6306
6307         pm_runtime_get_sync(device);
6308         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6309 }
6310
6311 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6312 {
6313         struct drm_device *dev = dev_priv->dev;
6314         struct device *device = &dev->pdev->dev;
6315
6316         if (!HAS_RUNTIME_PM(dev))
6317                 return;
6318
6319         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6320         pm_runtime_get_noresume(device);
6321 }
6322
6323 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6324 {
6325         struct drm_device *dev = dev_priv->dev;
6326         struct device *device = &dev->pdev->dev;
6327
6328         if (!HAS_RUNTIME_PM(dev))
6329                 return;
6330
6331         pm_runtime_mark_last_busy(device);
6332         pm_runtime_put_autosuspend(device);
6333 }
6334
6335 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6336 {
6337         struct drm_device *dev = dev_priv->dev;
6338         struct device *device = &dev->pdev->dev;
6339
6340         if (!HAS_RUNTIME_PM(dev))
6341                 return;
6342
6343         pm_runtime_set_active(device);
6344
6345         /*
6346          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6347          * requirement.
6348          */
6349         if (!intel_enable_rc6(dev)) {
6350                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6351                 return;
6352         }
6353
6354         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6355         pm_runtime_mark_last_busy(device);
6356         pm_runtime_use_autosuspend(device);
6357
6358         pm_runtime_put_autosuspend(device);
6359 }
6360
6361 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6362 {
6363         struct drm_device *dev = dev_priv->dev;
6364         struct device *device = &dev->pdev->dev;
6365
6366         if (!HAS_RUNTIME_PM(dev))
6367                 return;
6368
6369         if (!intel_enable_rc6(dev))
6370                 return;
6371
6372         /* Make sure we're not suspended first. */
6373         pm_runtime_get_sync(device);
6374         pm_runtime_disable(device);
6375 }
6376
6377 /* Set up chip specific power management-related functions */
6378 void intel_init_pm(struct drm_device *dev)
6379 {
6380         struct drm_i915_private *dev_priv = dev->dev_private;
6381
6382         if (HAS_FBC(dev)) {
6383                 if (INTEL_INFO(dev)->gen >= 7) {
6384                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6385                         dev_priv->display.enable_fbc = gen7_enable_fbc;
6386                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6387                 } else if (INTEL_INFO(dev)->gen >= 5) {
6388                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6389                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6390                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6391                 } else if (IS_GM45(dev)) {
6392                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6393                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6394                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6395                 } else {
6396                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6397                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6398                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6399
6400                         /* This value was pulled out of someone's hat */
6401                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6402                 }
6403         }
6404
6405         /* For cxsr */
6406         if (IS_PINEVIEW(dev))
6407                 i915_pineview_get_mem_freq(dev);
6408         else if (IS_GEN5(dev))
6409                 i915_ironlake_get_mem_freq(dev);
6410
6411         /* For FIFO watermark updates */
6412         if (HAS_PCH_SPLIT(dev)) {
6413                 ilk_setup_wm_latency(dev);
6414
6415                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6416                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6417                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6418                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6419                         dev_priv->display.update_wm = ilk_update_wm;
6420                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6421                 } else {
6422                         DRM_DEBUG_KMS("Failed to read display plane latency. "
6423                                       "Disable CxSR\n");
6424                 }
6425
6426                 if (IS_GEN5(dev))
6427                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6428                 else if (IS_GEN6(dev))
6429                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6430                 else if (IS_IVYBRIDGE(dev))
6431                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6432                 else if (IS_HASWELL(dev))
6433                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6434                 else if (INTEL_INFO(dev)->gen == 8)
6435                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6436         } else if (IS_CHERRYVIEW(dev)) {
6437                 dev_priv->display.update_wm = valleyview_update_wm;
6438                 dev_priv->display.init_clock_gating =
6439                         cherryview_init_clock_gating;
6440         } else if (IS_VALLEYVIEW(dev)) {
6441                 dev_priv->display.update_wm = valleyview_update_wm;
6442                 dev_priv->display.init_clock_gating =
6443                         valleyview_init_clock_gating;
6444         } else if (IS_PINEVIEW(dev)) {
6445                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6446                                             dev_priv->is_ddr3,
6447                                             dev_priv->fsb_freq,
6448                                             dev_priv->mem_freq)) {
6449                         DRM_INFO("failed to find known CxSR latency "
6450                                  "(found ddr%s fsb freq %d, mem freq %d), "
6451                                  "disabling CxSR\n",
6452                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6453                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6454                         /* Disable CxSR and never update its watermark again */
6455                         pineview_disable_cxsr(dev);
6456                         dev_priv->display.update_wm = NULL;
6457                 } else
6458                         dev_priv->display.update_wm = pineview_update_wm;
6459                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6460         } else if (IS_G4X(dev)) {
6461                 dev_priv->display.update_wm = g4x_update_wm;
6462                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6463         } else if (IS_GEN4(dev)) {
6464                 dev_priv->display.update_wm = i965_update_wm;
6465                 if (IS_CRESTLINE(dev))
6466                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6467                 else if (IS_BROADWATER(dev))
6468                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6469         } else if (IS_GEN3(dev)) {
6470                 dev_priv->display.update_wm = i9xx_update_wm;
6471                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6472                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6473         } else if (IS_GEN2(dev)) {
6474                 if (INTEL_INFO(dev)->num_pipes == 1) {
6475                         dev_priv->display.update_wm = i845_update_wm;
6476                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6477                 } else {
6478                         dev_priv->display.update_wm = i9xx_update_wm;
6479                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6480                 }
6481
6482                 if (IS_I85X(dev) || IS_I865G(dev))
6483                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6484                 else
6485                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
6486         } else {
6487                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6488         }
6489 }
6490
6491 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6492 {
6493         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6494
6495         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6496                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6497                 return -EAGAIN;
6498         }
6499
6500         I915_WRITE(GEN6_PCODE_DATA, *val);
6501         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6502
6503         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6504                      500)) {
6505                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6506                 return -ETIMEDOUT;
6507         }
6508
6509         *val = I915_READ(GEN6_PCODE_DATA);
6510         I915_WRITE(GEN6_PCODE_DATA, 0);
6511
6512         return 0;
6513 }
6514
6515 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6516 {
6517         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6518
6519         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6520                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6521                 return -EAGAIN;
6522         }
6523
6524         I915_WRITE(GEN6_PCODE_DATA, val);
6525         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6526
6527         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6528                      500)) {
6529                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6530                 return -ETIMEDOUT;
6531         }
6532
6533         I915_WRITE(GEN6_PCODE_DATA, 0);
6534
6535         return 0;
6536 }
6537
6538 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6539 {
6540         int div;
6541
6542         /* 4 x czclk */
6543         switch (dev_priv->mem_freq) {
6544         case 800:
6545                 div = 10;
6546                 break;
6547         case 1066:
6548                 div = 12;
6549                 break;
6550         case 1333:
6551                 div = 16;
6552                 break;
6553         default:
6554                 return -1;
6555         }
6556
6557         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6558 }
6559
6560 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6561 {
6562         int mul;
6563
6564         /* 4 x czclk */
6565         switch (dev_priv->mem_freq) {
6566         case 800:
6567                 mul = 10;
6568                 break;
6569         case 1066:
6570                 mul = 12;
6571                 break;
6572         case 1333:
6573                 mul = 16;
6574                 break;
6575         default:
6576                 return -1;
6577         }
6578
6579         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6580 }
6581
6582 void intel_pm_setup(struct drm_device *dev)
6583 {
6584         struct drm_i915_private *dev_priv = dev->dev_private;
6585
6586         mutex_init(&dev_priv->rps.hw_lock);
6587
6588         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6589                           intel_gen6_powersave_work);
6590
6591         dev_priv->pm.suspended = false;
6592         dev_priv->pm.irqs_disabled = false;
6593 }