drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * DOC: RC6
  36  *
  37  * RC6 is a special power stage which allows the GPU to enter an very
  38  * low-voltage mode when idle, using down to 0V while at this stage.  This
  39  * stage is entered automatically when the GPU is idle when RC6 support is
  40  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  41  *
  42  * There are different RC6 modes available in Intel GPU, which differentiate
  43  * among each other with the latency required to enter and leave RC6 and
  44  * voltage consumed by the GPU in different states.
  45  *
  46  * The combination of the following flags define which states GPU is allowed
  47  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  48  * RC6pp is deepest RC6. Their support by hardware varies according to the
  49  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  50  * which brings the most power savings; deeper states save more power, but
  51  * require higher latency to switch to and wake up.
  52  */
  53 #define INTEL_RC6_ENABLE                        (1<<0)
  54 #define INTEL_RC6p_ENABLE                       (1<<1)
  55 #define INTEL_RC6pp_ENABLE                      (1<<2)
  56
  57 static void bxt_init_clock_gating(struct drm_device *dev)
  58 {
  59         struct drm_i915_private *dev_priv = dev->dev_private;
  60
  61         /* WaDisableSDEUnitClockGating:bxt */
  62         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  63                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  64
  65         /*
  66          * FIXME:
  67          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  68          */
  69         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  70                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  71
  72         /*
  73          * Wa: Backlight PWM may stop in the asserted state, causing backlight
  74          * to stay fully on.
  75          */
  76         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
  77                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
  78                            PWM1_GATING_DIS | PWM2_GATING_DIS);
  79 }
  80
  81 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84         u32 tmp;
  85
  86         tmp = I915_READ(CLKCFG);
  87
  88         switch (tmp & CLKCFG_FSB_MASK) {
  89         case CLKCFG_FSB_533:
  90                 dev_priv->fsb_freq = 533; /* 133*4 */
  91                 break;
  92         case CLKCFG_FSB_800:
  93                 dev_priv->fsb_freq = 800; /* 200*4 */
  94                 break;
  95         case CLKCFG_FSB_667:
  96                 dev_priv->fsb_freq =  667; /* 167*4 */
  97                 break;
  98         case CLKCFG_FSB_400:
  99                 dev_priv->fsb_freq = 400; /* 100*4 */
 100                 break;
 101         }
 102
 103         switch (tmp & CLKCFG_MEM_MASK) {
 104         case CLKCFG_MEM_533:
 105                 dev_priv->mem_freq = 533;
 106                 break;
 107         case CLKCFG_MEM_667:
 108                 dev_priv->mem_freq = 667;
 109                 break;
 110         case CLKCFG_MEM_800:
 111                 dev_priv->mem_freq = 800;
 112                 break;
 113         }
 114
 115         /* detect pineview DDR3 setting */
 116         tmp = I915_READ(CSHRDDR3CTL);
 117         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 118 }
 119
 120 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         u16 ddrpll, csipll;
 124
 125         ddrpll = I915_READ16(DDRMPLL1);
 126         csipll = I915_READ16(CSIPLL0);
 127
 128         switch (ddrpll & 0xff) {
 129         case 0xc:
 130                 dev_priv->mem_freq = 800;
 131                 break;
 132         case 0x10:
 133                 dev_priv->mem_freq = 1066;
 134                 break;
 135         case 0x14:
 136                 dev_priv->mem_freq = 1333;
 137                 break;
 138         case 0x18:
 139                 dev_priv->mem_freq = 1600;
 140                 break;
 141         default:
 142                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 143                                  ddrpll & 0xff);
 144                 dev_priv->mem_freq = 0;
 145                 break;
 146         }
 147
 148         dev_priv->ips.r_t = dev_priv->mem_freq;
 149
 150         switch (csipll & 0x3ff) {
 151         case 0x00c:
 152                 dev_priv->fsb_freq = 3200;
 153                 break;
 154         case 0x00e:
 155                 dev_priv->fsb_freq = 3733;
 156                 break;
 157         case 0x010:
 158                 dev_priv->fsb_freq = 4266;
 159                 break;
 160         case 0x012:
 161                 dev_priv->fsb_freq = 4800;
 162                 break;
 163         case 0x014:
 164                 dev_priv->fsb_freq = 5333;
 165                 break;
 166         case 0x016:
 167                 dev_priv->fsb_freq = 5866;
 168                 break;
 169         case 0x018:
 170                 dev_priv->fsb_freq = 6400;
 171                 break;
 172         default:
 173                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 174                                  csipll & 0x3ff);
 175                 dev_priv->fsb_freq = 0;
 176                 break;
 177         }
 178
 179         if (dev_priv->fsb_freq == 3200) {
 180                 dev_priv->ips.c_m = 0;
 181         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 182                 dev_priv->ips.c_m = 1;
 183         } else {
 184                 dev_priv->ips.c_m = 2;
 185         }
 186 }
 187
 188 static const struct cxsr_latency cxsr_latency_table[] = {
 189         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 190         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 191         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 192         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 193         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 194
 195         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 196         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 197         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 198         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 199         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 200
 201         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 202         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 203         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 204         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 205         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 206
 207         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 208         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 209         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 210         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 211         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 212
 213         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 214         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 215         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 216         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 217         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 218
 219         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 220         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 221         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 222         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 223         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 224 };
 225
 226 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 227                                                          int is_ddr3,
 228                                                          int fsb,
 229                                                          int mem)
 230 {
 231         const struct cxsr_latency *latency;
 232         int i;
 233
 234         if (fsb == 0 || mem == 0)
 235                 return NULL;
 236
 237         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 238                 latency = &cxsr_latency_table[i];
 239                 if (is_desktop == latency->is_desktop &&
 240                     is_ddr3 == latency->is_ddr3 &&
 241                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 242                         return latency;
 243         }
 244
 245         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 246
 247         return NULL;
 248 }
 249
 250 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 251 {
 252         u32 val;
 253
 254         mutex_lock(&dev_priv->rps.hw_lock);
 255
 256         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 257         if (enable)
 258                 val &= ~FORCE_DDR_HIGH_FREQ;
 259         else
 260                 val |= FORCE_DDR_HIGH_FREQ;
 261         val &= ~FORCE_DDR_LOW_FREQ;
 262         val |= FORCE_DDR_FREQ_REQ_ACK;
 263         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 264
 265         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 266                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 267                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 268
 269         mutex_unlock(&dev_priv->rps.hw_lock);
 270 }
 271
 272 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 273 {
 274         u32 val;
 275
 276         mutex_lock(&dev_priv->rps.hw_lock);
 277
 278         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 279         if (enable)
 280                 val |= DSP_MAXFIFO_PM5_ENABLE;
 281         else
 282                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 283         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 284
 285         mutex_unlock(&dev_priv->rps.hw_lock);
 286 }
 287
 288 #define FW_WM(value, plane) \
 289         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 290
 291 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 292 {
 293         struct drm_device *dev = dev_priv->dev;
 294         u32 val;
 295
 296         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 297                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 298                 POSTING_READ(FW_BLC_SELF_VLV);
 299                 dev_priv->wm.vlv.cxsr = enable;
 300         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 301                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 302                 POSTING_READ(FW_BLC_SELF);
 303         } else if (IS_PINEVIEW(dev)) {
 304                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 305                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 306                 I915_WRITE(DSPFW3, val);
 307                 POSTING_READ(DSPFW3);
 308         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 309                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 310                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 311                 I915_WRITE(FW_BLC_SELF, val);
 312                 POSTING_READ(FW_BLC_SELF);
 313         } else if (IS_I915GM(dev)) {
 314                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 315                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 316                 I915_WRITE(INSTPM, val);
 317                 POSTING_READ(INSTPM);
 318         } else {
 319                 return;
 320         }
 321
 322         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 323                       enable ? "enabled" : "disabled");
 324 }
 325
 326
 327 /*
 328  * Latency for FIFO fetches is dependent on several factors:
 329  *   - memory configuration (speed, channels)
 330  *   - chipset
 331  *   - current MCH state
 332  * It can be fairly high in some situations, so here we assume a fairly
 333  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 334  * set this value too high, the FIFO will fetch frequently to stay full)
 335  * and power consumption (set it too low to save power and we might see
 336  * FIFO underruns and display "flicker").
 337  *
 338  * A value of 5us seems to be a good balance; safe for very low end
 339  * platforms but not overly aggressive on lower latency configs.
 340  */
 341 static const int pessimal_latency_ns = 5000;
 342
 343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 344         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 345
 346 static int vlv_get_fifo_size(struct drm_device *dev,
 347                               enum pipe pipe, int plane)
 348 {
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         int sprite0_start, sprite1_start, size;
 351
 352         switch (pipe) {
 353                 uint32_t dsparb, dsparb2, dsparb3;
 354         case PIPE_A:
 355                 dsparb = I915_READ(DSPARB);
 356                 dsparb2 = I915_READ(DSPARB2);
 357                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 358                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 359                 break;
 360         case PIPE_B:
 361                 dsparb = I915_READ(DSPARB);
 362                 dsparb2 = I915_READ(DSPARB2);
 363                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 364                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 365                 break;
 366         case PIPE_C:
 367                 dsparb2 = I915_READ(DSPARB2);
 368                 dsparb3 = I915_READ(DSPARB3);
 369                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 370                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 371                 break;
 372         default:
 373                 return 0;
 374         }
 375
 376         switch (plane) {
 377         case 0:
 378                 size = sprite0_start;
 379                 break;
 380         case 1:
 381                 size = sprite1_start - sprite0_start;
 382                 break;
 383         case 2:
 384                 size = 512 - 1 - sprite1_start;
 385                 break;
 386         default:
 387                 return 0;
 388         }
 389
 390         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 391                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 392                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 393                       size);
 394
 395         return size;
 396 }
 397
 398 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 399 {
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         uint32_t dsparb = I915_READ(DSPARB);
 402         int size;
 403
 404         size = dsparb & 0x7f;
 405         if (plane)
 406                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 407
 408         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 409                       plane ? "B" : "A", size);
 410
 411         return size;
 412 }
 413
 414 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         uint32_t dsparb = I915_READ(DSPARB);
 418         int size;
 419
 420         size = dsparb & 0x1ff;
 421         if (plane)
 422                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 423         size >>= 1; /* Convert to cachelines */
 424
 425         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 426                       plane ? "B" : "A", size);
 427
 428         return size;
 429 }
 430
 431 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 432 {
 433         struct drm_i915_private *dev_priv = dev->dev_private;
 434         uint32_t dsparb = I915_READ(DSPARB);
 435         int size;
 436
 437         size = dsparb & 0x7f;
 438         size >>= 2; /* Convert to cachelines */
 439
 440         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 441                       plane ? "B" : "A",
 442                       size);
 443
 444         return size;
 445 }
 446
 447 /* Pineview has different values for various configs */
 448 static const struct intel_watermark_params pineview_display_wm = {
 449         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 450         .max_wm = PINEVIEW_MAX_WM,
 451         .default_wm = PINEVIEW_DFT_WM,
 452         .guard_size = PINEVIEW_GUARD_WM,
 453         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 454 };
 455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 456         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 457         .max_wm = PINEVIEW_MAX_WM,
 458         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 459         .guard_size = PINEVIEW_GUARD_WM,
 460         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 461 };
 462 static const struct intel_watermark_params pineview_cursor_wm = {
 463         .fifo_size = PINEVIEW_CURSOR_FIFO,
 464         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 465         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 466         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 467         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 468 };
 469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 470         .fifo_size = PINEVIEW_CURSOR_FIFO,
 471         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 472         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 473         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 474         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 475 };
 476 static const struct intel_watermark_params g4x_wm_info = {
 477         .fifo_size = G4X_FIFO_SIZE,
 478         .max_wm = G4X_MAX_WM,
 479         .default_wm = G4X_MAX_WM,
 480         .guard_size = 2,
 481         .cacheline_size = G4X_FIFO_LINE_SIZE,
 482 };
 483 static const struct intel_watermark_params g4x_cursor_wm_info = {
 484         .fifo_size = I965_CURSOR_FIFO,
 485         .max_wm = I965_CURSOR_MAX_WM,
 486         .default_wm = I965_CURSOR_DFT_WM,
 487         .guard_size = 2,
 488         .cacheline_size = G4X_FIFO_LINE_SIZE,
 489 };
 490 static const struct intel_watermark_params i965_cursor_wm_info = {
 491         .fifo_size = I965_CURSOR_FIFO,
 492         .max_wm = I965_CURSOR_MAX_WM,
 493         .default_wm = I965_CURSOR_DFT_WM,
 494         .guard_size = 2,
 495         .cacheline_size = I915_FIFO_LINE_SIZE,
 496 };
 497 static const struct intel_watermark_params i945_wm_info = {
 498         .fifo_size = I945_FIFO_SIZE,
 499         .max_wm = I915_MAX_WM,
 500         .default_wm = 1,
 501         .guard_size = 2,
 502         .cacheline_size = I915_FIFO_LINE_SIZE,
 503 };
 504 static const struct intel_watermark_params i915_wm_info = {
 505         .fifo_size = I915_FIFO_SIZE,
 506         .max_wm = I915_MAX_WM,
 507         .default_wm = 1,
 508         .guard_size = 2,
 509         .cacheline_size = I915_FIFO_LINE_SIZE,
 510 };
 511 static const struct intel_watermark_params i830_a_wm_info = {
 512         .fifo_size = I855GM_FIFO_SIZE,
 513         .max_wm = I915_MAX_WM,
 514         .default_wm = 1,
 515         .guard_size = 2,
 516         .cacheline_size = I830_FIFO_LINE_SIZE,
 517 };
 518 static const struct intel_watermark_params i830_bc_wm_info = {
 519         .fifo_size = I855GM_FIFO_SIZE,
 520         .max_wm = I915_MAX_WM/2,
 521         .default_wm = 1,
 522         .guard_size = 2,
 523         .cacheline_size = I830_FIFO_LINE_SIZE,
 524 };
 525 static const struct intel_watermark_params i845_wm_info = {
 526         .fifo_size = I830_FIFO_SIZE,
 527         .max_wm = I915_MAX_WM,
 528         .default_wm = 1,
 529         .guard_size = 2,
 530         .cacheline_size = I830_FIFO_LINE_SIZE,
 531 };
 532
 533 /**
 534  * intel_calculate_wm - calculate watermark level
 535  * @clock_in_khz: pixel clock
 536  * @wm: chip FIFO params
 537  * @cpp: bytes per pixel
 538  * @latency_ns: memory latency for the platform
 539  *
 540  * Calculate the watermark level (the level at which the display plane will
 541  * start fetching from memory again).  Each chip has a different display
 542  * FIFO size and allocation, so the caller needs to figure that out and pass
 543  * in the correct intel_watermark_params structure.
 544  *
 545  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 546  * on the pixel size.  When it reaches the watermark level, it'll start
 547  * fetching FIFO line sized based chunks from memory until the FIFO fills
 548  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 549  * will occur, and a display engine hang could result.
 550  */
 551 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 552                                         const struct intel_watermark_params *wm,
 553                                         int fifo_size, int cpp,
 554                                         unsigned long latency_ns)
 555 {
 556         long entries_required, wm_size;
 557
 558         /*
 559          * Note: we need to make sure we don't overflow for various clock &
 560          * latency values.
 561          * clocks go from a few thousand to several hundred thousand.
 562          * latency is usually a few thousand
 563          */
 564         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 565                 1000;
 566         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 567
 568         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 569
 570         wm_size = fifo_size - (entries_required + wm->guard_size);
 571
 572         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 573
 574         /* Don't promote wm_size to unsigned... */
 575         if (wm_size > (long)wm->max_wm)
 576                 wm_size = wm->max_wm;
 577         if (wm_size <= 0)
 578                 wm_size = wm->default_wm;
 579
 580         /*
 581          * Bspec seems to indicate that the value shouldn't be lower than
 582          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 583          * Lets go for 8 which is the burst size since certain platforms
 584          * already use a hardcoded 8 (which is what the spec says should be
 585          * done).
 586          */
 587         if (wm_size <= 8)
 588                 wm_size = 8;
 589
 590         return wm_size;
 591 }
 592
 593 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 594 {
 595         struct drm_crtc *crtc, *enabled = NULL;
 596
 597         for_each_crtc(dev, crtc) {
 598                 if (intel_crtc_active(crtc)) {
 599                         if (enabled)
 600                                 return NULL;
 601                         enabled = crtc;
 602                 }
 603         }
 604
 605         return enabled;
 606 }
 607
 608 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 609 {
 610         struct drm_device *dev = unused_crtc->dev;
 611         struct drm_i915_private *dev_priv = dev->dev_private;
 612         struct drm_crtc *crtc;
 613         const struct cxsr_latency *latency;
 614         u32 reg;
 615         unsigned long wm;
 616
 617         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 618                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 619         if (!latency) {
 620                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 621                 intel_set_memory_cxsr(dev_priv, false);
 622                 return;
 623         }
 624
 625         crtc = single_enabled_crtc(dev);
 626         if (crtc) {
 627                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 628                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 629                 int clock = adjusted_mode->crtc_clock;
 630
 631                 /* Display SR */
 632                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 633                                         pineview_display_wm.fifo_size,
 634                                         cpp, latency->display_sr);
 635                 reg = I915_READ(DSPFW1);
 636                 reg &= ~DSPFW_SR_MASK;
 637                 reg |= FW_WM(wm, SR);
 638                 I915_WRITE(DSPFW1, reg);
 639                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 640
 641                 /* cursor SR */
 642                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 643                                         pineview_display_wm.fifo_size,
 644                                         cpp, latency->cursor_sr);
 645                 reg = I915_READ(DSPFW3);
 646                 reg &= ~DSPFW_CURSOR_SR_MASK;
 647                 reg |= FW_WM(wm, CURSOR_SR);
 648                 I915_WRITE(DSPFW3, reg);
 649
 650                 /* Display HPLL off SR */
 651                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 652                                         pineview_display_hplloff_wm.fifo_size,
 653                                         cpp, latency->display_hpll_disable);
 654                 reg = I915_READ(DSPFW3);
 655                 reg &= ~DSPFW_HPLL_SR_MASK;
 656                 reg |= FW_WM(wm, HPLL_SR);
 657                 I915_WRITE(DSPFW3, reg);
 658
 659                 /* cursor HPLL off SR */
 660                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 661                                         pineview_display_hplloff_wm.fifo_size,
 662                                         cpp, latency->cursor_hpll_disable);
 663                 reg = I915_READ(DSPFW3);
 664                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 665                 reg |= FW_WM(wm, HPLL_CURSOR);
 666                 I915_WRITE(DSPFW3, reg);
 667                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 668
 669                 intel_set_memory_cxsr(dev_priv, true);
 670         } else {
 671                 intel_set_memory_cxsr(dev_priv, false);
 672         }
 673 }
 674
 675 static bool g4x_compute_wm0(struct drm_device *dev,
 676                             int plane,
 677                             const struct intel_watermark_params *display,
 678                             int display_latency_ns,
 679                             const struct intel_watermark_params *cursor,
 680                             int cursor_latency_ns,
 681                             int *plane_wm,
 682                             int *cursor_wm)
 683 {
 684         struct drm_crtc *crtc;
 685         const struct drm_display_mode *adjusted_mode;
 686         int htotal, hdisplay, clock, cpp;
 687         int line_time_us, line_count;
 688         int entries, tlb_miss;
 689
 690         crtc = intel_get_crtc_for_plane(dev, plane);
 691         if (!intel_crtc_active(crtc)) {
 692                 *cursor_wm = cursor->guard_size;
 693                 *plane_wm = display->guard_size;
 694                 return false;
 695         }
 696
 697         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 698         clock = adjusted_mode->crtc_clock;
 699         htotal = adjusted_mode->crtc_htotal;
 700         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 701         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 702
 703         /* Use the small buffer method to calculate plane watermark */
 704         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 705         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 706         if (tlb_miss > 0)
 707                 entries += tlb_miss;
 708         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 709         *plane_wm = entries + display->guard_size;
 710         if (*plane_wm > (int)display->max_wm)
 711                 *plane_wm = display->max_wm;
 712
 713         /* Use the large buffer method to calculate cursor watermark */
 714         line_time_us = max(htotal * 1000 / clock, 1);
 715         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 716         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 717         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 718         if (tlb_miss > 0)
 719                 entries += tlb_miss;
 720         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 721         *cursor_wm = entries + cursor->guard_size;
 722         if (*cursor_wm > (int)cursor->max_wm)
 723                 *cursor_wm = (int)cursor->max_wm;
 724
 725         return true;
 726 }
 727
 728 /*
 729  * Check the wm result.
 730  *
 731  * If any calculated watermark values is larger than the maximum value that
 732  * can be programmed into the associated watermark register, that watermark
 733  * must be disabled.
 734  */
 735 static bool g4x_check_srwm(struct drm_device *dev,
 736                            int display_wm, int cursor_wm,
 737                            const struct intel_watermark_params *display,
 738                            const struct intel_watermark_params *cursor)
 739 {
 740         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 741                       display_wm, cursor_wm);
 742
 743         if (display_wm > display->max_wm) {
 744                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 745                               display_wm, display->max_wm);
 746                 return false;
 747         }
 748
 749         if (cursor_wm > cursor->max_wm) {
 750                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 751                               cursor_wm, cursor->max_wm);
 752                 return false;
 753         }
 754
 755         if (!(display_wm || cursor_wm)) {
 756                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 757                 return false;
 758         }
 759
 760         return true;
 761 }
 762
 763 static bool g4x_compute_srwm(struct drm_device *dev,
 764                              int plane,
 765                              int latency_ns,
 766                              const struct intel_watermark_params *display,
 767                              const struct intel_watermark_params *cursor,
 768                              int *display_wm, int *cursor_wm)
 769 {
 770         struct drm_crtc *crtc;
 771         const struct drm_display_mode *adjusted_mode;
 772         int hdisplay, htotal, cpp, clock;
 773         unsigned long line_time_us;
 774         int line_count, line_size;
 775         int small, large;
 776         int entries;
 777
 778         if (!latency_ns) {
 779                 *display_wm = *cursor_wm = 0;
 780                 return false;
 781         }
 782
 783         crtc = intel_get_crtc_for_plane(dev, plane);
 784         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 785         clock = adjusted_mode->crtc_clock;
 786         htotal = adjusted_mode->crtc_htotal;
 787         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 788         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 789
 790         line_time_us = max(htotal * 1000 / clock, 1);
 791         line_count = (latency_ns / line_time_us + 1000) / 1000;
 792         line_size = hdisplay * cpp;
 793
 794         /* Use the minimum of the small and large buffer method for primary */
 795         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 796         large = line_count * line_size;
 797
 798         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 799         *display_wm = entries + display->guard_size;
 800
 801         /* calculate the self-refresh watermark for display cursor */
 802         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 803         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 804         *cursor_wm = entries + cursor->guard_size;
 805
 806         return g4x_check_srwm(dev,
 807                               *display_wm, *cursor_wm,
 808                               display, cursor);
 809 }
 810
 811 #define FW_WM_VLV(value, plane) \
 812         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 813
 814 static void vlv_write_wm_values(struct intel_crtc *crtc,
 815                                 const struct vlv_wm_values *wm)
 816 {
 817         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 818         enum pipe pipe = crtc->pipe;
 819
 820         I915_WRITE(VLV_DDL(pipe),
 821                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 822                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 823                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 824                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 825
 826         I915_WRITE(DSPFW1,
 827                    FW_WM(wm->sr.plane, SR) |
 828                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 829                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 830                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 831         I915_WRITE(DSPFW2,
 832                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 833                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 834                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 835         I915_WRITE(DSPFW3,
 836                    FW_WM(wm->sr.cursor, CURSOR_SR));
 837
 838         if (IS_CHERRYVIEW(dev_priv)) {
 839                 I915_WRITE(DSPFW7_CHV,
 840                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 841                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 842                 I915_WRITE(DSPFW8_CHV,
 843                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 844                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 845                 I915_WRITE(DSPFW9_CHV,
 846                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 847                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 848                 I915_WRITE(DSPHOWM,
 849                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 850                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 851                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 852                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 853                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 854                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 855                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 856                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 857                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 858                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 859         } else {
 860                 I915_WRITE(DSPFW7,
 861                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 862                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 863                 I915_WRITE(DSPHOWM,
 864                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 865                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 866                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 867                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 868                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 869                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 870                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 871         }
 872
 873         /* zero (unused) WM1 watermarks */
 874         I915_WRITE(DSPFW4, 0);
 875         I915_WRITE(DSPFW5, 0);
 876         I915_WRITE(DSPFW6, 0);
 877         I915_WRITE(DSPHOWM1, 0);
 878
 879         POSTING_READ(DSPFW1);
 880 }
 881
 882 #undef FW_WM_VLV
 883
 884 enum vlv_wm_level {
 885         VLV_WM_LEVEL_PM2,
 886         VLV_WM_LEVEL_PM5,
 887         VLV_WM_LEVEL_DDR_DVFS,
 888 };
 889
 890 /* latency must be in 0.1us units. */
 891 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 892                                    unsigned int pipe_htotal,
 893                                    unsigned int horiz_pixels,
 894                                    unsigned int cpp,
 895                                    unsigned int latency)
 896 {
 897         unsigned int ret;
 898
 899         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 900         ret = (ret + 1) * horiz_pixels * cpp;
 901         ret = DIV_ROUND_UP(ret, 64);
 902
 903         return ret;
 904 }
 905
 906 static void vlv_setup_wm_latency(struct drm_device *dev)
 907 {
 908         struct drm_i915_private *dev_priv = dev->dev_private;
 909
 910         /* all latencies in usec */
 911         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 912
 913         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 914
 915         if (IS_CHERRYVIEW(dev_priv)) {
 916                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 917                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 918
 919                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 920         }
 921 }
 922
 923 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 924                                      struct intel_crtc *crtc,
 925                                      const struct intel_plane_state *state,
 926                                      int level)
 927 {
 928         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 929         int clock, htotal, cpp, width, wm;
 930
 931         if (dev_priv->wm.pri_latency[level] == 0)
 932                 return USHRT_MAX;
 933
 934         if (!state->visible)
 935                 return 0;
 936
 937         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 938         clock = crtc->config->base.adjusted_mode.crtc_clock;
 939         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 940         width = crtc->config->pipe_src_w;
 941         if (WARN_ON(htotal == 0))
 942                 htotal = 1;
 943
 944         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 945                 /*
 946                  * FIXME the formula gives values that are
 947                  * too big for the cursor FIFO, and hence we
 948                  * would never be able to use cursors. For
 949                  * now just hardcode the watermark.
 950                  */
 951                 wm = 63;
 952         } else {
 953                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 954                                     dev_priv->wm.pri_latency[level] * 10);
 955         }
 956
 957         return min_t(int, wm, USHRT_MAX);
 958 }
 959
 960 static void vlv_compute_fifo(struct intel_crtc *crtc)
 961 {
 962         struct drm_device *dev = crtc->base.dev;
 963         struct vlv_wm_state *wm_state = &crtc->wm_state;
 964         struct intel_plane *plane;
 965         unsigned int total_rate = 0;
 966         const int fifo_size = 512 - 1;
 967         int fifo_extra, fifo_left = fifo_size;
 968
 969         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 970                 struct intel_plane_state *state =
 971                         to_intel_plane_state(plane->base.state);
 972
 973                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 974                         continue;
 975
 976                 if (state->visible) {
 977                         wm_state->num_active_planes++;
 978                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 979                 }
 980         }
 981
 982         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 983                 struct intel_plane_state *state =
 984                         to_intel_plane_state(plane->base.state);
 985                 unsigned int rate;
 986
 987                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 988                         plane->wm.fifo_size = 63;
 989                         continue;
 990                 }
 991
 992                 if (!state->visible) {
 993                         plane->wm.fifo_size = 0;
 994                         continue;
 995                 }
 996
 997                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 998                 plane->wm.fifo_size = fifo_size * rate / total_rate;
 999                 fifo_left -= plane->wm.fifo_size;
1000         }
1001
1002         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004         /* spread the remainder evenly */
1005         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006                 int plane_extra;
1007
1008                 if (fifo_left == 0)
1009                         break;
1010
1011                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012                         continue;
1013
1014                 /* give it all to the first plane if none are active */
1015                 if (plane->wm.fifo_size == 0 &&
1016                     wm_state->num_active_planes)
1017                         continue;
1018
1019                 plane_extra = min(fifo_extra, fifo_left);
1020                 plane->wm.fifo_size += plane_extra;
1021                 fifo_left -= plane_extra;
1022         }
1023
1024         WARN_ON(fifo_left != 0);
1025 }
1026
1027 static void vlv_invert_wms(struct intel_crtc *crtc)
1028 {
1029         struct vlv_wm_state *wm_state = &crtc->wm_state;
1030         int level;
1031
1032         for (level = 0; level < wm_state->num_levels; level++) {
1033                 struct drm_device *dev = crtc->base.dev;
1034                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035                 struct intel_plane *plane;
1036
1037                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041                         switch (plane->base.type) {
1042                                 int sprite;
1043                         case DRM_PLANE_TYPE_CURSOR:
1044                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045                                         wm_state->wm[level].cursor;
1046                                 break;
1047                         case DRM_PLANE_TYPE_PRIMARY:
1048                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1049                                         wm_state->wm[level].primary;
1050                                 break;
1051                         case DRM_PLANE_TYPE_OVERLAY:
1052                                 sprite = plane->plane;
1053                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054                                         wm_state->wm[level].sprite[sprite];
1055                                 break;
1056                         }
1057                 }
1058         }
1059 }
1060
1061 static void vlv_compute_wm(struct intel_crtc *crtc)
1062 {
1063         struct drm_device *dev = crtc->base.dev;
1064         struct vlv_wm_state *wm_state = &crtc->wm_state;
1065         struct intel_plane *plane;
1066         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067         int level;
1068
1069         memset(wm_state, 0, sizeof(*wm_state));
1070
1071         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1072         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1073
1074         wm_state->num_active_planes = 0;
1075
1076         vlv_compute_fifo(crtc);
1077
1078         if (wm_state->num_active_planes != 1)
1079                 wm_state->cxsr = false;
1080
1081         if (wm_state->cxsr) {
1082                 for (level = 0; level < wm_state->num_levels; level++) {
1083                         wm_state->sr[level].plane = sr_fifo_size;
1084                         wm_state->sr[level].cursor = 63;
1085                 }
1086         }
1087
1088         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089                 struct intel_plane_state *state =
1090                         to_intel_plane_state(plane->base.state);
1091
1092                 if (!state->visible)
1093                         continue;
1094
1095                 /* normal watermarks */
1096                 for (level = 0; level < wm_state->num_levels; level++) {
1097                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100                         /* hack */
1101                         if (WARN_ON(level == 0 && wm > max_wm))
1102                                 wm = max_wm;
1103
1104                         if (wm > plane->wm.fifo_size)
1105                                 break;
1106
1107                         switch (plane->base.type) {
1108                                 int sprite;
1109                         case DRM_PLANE_TYPE_CURSOR:
1110                                 wm_state->wm[level].cursor = wm;
1111                                 break;
1112                         case DRM_PLANE_TYPE_PRIMARY:
1113                                 wm_state->wm[level].primary = wm;
1114                                 break;
1115                         case DRM_PLANE_TYPE_OVERLAY:
1116                                 sprite = plane->plane;
1117                                 wm_state->wm[level].sprite[sprite] = wm;
1118                                 break;
1119                         }
1120                 }
1121
1122                 wm_state->num_levels = level;
1123
1124                 if (!wm_state->cxsr)
1125                         continue;
1126
1127                 /* maxfifo watermarks */
1128                 switch (plane->base.type) {
1129                         int sprite, level;
1130                 case DRM_PLANE_TYPE_CURSOR:
1131                         for (level = 0; level < wm_state->num_levels; level++)
1132                                 wm_state->sr[level].cursor =
1133                                         wm_state->wm[level].cursor;
1134                         break;
1135                 case DRM_PLANE_TYPE_PRIMARY:
1136                         for (level = 0; level < wm_state->num_levels; level++)
1137                                 wm_state->sr[level].plane =
1138                                         min(wm_state->sr[level].plane,
1139                                             wm_state->wm[level].primary);
1140                         break;
1141                 case DRM_PLANE_TYPE_OVERLAY:
1142                         sprite = plane->plane;
1143                         for (level = 0; level < wm_state->num_levels; level++)
1144                                 wm_state->sr[level].plane =
1145                                         min(wm_state->sr[level].plane,
1146                                             wm_state->wm[level].sprite[sprite]);
1147                         break;
1148                 }
1149         }
1150
1151         /* clear any (partially) filled invalid levels */
1152         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1153                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155         }
1156
1157         vlv_invert_wms(crtc);
1158 }
1159
1160 #define VLV_FIFO(plane, value) \
1161         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164 {
1165         struct drm_device *dev = crtc->base.dev;
1166         struct drm_i915_private *dev_priv = to_i915(dev);
1167         struct intel_plane *plane;
1168         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172                         WARN_ON(plane->wm.fifo_size != 63);
1173                         continue;
1174                 }
1175
1176                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177                         sprite0_start = plane->wm.fifo_size;
1178                 else if (plane->plane == 0)
1179                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1180                 else
1181                         fifo_size = sprite1_start + plane->wm.fifo_size;
1182         }
1183
1184         WARN_ON(fifo_size != 512 - 1);
1185
1186         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187                       pipe_name(crtc->pipe), sprite0_start,
1188                       sprite1_start, fifo_size);
1189
1190         switch (crtc->pipe) {
1191                 uint32_t dsparb, dsparb2, dsparb3;
1192         case PIPE_A:
1193                 dsparb = I915_READ(DSPARB);
1194                 dsparb2 = I915_READ(DSPARB2);
1195
1196                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197                             VLV_FIFO(SPRITEB, 0xff));
1198                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199                            VLV_FIFO(SPRITEB, sprite1_start));
1200
1201                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202                              VLV_FIFO(SPRITEB_HI, 0x1));
1203                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206                 I915_WRITE(DSPARB, dsparb);
1207                 I915_WRITE(DSPARB2, dsparb2);
1208                 break;
1209         case PIPE_B:
1210                 dsparb = I915_READ(DSPARB);
1211                 dsparb2 = I915_READ(DSPARB2);
1212
1213                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214                             VLV_FIFO(SPRITED, 0xff));
1215                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216                            VLV_FIFO(SPRITED, sprite1_start));
1217
1218                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219                              VLV_FIFO(SPRITED_HI, 0xff));
1220                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223                 I915_WRITE(DSPARB, dsparb);
1224                 I915_WRITE(DSPARB2, dsparb2);
1225                 break;
1226         case PIPE_C:
1227                 dsparb3 = I915_READ(DSPARB3);
1228                 dsparb2 = I915_READ(DSPARB2);
1229
1230                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231                              VLV_FIFO(SPRITEF, 0xff));
1232                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233                             VLV_FIFO(SPRITEF, sprite1_start));
1234
1235                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236                              VLV_FIFO(SPRITEF_HI, 0xff));
1237                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240                 I915_WRITE(DSPARB3, dsparb3);
1241                 I915_WRITE(DSPARB2, dsparb2);
1242                 break;
1243         default:
1244                 break;
1245         }
1246 }
1247
1248 #undef VLV_FIFO
1249
1250 static void vlv_merge_wm(struct drm_device *dev,
1251                          struct vlv_wm_values *wm)
1252 {
1253         struct intel_crtc *crtc;
1254         int num_active_crtcs = 0;
1255
1256         wm->level = to_i915(dev)->wm.max_level;
1257         wm->cxsr = true;
1258
1259         for_each_intel_crtc(dev, crtc) {
1260                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262                 if (!crtc->active)
1263                         continue;
1264
1265                 if (!wm_state->cxsr)
1266                         wm->cxsr = false;
1267
1268                 num_active_crtcs++;
1269                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270         }
1271
1272         if (num_active_crtcs != 1)
1273                 wm->cxsr = false;
1274
1275         if (num_active_crtcs > 1)
1276                 wm->level = VLV_WM_LEVEL_PM2;
1277
1278         for_each_intel_crtc(dev, crtc) {
1279                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280                 enum pipe pipe = crtc->pipe;
1281
1282                 if (!crtc->active)
1283                         continue;
1284
1285                 wm->pipe[pipe] = wm_state->wm[wm->level];
1286                 if (wm->cxsr)
1287                         wm->sr = wm_state->sr[wm->level];
1288
1289                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293         }
1294 }
1295
1296 static void vlv_update_wm(struct drm_crtc *crtc)
1297 {
1298         struct drm_device *dev = crtc->dev;
1299         struct drm_i915_private *dev_priv = dev->dev_private;
1300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301         enum pipe pipe = intel_crtc->pipe;
1302         struct vlv_wm_values wm = {};
1303
1304         vlv_compute_wm(intel_crtc);
1305         vlv_merge_wm(dev, &wm);
1306
1307         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308                 /* FIXME should be part of crtc atomic commit */
1309                 vlv_pipe_set_fifo_size(intel_crtc);
1310                 return;
1311         }
1312
1313         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315                 chv_set_memory_dvfs(dev_priv, false);
1316
1317         if (wm.level < VLV_WM_LEVEL_PM5 &&
1318             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319                 chv_set_memory_pm5(dev_priv, false);
1320
1321         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1322                 intel_set_memory_cxsr(dev_priv, false);
1323
1324         /* FIXME should be part of crtc atomic commit */
1325         vlv_pipe_set_fifo_size(intel_crtc);
1326
1327         vlv_write_wm_values(intel_crtc, &wm);
1328
1329         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
1335         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1336                 intel_set_memory_cxsr(dev_priv, true);
1337
1338         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340                 chv_set_memory_pm5(dev_priv, true);
1341
1342         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344                 chv_set_memory_dvfs(dev_priv, true);
1345
1346         dev_priv->wm.vlv = wm;
1347 }
1348
1349 #define single_plane_enabled(mask) is_power_of_2(mask)
1350
1351 static void g4x_update_wm(struct drm_crtc *crtc)
1352 {
1353         struct drm_device *dev = crtc->dev;
1354         static const int sr_latency_ns = 12000;
1355         struct drm_i915_private *dev_priv = dev->dev_private;
1356         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357         int plane_sr, cursor_sr;
1358         unsigned int enabled = 0;
1359         bool cxsr_enabled;
1360
1361         if (g4x_compute_wm0(dev, PIPE_A,
1362                             &g4x_wm_info, pessimal_latency_ns,
1363                             &g4x_cursor_wm_info, pessimal_latency_ns,
1364                             &planea_wm, &cursora_wm))
1365                 enabled |= 1 << PIPE_A;
1366
1367         if (g4x_compute_wm0(dev, PIPE_B,
1368                             &g4x_wm_info, pessimal_latency_ns,
1369                             &g4x_cursor_wm_info, pessimal_latency_ns,
1370                             &planeb_wm, &cursorb_wm))
1371                 enabled |= 1 << PIPE_B;
1372
1373         if (single_plane_enabled(enabled) &&
1374             g4x_compute_srwm(dev, ffs(enabled) - 1,
1375                              sr_latency_ns,
1376                              &g4x_wm_info,
1377                              &g4x_cursor_wm_info,
1378                              &plane_sr, &cursor_sr)) {
1379                 cxsr_enabled = true;
1380         } else {
1381                 cxsr_enabled = false;
1382                 intel_set_memory_cxsr(dev_priv, false);
1383                 plane_sr = cursor_sr = 0;
1384         }
1385
1386         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1388                       planea_wm, cursora_wm,
1389                       planeb_wm, cursorb_wm,
1390                       plane_sr, cursor_sr);
1391
1392         I915_WRITE(DSPFW1,
1393                    FW_WM(plane_sr, SR) |
1394                    FW_WM(cursorb_wm, CURSORB) |
1395                    FW_WM(planeb_wm, PLANEB) |
1396                    FW_WM(planea_wm, PLANEA));
1397         I915_WRITE(DSPFW2,
1398                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1399                    FW_WM(cursora_wm, CURSORA));
1400         /* HPLL off in SR has some issues on G4x... disable it */
1401         I915_WRITE(DSPFW3,
1402                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1403                    FW_WM(cursor_sr, CURSOR_SR));
1404
1405         if (cxsr_enabled)
1406                 intel_set_memory_cxsr(dev_priv, true);
1407 }
1408
1409 static void i965_update_wm(struct drm_crtc *unused_crtc)
1410 {
1411         struct drm_device *dev = unused_crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         struct drm_crtc *crtc;
1414         int srwm = 1;
1415         int cursor_sr = 16;
1416         bool cxsr_enabled;
1417
1418         /* Calc sr entries for one plane configs */
1419         crtc = single_enabled_crtc(dev);
1420         if (crtc) {
1421                 /* self-refresh has much higher latency */
1422                 static const int sr_latency_ns = 12000;
1423                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1424                 int clock = adjusted_mode->crtc_clock;
1425                 int htotal = adjusted_mode->crtc_htotal;
1426                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1427                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1428                 unsigned long line_time_us;
1429                 int entries;
1430
1431                 line_time_us = max(htotal * 1000 / clock, 1);
1432
1433                 /* Use ns/us then divide to preserve precision */
1434                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1435                         cpp * hdisplay;
1436                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437                 srwm = I965_FIFO_SIZE - entries;
1438                 if (srwm < 0)
1439                         srwm = 1;
1440                 srwm &= 0x1ff;
1441                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442                               entries, srwm);
1443
1444                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1445                         cpp * crtc->cursor->state->crtc_w;
1446                 entries = DIV_ROUND_UP(entries,
1447                                           i965_cursor_wm_info.cacheline_size);
1448                 cursor_sr = i965_cursor_wm_info.fifo_size -
1449                         (entries + i965_cursor_wm_info.guard_size);
1450
1451                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452                         cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455                               "cursor %d\n", srwm, cursor_sr);
1456
1457                 cxsr_enabled = true;
1458         } else {
1459                 cxsr_enabled = false;
1460                 /* Turn off self refresh if both pipes are enabled */
1461                 intel_set_memory_cxsr(dev_priv, false);
1462         }
1463
1464         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465                       srwm);
1466
1467         /* 965 has limitations... */
1468         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469                    FW_WM(8, CURSORB) |
1470                    FW_WM(8, PLANEB) |
1471                    FW_WM(8, PLANEA));
1472         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473                    FW_WM(8, PLANEC_OLD));
1474         /* update cursor SR watermark */
1475         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1476
1477         if (cxsr_enabled)
1478                 intel_set_memory_cxsr(dev_priv, true);
1479 }
1480
1481 #undef FW_WM
1482
1483 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1484 {
1485         struct drm_device *dev = unused_crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         const struct intel_watermark_params *wm_info;
1488         uint32_t fwater_lo;
1489         uint32_t fwater_hi;
1490         int cwm, srwm = 1;
1491         int fifo_size;
1492         int planea_wm, planeb_wm;
1493         struct drm_crtc *crtc, *enabled = NULL;
1494
1495         if (IS_I945GM(dev))
1496                 wm_info = &i945_wm_info;
1497         else if (!IS_GEN2(dev))
1498                 wm_info = &i915_wm_info;
1499         else
1500                 wm_info = &i830_a_wm_info;
1501
1502         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503         crtc = intel_get_crtc_for_plane(dev, 0);
1504         if (intel_crtc_active(crtc)) {
1505                 const struct drm_display_mode *adjusted_mode;
1506                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1507                 if (IS_GEN2(dev))
1508                         cpp = 4;
1509
1510                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1511                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1512                                                wm_info, fifo_size, cpp,
1513                                                pessimal_latency_ns);
1514                 enabled = crtc;
1515         } else {
1516                 planea_wm = fifo_size - wm_info->guard_size;
1517                 if (planea_wm > (long)wm_info->max_wm)
1518                         planea_wm = wm_info->max_wm;
1519         }
1520
1521         if (IS_GEN2(dev))
1522                 wm_info = &i830_bc_wm_info;
1523
1524         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525         crtc = intel_get_crtc_for_plane(dev, 1);
1526         if (intel_crtc_active(crtc)) {
1527                 const struct drm_display_mode *adjusted_mode;
1528                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1529                 if (IS_GEN2(dev))
1530                         cpp = 4;
1531
1532                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1533                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1534                                                wm_info, fifo_size, cpp,
1535                                                pessimal_latency_ns);
1536                 if (enabled == NULL)
1537                         enabled = crtc;
1538                 else
1539                         enabled = NULL;
1540         } else {
1541                 planeb_wm = fifo_size - wm_info->guard_size;
1542                 if (planeb_wm > (long)wm_info->max_wm)
1543                         planeb_wm = wm_info->max_wm;
1544         }
1545
1546         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548         if (IS_I915GM(dev) && enabled) {
1549                 struct drm_i915_gem_object *obj;
1550
1551                 obj = intel_fb_obj(enabled->primary->state->fb);
1552
1553                 /* self-refresh seems busted with untiled */
1554                 if (obj->tiling_mode == I915_TILING_NONE)
1555                         enabled = NULL;
1556         }
1557
1558         /*
1559          * Overlay gets an aggressive default since video jitter is bad.
1560          */
1561         cwm = 2;
1562
1563         /* Play safe and disable self-refresh before adjusting watermarks. */
1564         intel_set_memory_cxsr(dev_priv, false);
1565
1566         /* Calc sr entries for one plane configs */
1567         if (HAS_FW_BLC(dev) && enabled) {
1568                 /* self-refresh has much higher latency */
1569                 static const int sr_latency_ns = 6000;
1570                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1571                 int clock = adjusted_mode->crtc_clock;
1572                 int htotal = adjusted_mode->crtc_htotal;
1573                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1574                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1575                 unsigned long line_time_us;
1576                 int entries;
1577
1578                 line_time_us = max(htotal * 1000 / clock, 1);
1579
1580                 /* Use ns/us then divide to preserve precision */
1581                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1582                         cpp * hdisplay;
1583                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585                 srwm = wm_info->fifo_size - entries;
1586                 if (srwm < 0)
1587                         srwm = 1;
1588
1589                 if (IS_I945G(dev) || IS_I945GM(dev))
1590                         I915_WRITE(FW_BLC_SELF,
1591                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592                 else if (IS_I915GM(dev))
1593                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594         }
1595
1596         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597                       planea_wm, planeb_wm, cwm, srwm);
1598
1599         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600         fwater_hi = (cwm & 0x1f);
1601
1602         /* Set request length to 8 cachelines per fetch */
1603         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604         fwater_hi = fwater_hi | (1 << 8);
1605
1606         I915_WRITE(FW_BLC, fwater_lo);
1607         I915_WRITE(FW_BLC2, fwater_hi);
1608
1609         if (enabled)
1610                 intel_set_memory_cxsr(dev_priv, true);
1611 }
1612
1613 static void i845_update_wm(struct drm_crtc *unused_crtc)
1614 {
1615         struct drm_device *dev = unused_crtc->dev;
1616         struct drm_i915_private *dev_priv = dev->dev_private;
1617         struct drm_crtc *crtc;
1618         const struct drm_display_mode *adjusted_mode;
1619         uint32_t fwater_lo;
1620         int planea_wm;
1621
1622         crtc = single_enabled_crtc(dev);
1623         if (crtc == NULL)
1624                 return;
1625
1626         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1627         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1628                                        &i845_wm_info,
1629                                        dev_priv->display.get_fifo_size(dev, 0),
1630                                        4, pessimal_latency_ns);
1631         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632         fwater_lo |= (3<<8) | planea_wm;
1633
1634         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636         I915_WRITE(FW_BLC, fwater_lo);
1637 }
1638
1639 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1640 {
1641         uint32_t pixel_rate;
1642
1643         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1644
1645         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646          * adjust the pixel_rate here. */
1647
1648         if (pipe_config->pch_pfit.enabled) {
1649                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1650                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652                 pipe_w = pipe_config->pipe_src_w;
1653                 pipe_h = pipe_config->pipe_src_h;
1654
1655                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656                 pfit_h = pfit_size & 0xFFFF;
1657                 if (pipe_w < pfit_w)
1658                         pipe_w = pfit_w;
1659                 if (pipe_h < pfit_h)
1660                         pipe_h = pfit_h;
1661
1662                 if (WARN_ON(!pfit_w || !pfit_h))
1663                         return pixel_rate;
1664
1665                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666                                      pfit_w * pfit_h);
1667         }
1668
1669         return pixel_rate;
1670 }
1671
1672 /* latency must be in 0.1us units. */
1673 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1674 {
1675         uint64_t ret;
1676
1677         if (WARN(latency == 0, "Latency value missing\n"))
1678                 return UINT_MAX;
1679
1680         ret = (uint64_t) pixel_rate * cpp * latency;
1681         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683         return ret;
1684 }
1685
1686 /* latency must be in 0.1us units. */
1687 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1688                                uint32_t horiz_pixels, uint8_t cpp,
1689                                uint32_t latency)
1690 {
1691         uint32_t ret;
1692
1693         if (WARN(latency == 0, "Latency value missing\n"))
1694                 return UINT_MAX;
1695         if (WARN_ON(!pipe_htotal))
1696                 return UINT_MAX;
1697
1698         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1699         ret = (ret + 1) * horiz_pixels * cpp;
1700         ret = DIV_ROUND_UP(ret, 64) + 2;
1701         return ret;
1702 }
1703
1704 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1705                            uint8_t cpp)
1706 {
1707         /*
1708          * Neither of these should be possible since this function shouldn't be
1709          * called if the CRTC is off or the plane is invisible.  But let's be
1710          * extra paranoid to avoid a potential divide-by-zero if we screw up
1711          * elsewhere in the driver.
1712          */
1713         if (WARN_ON(!cpp))
1714                 return 0;
1715         if (WARN_ON(!horiz_pixels))
1716                 return 0;
1717
1718         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1719 }
1720
1721 struct ilk_wm_maximums {
1722         uint16_t pri;
1723         uint16_t spr;
1724         uint16_t cur;
1725         uint16_t fbc;
1726 };
1727
1728 /*
1729  * For both WM_PIPE and WM_LP.
1730  * mem_value must be in 0.1us units.
1731  */
1732 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1733                                    const struct intel_plane_state *pstate,
1734                                    uint32_t mem_value,
1735                                    bool is_lp)
1736 {
1737         int cpp = pstate->base.fb ?
1738                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1739         uint32_t method1, method2;
1740
1741         if (!cstate->base.active || !pstate->visible)
1742                 return 0;
1743
1744         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1745
1746         if (!is_lp)
1747                 return method1;
1748
1749         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750                                  cstate->base.adjusted_mode.crtc_htotal,
1751                                  drm_rect_width(&pstate->dst),
1752                                  cpp, mem_value);
1753
1754         return min(method1, method2);
1755 }
1756
1757 /*
1758  * For both WM_PIPE and WM_LP.
1759  * mem_value must be in 0.1us units.
1760  */
1761 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1762                                    const struct intel_plane_state *pstate,
1763                                    uint32_t mem_value)
1764 {
1765         int cpp = pstate->base.fb ?
1766                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1767         uint32_t method1, method2;
1768
1769         if (!cstate->base.active || !pstate->visible)
1770                 return 0;
1771
1772         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1773         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774                                  cstate->base.adjusted_mode.crtc_htotal,
1775                                  drm_rect_width(&pstate->dst),
1776                                  cpp, mem_value);
1777         return min(method1, method2);
1778 }
1779
1780 /*
1781  * For both WM_PIPE and WM_LP.
1782  * mem_value must be in 0.1us units.
1783  */
1784 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1785                                    const struct intel_plane_state *pstate,
1786                                    uint32_t mem_value)
1787 {
1788         /*
1789          * We treat the cursor plane as always-on for the purposes of watermark
1790          * calculation.  Until we have two-stage watermark programming merged,
1791          * this is necessary to avoid flickering.
1792          */
1793         int cpp = 4;
1794         int width = pstate->visible ? pstate->base.crtc_w : 64;
1795
1796         if (!cstate->base.active)
1797                 return 0;
1798
1799         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800                               cstate->base.adjusted_mode.crtc_htotal,
1801                               width, cpp, mem_value);
1802 }
1803
1804 /* Only for WM_LP. */
1805 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1806                                    const struct intel_plane_state *pstate,
1807                                    uint32_t pri_val)
1808 {
1809         int cpp = pstate->base.fb ?
1810                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1811
1812         if (!cstate->base.active || !pstate->visible)
1813                 return 0;
1814
1815         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1816 }
1817
1818 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819 {
1820         if (INTEL_INFO(dev)->gen >= 8)
1821                 return 3072;
1822         else if (INTEL_INFO(dev)->gen >= 7)
1823                 return 768;
1824         else
1825                 return 512;
1826 }
1827
1828 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829                                          int level, bool is_sprite)
1830 {
1831         if (INTEL_INFO(dev)->gen >= 8)
1832                 /* BDW primary/sprite plane watermarks */
1833                 return level == 0 ? 255 : 2047;
1834         else if (INTEL_INFO(dev)->gen >= 7)
1835                 /* IVB/HSW primary/sprite plane watermarks */
1836                 return level == 0 ? 127 : 1023;
1837         else if (!is_sprite)
1838                 /* ILK/SNB primary plane watermarks */
1839                 return level == 0 ? 127 : 511;
1840         else
1841                 /* ILK/SNB sprite plane watermarks */
1842                 return level == 0 ? 63 : 255;
1843 }
1844
1845 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846                                           int level)
1847 {
1848         if (INTEL_INFO(dev)->gen >= 7)
1849                 return level == 0 ? 63 : 255;
1850         else
1851                 return level == 0 ? 31 : 63;
1852 }
1853
1854 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855 {
1856         if (INTEL_INFO(dev)->gen >= 8)
1857                 return 31;
1858         else
1859                 return 15;
1860 }
1861
1862 /* Calculate the maximum primary/sprite plane watermark */
1863 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864                                      int level,
1865                                      const struct intel_wm_config *config,
1866                                      enum intel_ddb_partitioning ddb_partitioning,
1867                                      bool is_sprite)
1868 {
1869         unsigned int fifo_size = ilk_display_fifo_size(dev);
1870
1871         /* if sprites aren't enabled, sprites get nothing */
1872         if (is_sprite && !config->sprites_enabled)
1873                 return 0;
1874
1875         /* HSW allows LP1+ watermarks even with multiple pipes */
1876         if (level == 0 || config->num_pipes_active > 1) {
1877                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879                 /*
1880                  * For some reason the non self refresh
1881                  * FIFO size is only half of the self
1882                  * refresh FIFO size on ILK/SNB.
1883                  */
1884                 if (INTEL_INFO(dev)->gen <= 6)
1885                         fifo_size /= 2;
1886         }
1887
1888         if (config->sprites_enabled) {
1889                 /* level 0 is always calculated with 1:1 split */
1890                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891                         if (is_sprite)
1892                                 fifo_size *= 5;
1893                         fifo_size /= 6;
1894                 } else {
1895                         fifo_size /= 2;
1896                 }
1897         }
1898
1899         /* clamp to max that the registers can hold */
1900         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1901 }
1902
1903 /* Calculate the maximum cursor plane watermark */
1904 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1905                                       int level,
1906                                       const struct intel_wm_config *config)
1907 {
1908         /* HSW LP1+ watermarks w/ multiple pipes */
1909         if (level > 0 && config->num_pipes_active > 1)
1910                 return 64;
1911
1912         /* otherwise just report max that registers can hold */
1913         return ilk_cursor_wm_reg_max(dev, level);
1914 }
1915
1916 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1917                                     int level,
1918                                     const struct intel_wm_config *config,
1919                                     enum intel_ddb_partitioning ddb_partitioning,
1920                                     struct ilk_wm_maximums *max)
1921 {
1922         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924         max->cur = ilk_cursor_wm_max(dev, level, config);
1925         max->fbc = ilk_fbc_wm_reg_max(dev);
1926 }
1927
1928 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929                                         int level,
1930                                         struct ilk_wm_maximums *max)
1931 {
1932         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934         max->cur = ilk_cursor_wm_reg_max(dev, level);
1935         max->fbc = ilk_fbc_wm_reg_max(dev);
1936 }
1937
1938 static bool ilk_validate_wm_level(int level,
1939                                   const struct ilk_wm_maximums *max,
1940                                   struct intel_wm_level *result)
1941 {
1942         bool ret;
1943
1944         /* already determined to be invalid? */
1945         if (!result->enable)
1946                 return false;
1947
1948         result->enable = result->pri_val <= max->pri &&
1949                          result->spr_val <= max->spr &&
1950                          result->cur_val <= max->cur;
1951
1952         ret = result->enable;
1953
1954         /*
1955          * HACK until we can pre-compute everything,
1956          * and thus fail gracefully if LP0 watermarks
1957          * are exceeded...
1958          */
1959         if (level == 0 && !result->enable) {
1960                 if (result->pri_val > max->pri)
1961                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962                                       level, result->pri_val, max->pri);
1963                 if (result->spr_val > max->spr)
1964                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965                                       level, result->spr_val, max->spr);
1966                 if (result->cur_val > max->cur)
1967                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968                                       level, result->cur_val, max->cur);
1969
1970                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973                 result->enable = true;
1974         }
1975
1976         return ret;
1977 }
1978
1979 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1980                                  const struct intel_crtc *intel_crtc,
1981                                  int level,
1982                                  struct intel_crtc_state *cstate,
1983                                  struct intel_plane_state *pristate,
1984                                  struct intel_plane_state *sprstate,
1985                                  struct intel_plane_state *curstate,
1986                                  struct intel_wm_level *result)
1987 {
1988         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992         /* WM1+ latency values stored in 0.5us units */
1993         if (level > 0) {
1994                 pri_latency *= 5;
1995                 spr_latency *= 5;
1996                 cur_latency *= 5;
1997         }
1998
1999         if (pristate) {
2000                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2001                                                      pri_latency, level);
2002                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2003         }
2004
2005         if (sprstate)
2006                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2007
2008         if (curstate)
2009                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2010
2011         result->enable = true;
2012 }
2013
2014 static uint32_t
2015 hsw_compute_linetime_wm(struct drm_device *dev,
2016                         struct intel_crtc_state *cstate)
2017 {
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         const struct drm_display_mode *adjusted_mode =
2020                 &cstate->base.adjusted_mode;
2021         u32 linetime, ips_linetime;
2022
2023         if (!cstate->base.active)
2024                 return 0;
2025         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2026                 return 0;
2027         if (WARN_ON(dev_priv->cdclk_freq == 0))
2028                 return 0;
2029
2030         /* The WM are computed with base on how long it takes to fill a single
2031          * row at the given clock rate, multiplied by 8.
2032          * */
2033         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2034                                      adjusted_mode->crtc_clock);
2035         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2036                                          dev_priv->cdclk_freq);
2037
2038         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2039                PIPE_WM_LINETIME_TIME(linetime);
2040 }
2041
2042 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2043 {
2044         struct drm_i915_private *dev_priv = dev->dev_private;
2045
2046         if (IS_GEN9(dev)) {
2047                 uint32_t val;
2048                 int ret, i;
2049                 int level, max_level = ilk_wm_max_level(dev);
2050
2051                 /* read the first set of memory latencies[0:3] */
2052                 val = 0; /* data0 to be programmed to 0 for first set */
2053                 mutex_lock(&dev_priv->rps.hw_lock);
2054                 ret = sandybridge_pcode_read(dev_priv,
2055                                              GEN9_PCODE_READ_MEM_LATENCY,
2056                                              &val);
2057                 mutex_unlock(&dev_priv->rps.hw_lock);
2058
2059                 if (ret) {
2060                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2061                         return;
2062                 }
2063
2064                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2065                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2066                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2067                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2068                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2069                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2070                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2071
2072                 /* read the second set of memory latencies[4:7] */
2073                 val = 1; /* data0 to be programmed to 1 for second set */
2074                 mutex_lock(&dev_priv->rps.hw_lock);
2075                 ret = sandybridge_pcode_read(dev_priv,
2076                                              GEN9_PCODE_READ_MEM_LATENCY,
2077                                              &val);
2078                 mutex_unlock(&dev_priv->rps.hw_lock);
2079                 if (ret) {
2080                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2081                         return;
2082                 }
2083
2084                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2085                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2086                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2087                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2088                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2089                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2090                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2091
2092                 /*
2093                  * WaWmMemoryReadLatency:skl
2094                  *
2095                  * punit doesn't take into account the read latency so we need
2096                  * to add 2us to the various latency levels we retrieve from
2097                  * the punit.
2098                  *   - W0 is a bit special in that it's the only level that
2099                  *   can't be disabled if we want to have display working, so
2100                  *   we always add 2us there.
2101                  *   - For levels >=1, punit returns 0us latency when they are
2102                  *   disabled, so we respect that and don't add 2us then
2103                  *
2104                  * Additionally, if a level n (n > 1) has a 0us latency, all
2105                  * levels m (m >= n) need to be disabled. We make sure to
2106                  * sanitize the values out of the punit to satisfy this
2107                  * requirement.
2108                  */
2109                 wm[0] += 2;
2110                 for (level = 1; level <= max_level; level++)
2111                         if (wm[level] != 0)
2112                                 wm[level] += 2;
2113                         else {
2114                                 for (i = level + 1; i <= max_level; i++)
2115                                         wm[i] = 0;
2116
2117                                 break;
2118                         }
2119         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2120                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2121
2122                 wm[0] = (sskpd >> 56) & 0xFF;
2123                 if (wm[0] == 0)
2124                         wm[0] = sskpd & 0xF;
2125                 wm[1] = (sskpd >> 4) & 0xFF;
2126                 wm[2] = (sskpd >> 12) & 0xFF;
2127                 wm[3] = (sskpd >> 20) & 0x1FF;
2128                 wm[4] = (sskpd >> 32) & 0x1FF;
2129         } else if (INTEL_INFO(dev)->gen >= 6) {
2130                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2131
2132                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2133                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2134                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2135                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2136         } else if (INTEL_INFO(dev)->gen >= 5) {
2137                 uint32_t mltr = I915_READ(MLTR_ILK);
2138
2139                 /* ILK primary LP0 latency is 700 ns */
2140                 wm[0] = 7;
2141                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2142                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2143         }
2144 }
2145
2146 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147 {
2148         /* ILK sprite LP0 latency is 1300 ns */
2149         if (INTEL_INFO(dev)->gen == 5)
2150                 wm[0] = 13;
2151 }
2152
2153 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154 {
2155         /* ILK cursor LP0 latency is 1300 ns */
2156         if (INTEL_INFO(dev)->gen == 5)
2157                 wm[0] = 13;
2158
2159         /* WaDoubleCursorLP3Latency:ivb */
2160         if (IS_IVYBRIDGE(dev))
2161                 wm[3] *= 2;
2162 }
2163
2164 int ilk_wm_max_level(const struct drm_device *dev)
2165 {
2166         /* how many WM levels are we expecting */
2167         if (INTEL_INFO(dev)->gen >= 9)
2168                 return 7;
2169         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2170                 return 4;
2171         else if (INTEL_INFO(dev)->gen >= 6)
2172                 return 3;
2173         else
2174                 return 2;
2175 }
2176
2177 static void intel_print_wm_latency(struct drm_device *dev,
2178                                    const char *name,
2179                                    const uint16_t wm[8])
2180 {
2181         int level, max_level = ilk_wm_max_level(dev);
2182
2183         for (level = 0; level <= max_level; level++) {
2184                 unsigned int latency = wm[level];
2185
2186                 if (latency == 0) {
2187                         DRM_ERROR("%s WM%d latency not provided\n",
2188                                   name, level);
2189                         continue;
2190                 }
2191
2192                 /*
2193                  * - latencies are in us on gen9.
2194                  * - before then, WM1+ latency values are in 0.5us units
2195                  */
2196                 if (IS_GEN9(dev))
2197                         latency *= 10;
2198                 else if (level > 0)
2199                         latency *= 5;
2200
2201                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2202                               name, level, wm[level],
2203                               latency / 10, latency % 10);
2204         }
2205 }
2206
2207 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2208                                     uint16_t wm[5], uint16_t min)
2209 {
2210         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2211
2212         if (wm[0] >= min)
2213                 return false;
2214
2215         wm[0] = max(wm[0], min);
2216         for (level = 1; level <= max_level; level++)
2217                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2218
2219         return true;
2220 }
2221
2222 static void snb_wm_latency_quirk(struct drm_device *dev)
2223 {
2224         struct drm_i915_private *dev_priv = dev->dev_private;
2225         bool changed;
2226
2227         /*
2228          * The BIOS provided WM memory latency values are often
2229          * inadequate for high resolution displays. Adjust them.
2230          */
2231         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2232                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2233                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2234
2235         if (!changed)
2236                 return;
2237
2238         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2239         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2242 }
2243
2244 static void ilk_setup_wm_latency(struct drm_device *dev)
2245 {
2246         struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2249
2250         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2251                sizeof(dev_priv->wm.pri_latency));
2252         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2253                sizeof(dev_priv->wm.pri_latency));
2254
2255         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2256         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2257
2258         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2259         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2260         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2261
2262         if (IS_GEN6(dev))
2263                 snb_wm_latency_quirk(dev);
2264 }
2265
2266 static void skl_setup_wm_latency(struct drm_device *dev)
2267 {
2268         struct drm_i915_private *dev_priv = dev->dev_private;
2269
2270         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2271         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2272 }
2273
2274 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2275                                  struct intel_pipe_wm *pipe_wm)
2276 {
2277         /* LP0 watermark maximums depend on this pipe alone */
2278         const struct intel_wm_config config = {
2279                 .num_pipes_active = 1,
2280                 .sprites_enabled = pipe_wm->sprites_enabled,
2281                 .sprites_scaled = pipe_wm->sprites_scaled,
2282         };
2283         struct ilk_wm_maximums max;
2284
2285         /* LP0 watermarks always use 1/2 DDB partitioning */
2286         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2287
2288         /* At least LP0 must be valid */
2289         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2290                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2291                 return false;
2292         }
2293
2294         return true;
2295 }
2296
2297 /* Compute new watermarks for the pipe */
2298 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2299 {
2300         struct drm_atomic_state *state = cstate->base.state;
2301         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2302         struct intel_pipe_wm *pipe_wm;
2303         struct drm_device *dev = state->dev;
2304         const struct drm_i915_private *dev_priv = dev->dev_private;
2305         struct intel_plane *intel_plane;
2306         struct intel_plane_state *pristate = NULL;
2307         struct intel_plane_state *sprstate = NULL;
2308         struct intel_plane_state *curstate = NULL;
2309         int level, max_level = ilk_wm_max_level(dev), usable_level;
2310         struct ilk_wm_maximums max;
2311
2312         pipe_wm = &cstate->wm.optimal.ilk;
2313
2314         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2315                 struct intel_plane_state *ps;
2316
2317                 ps = intel_atomic_get_existing_plane_state(state,
2318                                                            intel_plane);
2319                 if (!ps)
2320                         continue;
2321
2322                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2323                         pristate = ps;
2324                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2325                         sprstate = ps;
2326                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2327                         curstate = ps;
2328         }
2329
2330         pipe_wm->pipe_enabled = cstate->base.active;
2331         if (sprstate) {
2332                 pipe_wm->sprites_enabled = sprstate->visible;
2333                 pipe_wm->sprites_scaled = sprstate->visible &&
2334                         (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2335                          drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2336         }
2337
2338         usable_level = max_level;
2339
2340         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2341         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2342                 usable_level = 1;
2343
2344         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2345         if (pipe_wm->sprites_scaled)
2346                 usable_level = 0;
2347
2348         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2349                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2350
2351         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2352         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2353
2354         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2355                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
2356
2357         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2358                 return -EINVAL;
2359
2360         ilk_compute_wm_reg_maximums(dev, 1, &max);
2361
2362         for (level = 1; level <= max_level; level++) {
2363                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2364
2365                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2366                                      pristate, sprstate, curstate, wm);
2367
2368                 /*
2369                  * Disable any watermark level that exceeds the
2370                  * register maximums since such watermarks are
2371                  * always invalid.
2372                  */
2373                 if (level > usable_level)
2374                         continue;
2375
2376                 if (ilk_validate_wm_level(level, &max, wm))
2377                         pipe_wm->wm[level] = *wm;
2378                 else
2379                         usable_level = level;
2380         }
2381
2382         return 0;
2383 }
2384
2385 /*
2386  * Build a set of 'intermediate' watermark values that satisfy both the old
2387  * state and the new state.  These can be programmed to the hardware
2388  * immediately.
2389  */
2390 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2391                                        struct intel_crtc *intel_crtc,
2392                                        struct intel_crtc_state *newstate)
2393 {
2394         struct intel_pipe_wm *a = &newstate->wm.intermediate;
2395         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2396         int level, max_level = ilk_wm_max_level(dev);
2397
2398         /*
2399          * Start with the final, target watermarks, then combine with the
2400          * currently active watermarks to get values that are safe both before
2401          * and after the vblank.
2402          */
2403         *a = newstate->wm.optimal.ilk;
2404         a->pipe_enabled |= b->pipe_enabled;
2405         a->sprites_enabled |= b->sprites_enabled;
2406         a->sprites_scaled |= b->sprites_scaled;
2407
2408         for (level = 0; level <= max_level; level++) {
2409                 struct intel_wm_level *a_wm = &a->wm[level];
2410                 const struct intel_wm_level *b_wm = &b->wm[level];
2411
2412                 a_wm->enable &= b_wm->enable;
2413                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2414                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2415                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2416                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2417         }
2418
2419         /*
2420          * We need to make sure that these merged watermark values are
2421          * actually a valid configuration themselves.  If they're not,
2422          * there's no safe way to transition from the old state to
2423          * the new state, so we need to fail the atomic transaction.
2424          */
2425         if (!ilk_validate_pipe_wm(dev, a))
2426                 return -EINVAL;
2427
2428         /*
2429          * If our intermediate WM are identical to the final WM, then we can
2430          * omit the post-vblank programming; only update if it's different.
2431          */
2432         if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2433                 newstate->wm.need_postvbl_update = false;
2434
2435         return 0;
2436 }
2437
2438 /*
2439  * Merge the watermarks from all active pipes for a specific level.
2440  */
2441 static void ilk_merge_wm_level(struct drm_device *dev,
2442                                int level,
2443                                struct intel_wm_level *ret_wm)
2444 {
2445         const struct intel_crtc *intel_crtc;
2446
2447         ret_wm->enable = true;
2448
2449         for_each_intel_crtc(dev, intel_crtc) {
2450                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2451                 const struct intel_wm_level *wm = &active->wm[level];
2452
2453                 if (!active->pipe_enabled)
2454                         continue;
2455
2456                 /*
2457                  * The watermark values may have been used in the past,
2458                  * so we must maintain them in the registers for some
2459                  * time even if the level is now disabled.
2460                  */
2461                 if (!wm->enable)
2462                         ret_wm->enable = false;
2463
2464                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2465                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2466                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2467                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2468         }
2469 }
2470
2471 /*
2472  * Merge all low power watermarks for all active pipes.
2473  */
2474 static void ilk_wm_merge(struct drm_device *dev,
2475                          const struct intel_wm_config *config,
2476                          const struct ilk_wm_maximums *max,
2477                          struct intel_pipe_wm *merged)
2478 {
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480         int level, max_level = ilk_wm_max_level(dev);
2481         int last_enabled_level = max_level;
2482
2483         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2484         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2485             config->num_pipes_active > 1)
2486                 return;
2487
2488         /* ILK: FBC WM must be disabled always */
2489         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2490
2491         /* merge each WM1+ level */
2492         for (level = 1; level <= max_level; level++) {
2493                 struct intel_wm_level *wm = &merged->wm[level];
2494
2495                 ilk_merge_wm_level(dev, level, wm);
2496
2497                 if (level > last_enabled_level)
2498                         wm->enable = false;
2499                 else if (!ilk_validate_wm_level(level, max, wm))
2500                         /* make sure all following levels get disabled */
2501                         last_enabled_level = level - 1;
2502
2503                 /*
2504                  * The spec says it is preferred to disable
2505                  * FBC WMs instead of disabling a WM level.
2506                  */
2507                 if (wm->fbc_val > max->fbc) {
2508                         if (wm->enable)
2509                                 merged->fbc_wm_enabled = false;
2510                         wm->fbc_val = 0;
2511                 }
2512         }
2513
2514         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2515         /*
2516          * FIXME this is racy. FBC might get enabled later.
2517          * What we should check here is whether FBC can be
2518          * enabled sometime later.
2519          */
2520         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2521             intel_fbc_is_active(dev_priv)) {
2522                 for (level = 2; level <= max_level; level++) {
2523                         struct intel_wm_level *wm = &merged->wm[level];
2524
2525                         wm->enable = false;
2526                 }
2527         }
2528 }
2529
2530 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2531 {
2532         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2533         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2534 }
2535
2536 /* The value we need to program into the WM_LPx latency field */
2537 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2538 {
2539         struct drm_i915_private *dev_priv = dev->dev_private;
2540
2541         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2542                 return 2 * level;
2543         else
2544                 return dev_priv->wm.pri_latency[level];
2545 }
2546
2547 static void ilk_compute_wm_results(struct drm_device *dev,
2548                                    const struct intel_pipe_wm *merged,
2549                                    enum intel_ddb_partitioning partitioning,
2550                                    struct ilk_wm_values *results)
2551 {
2552         struct intel_crtc *intel_crtc;
2553         int level, wm_lp;
2554
2555         results->enable_fbc_wm = merged->fbc_wm_enabled;
2556         results->partitioning = partitioning;
2557
2558         /* LP1+ register values */
2559         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2560                 const struct intel_wm_level *r;
2561
2562                 level = ilk_wm_lp_to_level(wm_lp, merged);
2563
2564                 r = &merged->wm[level];
2565
2566                 /*
2567                  * Maintain the watermark values even if the level is
2568                  * disabled. Doing otherwise could cause underruns.
2569                  */
2570                 results->wm_lp[wm_lp - 1] =
2571                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2572                         (r->pri_val << WM1_LP_SR_SHIFT) |
2573                         r->cur_val;
2574
2575                 if (r->enable)
2576                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2577
2578                 if (INTEL_INFO(dev)->gen >= 8)
2579                         results->wm_lp[wm_lp - 1] |=
2580                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2581                 else
2582                         results->wm_lp[wm_lp - 1] |=
2583                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2584
2585                 /*
2586                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2587                  * level is disabled. Doing otherwise could cause underruns.
2588                  */
2589                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2590                         WARN_ON(wm_lp != 1);
2591                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2592                 } else
2593                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2594         }
2595
2596         /* LP0 register values */
2597         for_each_intel_crtc(dev, intel_crtc) {
2598                 enum pipe pipe = intel_crtc->pipe;
2599                 const struct intel_wm_level *r =
2600                         &intel_crtc->wm.active.ilk.wm[0];
2601
2602                 if (WARN_ON(!r->enable))
2603                         continue;
2604
2605                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2606
2607                 results->wm_pipe[pipe] =
2608                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2609                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2610                         r->cur_val;
2611         }
2612 }
2613
2614 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2615  * case both are at the same level. Prefer r1 in case they're the same. */
2616 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2617                                                   struct intel_pipe_wm *r1,
2618                                                   struct intel_pipe_wm *r2)
2619 {
2620         int level, max_level = ilk_wm_max_level(dev);
2621         int level1 = 0, level2 = 0;
2622
2623         for (level = 1; level <= max_level; level++) {
2624                 if (r1->wm[level].enable)
2625                         level1 = level;
2626                 if (r2->wm[level].enable)
2627                         level2 = level;
2628         }
2629
2630         if (level1 == level2) {
2631                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2632                         return r2;
2633                 else
2634                         return r1;
2635         } else if (level1 > level2) {
2636                 return r1;
2637         } else {
2638                 return r2;
2639         }
2640 }
2641
2642 /* dirty bits used to track which watermarks need changes */
2643 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2644 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2645 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2646 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2647 #define WM_DIRTY_FBC (1 << 24)
2648 #define WM_DIRTY_DDB (1 << 25)
2649
2650 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2651                                          const struct ilk_wm_values *old,
2652                                          const struct ilk_wm_values *new)
2653 {
2654         unsigned int dirty = 0;
2655         enum pipe pipe;
2656         int wm_lp;
2657
2658         for_each_pipe(dev_priv, pipe) {
2659                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2660                         dirty |= WM_DIRTY_LINETIME(pipe);
2661                         /* Must disable LP1+ watermarks too */
2662                         dirty |= WM_DIRTY_LP_ALL;
2663                 }
2664
2665                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2666                         dirty |= WM_DIRTY_PIPE(pipe);
2667                         /* Must disable LP1+ watermarks too */
2668                         dirty |= WM_DIRTY_LP_ALL;
2669                 }
2670         }
2671
2672         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2673                 dirty |= WM_DIRTY_FBC;
2674                 /* Must disable LP1+ watermarks too */
2675                 dirty |= WM_DIRTY_LP_ALL;
2676         }
2677
2678         if (old->partitioning != new->partitioning) {
2679                 dirty |= WM_DIRTY_DDB;
2680                 /* Must disable LP1+ watermarks too */
2681                 dirty |= WM_DIRTY_LP_ALL;
2682         }
2683
2684         /* LP1+ watermarks already deemed dirty, no need to continue */
2685         if (dirty & WM_DIRTY_LP_ALL)
2686                 return dirty;
2687
2688         /* Find the lowest numbered LP1+ watermark in need of an update... */
2689         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2690                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2691                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2692                         break;
2693         }
2694
2695         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2696         for (; wm_lp <= 3; wm_lp++)
2697                 dirty |= WM_DIRTY_LP(wm_lp);
2698
2699         return dirty;
2700 }
2701
2702 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2703                                unsigned int dirty)
2704 {
2705         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2706         bool changed = false;
2707
2708         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2709                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2710                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2711                 changed = true;
2712         }
2713         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2714                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2715                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2716                 changed = true;
2717         }
2718         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2719                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2720                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2721                 changed = true;
2722         }
2723
2724         /*
2725          * Don't touch WM1S_LP_EN here.
2726          * Doing so could cause underruns.
2727          */
2728
2729         return changed;
2730 }
2731
2732 /*
2733  * The spec says we shouldn't write when we don't need, because every write
2734  * causes WMs to be re-evaluated, expending some power.
2735  */
2736 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2737                                 struct ilk_wm_values *results)
2738 {
2739         struct drm_device *dev = dev_priv->dev;
2740         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2741         unsigned int dirty;
2742         uint32_t val;
2743
2744         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2745         if (!dirty)
2746                 return;
2747
2748         _ilk_disable_lp_wm(dev_priv, dirty);
2749
2750         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2751                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2752         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2753                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2754         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2755                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2756
2757         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2758                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2759         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2760                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2761         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2762                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2763
2764         if (dirty & WM_DIRTY_DDB) {
2765                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2766                         val = I915_READ(WM_MISC);
2767                         if (results->partitioning == INTEL_DDB_PART_1_2)
2768                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2769                         else
2770                                 val |= WM_MISC_DATA_PARTITION_5_6;
2771                         I915_WRITE(WM_MISC, val);
2772                 } else {
2773                         val = I915_READ(DISP_ARB_CTL2);
2774                         if (results->partitioning == INTEL_DDB_PART_1_2)
2775                                 val &= ~DISP_DATA_PARTITION_5_6;
2776                         else
2777                                 val |= DISP_DATA_PARTITION_5_6;
2778                         I915_WRITE(DISP_ARB_CTL2, val);
2779                 }
2780         }
2781
2782         if (dirty & WM_DIRTY_FBC) {
2783                 val = I915_READ(DISP_ARB_CTL);
2784                 if (results->enable_fbc_wm)
2785                         val &= ~DISP_FBC_WM_DIS;
2786                 else
2787                         val |= DISP_FBC_WM_DIS;
2788                 I915_WRITE(DISP_ARB_CTL, val);
2789         }
2790
2791         if (dirty & WM_DIRTY_LP(1) &&
2792             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2793                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2794
2795         if (INTEL_INFO(dev)->gen >= 7) {
2796                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2797                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2798                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2799                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2800         }
2801
2802         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2803                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2804         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2805                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2806         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2807                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2808
2809         dev_priv->wm.hw = *results;
2810 }
2811
2812 bool ilk_disable_lp_wm(struct drm_device *dev)
2813 {
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815
2816         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2817 }
2818
2819 /*
2820  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2821  * different active planes.
2822  */
2823
2824 #define SKL_DDB_SIZE            896     /* in blocks */
2825 #define BXT_DDB_SIZE            512
2826
2827 /*
2828  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2829  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2830  * other universal planes are in indices 1..n.  Note that this may leave unused
2831  * indices between the top "sprite" plane and the cursor.
2832  */
2833 static int
2834 skl_wm_plane_id(const struct intel_plane *plane)
2835 {
2836         switch (plane->base.type) {
2837         case DRM_PLANE_TYPE_PRIMARY:
2838                 return 0;
2839         case DRM_PLANE_TYPE_CURSOR:
2840                 return PLANE_CURSOR;
2841         case DRM_PLANE_TYPE_OVERLAY:
2842                 return plane->plane + 1;
2843         default:
2844                 MISSING_CASE(plane->base.type);
2845                 return plane->plane;
2846         }
2847 }
2848
2849 static void
2850 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2851                                    const struct intel_crtc_state *cstate,
2852                                    const struct intel_wm_config *config,
2853                                    struct skl_ddb_entry *alloc /* out */)
2854 {
2855         struct drm_crtc *for_crtc = cstate->base.crtc;
2856         struct drm_crtc *crtc;
2857         unsigned int pipe_size, ddb_size;
2858         int nth_active_pipe;
2859
2860         if (!cstate->base.active) {
2861                 alloc->start = 0;
2862                 alloc->end = 0;
2863                 return;
2864         }
2865
2866         if (IS_BROXTON(dev))
2867                 ddb_size = BXT_DDB_SIZE;
2868         else
2869                 ddb_size = SKL_DDB_SIZE;
2870
2871         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2872
2873         nth_active_pipe = 0;
2874         for_each_crtc(dev, crtc) {
2875                 if (!to_intel_crtc(crtc)->active)
2876                         continue;
2877
2878                 if (crtc == for_crtc)
2879                         break;
2880
2881                 nth_active_pipe++;
2882         }
2883
2884         pipe_size = ddb_size / config->num_pipes_active;
2885         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2886         alloc->end = alloc->start + pipe_size;
2887 }
2888
2889 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2890 {
2891         if (config->num_pipes_active == 1)
2892                 return 32;
2893
2894         return 8;
2895 }
2896
2897 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2898 {
2899         entry->start = reg & 0x3ff;
2900         entry->end = (reg >> 16) & 0x3ff;
2901         if (entry->end)
2902                 entry->end += 1;
2903 }
2904
2905 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2906                           struct skl_ddb_allocation *ddb /* out */)
2907 {
2908         enum pipe pipe;
2909         int plane;
2910         u32 val;
2911
2912         memset(ddb, 0, sizeof(*ddb));
2913
2914         for_each_pipe(dev_priv, pipe) {
2915                 enum intel_display_power_domain power_domain;
2916
2917                 power_domain = POWER_DOMAIN_PIPE(pipe);
2918                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2919                         continue;
2920
2921                 for_each_plane(dev_priv, pipe, plane) {
2922                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2923                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2924                                                    val);
2925                 }
2926
2927                 val = I915_READ(CUR_BUF_CFG(pipe));
2928                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2929                                            val);
2930
2931                 intel_display_power_put(dev_priv, power_domain);
2932         }
2933 }
2934
2935 static unsigned int
2936 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2937                              const struct drm_plane_state *pstate,
2938                              int y)
2939 {
2940         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2941         struct drm_framebuffer *fb = pstate->fb;
2942
2943         /* for planar format */
2944         if (fb->pixel_format == DRM_FORMAT_NV12) {
2945                 if (y)  /* y-plane data rate */
2946                         return intel_crtc->config->pipe_src_w *
2947                                 intel_crtc->config->pipe_src_h *
2948                                 drm_format_plane_cpp(fb->pixel_format, 0);
2949                 else    /* uv-plane data rate */
2950                         return (intel_crtc->config->pipe_src_w/2) *
2951                                 (intel_crtc->config->pipe_src_h/2) *
2952                                 drm_format_plane_cpp(fb->pixel_format, 1);
2953         }
2954
2955         /* for packed formats */
2956         return intel_crtc->config->pipe_src_w *
2957                 intel_crtc->config->pipe_src_h *
2958                 drm_format_plane_cpp(fb->pixel_format, 0);
2959 }
2960
2961 /*
2962  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2963  * a 8192x4096@32bpp framebuffer:
2964  *   3 * 4096 * 8192  * 4 < 2^32
2965  */
2966 static unsigned int
2967 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2968 {
2969         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2970         struct drm_device *dev = intel_crtc->base.dev;
2971         const struct intel_plane *intel_plane;
2972         unsigned int total_data_rate = 0;
2973
2974         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2975                 const struct drm_plane_state *pstate = intel_plane->base.state;
2976
2977                 if (pstate->fb == NULL)
2978                         continue;
2979
2980                 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2981                         continue;
2982
2983                 /* packed/uv */
2984                 total_data_rate += skl_plane_relative_data_rate(cstate,
2985                                                                 pstate,
2986                                                                 0);
2987
2988                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2989                         /* y-plane */
2990                         total_data_rate += skl_plane_relative_data_rate(cstate,
2991                                                                         pstate,
2992                                                                         1);
2993         }
2994
2995         return total_data_rate;
2996 }
2997
2998 static void
2999 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3000                       struct skl_ddb_allocation *ddb /* out */)
3001 {
3002         struct drm_crtc *crtc = cstate->base.crtc;
3003         struct drm_device *dev = crtc->dev;
3004         struct drm_i915_private *dev_priv = to_i915(dev);
3005         struct intel_wm_config *config = &dev_priv->wm.config;
3006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3007         struct intel_plane *intel_plane;
3008         enum pipe pipe = intel_crtc->pipe;
3009         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3010         uint16_t alloc_size, start, cursor_blocks;
3011         uint16_t minimum[I915_MAX_PLANES];
3012         uint16_t y_minimum[I915_MAX_PLANES];
3013         unsigned int total_data_rate;
3014
3015         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
3016         alloc_size = skl_ddb_entry_size(alloc);
3017         if (alloc_size == 0) {
3018                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3019                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3020                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
3021                 return;
3022         }
3023
3024         cursor_blocks = skl_cursor_allocation(config);
3025         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3026         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3027
3028         alloc_size -= cursor_blocks;
3029         alloc->end -= cursor_blocks;
3030
3031         /* 1. Allocate the mininum required blocks for each active plane */
3032         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3033                 struct drm_plane *plane = &intel_plane->base;
3034                 struct drm_framebuffer *fb = plane->state->fb;
3035                 int id = skl_wm_plane_id(intel_plane);
3036
3037                 if (fb == NULL)
3038                         continue;
3039                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3040                         continue;
3041
3042                 minimum[id] = 8;
3043                 alloc_size -= minimum[id];
3044                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3045                 alloc_size -= y_minimum[id];
3046         }
3047
3048         /*
3049          * 2. Distribute the remaining space in proportion to the amount of
3050          * data each plane needs to fetch from memory.
3051          *
3052          * FIXME: we may not allocate every single block here.
3053          */
3054         total_data_rate = skl_get_total_relative_data_rate(cstate);
3055
3056         start = alloc->start;
3057         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3058                 struct drm_plane *plane = &intel_plane->base;
3059                 struct drm_plane_state *pstate = intel_plane->base.state;
3060                 unsigned int data_rate, y_data_rate;
3061                 uint16_t plane_blocks, y_plane_blocks = 0;
3062                 int id = skl_wm_plane_id(intel_plane);
3063
3064                 if (pstate->fb == NULL)
3065                         continue;
3066                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3067                         continue;
3068
3069                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3070
3071                 /*
3072                  * allocation for (packed formats) or (uv-plane part of planar format):
3073                  * promote the expression to 64 bits to avoid overflowing, the
3074                  * result is < available as data_rate / total_data_rate < 1
3075                  */
3076                 plane_blocks = minimum[id];
3077                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3078                                         total_data_rate);
3079
3080                 ddb->plane[pipe][id].start = start;
3081                 ddb->plane[pipe][id].end = start + plane_blocks;
3082
3083                 start += plane_blocks;
3084
3085                 /*
3086                  * allocation for y_plane part of planar format:
3087                  */
3088                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3089                         y_data_rate = skl_plane_relative_data_rate(cstate,
3090                                                                    pstate,
3091                                                                    1);
3092                         y_plane_blocks = y_minimum[id];
3093                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3094                                                 total_data_rate);
3095
3096                         ddb->y_plane[pipe][id].start = start;
3097                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3098
3099                         start += y_plane_blocks;
3100                 }
3101
3102         }
3103
3104 }
3105
3106 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3107 {
3108         /* TODO: Take into account the scalers once we support them */
3109         return config->base.adjusted_mode.crtc_clock;
3110 }
3111
3112 /*
3113  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3114  * for the read latency) and cpp should always be <= 8, so that
3115  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3116  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3117 */
3118 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3119 {
3120         uint32_t wm_intermediate_val, ret;
3121
3122         if (latency == 0)
3123                 return UINT_MAX;
3124
3125         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3126         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3127
3128         return ret;
3129 }
3130
3131 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3132                                uint32_t horiz_pixels, uint8_t cpp,
3133                                uint64_t tiling, uint32_t latency)
3134 {
3135         uint32_t ret;
3136         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3137         uint32_t wm_intermediate_val;
3138
3139         if (latency == 0)
3140                 return UINT_MAX;
3141
3142         plane_bytes_per_line = horiz_pixels * cpp;
3143
3144         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3145             tiling == I915_FORMAT_MOD_Yf_TILED) {
3146                 plane_bytes_per_line *= 4;
3147                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3148                 plane_blocks_per_line /= 4;
3149         } else {
3150                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3151         }
3152
3153         wm_intermediate_val = latency * pixel_rate;
3154         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3155                                 plane_blocks_per_line;
3156
3157         return ret;
3158 }
3159
3160 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3161                                        const struct intel_crtc *intel_crtc)
3162 {
3163         struct drm_device *dev = intel_crtc->base.dev;
3164         struct drm_i915_private *dev_priv = dev->dev_private;
3165         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3166
3167         /*
3168          * If ddb allocation of pipes changed, it may require recalculation of
3169          * watermarks
3170          */
3171         if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3172                 return true;
3173
3174         return false;
3175 }
3176
3177 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3178                                  struct intel_crtc_state *cstate,
3179                                  struct intel_plane *intel_plane,
3180                                  uint16_t ddb_allocation,
3181                                  int level,
3182                                  uint16_t *out_blocks, /* out */
3183                                  uint8_t *out_lines /* out */)
3184 {
3185         struct drm_plane *plane = &intel_plane->base;
3186         struct drm_framebuffer *fb = plane->state->fb;
3187         uint32_t latency = dev_priv->wm.skl_latency[level];
3188         uint32_t method1, method2;
3189         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3190         uint32_t res_blocks, res_lines;
3191         uint32_t selected_result;
3192         uint8_t cpp;
3193
3194         if (latency == 0 || !cstate->base.active || !fb)
3195                 return false;
3196
3197         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3198         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3199                                  cpp, latency);
3200         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3201                                  cstate->base.adjusted_mode.crtc_htotal,
3202                                  cstate->pipe_src_w,
3203                                  cpp, fb->modifier[0],
3204                                  latency);
3205
3206         plane_bytes_per_line = cstate->pipe_src_w * cpp;
3207         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3208
3209         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3210             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3211                 uint32_t min_scanlines = 4;
3212                 uint32_t y_tile_minimum;
3213                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3214                         int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3215                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3216                                 drm_format_plane_cpp(fb->pixel_format, 0);
3217
3218                         switch (cpp) {
3219                         case 1:
3220                                 min_scanlines = 16;
3221                                 break;
3222                         case 2:
3223                                 min_scanlines = 8;
3224                                 break;
3225                         case 8:
3226                                 WARN(1, "Unsupported pixel depth for rotation");
3227                         }
3228                 }
3229                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3230                 selected_result = max(method2, y_tile_minimum);
3231         } else {
3232                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3233                         selected_result = min(method1, method2);
3234                 else
3235                         selected_result = method1;
3236         }
3237
3238         res_blocks = selected_result + 1;
3239         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3240
3241         if (level >= 1 && level <= 7) {
3242                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3243                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3244                         res_lines += 4;
3245                 else
3246                         res_blocks++;
3247         }
3248
3249         if (res_blocks >= ddb_allocation || res_lines > 31)
3250                 return false;
3251
3252         *out_blocks = res_blocks;
3253         *out_lines = res_lines;
3254
3255         return true;
3256 }
3257
3258 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3259                                  struct skl_ddb_allocation *ddb,
3260                                  struct intel_crtc_state *cstate,
3261                                  int level,
3262                                  struct skl_wm_level *result)
3263 {
3264         struct drm_device *dev = dev_priv->dev;
3265         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3266         struct intel_plane *intel_plane;
3267         uint16_t ddb_blocks;
3268         enum pipe pipe = intel_crtc->pipe;
3269
3270         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3271                 int i = skl_wm_plane_id(intel_plane);
3272
3273                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3274
3275                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3276                                                 cstate,
3277                                                 intel_plane,
3278                                                 ddb_blocks,
3279                                                 level,
3280                                                 &result->plane_res_b[i],
3281                                                 &result->plane_res_l[i]);
3282         }
3283 }
3284
3285 static uint32_t
3286 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3287 {
3288         if (!cstate->base.active)
3289                 return 0;
3290
3291         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3292                 return 0;
3293
3294         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3295                             skl_pipe_pixel_rate(cstate));
3296 }
3297
3298 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3299                                       struct skl_wm_level *trans_wm /* out */)
3300 {
3301         struct drm_crtc *crtc = cstate->base.crtc;
3302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3303         struct intel_plane *intel_plane;
3304
3305         if (!cstate->base.active)
3306                 return;
3307
3308         /* Until we know more, just disable transition WMs */
3309         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3310                 int i = skl_wm_plane_id(intel_plane);
3311
3312                 trans_wm->plane_en[i] = false;
3313         }
3314 }
3315
3316 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3317                                 struct skl_ddb_allocation *ddb,
3318                                 struct skl_pipe_wm *pipe_wm)
3319 {
3320         struct drm_device *dev = cstate->base.crtc->dev;
3321         const struct drm_i915_private *dev_priv = dev->dev_private;
3322         int level, max_level = ilk_wm_max_level(dev);
3323
3324         for (level = 0; level <= max_level; level++) {
3325                 skl_compute_wm_level(dev_priv, ddb, cstate,
3326                                      level, &pipe_wm->wm[level]);
3327         }
3328         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3329
3330         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3331 }
3332
3333 static void skl_compute_wm_results(struct drm_device *dev,
3334                                    struct skl_pipe_wm *p_wm,
3335                                    struct skl_wm_values *r,
3336                                    struct intel_crtc *intel_crtc)
3337 {
3338         int level, max_level = ilk_wm_max_level(dev);
3339         enum pipe pipe = intel_crtc->pipe;
3340         uint32_t temp;
3341         int i;
3342
3343         for (level = 0; level <= max_level; level++) {
3344                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3345                         temp = 0;
3346
3347                         temp |= p_wm->wm[level].plane_res_l[i] <<
3348                                         PLANE_WM_LINES_SHIFT;
3349                         temp |= p_wm->wm[level].plane_res_b[i];
3350                         if (p_wm->wm[level].plane_en[i])
3351                                 temp |= PLANE_WM_EN;
3352
3353                         r->plane[pipe][i][level] = temp;
3354                 }
3355
3356                 temp = 0;
3357
3358                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3359                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3360
3361                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3362                         temp |= PLANE_WM_EN;
3363
3364                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3365
3366         }
3367
3368         /* transition WMs */
3369         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3370                 temp = 0;
3371                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3372                 temp |= p_wm->trans_wm.plane_res_b[i];
3373                 if (p_wm->trans_wm.plane_en[i])
3374                         temp |= PLANE_WM_EN;
3375
3376                 r->plane_trans[pipe][i] = temp;
3377         }
3378
3379         temp = 0;
3380         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3381         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3382         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3383                 temp |= PLANE_WM_EN;
3384
3385         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3386
3387         r->wm_linetime[pipe] = p_wm->linetime;
3388 }
3389
3390 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3391                                 i915_reg_t reg,
3392                                 const struct skl_ddb_entry *entry)
3393 {
3394         if (entry->end)
3395                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3396         else
3397                 I915_WRITE(reg, 0);
3398 }
3399
3400 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3401                                 const struct skl_wm_values *new)
3402 {
3403         struct drm_device *dev = dev_priv->dev;
3404         struct intel_crtc *crtc;
3405
3406         for_each_intel_crtc(dev, crtc) {
3407                 int i, level, max_level = ilk_wm_max_level(dev);
3408                 enum pipe pipe = crtc->pipe;
3409
3410                 if (!new->dirty[pipe])
3411                         continue;
3412
3413                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3414
3415                 for (level = 0; level <= max_level; level++) {
3416                         for (i = 0; i < intel_num_planes(crtc); i++)
3417                                 I915_WRITE(PLANE_WM(pipe, i, level),
3418                                            new->plane[pipe][i][level]);
3419                         I915_WRITE(CUR_WM(pipe, level),
3420                                    new->plane[pipe][PLANE_CURSOR][level]);
3421                 }
3422                 for (i = 0; i < intel_num_planes(crtc); i++)
3423                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3424                                    new->plane_trans[pipe][i]);
3425                 I915_WRITE(CUR_WM_TRANS(pipe),
3426                            new->plane_trans[pipe][PLANE_CURSOR]);
3427
3428                 for (i = 0; i < intel_num_planes(crtc); i++) {
3429                         skl_ddb_entry_write(dev_priv,
3430                                             PLANE_BUF_CFG(pipe, i),
3431                                             &new->ddb.plane[pipe][i]);
3432                         skl_ddb_entry_write(dev_priv,
3433                                             PLANE_NV12_BUF_CFG(pipe, i),
3434                                             &new->ddb.y_plane[pipe][i]);
3435                 }
3436
3437                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3438                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3439         }
3440 }
3441
3442 /*
3443  * When setting up a new DDB allocation arrangement, we need to correctly
3444  * sequence the times at which the new allocations for the pipes are taken into
3445  * account or we'll have pipes fetching from space previously allocated to
3446  * another pipe.
3447  *
3448  * Roughly the sequence looks like:
3449  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3450  *     overlapping with a previous light-up pipe (another way to put it is:
3451  *     pipes with their new allocation strickly included into their old ones).
3452  *  2. re-allocate the other pipes that get their allocation reduced
3453  *  3. allocate the pipes having their allocation increased
3454  *
3455  * Steps 1. and 2. are here to take care of the following case:
3456  * - Initially DDB looks like this:
3457  *     |   B    |   C    |
3458  * - enable pipe A.
3459  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3460  *   allocation
3461  *     |  A  |  B  |  C  |
3462  *
3463  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3464  */
3465
3466 static void
3467 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3468 {
3469         int plane;
3470
3471         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3472
3473         for_each_plane(dev_priv, pipe, plane) {
3474                 I915_WRITE(PLANE_SURF(pipe, plane),
3475                            I915_READ(PLANE_SURF(pipe, plane)));
3476         }
3477         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3478 }
3479
3480 static bool
3481 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3482                             const struct skl_ddb_allocation *new,
3483                             enum pipe pipe)
3484 {
3485         uint16_t old_size, new_size;
3486
3487         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3488         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3489
3490         return old_size != new_size &&
3491                new->pipe[pipe].start >= old->pipe[pipe].start &&
3492                new->pipe[pipe].end <= old->pipe[pipe].end;
3493 }
3494
3495 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3496                                 struct skl_wm_values *new_values)
3497 {
3498         struct drm_device *dev = dev_priv->dev;
3499         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3500         bool reallocated[I915_MAX_PIPES] = {};
3501         struct intel_crtc *crtc;
3502         enum pipe pipe;
3503
3504         new_ddb = &new_values->ddb;
3505         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3506
3507         /*
3508          * First pass: flush the pipes with the new allocation contained into
3509          * the old space.
3510          *
3511          * We'll wait for the vblank on those pipes to ensure we can safely
3512          * re-allocate the freed space without this pipe fetching from it.
3513          */
3514         for_each_intel_crtc(dev, crtc) {
3515                 if (!crtc->active)
3516                         continue;
3517
3518                 pipe = crtc->pipe;
3519
3520                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3521                         continue;
3522
3523                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3524                 intel_wait_for_vblank(dev, pipe);
3525
3526                 reallocated[pipe] = true;
3527         }
3528
3529
3530         /*
3531          * Second pass: flush the pipes that are having their allocation
3532          * reduced, but overlapping with a previous allocation.
3533          *
3534          * Here as well we need to wait for the vblank to make sure the freed
3535          * space is not used anymore.
3536          */
3537         for_each_intel_crtc(dev, crtc) {
3538                 if (!crtc->active)
3539                         continue;
3540
3541                 pipe = crtc->pipe;
3542
3543                 if (reallocated[pipe])
3544                         continue;
3545
3546                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3547                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3548                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3549                         intel_wait_for_vblank(dev, pipe);
3550                         reallocated[pipe] = true;
3551                 }
3552         }
3553
3554         /*
3555          * Third pass: flush the pipes that got more space allocated.
3556          *
3557          * We don't need to actively wait for the update here, next vblank
3558          * will just get more DDB space with the correct WM values.
3559          */
3560         for_each_intel_crtc(dev, crtc) {
3561                 if (!crtc->active)
3562                         continue;
3563
3564                 pipe = crtc->pipe;
3565
3566                 /*
3567                  * At this point, only the pipes more space than before are
3568                  * left to re-allocate.
3569                  */
3570                 if (reallocated[pipe])
3571                         continue;
3572
3573                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3574         }
3575 }
3576
3577 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3578                                struct skl_ddb_allocation *ddb, /* out */
3579                                struct skl_pipe_wm *pipe_wm /* out */)
3580 {
3581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3582         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3583
3584         skl_allocate_pipe_ddb(cstate, ddb);
3585         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3586
3587         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3588                 return false;
3589
3590         intel_crtc->wm.active.skl = *pipe_wm;
3591
3592         return true;
3593 }
3594
3595 static void skl_update_other_pipe_wm(struct drm_device *dev,
3596                                      struct drm_crtc *crtc,
3597                                      struct skl_wm_values *r)
3598 {
3599         struct intel_crtc *intel_crtc;
3600         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3601
3602         /*
3603          * If the WM update hasn't changed the allocation for this_crtc (the
3604          * crtc we are currently computing the new WM values for), other
3605          * enabled crtcs will keep the same allocation and we don't need to
3606          * recompute anything for them.
3607          */
3608         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3609                 return;
3610
3611         /*
3612          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3613          * other active pipes need new DDB allocation and WM values.
3614          */
3615         for_each_intel_crtc(dev, intel_crtc) {
3616                 struct skl_pipe_wm pipe_wm = {};
3617                 bool wm_changed;
3618
3619                 if (this_crtc->pipe == intel_crtc->pipe)
3620                         continue;
3621
3622                 if (!intel_crtc->active)
3623                         continue;
3624
3625                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3626                                                 &r->ddb, &pipe_wm);
3627
3628                 /*
3629                  * If we end up re-computing the other pipe WM values, it's
3630                  * because it was really needed, so we expect the WM values to
3631                  * be different.
3632                  */
3633                 WARN_ON(!wm_changed);
3634
3635                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3636                 r->dirty[intel_crtc->pipe] = true;
3637         }
3638 }
3639
3640 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3641 {
3642         watermarks->wm_linetime[pipe] = 0;
3643         memset(watermarks->plane[pipe], 0,
3644                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3645         memset(watermarks->plane_trans[pipe],
3646                0, sizeof(uint32_t) * I915_MAX_PLANES);
3647         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3648
3649         /* Clear ddb entries for pipe */
3650         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3651         memset(&watermarks->ddb.plane[pipe], 0,
3652                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3653         memset(&watermarks->ddb.y_plane[pipe], 0,
3654                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3655         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3656                sizeof(struct skl_ddb_entry));
3657
3658 }
3659
3660 static void skl_update_wm(struct drm_crtc *crtc)
3661 {
3662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3663         struct drm_device *dev = crtc->dev;
3664         struct drm_i915_private *dev_priv = dev->dev_private;
3665         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3666         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3667         struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3668
3669
3670         /* Clear all dirty flags */
3671         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3672
3673         skl_clear_wm(results, intel_crtc->pipe);
3674
3675         if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3676                 return;
3677
3678         skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3679         results->dirty[intel_crtc->pipe] = true;
3680
3681         skl_update_other_pipe_wm(dev, crtc, results);
3682         skl_write_wm_values(dev_priv, results);
3683         skl_flush_wm_values(dev_priv, results);
3684
3685         /* store the new configuration */
3686         dev_priv->wm.skl_hw = *results;
3687 }
3688
3689 static void ilk_compute_wm_config(struct drm_device *dev,
3690                                   struct intel_wm_config *config)
3691 {
3692         struct intel_crtc *crtc;
3693
3694         /* Compute the currently _active_ config */
3695         for_each_intel_crtc(dev, crtc) {
3696                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3697
3698                 if (!wm->pipe_enabled)
3699                         continue;
3700
3701                 config->sprites_enabled |= wm->sprites_enabled;
3702                 config->sprites_scaled |= wm->sprites_scaled;
3703                 config->num_pipes_active++;
3704         }
3705 }
3706
3707 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3708 {
3709         struct drm_device *dev = dev_priv->dev;
3710         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3711         struct ilk_wm_maximums max;
3712         struct intel_wm_config config = {};
3713         struct ilk_wm_values results = {};
3714         enum intel_ddb_partitioning partitioning;
3715
3716         ilk_compute_wm_config(dev, &config);
3717
3718         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3719         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3720
3721         /* 5/6 split only in single pipe config on IVB+ */
3722         if (INTEL_INFO(dev)->gen >= 7 &&
3723             config.num_pipes_active == 1 && config.sprites_enabled) {
3724                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3725                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3726
3727                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3728         } else {
3729                 best_lp_wm = &lp_wm_1_2;
3730         }
3731
3732         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3733                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3734
3735         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3736
3737         ilk_write_wm_values(dev_priv, &results);
3738 }
3739
3740 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
3741 {
3742         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3743         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3744
3745         mutex_lock(&dev_priv->wm.wm_mutex);
3746         intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3747         ilk_program_watermarks(dev_priv);
3748         mutex_unlock(&dev_priv->wm.wm_mutex);
3749 }
3750
3751 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3752 {
3753         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3754         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3755
3756         mutex_lock(&dev_priv->wm.wm_mutex);
3757         if (cstate->wm.need_postvbl_update) {
3758                 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3759                 ilk_program_watermarks(dev_priv);
3760         }
3761         mutex_unlock(&dev_priv->wm.wm_mutex);
3762 }
3763
3764 static void skl_pipe_wm_active_state(uint32_t val,
3765                                      struct skl_pipe_wm *active,
3766                                      bool is_transwm,
3767                                      bool is_cursor,
3768                                      int i,
3769                                      int level)
3770 {
3771         bool is_enabled = (val & PLANE_WM_EN) != 0;
3772
3773         if (!is_transwm) {
3774                 if (!is_cursor) {
3775                         active->wm[level].plane_en[i] = is_enabled;
3776                         active->wm[level].plane_res_b[i] =
3777                                         val & PLANE_WM_BLOCKS_MASK;
3778                         active->wm[level].plane_res_l[i] =
3779                                         (val >> PLANE_WM_LINES_SHIFT) &
3780                                                 PLANE_WM_LINES_MASK;
3781                 } else {
3782                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3783                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3784                                         val & PLANE_WM_BLOCKS_MASK;
3785                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3786                                         (val >> PLANE_WM_LINES_SHIFT) &
3787                                                 PLANE_WM_LINES_MASK;
3788                 }
3789         } else {
3790                 if (!is_cursor) {
3791                         active->trans_wm.plane_en[i] = is_enabled;
3792                         active->trans_wm.plane_res_b[i] =
3793                                         val & PLANE_WM_BLOCKS_MASK;
3794                         active->trans_wm.plane_res_l[i] =
3795                                         (val >> PLANE_WM_LINES_SHIFT) &
3796                                                 PLANE_WM_LINES_MASK;
3797                 } else {
3798                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3799                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3800                                         val & PLANE_WM_BLOCKS_MASK;
3801                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3802                                         (val >> PLANE_WM_LINES_SHIFT) &
3803                                                 PLANE_WM_LINES_MASK;
3804                 }
3805         }
3806 }
3807
3808 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3809 {
3810         struct drm_device *dev = crtc->dev;
3811         struct drm_i915_private *dev_priv = dev->dev_private;
3812         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3815         struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3816         enum pipe pipe = intel_crtc->pipe;
3817         int level, i, max_level;
3818         uint32_t temp;
3819
3820         max_level = ilk_wm_max_level(dev);
3821
3822         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3823
3824         for (level = 0; level <= max_level; level++) {
3825                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3826                         hw->plane[pipe][i][level] =
3827                                         I915_READ(PLANE_WM(pipe, i, level));
3828                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3829         }
3830
3831         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3832                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3833         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3834
3835         if (!intel_crtc->active)
3836                 return;
3837
3838         hw->dirty[pipe] = true;
3839
3840         active->linetime = hw->wm_linetime[pipe];
3841
3842         for (level = 0; level <= max_level; level++) {
3843                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3844                         temp = hw->plane[pipe][i][level];
3845                         skl_pipe_wm_active_state(temp, active, false,
3846                                                 false, i, level);
3847                 }
3848                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3849                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3850         }
3851
3852         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3853                 temp = hw->plane_trans[pipe][i];
3854                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3855         }
3856
3857         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3858         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3859
3860         intel_crtc->wm.active.skl = *active;
3861 }
3862
3863 void skl_wm_get_hw_state(struct drm_device *dev)
3864 {
3865         struct drm_i915_private *dev_priv = dev->dev_private;
3866         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3867         struct drm_crtc *crtc;
3868
3869         skl_ddb_get_hw_state(dev_priv, ddb);
3870         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3871                 skl_pipe_wm_get_hw_state(crtc);
3872 }
3873
3874 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3875 {
3876         struct drm_device *dev = crtc->dev;
3877         struct drm_i915_private *dev_priv = dev->dev_private;
3878         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3880         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3881         struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3882         enum pipe pipe = intel_crtc->pipe;
3883         static const i915_reg_t wm0_pipe_reg[] = {
3884                 [PIPE_A] = WM0_PIPEA_ILK,
3885                 [PIPE_B] = WM0_PIPEB_ILK,
3886                 [PIPE_C] = WM0_PIPEC_IVB,
3887         };
3888
3889         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3890         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3891                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3892
3893         active->pipe_enabled = intel_crtc->active;
3894
3895         if (active->pipe_enabled) {
3896                 u32 tmp = hw->wm_pipe[pipe];
3897
3898                 /*
3899                  * For active pipes LP0 watermark is marked as
3900                  * enabled, and LP1+ watermaks as disabled since
3901                  * we can't really reverse compute them in case
3902                  * multiple pipes are active.
3903                  */
3904                 active->wm[0].enable = true;
3905                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3906                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3907                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3908                 active->linetime = hw->wm_linetime[pipe];
3909         } else {
3910                 int level, max_level = ilk_wm_max_level(dev);
3911
3912                 /*
3913                  * For inactive pipes, all watermark levels
3914                  * should be marked as enabled but zeroed,
3915                  * which is what we'd compute them to.
3916                  */
3917                 for (level = 0; level <= max_level; level++)
3918                         active->wm[level].enable = true;
3919         }
3920
3921         intel_crtc->wm.active.ilk = *active;
3922 }
3923
3924 #define _FW_WM(value, plane) \
3925         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3926 #define _FW_WM_VLV(value, plane) \
3927         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3928
3929 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3930                                struct vlv_wm_values *wm)
3931 {
3932         enum pipe pipe;
3933         uint32_t tmp;
3934
3935         for_each_pipe(dev_priv, pipe) {
3936                 tmp = I915_READ(VLV_DDL(pipe));
3937
3938                 wm->ddl[pipe].primary =
3939                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3940                 wm->ddl[pipe].cursor =
3941                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3942                 wm->ddl[pipe].sprite[0] =
3943                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3944                 wm->ddl[pipe].sprite[1] =
3945                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3946         }
3947
3948         tmp = I915_READ(DSPFW1);
3949         wm->sr.plane = _FW_WM(tmp, SR);
3950         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3951         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3952         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3953
3954         tmp = I915_READ(DSPFW2);
3955         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3956         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3957         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3958
3959         tmp = I915_READ(DSPFW3);
3960         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3961
3962         if (IS_CHERRYVIEW(dev_priv)) {
3963                 tmp = I915_READ(DSPFW7_CHV);
3964                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3965                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3966
3967                 tmp = I915_READ(DSPFW8_CHV);
3968                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3969                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3970
3971                 tmp = I915_READ(DSPFW9_CHV);
3972                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3973                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3974
3975                 tmp = I915_READ(DSPHOWM);
3976                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3977                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3978                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3979                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3980                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3981                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3982                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3983                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3984                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3985                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3986         } else {
3987                 tmp = I915_READ(DSPFW7);
3988                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3989                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3990
3991                 tmp = I915_READ(DSPHOWM);
3992                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3993                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3994                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3995                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3996                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3997                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3998                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3999         }
4000 }
4001
4002 #undef _FW_WM
4003 #undef _FW_WM_VLV
4004
4005 void vlv_wm_get_hw_state(struct drm_device *dev)
4006 {
4007         struct drm_i915_private *dev_priv = to_i915(dev);
4008         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4009         struct intel_plane *plane;
4010         enum pipe pipe;
4011         u32 val;
4012
4013         vlv_read_wm_values(dev_priv, wm);
4014
4015         for_each_intel_plane(dev, plane) {
4016                 switch (plane->base.type) {
4017                         int sprite;
4018                 case DRM_PLANE_TYPE_CURSOR:
4019                         plane->wm.fifo_size = 63;
4020                         break;
4021                 case DRM_PLANE_TYPE_PRIMARY:
4022                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4023                         break;
4024                 case DRM_PLANE_TYPE_OVERLAY:
4025                         sprite = plane->plane;
4026                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4027                         break;
4028                 }
4029         }
4030
4031         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4032         wm->level = VLV_WM_LEVEL_PM2;
4033
4034         if (IS_CHERRYVIEW(dev_priv)) {
4035                 mutex_lock(&dev_priv->rps.hw_lock);
4036
4037                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4038                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4039                         wm->level = VLV_WM_LEVEL_PM5;
4040
4041                 /*
4042                  * If DDR DVFS is disabled in the BIOS, Punit
4043                  * will never ack the request. So if that happens
4044                  * assume we don't have to enable/disable DDR DVFS
4045                  * dynamically. To test that just set the REQ_ACK
4046                  * bit to poke the Punit, but don't change the
4047                  * HIGH/LOW bits so that we don't actually change
4048                  * the current state.
4049                  */
4050                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4051                 val |= FORCE_DDR_FREQ_REQ_ACK;
4052                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4053
4054                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4055                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4056                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4057                                       "assuming DDR DVFS is disabled\n");
4058                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4059                 } else {
4060                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4061                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4062                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4063                 }
4064
4065                 mutex_unlock(&dev_priv->rps.hw_lock);
4066         }
4067
4068         for_each_pipe(dev_priv, pipe)
4069                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4070                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4071                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4072
4073         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4074                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4075 }
4076
4077 void ilk_wm_get_hw_state(struct drm_device *dev)
4078 {
4079         struct drm_i915_private *dev_priv = dev->dev_private;
4080         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4081         struct drm_crtc *crtc;
4082
4083         for_each_crtc(dev, crtc)
4084                 ilk_pipe_wm_get_hw_state(crtc);
4085
4086         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4087         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4088         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4089
4090         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4091         if (INTEL_INFO(dev)->gen >= 7) {
4092                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4093                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4094         }
4095
4096         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4097                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4098                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4099         else if (IS_IVYBRIDGE(dev))
4100                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4101                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4102
4103         hw->enable_fbc_wm =
4104                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4105 }
4106
4107 /**
4108  * intel_update_watermarks - update FIFO watermark values based on current modes
4109  *
4110  * Calculate watermark values for the various WM regs based on current mode
4111  * and plane configuration.
4112  *
4113  * There are several cases to deal with here:
4114  *   - normal (i.e. non-self-refresh)
4115  *   - self-refresh (SR) mode
4116  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4117  *   - lines are small relative to FIFO size (buffer can hold more than 2
4118  *     lines), so need to account for TLB latency
4119  *
4120  *   The normal calculation is:
4121  *     watermark = dotclock * bytes per pixel * latency
4122  *   where latency is platform & configuration dependent (we assume pessimal
4123  *   values here).
4124  *
4125  *   The SR calculation is:
4126  *     watermark = (trunc(latency/line time)+1) * surface width *
4127  *       bytes per pixel
4128  *   where
4129  *     line time = htotal / dotclock
4130  *     surface width = hdisplay for normal plane and 64 for cursor
4131  *   and latency is assumed to be high, as above.
4132  *
4133  * The final value programmed to the register should always be rounded up,
4134  * and include an extra 2 entries to account for clock crossings.
4135  *
4136  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4137  * to set the non-SR watermarks to 8.
4138  */
4139 void intel_update_watermarks(struct drm_crtc *crtc)
4140 {
4141         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4142
4143         if (dev_priv->display.update_wm)
4144                 dev_priv->display.update_wm(crtc);
4145 }
4146
4147 /*
4148  * Lock protecting IPS related data structures
4149  */
4150 DEFINE_SPINLOCK(mchdev_lock);
4151
4152 /* Global for IPS driver to get at the current i915 device. Protected by
4153  * mchdev_lock. */
4154 static struct drm_i915_private *i915_mch_dev;
4155
4156 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4157 {
4158         struct drm_i915_private *dev_priv = dev->dev_private;
4159         u16 rgvswctl;
4160
4161         assert_spin_locked(&mchdev_lock);
4162
4163         rgvswctl = I915_READ16(MEMSWCTL);
4164         if (rgvswctl & MEMCTL_CMD_STS) {
4165                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4166                 return false; /* still busy with another command */
4167         }
4168
4169         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4170                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4171         I915_WRITE16(MEMSWCTL, rgvswctl);
4172         POSTING_READ16(MEMSWCTL);
4173
4174         rgvswctl |= MEMCTL_CMD_STS;
4175         I915_WRITE16(MEMSWCTL, rgvswctl);
4176
4177         return true;
4178 }
4179
4180 static void ironlake_enable_drps(struct drm_device *dev)
4181 {
4182         struct drm_i915_private *dev_priv = dev->dev_private;
4183         u32 rgvmodectl;
4184         u8 fmax, fmin, fstart, vstart;
4185
4186         spin_lock_irq(&mchdev_lock);
4187
4188         rgvmodectl = I915_READ(MEMMODECTL);
4189
4190         /* Enable temp reporting */
4191         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4192         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4193
4194         /* 100ms RC evaluation intervals */
4195         I915_WRITE(RCUPEI, 100000);
4196         I915_WRITE(RCDNEI, 100000);
4197
4198         /* Set max/min thresholds to 90ms and 80ms respectively */
4199         I915_WRITE(RCBMAXAVG, 90000);
4200         I915_WRITE(RCBMINAVG, 80000);
4201
4202         I915_WRITE(MEMIHYST, 1);
4203
4204         /* Set up min, max, and cur for interrupt handling */
4205         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4206         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4207         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4208                 MEMMODE_FSTART_SHIFT;
4209
4210         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4211                 PXVFREQ_PX_SHIFT;
4212
4213         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4214         dev_priv->ips.fstart = fstart;
4215
4216         dev_priv->ips.max_delay = fstart;
4217         dev_priv->ips.min_delay = fmin;
4218         dev_priv->ips.cur_delay = fstart;
4219
4220         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4221                          fmax, fmin, fstart);
4222
4223         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4224
4225         /*
4226          * Interrupts will be enabled in ironlake_irq_postinstall
4227          */
4228
4229         I915_WRITE(VIDSTART, vstart);
4230         POSTING_READ(VIDSTART);
4231
4232         rgvmodectl |= MEMMODE_SWMODE_EN;
4233         I915_WRITE(MEMMODECTL, rgvmodectl);
4234
4235         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4236                 DRM_ERROR("stuck trying to change perf mode\n");
4237         mdelay(1);
4238
4239         ironlake_set_drps(dev, fstart);
4240
4241         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4242                 I915_READ(DDREC) + I915_READ(CSIEC);
4243         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4244         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4245         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4246
4247         spin_unlock_irq(&mchdev_lock);
4248 }
4249
4250 static void ironlake_disable_drps(struct drm_device *dev)
4251 {
4252         struct drm_i915_private *dev_priv = dev->dev_private;
4253         u16 rgvswctl;
4254
4255         spin_lock_irq(&mchdev_lock);
4256
4257         rgvswctl = I915_READ16(MEMSWCTL);
4258
4259         /* Ack interrupts, disable EFC interrupt */
4260         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4261         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4262         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4263         I915_WRITE(DEIIR, DE_PCU_EVENT);
4264         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4265
4266         /* Go back to the starting frequency */
4267         ironlake_set_drps(dev, dev_priv->ips.fstart);
4268         mdelay(1);
4269         rgvswctl |= MEMCTL_CMD_STS;
4270         I915_WRITE(MEMSWCTL, rgvswctl);
4271         mdelay(1);
4272
4273         spin_unlock_irq(&mchdev_lock);
4274 }
4275
4276 /* There's a funny hw issue where the hw returns all 0 when reading from
4277  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4278  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4279  * all limits and the gpu stuck at whatever frequency it is at atm).
4280  */
4281 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4282 {
4283         u32 limits;
4284
4285         /* Only set the down limit when we've reached the lowest level to avoid
4286          * getting more interrupts, otherwise leave this clear. This prevents a
4287          * race in the hw when coming out of rc6: There's a tiny window where
4288          * the hw runs at the minimal clock before selecting the desired
4289          * frequency, if the down threshold expires in that window we will not
4290          * receive a down interrupt. */
4291         if (IS_GEN9(dev_priv->dev)) {
4292                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4293                 if (val <= dev_priv->rps.min_freq_softlimit)
4294                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4295         } else {
4296                 limits = dev_priv->rps.max_freq_softlimit << 24;
4297                 if (val <= dev_priv->rps.min_freq_softlimit)
4298                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4299         }
4300
4301         return limits;
4302 }
4303
4304 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4305 {
4306         int new_power;
4307         u32 threshold_up = 0, threshold_down = 0; /* in % */
4308         u32 ei_up = 0, ei_down = 0;
4309
4310         new_power = dev_priv->rps.power;
4311         switch (dev_priv->rps.power) {
4312         case LOW_POWER:
4313                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4314                         new_power = BETWEEN;
4315                 break;
4316
4317         case BETWEEN:
4318                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4319                         new_power = LOW_POWER;
4320                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4321                         new_power = HIGH_POWER;
4322                 break;
4323
4324         case HIGH_POWER:
4325                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4326                         new_power = BETWEEN;
4327                 break;
4328         }
4329         /* Max/min bins are special */
4330         if (val <= dev_priv->rps.min_freq_softlimit)
4331                 new_power = LOW_POWER;
4332         if (val >= dev_priv->rps.max_freq_softlimit)
4333                 new_power = HIGH_POWER;
4334         if (new_power == dev_priv->rps.power)
4335                 return;
4336
4337         /* Note the units here are not exactly 1us, but 1280ns. */
4338         switch (new_power) {
4339         case LOW_POWER:
4340                 /* Upclock if more than 95% busy over 16ms */
4341                 ei_up = 16000;
4342                 threshold_up = 95;
4343
4344                 /* Downclock if less than 85% busy over 32ms */
4345                 ei_down = 32000;
4346                 threshold_down = 85;
4347                 break;
4348
4349         case BETWEEN:
4350                 /* Upclock if more than 90% busy over 13ms */
4351                 ei_up = 13000;
4352                 threshold_up = 90;
4353
4354                 /* Downclock if less than 75% busy over 32ms */
4355                 ei_down = 32000;
4356                 threshold_down = 75;
4357                 break;
4358
4359         case HIGH_POWER:
4360                 /* Upclock if more than 85% busy over 10ms */
4361                 ei_up = 10000;
4362                 threshold_up = 85;
4363
4364                 /* Downclock if less than 60% busy over 32ms */
4365                 ei_down = 32000;
4366                 threshold_down = 60;
4367                 break;
4368         }
4369
4370         I915_WRITE(GEN6_RP_UP_EI,
4371                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4372         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4373                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4374
4375         I915_WRITE(GEN6_RP_DOWN_EI,
4376                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4377         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4378                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4379
4380          I915_WRITE(GEN6_RP_CONTROL,
4381                     GEN6_RP_MEDIA_TURBO |
4382                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4383                     GEN6_RP_MEDIA_IS_GFX |
4384                     GEN6_RP_ENABLE |
4385                     GEN6_RP_UP_BUSY_AVG |
4386                     GEN6_RP_DOWN_IDLE_AVG);
4387
4388         dev_priv->rps.power = new_power;
4389         dev_priv->rps.up_threshold = threshold_up;
4390         dev_priv->rps.down_threshold = threshold_down;
4391         dev_priv->rps.last_adj = 0;
4392 }
4393
4394 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4395 {
4396         u32 mask = 0;
4397
4398         if (val > dev_priv->rps.min_freq_softlimit)
4399                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4400         if (val < dev_priv->rps.max_freq_softlimit)
4401                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4402
4403         mask &= dev_priv->pm_rps_events;
4404
4405         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4406 }
4407
4408 /* gen6_set_rps is called to update the frequency request, but should also be
4409  * called when the range (min_delay and max_delay) is modified so that we can
4410  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4411 static void gen6_set_rps(struct drm_device *dev, u8 val)
4412 {
4413         struct drm_i915_private *dev_priv = dev->dev_private;
4414
4415         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4416         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4417                 return;
4418
4419         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4420         WARN_ON(val > dev_priv->rps.max_freq);
4421         WARN_ON(val < dev_priv->rps.min_freq);
4422
4423         /* min/max delay may still have been modified so be sure to
4424          * write the limits value.
4425          */
4426         if (val != dev_priv->rps.cur_freq) {
4427                 gen6_set_rps_thresholds(dev_priv, val);
4428
4429                 if (IS_GEN9(dev))
4430                         I915_WRITE(GEN6_RPNSWREQ,
4431                                    GEN9_FREQUENCY(val));
4432                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4433                         I915_WRITE(GEN6_RPNSWREQ,
4434                                    HSW_FREQUENCY(val));
4435                 else
4436                         I915_WRITE(GEN6_RPNSWREQ,
4437                                    GEN6_FREQUENCY(val) |
4438                                    GEN6_OFFSET(0) |
4439                                    GEN6_AGGRESSIVE_TURBO);
4440         }
4441
4442         /* Make sure we continue to get interrupts
4443          * until we hit the minimum or maximum frequencies.
4444          */
4445         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4446         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4447
4448         POSTING_READ(GEN6_RPNSWREQ);
4449
4450         dev_priv->rps.cur_freq = val;
4451         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4452 }
4453
4454 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4455 {
4456         struct drm_i915_private *dev_priv = dev->dev_private;
4457
4458         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4459         WARN_ON(val > dev_priv->rps.max_freq);
4460         WARN_ON(val < dev_priv->rps.min_freq);
4461
4462         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4463                       "Odd GPU freq value\n"))
4464                 val &= ~1;
4465
4466         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4467
4468         if (val != dev_priv->rps.cur_freq) {
4469                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4470                 if (!IS_CHERRYVIEW(dev_priv))
4471                         gen6_set_rps_thresholds(dev_priv, val);
4472         }
4473
4474         dev_priv->rps.cur_freq = val;
4475         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4476 }
4477
4478 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4479  *
4480  * * If Gfx is Idle, then
4481  * 1. Forcewake Media well.
4482  * 2. Request idle freq.
4483  * 3. Release Forcewake of Media well.
4484 */
4485 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4486 {
4487         u32 val = dev_priv->rps.idle_freq;
4488
4489         if (dev_priv->rps.cur_freq <= val)
4490                 return;
4491
4492         /* Wake up the media well, as that takes a lot less
4493          * power than the Render well. */
4494         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4495         valleyview_set_rps(dev_priv->dev, val);
4496         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4497 }
4498
4499 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4500 {
4501         mutex_lock(&dev_priv->rps.hw_lock);
4502         if (dev_priv->rps.enabled) {
4503                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4504                         gen6_rps_reset_ei(dev_priv);
4505                 I915_WRITE(GEN6_PMINTRMSK,
4506                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4507         }
4508         mutex_unlock(&dev_priv->rps.hw_lock);
4509 }
4510
4511 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4512 {
4513         struct drm_device *dev = dev_priv->dev;
4514
4515         mutex_lock(&dev_priv->rps.hw_lock);
4516         if (dev_priv->rps.enabled) {
4517                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4518                         vlv_set_rps_idle(dev_priv);
4519                 else
4520                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4521                 dev_priv->rps.last_adj = 0;
4522                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4523         }
4524         mutex_unlock(&dev_priv->rps.hw_lock);
4525
4526         spin_lock(&dev_priv->rps.client_lock);
4527         while (!list_empty(&dev_priv->rps.clients))
4528                 list_del_init(dev_priv->rps.clients.next);
4529         spin_unlock(&dev_priv->rps.client_lock);
4530 }
4531
4532 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4533                     struct intel_rps_client *rps,
4534                     unsigned long submitted)
4535 {
4536         /* This is intentionally racy! We peek at the state here, then
4537          * validate inside the RPS worker.
4538          */
4539         if (!(dev_priv->mm.busy &&
4540               dev_priv->rps.enabled &&
4541               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4542                 return;
4543
4544         /* Force a RPS boost (and don't count it against the client) if
4545          * the GPU is severely congested.
4546          */
4547         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4548                 rps = NULL;
4549
4550         spin_lock(&dev_priv->rps.client_lock);
4551         if (rps == NULL || list_empty(&rps->link)) {
4552                 spin_lock_irq(&dev_priv->irq_lock);
4553                 if (dev_priv->rps.interrupts_enabled) {
4554                         dev_priv->rps.client_boost = true;
4555                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4556                 }
4557                 spin_unlock_irq(&dev_priv->irq_lock);
4558
4559                 if (rps != NULL) {
4560                         list_add(&rps->link, &dev_priv->rps.clients);
4561                         rps->boosts++;
4562                 } else
4563                         dev_priv->rps.boosts++;
4564         }
4565         spin_unlock(&dev_priv->rps.client_lock);
4566 }
4567
4568 void intel_set_rps(struct drm_device *dev, u8 val)
4569 {
4570         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4571                 valleyview_set_rps(dev, val);
4572         else
4573                 gen6_set_rps(dev, val);
4574 }
4575
4576 static void gen9_disable_rps(struct drm_device *dev)
4577 {
4578         struct drm_i915_private *dev_priv = dev->dev_private;
4579
4580         I915_WRITE(GEN6_RC_CONTROL, 0);
4581         I915_WRITE(GEN9_PG_ENABLE, 0);
4582 }
4583
4584 static void gen6_disable_rps(struct drm_device *dev)
4585 {
4586         struct drm_i915_private *dev_priv = dev->dev_private;
4587
4588         I915_WRITE(GEN6_RC_CONTROL, 0);
4589         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4590 }
4591
4592 static void cherryview_disable_rps(struct drm_device *dev)
4593 {
4594         struct drm_i915_private *dev_priv = dev->dev_private;
4595
4596         I915_WRITE(GEN6_RC_CONTROL, 0);
4597 }
4598
4599 static void valleyview_disable_rps(struct drm_device *dev)
4600 {
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602
4603         /* we're doing forcewake before Disabling RC6,
4604          * This what the BIOS expects when going into suspend */
4605         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4606
4607         I915_WRITE(GEN6_RC_CONTROL, 0);
4608
4609         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4610 }
4611
4612 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4613 {
4614         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4615                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4616                         mode = GEN6_RC_CTL_RC6_ENABLE;
4617                 else
4618                         mode = 0;
4619         }
4620         if (HAS_RC6p(dev))
4621                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4622                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4623                               onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4624                               onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4625
4626         else
4627                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4628                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4629 }
4630
4631 static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4632 {
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         bool enable_rc6 = true;
4635         unsigned long rc6_ctx_base;
4636
4637         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4638                 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4639                 enable_rc6 = false;
4640         }
4641
4642         /*
4643          * The exact context size is not known for BXT, so assume a page size
4644          * for this check.
4645          */
4646         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4647         if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) &&
4648               (rc6_ctx_base + PAGE_SIZE <= dev_priv->gtt.stolen_reserved_base +
4649                                         dev_priv->gtt.stolen_reserved_size))) {
4650                 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4651                 enable_rc6 = false;
4652         }
4653
4654         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4655               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4656               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4657               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4658                 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4659                 enable_rc6 = false;
4660         }
4661
4662         if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4663                                             GEN6_RC_CTL_HW_ENABLE)) &&
4664             ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4665              !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4666                 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4667                 enable_rc6 = false;
4668         }
4669
4670         return enable_rc6;
4671 }
4672
4673 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4674 {
4675         /* No RC6 before Ironlake and code is gone for ilk. */
4676         if (INTEL_INFO(dev)->gen < 6)
4677                 return 0;
4678
4679         if (!enable_rc6)
4680                 return 0;
4681
4682         if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4683                 DRM_INFO("RC6 disabled by BIOS\n");
4684                 return 0;
4685         }
4686
4687         /* Respect the kernel parameter if it is set */
4688         if (enable_rc6 >= 0) {
4689                 int mask;
4690
4691                 if (HAS_RC6p(dev))
4692                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4693                                INTEL_RC6pp_ENABLE;
4694                 else
4695                         mask = INTEL_RC6_ENABLE;
4696
4697                 if ((enable_rc6 & mask) != enable_rc6)
4698                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4699                                       enable_rc6 & mask, enable_rc6, mask);
4700
4701                 return enable_rc6 & mask;
4702         }
4703
4704         if (IS_IVYBRIDGE(dev))
4705                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4706
4707         return INTEL_RC6_ENABLE;
4708 }
4709
4710 int intel_enable_rc6(const struct drm_device *dev)
4711 {
4712         return i915.enable_rc6;
4713 }
4714
4715 static void gen6_init_rps_frequencies(struct drm_device *dev)
4716 {
4717         struct drm_i915_private *dev_priv = dev->dev_private;
4718         uint32_t rp_state_cap;
4719         u32 ddcc_status = 0;
4720         int ret;
4721
4722         /* All of these values are in units of 50MHz */
4723         dev_priv->rps.cur_freq          = 0;
4724         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4725         if (IS_BROXTON(dev)) {
4726                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4727                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4728                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4729                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4730         } else {
4731                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4732                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4733                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4734                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4735         }
4736
4737         /* hw_max = RP0 until we check for overclocking */
4738         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4739
4740         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4741         if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4742             IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4743                 ret = sandybridge_pcode_read(dev_priv,
4744                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4745                                         &ddcc_status);
4746                 if (0 == ret)
4747                         dev_priv->rps.efficient_freq =
4748                                 clamp_t(u8,
4749                                         ((ddcc_status >> 8) & 0xff),
4750                                         dev_priv->rps.min_freq,
4751                                         dev_priv->rps.max_freq);
4752         }
4753
4754         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4755                 /* Store the frequency values in 16.66 MHZ units, which is
4756                    the natural hardware unit for SKL */
4757                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4758                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4759                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4760                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4761                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4762         }
4763
4764         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4765
4766         /* Preserve min/max settings in case of re-init */
4767         if (dev_priv->rps.max_freq_softlimit == 0)
4768                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4769
4770         if (dev_priv->rps.min_freq_softlimit == 0) {
4771                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4772                         dev_priv->rps.min_freq_softlimit =
4773                                 max_t(int, dev_priv->rps.efficient_freq,
4774                                       intel_freq_opcode(dev_priv, 450));
4775                 else
4776                         dev_priv->rps.min_freq_softlimit =
4777                                 dev_priv->rps.min_freq;
4778         }
4779 }
4780
4781 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4782 static void gen9_enable_rps(struct drm_device *dev)
4783 {
4784         struct drm_i915_private *dev_priv = dev->dev_private;
4785
4786         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4787
4788         gen6_init_rps_frequencies(dev);
4789
4790         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4791         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4792                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4793                 return;
4794         }
4795
4796         /* Program defaults and thresholds for RPS*/
4797         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4798                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4799
4800         /* 1 second timeout*/
4801         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4802                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4803
4804         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4805
4806         /* Leaning on the below call to gen6_set_rps to program/setup the
4807          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4808          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4809         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4810         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4811
4812         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4813 }
4814
4815 static void gen9_enable_rc6(struct drm_device *dev)
4816 {
4817         struct drm_i915_private *dev_priv = dev->dev_private;
4818         struct intel_engine_cs *ring;
4819         uint32_t rc6_mask = 0;
4820         int unused;
4821
4822         /* 1a: Software RC state - RC0 */
4823         I915_WRITE(GEN6_RC_STATE, 0);
4824
4825         /* 1b: Get forcewake during program sequence. Although the driver
4826          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4827         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4828
4829         /* 2a: Disable RC states. */
4830         I915_WRITE(GEN6_RC_CONTROL, 0);
4831
4832         /* 2b: Program RC6 thresholds.*/
4833
4834         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4835         if (IS_SKYLAKE(dev))
4836                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4837         else
4838                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4839         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4840         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4841         for_each_ring(ring, dev_priv, unused)
4842                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4843
4844         if (HAS_GUC_UCODE(dev))
4845                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4846
4847         I915_WRITE(GEN6_RC_SLEEP, 0);
4848
4849         /* 2c: Program Coarse Power Gating Policies. */
4850         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4851         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4852
4853         /* 3a: Enable RC6 */
4854         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4855                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4856         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4857         /* WaRsUseTimeoutMode */
4858         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4859             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4860                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4861                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4862                            GEN7_RC_CTL_TO_MODE |
4863                            rc6_mask);
4864         } else {
4865                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4866                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4867                            GEN6_RC_CTL_EI_MODE(1) |
4868                            rc6_mask);
4869         }
4870
4871         /*
4872          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4873          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4874          */
4875         if (NEEDS_WaRsDisableCoarsePowerGating(dev))
4876                 I915_WRITE(GEN9_PG_ENABLE, 0);
4877         else
4878                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4879                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4880
4881         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4882
4883 }
4884
4885 static void gen8_enable_rps(struct drm_device *dev)
4886 {
4887         struct drm_i915_private *dev_priv = dev->dev_private;
4888         struct intel_engine_cs *ring;
4889         uint32_t rc6_mask = 0;
4890         int unused;
4891
4892         /* 1a: Software RC state - RC0 */
4893         I915_WRITE(GEN6_RC_STATE, 0);
4894
4895         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4896          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4897         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4898
4899         /* 2a: Disable RC states. */
4900         I915_WRITE(GEN6_RC_CONTROL, 0);
4901
4902         /* Initialize rps frequencies */
4903         gen6_init_rps_frequencies(dev);
4904
4905         /* 2b: Program RC6 thresholds.*/
4906         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4907         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4908         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4909         for_each_ring(ring, dev_priv, unused)
4910                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4911         I915_WRITE(GEN6_RC_SLEEP, 0);
4912         if (IS_BROADWELL(dev))
4913                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4914         else
4915                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4916
4917         /* 3: Enable RC6 */
4918         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4919                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4920         intel_print_rc6_info(dev, rc6_mask);
4921         if (IS_BROADWELL(dev))
4922                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4923                                 GEN7_RC_CTL_TO_MODE |
4924                                 rc6_mask);
4925         else
4926                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4927                                 GEN6_RC_CTL_EI_MODE(1) |
4928                                 rc6_mask);
4929
4930         /* 4 Program defaults and thresholds for RPS*/
4931         I915_WRITE(GEN6_RPNSWREQ,
4932                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4933         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4934                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4935         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4936         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4937
4938         /* Docs recommend 900MHz, and 300 MHz respectively */
4939         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4940                    dev_priv->rps.max_freq_softlimit << 24 |
4941                    dev_priv->rps.min_freq_softlimit << 16);
4942
4943         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4944         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4945         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4946         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4947
4948         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4949
4950         /* 5: Enable RPS */
4951         I915_WRITE(GEN6_RP_CONTROL,
4952                    GEN6_RP_MEDIA_TURBO |
4953                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4954                    GEN6_RP_MEDIA_IS_GFX |
4955                    GEN6_RP_ENABLE |
4956                    GEN6_RP_UP_BUSY_AVG |
4957                    GEN6_RP_DOWN_IDLE_AVG);
4958
4959         /* 6: Ring frequency + overclocking (our driver does this later */
4960
4961         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4962         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4963
4964         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4965 }
4966
4967 static void gen6_enable_rps(struct drm_device *dev)
4968 {
4969         struct drm_i915_private *dev_priv = dev->dev_private;
4970         struct intel_engine_cs *ring;
4971         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4972         u32 gtfifodbg;
4973         int rc6_mode;
4974         int i, ret;
4975
4976         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4977
4978         /* Here begins a magic sequence of register writes to enable
4979          * auto-downclocking.
4980          *
4981          * Perhaps there might be some value in exposing these to
4982          * userspace...
4983          */
4984         I915_WRITE(GEN6_RC_STATE, 0);
4985
4986         /* Clear the DBG now so we don't confuse earlier errors */
4987         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4988                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4989                 I915_WRITE(GTFIFODBG, gtfifodbg);
4990         }
4991
4992         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4993
4994         /* Initialize rps frequencies */
4995         gen6_init_rps_frequencies(dev);
4996
4997         /* disable the counters and set deterministic thresholds */
4998         I915_WRITE(GEN6_RC_CONTROL, 0);
4999
5000         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5001         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5002         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5003         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5004         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5005
5006         for_each_ring(ring, dev_priv, i)
5007                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5008
5009         I915_WRITE(GEN6_RC_SLEEP, 0);
5010         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5011         if (IS_IVYBRIDGE(dev))
5012                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5013         else
5014                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5015         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5016         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5017
5018         /* Check if we are enabling RC6 */
5019         rc6_mode = intel_enable_rc6(dev_priv->dev);
5020         if (rc6_mode & INTEL_RC6_ENABLE)
5021                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5022
5023         /* We don't use those on Haswell */
5024         if (!IS_HASWELL(dev)) {
5025                 if (rc6_mode & INTEL_RC6p_ENABLE)
5026                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5027
5028                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5029                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5030         }
5031
5032         intel_print_rc6_info(dev, rc6_mask);
5033
5034         I915_WRITE(GEN6_RC_CONTROL,
5035                    rc6_mask |
5036                    GEN6_RC_CTL_EI_MODE(1) |
5037                    GEN6_RC_CTL_HW_ENABLE);
5038
5039         /* Power down if completely idle for over 50ms */
5040         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5041         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5042
5043         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5044         if (ret)
5045                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5046
5047         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5048         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5049                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5050                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5051                                  (pcu_mbox & 0xff) * 50);
5052                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5053         }
5054
5055         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5056         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5057
5058         rc6vids = 0;
5059         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5060         if (IS_GEN6(dev) && ret) {
5061                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5062         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5063                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5064                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5065                 rc6vids &= 0xffff00;
5066                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5067                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5068                 if (ret)
5069                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5070         }
5071
5072         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5073 }
5074
5075 static void __gen6_update_ring_freq(struct drm_device *dev)
5076 {
5077         struct drm_i915_private *dev_priv = dev->dev_private;
5078         int min_freq = 15;
5079         unsigned int gpu_freq;
5080         unsigned int max_ia_freq, min_ring_freq;
5081         unsigned int max_gpu_freq, min_gpu_freq;
5082         int scaling_factor = 180;
5083         struct cpufreq_policy *policy;
5084
5085         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5086
5087         policy = cpufreq_cpu_get(0);
5088         if (policy) {
5089                 max_ia_freq = policy->cpuinfo.max_freq;
5090                 cpufreq_cpu_put(policy);
5091         } else {
5092                 /*
5093                  * Default to measured freq if none found, PCU will ensure we
5094                  * don't go over
5095                  */
5096                 max_ia_freq = tsc_khz;
5097         }
5098
5099         /* Convert from kHz to MHz */
5100         max_ia_freq /= 1000;
5101
5102         min_ring_freq = I915_READ(DCLK) & 0xf;
5103         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5104         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5105
5106         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5107                 /* Convert GT frequency to 50 HZ units */
5108                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5109                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5110         } else {
5111                 min_gpu_freq = dev_priv->rps.min_freq;
5112                 max_gpu_freq = dev_priv->rps.max_freq;
5113         }
5114
5115         /*
5116          * For each potential GPU frequency, load a ring frequency we'd like
5117          * to use for memory access.  We do this by specifying the IA frequency
5118          * the PCU should use as a reference to determine the ring frequency.
5119          */
5120         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5121                 int diff = max_gpu_freq - gpu_freq;
5122                 unsigned int ia_freq = 0, ring_freq = 0;
5123
5124                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5125                         /*
5126                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5127                          * No floor required for ring frequency on SKL.
5128                          */
5129                         ring_freq = gpu_freq;
5130                 } else if (INTEL_INFO(dev)->gen >= 8) {
5131                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5132                         ring_freq = max(min_ring_freq, gpu_freq);
5133                 } else if (IS_HASWELL(dev)) {
5134                         ring_freq = mult_frac(gpu_freq, 5, 4);
5135                         ring_freq = max(min_ring_freq, ring_freq);
5136                         /* leave ia_freq as the default, chosen by cpufreq */
5137                 } else {
5138                         /* On older processors, there is no separate ring
5139                          * clock domain, so in order to boost the bandwidth
5140                          * of the ring, we need to upclock the CPU (ia_freq).
5141                          *
5142                          * For GPU frequencies less than 750MHz,
5143                          * just use the lowest ring freq.
5144                          */
5145                         if (gpu_freq < min_freq)
5146                                 ia_freq = 800;
5147                         else
5148                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5149                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5150                 }
5151
5152                 sandybridge_pcode_write(dev_priv,
5153                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5154                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5155                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5156                                         gpu_freq);
5157         }
5158 }
5159
5160 void gen6_update_ring_freq(struct drm_device *dev)
5161 {
5162         struct drm_i915_private *dev_priv = dev->dev_private;
5163
5164         if (!HAS_CORE_RING_FREQ(dev))
5165                 return;
5166
5167         mutex_lock(&dev_priv->rps.hw_lock);
5168         __gen6_update_ring_freq(dev);
5169         mutex_unlock(&dev_priv->rps.hw_lock);
5170 }
5171
5172 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5173 {
5174         struct drm_device *dev = dev_priv->dev;
5175         u32 val, rp0;
5176
5177         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5178
5179         switch (INTEL_INFO(dev)->eu_total) {
5180         case 8:
5181                 /* (2 * 4) config */
5182                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5183                 break;
5184         case 12:
5185                 /* (2 * 6) config */
5186                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5187                 break;
5188         case 16:
5189                 /* (2 * 8) config */
5190         default:
5191                 /* Setting (2 * 8) Min RP0 for any other combination */
5192                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5193                 break;
5194         }
5195
5196         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5197
5198         return rp0;
5199 }
5200
5201 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5202 {
5203         u32 val, rpe;
5204
5205         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5206         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5207
5208         return rpe;
5209 }
5210
5211 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5212 {
5213         u32 val, rp1;
5214
5215         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5216         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5217
5218         return rp1;
5219 }
5220
5221 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5222 {
5223         u32 val, rp1;
5224
5225         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5226
5227         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5228
5229         return rp1;
5230 }
5231
5232 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5233 {
5234         u32 val, rp0;
5235
5236         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5237
5238         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5239         /* Clamp to max */
5240         rp0 = min_t(u32, rp0, 0xea);
5241
5242         return rp0;
5243 }
5244
5245 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5246 {
5247         u32 val, rpe;
5248
5249         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5250         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5251         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5252         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5253
5254         return rpe;
5255 }
5256
5257 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5258 {
5259         u32 val;
5260
5261         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5262         /*
5263          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5264          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5265          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5266          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5267          * to make sure it matches what Punit accepts.
5268          */
5269         return max_t(u32, val, 0xc0);
5270 }
5271
5272 /* Check that the pctx buffer wasn't move under us. */
5273 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5274 {
5275         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5276
5277         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5278                              dev_priv->vlv_pctx->stolen->start);
5279 }
5280
5281
5282 /* Check that the pcbr address is not empty. */
5283 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5284 {
5285         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5286
5287         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5288 }
5289
5290 static void cherryview_setup_pctx(struct drm_device *dev)
5291 {
5292         struct drm_i915_private *dev_priv = dev->dev_private;
5293         unsigned long pctx_paddr, paddr;
5294         struct i915_gtt *gtt = &dev_priv->gtt;
5295         u32 pcbr;
5296         int pctx_size = 32*1024;
5297
5298         pcbr = I915_READ(VLV_PCBR);
5299         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5300                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5301                 paddr = (dev_priv->mm.stolen_base +
5302                          (gtt->stolen_size - pctx_size));
5303
5304                 pctx_paddr = (paddr & (~4095));
5305                 I915_WRITE(VLV_PCBR, pctx_paddr);
5306         }
5307
5308         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5309 }
5310
5311 static void valleyview_setup_pctx(struct drm_device *dev)
5312 {
5313         struct drm_i915_private *dev_priv = dev->dev_private;
5314         struct drm_i915_gem_object *pctx;
5315         unsigned long pctx_paddr;
5316         u32 pcbr;
5317         int pctx_size = 24*1024;
5318
5319         mutex_lock(&dev->struct_mutex);
5320
5321         pcbr = I915_READ(VLV_PCBR);
5322         if (pcbr) {
5323                 /* BIOS set it up already, grab the pre-alloc'd space */
5324                 int pcbr_offset;
5325
5326                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5327                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5328                                                                       pcbr_offset,
5329                                                                       I915_GTT_OFFSET_NONE,
5330                                                                       pctx_size);
5331                 goto out;
5332         }
5333
5334         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5335
5336         /*
5337          * From the Gunit register HAS:
5338          * The Gfx driver is expected to program this register and ensure
5339          * proper allocation within Gfx stolen memory.  For example, this
5340          * register should be programmed such than the PCBR range does not
5341          * overlap with other ranges, such as the frame buffer, protected
5342          * memory, or any other relevant ranges.
5343          */
5344         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5345         if (!pctx) {
5346                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5347                 goto out;
5348         }
5349
5350         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5351         I915_WRITE(VLV_PCBR, pctx_paddr);
5352
5353 out:
5354         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5355         dev_priv->vlv_pctx = pctx;
5356         mutex_unlock(&dev->struct_mutex);
5357 }
5358
5359 static void valleyview_cleanup_pctx(struct drm_device *dev)
5360 {
5361         struct drm_i915_private *dev_priv = dev->dev_private;
5362
5363         if (WARN_ON(!dev_priv->vlv_pctx))
5364                 return;
5365
5366         drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5367         dev_priv->vlv_pctx = NULL;
5368 }
5369
5370 static void valleyview_init_gt_powersave(struct drm_device *dev)
5371 {
5372         struct drm_i915_private *dev_priv = dev->dev_private;
5373         u32 val;
5374
5375         valleyview_setup_pctx(dev);
5376
5377         mutex_lock(&dev_priv->rps.hw_lock);
5378
5379         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5380         switch ((val >> 6) & 3) {
5381         case 0:
5382         case 1:
5383                 dev_priv->mem_freq = 800;
5384                 break;
5385         case 2:
5386                 dev_priv->mem_freq = 1066;
5387                 break;
5388         case 3:
5389                 dev_priv->mem_freq = 1333;
5390                 break;
5391         }
5392         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5393
5394         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5395         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5396         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5397                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5398                          dev_priv->rps.max_freq);
5399
5400         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5401         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5402                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5403                          dev_priv->rps.efficient_freq);
5404
5405         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5406         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5407                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5408                          dev_priv->rps.rp1_freq);
5409
5410         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5411         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5412                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5413                          dev_priv->rps.min_freq);
5414
5415         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5416
5417         /* Preserve min/max settings in case of re-init */
5418         if (dev_priv->rps.max_freq_softlimit == 0)
5419                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5420
5421         if (dev_priv->rps.min_freq_softlimit == 0)
5422                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5423
5424         mutex_unlock(&dev_priv->rps.hw_lock);
5425 }
5426
5427 static void cherryview_init_gt_powersave(struct drm_device *dev)
5428 {
5429         struct drm_i915_private *dev_priv = dev->dev_private;
5430         u32 val;
5431
5432         cherryview_setup_pctx(dev);
5433
5434         mutex_lock(&dev_priv->rps.hw_lock);
5435
5436         mutex_lock(&dev_priv->sb_lock);
5437         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5438         mutex_unlock(&dev_priv->sb_lock);
5439
5440         switch ((val >> 2) & 0x7) {
5441         case 3:
5442                 dev_priv->mem_freq = 2000;
5443                 break;
5444         default:
5445                 dev_priv->mem_freq = 1600;
5446                 break;
5447         }
5448         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5449
5450         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5451         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5452         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5453                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5454                          dev_priv->rps.max_freq);
5455
5456         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5457         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5458                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5459                          dev_priv->rps.efficient_freq);
5460
5461         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5462         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5463                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5464                          dev_priv->rps.rp1_freq);
5465
5466         /* PUnit validated range is only [RPe, RP0] */
5467         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5468         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5469                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5470                          dev_priv->rps.min_freq);
5471
5472         WARN_ONCE((dev_priv->rps.max_freq |
5473                    dev_priv->rps.efficient_freq |
5474                    dev_priv->rps.rp1_freq |
5475                    dev_priv->rps.min_freq) & 1,
5476                   "Odd GPU freq values\n");
5477
5478         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5479
5480         /* Preserve min/max settings in case of re-init */
5481         if (dev_priv->rps.max_freq_softlimit == 0)
5482                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5483
5484         if (dev_priv->rps.min_freq_softlimit == 0)
5485                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5486
5487         mutex_unlock(&dev_priv->rps.hw_lock);
5488 }
5489
5490 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5491 {
5492         valleyview_cleanup_pctx(dev);
5493 }
5494
5495 static void cherryview_enable_rps(struct drm_device *dev)
5496 {
5497         struct drm_i915_private *dev_priv = dev->dev_private;
5498         struct intel_engine_cs *ring;
5499         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5500         int i;
5501
5502         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5503
5504         gtfifodbg = I915_READ(GTFIFODBG);
5505         if (gtfifodbg) {
5506                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5507                                  gtfifodbg);
5508                 I915_WRITE(GTFIFODBG, gtfifodbg);
5509         }
5510
5511         cherryview_check_pctx(dev_priv);
5512
5513         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5514          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5515         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5516
5517         /*  Disable RC states. */
5518         I915_WRITE(GEN6_RC_CONTROL, 0);
5519
5520         /* 2a: Program RC6 thresholds.*/
5521         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5522         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5523         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5524
5525         for_each_ring(ring, dev_priv, i)
5526                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5527         I915_WRITE(GEN6_RC_SLEEP, 0);
5528
5529         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5530         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5531
5532         /* allows RC6 residency counter to work */
5533         I915_WRITE(VLV_COUNTER_CONTROL,
5534                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5535                                       VLV_MEDIA_RC6_COUNT_EN |
5536                                       VLV_RENDER_RC6_COUNT_EN));
5537
5538         /* For now we assume BIOS is allocating and populating the PCBR  */
5539         pcbr = I915_READ(VLV_PCBR);
5540
5541         /* 3: Enable RC6 */
5542         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5543                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5544                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5545
5546         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5547
5548         /* 4 Program defaults and thresholds for RPS*/
5549         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5550         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5551         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5552         I915_WRITE(GEN6_RP_UP_EI, 66000);
5553         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5554
5555         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5556
5557         /* 5: Enable RPS */
5558         I915_WRITE(GEN6_RP_CONTROL,
5559                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5560                    GEN6_RP_MEDIA_IS_GFX |
5561                    GEN6_RP_ENABLE |
5562                    GEN6_RP_UP_BUSY_AVG |
5563                    GEN6_RP_DOWN_IDLE_AVG);
5564
5565         /* Setting Fixed Bias */
5566         val = VLV_OVERRIDE_EN |
5567                   VLV_SOC_TDP_EN |
5568                   CHV_BIAS_CPU_50_SOC_50;
5569         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5570
5571         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5572
5573         /* RPS code assumes GPLL is used */
5574         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5575
5576         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5577         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5578
5579         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5580         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5581                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5582                          dev_priv->rps.cur_freq);
5583
5584         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5585                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5586                          dev_priv->rps.efficient_freq);
5587
5588         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5589
5590         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5591 }
5592
5593 static void valleyview_enable_rps(struct drm_device *dev)
5594 {
5595         struct drm_i915_private *dev_priv = dev->dev_private;
5596         struct intel_engine_cs *ring;
5597         u32 gtfifodbg, val, rc6_mode = 0;
5598         int i;
5599
5600         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5601
5602         valleyview_check_pctx(dev_priv);
5603
5604         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5605                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5606                                  gtfifodbg);
5607                 I915_WRITE(GTFIFODBG, gtfifodbg);
5608         }
5609
5610         /* If VLV, Forcewake all wells, else re-direct to regular path */
5611         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5612
5613         /*  Disable RC states. */
5614         I915_WRITE(GEN6_RC_CONTROL, 0);
5615
5616         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5617         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5618         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5619         I915_WRITE(GEN6_RP_UP_EI, 66000);
5620         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5621
5622         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5623
5624         I915_WRITE(GEN6_RP_CONTROL,
5625                    GEN6_RP_MEDIA_TURBO |
5626                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5627                    GEN6_RP_MEDIA_IS_GFX |
5628                    GEN6_RP_ENABLE |
5629                    GEN6_RP_UP_BUSY_AVG |
5630                    GEN6_RP_DOWN_IDLE_CONT);
5631
5632         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5633         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5634         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5635
5636         for_each_ring(ring, dev_priv, i)
5637                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5638
5639         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5640
5641         /* allows RC6 residency counter to work */
5642         I915_WRITE(VLV_COUNTER_CONTROL,
5643                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5644                                       VLV_RENDER_RC0_COUNT_EN |
5645                                       VLV_MEDIA_RC6_COUNT_EN |
5646                                       VLV_RENDER_RC6_COUNT_EN));
5647
5648         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5649                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5650
5651         intel_print_rc6_info(dev, rc6_mode);
5652
5653         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5654
5655         /* Setting Fixed Bias */
5656         val = VLV_OVERRIDE_EN |
5657                   VLV_SOC_TDP_EN |
5658                   VLV_BIAS_CPU_125_SOC_875;
5659         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5660
5661         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5662
5663         /* RPS code assumes GPLL is used */
5664         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5665
5666         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5667         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5668
5669         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5670         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5671                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5672                          dev_priv->rps.cur_freq);
5673
5674         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5675                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5676                          dev_priv->rps.efficient_freq);
5677
5678         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5679
5680         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5681 }
5682
5683 static unsigned long intel_pxfreq(u32 vidfreq)
5684 {
5685         unsigned long freq;
5686         int div = (vidfreq & 0x3f0000) >> 16;
5687         int post = (vidfreq & 0x3000) >> 12;
5688         int pre = (vidfreq & 0x7);
5689
5690         if (!pre)
5691                 return 0;
5692
5693         freq = ((div * 133333) / ((1<<post) * pre));
5694
5695         return freq;
5696 }
5697
5698 static const struct cparams {
5699         u16 i;
5700         u16 t;
5701         u16 m;
5702         u16 c;
5703 } cparams[] = {
5704         { 1, 1333, 301, 28664 },
5705         { 1, 1066, 294, 24460 },
5706         { 1, 800, 294, 25192 },
5707         { 0, 1333, 276, 27605 },
5708         { 0, 1066, 276, 27605 },
5709         { 0, 800, 231, 23784 },
5710 };
5711
5712 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5713 {
5714         u64 total_count, diff, ret;
5715         u32 count1, count2, count3, m = 0, c = 0;
5716         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5717         int i;
5718
5719         assert_spin_locked(&mchdev_lock);
5720
5721         diff1 = now - dev_priv->ips.last_time1;
5722
5723         /* Prevent division-by-zero if we are asking too fast.
5724          * Also, we don't get interesting results if we are polling
5725          * faster than once in 10ms, so just return the saved value
5726          * in such cases.
5727          */
5728         if (diff1 <= 10)
5729                 return dev_priv->ips.chipset_power;
5730
5731         count1 = I915_READ(DMIEC);
5732         count2 = I915_READ(DDREC);
5733         count3 = I915_READ(CSIEC);
5734
5735         total_count = count1 + count2 + count3;
5736
5737         /* FIXME: handle per-counter overflow */
5738         if (total_count < dev_priv->ips.last_count1) {
5739                 diff = ~0UL - dev_priv->ips.last_count1;
5740                 diff += total_count;
5741         } else {
5742                 diff = total_count - dev_priv->ips.last_count1;
5743         }
5744
5745         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5746                 if (cparams[i].i == dev_priv->ips.c_m &&
5747                     cparams[i].t == dev_priv->ips.r_t) {
5748                         m = cparams[i].m;
5749                         c = cparams[i].c;
5750                         break;
5751                 }
5752         }
5753
5754         diff = div_u64(diff, diff1);
5755         ret = ((m * diff) + c);
5756         ret = div_u64(ret, 10);
5757
5758         dev_priv->ips.last_count1 = total_count;
5759         dev_priv->ips.last_time1 = now;
5760
5761         dev_priv->ips.chipset_power = ret;
5762
5763         return ret;
5764 }
5765
5766 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5767 {
5768         struct drm_device *dev = dev_priv->dev;
5769         unsigned long val;
5770
5771         if (INTEL_INFO(dev)->gen != 5)
5772                 return 0;
5773
5774         spin_lock_irq(&mchdev_lock);
5775
5776         val = __i915_chipset_val(dev_priv);
5777
5778         spin_unlock_irq(&mchdev_lock);
5779
5780         return val;
5781 }
5782
5783 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5784 {
5785         unsigned long m, x, b;
5786         u32 tsfs;
5787
5788         tsfs = I915_READ(TSFS);
5789
5790         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5791         x = I915_READ8(TR1);
5792
5793         b = tsfs & TSFS_INTR_MASK;
5794
5795         return ((m * x) / 127) - b;
5796 }
5797
5798 static int _pxvid_to_vd(u8 pxvid)
5799 {
5800         if (pxvid == 0)
5801                 return 0;
5802
5803         if (pxvid >= 8 && pxvid < 31)
5804                 pxvid = 31;
5805
5806         return (pxvid + 2) * 125;
5807 }
5808
5809 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5810 {
5811         struct drm_device *dev = dev_priv->dev;
5812         const int vd = _pxvid_to_vd(pxvid);
5813         const int vm = vd - 1125;
5814
5815         if (INTEL_INFO(dev)->is_mobile)
5816                 return vm > 0 ? vm : 0;
5817
5818         return vd;
5819 }
5820
5821 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5822 {
5823         u64 now, diff, diffms;
5824         u32 count;
5825
5826         assert_spin_locked(&mchdev_lock);
5827
5828         now = ktime_get_raw_ns();
5829         diffms = now - dev_priv->ips.last_time2;
5830         do_div(diffms, NSEC_PER_MSEC);
5831
5832         /* Don't divide by 0 */
5833         if (!diffms)
5834                 return;
5835
5836         count = I915_READ(GFXEC);
5837
5838         if (count < dev_priv->ips.last_count2) {
5839                 diff = ~0UL - dev_priv->ips.last_count2;
5840                 diff += count;
5841         } else {
5842                 diff = count - dev_priv->ips.last_count2;
5843         }
5844
5845         dev_priv->ips.last_count2 = count;
5846         dev_priv->ips.last_time2 = now;
5847
5848         /* More magic constants... */
5849         diff = diff * 1181;
5850         diff = div_u64(diff, diffms * 10);
5851         dev_priv->ips.gfx_power = diff;
5852 }
5853
5854 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5855 {
5856         struct drm_device *dev = dev_priv->dev;
5857
5858         if (INTEL_INFO(dev)->gen != 5)
5859                 return;
5860
5861         spin_lock_irq(&mchdev_lock);
5862
5863         __i915_update_gfx_val(dev_priv);
5864
5865         spin_unlock_irq(&mchdev_lock);
5866 }
5867
5868 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5869 {
5870         unsigned long t, corr, state1, corr2, state2;
5871         u32 pxvid, ext_v;
5872
5873         assert_spin_locked(&mchdev_lock);
5874
5875         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5876         pxvid = (pxvid >> 24) & 0x7f;
5877         ext_v = pvid_to_extvid(dev_priv, pxvid);
5878
5879         state1 = ext_v;
5880
5881         t = i915_mch_val(dev_priv);
5882
5883         /* Revel in the empirically derived constants */
5884
5885         /* Correction factor in 1/100000 units */
5886         if (t > 80)
5887                 corr = ((t * 2349) + 135940);
5888         else if (t >= 50)
5889                 corr = ((t * 964) + 29317);
5890         else /* < 50 */
5891                 corr = ((t * 301) + 1004);
5892
5893         corr = corr * ((150142 * state1) / 10000 - 78642);
5894         corr /= 100000;
5895         corr2 = (corr * dev_priv->ips.corr);
5896
5897         state2 = (corr2 * state1) / 10000;
5898         state2 /= 100; /* convert to mW */
5899
5900         __i915_update_gfx_val(dev_priv);
5901
5902         return dev_priv->ips.gfx_power + state2;
5903 }
5904
5905 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5906 {
5907         struct drm_device *dev = dev_priv->dev;
5908         unsigned long val;
5909
5910         if (INTEL_INFO(dev)->gen != 5)
5911                 return 0;
5912
5913         spin_lock_irq(&mchdev_lock);
5914
5915         val = __i915_gfx_val(dev_priv);
5916
5917         spin_unlock_irq(&mchdev_lock);
5918
5919         return val;
5920 }
5921
5922 /**
5923  * i915_read_mch_val - return value for IPS use
5924  *
5925  * Calculate and return a value for the IPS driver to use when deciding whether
5926  * we have thermal and power headroom to increase CPU or GPU power budget.
5927  */
5928 unsigned long i915_read_mch_val(void)
5929 {
5930         struct drm_i915_private *dev_priv;
5931         unsigned long chipset_val, graphics_val, ret = 0;
5932
5933         spin_lock_irq(&mchdev_lock);
5934         if (!i915_mch_dev)
5935                 goto out_unlock;
5936         dev_priv = i915_mch_dev;
5937
5938         chipset_val = __i915_chipset_val(dev_priv);
5939         graphics_val = __i915_gfx_val(dev_priv);
5940
5941         ret = chipset_val + graphics_val;
5942
5943 out_unlock:
5944         spin_unlock_irq(&mchdev_lock);
5945
5946         return ret;
5947 }
5948 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5949
5950 /**
5951  * i915_gpu_raise - raise GPU frequency limit
5952  *
5953  * Raise the limit; IPS indicates we have thermal headroom.
5954  */
5955 bool i915_gpu_raise(void)
5956 {
5957         struct drm_i915_private *dev_priv;
5958         bool ret = true;
5959
5960         spin_lock_irq(&mchdev_lock);
5961         if (!i915_mch_dev) {
5962                 ret = false;
5963                 goto out_unlock;
5964         }
5965         dev_priv = i915_mch_dev;
5966
5967         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5968                 dev_priv->ips.max_delay--;
5969
5970 out_unlock:
5971         spin_unlock_irq(&mchdev_lock);
5972
5973         return ret;
5974 }
5975 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5976
5977 /**
5978  * i915_gpu_lower - lower GPU frequency limit
5979  *
5980  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5981  * frequency maximum.
5982  */
5983 bool i915_gpu_lower(void)
5984 {
5985         struct drm_i915_private *dev_priv;
5986         bool ret = true;
5987
5988         spin_lock_irq(&mchdev_lock);
5989         if (!i915_mch_dev) {
5990                 ret = false;
5991                 goto out_unlock;
5992         }
5993         dev_priv = i915_mch_dev;
5994
5995         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5996                 dev_priv->ips.max_delay++;
5997
5998 out_unlock:
5999         spin_unlock_irq(&mchdev_lock);
6000
6001         return ret;
6002 }
6003 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6004
6005 /**
6006  * i915_gpu_busy - indicate GPU business to IPS
6007  *
6008  * Tell the IPS driver whether or not the GPU is busy.
6009  */
6010 bool i915_gpu_busy(void)
6011 {
6012         struct drm_i915_private *dev_priv;
6013         struct intel_engine_cs *ring;
6014         bool ret = false;
6015         int i;
6016
6017         spin_lock_irq(&mchdev_lock);
6018         if (!i915_mch_dev)
6019                 goto out_unlock;
6020         dev_priv = i915_mch_dev;
6021
6022         for_each_ring(ring, dev_priv, i)
6023                 ret |= !list_empty(&ring->request_list);
6024
6025 out_unlock:
6026         spin_unlock_irq(&mchdev_lock);
6027
6028         return ret;
6029 }
6030 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6031
6032 /**
6033  * i915_gpu_turbo_disable - disable graphics turbo
6034  *
6035  * Disable graphics turbo by resetting the max frequency and setting the
6036  * current frequency to the default.
6037  */
6038 bool i915_gpu_turbo_disable(void)
6039 {
6040         struct drm_i915_private *dev_priv;
6041         bool ret = true;
6042
6043         spin_lock_irq(&mchdev_lock);
6044         if (!i915_mch_dev) {
6045                 ret = false;
6046                 goto out_unlock;
6047         }
6048         dev_priv = i915_mch_dev;
6049
6050         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6051
6052         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6053                 ret = false;
6054
6055 out_unlock:
6056         spin_unlock_irq(&mchdev_lock);
6057
6058         return ret;
6059 }
6060 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6061
6062 /**
6063  * Tells the intel_ips driver that the i915 driver is now loaded, if
6064  * IPS got loaded first.
6065  *
6066  * This awkward dance is so that neither module has to depend on the
6067  * other in order for IPS to do the appropriate communication of
6068  * GPU turbo limits to i915.
6069  */
6070 static void
6071 ips_ping_for_i915_load(void)
6072 {
6073         void (*link)(void);
6074
6075         link = symbol_get(ips_link_to_i915_driver);
6076         if (link) {
6077                 link();
6078                 symbol_put(ips_link_to_i915_driver);
6079         }
6080 }
6081
6082 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6083 {
6084         /* We only register the i915 ips part with intel-ips once everything is
6085          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6086         spin_lock_irq(&mchdev_lock);
6087         i915_mch_dev = dev_priv;
6088         spin_unlock_irq(&mchdev_lock);
6089
6090         ips_ping_for_i915_load();
6091 }
6092
6093 void intel_gpu_ips_teardown(void)
6094 {
6095         spin_lock_irq(&mchdev_lock);
6096         i915_mch_dev = NULL;
6097         spin_unlock_irq(&mchdev_lock);
6098 }
6099
6100 static void intel_init_emon(struct drm_device *dev)
6101 {
6102         struct drm_i915_private *dev_priv = dev->dev_private;
6103         u32 lcfuse;
6104         u8 pxw[16];
6105         int i;
6106
6107         /* Disable to program */
6108         I915_WRITE(ECR, 0);
6109         POSTING_READ(ECR);
6110
6111         /* Program energy weights for various events */
6112         I915_WRITE(SDEW, 0x15040d00);
6113         I915_WRITE(CSIEW0, 0x007f0000);
6114         I915_WRITE(CSIEW1, 0x1e220004);
6115         I915_WRITE(CSIEW2, 0x04000004);
6116
6117         for (i = 0; i < 5; i++)
6118                 I915_WRITE(PEW(i), 0);
6119         for (i = 0; i < 3; i++)
6120                 I915_WRITE(DEW(i), 0);
6121
6122         /* Program P-state weights to account for frequency power adjustment */
6123         for (i = 0; i < 16; i++) {
6124                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6125                 unsigned long freq = intel_pxfreq(pxvidfreq);
6126                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6127                         PXVFREQ_PX_SHIFT;
6128                 unsigned long val;
6129
6130                 val = vid * vid;
6131                 val *= (freq / 1000);
6132                 val *= 255;
6133                 val /= (127*127*900);
6134                 if (val > 0xff)
6135                         DRM_ERROR("bad pxval: %ld\n", val);
6136                 pxw[i] = val;
6137         }
6138         /* Render standby states get 0 weight */
6139         pxw[14] = 0;
6140         pxw[15] = 0;
6141
6142         for (i = 0; i < 4; i++) {
6143                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6144                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6145                 I915_WRITE(PXW(i), val);
6146         }
6147
6148         /* Adjust magic regs to magic values (more experimental results) */
6149         I915_WRITE(OGW0, 0);
6150         I915_WRITE(OGW1, 0);
6151         I915_WRITE(EG0, 0x00007f00);
6152         I915_WRITE(EG1, 0x0000000e);
6153         I915_WRITE(EG2, 0x000e0000);
6154         I915_WRITE(EG3, 0x68000300);
6155         I915_WRITE(EG4, 0x42000000);
6156         I915_WRITE(EG5, 0x00140031);
6157         I915_WRITE(EG6, 0);
6158         I915_WRITE(EG7, 0);
6159
6160         for (i = 0; i < 8; i++)
6161                 I915_WRITE(PXWL(i), 0);
6162
6163         /* Enable PMON + select events */
6164         I915_WRITE(ECR, 0x80000019);
6165
6166         lcfuse = I915_READ(LCFUSE02);
6167
6168         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6169 }
6170
6171 void intel_init_gt_powersave(struct drm_device *dev)
6172 {
6173         struct drm_i915_private *dev_priv = dev->dev_private;
6174
6175         /*
6176          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6177          * requirement.
6178          */
6179         if (!i915.enable_rc6) {
6180                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6181                 intel_runtime_pm_get(dev_priv);
6182         }
6183
6184         if (IS_CHERRYVIEW(dev))
6185                 cherryview_init_gt_powersave(dev);
6186         else if (IS_VALLEYVIEW(dev))
6187                 valleyview_init_gt_powersave(dev);
6188 }
6189
6190 void intel_cleanup_gt_powersave(struct drm_device *dev)
6191 {
6192         struct drm_i915_private *dev_priv = dev->dev_private;
6193
6194         if (IS_CHERRYVIEW(dev))
6195                 return;
6196         else if (IS_VALLEYVIEW(dev))
6197                 valleyview_cleanup_gt_powersave(dev);
6198
6199         if (!i915.enable_rc6)
6200                 intel_runtime_pm_put(dev_priv);
6201 }
6202
6203 static void gen6_suspend_rps(struct drm_device *dev)
6204 {
6205         struct drm_i915_private *dev_priv = dev->dev_private;
6206
6207         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6208
6209         gen6_disable_rps_interrupts(dev);
6210 }
6211
6212 /**
6213  * intel_suspend_gt_powersave - suspend PM work and helper threads
6214  * @dev: drm device
6215  *
6216  * We don't want to disable RC6 or other features here, we just want
6217  * to make sure any work we've queued has finished and won't bother
6218  * us while we're suspended.
6219  */
6220 void intel_suspend_gt_powersave(struct drm_device *dev)
6221 {
6222         struct drm_i915_private *dev_priv = dev->dev_private;
6223
6224         if (INTEL_INFO(dev)->gen < 6)
6225                 return;
6226
6227         gen6_suspend_rps(dev);
6228
6229         /* Force GPU to min freq during suspend */
6230         gen6_rps_idle(dev_priv);
6231 }
6232
6233 void intel_disable_gt_powersave(struct drm_device *dev)
6234 {
6235         struct drm_i915_private *dev_priv = dev->dev_private;
6236
6237         if (IS_IRONLAKE_M(dev)) {
6238                 ironlake_disable_drps(dev);
6239         } else if (INTEL_INFO(dev)->gen >= 6) {
6240                 intel_suspend_gt_powersave(dev);
6241
6242                 mutex_lock(&dev_priv->rps.hw_lock);
6243                 if (INTEL_INFO(dev)->gen >= 9)
6244                         gen9_disable_rps(dev);
6245                 else if (IS_CHERRYVIEW(dev))
6246                         cherryview_disable_rps(dev);
6247                 else if (IS_VALLEYVIEW(dev))
6248                         valleyview_disable_rps(dev);
6249                 else
6250                         gen6_disable_rps(dev);
6251
6252                 dev_priv->rps.enabled = false;
6253                 mutex_unlock(&dev_priv->rps.hw_lock);
6254         }
6255 }
6256
6257 static void intel_gen6_powersave_work(struct work_struct *work)
6258 {
6259         struct drm_i915_private *dev_priv =
6260                 container_of(work, struct drm_i915_private,
6261                              rps.delayed_resume_work.work);
6262         struct drm_device *dev = dev_priv->dev;
6263
6264         mutex_lock(&dev_priv->rps.hw_lock);
6265
6266         gen6_reset_rps_interrupts(dev);
6267
6268         if (IS_CHERRYVIEW(dev)) {
6269                 cherryview_enable_rps(dev);
6270         } else if (IS_VALLEYVIEW(dev)) {
6271                 valleyview_enable_rps(dev);
6272         } else if (INTEL_INFO(dev)->gen >= 9) {
6273                 gen9_enable_rc6(dev);
6274                 gen9_enable_rps(dev);
6275                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6276                         __gen6_update_ring_freq(dev);
6277         } else if (IS_BROADWELL(dev)) {
6278                 gen8_enable_rps(dev);
6279                 __gen6_update_ring_freq(dev);
6280         } else {
6281                 gen6_enable_rps(dev);
6282                 __gen6_update_ring_freq(dev);
6283         }
6284
6285         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6286         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6287
6288         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6289         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6290
6291         dev_priv->rps.enabled = true;
6292
6293         gen6_enable_rps_interrupts(dev);
6294
6295         mutex_unlock(&dev_priv->rps.hw_lock);
6296
6297         intel_runtime_pm_put(dev_priv);
6298 }
6299
6300 void intel_enable_gt_powersave(struct drm_device *dev)
6301 {
6302         struct drm_i915_private *dev_priv = dev->dev_private;
6303
6304         /* Powersaving is controlled by the host when inside a VM */
6305         if (intel_vgpu_active(dev))
6306                 return;
6307
6308         if (IS_IRONLAKE_M(dev)) {
6309                 ironlake_enable_drps(dev);
6310                 mutex_lock(&dev->struct_mutex);
6311                 intel_init_emon(dev);
6312                 mutex_unlock(&dev->struct_mutex);
6313         } else if (INTEL_INFO(dev)->gen >= 6) {
6314                 /*
6315                  * PCU communication is slow and this doesn't need to be
6316                  * done at any specific time, so do this out of our fast path
6317                  * to make resume and init faster.
6318                  *
6319                  * We depend on the HW RC6 power context save/restore
6320                  * mechanism when entering D3 through runtime PM suspend. So
6321                  * disable RPM until RPS/RC6 is properly setup. We can only
6322                  * get here via the driver load/system resume/runtime resume
6323                  * paths, so the _noresume version is enough (and in case of
6324                  * runtime resume it's necessary).
6325                  */
6326                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6327                                            round_jiffies_up_relative(HZ)))
6328                         intel_runtime_pm_get_noresume(dev_priv);
6329         }
6330 }
6331
6332 void intel_reset_gt_powersave(struct drm_device *dev)
6333 {
6334         struct drm_i915_private *dev_priv = dev->dev_private;
6335
6336         if (INTEL_INFO(dev)->gen < 6)
6337                 return;
6338
6339         gen6_suspend_rps(dev);
6340         dev_priv->rps.enabled = false;
6341 }
6342
6343 static void ibx_init_clock_gating(struct drm_device *dev)
6344 {
6345         struct drm_i915_private *dev_priv = dev->dev_private;
6346
6347         /*
6348          * On Ibex Peak and Cougar Point, we need to disable clock
6349          * gating for the panel power sequencer or it will fail to
6350          * start up when no ports are active.
6351          */
6352         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6353 }
6354
6355 static void g4x_disable_trickle_feed(struct drm_device *dev)
6356 {
6357         struct drm_i915_private *dev_priv = dev->dev_private;
6358         enum pipe pipe;
6359
6360         for_each_pipe(dev_priv, pipe) {
6361                 I915_WRITE(DSPCNTR(pipe),
6362                            I915_READ(DSPCNTR(pipe)) |
6363                            DISPPLANE_TRICKLE_FEED_DISABLE);
6364
6365                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6366                 POSTING_READ(DSPSURF(pipe));
6367         }
6368 }
6369
6370 static void ilk_init_lp_watermarks(struct drm_device *dev)
6371 {
6372         struct drm_i915_private *dev_priv = dev->dev_private;
6373
6374         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6375         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6376         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6377
6378         /*
6379          * Don't touch WM1S_LP_EN here.
6380          * Doing so could cause underruns.
6381          */
6382 }
6383
6384 static void ironlake_init_clock_gating(struct drm_device *dev)
6385 {
6386         struct drm_i915_private *dev_priv = dev->dev_private;
6387         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6388
6389         /*
6390          * Required for FBC
6391          * WaFbcDisableDpfcClockGating:ilk
6392          */
6393         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6394                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6395                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6396
6397         I915_WRITE(PCH_3DCGDIS0,
6398                    MARIUNIT_CLOCK_GATE_DISABLE |
6399                    SVSMUNIT_CLOCK_GATE_DISABLE);
6400         I915_WRITE(PCH_3DCGDIS1,
6401                    VFMUNIT_CLOCK_GATE_DISABLE);
6402
6403         /*
6404          * According to the spec the following bits should be set in
6405          * order to enable memory self-refresh
6406          * The bit 22/21 of 0x42004
6407          * The bit 5 of 0x42020
6408          * The bit 15 of 0x45000
6409          */
6410         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6411                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6412                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6413         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6414         I915_WRITE(DISP_ARB_CTL,
6415                    (I915_READ(DISP_ARB_CTL) |
6416                     DISP_FBC_WM_DIS));
6417
6418         ilk_init_lp_watermarks(dev);
6419
6420         /*
6421          * Based on the document from hardware guys the following bits
6422          * should be set unconditionally in order to enable FBC.
6423          * The bit 22 of 0x42000
6424          * The bit 22 of 0x42004
6425          * The bit 7,8,9 of 0x42020.
6426          */
6427         if (IS_IRONLAKE_M(dev)) {
6428                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6429                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6430                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6431                            ILK_FBCQ_DIS);
6432                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6433                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6434                            ILK_DPARB_GATE);
6435         }
6436
6437         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6438
6439         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6440                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6441                    ILK_ELPIN_409_SELECT);
6442         I915_WRITE(_3D_CHICKEN2,
6443                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6444                    _3D_CHICKEN2_WM_READ_PIPELINED);
6445
6446         /* WaDisableRenderCachePipelinedFlush:ilk */
6447         I915_WRITE(CACHE_MODE_0,
6448                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6449
6450         /* WaDisable_RenderCache_OperationalFlush:ilk */
6451         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6452
6453         g4x_disable_trickle_feed(dev);
6454
6455         ibx_init_clock_gating(dev);
6456 }
6457
6458 static void cpt_init_clock_gating(struct drm_device *dev)
6459 {
6460         struct drm_i915_private *dev_priv = dev->dev_private;
6461         int pipe;
6462         uint32_t val;
6463
6464         /*
6465          * On Ibex Peak and Cougar Point, we need to disable clock
6466          * gating for the panel power sequencer or it will fail to
6467          * start up when no ports are active.
6468          */
6469         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6470                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6471                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6472         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6473                    DPLS_EDP_PPS_FIX_DIS);
6474         /* The below fixes the weird display corruption, a few pixels shifted
6475          * downward, on (only) LVDS of some HP laptops with IVY.
6476          */
6477         for_each_pipe(dev_priv, pipe) {
6478                 val = I915_READ(TRANS_CHICKEN2(pipe));
6479                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6480                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6481                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6482                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6483                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6484                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6485                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6486                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6487         }
6488         /* WADP0ClockGatingDisable */
6489         for_each_pipe(dev_priv, pipe) {
6490                 I915_WRITE(TRANS_CHICKEN1(pipe),
6491                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6492         }
6493 }
6494
6495 static void gen6_check_mch_setup(struct drm_device *dev)
6496 {
6497         struct drm_i915_private *dev_priv = dev->dev_private;
6498         uint32_t tmp;
6499
6500         tmp = I915_READ(MCH_SSKPD);
6501         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6502                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6503                               tmp);
6504 }
6505
6506 static void gen6_init_clock_gating(struct drm_device *dev)
6507 {
6508         struct drm_i915_private *dev_priv = dev->dev_private;
6509         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6510
6511         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6512
6513         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6514                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6515                    ILK_ELPIN_409_SELECT);
6516
6517         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6518         I915_WRITE(_3D_CHICKEN,
6519                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6520
6521         /* WaDisable_RenderCache_OperationalFlush:snb */
6522         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6523
6524         /*
6525          * BSpec recoomends 8x4 when MSAA is used,
6526          * however in practice 16x4 seems fastest.
6527          *
6528          * Note that PS/WM thread counts depend on the WIZ hashing
6529          * disable bit, which we don't touch here, but it's good
6530          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6531          */
6532         I915_WRITE(GEN6_GT_MODE,
6533                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6534
6535         ilk_init_lp_watermarks(dev);
6536
6537         I915_WRITE(CACHE_MODE_0,
6538                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6539
6540         I915_WRITE(GEN6_UCGCTL1,
6541                    I915_READ(GEN6_UCGCTL1) |
6542                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6543                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6544
6545         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6546          * gating disable must be set.  Failure to set it results in
6547          * flickering pixels due to Z write ordering failures after
6548          * some amount of runtime in the Mesa "fire" demo, and Unigine
6549          * Sanctuary and Tropics, and apparently anything else with
6550          * alpha test or pixel discard.
6551          *
6552          * According to the spec, bit 11 (RCCUNIT) must also be set,
6553          * but we didn't debug actual testcases to find it out.
6554          *
6555          * WaDisableRCCUnitClockGating:snb
6556          * WaDisableRCPBUnitClockGating:snb
6557          */
6558         I915_WRITE(GEN6_UCGCTL2,
6559                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6560                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6561
6562         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6563         I915_WRITE(_3D_CHICKEN3,
6564                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6565
6566         /*
6567          * Bspec says:
6568          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6569          * 3DSTATE_SF number of SF output attributes is more than 16."
6570          */
6571         I915_WRITE(_3D_CHICKEN3,
6572                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6573
6574         /*
6575          * According to the spec the following bits should be
6576          * set in order to enable memory self-refresh and fbc:
6577          * The bit21 and bit22 of 0x42000
6578          * The bit21 and bit22 of 0x42004
6579          * The bit5 and bit7 of 0x42020
6580          * The bit14 of 0x70180
6581          * The bit14 of 0x71180
6582          *
6583          * WaFbcAsynchFlipDisableFbcQueue:snb
6584          */
6585         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6586                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6587                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6588         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6589                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6590                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6591         I915_WRITE(ILK_DSPCLK_GATE_D,
6592                    I915_READ(ILK_DSPCLK_GATE_D) |
6593                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6594                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6595
6596         g4x_disable_trickle_feed(dev);
6597
6598         cpt_init_clock_gating(dev);
6599
6600         gen6_check_mch_setup(dev);
6601 }
6602
6603 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6604 {
6605         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6606
6607         /*
6608          * WaVSThreadDispatchOverride:ivb,vlv
6609          *
6610          * This actually overrides the dispatch
6611          * mode for all thread types.
6612          */
6613         reg &= ~GEN7_FF_SCHED_MASK;
6614         reg |= GEN7_FF_TS_SCHED_HW;
6615         reg |= GEN7_FF_VS_SCHED_HW;
6616         reg |= GEN7_FF_DS_SCHED_HW;
6617
6618         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6619 }
6620
6621 static void lpt_init_clock_gating(struct drm_device *dev)
6622 {
6623         struct drm_i915_private *dev_priv = dev->dev_private;
6624
6625         /*
6626          * TODO: this bit should only be enabled when really needed, then
6627          * disabled when not needed anymore in order to save power.
6628          */
6629         if (HAS_PCH_LPT_LP(dev))
6630                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6631                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6632                            PCH_LP_PARTITION_LEVEL_DISABLE);
6633
6634         /* WADPOClockGatingDisable:hsw */
6635         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6636                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6637                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6638 }
6639
6640 static void lpt_suspend_hw(struct drm_device *dev)
6641 {
6642         struct drm_i915_private *dev_priv = dev->dev_private;
6643
6644         if (HAS_PCH_LPT_LP(dev)) {
6645                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6646
6647                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6648                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6649         }
6650 }
6651
6652 static void broadwell_init_clock_gating(struct drm_device *dev)
6653 {
6654         struct drm_i915_private *dev_priv = dev->dev_private;
6655         enum pipe pipe;
6656         uint32_t misccpctl;
6657
6658         ilk_init_lp_watermarks(dev);
6659
6660         /* WaSwitchSolVfFArbitrationPriority:bdw */
6661         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6662
6663         /* WaPsrDPAMaskVBlankInSRD:bdw */
6664         I915_WRITE(CHICKEN_PAR1_1,
6665                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6666
6667         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6668         for_each_pipe(dev_priv, pipe) {
6669                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6670                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6671                            BDW_DPRS_MASK_VBLANK_SRD);
6672         }
6673
6674         /* WaVSRefCountFullforceMissDisable:bdw */
6675         /* WaDSRefCountFullforceMissDisable:bdw */
6676         I915_WRITE(GEN7_FF_THREAD_MODE,
6677                    I915_READ(GEN7_FF_THREAD_MODE) &
6678                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6679
6680         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6681                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6682
6683         /* WaDisableSDEUnitClockGating:bdw */
6684         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6685                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6686
6687         /*
6688          * WaProgramL3SqcReg1Default:bdw
6689          * WaTempDisableDOPClkGating:bdw
6690          */
6691         misccpctl = I915_READ(GEN7_MISCCPCTL);
6692         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6693         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6694         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6695
6696         /*
6697          * WaGttCachingOffByDefault:bdw
6698          * GTT cache may not work with big pages, so if those
6699          * are ever enabled GTT cache may need to be disabled.
6700          */
6701         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6702
6703         lpt_init_clock_gating(dev);
6704 }
6705
6706 static void haswell_init_clock_gating(struct drm_device *dev)
6707 {
6708         struct drm_i915_private *dev_priv = dev->dev_private;
6709
6710         ilk_init_lp_watermarks(dev);
6711
6712         /* L3 caching of data atomics doesn't work -- disable it. */
6713         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6714         I915_WRITE(HSW_ROW_CHICKEN3,
6715                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6716
6717         /* This is required by WaCatErrorRejectionIssue:hsw */
6718         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6719                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6720                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6721
6722         /* WaVSRefCountFullforceMissDisable:hsw */
6723         I915_WRITE(GEN7_FF_THREAD_MODE,
6724                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6725
6726         /* WaDisable_RenderCache_OperationalFlush:hsw */
6727         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6728
6729         /* enable HiZ Raw Stall Optimization */
6730         I915_WRITE(CACHE_MODE_0_GEN7,
6731                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6732
6733         /* WaDisable4x2SubspanOptimization:hsw */
6734         I915_WRITE(CACHE_MODE_1,
6735                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6736
6737         /*
6738          * BSpec recommends 8x4 when MSAA is used,
6739          * however in practice 16x4 seems fastest.
6740          *
6741          * Note that PS/WM thread counts depend on the WIZ hashing
6742          * disable bit, which we don't touch here, but it's good
6743          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6744          */
6745         I915_WRITE(GEN7_GT_MODE,
6746                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6747
6748         /* WaSampleCChickenBitEnable:hsw */
6749         I915_WRITE(HALF_SLICE_CHICKEN3,
6750                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6751
6752         /* WaSwitchSolVfFArbitrationPriority:hsw */
6753         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6754
6755         /* WaRsPkgCStateDisplayPMReq:hsw */
6756         I915_WRITE(CHICKEN_PAR1_1,
6757                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6758
6759         lpt_init_clock_gating(dev);
6760 }
6761
6762 static void ivybridge_init_clock_gating(struct drm_device *dev)
6763 {
6764         struct drm_i915_private *dev_priv = dev->dev_private;
6765         uint32_t snpcr;
6766
6767         ilk_init_lp_watermarks(dev);
6768
6769         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6770
6771         /* WaDisableEarlyCull:ivb */
6772         I915_WRITE(_3D_CHICKEN3,
6773                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6774
6775         /* WaDisableBackToBackFlipFix:ivb */
6776         I915_WRITE(IVB_CHICKEN3,
6777                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6778                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6779
6780         /* WaDisablePSDDualDispatchEnable:ivb */
6781         if (IS_IVB_GT1(dev))
6782                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6783                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6784
6785         /* WaDisable_RenderCache_OperationalFlush:ivb */
6786         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6787
6788         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6789         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6790                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6791
6792         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6793         I915_WRITE(GEN7_L3CNTLREG1,
6794                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6795         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6796                    GEN7_WA_L3_CHICKEN_MODE);
6797         if (IS_IVB_GT1(dev))
6798                 I915_WRITE(GEN7_ROW_CHICKEN2,
6799                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6800         else {
6801                 /* must write both registers */
6802                 I915_WRITE(GEN7_ROW_CHICKEN2,
6803                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6804                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6805                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6806         }
6807
6808         /* WaForceL3Serialization:ivb */
6809         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6810                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6811
6812         /*
6813          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6814          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6815          */
6816         I915_WRITE(GEN6_UCGCTL2,
6817                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6818
6819         /* This is required by WaCatErrorRejectionIssue:ivb */
6820         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6821                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6822                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6823
6824         g4x_disable_trickle_feed(dev);
6825
6826         gen7_setup_fixed_func_scheduler(dev_priv);
6827
6828         if (0) { /* causes HiZ corruption on ivb:gt1 */
6829                 /* enable HiZ Raw Stall Optimization */
6830                 I915_WRITE(CACHE_MODE_0_GEN7,
6831                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6832         }
6833
6834         /* WaDisable4x2SubspanOptimization:ivb */
6835         I915_WRITE(CACHE_MODE_1,
6836                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6837
6838         /*
6839          * BSpec recommends 8x4 when MSAA is used,
6840          * however in practice 16x4 seems fastest.
6841          *
6842          * Note that PS/WM thread counts depend on the WIZ hashing
6843          * disable bit, which we don't touch here, but it's good
6844          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6845          */
6846         I915_WRITE(GEN7_GT_MODE,
6847                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6848
6849         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6850         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6851         snpcr |= GEN6_MBC_SNPCR_MED;
6852         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6853
6854         if (!HAS_PCH_NOP(dev))
6855                 cpt_init_clock_gating(dev);
6856
6857         gen6_check_mch_setup(dev);
6858 }
6859
6860 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6861 {
6862         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6863
6864         /*
6865          * Disable trickle feed and enable pnd deadline calculation
6866          */
6867         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6868         I915_WRITE(CBR1_VLV, 0);
6869 }
6870
6871 static void valleyview_init_clock_gating(struct drm_device *dev)
6872 {
6873         struct drm_i915_private *dev_priv = dev->dev_private;
6874
6875         vlv_init_display_clock_gating(dev_priv);
6876
6877         /* WaDisableEarlyCull:vlv */
6878         I915_WRITE(_3D_CHICKEN3,
6879                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6880
6881         /* WaDisableBackToBackFlipFix:vlv */
6882         I915_WRITE(IVB_CHICKEN3,
6883                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6884                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6885
6886         /* WaPsdDispatchEnable:vlv */
6887         /* WaDisablePSDDualDispatchEnable:vlv */
6888         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6889                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6890                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6891
6892         /* WaDisable_RenderCache_OperationalFlush:vlv */
6893         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6894
6895         /* WaForceL3Serialization:vlv */
6896         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6897                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6898
6899         /* WaDisableDopClockGating:vlv */
6900         I915_WRITE(GEN7_ROW_CHICKEN2,
6901                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6902
6903         /* This is required by WaCatErrorRejectionIssue:vlv */
6904         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6905                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6906                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6907
6908         gen7_setup_fixed_func_scheduler(dev_priv);
6909
6910         /*
6911          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6912          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6913          */
6914         I915_WRITE(GEN6_UCGCTL2,
6915                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6916
6917         /* WaDisableL3Bank2xClockGate:vlv
6918          * Disabling L3 clock gating- MMIO 940c[25] = 1
6919          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6920         I915_WRITE(GEN7_UCGCTL4,
6921                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6922
6923         /*
6924          * BSpec says this must be set, even though
6925          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6926          */
6927         I915_WRITE(CACHE_MODE_1,
6928                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6929
6930         /*
6931          * BSpec recommends 8x4 when MSAA is used,
6932          * however in practice 16x4 seems fastest.
6933          *
6934          * Note that PS/WM thread counts depend on the WIZ hashing
6935          * disable bit, which we don't touch here, but it's good
6936          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6937          */
6938         I915_WRITE(GEN7_GT_MODE,
6939                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6940
6941         /*
6942          * WaIncreaseL3CreditsForVLVB0:vlv
6943          * This is the hardware default actually.
6944          */
6945         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6946
6947         /*
6948          * WaDisableVLVClockGating_VBIIssue:vlv
6949          * Disable clock gating on th GCFG unit to prevent a delay
6950          * in the reporting of vblank events.
6951          */
6952         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6953 }
6954
6955 static void cherryview_init_clock_gating(struct drm_device *dev)
6956 {
6957         struct drm_i915_private *dev_priv = dev->dev_private;
6958
6959         vlv_init_display_clock_gating(dev_priv);
6960
6961         /* WaVSRefCountFullforceMissDisable:chv */
6962         /* WaDSRefCountFullforceMissDisable:chv */
6963         I915_WRITE(GEN7_FF_THREAD_MODE,
6964                    I915_READ(GEN7_FF_THREAD_MODE) &
6965                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6966
6967         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6968         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6969                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6970
6971         /* WaDisableCSUnitClockGating:chv */
6972         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6973                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6974
6975         /* WaDisableSDEUnitClockGating:chv */
6976         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6977                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6978
6979         /*
6980          * GTT cache may not work with big pages, so if those
6981          * are ever enabled GTT cache may need to be disabled.
6982          */
6983         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6984 }
6985
6986 static void g4x_init_clock_gating(struct drm_device *dev)
6987 {
6988         struct drm_i915_private *dev_priv = dev->dev_private;
6989         uint32_t dspclk_gate;
6990
6991         I915_WRITE(RENCLK_GATE_D1, 0);
6992         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6993                    GS_UNIT_CLOCK_GATE_DISABLE |
6994                    CL_UNIT_CLOCK_GATE_DISABLE);
6995         I915_WRITE(RAMCLK_GATE_D, 0);
6996         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6997                 OVRUNIT_CLOCK_GATE_DISABLE |
6998                 OVCUNIT_CLOCK_GATE_DISABLE;
6999         if (IS_GM45(dev))
7000                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7001         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7002
7003         /* WaDisableRenderCachePipelinedFlush */
7004         I915_WRITE(CACHE_MODE_0,
7005                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7006
7007         /* WaDisable_RenderCache_OperationalFlush:g4x */
7008         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7009
7010         g4x_disable_trickle_feed(dev);
7011 }
7012
7013 static void crestline_init_clock_gating(struct drm_device *dev)
7014 {
7015         struct drm_i915_private *dev_priv = dev->dev_private;
7016
7017         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7018         I915_WRITE(RENCLK_GATE_D2, 0);
7019         I915_WRITE(DSPCLK_GATE_D, 0);
7020         I915_WRITE(RAMCLK_GATE_D, 0);
7021         I915_WRITE16(DEUC, 0);
7022         I915_WRITE(MI_ARB_STATE,
7023                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7024
7025         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7026         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7027 }
7028
7029 static void broadwater_init_clock_gating(struct drm_device *dev)
7030 {
7031         struct drm_i915_private *dev_priv = dev->dev_private;
7032
7033         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7034                    I965_RCC_CLOCK_GATE_DISABLE |
7035                    I965_RCPB_CLOCK_GATE_DISABLE |
7036                    I965_ISC_CLOCK_GATE_DISABLE |
7037                    I965_FBC_CLOCK_GATE_DISABLE);
7038         I915_WRITE(RENCLK_GATE_D2, 0);
7039         I915_WRITE(MI_ARB_STATE,
7040                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7041
7042         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7043         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7044 }
7045
7046 static void gen3_init_clock_gating(struct drm_device *dev)
7047 {
7048         struct drm_i915_private *dev_priv = dev->dev_private;
7049         u32 dstate = I915_READ(D_STATE);
7050
7051         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7052                 DSTATE_DOT_CLOCK_GATING;
7053         I915_WRITE(D_STATE, dstate);
7054
7055         if (IS_PINEVIEW(dev))
7056                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7057
7058         /* IIR "flip pending" means done if this bit is set */
7059         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7060
7061         /* interrupts should cause a wake up from C3 */
7062         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7063
7064         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7065         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7066
7067         I915_WRITE(MI_ARB_STATE,
7068                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7069 }
7070
7071 static void i85x_init_clock_gating(struct drm_device *dev)
7072 {
7073         struct drm_i915_private *dev_priv = dev->dev_private;
7074
7075         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7076
7077         /* interrupts should cause a wake up from C3 */
7078         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7079                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7080
7081         I915_WRITE(MEM_MODE,
7082                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7083 }
7084
7085 static void i830_init_clock_gating(struct drm_device *dev)
7086 {
7087         struct drm_i915_private *dev_priv = dev->dev_private;
7088
7089         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7090
7091         I915_WRITE(MEM_MODE,
7092                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7093                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7094 }
7095
7096 void intel_init_clock_gating(struct drm_device *dev)
7097 {
7098         struct drm_i915_private *dev_priv = dev->dev_private;
7099
7100         if (dev_priv->display.init_clock_gating)
7101                 dev_priv->display.init_clock_gating(dev);
7102 }
7103
7104 void intel_suspend_hw(struct drm_device *dev)
7105 {
7106         if (HAS_PCH_LPT(dev))
7107                 lpt_suspend_hw(dev);
7108 }
7109
7110 /* Set up chip specific power management-related functions */
7111 void intel_init_pm(struct drm_device *dev)
7112 {
7113         struct drm_i915_private *dev_priv = dev->dev_private;
7114
7115         intel_fbc_init(dev_priv);
7116
7117         /* For cxsr */
7118         if (IS_PINEVIEW(dev))
7119                 i915_pineview_get_mem_freq(dev);
7120         else if (IS_GEN5(dev))
7121                 i915_ironlake_get_mem_freq(dev);
7122
7123         /* For FIFO watermark updates */
7124         if (INTEL_INFO(dev)->gen >= 9) {
7125                 skl_setup_wm_latency(dev);
7126
7127                 if (IS_BROXTON(dev))
7128                         dev_priv->display.init_clock_gating =
7129                                 bxt_init_clock_gating;
7130                 dev_priv->display.update_wm = skl_update_wm;
7131         } else if (HAS_PCH_SPLIT(dev)) {
7132                 ilk_setup_wm_latency(dev);
7133
7134                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7135                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7136                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7137                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7138                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7139                         dev_priv->display.compute_intermediate_wm =
7140                                 ilk_compute_intermediate_wm;
7141                         dev_priv->display.initial_watermarks =
7142                                 ilk_initial_watermarks;
7143                         dev_priv->display.optimize_watermarks =
7144                                 ilk_optimize_watermarks;
7145                 } else {
7146                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7147                                       "Disable CxSR\n");
7148                 }
7149
7150                 if (IS_GEN5(dev))
7151                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7152                 else if (IS_GEN6(dev))
7153                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7154                 else if (IS_IVYBRIDGE(dev))
7155                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7156                 else if (IS_HASWELL(dev))
7157                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7158                 else if (INTEL_INFO(dev)->gen == 8)
7159                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7160         } else if (IS_CHERRYVIEW(dev)) {
7161                 vlv_setup_wm_latency(dev);
7162
7163                 dev_priv->display.update_wm = vlv_update_wm;
7164                 dev_priv->display.init_clock_gating =
7165                         cherryview_init_clock_gating;
7166         } else if (IS_VALLEYVIEW(dev)) {
7167                 vlv_setup_wm_latency(dev);
7168
7169                 dev_priv->display.update_wm = vlv_update_wm;
7170                 dev_priv->display.init_clock_gating =
7171                         valleyview_init_clock_gating;
7172         } else if (IS_PINEVIEW(dev)) {
7173                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7174                                             dev_priv->is_ddr3,
7175                                             dev_priv->fsb_freq,
7176                                             dev_priv->mem_freq)) {
7177                         DRM_INFO("failed to find known CxSR latency "
7178                                  "(found ddr%s fsb freq %d, mem freq %d), "
7179                                  "disabling CxSR\n",
7180                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7181                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7182                         /* Disable CxSR and never update its watermark again */
7183                         intel_set_memory_cxsr(dev_priv, false);
7184                         dev_priv->display.update_wm = NULL;
7185                 } else
7186                         dev_priv->display.update_wm = pineview_update_wm;
7187                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7188         } else if (IS_G4X(dev)) {
7189                 dev_priv->display.update_wm = g4x_update_wm;
7190                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7191         } else if (IS_GEN4(dev)) {
7192                 dev_priv->display.update_wm = i965_update_wm;
7193                 if (IS_CRESTLINE(dev))
7194                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7195                 else if (IS_BROADWATER(dev))
7196                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7197         } else if (IS_GEN3(dev)) {
7198                 dev_priv->display.update_wm = i9xx_update_wm;
7199                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7200                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7201         } else if (IS_GEN2(dev)) {
7202                 if (INTEL_INFO(dev)->num_pipes == 1) {
7203                         dev_priv->display.update_wm = i845_update_wm;
7204                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7205                 } else {
7206                         dev_priv->display.update_wm = i9xx_update_wm;
7207                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7208                 }
7209
7210                 if (IS_I85X(dev) || IS_I865G(dev))
7211                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7212                 else
7213                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7214         } else {
7215                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7216         }
7217 }
7218
7219 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7220 {
7221         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7222
7223         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7224                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7225                 return -EAGAIN;
7226         }
7227
7228         I915_WRITE(GEN6_PCODE_DATA, *val);
7229         I915_WRITE(GEN6_PCODE_DATA1, 0);
7230         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7231
7232         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7233                      500)) {
7234                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7235                 return -ETIMEDOUT;
7236         }
7237
7238         *val = I915_READ(GEN6_PCODE_DATA);
7239         I915_WRITE(GEN6_PCODE_DATA, 0);
7240
7241         return 0;
7242 }
7243
7244 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7245 {
7246         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7247
7248         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7249                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7250                 return -EAGAIN;
7251         }
7252
7253         I915_WRITE(GEN6_PCODE_DATA, val);
7254         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7255
7256         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7257                      500)) {
7258                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7259                 return -ETIMEDOUT;
7260         }
7261
7262         I915_WRITE(GEN6_PCODE_DATA, 0);
7263
7264         return 0;
7265 }
7266
7267 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7268 {
7269         switch (czclk_freq) {
7270         case 200:
7271                 return 10;
7272         case 267:
7273                 return 12;
7274         case 320:
7275         case 333:
7276                 return 16;
7277         case 400:
7278                 return 20;
7279         default:
7280                 return -1;
7281         }
7282 }
7283
7284 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7285 {
7286         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7287
7288         div = vlv_gpu_freq_div(czclk_freq);
7289         if (div < 0)
7290                 return div;
7291
7292         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7293 }
7294
7295 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7296 {
7297         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7298
7299         mul = vlv_gpu_freq_div(czclk_freq);
7300         if (mul < 0)
7301                 return mul;
7302
7303         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7304 }
7305
7306 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7307 {
7308         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7309
7310         div = vlv_gpu_freq_div(czclk_freq);
7311         if (div < 0)
7312                 return div;
7313         div /= 2;
7314
7315         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7316 }
7317
7318 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7319 {
7320         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7321
7322         mul = vlv_gpu_freq_div(czclk_freq);
7323         if (mul < 0)
7324                 return mul;
7325         mul /= 2;
7326
7327         /* CHV needs even values */
7328         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7329 }
7330
7331 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7332 {
7333         if (IS_GEN9(dev_priv->dev))
7334                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7335                                          GEN9_FREQ_SCALER);
7336         else if (IS_CHERRYVIEW(dev_priv->dev))
7337                 return chv_gpu_freq(dev_priv, val);
7338         else if (IS_VALLEYVIEW(dev_priv->dev))
7339                 return byt_gpu_freq(dev_priv, val);
7340         else
7341                 return val * GT_FREQUENCY_MULTIPLIER;
7342 }
7343
7344 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7345 {
7346         if (IS_GEN9(dev_priv->dev))
7347                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7348                                          GT_FREQUENCY_MULTIPLIER);
7349         else if (IS_CHERRYVIEW(dev_priv->dev))
7350                 return chv_freq_opcode(dev_priv, val);
7351         else if (IS_VALLEYVIEW(dev_priv->dev))
7352                 return byt_freq_opcode(dev_priv, val);
7353         else
7354                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7355 }
7356
7357 struct request_boost {
7358         struct work_struct work;
7359         struct drm_i915_gem_request *req;
7360 };
7361
7362 static void __intel_rps_boost_work(struct work_struct *work)
7363 {
7364         struct request_boost *boost = container_of(work, struct request_boost, work);
7365         struct drm_i915_gem_request *req = boost->req;
7366
7367         if (!i915_gem_request_completed(req, true))
7368                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7369                                req->emitted_jiffies);
7370
7371         i915_gem_request_unreference__unlocked(req);
7372         kfree(boost);
7373 }
7374
7375 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7376                                        struct drm_i915_gem_request *req)
7377 {
7378         struct request_boost *boost;
7379
7380         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7381                 return;
7382
7383         if (i915_gem_request_completed(req, true))
7384                 return;
7385
7386         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7387         if (boost == NULL)
7388                 return;
7389
7390         i915_gem_request_reference(req);
7391         boost->req = req;
7392
7393         INIT_WORK(&boost->work, __intel_rps_boost_work);
7394         queue_work(to_i915(dev)->wq, &boost->work);
7395 }
7396
7397 void intel_pm_setup(struct drm_device *dev)
7398 {
7399         struct drm_i915_private *dev_priv = dev->dev_private;
7400
7401         mutex_init(&dev_priv->rps.hw_lock);
7402         spin_lock_init(&dev_priv->rps.client_lock);
7403
7404         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7405                           intel_gen6_powersave_work);
7406         INIT_LIST_HEAD(&dev_priv->rps.clients);
7407         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7408         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7409
7410         dev_priv->pm.suspended = false;
7411         atomic_set(&dev_priv->pm.wakeref_count, 0);
7412         atomic_set(&dev_priv->pm.atomic_seq, 0);
7413 }