drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 static void gen9_init_clock_gating(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58
  59         /* WaEnableLbsSlaRetryTimerDecrement:skl */
  60         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
  61                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
  62
  63         /* WaDisableKillLogic:bxt,skl */
  64         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  65                    ECOCHK_DIS_TLB);
  66 }
  67
  68 static void skl_init_clock_gating(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         gen9_init_clock_gating(dev);
  73
  74         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
  75                 /* WaDisableHDCInvalidation:skl */
  76                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  77                            BDW_DISABLE_HDC_INVALIDATION);
  78
  79                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
  80                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
  81                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
  82         }
  83
  84         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
  85          * involving this register should also be added to WA batch as required.
  86          */
  87         if (INTEL_REVID(dev) <= SKL_REVID_E0)
  88                 /* WaDisableLSQCROPERFforOCL:skl */
  89                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
  90                            GEN8_LQSC_RO_PERF_DIS);
  91
  92         /* WaEnableGapsTsvCreditFix:skl */
  93         if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
  94                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
  95                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
  96         }
  97 }
  98
  99 static void bxt_init_clock_gating(struct drm_device *dev)
 100 {
 101         struct drm_i915_private *dev_priv = dev->dev_private;
 102
 103         gen9_init_clock_gating(dev);
 104
 105         /* WaDisableSDEUnitClockGating:bxt */
 106         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 107                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 108
 109         /*
 110          * FIXME:
 111          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 112          */
 113         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 114                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 115
 116         /* WaStoreMultiplePTEenable:bxt */
 117         /* This is a requirement according to Hardware specification */
 118         if (INTEL_REVID(dev) == BXT_REVID_A0)
 119                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 120
 121         /* WaSetClckGatingDisableMedia:bxt */
 122         if (INTEL_REVID(dev) == BXT_REVID_A0) {
 123                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
 124                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
 125         }
 126 }
 127
 128 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 129 {
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131         u32 tmp;
 132
 133         tmp = I915_READ(CLKCFG);
 134
 135         switch (tmp & CLKCFG_FSB_MASK) {
 136         case CLKCFG_FSB_533:
 137                 dev_priv->fsb_freq = 533; /* 133*4 */
 138                 break;
 139         case CLKCFG_FSB_800:
 140                 dev_priv->fsb_freq = 800; /* 200*4 */
 141                 break;
 142         case CLKCFG_FSB_667:
 143                 dev_priv->fsb_freq =  667; /* 167*4 */
 144                 break;
 145         case CLKCFG_FSB_400:
 146                 dev_priv->fsb_freq = 400; /* 100*4 */
 147                 break;
 148         }
 149
 150         switch (tmp & CLKCFG_MEM_MASK) {
 151         case CLKCFG_MEM_533:
 152                 dev_priv->mem_freq = 533;
 153                 break;
 154         case CLKCFG_MEM_667:
 155                 dev_priv->mem_freq = 667;
 156                 break;
 157         case CLKCFG_MEM_800:
 158                 dev_priv->mem_freq = 800;
 159                 break;
 160         }
 161
 162         /* detect pineview DDR3 setting */
 163         tmp = I915_READ(CSHRDDR3CTL);
 164         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 165 }
 166
 167 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 168 {
 169         struct drm_i915_private *dev_priv = dev->dev_private;
 170         u16 ddrpll, csipll;
 171
 172         ddrpll = I915_READ16(DDRMPLL1);
 173         csipll = I915_READ16(CSIPLL0);
 174
 175         switch (ddrpll & 0xff) {
 176         case 0xc:
 177                 dev_priv->mem_freq = 800;
 178                 break;
 179         case 0x10:
 180                 dev_priv->mem_freq = 1066;
 181                 break;
 182         case 0x14:
 183                 dev_priv->mem_freq = 1333;
 184                 break;
 185         case 0x18:
 186                 dev_priv->mem_freq = 1600;
 187                 break;
 188         default:
 189                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 190                                  ddrpll & 0xff);
 191                 dev_priv->mem_freq = 0;
 192                 break;
 193         }
 194
 195         dev_priv->ips.r_t = dev_priv->mem_freq;
 196
 197         switch (csipll & 0x3ff) {
 198         case 0x00c:
 199                 dev_priv->fsb_freq = 3200;
 200                 break;
 201         case 0x00e:
 202                 dev_priv->fsb_freq = 3733;
 203                 break;
 204         case 0x010:
 205                 dev_priv->fsb_freq = 4266;
 206                 break;
 207         case 0x012:
 208                 dev_priv->fsb_freq = 4800;
 209                 break;
 210         case 0x014:
 211                 dev_priv->fsb_freq = 5333;
 212                 break;
 213         case 0x016:
 214                 dev_priv->fsb_freq = 5866;
 215                 break;
 216         case 0x018:
 217                 dev_priv->fsb_freq = 6400;
 218                 break;
 219         default:
 220                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 221                                  csipll & 0x3ff);
 222                 dev_priv->fsb_freq = 0;
 223                 break;
 224         }
 225
 226         if (dev_priv->fsb_freq == 3200) {
 227                 dev_priv->ips.c_m = 0;
 228         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 229                 dev_priv->ips.c_m = 1;
 230         } else {
 231                 dev_priv->ips.c_m = 2;
 232         }
 233 }
 234
 235 static const struct cxsr_latency cxsr_latency_table[] = {
 236         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 237         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 238         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 239         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 240         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 241
 242         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 243         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 244         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 245         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 246         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 247
 248         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 249         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 250         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 251         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 252         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 253
 254         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 255         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 256         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 257         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 258         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 259
 260         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 261         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 262         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 263         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 264         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 265
 266         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 267         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 268         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 269         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 270         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 271 };
 272
 273 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 274                                                          int is_ddr3,
 275                                                          int fsb,
 276                                                          int mem)
 277 {
 278         const struct cxsr_latency *latency;
 279         int i;
 280
 281         if (fsb == 0 || mem == 0)
 282                 return NULL;
 283
 284         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 285                 latency = &cxsr_latency_table[i];
 286                 if (is_desktop == latency->is_desktop &&
 287                     is_ddr3 == latency->is_ddr3 &&
 288                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 289                         return latency;
 290         }
 291
 292         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 293
 294         return NULL;
 295 }
 296
 297 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 298 {
 299         u32 val;
 300
 301         mutex_lock(&dev_priv->rps.hw_lock);
 302
 303         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 304         if (enable)
 305                 val &= ~FORCE_DDR_HIGH_FREQ;
 306         else
 307                 val |= FORCE_DDR_HIGH_FREQ;
 308         val &= ~FORCE_DDR_LOW_FREQ;
 309         val |= FORCE_DDR_FREQ_REQ_ACK;
 310         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 311
 312         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 313                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 314                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 315
 316         mutex_unlock(&dev_priv->rps.hw_lock);
 317 }
 318
 319 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 320 {
 321         u32 val;
 322
 323         mutex_lock(&dev_priv->rps.hw_lock);
 324
 325         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 326         if (enable)
 327                 val |= DSP_MAXFIFO_PM5_ENABLE;
 328         else
 329                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 330         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 331
 332         mutex_unlock(&dev_priv->rps.hw_lock);
 333 }
 334
 335 #define FW_WM(value, plane) \
 336         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 337
 338 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 339 {
 340         struct drm_device *dev = dev_priv->dev;
 341         u32 val;
 342
 343         if (IS_VALLEYVIEW(dev)) {
 344                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 345                 POSTING_READ(FW_BLC_SELF_VLV);
 346                 dev_priv->wm.vlv.cxsr = enable;
 347         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 348                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 349                 POSTING_READ(FW_BLC_SELF);
 350         } else if (IS_PINEVIEW(dev)) {
 351                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 352                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 353                 I915_WRITE(DSPFW3, val);
 354                 POSTING_READ(DSPFW3);
 355         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 356                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 357                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 358                 I915_WRITE(FW_BLC_SELF, val);
 359                 POSTING_READ(FW_BLC_SELF);
 360         } else if (IS_I915GM(dev)) {
 361                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 362                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 363                 I915_WRITE(INSTPM, val);
 364                 POSTING_READ(INSTPM);
 365         } else {
 366                 return;
 367         }
 368
 369         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 370                       enable ? "enabled" : "disabled");
 371 }
 372
 373
 374 /*
 375  * Latency for FIFO fetches is dependent on several factors:
 376  *   - memory configuration (speed, channels)
 377  *   - chipset
 378  *   - current MCH state
 379  * It can be fairly high in some situations, so here we assume a fairly
 380  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 381  * set this value too high, the FIFO will fetch frequently to stay full)
 382  * and power consumption (set it too low to save power and we might see
 383  * FIFO underruns and display "flicker").
 384  *
 385  * A value of 5us seems to be a good balance; safe for very low end
 386  * platforms but not overly aggressive on lower latency configs.
 387  */
 388 static const int pessimal_latency_ns = 5000;
 389
 390 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 391         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 392
 393 static int vlv_get_fifo_size(struct drm_device *dev,
 394                               enum pipe pipe, int plane)
 395 {
 396         struct drm_i915_private *dev_priv = dev->dev_private;
 397         int sprite0_start, sprite1_start, size;
 398
 399         switch (pipe) {
 400                 uint32_t dsparb, dsparb2, dsparb3;
 401         case PIPE_A:
 402                 dsparb = I915_READ(DSPARB);
 403                 dsparb2 = I915_READ(DSPARB2);
 404                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 405                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 406                 break;
 407         case PIPE_B:
 408                 dsparb = I915_READ(DSPARB);
 409                 dsparb2 = I915_READ(DSPARB2);
 410                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 411                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 412                 break;
 413         case PIPE_C:
 414                 dsparb2 = I915_READ(DSPARB2);
 415                 dsparb3 = I915_READ(DSPARB3);
 416                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 417                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 418                 break;
 419         default:
 420                 return 0;
 421         }
 422
 423         switch (plane) {
 424         case 0:
 425                 size = sprite0_start;
 426                 break;
 427         case 1:
 428                 size = sprite1_start - sprite0_start;
 429                 break;
 430         case 2:
 431                 size = 512 - 1 - sprite1_start;
 432                 break;
 433         default:
 434                 return 0;
 435         }
 436
 437         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 438                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 439                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 440                       size);
 441
 442         return size;
 443 }
 444
 445 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 446 {
 447         struct drm_i915_private *dev_priv = dev->dev_private;
 448         uint32_t dsparb = I915_READ(DSPARB);
 449         int size;
 450
 451         size = dsparb & 0x7f;
 452         if (plane)
 453                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 454
 455         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 456                       plane ? "B" : "A", size);
 457
 458         return size;
 459 }
 460
 461 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 462 {
 463         struct drm_i915_private *dev_priv = dev->dev_private;
 464         uint32_t dsparb = I915_READ(DSPARB);
 465         int size;
 466
 467         size = dsparb & 0x1ff;
 468         if (plane)
 469                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 470         size >>= 1; /* Convert to cachelines */
 471
 472         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 473                       plane ? "B" : "A", size);
 474
 475         return size;
 476 }
 477
 478 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 479 {
 480         struct drm_i915_private *dev_priv = dev->dev_private;
 481         uint32_t dsparb = I915_READ(DSPARB);
 482         int size;
 483
 484         size = dsparb & 0x7f;
 485         size >>= 2; /* Convert to cachelines */
 486
 487         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 488                       plane ? "B" : "A",
 489                       size);
 490
 491         return size;
 492 }
 493
 494 /* Pineview has different values for various configs */
 495 static const struct intel_watermark_params pineview_display_wm = {
 496         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 497         .max_wm = PINEVIEW_MAX_WM,
 498         .default_wm = PINEVIEW_DFT_WM,
 499         .guard_size = PINEVIEW_GUARD_WM,
 500         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 501 };
 502 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 503         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 504         .max_wm = PINEVIEW_MAX_WM,
 505         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 506         .guard_size = PINEVIEW_GUARD_WM,
 507         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 508 };
 509 static const struct intel_watermark_params pineview_cursor_wm = {
 510         .fifo_size = PINEVIEW_CURSOR_FIFO,
 511         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 512         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 513         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 514         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 515 };
 516 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 517         .fifo_size = PINEVIEW_CURSOR_FIFO,
 518         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 519         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 520         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 521         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 522 };
 523 static const struct intel_watermark_params g4x_wm_info = {
 524         .fifo_size = G4X_FIFO_SIZE,
 525         .max_wm = G4X_MAX_WM,
 526         .default_wm = G4X_MAX_WM,
 527         .guard_size = 2,
 528         .cacheline_size = G4X_FIFO_LINE_SIZE,
 529 };
 530 static const struct intel_watermark_params g4x_cursor_wm_info = {
 531         .fifo_size = I965_CURSOR_FIFO,
 532         .max_wm = I965_CURSOR_MAX_WM,
 533         .default_wm = I965_CURSOR_DFT_WM,
 534         .guard_size = 2,
 535         .cacheline_size = G4X_FIFO_LINE_SIZE,
 536 };
 537 static const struct intel_watermark_params valleyview_wm_info = {
 538         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 539         .max_wm = VALLEYVIEW_MAX_WM,
 540         .default_wm = VALLEYVIEW_MAX_WM,
 541         .guard_size = 2,
 542         .cacheline_size = G4X_FIFO_LINE_SIZE,
 543 };
 544 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 545         .fifo_size = I965_CURSOR_FIFO,
 546         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 547         .default_wm = I965_CURSOR_DFT_WM,
 548         .guard_size = 2,
 549         .cacheline_size = G4X_FIFO_LINE_SIZE,
 550 };
 551 static const struct intel_watermark_params i965_cursor_wm_info = {
 552         .fifo_size = I965_CURSOR_FIFO,
 553         .max_wm = I965_CURSOR_MAX_WM,
 554         .default_wm = I965_CURSOR_DFT_WM,
 555         .guard_size = 2,
 556         .cacheline_size = I915_FIFO_LINE_SIZE,
 557 };
 558 static const struct intel_watermark_params i945_wm_info = {
 559         .fifo_size = I945_FIFO_SIZE,
 560         .max_wm = I915_MAX_WM,
 561         .default_wm = 1,
 562         .guard_size = 2,
 563         .cacheline_size = I915_FIFO_LINE_SIZE,
 564 };
 565 static const struct intel_watermark_params i915_wm_info = {
 566         .fifo_size = I915_FIFO_SIZE,
 567         .max_wm = I915_MAX_WM,
 568         .default_wm = 1,
 569         .guard_size = 2,
 570         .cacheline_size = I915_FIFO_LINE_SIZE,
 571 };
 572 static const struct intel_watermark_params i830_a_wm_info = {
 573         .fifo_size = I855GM_FIFO_SIZE,
 574         .max_wm = I915_MAX_WM,
 575         .default_wm = 1,
 576         .guard_size = 2,
 577         .cacheline_size = I830_FIFO_LINE_SIZE,
 578 };
 579 static const struct intel_watermark_params i830_bc_wm_info = {
 580         .fifo_size = I855GM_FIFO_SIZE,
 581         .max_wm = I915_MAX_WM/2,
 582         .default_wm = 1,
 583         .guard_size = 2,
 584         .cacheline_size = I830_FIFO_LINE_SIZE,
 585 };
 586 static const struct intel_watermark_params i845_wm_info = {
 587         .fifo_size = I830_FIFO_SIZE,
 588         .max_wm = I915_MAX_WM,
 589         .default_wm = 1,
 590         .guard_size = 2,
 591         .cacheline_size = I830_FIFO_LINE_SIZE,
 592 };
 593
 594 /**
 595  * intel_calculate_wm - calculate watermark level
 596  * @clock_in_khz: pixel clock
 597  * @wm: chip FIFO params
 598  * @pixel_size: display pixel size
 599  * @latency_ns: memory latency for the platform
 600  *
 601  * Calculate the watermark level (the level at which the display plane will
 602  * start fetching from memory again).  Each chip has a different display
 603  * FIFO size and allocation, so the caller needs to figure that out and pass
 604  * in the correct intel_watermark_params structure.
 605  *
 606  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 607  * on the pixel size.  When it reaches the watermark level, it'll start
 608  * fetching FIFO line sized based chunks from memory until the FIFO fills
 609  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 610  * will occur, and a display engine hang could result.
 611  */
 612 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 613                                         const struct intel_watermark_params *wm,
 614                                         int fifo_size,
 615                                         int pixel_size,
 616                                         unsigned long latency_ns)
 617 {
 618         long entries_required, wm_size;
 619
 620         /*
 621          * Note: we need to make sure we don't overflow for various clock &
 622          * latency values.
 623          * clocks go from a few thousand to several hundred thousand.
 624          * latency is usually a few thousand
 625          */
 626         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 627                 1000;
 628         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 629
 630         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 631
 632         wm_size = fifo_size - (entries_required + wm->guard_size);
 633
 634         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 635
 636         /* Don't promote wm_size to unsigned... */
 637         if (wm_size > (long)wm->max_wm)
 638                 wm_size = wm->max_wm;
 639         if (wm_size <= 0)
 640                 wm_size = wm->default_wm;
 641
 642         /*
 643          * Bspec seems to indicate that the value shouldn't be lower than
 644          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 645          * Lets go for 8 which is the burst size since certain platforms
 646          * already use a hardcoded 8 (which is what the spec says should be
 647          * done).
 648          */
 649         if (wm_size <= 8)
 650                 wm_size = 8;
 651
 652         return wm_size;
 653 }
 654
 655 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 656 {
 657         struct drm_crtc *crtc, *enabled = NULL;
 658
 659         for_each_crtc(dev, crtc) {
 660                 if (intel_crtc_active(crtc)) {
 661                         if (enabled)
 662                                 return NULL;
 663                         enabled = crtc;
 664                 }
 665         }
 666
 667         return enabled;
 668 }
 669
 670 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 671 {
 672         struct drm_device *dev = unused_crtc->dev;
 673         struct drm_i915_private *dev_priv = dev->dev_private;
 674         struct drm_crtc *crtc;
 675         const struct cxsr_latency *latency;
 676         u32 reg;
 677         unsigned long wm;
 678
 679         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 680                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 681         if (!latency) {
 682                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 683                 intel_set_memory_cxsr(dev_priv, false);
 684                 return;
 685         }
 686
 687         crtc = single_enabled_crtc(dev);
 688         if (crtc) {
 689                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 690                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 691                 int clock = adjusted_mode->crtc_clock;
 692
 693                 /* Display SR */
 694                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 695                                         pineview_display_wm.fifo_size,
 696                                         pixel_size, latency->display_sr);
 697                 reg = I915_READ(DSPFW1);
 698                 reg &= ~DSPFW_SR_MASK;
 699                 reg |= FW_WM(wm, SR);
 700                 I915_WRITE(DSPFW1, reg);
 701                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 702
 703                 /* cursor SR */
 704                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 705                                         pineview_display_wm.fifo_size,
 706                                         pixel_size, latency->cursor_sr);
 707                 reg = I915_READ(DSPFW3);
 708                 reg &= ~DSPFW_CURSOR_SR_MASK;
 709                 reg |= FW_WM(wm, CURSOR_SR);
 710                 I915_WRITE(DSPFW3, reg);
 711
 712                 /* Display HPLL off SR */
 713                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 714                                         pineview_display_hplloff_wm.fifo_size,
 715                                         pixel_size, latency->display_hpll_disable);
 716                 reg = I915_READ(DSPFW3);
 717                 reg &= ~DSPFW_HPLL_SR_MASK;
 718                 reg |= FW_WM(wm, HPLL_SR);
 719                 I915_WRITE(DSPFW3, reg);
 720
 721                 /* cursor HPLL off SR */
 722                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 723                                         pineview_display_hplloff_wm.fifo_size,
 724                                         pixel_size, latency->cursor_hpll_disable);
 725                 reg = I915_READ(DSPFW3);
 726                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 727                 reg |= FW_WM(wm, HPLL_CURSOR);
 728                 I915_WRITE(DSPFW3, reg);
 729                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 730
 731                 intel_set_memory_cxsr(dev_priv, true);
 732         } else {
 733                 intel_set_memory_cxsr(dev_priv, false);
 734         }
 735 }
 736
 737 static bool g4x_compute_wm0(struct drm_device *dev,
 738                             int plane,
 739                             const struct intel_watermark_params *display,
 740                             int display_latency_ns,
 741                             const struct intel_watermark_params *cursor,
 742                             int cursor_latency_ns,
 743                             int *plane_wm,
 744                             int *cursor_wm)
 745 {
 746         struct drm_crtc *crtc;
 747         const struct drm_display_mode *adjusted_mode;
 748         int htotal, hdisplay, clock, pixel_size;
 749         int line_time_us, line_count;
 750         int entries, tlb_miss;
 751
 752         crtc = intel_get_crtc_for_plane(dev, plane);
 753         if (!intel_crtc_active(crtc)) {
 754                 *cursor_wm = cursor->guard_size;
 755                 *plane_wm = display->guard_size;
 756                 return false;
 757         }
 758
 759         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 760         clock = adjusted_mode->crtc_clock;
 761         htotal = adjusted_mode->crtc_htotal;
 762         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 763         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 764
 765         /* Use the small buffer method to calculate plane watermark */
 766         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 767         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 768         if (tlb_miss > 0)
 769                 entries += tlb_miss;
 770         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 771         *plane_wm = entries + display->guard_size;
 772         if (*plane_wm > (int)display->max_wm)
 773                 *plane_wm = display->max_wm;
 774
 775         /* Use the large buffer method to calculate cursor watermark */
 776         line_time_us = max(htotal * 1000 / clock, 1);
 777         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 778         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 779         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 780         if (tlb_miss > 0)
 781                 entries += tlb_miss;
 782         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 783         *cursor_wm = entries + cursor->guard_size;
 784         if (*cursor_wm > (int)cursor->max_wm)
 785                 *cursor_wm = (int)cursor->max_wm;
 786
 787         return true;
 788 }
 789
 790 /*
 791  * Check the wm result.
 792  *
 793  * If any calculated watermark values is larger than the maximum value that
 794  * can be programmed into the associated watermark register, that watermark
 795  * must be disabled.
 796  */
 797 static bool g4x_check_srwm(struct drm_device *dev,
 798                            int display_wm, int cursor_wm,
 799                            const struct intel_watermark_params *display,
 800                            const struct intel_watermark_params *cursor)
 801 {
 802         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 803                       display_wm, cursor_wm);
 804
 805         if (display_wm > display->max_wm) {
 806                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 807                               display_wm, display->max_wm);
 808                 return false;
 809         }
 810
 811         if (cursor_wm > cursor->max_wm) {
 812                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 813                               cursor_wm, cursor->max_wm);
 814                 return false;
 815         }
 816
 817         if (!(display_wm || cursor_wm)) {
 818                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 819                 return false;
 820         }
 821
 822         return true;
 823 }
 824
 825 static bool g4x_compute_srwm(struct drm_device *dev,
 826                              int plane,
 827                              int latency_ns,
 828                              const struct intel_watermark_params *display,
 829                              const struct intel_watermark_params *cursor,
 830                              int *display_wm, int *cursor_wm)
 831 {
 832         struct drm_crtc *crtc;
 833         const struct drm_display_mode *adjusted_mode;
 834         int hdisplay, htotal, pixel_size, clock;
 835         unsigned long line_time_us;
 836         int line_count, line_size;
 837         int small, large;
 838         int entries;
 839
 840         if (!latency_ns) {
 841                 *display_wm = *cursor_wm = 0;
 842                 return false;
 843         }
 844
 845         crtc = intel_get_crtc_for_plane(dev, plane);
 846         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 847         clock = adjusted_mode->crtc_clock;
 848         htotal = adjusted_mode->crtc_htotal;
 849         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 850         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 851
 852         line_time_us = max(htotal * 1000 / clock, 1);
 853         line_count = (latency_ns / line_time_us + 1000) / 1000;
 854         line_size = hdisplay * pixel_size;
 855
 856         /* Use the minimum of the small and large buffer method for primary */
 857         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 858         large = line_count * line_size;
 859
 860         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 861         *display_wm = entries + display->guard_size;
 862
 863         /* calculate the self-refresh watermark for display cursor */
 864         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 865         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 866         *cursor_wm = entries + cursor->guard_size;
 867
 868         return g4x_check_srwm(dev,
 869                               *display_wm, *cursor_wm,
 870                               display, cursor);
 871 }
 872
 873 #define FW_WM_VLV(value, plane) \
 874         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 875
 876 static void vlv_write_wm_values(struct intel_crtc *crtc,
 877                                 const struct vlv_wm_values *wm)
 878 {
 879         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 880         enum pipe pipe = crtc->pipe;
 881
 882         I915_WRITE(VLV_DDL(pipe),
 883                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 884                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 885                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 886                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 887
 888         I915_WRITE(DSPFW1,
 889                    FW_WM(wm->sr.plane, SR) |
 890                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 891                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 892                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 893         I915_WRITE(DSPFW2,
 894                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 895                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 896                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 897         I915_WRITE(DSPFW3,
 898                    FW_WM(wm->sr.cursor, CURSOR_SR));
 899
 900         if (IS_CHERRYVIEW(dev_priv)) {
 901                 I915_WRITE(DSPFW7_CHV,
 902                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 903                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 904                 I915_WRITE(DSPFW8_CHV,
 905                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 906                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 907                 I915_WRITE(DSPFW9_CHV,
 908                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 909                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 910                 I915_WRITE(DSPHOWM,
 911                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 912                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 913                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 914                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 915                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 916                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 917                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 918                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 919                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 920                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 921         } else {
 922                 I915_WRITE(DSPFW7,
 923                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 924                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 925                 I915_WRITE(DSPHOWM,
 926                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 927                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 928                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 929                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 930                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 931                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 932                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 933         }
 934
 935         /* zero (unused) WM1 watermarks */
 936         I915_WRITE(DSPFW4, 0);
 937         I915_WRITE(DSPFW5, 0);
 938         I915_WRITE(DSPFW6, 0);
 939         I915_WRITE(DSPHOWM1, 0);
 940
 941         POSTING_READ(DSPFW1);
 942 }
 943
 944 #undef FW_WM_VLV
 945
 946 enum vlv_wm_level {
 947         VLV_WM_LEVEL_PM2,
 948         VLV_WM_LEVEL_PM5,
 949         VLV_WM_LEVEL_DDR_DVFS,
 950 };
 951
 952 /* latency must be in 0.1us units. */
 953 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 954                                    unsigned int pipe_htotal,
 955                                    unsigned int horiz_pixels,
 956                                    unsigned int bytes_per_pixel,
 957                                    unsigned int latency)
 958 {
 959         unsigned int ret;
 960
 961         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 962         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 963         ret = DIV_ROUND_UP(ret, 64);
 964
 965         return ret;
 966 }
 967
 968 static void vlv_setup_wm_latency(struct drm_device *dev)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971
 972         /* all latencies in usec */
 973         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 974
 975         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 976
 977         if (IS_CHERRYVIEW(dev_priv)) {
 978                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 979                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 980
 981                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 982         }
 983 }
 984
 985 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 986                                      struct intel_crtc *crtc,
 987                                      const struct intel_plane_state *state,
 988                                      int level)
 989 {
 990         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 991         int clock, htotal, pixel_size, width, wm;
 992
 993         if (dev_priv->wm.pri_latency[level] == 0)
 994                 return USHRT_MAX;
 995
 996         if (!state->visible)
 997                 return 0;
 998
 999         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1000         clock = crtc->config->base.adjusted_mode.crtc_clock;
1001         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1002         width = crtc->config->pipe_src_w;
1003         if (WARN_ON(htotal == 0))
1004                 htotal = 1;
1005
1006         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1007                 /*
1008                  * FIXME the formula gives values that are
1009                  * too big for the cursor FIFO, and hence we
1010                  * would never be able to use cursors. For
1011                  * now just hardcode the watermark.
1012                  */
1013                 wm = 63;
1014         } else {
1015                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1016                                     dev_priv->wm.pri_latency[level] * 10);
1017         }
1018
1019         return min_t(int, wm, USHRT_MAX);
1020 }
1021
1022 static void vlv_compute_fifo(struct intel_crtc *crtc)
1023 {
1024         struct drm_device *dev = crtc->base.dev;
1025         struct vlv_wm_state *wm_state = &crtc->wm_state;
1026         struct intel_plane *plane;
1027         unsigned int total_rate = 0;
1028         const int fifo_size = 512 - 1;
1029         int fifo_extra, fifo_left = fifo_size;
1030
1031         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1032                 struct intel_plane_state *state =
1033                         to_intel_plane_state(plane->base.state);
1034
1035                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1036                         continue;
1037
1038                 if (state->visible) {
1039                         wm_state->num_active_planes++;
1040                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1041                 }
1042         }
1043
1044         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1045                 struct intel_plane_state *state =
1046                         to_intel_plane_state(plane->base.state);
1047                 unsigned int rate;
1048
1049                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1050                         plane->wm.fifo_size = 63;
1051                         continue;
1052                 }
1053
1054                 if (!state->visible) {
1055                         plane->wm.fifo_size = 0;
1056                         continue;
1057                 }
1058
1059                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1060                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1061                 fifo_left -= plane->wm.fifo_size;
1062         }
1063
1064         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1065
1066         /* spread the remainder evenly */
1067         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1068                 int plane_extra;
1069
1070                 if (fifo_left == 0)
1071                         break;
1072
1073                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1074                         continue;
1075
1076                 /* give it all to the first plane if none are active */
1077                 if (plane->wm.fifo_size == 0 &&
1078                     wm_state->num_active_planes)
1079                         continue;
1080
1081                 plane_extra = min(fifo_extra, fifo_left);
1082                 plane->wm.fifo_size += plane_extra;
1083                 fifo_left -= plane_extra;
1084         }
1085
1086         WARN_ON(fifo_left != 0);
1087 }
1088
1089 static void vlv_invert_wms(struct intel_crtc *crtc)
1090 {
1091         struct vlv_wm_state *wm_state = &crtc->wm_state;
1092         int level;
1093
1094         for (level = 0; level < wm_state->num_levels; level++) {
1095                 struct drm_device *dev = crtc->base.dev;
1096                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1097                 struct intel_plane *plane;
1098
1099                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1100                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1101
1102                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103                         switch (plane->base.type) {
1104                                 int sprite;
1105                         case DRM_PLANE_TYPE_CURSOR:
1106                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1107                                         wm_state->wm[level].cursor;
1108                                 break;
1109                         case DRM_PLANE_TYPE_PRIMARY:
1110                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1111                                         wm_state->wm[level].primary;
1112                                 break;
1113                         case DRM_PLANE_TYPE_OVERLAY:
1114                                 sprite = plane->plane;
1115                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1116                                         wm_state->wm[level].sprite[sprite];
1117                                 break;
1118                         }
1119                 }
1120         }
1121 }
1122
1123 static void vlv_compute_wm(struct intel_crtc *crtc)
1124 {
1125         struct drm_device *dev = crtc->base.dev;
1126         struct vlv_wm_state *wm_state = &crtc->wm_state;
1127         struct intel_plane *plane;
1128         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1129         int level;
1130
1131         memset(wm_state, 0, sizeof(*wm_state));
1132
1133         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1134         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1135
1136         wm_state->num_active_planes = 0;
1137
1138         vlv_compute_fifo(crtc);
1139
1140         if (wm_state->num_active_planes != 1)
1141                 wm_state->cxsr = false;
1142
1143         if (wm_state->cxsr) {
1144                 for (level = 0; level < wm_state->num_levels; level++) {
1145                         wm_state->sr[level].plane = sr_fifo_size;
1146                         wm_state->sr[level].cursor = 63;
1147                 }
1148         }
1149
1150         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1151                 struct intel_plane_state *state =
1152                         to_intel_plane_state(plane->base.state);
1153
1154                 if (!state->visible)
1155                         continue;
1156
1157                 /* normal watermarks */
1158                 for (level = 0; level < wm_state->num_levels; level++) {
1159                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1160                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1161
1162                         /* hack */
1163                         if (WARN_ON(level == 0 && wm > max_wm))
1164                                 wm = max_wm;
1165
1166                         if (wm > plane->wm.fifo_size)
1167                                 break;
1168
1169                         switch (plane->base.type) {
1170                                 int sprite;
1171                         case DRM_PLANE_TYPE_CURSOR:
1172                                 wm_state->wm[level].cursor = wm;
1173                                 break;
1174                         case DRM_PLANE_TYPE_PRIMARY:
1175                                 wm_state->wm[level].primary = wm;
1176                                 break;
1177                         case DRM_PLANE_TYPE_OVERLAY:
1178                                 sprite = plane->plane;
1179                                 wm_state->wm[level].sprite[sprite] = wm;
1180                                 break;
1181                         }
1182                 }
1183
1184                 wm_state->num_levels = level;
1185
1186                 if (!wm_state->cxsr)
1187                         continue;
1188
1189                 /* maxfifo watermarks */
1190                 switch (plane->base.type) {
1191                         int sprite, level;
1192                 case DRM_PLANE_TYPE_CURSOR:
1193                         for (level = 0; level < wm_state->num_levels; level++)
1194                                 wm_state->sr[level].cursor =
1195                                         wm_state->sr[level].cursor;
1196                         break;
1197                 case DRM_PLANE_TYPE_PRIMARY:
1198                         for (level = 0; level < wm_state->num_levels; level++)
1199                                 wm_state->sr[level].plane =
1200                                         min(wm_state->sr[level].plane,
1201                                             wm_state->wm[level].primary);
1202                         break;
1203                 case DRM_PLANE_TYPE_OVERLAY:
1204                         sprite = plane->plane;
1205                         for (level = 0; level < wm_state->num_levels; level++)
1206                                 wm_state->sr[level].plane =
1207                                         min(wm_state->sr[level].plane,
1208                                             wm_state->wm[level].sprite[sprite]);
1209                         break;
1210                 }
1211         }
1212
1213         /* clear any (partially) filled invalid levels */
1214         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1215                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1216                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1217         }
1218
1219         vlv_invert_wms(crtc);
1220 }
1221
1222 #define VLV_FIFO(plane, value) \
1223         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1224
1225 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1226 {
1227         struct drm_device *dev = crtc->base.dev;
1228         struct drm_i915_private *dev_priv = to_i915(dev);
1229         struct intel_plane *plane;
1230         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1231
1232         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1233                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1234                         WARN_ON(plane->wm.fifo_size != 63);
1235                         continue;
1236                 }
1237
1238                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1239                         sprite0_start = plane->wm.fifo_size;
1240                 else if (plane->plane == 0)
1241                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1242                 else
1243                         fifo_size = sprite1_start + plane->wm.fifo_size;
1244         }
1245
1246         WARN_ON(fifo_size != 512 - 1);
1247
1248         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1249                       pipe_name(crtc->pipe), sprite0_start,
1250                       sprite1_start, fifo_size);
1251
1252         switch (crtc->pipe) {
1253                 uint32_t dsparb, dsparb2, dsparb3;
1254         case PIPE_A:
1255                 dsparb = I915_READ(DSPARB);
1256                 dsparb2 = I915_READ(DSPARB2);
1257
1258                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1259                             VLV_FIFO(SPRITEB, 0xff));
1260                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1261                            VLV_FIFO(SPRITEB, sprite1_start));
1262
1263                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1264                              VLV_FIFO(SPRITEB_HI, 0x1));
1265                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1266                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1267
1268                 I915_WRITE(DSPARB, dsparb);
1269                 I915_WRITE(DSPARB2, dsparb2);
1270                 break;
1271         case PIPE_B:
1272                 dsparb = I915_READ(DSPARB);
1273                 dsparb2 = I915_READ(DSPARB2);
1274
1275                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1276                             VLV_FIFO(SPRITED, 0xff));
1277                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1278                            VLV_FIFO(SPRITED, sprite1_start));
1279
1280                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1281                              VLV_FIFO(SPRITED_HI, 0xff));
1282                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1283                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1284
1285                 I915_WRITE(DSPARB, dsparb);
1286                 I915_WRITE(DSPARB2, dsparb2);
1287                 break;
1288         case PIPE_C:
1289                 dsparb3 = I915_READ(DSPARB3);
1290                 dsparb2 = I915_READ(DSPARB2);
1291
1292                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1293                              VLV_FIFO(SPRITEF, 0xff));
1294                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1295                             VLV_FIFO(SPRITEF, sprite1_start));
1296
1297                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1298                              VLV_FIFO(SPRITEF_HI, 0xff));
1299                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1300                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1301
1302                 I915_WRITE(DSPARB3, dsparb3);
1303                 I915_WRITE(DSPARB2, dsparb2);
1304                 break;
1305         default:
1306                 break;
1307         }
1308 }
1309
1310 #undef VLV_FIFO
1311
1312 static void vlv_merge_wm(struct drm_device *dev,
1313                          struct vlv_wm_values *wm)
1314 {
1315         struct intel_crtc *crtc;
1316         int num_active_crtcs = 0;
1317
1318         wm->level = to_i915(dev)->wm.max_level;
1319         wm->cxsr = true;
1320
1321         for_each_intel_crtc(dev, crtc) {
1322                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1323
1324                 if (!crtc->active)
1325                         continue;
1326
1327                 if (!wm_state->cxsr)
1328                         wm->cxsr = false;
1329
1330                 num_active_crtcs++;
1331                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1332         }
1333
1334         if (num_active_crtcs != 1)
1335                 wm->cxsr = false;
1336
1337         if (num_active_crtcs > 1)
1338                 wm->level = VLV_WM_LEVEL_PM2;
1339
1340         for_each_intel_crtc(dev, crtc) {
1341                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1342                 enum pipe pipe = crtc->pipe;
1343
1344                 if (!crtc->active)
1345                         continue;
1346
1347                 wm->pipe[pipe] = wm_state->wm[wm->level];
1348                 if (wm->cxsr)
1349                         wm->sr = wm_state->sr[wm->level];
1350
1351                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1352                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1353                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1354                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1355         }
1356 }
1357
1358 static void vlv_update_wm(struct drm_crtc *crtc)
1359 {
1360         struct drm_device *dev = crtc->dev;
1361         struct drm_i915_private *dev_priv = dev->dev_private;
1362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1363         enum pipe pipe = intel_crtc->pipe;
1364         struct vlv_wm_values wm = {};
1365
1366         vlv_compute_wm(intel_crtc);
1367         vlv_merge_wm(dev, &wm);
1368
1369         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1370                 /* FIXME should be part of crtc atomic commit */
1371                 vlv_pipe_set_fifo_size(intel_crtc);
1372                 return;
1373         }
1374
1375         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1376             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1377                 chv_set_memory_dvfs(dev_priv, false);
1378
1379         if (wm.level < VLV_WM_LEVEL_PM5 &&
1380             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1381                 chv_set_memory_pm5(dev_priv, false);
1382
1383         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1384                 intel_set_memory_cxsr(dev_priv, false);
1385
1386         /* FIXME should be part of crtc atomic commit */
1387         vlv_pipe_set_fifo_size(intel_crtc);
1388
1389         vlv_write_wm_values(intel_crtc, &wm);
1390
1391         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1392                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1393                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1394                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1395                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1396
1397         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1398                 intel_set_memory_cxsr(dev_priv, true);
1399
1400         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1401             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1402                 chv_set_memory_pm5(dev_priv, true);
1403
1404         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1405             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1406                 chv_set_memory_dvfs(dev_priv, true);
1407
1408         dev_priv->wm.vlv = wm;
1409 }
1410
1411 #define single_plane_enabled(mask) is_power_of_2(mask)
1412
1413 static void g4x_update_wm(struct drm_crtc *crtc)
1414 {
1415         struct drm_device *dev = crtc->dev;
1416         static const int sr_latency_ns = 12000;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1419         int plane_sr, cursor_sr;
1420         unsigned int enabled = 0;
1421         bool cxsr_enabled;
1422
1423         if (g4x_compute_wm0(dev, PIPE_A,
1424                             &g4x_wm_info, pessimal_latency_ns,
1425                             &g4x_cursor_wm_info, pessimal_latency_ns,
1426                             &planea_wm, &cursora_wm))
1427                 enabled |= 1 << PIPE_A;
1428
1429         if (g4x_compute_wm0(dev, PIPE_B,
1430                             &g4x_wm_info, pessimal_latency_ns,
1431                             &g4x_cursor_wm_info, pessimal_latency_ns,
1432                             &planeb_wm, &cursorb_wm))
1433                 enabled |= 1 << PIPE_B;
1434
1435         if (single_plane_enabled(enabled) &&
1436             g4x_compute_srwm(dev, ffs(enabled) - 1,
1437                              sr_latency_ns,
1438                              &g4x_wm_info,
1439                              &g4x_cursor_wm_info,
1440                              &plane_sr, &cursor_sr)) {
1441                 cxsr_enabled = true;
1442         } else {
1443                 cxsr_enabled = false;
1444                 intel_set_memory_cxsr(dev_priv, false);
1445                 plane_sr = cursor_sr = 0;
1446         }
1447
1448         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1449                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1450                       planea_wm, cursora_wm,
1451                       planeb_wm, cursorb_wm,
1452                       plane_sr, cursor_sr);
1453
1454         I915_WRITE(DSPFW1,
1455                    FW_WM(plane_sr, SR) |
1456                    FW_WM(cursorb_wm, CURSORB) |
1457                    FW_WM(planeb_wm, PLANEB) |
1458                    FW_WM(planea_wm, PLANEA));
1459         I915_WRITE(DSPFW2,
1460                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1461                    FW_WM(cursora_wm, CURSORA));
1462         /* HPLL off in SR has some issues on G4x... disable it */
1463         I915_WRITE(DSPFW3,
1464                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1465                    FW_WM(cursor_sr, CURSOR_SR));
1466
1467         if (cxsr_enabled)
1468                 intel_set_memory_cxsr(dev_priv, true);
1469 }
1470
1471 static void i965_update_wm(struct drm_crtc *unused_crtc)
1472 {
1473         struct drm_device *dev = unused_crtc->dev;
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         struct drm_crtc *crtc;
1476         int srwm = 1;
1477         int cursor_sr = 16;
1478         bool cxsr_enabled;
1479
1480         /* Calc sr entries for one plane configs */
1481         crtc = single_enabled_crtc(dev);
1482         if (crtc) {
1483                 /* self-refresh has much higher latency */
1484                 static const int sr_latency_ns = 12000;
1485                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1486                 int clock = adjusted_mode->crtc_clock;
1487                 int htotal = adjusted_mode->crtc_htotal;
1488                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1489                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1490                 unsigned long line_time_us;
1491                 int entries;
1492
1493                 line_time_us = max(htotal * 1000 / clock, 1);
1494
1495                 /* Use ns/us then divide to preserve precision */
1496                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1497                         pixel_size * hdisplay;
1498                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1499                 srwm = I965_FIFO_SIZE - entries;
1500                 if (srwm < 0)
1501                         srwm = 1;
1502                 srwm &= 0x1ff;
1503                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1504                               entries, srwm);
1505
1506                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1507                         pixel_size * crtc->cursor->state->crtc_w;
1508                 entries = DIV_ROUND_UP(entries,
1509                                           i965_cursor_wm_info.cacheline_size);
1510                 cursor_sr = i965_cursor_wm_info.fifo_size -
1511                         (entries + i965_cursor_wm_info.guard_size);
1512
1513                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1514                         cursor_sr = i965_cursor_wm_info.max_wm;
1515
1516                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1517                               "cursor %d\n", srwm, cursor_sr);
1518
1519                 cxsr_enabled = true;
1520         } else {
1521                 cxsr_enabled = false;
1522                 /* Turn off self refresh if both pipes are enabled */
1523                 intel_set_memory_cxsr(dev_priv, false);
1524         }
1525
1526         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1527                       srwm);
1528
1529         /* 965 has limitations... */
1530         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1531                    FW_WM(8, CURSORB) |
1532                    FW_WM(8, PLANEB) |
1533                    FW_WM(8, PLANEA));
1534         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1535                    FW_WM(8, PLANEC_OLD));
1536         /* update cursor SR watermark */
1537         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1538
1539         if (cxsr_enabled)
1540                 intel_set_memory_cxsr(dev_priv, true);
1541 }
1542
1543 #undef FW_WM
1544
1545 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1546 {
1547         struct drm_device *dev = unused_crtc->dev;
1548         struct drm_i915_private *dev_priv = dev->dev_private;
1549         const struct intel_watermark_params *wm_info;
1550         uint32_t fwater_lo;
1551         uint32_t fwater_hi;
1552         int cwm, srwm = 1;
1553         int fifo_size;
1554         int planea_wm, planeb_wm;
1555         struct drm_crtc *crtc, *enabled = NULL;
1556
1557         if (IS_I945GM(dev))
1558                 wm_info = &i945_wm_info;
1559         else if (!IS_GEN2(dev))
1560                 wm_info = &i915_wm_info;
1561         else
1562                 wm_info = &i830_a_wm_info;
1563
1564         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1565         crtc = intel_get_crtc_for_plane(dev, 0);
1566         if (intel_crtc_active(crtc)) {
1567                 const struct drm_display_mode *adjusted_mode;
1568                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1569                 if (IS_GEN2(dev))
1570                         cpp = 4;
1571
1572                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1573                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1574                                                wm_info, fifo_size, cpp,
1575                                                pessimal_latency_ns);
1576                 enabled = crtc;
1577         } else {
1578                 planea_wm = fifo_size - wm_info->guard_size;
1579                 if (planea_wm > (long)wm_info->max_wm)
1580                         planea_wm = wm_info->max_wm;
1581         }
1582
1583         if (IS_GEN2(dev))
1584                 wm_info = &i830_bc_wm_info;
1585
1586         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1587         crtc = intel_get_crtc_for_plane(dev, 1);
1588         if (intel_crtc_active(crtc)) {
1589                 const struct drm_display_mode *adjusted_mode;
1590                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1591                 if (IS_GEN2(dev))
1592                         cpp = 4;
1593
1594                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1595                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1596                                                wm_info, fifo_size, cpp,
1597                                                pessimal_latency_ns);
1598                 if (enabled == NULL)
1599                         enabled = crtc;
1600                 else
1601                         enabled = NULL;
1602         } else {
1603                 planeb_wm = fifo_size - wm_info->guard_size;
1604                 if (planeb_wm > (long)wm_info->max_wm)
1605                         planeb_wm = wm_info->max_wm;
1606         }
1607
1608         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1609
1610         if (IS_I915GM(dev) && enabled) {
1611                 struct drm_i915_gem_object *obj;
1612
1613                 obj = intel_fb_obj(enabled->primary->state->fb);
1614
1615                 /* self-refresh seems busted with untiled */
1616                 if (obj->tiling_mode == I915_TILING_NONE)
1617                         enabled = NULL;
1618         }
1619
1620         /*
1621          * Overlay gets an aggressive default since video jitter is bad.
1622          */
1623         cwm = 2;
1624
1625         /* Play safe and disable self-refresh before adjusting watermarks. */
1626         intel_set_memory_cxsr(dev_priv, false);
1627
1628         /* Calc sr entries for one plane configs */
1629         if (HAS_FW_BLC(dev) && enabled) {
1630                 /* self-refresh has much higher latency */
1631                 static const int sr_latency_ns = 6000;
1632                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1633                 int clock = adjusted_mode->crtc_clock;
1634                 int htotal = adjusted_mode->crtc_htotal;
1635                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1636                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1637                 unsigned long line_time_us;
1638                 int entries;
1639
1640                 line_time_us = max(htotal * 1000 / clock, 1);
1641
1642                 /* Use ns/us then divide to preserve precision */
1643                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1644                         pixel_size * hdisplay;
1645                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647                 srwm = wm_info->fifo_size - entries;
1648                 if (srwm < 0)
1649                         srwm = 1;
1650
1651                 if (IS_I945G(dev) || IS_I945GM(dev))
1652                         I915_WRITE(FW_BLC_SELF,
1653                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1654                 else if (IS_I915GM(dev))
1655                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656         }
1657
1658         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659                       planea_wm, planeb_wm, cwm, srwm);
1660
1661         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662         fwater_hi = (cwm & 0x1f);
1663
1664         /* Set request length to 8 cachelines per fetch */
1665         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666         fwater_hi = fwater_hi | (1 << 8);
1667
1668         I915_WRITE(FW_BLC, fwater_lo);
1669         I915_WRITE(FW_BLC2, fwater_hi);
1670
1671         if (enabled)
1672                 intel_set_memory_cxsr(dev_priv, true);
1673 }
1674
1675 static void i845_update_wm(struct drm_crtc *unused_crtc)
1676 {
1677         struct drm_device *dev = unused_crtc->dev;
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679         struct drm_crtc *crtc;
1680         const struct drm_display_mode *adjusted_mode;
1681         uint32_t fwater_lo;
1682         int planea_wm;
1683
1684         crtc = single_enabled_crtc(dev);
1685         if (crtc == NULL)
1686                 return;
1687
1688         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1689         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1690                                        &i845_wm_info,
1691                                        dev_priv->display.get_fifo_size(dev, 0),
1692                                        4, pessimal_latency_ns);
1693         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1694         fwater_lo |= (3<<8) | planea_wm;
1695
1696         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1697
1698         I915_WRITE(FW_BLC, fwater_lo);
1699 }
1700
1701 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1702 {
1703         uint32_t pixel_rate;
1704
1705         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1706
1707         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1708          * adjust the pixel_rate here. */
1709
1710         if (pipe_config->pch_pfit.enabled) {
1711                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1712                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1713
1714                 pipe_w = pipe_config->pipe_src_w;
1715                 pipe_h = pipe_config->pipe_src_h;
1716
1717                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1718                 pfit_h = pfit_size & 0xFFFF;
1719                 if (pipe_w < pfit_w)
1720                         pipe_w = pfit_w;
1721                 if (pipe_h < pfit_h)
1722                         pipe_h = pfit_h;
1723
1724                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1725                                      pfit_w * pfit_h);
1726         }
1727
1728         return pixel_rate;
1729 }
1730
1731 /* latency must be in 0.1us units. */
1732 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1733                                uint32_t latency)
1734 {
1735         uint64_t ret;
1736
1737         if (WARN(latency == 0, "Latency value missing\n"))
1738                 return UINT_MAX;
1739
1740         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1741         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1742
1743         return ret;
1744 }
1745
1746 /* latency must be in 0.1us units. */
1747 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1748                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1749                                uint32_t latency)
1750 {
1751         uint32_t ret;
1752
1753         if (WARN(latency == 0, "Latency value missing\n"))
1754                 return UINT_MAX;
1755
1756         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1757         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1758         ret = DIV_ROUND_UP(ret, 64) + 2;
1759         return ret;
1760 }
1761
1762 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1763                            uint8_t bytes_per_pixel)
1764 {
1765         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1766 }
1767
1768 struct ilk_wm_maximums {
1769         uint16_t pri;
1770         uint16_t spr;
1771         uint16_t cur;
1772         uint16_t fbc;
1773 };
1774
1775 /* used in computing the new watermarks state */
1776 struct intel_wm_config {
1777         unsigned int num_pipes_active;
1778         bool sprites_enabled;
1779         bool sprites_scaled;
1780 };
1781
1782 /*
1783  * For both WM_PIPE and WM_LP.
1784  * mem_value must be in 0.1us units.
1785  */
1786 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1787                                    const struct intel_plane_state *pstate,
1788                                    uint32_t mem_value,
1789                                    bool is_lp)
1790 {
1791         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1792         uint32_t method1, method2;
1793
1794         if (!cstate->base.active || !pstate->visible)
1795                 return 0;
1796
1797         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1798
1799         if (!is_lp)
1800                 return method1;
1801
1802         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1803                                  cstate->base.adjusted_mode.crtc_htotal,
1804                                  drm_rect_width(&pstate->dst),
1805                                  bpp,
1806                                  mem_value);
1807
1808         return min(method1, method2);
1809 }
1810
1811 /*
1812  * For both WM_PIPE and WM_LP.
1813  * mem_value must be in 0.1us units.
1814  */
1815 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1816                                    const struct intel_plane_state *pstate,
1817                                    uint32_t mem_value)
1818 {
1819         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1820         uint32_t method1, method2;
1821
1822         if (!cstate->base.active || !pstate->visible)
1823                 return 0;
1824
1825         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1826         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1827                                  cstate->base.adjusted_mode.crtc_htotal,
1828                                  drm_rect_width(&pstate->dst),
1829                                  bpp,
1830                                  mem_value);
1831         return min(method1, method2);
1832 }
1833
1834 /*
1835  * For both WM_PIPE and WM_LP.
1836  * mem_value must be in 0.1us units.
1837  */
1838 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1839                                    const struct intel_plane_state *pstate,
1840                                    uint32_t mem_value)
1841 {
1842         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1843
1844         if (!cstate->base.active || !pstate->visible)
1845                 return 0;
1846
1847         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1848                               cstate->base.adjusted_mode.crtc_htotal,
1849                               drm_rect_width(&pstate->dst),
1850                               bpp,
1851                               mem_value);
1852 }
1853
1854 /* Only for WM_LP. */
1855 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1856                                    const struct intel_plane_state *pstate,
1857                                    uint32_t pri_val)
1858 {
1859         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1860
1861         if (!cstate->base.active || !pstate->visible)
1862                 return 0;
1863
1864         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1865 }
1866
1867 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1868 {
1869         if (INTEL_INFO(dev)->gen >= 8)
1870                 return 3072;
1871         else if (INTEL_INFO(dev)->gen >= 7)
1872                 return 768;
1873         else
1874                 return 512;
1875 }
1876
1877 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1878                                          int level, bool is_sprite)
1879 {
1880         if (INTEL_INFO(dev)->gen >= 8)
1881                 /* BDW primary/sprite plane watermarks */
1882                 return level == 0 ? 255 : 2047;
1883         else if (INTEL_INFO(dev)->gen >= 7)
1884                 /* IVB/HSW primary/sprite plane watermarks */
1885                 return level == 0 ? 127 : 1023;
1886         else if (!is_sprite)
1887                 /* ILK/SNB primary plane watermarks */
1888                 return level == 0 ? 127 : 511;
1889         else
1890                 /* ILK/SNB sprite plane watermarks */
1891                 return level == 0 ? 63 : 255;
1892 }
1893
1894 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1895                                           int level)
1896 {
1897         if (INTEL_INFO(dev)->gen >= 7)
1898                 return level == 0 ? 63 : 255;
1899         else
1900                 return level == 0 ? 31 : 63;
1901 }
1902
1903 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1904 {
1905         if (INTEL_INFO(dev)->gen >= 8)
1906                 return 31;
1907         else
1908                 return 15;
1909 }
1910
1911 /* Calculate the maximum primary/sprite plane watermark */
1912 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1913                                      int level,
1914                                      const struct intel_wm_config *config,
1915                                      enum intel_ddb_partitioning ddb_partitioning,
1916                                      bool is_sprite)
1917 {
1918         unsigned int fifo_size = ilk_display_fifo_size(dev);
1919
1920         /* if sprites aren't enabled, sprites get nothing */
1921         if (is_sprite && !config->sprites_enabled)
1922                 return 0;
1923
1924         /* HSW allows LP1+ watermarks even with multiple pipes */
1925         if (level == 0 || config->num_pipes_active > 1) {
1926                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1927
1928                 /*
1929                  * For some reason the non self refresh
1930                  * FIFO size is only half of the self
1931                  * refresh FIFO size on ILK/SNB.
1932                  */
1933                 if (INTEL_INFO(dev)->gen <= 6)
1934                         fifo_size /= 2;
1935         }
1936
1937         if (config->sprites_enabled) {
1938                 /* level 0 is always calculated with 1:1 split */
1939                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1940                         if (is_sprite)
1941                                 fifo_size *= 5;
1942                         fifo_size /= 6;
1943                 } else {
1944                         fifo_size /= 2;
1945                 }
1946         }
1947
1948         /* clamp to max that the registers can hold */
1949         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1950 }
1951
1952 /* Calculate the maximum cursor plane watermark */
1953 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1954                                       int level,
1955                                       const struct intel_wm_config *config)
1956 {
1957         /* HSW LP1+ watermarks w/ multiple pipes */
1958         if (level > 0 && config->num_pipes_active > 1)
1959                 return 64;
1960
1961         /* otherwise just report max that registers can hold */
1962         return ilk_cursor_wm_reg_max(dev, level);
1963 }
1964
1965 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1966                                     int level,
1967                                     const struct intel_wm_config *config,
1968                                     enum intel_ddb_partitioning ddb_partitioning,
1969                                     struct ilk_wm_maximums *max)
1970 {
1971         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1972         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1973         max->cur = ilk_cursor_wm_max(dev, level, config);
1974         max->fbc = ilk_fbc_wm_reg_max(dev);
1975 }
1976
1977 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1978                                         int level,
1979                                         struct ilk_wm_maximums *max)
1980 {
1981         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1982         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1983         max->cur = ilk_cursor_wm_reg_max(dev, level);
1984         max->fbc = ilk_fbc_wm_reg_max(dev);
1985 }
1986
1987 static bool ilk_validate_wm_level(int level,
1988                                   const struct ilk_wm_maximums *max,
1989                                   struct intel_wm_level *result)
1990 {
1991         bool ret;
1992
1993         /* already determined to be invalid? */
1994         if (!result->enable)
1995                 return false;
1996
1997         result->enable = result->pri_val <= max->pri &&
1998                          result->spr_val <= max->spr &&
1999                          result->cur_val <= max->cur;
2000
2001         ret = result->enable;
2002
2003         /*
2004          * HACK until we can pre-compute everything,
2005          * and thus fail gracefully if LP0 watermarks
2006          * are exceeded...
2007          */
2008         if (level == 0 && !result->enable) {
2009                 if (result->pri_val > max->pri)
2010                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2011                                       level, result->pri_val, max->pri);
2012                 if (result->spr_val > max->spr)
2013                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2014                                       level, result->spr_val, max->spr);
2015                 if (result->cur_val > max->cur)
2016                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2017                                       level, result->cur_val, max->cur);
2018
2019                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2020                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2021                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2022                 result->enable = true;
2023         }
2024
2025         return ret;
2026 }
2027
2028 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2029                                  const struct intel_crtc *intel_crtc,
2030                                  int level,
2031                                  struct intel_crtc_state *cstate,
2032                                  struct intel_wm_level *result)
2033 {
2034         struct intel_plane *intel_plane;
2035         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2036         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2037         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2038
2039         /* WM1+ latency values stored in 0.5us units */
2040         if (level > 0) {
2041                 pri_latency *= 5;
2042                 spr_latency *= 5;
2043                 cur_latency *= 5;
2044         }
2045
2046         for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {
2047                 struct intel_plane_state *pstate =
2048                         to_intel_plane_state(intel_plane->base.state);
2049
2050                 switch (intel_plane->base.type) {
2051                 case DRM_PLANE_TYPE_PRIMARY:
2052                         result->pri_val = ilk_compute_pri_wm(cstate, pstate,
2053                                                              pri_latency,
2054                                                              level);
2055                         result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
2056                                                              result->pri_val);
2057                         break;
2058                 case DRM_PLANE_TYPE_OVERLAY:
2059                         result->spr_val = ilk_compute_spr_wm(cstate, pstate,
2060                                                              spr_latency);
2061                         break;
2062                 case DRM_PLANE_TYPE_CURSOR:
2063                         result->cur_val = ilk_compute_cur_wm(cstate, pstate,
2064                                                              cur_latency);
2065                         break;
2066                 }
2067         }
2068
2069         result->enable = true;
2070 }
2071
2072 static uint32_t
2073 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2074 {
2075         struct drm_i915_private *dev_priv = dev->dev_private;
2076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
2078         u32 linetime, ips_linetime;
2079
2080         if (!intel_crtc->active)
2081                 return 0;
2082
2083         /* The WM are computed with base on how long it takes to fill a single
2084          * row at the given clock rate, multiplied by 8.
2085          * */
2086         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2087                                      adjusted_mode->crtc_clock);
2088         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2089                                          dev_priv->cdclk_freq);
2090
2091         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2092                PIPE_WM_LINETIME_TIME(linetime);
2093 }
2094
2095 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2096 {
2097         struct drm_i915_private *dev_priv = dev->dev_private;
2098
2099         if (IS_GEN9(dev)) {
2100                 uint32_t val;
2101                 int ret, i;
2102                 int level, max_level = ilk_wm_max_level(dev);
2103
2104                 /* read the first set of memory latencies[0:3] */
2105                 val = 0; /* data0 to be programmed to 0 for first set */
2106                 mutex_lock(&dev_priv->rps.hw_lock);
2107                 ret = sandybridge_pcode_read(dev_priv,
2108                                              GEN9_PCODE_READ_MEM_LATENCY,
2109                                              &val);
2110                 mutex_unlock(&dev_priv->rps.hw_lock);
2111
2112                 if (ret) {
2113                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2114                         return;
2115                 }
2116
2117                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2118                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2119                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2120                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2121                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2122                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2123                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2124
2125                 /* read the second set of memory latencies[4:7] */
2126                 val = 1; /* data0 to be programmed to 1 for second set */
2127                 mutex_lock(&dev_priv->rps.hw_lock);
2128                 ret = sandybridge_pcode_read(dev_priv,
2129                                              GEN9_PCODE_READ_MEM_LATENCY,
2130                                              &val);
2131                 mutex_unlock(&dev_priv->rps.hw_lock);
2132                 if (ret) {
2133                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2134                         return;
2135                 }
2136
2137                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2138                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2139                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2140                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2141                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2142                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2143                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2144
2145                 /*
2146                  * WaWmMemoryReadLatency:skl
2147                  *
2148                  * punit doesn't take into account the read latency so we need
2149                  * to add 2us to the various latency levels we retrieve from
2150                  * the punit.
2151                  *   - W0 is a bit special in that it's the only level that
2152                  *   can't be disabled if we want to have display working, so
2153                  *   we always add 2us there.
2154                  *   - For levels >=1, punit returns 0us latency when they are
2155                  *   disabled, so we respect that and don't add 2us then
2156                  *
2157                  * Additionally, if a level n (n > 1) has a 0us latency, all
2158                  * levels m (m >= n) need to be disabled. We make sure to
2159                  * sanitize the values out of the punit to satisfy this
2160                  * requirement.
2161                  */
2162                 wm[0] += 2;
2163                 for (level = 1; level <= max_level; level++)
2164                         if (wm[level] != 0)
2165                                 wm[level] += 2;
2166                         else {
2167                                 for (i = level + 1; i <= max_level; i++)
2168                                         wm[i] = 0;
2169
2170                                 break;
2171                         }
2172         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2173                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2174
2175                 wm[0] = (sskpd >> 56) & 0xFF;
2176                 if (wm[0] == 0)
2177                         wm[0] = sskpd & 0xF;
2178                 wm[1] = (sskpd >> 4) & 0xFF;
2179                 wm[2] = (sskpd >> 12) & 0xFF;
2180                 wm[3] = (sskpd >> 20) & 0x1FF;
2181                 wm[4] = (sskpd >> 32) & 0x1FF;
2182         } else if (INTEL_INFO(dev)->gen >= 6) {
2183                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2184
2185                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2186                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2187                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2188                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2189         } else if (INTEL_INFO(dev)->gen >= 5) {
2190                 uint32_t mltr = I915_READ(MLTR_ILK);
2191
2192                 /* ILK primary LP0 latency is 700 ns */
2193                 wm[0] = 7;
2194                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2195                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2196         }
2197 }
2198
2199 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2200 {
2201         /* ILK sprite LP0 latency is 1300 ns */
2202         if (INTEL_INFO(dev)->gen == 5)
2203                 wm[0] = 13;
2204 }
2205
2206 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2207 {
2208         /* ILK cursor LP0 latency is 1300 ns */
2209         if (INTEL_INFO(dev)->gen == 5)
2210                 wm[0] = 13;
2211
2212         /* WaDoubleCursorLP3Latency:ivb */
2213         if (IS_IVYBRIDGE(dev))
2214                 wm[3] *= 2;
2215 }
2216
2217 int ilk_wm_max_level(const struct drm_device *dev)
2218 {
2219         /* how many WM levels are we expecting */
2220         if (INTEL_INFO(dev)->gen >= 9)
2221                 return 7;
2222         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2223                 return 4;
2224         else if (INTEL_INFO(dev)->gen >= 6)
2225                 return 3;
2226         else
2227                 return 2;
2228 }
2229
2230 static void intel_print_wm_latency(struct drm_device *dev,
2231                                    const char *name,
2232                                    const uint16_t wm[8])
2233 {
2234         int level, max_level = ilk_wm_max_level(dev);
2235
2236         for (level = 0; level <= max_level; level++) {
2237                 unsigned int latency = wm[level];
2238
2239                 if (latency == 0) {
2240                         DRM_ERROR("%s WM%d latency not provided\n",
2241                                   name, level);
2242                         continue;
2243                 }
2244
2245                 /*
2246                  * - latencies are in us on gen9.
2247                  * - before then, WM1+ latency values are in 0.5us units
2248                  */
2249                 if (IS_GEN9(dev))
2250                         latency *= 10;
2251                 else if (level > 0)
2252                         latency *= 5;
2253
2254                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2255                               name, level, wm[level],
2256                               latency / 10, latency % 10);
2257         }
2258 }
2259
2260 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2261                                     uint16_t wm[5], uint16_t min)
2262 {
2263         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2264
2265         if (wm[0] >= min)
2266                 return false;
2267
2268         wm[0] = max(wm[0], min);
2269         for (level = 1; level <= max_level; level++)
2270                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2271
2272         return true;
2273 }
2274
2275 static void snb_wm_latency_quirk(struct drm_device *dev)
2276 {
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         bool changed;
2279
2280         /*
2281          * The BIOS provided WM memory latency values are often
2282          * inadequate for high resolution displays. Adjust them.
2283          */
2284         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2285                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2286                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2287
2288         if (!changed)
2289                 return;
2290
2291         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2292         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2293         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2294         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2295 }
2296
2297 static void ilk_setup_wm_latency(struct drm_device *dev)
2298 {
2299         struct drm_i915_private *dev_priv = dev->dev_private;
2300
2301         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2302
2303         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2304                sizeof(dev_priv->wm.pri_latency));
2305         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2306                sizeof(dev_priv->wm.pri_latency));
2307
2308         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2309         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2310
2311         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2312         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2313         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2314
2315         if (IS_GEN6(dev))
2316                 snb_wm_latency_quirk(dev);
2317 }
2318
2319 static void skl_setup_wm_latency(struct drm_device *dev)
2320 {
2321         struct drm_i915_private *dev_priv = dev->dev_private;
2322
2323         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2324         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2325 }
2326
2327 static void ilk_compute_wm_config(struct drm_device *dev,
2328                                   struct intel_wm_config *config)
2329 {
2330         struct intel_crtc *intel_crtc;
2331
2332         /* Compute the currently _active_ config */
2333         for_each_intel_crtc(dev, intel_crtc) {
2334                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2335
2336                 if (!wm->pipe_enabled)
2337                         continue;
2338
2339                 config->sprites_enabled |= wm->sprites_enabled;
2340                 config->sprites_scaled |= wm->sprites_scaled;
2341                 config->num_pipes_active++;
2342         }
2343 }
2344
2345 /* Compute new watermarks for the pipe */
2346 static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
2347                                   struct intel_pipe_wm *pipe_wm)
2348 {
2349         struct drm_crtc *crtc = cstate->base.crtc;
2350         struct drm_device *dev = crtc->dev;
2351         const struct drm_i915_private *dev_priv = dev->dev_private;
2352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2353         struct intel_plane *intel_plane;
2354         struct intel_plane_state *sprstate = NULL;
2355         int level, max_level = ilk_wm_max_level(dev);
2356         /* LP0 watermark maximums depend on this pipe alone */
2357         struct intel_wm_config config = {
2358                 .num_pipes_active = 1,
2359         };
2360         struct ilk_wm_maximums max;
2361
2362         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2363                 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
2364                         sprstate = to_intel_plane_state(intel_plane->base.state);
2365                         break;
2366                 }
2367         }
2368
2369         config.sprites_enabled = sprstate->visible;
2370         config.sprites_scaled = sprstate->visible &&
2371                 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2372                 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2373
2374         pipe_wm->pipe_enabled = cstate->base.active;
2375         pipe_wm->sprites_enabled = sprstate->visible;
2376         pipe_wm->sprites_scaled = config.sprites_scaled;
2377
2378         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2379         if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2380                 max_level = 1;
2381
2382         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2383         if (config.sprites_scaled)
2384                 max_level = 0;
2385
2386         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
2387
2388         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2389                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2390
2391         /* LP0 watermarks always use 1/2 DDB partitioning */
2392         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2393
2394         /* At least LP0 must be valid */
2395         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2396                 return false;
2397
2398         ilk_compute_wm_reg_maximums(dev, 1, &max);
2399
2400         for (level = 1; level <= max_level; level++) {
2401                 struct intel_wm_level wm = {};
2402
2403                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
2404
2405                 /*
2406                  * Disable any watermark level that exceeds the
2407                  * register maximums since such watermarks are
2408                  * always invalid.
2409                  */
2410                 if (!ilk_validate_wm_level(level, &max, &wm))
2411                         break;
2412
2413                 pipe_wm->wm[level] = wm;
2414         }
2415
2416         return true;
2417 }
2418
2419 /*
2420  * Merge the watermarks from all active pipes for a specific level.
2421  */
2422 static void ilk_merge_wm_level(struct drm_device *dev,
2423                                int level,
2424                                struct intel_wm_level *ret_wm)
2425 {
2426         const struct intel_crtc *intel_crtc;
2427
2428         ret_wm->enable = true;
2429
2430         for_each_intel_crtc(dev, intel_crtc) {
2431                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2432                 const struct intel_wm_level *wm = &active->wm[level];
2433
2434                 if (!active->pipe_enabled)
2435                         continue;
2436
2437                 /*
2438                  * The watermark values may have been used in the past,
2439                  * so we must maintain them in the registers for some
2440                  * time even if the level is now disabled.
2441                  */
2442                 if (!wm->enable)
2443                         ret_wm->enable = false;
2444
2445                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2446                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2447                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2448                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2449         }
2450 }
2451
2452 /*
2453  * Merge all low power watermarks for all active pipes.
2454  */
2455 static void ilk_wm_merge(struct drm_device *dev,
2456                          const struct intel_wm_config *config,
2457                          const struct ilk_wm_maximums *max,
2458                          struct intel_pipe_wm *merged)
2459 {
2460         struct drm_i915_private *dev_priv = dev->dev_private;
2461         int level, max_level = ilk_wm_max_level(dev);
2462         int last_enabled_level = max_level;
2463
2464         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2465         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2466             config->num_pipes_active > 1)
2467                 return;
2468
2469         /* ILK: FBC WM must be disabled always */
2470         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2471
2472         /* merge each WM1+ level */
2473         for (level = 1; level <= max_level; level++) {
2474                 struct intel_wm_level *wm = &merged->wm[level];
2475
2476                 ilk_merge_wm_level(dev, level, wm);
2477
2478                 if (level > last_enabled_level)
2479                         wm->enable = false;
2480                 else if (!ilk_validate_wm_level(level, max, wm))
2481                         /* make sure all following levels get disabled */
2482                         last_enabled_level = level - 1;
2483
2484                 /*
2485                  * The spec says it is preferred to disable
2486                  * FBC WMs instead of disabling a WM level.
2487                  */
2488                 if (wm->fbc_val > max->fbc) {
2489                         if (wm->enable)
2490                                 merged->fbc_wm_enabled = false;
2491                         wm->fbc_val = 0;
2492                 }
2493         }
2494
2495         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2496         /*
2497          * FIXME this is racy. FBC might get enabled later.
2498          * What we should check here is whether FBC can be
2499          * enabled sometime later.
2500          */
2501         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2502             intel_fbc_enabled(dev_priv)) {
2503                 for (level = 2; level <= max_level; level++) {
2504                         struct intel_wm_level *wm = &merged->wm[level];
2505
2506                         wm->enable = false;
2507                 }
2508         }
2509 }
2510
2511 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2512 {
2513         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2514         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2515 }
2516
2517 /* The value we need to program into the WM_LPx latency field */
2518 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2519 {
2520         struct drm_i915_private *dev_priv = dev->dev_private;
2521
2522         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2523                 return 2 * level;
2524         else
2525                 return dev_priv->wm.pri_latency[level];
2526 }
2527
2528 static void ilk_compute_wm_results(struct drm_device *dev,
2529                                    const struct intel_pipe_wm *merged,
2530                                    enum intel_ddb_partitioning partitioning,
2531                                    struct ilk_wm_values *results)
2532 {
2533         struct intel_crtc *intel_crtc;
2534         int level, wm_lp;
2535
2536         results->enable_fbc_wm = merged->fbc_wm_enabled;
2537         results->partitioning = partitioning;
2538
2539         /* LP1+ register values */
2540         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2541                 const struct intel_wm_level *r;
2542
2543                 level = ilk_wm_lp_to_level(wm_lp, merged);
2544
2545                 r = &merged->wm[level];
2546
2547                 /*
2548                  * Maintain the watermark values even if the level is
2549                  * disabled. Doing otherwise could cause underruns.
2550                  */
2551                 results->wm_lp[wm_lp - 1] =
2552                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2553                         (r->pri_val << WM1_LP_SR_SHIFT) |
2554                         r->cur_val;
2555
2556                 if (r->enable)
2557                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2558
2559                 if (INTEL_INFO(dev)->gen >= 8)
2560                         results->wm_lp[wm_lp - 1] |=
2561                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2562                 else
2563                         results->wm_lp[wm_lp - 1] |=
2564                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2565
2566                 /*
2567                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2568                  * level is disabled. Doing otherwise could cause underruns.
2569                  */
2570                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2571                         WARN_ON(wm_lp != 1);
2572                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2573                 } else
2574                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2575         }
2576
2577         /* LP0 register values */
2578         for_each_intel_crtc(dev, intel_crtc) {
2579                 enum pipe pipe = intel_crtc->pipe;
2580                 const struct intel_wm_level *r =
2581                         &intel_crtc->wm.active.wm[0];
2582
2583                 if (WARN_ON(!r->enable))
2584                         continue;
2585
2586                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2587
2588                 results->wm_pipe[pipe] =
2589                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2590                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2591                         r->cur_val;
2592         }
2593 }
2594
2595 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2596  * case both are at the same level. Prefer r1 in case they're the same. */
2597 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2598                                                   struct intel_pipe_wm *r1,
2599                                                   struct intel_pipe_wm *r2)
2600 {
2601         int level, max_level = ilk_wm_max_level(dev);
2602         int level1 = 0, level2 = 0;
2603
2604         for (level = 1; level <= max_level; level++) {
2605                 if (r1->wm[level].enable)
2606                         level1 = level;
2607                 if (r2->wm[level].enable)
2608                         level2 = level;
2609         }
2610
2611         if (level1 == level2) {
2612                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2613                         return r2;
2614                 else
2615                         return r1;
2616         } else if (level1 > level2) {
2617                 return r1;
2618         } else {
2619                 return r2;
2620         }
2621 }
2622
2623 /* dirty bits used to track which watermarks need changes */
2624 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2625 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2626 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2627 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2628 #define WM_DIRTY_FBC (1 << 24)
2629 #define WM_DIRTY_DDB (1 << 25)
2630
2631 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2632                                          const struct ilk_wm_values *old,
2633                                          const struct ilk_wm_values *new)
2634 {
2635         unsigned int dirty = 0;
2636         enum pipe pipe;
2637         int wm_lp;
2638
2639         for_each_pipe(dev_priv, pipe) {
2640                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2641                         dirty |= WM_DIRTY_LINETIME(pipe);
2642                         /* Must disable LP1+ watermarks too */
2643                         dirty |= WM_DIRTY_LP_ALL;
2644                 }
2645
2646                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2647                         dirty |= WM_DIRTY_PIPE(pipe);
2648                         /* Must disable LP1+ watermarks too */
2649                         dirty |= WM_DIRTY_LP_ALL;
2650                 }
2651         }
2652
2653         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2654                 dirty |= WM_DIRTY_FBC;
2655                 /* Must disable LP1+ watermarks too */
2656                 dirty |= WM_DIRTY_LP_ALL;
2657         }
2658
2659         if (old->partitioning != new->partitioning) {
2660                 dirty |= WM_DIRTY_DDB;
2661                 /* Must disable LP1+ watermarks too */
2662                 dirty |= WM_DIRTY_LP_ALL;
2663         }
2664
2665         /* LP1+ watermarks already deemed dirty, no need to continue */
2666         if (dirty & WM_DIRTY_LP_ALL)
2667                 return dirty;
2668
2669         /* Find the lowest numbered LP1+ watermark in need of an update... */
2670         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2671                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2672                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2673                         break;
2674         }
2675
2676         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2677         for (; wm_lp <= 3; wm_lp++)
2678                 dirty |= WM_DIRTY_LP(wm_lp);
2679
2680         return dirty;
2681 }
2682
2683 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2684                                unsigned int dirty)
2685 {
2686         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2687         bool changed = false;
2688
2689         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2690                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2691                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2692                 changed = true;
2693         }
2694         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2695                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2696                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2697                 changed = true;
2698         }
2699         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2700                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2701                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2702                 changed = true;
2703         }
2704
2705         /*
2706          * Don't touch WM1S_LP_EN here.
2707          * Doing so could cause underruns.
2708          */
2709
2710         return changed;
2711 }
2712
2713 /*
2714  * The spec says we shouldn't write when we don't need, because every write
2715  * causes WMs to be re-evaluated, expending some power.
2716  */
2717 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2718                                 struct ilk_wm_values *results)
2719 {
2720         struct drm_device *dev = dev_priv->dev;
2721         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2722         unsigned int dirty;
2723         uint32_t val;
2724
2725         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2726         if (!dirty)
2727                 return;
2728
2729         _ilk_disable_lp_wm(dev_priv, dirty);
2730
2731         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2732                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2733         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2734                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2735         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2736                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2737
2738         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2739                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2740         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2741                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2742         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2743                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2744
2745         if (dirty & WM_DIRTY_DDB) {
2746                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2747                         val = I915_READ(WM_MISC);
2748                         if (results->partitioning == INTEL_DDB_PART_1_2)
2749                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2750                         else
2751                                 val |= WM_MISC_DATA_PARTITION_5_6;
2752                         I915_WRITE(WM_MISC, val);
2753                 } else {
2754                         val = I915_READ(DISP_ARB_CTL2);
2755                         if (results->partitioning == INTEL_DDB_PART_1_2)
2756                                 val &= ~DISP_DATA_PARTITION_5_6;
2757                         else
2758                                 val |= DISP_DATA_PARTITION_5_6;
2759                         I915_WRITE(DISP_ARB_CTL2, val);
2760                 }
2761         }
2762
2763         if (dirty & WM_DIRTY_FBC) {
2764                 val = I915_READ(DISP_ARB_CTL);
2765                 if (results->enable_fbc_wm)
2766                         val &= ~DISP_FBC_WM_DIS;
2767                 else
2768                         val |= DISP_FBC_WM_DIS;
2769                 I915_WRITE(DISP_ARB_CTL, val);
2770         }
2771
2772         if (dirty & WM_DIRTY_LP(1) &&
2773             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2774                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2775
2776         if (INTEL_INFO(dev)->gen >= 7) {
2777                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2778                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2779                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2780                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2781         }
2782
2783         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2784                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2785         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2786                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2787         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2788                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2789
2790         dev_priv->wm.hw = *results;
2791 }
2792
2793 static bool ilk_disable_lp_wm(struct drm_device *dev)
2794 {
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796
2797         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2798 }
2799
2800 /*
2801  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2802  * different active planes.
2803  */
2804
2805 #define SKL_DDB_SIZE            896     /* in blocks */
2806 #define BXT_DDB_SIZE            512
2807
2808 /*
2809  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2810  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2811  * other universal planes are in indices 1..n.  Note that this may leave unused
2812  * indices between the top "sprite" plane and the cursor.
2813  */
2814 static int
2815 skl_wm_plane_id(const struct intel_plane *plane)
2816 {
2817         switch (plane->base.type) {
2818         case DRM_PLANE_TYPE_PRIMARY:
2819                 return 0;
2820         case DRM_PLANE_TYPE_CURSOR:
2821                 return PLANE_CURSOR;
2822         case DRM_PLANE_TYPE_OVERLAY:
2823                 return plane->plane + 1;
2824         default:
2825                 MISSING_CASE(plane->base.type);
2826                 return plane->plane;
2827         }
2828 }
2829
2830 static void
2831 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2832                                    const struct intel_crtc_state *cstate,
2833                                    const struct intel_wm_config *config,
2834                                    struct skl_ddb_entry *alloc /* out */)
2835 {
2836         struct drm_crtc *for_crtc = cstate->base.crtc;
2837         struct drm_crtc *crtc;
2838         unsigned int pipe_size, ddb_size;
2839         int nth_active_pipe;
2840
2841         if (!cstate->base.active) {
2842                 alloc->start = 0;
2843                 alloc->end = 0;
2844                 return;
2845         }
2846
2847         if (IS_BROXTON(dev))
2848                 ddb_size = BXT_DDB_SIZE;
2849         else
2850                 ddb_size = SKL_DDB_SIZE;
2851
2852         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2853
2854         nth_active_pipe = 0;
2855         for_each_crtc(dev, crtc) {
2856                 if (!to_intel_crtc(crtc)->active)
2857                         continue;
2858
2859                 if (crtc == for_crtc)
2860                         break;
2861
2862                 nth_active_pipe++;
2863         }
2864
2865         pipe_size = ddb_size / config->num_pipes_active;
2866         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2867         alloc->end = alloc->start + pipe_size;
2868 }
2869
2870 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2871 {
2872         if (config->num_pipes_active == 1)
2873                 return 32;
2874
2875         return 8;
2876 }
2877
2878 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2879 {
2880         entry->start = reg & 0x3ff;
2881         entry->end = (reg >> 16) & 0x3ff;
2882         if (entry->end)
2883                 entry->end += 1;
2884 }
2885
2886 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2887                           struct skl_ddb_allocation *ddb /* out */)
2888 {
2889         enum pipe pipe;
2890         int plane;
2891         u32 val;
2892
2893         for_each_pipe(dev_priv, pipe) {
2894                 for_each_plane(dev_priv, pipe, plane) {
2895                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2896                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2897                                                    val);
2898                 }
2899
2900                 val = I915_READ(CUR_BUF_CFG(pipe));
2901                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2902                                            val);
2903         }
2904 }
2905
2906 static unsigned int
2907 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2908                              const struct drm_plane_state *pstate,
2909                              int y)
2910 {
2911         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2912         struct drm_framebuffer *fb = pstate->fb;
2913
2914         /* for planar format */
2915         if (fb->pixel_format == DRM_FORMAT_NV12) {
2916                 if (y)  /* y-plane data rate */
2917                         return intel_crtc->config->pipe_src_w *
2918                                 intel_crtc->config->pipe_src_h *
2919                                 drm_format_plane_cpp(fb->pixel_format, 0);
2920                 else    /* uv-plane data rate */
2921                         return (intel_crtc->config->pipe_src_w/2) *
2922                                 (intel_crtc->config->pipe_src_h/2) *
2923                                 drm_format_plane_cpp(fb->pixel_format, 1);
2924         }
2925
2926         /* for packed formats */
2927         return intel_crtc->config->pipe_src_w *
2928                 intel_crtc->config->pipe_src_h *
2929                 drm_format_plane_cpp(fb->pixel_format, 0);
2930 }
2931
2932 /*
2933  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2934  * a 8192x4096@32bpp framebuffer:
2935  *   3 * 4096 * 8192  * 4 < 2^32
2936  */
2937 static unsigned int
2938 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2939 {
2940         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2941         struct drm_device *dev = intel_crtc->base.dev;
2942         const struct intel_plane *intel_plane;
2943         unsigned int total_data_rate = 0;
2944
2945         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2946                 const struct drm_plane_state *pstate = intel_plane->base.state;
2947
2948                 if (pstate->fb == NULL)
2949                         continue;
2950
2951                 /* packed/uv */
2952                 total_data_rate += skl_plane_relative_data_rate(cstate,
2953                                                                 pstate,
2954                                                                 0);
2955
2956                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2957                         /* y-plane */
2958                         total_data_rate += skl_plane_relative_data_rate(cstate,
2959                                                                         pstate,
2960                                                                         1);
2961         }
2962
2963         return total_data_rate;
2964 }
2965
2966 static void
2967 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
2968                       const struct intel_wm_config *config,
2969                       struct skl_ddb_allocation *ddb /* out */)
2970 {
2971         struct drm_crtc *crtc = cstate->base.crtc;
2972         struct drm_device *dev = crtc->dev;
2973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2974         struct intel_plane *intel_plane;
2975         enum pipe pipe = intel_crtc->pipe;
2976         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2977         uint16_t alloc_size, start, cursor_blocks;
2978         uint16_t minimum[I915_MAX_PLANES];
2979         uint16_t y_minimum[I915_MAX_PLANES];
2980         unsigned int total_data_rate;
2981
2982         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
2983         alloc_size = skl_ddb_entry_size(alloc);
2984         if (alloc_size == 0) {
2985                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2986                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2987                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2988                 return;
2989         }
2990
2991         cursor_blocks = skl_cursor_allocation(config);
2992         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2993         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2994
2995         alloc_size -= cursor_blocks;
2996         alloc->end -= cursor_blocks;
2997
2998         /* 1. Allocate the mininum required blocks for each active plane */
2999         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3000                 struct drm_plane *plane = &intel_plane->base;
3001                 struct drm_framebuffer *fb = plane->fb;
3002                 int id = skl_wm_plane_id(intel_plane);
3003
3004                 if (fb == NULL)
3005                         continue;
3006                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3007                         continue;
3008
3009                 minimum[id] = 8;
3010                 alloc_size -= minimum[id];
3011                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3012                 alloc_size -= y_minimum[id];
3013         }
3014
3015         /*
3016          * 2. Distribute the remaining space in proportion to the amount of
3017          * data each plane needs to fetch from memory.
3018          *
3019          * FIXME: we may not allocate every single block here.
3020          */
3021         total_data_rate = skl_get_total_relative_data_rate(cstate);
3022
3023         start = alloc->start;
3024         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3025                 struct drm_plane *plane = &intel_plane->base;
3026                 struct drm_plane_state *pstate = intel_plane->base.state;
3027                 unsigned int data_rate, y_data_rate;
3028                 uint16_t plane_blocks, y_plane_blocks = 0;
3029                 int id = skl_wm_plane_id(intel_plane);
3030
3031                 if (pstate->fb == NULL)
3032                         continue;
3033                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3034                         continue;
3035
3036                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3037
3038                 /*
3039                  * allocation for (packed formats) or (uv-plane part of planar format):
3040                  * promote the expression to 64 bits to avoid overflowing, the
3041                  * result is < available as data_rate / total_data_rate < 1
3042                  */
3043                 plane_blocks = minimum[id];
3044                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3045                                         total_data_rate);
3046
3047                 ddb->plane[pipe][id].start = start;
3048                 ddb->plane[pipe][id].end = start + plane_blocks;
3049
3050                 start += plane_blocks;
3051
3052                 /*
3053                  * allocation for y_plane part of planar format:
3054                  */
3055                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3056                         y_data_rate = skl_plane_relative_data_rate(cstate,
3057                                                                    pstate,
3058                                                                    1);
3059                         y_plane_blocks = y_minimum[id];
3060                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3061                                                 total_data_rate);
3062
3063                         ddb->y_plane[pipe][id].start = start;
3064                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3065
3066                         start += y_plane_blocks;
3067                 }
3068
3069         }
3070
3071 }
3072
3073 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3074 {
3075         /* TODO: Take into account the scalers once we support them */
3076         return config->base.adjusted_mode.crtc_clock;
3077 }
3078
3079 /*
3080  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3081  * for the read latency) and bytes_per_pixel should always be <= 8, so that
3082  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3083  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3084 */
3085 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3086                                uint32_t latency)
3087 {
3088         uint32_t wm_intermediate_val, ret;
3089
3090         if (latency == 0)
3091                 return UINT_MAX;
3092
3093         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3094         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3095
3096         return ret;
3097 }
3098
3099 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3100                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3101                                uint64_t tiling, uint32_t latency)
3102 {
3103         uint32_t ret;
3104         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3105         uint32_t wm_intermediate_val;
3106
3107         if (latency == 0)
3108                 return UINT_MAX;
3109
3110         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3111
3112         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3113             tiling == I915_FORMAT_MOD_Yf_TILED) {
3114                 plane_bytes_per_line *= 4;
3115                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3116                 plane_blocks_per_line /= 4;
3117         } else {
3118                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3119         }
3120
3121         wm_intermediate_val = latency * pixel_rate;
3122         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3123                                 plane_blocks_per_line;
3124
3125         return ret;
3126 }
3127
3128 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3129                                        const struct intel_crtc *intel_crtc)
3130 {
3131         struct drm_device *dev = intel_crtc->base.dev;
3132         struct drm_i915_private *dev_priv = dev->dev_private;
3133         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3134         enum pipe pipe = intel_crtc->pipe;
3135
3136         if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3137                    sizeof(new_ddb->plane[pipe])))
3138                 return true;
3139
3140         if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
3141                     sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
3142                 return true;
3143
3144         return false;
3145 }
3146
3147 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3148                                              struct intel_wm_config *config)
3149 {
3150         struct drm_crtc *crtc;
3151
3152         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3153                 config->num_pipes_active += to_intel_crtc(crtc)->active;
3154 }
3155
3156 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3157                                  struct intel_crtc_state *cstate,
3158                                  struct intel_plane *intel_plane,
3159                                  uint16_t ddb_allocation,
3160                                  int level,
3161                                  uint16_t *out_blocks, /* out */
3162                                  uint8_t *out_lines /* out */)
3163 {
3164         struct drm_plane *plane = &intel_plane->base;
3165         struct drm_framebuffer *fb = plane->state->fb;
3166         uint32_t latency = dev_priv->wm.skl_latency[level];
3167         uint32_t method1, method2;
3168         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3169         uint32_t res_blocks, res_lines;
3170         uint32_t selected_result;
3171         uint8_t bytes_per_pixel;
3172
3173         if (latency == 0 || !cstate->base.active || !fb)
3174                 return false;
3175
3176         bytes_per_pixel = (fb->pixel_format == DRM_FORMAT_NV12) ?
3177                 drm_format_plane_cpp(DRM_FORMAT_NV12, 0) :
3178                 drm_format_plane_cpp(DRM_FORMAT_NV12, 1);
3179         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3180                                  bytes_per_pixel,
3181                                  latency);
3182         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3183                                  cstate->base.adjusted_mode.crtc_htotal,
3184                                  cstate->pipe_src_w,
3185                                  bytes_per_pixel,
3186                                  fb->modifier[0],
3187                                  latency);
3188
3189         plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
3190         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3191
3192         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3193             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3194                 uint32_t min_scanlines = 4;
3195                 uint32_t y_tile_minimum;
3196                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3197                         int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3198                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3199                                 drm_format_plane_cpp(fb->pixel_format, 0);
3200
3201                         switch (bpp) {
3202                         case 1:
3203                                 min_scanlines = 16;
3204                                 break;
3205                         case 2:
3206                                 min_scanlines = 8;
3207                                 break;
3208                         case 8:
3209                                 WARN(1, "Unsupported pixel depth for rotation");
3210                         }
3211                 }
3212                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3213                 selected_result = max(method2, y_tile_minimum);
3214         } else {
3215                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3216                         selected_result = min(method1, method2);
3217                 else
3218                         selected_result = method1;
3219         }
3220
3221         res_blocks = selected_result + 1;
3222         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3223
3224         if (level >= 1 && level <= 7) {
3225                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3226                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3227                         res_lines += 4;
3228                 else
3229                         res_blocks++;
3230         }
3231
3232         if (res_blocks >= ddb_allocation || res_lines > 31)
3233                 return false;
3234
3235         *out_blocks = res_blocks;
3236         *out_lines = res_lines;
3237
3238         return true;
3239 }
3240
3241 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3242                                  struct skl_ddb_allocation *ddb,
3243                                  struct intel_crtc_state *cstate,
3244                                  int level,
3245                                  struct skl_wm_level *result)
3246 {
3247         struct drm_device *dev = dev_priv->dev;
3248         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3249         struct intel_plane *intel_plane;
3250         uint16_t ddb_blocks;
3251         enum pipe pipe = intel_crtc->pipe;
3252
3253         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3254                 int i = skl_wm_plane_id(intel_plane);
3255
3256                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3257
3258                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3259                                                 cstate,
3260                                                 intel_plane,
3261                                                 ddb_blocks,
3262                                                 level,
3263                                                 &result->plane_res_b[i],
3264                                                 &result->plane_res_l[i]);
3265         }
3266 }
3267
3268 static uint32_t
3269 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3270 {
3271         if (!cstate->base.active)
3272                 return 0;
3273
3274         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3275                 return 0;
3276
3277         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3278                             skl_pipe_pixel_rate(cstate));
3279 }
3280
3281 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3282                                       struct skl_wm_level *trans_wm /* out */)
3283 {
3284         struct drm_crtc *crtc = cstate->base.crtc;
3285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3286         struct intel_plane *intel_plane;
3287
3288         if (!cstate->base.active)
3289                 return;
3290
3291         /* Until we know more, just disable transition WMs */
3292         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3293                 int i = skl_wm_plane_id(intel_plane);
3294
3295                 trans_wm->plane_en[i] = false;
3296         }
3297 }
3298
3299 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3300                                 struct skl_ddb_allocation *ddb,
3301                                 struct skl_pipe_wm *pipe_wm)
3302 {
3303         struct drm_device *dev = cstate->base.crtc->dev;
3304         const struct drm_i915_private *dev_priv = dev->dev_private;
3305         int level, max_level = ilk_wm_max_level(dev);
3306
3307         for (level = 0; level <= max_level; level++) {
3308                 skl_compute_wm_level(dev_priv, ddb, cstate,
3309                                      level, &pipe_wm->wm[level]);
3310         }
3311         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3312
3313         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3314 }
3315
3316 static void skl_compute_wm_results(struct drm_device *dev,
3317                                    struct skl_pipe_wm *p_wm,
3318                                    struct skl_wm_values *r,
3319                                    struct intel_crtc *intel_crtc)
3320 {
3321         int level, max_level = ilk_wm_max_level(dev);
3322         enum pipe pipe = intel_crtc->pipe;
3323         uint32_t temp;
3324         int i;
3325
3326         for (level = 0; level <= max_level; level++) {
3327                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3328                         temp = 0;
3329
3330                         temp |= p_wm->wm[level].plane_res_l[i] <<
3331                                         PLANE_WM_LINES_SHIFT;
3332                         temp |= p_wm->wm[level].plane_res_b[i];
3333                         if (p_wm->wm[level].plane_en[i])
3334                                 temp |= PLANE_WM_EN;
3335
3336                         r->plane[pipe][i][level] = temp;
3337                 }
3338
3339                 temp = 0;
3340
3341                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3342                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3343
3344                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3345                         temp |= PLANE_WM_EN;
3346
3347                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3348
3349         }
3350
3351         /* transition WMs */
3352         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3353                 temp = 0;
3354                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3355                 temp |= p_wm->trans_wm.plane_res_b[i];
3356                 if (p_wm->trans_wm.plane_en[i])
3357                         temp |= PLANE_WM_EN;
3358
3359                 r->plane_trans[pipe][i] = temp;
3360         }
3361
3362         temp = 0;
3363         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3364         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3365         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3366                 temp |= PLANE_WM_EN;
3367
3368         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3369
3370         r->wm_linetime[pipe] = p_wm->linetime;
3371 }
3372
3373 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3374                                 const struct skl_ddb_entry *entry)
3375 {
3376         if (entry->end)
3377                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3378         else
3379                 I915_WRITE(reg, 0);
3380 }
3381
3382 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3383                                 const struct skl_wm_values *new)
3384 {
3385         struct drm_device *dev = dev_priv->dev;
3386         struct intel_crtc *crtc;
3387
3388         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3389                 int i, level, max_level = ilk_wm_max_level(dev);
3390                 enum pipe pipe = crtc->pipe;
3391
3392                 if (!new->dirty[pipe])
3393                         continue;
3394
3395                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3396
3397                 for (level = 0; level <= max_level; level++) {
3398                         for (i = 0; i < intel_num_planes(crtc); i++)
3399                                 I915_WRITE(PLANE_WM(pipe, i, level),
3400                                            new->plane[pipe][i][level]);
3401                         I915_WRITE(CUR_WM(pipe, level),
3402                                    new->plane[pipe][PLANE_CURSOR][level]);
3403                 }
3404                 for (i = 0; i < intel_num_planes(crtc); i++)
3405                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3406                                    new->plane_trans[pipe][i]);
3407                 I915_WRITE(CUR_WM_TRANS(pipe),
3408                            new->plane_trans[pipe][PLANE_CURSOR]);
3409
3410                 for (i = 0; i < intel_num_planes(crtc); i++) {
3411                         skl_ddb_entry_write(dev_priv,
3412                                             PLANE_BUF_CFG(pipe, i),
3413                                             &new->ddb.plane[pipe][i]);
3414                         skl_ddb_entry_write(dev_priv,
3415                                             PLANE_NV12_BUF_CFG(pipe, i),
3416                                             &new->ddb.y_plane[pipe][i]);
3417                 }
3418
3419                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3420                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3421         }
3422 }
3423
3424 /*
3425  * When setting up a new DDB allocation arrangement, we need to correctly
3426  * sequence the times at which the new allocations for the pipes are taken into
3427  * account or we'll have pipes fetching from space previously allocated to
3428  * another pipe.
3429  *
3430  * Roughly the sequence looks like:
3431  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3432  *     overlapping with a previous light-up pipe (another way to put it is:
3433  *     pipes with their new allocation strickly included into their old ones).
3434  *  2. re-allocate the other pipes that get their allocation reduced
3435  *  3. allocate the pipes having their allocation increased
3436  *
3437  * Steps 1. and 2. are here to take care of the following case:
3438  * - Initially DDB looks like this:
3439  *     |   B    |   C    |
3440  * - enable pipe A.
3441  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3442  *   allocation
3443  *     |  A  |  B  |  C  |
3444  *
3445  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3446  */
3447
3448 static void
3449 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3450 {
3451         int plane;
3452
3453         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3454
3455         for_each_plane(dev_priv, pipe, plane) {
3456                 I915_WRITE(PLANE_SURF(pipe, plane),
3457                            I915_READ(PLANE_SURF(pipe, plane)));
3458         }
3459         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3460 }
3461
3462 static bool
3463 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3464                             const struct skl_ddb_allocation *new,
3465                             enum pipe pipe)
3466 {
3467         uint16_t old_size, new_size;
3468
3469         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3470         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3471
3472         return old_size != new_size &&
3473                new->pipe[pipe].start >= old->pipe[pipe].start &&
3474                new->pipe[pipe].end <= old->pipe[pipe].end;
3475 }
3476
3477 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3478                                 struct skl_wm_values *new_values)
3479 {
3480         struct drm_device *dev = dev_priv->dev;
3481         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3482         bool reallocated[I915_MAX_PIPES] = {};
3483         struct intel_crtc *crtc;
3484         enum pipe pipe;
3485
3486         new_ddb = &new_values->ddb;
3487         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3488
3489         /*
3490          * First pass: flush the pipes with the new allocation contained into
3491          * the old space.
3492          *
3493          * We'll wait for the vblank on those pipes to ensure we can safely
3494          * re-allocate the freed space without this pipe fetching from it.
3495          */
3496         for_each_intel_crtc(dev, crtc) {
3497                 if (!crtc->active)
3498                         continue;
3499
3500                 pipe = crtc->pipe;
3501
3502                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3503                         continue;
3504
3505                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3506                 intel_wait_for_vblank(dev, pipe);
3507
3508                 reallocated[pipe] = true;
3509         }
3510
3511
3512         /*
3513          * Second pass: flush the pipes that are having their allocation
3514          * reduced, but overlapping with a previous allocation.
3515          *
3516          * Here as well we need to wait for the vblank to make sure the freed
3517          * space is not used anymore.
3518          */
3519         for_each_intel_crtc(dev, crtc) {
3520                 if (!crtc->active)
3521                         continue;
3522
3523                 pipe = crtc->pipe;
3524
3525                 if (reallocated[pipe])
3526                         continue;
3527
3528                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3529                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3530                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3531                         intel_wait_for_vblank(dev, pipe);
3532                         reallocated[pipe] = true;
3533                 }
3534         }
3535
3536         /*
3537          * Third pass: flush the pipes that got more space allocated.
3538          *
3539          * We don't need to actively wait for the update here, next vblank
3540          * will just get more DDB space with the correct WM values.
3541          */
3542         for_each_intel_crtc(dev, crtc) {
3543                 if (!crtc->active)
3544                         continue;
3545
3546                 pipe = crtc->pipe;
3547
3548                 /*
3549                  * At this point, only the pipes more space than before are
3550                  * left to re-allocate.
3551                  */
3552                 if (reallocated[pipe])
3553                         continue;
3554
3555                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3556         }
3557 }
3558
3559 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3560                                struct intel_wm_config *config,
3561                                struct skl_ddb_allocation *ddb, /* out */
3562                                struct skl_pipe_wm *pipe_wm /* out */)
3563 {
3564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3566
3567         skl_allocate_pipe_ddb(cstate, config, ddb);
3568         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3569
3570         if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3571                 return false;
3572
3573         intel_crtc->wm.skl_active = *pipe_wm;
3574
3575         return true;
3576 }
3577
3578 static void skl_update_other_pipe_wm(struct drm_device *dev,
3579                                      struct drm_crtc *crtc,
3580                                      struct intel_wm_config *config,
3581                                      struct skl_wm_values *r)
3582 {
3583         struct intel_crtc *intel_crtc;
3584         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3585
3586         /*
3587          * If the WM update hasn't changed the allocation for this_crtc (the
3588          * crtc we are currently computing the new WM values for), other
3589          * enabled crtcs will keep the same allocation and we don't need to
3590          * recompute anything for them.
3591          */
3592         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3593                 return;
3594
3595         /*
3596          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3597          * other active pipes need new DDB allocation and WM values.
3598          */
3599         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3600                                 base.head) {
3601                 struct skl_pipe_wm pipe_wm = {};
3602                 bool wm_changed;
3603
3604                 if (this_crtc->pipe == intel_crtc->pipe)
3605                         continue;
3606
3607                 if (!intel_crtc->active)
3608                         continue;
3609
3610                 wm_changed = skl_update_pipe_wm(&intel_crtc->base, config,
3611                                                 &r->ddb, &pipe_wm);
3612
3613                 /*
3614                  * If we end up re-computing the other pipe WM values, it's
3615                  * because it was really needed, so we expect the WM values to
3616                  * be different.
3617                  */
3618                 WARN_ON(!wm_changed);
3619
3620                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3621                 r->dirty[intel_crtc->pipe] = true;
3622         }
3623 }
3624
3625 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3626 {
3627         watermarks->wm_linetime[pipe] = 0;
3628         memset(watermarks->plane[pipe], 0,
3629                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3630         memset(watermarks->plane_trans[pipe],
3631                0, sizeof(uint32_t) * I915_MAX_PLANES);
3632         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3633
3634         /* Clear ddb entries for pipe */
3635         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3636         memset(&watermarks->ddb.plane[pipe], 0,
3637                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3638         memset(&watermarks->ddb.y_plane[pipe], 0,
3639                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3640         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3641                sizeof(struct skl_ddb_entry));
3642
3643 }
3644
3645 static void skl_update_wm(struct drm_crtc *crtc)
3646 {
3647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3648         struct drm_device *dev = crtc->dev;
3649         struct drm_i915_private *dev_priv = dev->dev_private;
3650         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3651         struct skl_pipe_wm pipe_wm = {};
3652         struct intel_wm_config config = {};
3653
3654
3655         /* Clear all dirty flags */
3656         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3657
3658         skl_clear_wm(results, intel_crtc->pipe);
3659
3660         skl_compute_wm_global_parameters(dev, &config);
3661
3662         if (!skl_update_pipe_wm(crtc, &config, &results->ddb, &pipe_wm))
3663                 return;
3664
3665         skl_compute_wm_results(dev, &pipe_wm, results, intel_crtc);
3666         results->dirty[intel_crtc->pipe] = true;
3667
3668         skl_update_other_pipe_wm(dev, crtc, &config, results);
3669         skl_write_wm_values(dev_priv, results);
3670         skl_flush_wm_values(dev_priv, results);
3671
3672         /* store the new configuration */
3673         dev_priv->wm.skl_hw = *results;
3674 }
3675
3676 static void ilk_update_wm(struct drm_crtc *crtc)
3677 {
3678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3679         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3680         struct drm_device *dev = crtc->dev;
3681         struct drm_i915_private *dev_priv = dev->dev_private;
3682         struct ilk_wm_maximums max;
3683         struct ilk_wm_values results = {};
3684         enum intel_ddb_partitioning partitioning;
3685         struct intel_pipe_wm pipe_wm = {};
3686         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3687         struct intel_wm_config config = {};
3688
3689         WARN_ON(cstate->base.active != intel_crtc->active);
3690
3691         /*
3692          * IVB workaround: must disable low power watermarks for at least
3693          * one frame before enabling scaling.  LP watermarks can be re-enabled
3694          * when scaling is disabled.
3695          *
3696          * WaCxSRDisabledForSpriteScaling:ivb
3697          */
3698         if (cstate->disable_lp_wm) {
3699                 ilk_disable_lp_wm(dev);
3700                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3701         }
3702
3703         intel_compute_pipe_wm(cstate, &pipe_wm);
3704
3705         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3706                 return;
3707
3708         intel_crtc->wm.active = pipe_wm;
3709
3710         ilk_compute_wm_config(dev, &config);
3711
3712         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3713         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3714
3715         /* 5/6 split only in single pipe config on IVB+ */
3716         if (INTEL_INFO(dev)->gen >= 7 &&
3717             config.num_pipes_active == 1 && config.sprites_enabled) {
3718                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3719                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3720
3721                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3722         } else {
3723                 best_lp_wm = &lp_wm_1_2;
3724         }
3725
3726         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3727                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3728
3729         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3730
3731         ilk_write_wm_values(dev_priv, &results);
3732 }
3733
3734 static void skl_pipe_wm_active_state(uint32_t val,
3735                                      struct skl_pipe_wm *active,
3736                                      bool is_transwm,
3737                                      bool is_cursor,
3738                                      int i,
3739                                      int level)
3740 {
3741         bool is_enabled = (val & PLANE_WM_EN) != 0;
3742
3743         if (!is_transwm) {
3744                 if (!is_cursor) {
3745                         active->wm[level].plane_en[i] = is_enabled;
3746                         active->wm[level].plane_res_b[i] =
3747                                         val & PLANE_WM_BLOCKS_MASK;
3748                         active->wm[level].plane_res_l[i] =
3749                                         (val >> PLANE_WM_LINES_SHIFT) &
3750                                                 PLANE_WM_LINES_MASK;
3751                 } else {
3752                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3753                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3754                                         val & PLANE_WM_BLOCKS_MASK;
3755                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3756                                         (val >> PLANE_WM_LINES_SHIFT) &
3757                                                 PLANE_WM_LINES_MASK;
3758                 }
3759         } else {
3760                 if (!is_cursor) {
3761                         active->trans_wm.plane_en[i] = is_enabled;
3762                         active->trans_wm.plane_res_b[i] =
3763                                         val & PLANE_WM_BLOCKS_MASK;
3764                         active->trans_wm.plane_res_l[i] =
3765                                         (val >> PLANE_WM_LINES_SHIFT) &
3766                                                 PLANE_WM_LINES_MASK;
3767                 } else {
3768                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3769                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3770                                         val & PLANE_WM_BLOCKS_MASK;
3771                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3772                                         (val >> PLANE_WM_LINES_SHIFT) &
3773                                                 PLANE_WM_LINES_MASK;
3774                 }
3775         }
3776 }
3777
3778 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3779 {
3780         struct drm_device *dev = crtc->dev;
3781         struct drm_i915_private *dev_priv = dev->dev_private;
3782         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3784         struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3785         enum pipe pipe = intel_crtc->pipe;
3786         int level, i, max_level;
3787         uint32_t temp;
3788
3789         max_level = ilk_wm_max_level(dev);
3790
3791         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3792
3793         for (level = 0; level <= max_level; level++) {
3794                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3795                         hw->plane[pipe][i][level] =
3796                                         I915_READ(PLANE_WM(pipe, i, level));
3797                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3798         }
3799
3800         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3801                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3802         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3803
3804         if (!intel_crtc->active)
3805                 return;
3806
3807         hw->dirty[pipe] = true;
3808
3809         active->linetime = hw->wm_linetime[pipe];
3810
3811         for (level = 0; level <= max_level; level++) {
3812                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3813                         temp = hw->plane[pipe][i][level];
3814                         skl_pipe_wm_active_state(temp, active, false,
3815                                                 false, i, level);
3816                 }
3817                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3818                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3819         }
3820
3821         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3822                 temp = hw->plane_trans[pipe][i];
3823                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3824         }
3825
3826         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3827         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3828 }
3829
3830 void skl_wm_get_hw_state(struct drm_device *dev)
3831 {
3832         struct drm_i915_private *dev_priv = dev->dev_private;
3833         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3834         struct drm_crtc *crtc;
3835
3836         skl_ddb_get_hw_state(dev_priv, ddb);
3837         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3838                 skl_pipe_wm_get_hw_state(crtc);
3839 }
3840
3841 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3842 {
3843         struct drm_device *dev = crtc->dev;
3844         struct drm_i915_private *dev_priv = dev->dev_private;
3845         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3847         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3848         enum pipe pipe = intel_crtc->pipe;
3849         static const unsigned int wm0_pipe_reg[] = {
3850                 [PIPE_A] = WM0_PIPEA_ILK,
3851                 [PIPE_B] = WM0_PIPEB_ILK,
3852                 [PIPE_C] = WM0_PIPEC_IVB,
3853         };
3854
3855         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3856         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3857                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3858
3859         active->pipe_enabled = intel_crtc->active;
3860
3861         if (active->pipe_enabled) {
3862                 u32 tmp = hw->wm_pipe[pipe];
3863
3864                 /*
3865                  * For active pipes LP0 watermark is marked as
3866                  * enabled, and LP1+ watermaks as disabled since
3867                  * we can't really reverse compute them in case
3868                  * multiple pipes are active.
3869                  */
3870                 active->wm[0].enable = true;
3871                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3872                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3873                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3874                 active->linetime = hw->wm_linetime[pipe];
3875         } else {
3876                 int level, max_level = ilk_wm_max_level(dev);
3877
3878                 /*
3879                  * For inactive pipes, all watermark levels
3880                  * should be marked as enabled but zeroed,
3881                  * which is what we'd compute them to.
3882                  */
3883                 for (level = 0; level <= max_level; level++)
3884                         active->wm[level].enable = true;
3885         }
3886 }
3887
3888 #define _FW_WM(value, plane) \
3889         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3890 #define _FW_WM_VLV(value, plane) \
3891         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3892
3893 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3894                                struct vlv_wm_values *wm)
3895 {
3896         enum pipe pipe;
3897         uint32_t tmp;
3898
3899         for_each_pipe(dev_priv, pipe) {
3900                 tmp = I915_READ(VLV_DDL(pipe));
3901
3902                 wm->ddl[pipe].primary =
3903                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3904                 wm->ddl[pipe].cursor =
3905                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3906                 wm->ddl[pipe].sprite[0] =
3907                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3908                 wm->ddl[pipe].sprite[1] =
3909                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3910         }
3911
3912         tmp = I915_READ(DSPFW1);
3913         wm->sr.plane = _FW_WM(tmp, SR);
3914         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3915         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3916         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3917
3918         tmp = I915_READ(DSPFW2);
3919         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3920         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3921         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3922
3923         tmp = I915_READ(DSPFW3);
3924         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3925
3926         if (IS_CHERRYVIEW(dev_priv)) {
3927                 tmp = I915_READ(DSPFW7_CHV);
3928                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3929                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3930
3931                 tmp = I915_READ(DSPFW8_CHV);
3932                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3933                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3934
3935                 tmp = I915_READ(DSPFW9_CHV);
3936                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3937                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3938
3939                 tmp = I915_READ(DSPHOWM);
3940                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3941                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3942                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3943                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3944                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3945                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3946                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3947                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3948                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3949                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3950         } else {
3951                 tmp = I915_READ(DSPFW7);
3952                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3953                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3954
3955                 tmp = I915_READ(DSPHOWM);
3956                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3957                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3958                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3959                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3960                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3961                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3962                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3963         }
3964 }
3965
3966 #undef _FW_WM
3967 #undef _FW_WM_VLV
3968
3969 void vlv_wm_get_hw_state(struct drm_device *dev)
3970 {
3971         struct drm_i915_private *dev_priv = to_i915(dev);
3972         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3973         struct intel_plane *plane;
3974         enum pipe pipe;
3975         u32 val;
3976
3977         vlv_read_wm_values(dev_priv, wm);
3978
3979         for_each_intel_plane(dev, plane) {
3980                 switch (plane->base.type) {
3981                         int sprite;
3982                 case DRM_PLANE_TYPE_CURSOR:
3983                         plane->wm.fifo_size = 63;
3984                         break;
3985                 case DRM_PLANE_TYPE_PRIMARY:
3986                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3987                         break;
3988                 case DRM_PLANE_TYPE_OVERLAY:
3989                         sprite = plane->plane;
3990                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3991                         break;
3992                 }
3993         }
3994
3995         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3996         wm->level = VLV_WM_LEVEL_PM2;
3997
3998         if (IS_CHERRYVIEW(dev_priv)) {
3999                 mutex_lock(&dev_priv->rps.hw_lock);
4000
4001                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4002                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4003                         wm->level = VLV_WM_LEVEL_PM5;
4004
4005                 /*
4006                  * If DDR DVFS is disabled in the BIOS, Punit
4007                  * will never ack the request. So if that happens
4008                  * assume we don't have to enable/disable DDR DVFS
4009                  * dynamically. To test that just set the REQ_ACK
4010                  * bit to poke the Punit, but don't change the
4011                  * HIGH/LOW bits so that we don't actually change
4012                  * the current state.
4013                  */
4014                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4015                 val |= FORCE_DDR_FREQ_REQ_ACK;
4016                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4017
4018                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4019                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4020                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4021                                       "assuming DDR DVFS is disabled\n");
4022                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4023                 } else {
4024                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4025                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4026                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4027                 }
4028
4029                 mutex_unlock(&dev_priv->rps.hw_lock);
4030         }
4031
4032         for_each_pipe(dev_priv, pipe)
4033                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4034                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4035                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4036
4037         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4038                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4039 }
4040
4041 void ilk_wm_get_hw_state(struct drm_device *dev)
4042 {
4043         struct drm_i915_private *dev_priv = dev->dev_private;
4044         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4045         struct drm_crtc *crtc;
4046
4047         for_each_crtc(dev, crtc)
4048                 ilk_pipe_wm_get_hw_state(crtc);
4049
4050         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4051         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4052         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4053
4054         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4055         if (INTEL_INFO(dev)->gen >= 7) {
4056                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4057                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4058         }
4059
4060         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4061                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4062                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4063         else if (IS_IVYBRIDGE(dev))
4064                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4065                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4066
4067         hw->enable_fbc_wm =
4068                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4069 }
4070
4071 /**
4072  * intel_update_watermarks - update FIFO watermark values based on current modes
4073  *
4074  * Calculate watermark values for the various WM regs based on current mode
4075  * and plane configuration.
4076  *
4077  * There are several cases to deal with here:
4078  *   - normal (i.e. non-self-refresh)
4079  *   - self-refresh (SR) mode
4080  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4081  *   - lines are small relative to FIFO size (buffer can hold more than 2
4082  *     lines), so need to account for TLB latency
4083  *
4084  *   The normal calculation is:
4085  *     watermark = dotclock * bytes per pixel * latency
4086  *   where latency is platform & configuration dependent (we assume pessimal
4087  *   values here).
4088  *
4089  *   The SR calculation is:
4090  *     watermark = (trunc(latency/line time)+1) * surface width *
4091  *       bytes per pixel
4092  *   where
4093  *     line time = htotal / dotclock
4094  *     surface width = hdisplay for normal plane and 64 for cursor
4095  *   and latency is assumed to be high, as above.
4096  *
4097  * The final value programmed to the register should always be rounded up,
4098  * and include an extra 2 entries to account for clock crossings.
4099  *
4100  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4101  * to set the non-SR watermarks to 8.
4102  */
4103 void intel_update_watermarks(struct drm_crtc *crtc)
4104 {
4105         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4106
4107         if (dev_priv->display.update_wm)
4108                 dev_priv->display.update_wm(crtc);
4109 }
4110
4111 /**
4112  * Lock protecting IPS related data structures
4113  */
4114 DEFINE_SPINLOCK(mchdev_lock);
4115
4116 /* Global for IPS driver to get at the current i915 device. Protected by
4117  * mchdev_lock. */
4118 static struct drm_i915_private *i915_mch_dev;
4119
4120 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4121 {
4122         struct drm_i915_private *dev_priv = dev->dev_private;
4123         u16 rgvswctl;
4124
4125         assert_spin_locked(&mchdev_lock);
4126
4127         rgvswctl = I915_READ16(MEMSWCTL);
4128         if (rgvswctl & MEMCTL_CMD_STS) {
4129                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4130                 return false; /* still busy with another command */
4131         }
4132
4133         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4134                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4135         I915_WRITE16(MEMSWCTL, rgvswctl);
4136         POSTING_READ16(MEMSWCTL);
4137
4138         rgvswctl |= MEMCTL_CMD_STS;
4139         I915_WRITE16(MEMSWCTL, rgvswctl);
4140
4141         return true;
4142 }
4143
4144 static void ironlake_enable_drps(struct drm_device *dev)
4145 {
4146         struct drm_i915_private *dev_priv = dev->dev_private;
4147         u32 rgvmodectl = I915_READ(MEMMODECTL);
4148         u8 fmax, fmin, fstart, vstart;
4149
4150         spin_lock_irq(&mchdev_lock);
4151
4152         /* Enable temp reporting */
4153         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4154         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4155
4156         /* 100ms RC evaluation intervals */
4157         I915_WRITE(RCUPEI, 100000);
4158         I915_WRITE(RCDNEI, 100000);
4159
4160         /* Set max/min thresholds to 90ms and 80ms respectively */
4161         I915_WRITE(RCBMAXAVG, 90000);
4162         I915_WRITE(RCBMINAVG, 80000);
4163
4164         I915_WRITE(MEMIHYST, 1);
4165
4166         /* Set up min, max, and cur for interrupt handling */
4167         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4168         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4169         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4170                 MEMMODE_FSTART_SHIFT;
4171
4172         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4173                 PXVFREQ_PX_SHIFT;
4174
4175         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4176         dev_priv->ips.fstart = fstart;
4177
4178         dev_priv->ips.max_delay = fstart;
4179         dev_priv->ips.min_delay = fmin;
4180         dev_priv->ips.cur_delay = fstart;
4181
4182         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4183                          fmax, fmin, fstart);
4184
4185         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4186
4187         /*
4188          * Interrupts will be enabled in ironlake_irq_postinstall
4189          */
4190
4191         I915_WRITE(VIDSTART, vstart);
4192         POSTING_READ(VIDSTART);
4193
4194         rgvmodectl |= MEMMODE_SWMODE_EN;
4195         I915_WRITE(MEMMODECTL, rgvmodectl);
4196
4197         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4198                 DRM_ERROR("stuck trying to change perf mode\n");
4199         mdelay(1);
4200
4201         ironlake_set_drps(dev, fstart);
4202
4203         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4204                 I915_READ(DDREC) + I915_READ(CSIEC);
4205         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4206         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4207         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4208
4209         spin_unlock_irq(&mchdev_lock);
4210 }
4211
4212 static void ironlake_disable_drps(struct drm_device *dev)
4213 {
4214         struct drm_i915_private *dev_priv = dev->dev_private;
4215         u16 rgvswctl;
4216
4217         spin_lock_irq(&mchdev_lock);
4218
4219         rgvswctl = I915_READ16(MEMSWCTL);
4220
4221         /* Ack interrupts, disable EFC interrupt */
4222         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4223         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4224         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4225         I915_WRITE(DEIIR, DE_PCU_EVENT);
4226         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4227
4228         /* Go back to the starting frequency */
4229         ironlake_set_drps(dev, dev_priv->ips.fstart);
4230         mdelay(1);
4231         rgvswctl |= MEMCTL_CMD_STS;
4232         I915_WRITE(MEMSWCTL, rgvswctl);
4233         mdelay(1);
4234
4235         spin_unlock_irq(&mchdev_lock);
4236 }
4237
4238 /* There's a funny hw issue where the hw returns all 0 when reading from
4239  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4240  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4241  * all limits and the gpu stuck at whatever frequency it is at atm).
4242  */
4243 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4244 {
4245         u32 limits;
4246
4247         /* Only set the down limit when we've reached the lowest level to avoid
4248          * getting more interrupts, otherwise leave this clear. This prevents a
4249          * race in the hw when coming out of rc6: There's a tiny window where
4250          * the hw runs at the minimal clock before selecting the desired
4251          * frequency, if the down threshold expires in that window we will not
4252          * receive a down interrupt. */
4253         if (IS_GEN9(dev_priv->dev)) {
4254                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4255                 if (val <= dev_priv->rps.min_freq_softlimit)
4256                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4257         } else {
4258                 limits = dev_priv->rps.max_freq_softlimit << 24;
4259                 if (val <= dev_priv->rps.min_freq_softlimit)
4260                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4261         }
4262
4263         return limits;
4264 }
4265
4266 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4267 {
4268         int new_power;
4269         u32 threshold_up = 0, threshold_down = 0; /* in % */
4270         u32 ei_up = 0, ei_down = 0;
4271
4272         new_power = dev_priv->rps.power;
4273         switch (dev_priv->rps.power) {
4274         case LOW_POWER:
4275                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4276                         new_power = BETWEEN;
4277                 break;
4278
4279         case BETWEEN:
4280                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4281                         new_power = LOW_POWER;
4282                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4283                         new_power = HIGH_POWER;
4284                 break;
4285
4286         case HIGH_POWER:
4287                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4288                         new_power = BETWEEN;
4289                 break;
4290         }
4291         /* Max/min bins are special */
4292         if (val <= dev_priv->rps.min_freq_softlimit)
4293                 new_power = LOW_POWER;
4294         if (val >= dev_priv->rps.max_freq_softlimit)
4295                 new_power = HIGH_POWER;
4296         if (new_power == dev_priv->rps.power)
4297                 return;
4298
4299         /* Note the units here are not exactly 1us, but 1280ns. */
4300         switch (new_power) {
4301         case LOW_POWER:
4302                 /* Upclock if more than 95% busy over 16ms */
4303                 ei_up = 16000;
4304                 threshold_up = 95;
4305
4306                 /* Downclock if less than 85% busy over 32ms */
4307                 ei_down = 32000;
4308                 threshold_down = 85;
4309                 break;
4310
4311         case BETWEEN:
4312                 /* Upclock if more than 90% busy over 13ms */
4313                 ei_up = 13000;
4314                 threshold_up = 90;
4315
4316                 /* Downclock if less than 75% busy over 32ms */
4317                 ei_down = 32000;
4318                 threshold_down = 75;
4319                 break;
4320
4321         case HIGH_POWER:
4322                 /* Upclock if more than 85% busy over 10ms */
4323                 ei_up = 10000;
4324                 threshold_up = 85;
4325
4326                 /* Downclock if less than 60% busy over 32ms */
4327                 ei_down = 32000;
4328                 threshold_down = 60;
4329                 break;
4330         }
4331
4332         I915_WRITE(GEN6_RP_UP_EI,
4333                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4334         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4335                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4336
4337         I915_WRITE(GEN6_RP_DOWN_EI,
4338                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4339         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4340                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4341
4342          I915_WRITE(GEN6_RP_CONTROL,
4343                     GEN6_RP_MEDIA_TURBO |
4344                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4345                     GEN6_RP_MEDIA_IS_GFX |
4346                     GEN6_RP_ENABLE |
4347                     GEN6_RP_UP_BUSY_AVG |
4348                     GEN6_RP_DOWN_IDLE_AVG);
4349
4350         dev_priv->rps.power = new_power;
4351         dev_priv->rps.up_threshold = threshold_up;
4352         dev_priv->rps.down_threshold = threshold_down;
4353         dev_priv->rps.last_adj = 0;
4354 }
4355
4356 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4357 {
4358         u32 mask = 0;
4359
4360         if (val > dev_priv->rps.min_freq_softlimit)
4361                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4362         if (val < dev_priv->rps.max_freq_softlimit)
4363                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4364
4365         mask &= dev_priv->pm_rps_events;
4366
4367         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4368 }
4369
4370 /* gen6_set_rps is called to update the frequency request, but should also be
4371  * called when the range (min_delay and max_delay) is modified so that we can
4372  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4373 static void gen6_set_rps(struct drm_device *dev, u8 val)
4374 {
4375         struct drm_i915_private *dev_priv = dev->dev_private;
4376
4377         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4378         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4379                 return;
4380
4381         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4382         WARN_ON(val > dev_priv->rps.max_freq);
4383         WARN_ON(val < dev_priv->rps.min_freq);
4384
4385         /* min/max delay may still have been modified so be sure to
4386          * write the limits value.
4387          */
4388         if (val != dev_priv->rps.cur_freq) {
4389                 gen6_set_rps_thresholds(dev_priv, val);
4390
4391                 if (IS_GEN9(dev))
4392                         I915_WRITE(GEN6_RPNSWREQ,
4393                                    GEN9_FREQUENCY(val));
4394                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4395                         I915_WRITE(GEN6_RPNSWREQ,
4396                                    HSW_FREQUENCY(val));
4397                 else
4398                         I915_WRITE(GEN6_RPNSWREQ,
4399                                    GEN6_FREQUENCY(val) |
4400                                    GEN6_OFFSET(0) |
4401                                    GEN6_AGGRESSIVE_TURBO);
4402         }
4403
4404         /* Make sure we continue to get interrupts
4405          * until we hit the minimum or maximum frequencies.
4406          */
4407         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4408         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4409
4410         POSTING_READ(GEN6_RPNSWREQ);
4411
4412         dev_priv->rps.cur_freq = val;
4413         trace_intel_gpu_freq_change(val * 50);
4414 }
4415
4416 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4417 {
4418         struct drm_i915_private *dev_priv = dev->dev_private;
4419
4420         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4421         WARN_ON(val > dev_priv->rps.max_freq);
4422         WARN_ON(val < dev_priv->rps.min_freq);
4423
4424         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4425                       "Odd GPU freq value\n"))
4426                 val &= ~1;
4427
4428         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4429
4430         if (val != dev_priv->rps.cur_freq) {
4431                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4432                 if (!IS_CHERRYVIEW(dev_priv))
4433                         gen6_set_rps_thresholds(dev_priv, val);
4434         }
4435
4436         dev_priv->rps.cur_freq = val;
4437         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4438 }
4439
4440 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4441  *
4442  * * If Gfx is Idle, then
4443  * 1. Forcewake Media well.
4444  * 2. Request idle freq.
4445  * 3. Release Forcewake of Media well.
4446 */
4447 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4448 {
4449         u32 val = dev_priv->rps.idle_freq;
4450
4451         if (dev_priv->rps.cur_freq <= val)
4452                 return;
4453
4454         /* Wake up the media well, as that takes a lot less
4455          * power than the Render well. */
4456         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4457         valleyview_set_rps(dev_priv->dev, val);
4458         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4459 }
4460
4461 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4462 {
4463         mutex_lock(&dev_priv->rps.hw_lock);
4464         if (dev_priv->rps.enabled) {
4465                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4466                         gen6_rps_reset_ei(dev_priv);
4467                 I915_WRITE(GEN6_PMINTRMSK,
4468                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4469         }
4470         mutex_unlock(&dev_priv->rps.hw_lock);
4471 }
4472
4473 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4474 {
4475         struct drm_device *dev = dev_priv->dev;
4476
4477         mutex_lock(&dev_priv->rps.hw_lock);
4478         if (dev_priv->rps.enabled) {
4479                 if (IS_VALLEYVIEW(dev))
4480                         vlv_set_rps_idle(dev_priv);
4481                 else
4482                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4483                 dev_priv->rps.last_adj = 0;
4484                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4485         }
4486         mutex_unlock(&dev_priv->rps.hw_lock);
4487
4488         spin_lock(&dev_priv->rps.client_lock);
4489         while (!list_empty(&dev_priv->rps.clients))
4490                 list_del_init(dev_priv->rps.clients.next);
4491         spin_unlock(&dev_priv->rps.client_lock);
4492 }
4493
4494 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4495                     struct intel_rps_client *rps,
4496                     unsigned long submitted)
4497 {
4498         /* This is intentionally racy! We peek at the state here, then
4499          * validate inside the RPS worker.
4500          */
4501         if (!(dev_priv->mm.busy &&
4502               dev_priv->rps.enabled &&
4503               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4504                 return;
4505
4506         /* Force a RPS boost (and don't count it against the client) if
4507          * the GPU is severely congested.
4508          */
4509         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4510                 rps = NULL;
4511
4512         spin_lock(&dev_priv->rps.client_lock);
4513         if (rps == NULL || list_empty(&rps->link)) {
4514                 spin_lock_irq(&dev_priv->irq_lock);
4515                 if (dev_priv->rps.interrupts_enabled) {
4516                         dev_priv->rps.client_boost = true;
4517                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4518                 }
4519                 spin_unlock_irq(&dev_priv->irq_lock);
4520
4521                 if (rps != NULL) {
4522                         list_add(&rps->link, &dev_priv->rps.clients);
4523                         rps->boosts++;
4524                 } else
4525                         dev_priv->rps.boosts++;
4526         }
4527         spin_unlock(&dev_priv->rps.client_lock);
4528 }
4529
4530 void intel_set_rps(struct drm_device *dev, u8 val)
4531 {
4532         if (IS_VALLEYVIEW(dev))
4533                 valleyview_set_rps(dev, val);
4534         else
4535                 gen6_set_rps(dev, val);
4536 }
4537
4538 static void gen9_disable_rps(struct drm_device *dev)
4539 {
4540         struct drm_i915_private *dev_priv = dev->dev_private;
4541
4542         I915_WRITE(GEN6_RC_CONTROL, 0);
4543         I915_WRITE(GEN9_PG_ENABLE, 0);
4544 }
4545
4546 static void gen6_disable_rps(struct drm_device *dev)
4547 {
4548         struct drm_i915_private *dev_priv = dev->dev_private;
4549
4550         I915_WRITE(GEN6_RC_CONTROL, 0);
4551         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4552 }
4553
4554 static void cherryview_disable_rps(struct drm_device *dev)
4555 {
4556         struct drm_i915_private *dev_priv = dev->dev_private;
4557
4558         I915_WRITE(GEN6_RC_CONTROL, 0);
4559 }
4560
4561 static void valleyview_disable_rps(struct drm_device *dev)
4562 {
4563         struct drm_i915_private *dev_priv = dev->dev_private;
4564
4565         /* we're doing forcewake before Disabling RC6,
4566          * This what the BIOS expects when going into suspend */
4567         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4568
4569         I915_WRITE(GEN6_RC_CONTROL, 0);
4570
4571         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4572 }
4573
4574 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4575 {
4576         if (IS_VALLEYVIEW(dev)) {
4577                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4578                         mode = GEN6_RC_CTL_RC6_ENABLE;
4579                 else
4580                         mode = 0;
4581         }
4582         if (HAS_RC6p(dev))
4583                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4584                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4585                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4586                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4587
4588         else
4589                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4590                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4591 }
4592
4593 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4594 {
4595         /* No RC6 before Ironlake and code is gone for ilk. */
4596         if (INTEL_INFO(dev)->gen < 6)
4597                 return 0;
4598
4599         /* Respect the kernel parameter if it is set */
4600         if (enable_rc6 >= 0) {
4601                 int mask;
4602
4603                 if (HAS_RC6p(dev))
4604                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4605                                INTEL_RC6pp_ENABLE;
4606                 else
4607                         mask = INTEL_RC6_ENABLE;
4608
4609                 if ((enable_rc6 & mask) != enable_rc6)
4610                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4611                                       enable_rc6 & mask, enable_rc6, mask);
4612
4613                 return enable_rc6 & mask;
4614         }
4615
4616         if (IS_IVYBRIDGE(dev))
4617                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4618
4619         return INTEL_RC6_ENABLE;
4620 }
4621
4622 int intel_enable_rc6(const struct drm_device *dev)
4623 {
4624         return i915.enable_rc6;
4625 }
4626
4627 static void gen6_init_rps_frequencies(struct drm_device *dev)
4628 {
4629         struct drm_i915_private *dev_priv = dev->dev_private;
4630         uint32_t rp_state_cap;
4631         u32 ddcc_status = 0;
4632         int ret;
4633
4634         /* All of these values are in units of 50MHz */
4635         dev_priv->rps.cur_freq          = 0;
4636         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4637         if (IS_BROXTON(dev)) {
4638                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4639                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4640                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4641                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4642         } else {
4643                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4644                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4645                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4646                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4647         }
4648
4649         /* hw_max = RP0 until we check for overclocking */
4650         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4651
4652         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4653         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4654                 ret = sandybridge_pcode_read(dev_priv,
4655                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4656                                         &ddcc_status);
4657                 if (0 == ret)
4658                         dev_priv->rps.efficient_freq =
4659                                 clamp_t(u8,
4660                                         ((ddcc_status >> 8) & 0xff),
4661                                         dev_priv->rps.min_freq,
4662                                         dev_priv->rps.max_freq);
4663         }
4664
4665         if (IS_SKYLAKE(dev)) {
4666                 /* Store the frequency values in 16.66 MHZ units, which is
4667                    the natural hardware unit for SKL */
4668                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4669                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4670                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4671                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4672                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4673         }
4674
4675         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4676
4677         /* Preserve min/max settings in case of re-init */
4678         if (dev_priv->rps.max_freq_softlimit == 0)
4679                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4680
4681         if (dev_priv->rps.min_freq_softlimit == 0) {
4682                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4683                         dev_priv->rps.min_freq_softlimit =
4684                                 max_t(int, dev_priv->rps.efficient_freq,
4685                                       intel_freq_opcode(dev_priv, 450));
4686                 else
4687                         dev_priv->rps.min_freq_softlimit =
4688                                 dev_priv->rps.min_freq;
4689         }
4690 }
4691
4692 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4693 static void gen9_enable_rps(struct drm_device *dev)
4694 {
4695         struct drm_i915_private *dev_priv = dev->dev_private;
4696
4697         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4698
4699         gen6_init_rps_frequencies(dev);
4700
4701         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4702         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4703                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4704                 return;
4705         }
4706
4707         /* Program defaults and thresholds for RPS*/
4708         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4709                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4710
4711         /* 1 second timeout*/
4712         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4713                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4714
4715         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4716
4717         /* Leaning on the below call to gen6_set_rps to program/setup the
4718          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4719          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4720         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4721         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4722
4723         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4724 }
4725
4726 static void gen9_enable_rc6(struct drm_device *dev)
4727 {
4728         struct drm_i915_private *dev_priv = dev->dev_private;
4729         struct intel_engine_cs *ring;
4730         uint32_t rc6_mask = 0;
4731         int unused;
4732
4733         /* 1a: Software RC state - RC0 */
4734         I915_WRITE(GEN6_RC_STATE, 0);
4735
4736         /* 1b: Get forcewake during program sequence. Although the driver
4737          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4738         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4739
4740         /* 2a: Disable RC states. */
4741         I915_WRITE(GEN6_RC_CONTROL, 0);
4742
4743         /* 2b: Program RC6 thresholds.*/
4744
4745         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4746         if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4747                                  (INTEL_REVID(dev) <= SKL_REVID_E0)))
4748                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4749         else
4750                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4751         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4752         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4753         for_each_ring(ring, dev_priv, unused)
4754                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4755
4756         if (HAS_GUC_UCODE(dev))
4757                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4758
4759         I915_WRITE(GEN6_RC_SLEEP, 0);
4760
4761         /* 2c: Program Coarse Power Gating Policies. */
4762         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4763         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4764
4765         /* 3a: Enable RC6 */
4766         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4767                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4768         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4769                         "on" : "off");
4770         /* WaRsUseTimeoutMode */
4771         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4772             (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
4773                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4774                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4775                            GEN7_RC_CTL_TO_MODE |
4776                            rc6_mask);
4777         } else {
4778                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4779                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4780                            GEN6_RC_CTL_EI_MODE(1) |
4781                            rc6_mask);
4782         }
4783
4784         /*
4785          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4786          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4787          */
4788         if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4789             ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
4790                 I915_WRITE(GEN9_PG_ENABLE, 0);
4791         else
4792                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4793                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4794
4795         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4796
4797 }
4798
4799 static void gen8_enable_rps(struct drm_device *dev)
4800 {
4801         struct drm_i915_private *dev_priv = dev->dev_private;
4802         struct intel_engine_cs *ring;
4803         uint32_t rc6_mask = 0;
4804         int unused;
4805
4806         /* 1a: Software RC state - RC0 */
4807         I915_WRITE(GEN6_RC_STATE, 0);
4808
4809         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4810          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4811         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4812
4813         /* 2a: Disable RC states. */
4814         I915_WRITE(GEN6_RC_CONTROL, 0);
4815
4816         /* Initialize rps frequencies */
4817         gen6_init_rps_frequencies(dev);
4818
4819         /* 2b: Program RC6 thresholds.*/
4820         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4821         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4822         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4823         for_each_ring(ring, dev_priv, unused)
4824                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4825         I915_WRITE(GEN6_RC_SLEEP, 0);
4826         if (IS_BROADWELL(dev))
4827                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4828         else
4829                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4830
4831         /* 3: Enable RC6 */
4832         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4833                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4834         intel_print_rc6_info(dev, rc6_mask);
4835         if (IS_BROADWELL(dev))
4836                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4837                                 GEN7_RC_CTL_TO_MODE |
4838                                 rc6_mask);
4839         else
4840                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4841                                 GEN6_RC_CTL_EI_MODE(1) |
4842                                 rc6_mask);
4843
4844         /* 4 Program defaults and thresholds for RPS*/
4845         I915_WRITE(GEN6_RPNSWREQ,
4846                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4847         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4848                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4849         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4850         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4851
4852         /* Docs recommend 900MHz, and 300 MHz respectively */
4853         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4854                    dev_priv->rps.max_freq_softlimit << 24 |
4855                    dev_priv->rps.min_freq_softlimit << 16);
4856
4857         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4858         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4859         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4860         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4861
4862         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4863
4864         /* 5: Enable RPS */
4865         I915_WRITE(GEN6_RP_CONTROL,
4866                    GEN6_RP_MEDIA_TURBO |
4867                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4868                    GEN6_RP_MEDIA_IS_GFX |
4869                    GEN6_RP_ENABLE |
4870                    GEN6_RP_UP_BUSY_AVG |
4871                    GEN6_RP_DOWN_IDLE_AVG);
4872
4873         /* 6: Ring frequency + overclocking (our driver does this later */
4874
4875         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4876         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4877
4878         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4879 }
4880
4881 static void gen6_enable_rps(struct drm_device *dev)
4882 {
4883         struct drm_i915_private *dev_priv = dev->dev_private;
4884         struct intel_engine_cs *ring;
4885         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4886         u32 gtfifodbg;
4887         int rc6_mode;
4888         int i, ret;
4889
4890         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4891
4892         /* Here begins a magic sequence of register writes to enable
4893          * auto-downclocking.
4894          *
4895          * Perhaps there might be some value in exposing these to
4896          * userspace...
4897          */
4898         I915_WRITE(GEN6_RC_STATE, 0);
4899
4900         /* Clear the DBG now so we don't confuse earlier errors */
4901         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4902                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4903                 I915_WRITE(GTFIFODBG, gtfifodbg);
4904         }
4905
4906         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4907
4908         /* Initialize rps frequencies */
4909         gen6_init_rps_frequencies(dev);
4910
4911         /* disable the counters and set deterministic thresholds */
4912         I915_WRITE(GEN6_RC_CONTROL, 0);
4913
4914         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4915         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4916         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4917         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4918         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4919
4920         for_each_ring(ring, dev_priv, i)
4921                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4922
4923         I915_WRITE(GEN6_RC_SLEEP, 0);
4924         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4925         if (IS_IVYBRIDGE(dev))
4926                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4927         else
4928                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4929         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4930         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4931
4932         /* Check if we are enabling RC6 */
4933         rc6_mode = intel_enable_rc6(dev_priv->dev);
4934         if (rc6_mode & INTEL_RC6_ENABLE)
4935                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4936
4937         /* We don't use those on Haswell */
4938         if (!IS_HASWELL(dev)) {
4939                 if (rc6_mode & INTEL_RC6p_ENABLE)
4940                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4941
4942                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4943                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4944         }
4945
4946         intel_print_rc6_info(dev, rc6_mask);
4947
4948         I915_WRITE(GEN6_RC_CONTROL,
4949                    rc6_mask |
4950                    GEN6_RC_CTL_EI_MODE(1) |
4951                    GEN6_RC_CTL_HW_ENABLE);
4952
4953         /* Power down if completely idle for over 50ms */
4954         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4955         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4956
4957         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4958         if (ret)
4959                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4960
4961         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4962         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4963                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4964                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4965                                  (pcu_mbox & 0xff) * 50);
4966                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4967         }
4968
4969         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4970         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4971
4972         rc6vids = 0;
4973         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4974         if (IS_GEN6(dev) && ret) {
4975                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4976         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4977                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4978                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4979                 rc6vids &= 0xffff00;
4980                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4981                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4982                 if (ret)
4983                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4984         }
4985
4986         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4987 }
4988
4989 static void __gen6_update_ring_freq(struct drm_device *dev)
4990 {
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         int min_freq = 15;
4993         unsigned int gpu_freq;
4994         unsigned int max_ia_freq, min_ring_freq;
4995         unsigned int max_gpu_freq, min_gpu_freq;
4996         int scaling_factor = 180;
4997         struct cpufreq_policy *policy;
4998
4999         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5000
5001         policy = cpufreq_cpu_get(0);
5002         if (policy) {
5003                 max_ia_freq = policy->cpuinfo.max_freq;
5004                 cpufreq_cpu_put(policy);
5005         } else {
5006                 /*
5007                  * Default to measured freq if none found, PCU will ensure we
5008                  * don't go over
5009                  */
5010                 max_ia_freq = tsc_khz;
5011         }
5012
5013         /* Convert from kHz to MHz */
5014         max_ia_freq /= 1000;
5015
5016         min_ring_freq = I915_READ(DCLK) & 0xf;
5017         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5018         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5019
5020         if (IS_SKYLAKE(dev)) {
5021                 /* Convert GT frequency to 50 HZ units */
5022                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5023                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5024         } else {
5025                 min_gpu_freq = dev_priv->rps.min_freq;
5026                 max_gpu_freq = dev_priv->rps.max_freq;
5027         }
5028
5029         /*
5030          * For each potential GPU frequency, load a ring frequency we'd like
5031          * to use for memory access.  We do this by specifying the IA frequency
5032          * the PCU should use as a reference to determine the ring frequency.
5033          */
5034         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5035                 int diff = max_gpu_freq - gpu_freq;
5036                 unsigned int ia_freq = 0, ring_freq = 0;
5037
5038                 if (IS_SKYLAKE(dev)) {
5039                         /*
5040                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5041                          * No floor required for ring frequency on SKL.
5042                          */
5043                         ring_freq = gpu_freq;
5044                 } else if (INTEL_INFO(dev)->gen >= 8) {
5045                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5046                         ring_freq = max(min_ring_freq, gpu_freq);
5047                 } else if (IS_HASWELL(dev)) {
5048                         ring_freq = mult_frac(gpu_freq, 5, 4);
5049                         ring_freq = max(min_ring_freq, ring_freq);
5050                         /* leave ia_freq as the default, chosen by cpufreq */
5051                 } else {
5052                         /* On older processors, there is no separate ring
5053                          * clock domain, so in order to boost the bandwidth
5054                          * of the ring, we need to upclock the CPU (ia_freq).
5055                          *
5056                          * For GPU frequencies less than 750MHz,
5057                          * just use the lowest ring freq.
5058                          */
5059                         if (gpu_freq < min_freq)
5060                                 ia_freq = 800;
5061                         else
5062                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5063                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5064                 }
5065
5066                 sandybridge_pcode_write(dev_priv,
5067                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5068                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5069                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5070                                         gpu_freq);
5071         }
5072 }
5073
5074 void gen6_update_ring_freq(struct drm_device *dev)
5075 {
5076         struct drm_i915_private *dev_priv = dev->dev_private;
5077
5078         if (!HAS_CORE_RING_FREQ(dev))
5079                 return;
5080
5081         mutex_lock(&dev_priv->rps.hw_lock);
5082         __gen6_update_ring_freq(dev);
5083         mutex_unlock(&dev_priv->rps.hw_lock);
5084 }
5085
5086 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5087 {
5088         struct drm_device *dev = dev_priv->dev;
5089         u32 val, rp0;
5090
5091         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5092
5093         switch (INTEL_INFO(dev)->eu_total) {
5094         case 8:
5095                 /* (2 * 4) config */
5096                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5097                 break;
5098         case 12:
5099                 /* (2 * 6) config */
5100                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5101                 break;
5102         case 16:
5103                 /* (2 * 8) config */
5104         default:
5105                 /* Setting (2 * 8) Min RP0 for any other combination */
5106                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5107                 break;
5108         }
5109
5110         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5111
5112         return rp0;
5113 }
5114
5115 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5116 {
5117         u32 val, rpe;
5118
5119         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5120         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5121
5122         return rpe;
5123 }
5124
5125 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5126 {
5127         u32 val, rp1;
5128
5129         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5130         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5131
5132         return rp1;
5133 }
5134
5135 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5136 {
5137         u32 val, rp1;
5138
5139         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5140
5141         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5142
5143         return rp1;
5144 }
5145
5146 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5147 {
5148         u32 val, rp0;
5149
5150         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5151
5152         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5153         /* Clamp to max */
5154         rp0 = min_t(u32, rp0, 0xea);
5155
5156         return rp0;
5157 }
5158
5159 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5160 {
5161         u32 val, rpe;
5162
5163         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5164         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5165         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5166         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5167
5168         return rpe;
5169 }
5170
5171 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5172 {
5173         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5174 }
5175
5176 /* Check that the pctx buffer wasn't move under us. */
5177 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5178 {
5179         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5180
5181         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5182                              dev_priv->vlv_pctx->stolen->start);
5183 }
5184
5185
5186 /* Check that the pcbr address is not empty. */
5187 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5188 {
5189         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5190
5191         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5192 }
5193
5194 static void cherryview_setup_pctx(struct drm_device *dev)
5195 {
5196         struct drm_i915_private *dev_priv = dev->dev_private;
5197         unsigned long pctx_paddr, paddr;
5198         struct i915_gtt *gtt = &dev_priv->gtt;
5199         u32 pcbr;
5200         int pctx_size = 32*1024;
5201
5202         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5203
5204         pcbr = I915_READ(VLV_PCBR);
5205         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5206                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5207                 paddr = (dev_priv->mm.stolen_base +
5208                          (gtt->stolen_size - pctx_size));
5209
5210                 pctx_paddr = (paddr & (~4095));
5211                 I915_WRITE(VLV_PCBR, pctx_paddr);
5212         }
5213
5214         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5215 }
5216
5217 static void valleyview_setup_pctx(struct drm_device *dev)
5218 {
5219         struct drm_i915_private *dev_priv = dev->dev_private;
5220         struct drm_i915_gem_object *pctx;
5221         unsigned long pctx_paddr;
5222         u32 pcbr;
5223         int pctx_size = 24*1024;
5224
5225         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5226
5227         pcbr = I915_READ(VLV_PCBR);
5228         if (pcbr) {
5229                 /* BIOS set it up already, grab the pre-alloc'd space */
5230                 int pcbr_offset;
5231
5232                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5233                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5234                                                                       pcbr_offset,
5235                                                                       I915_GTT_OFFSET_NONE,
5236                                                                       pctx_size);
5237                 goto out;
5238         }
5239
5240         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5241
5242         /*
5243          * From the Gunit register HAS:
5244          * The Gfx driver is expected to program this register and ensure
5245          * proper allocation within Gfx stolen memory.  For example, this
5246          * register should be programmed such than the PCBR range does not
5247          * overlap with other ranges, such as the frame buffer, protected
5248          * memory, or any other relevant ranges.
5249          */
5250         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5251         if (!pctx) {
5252                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5253                 return;
5254         }
5255
5256         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5257         I915_WRITE(VLV_PCBR, pctx_paddr);
5258
5259 out:
5260         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5261         dev_priv->vlv_pctx = pctx;
5262 }
5263
5264 static void valleyview_cleanup_pctx(struct drm_device *dev)
5265 {
5266         struct drm_i915_private *dev_priv = dev->dev_private;
5267
5268         if (WARN_ON(!dev_priv->vlv_pctx))
5269                 return;
5270
5271         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5272         dev_priv->vlv_pctx = NULL;
5273 }
5274
5275 static void valleyview_init_gt_powersave(struct drm_device *dev)
5276 {
5277         struct drm_i915_private *dev_priv = dev->dev_private;
5278         u32 val;
5279
5280         valleyview_setup_pctx(dev);
5281
5282         mutex_lock(&dev_priv->rps.hw_lock);
5283
5284         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5285         switch ((val >> 6) & 3) {
5286         case 0:
5287         case 1:
5288                 dev_priv->mem_freq = 800;
5289                 break;
5290         case 2:
5291                 dev_priv->mem_freq = 1066;
5292                 break;
5293         case 3:
5294                 dev_priv->mem_freq = 1333;
5295                 break;
5296         }
5297         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5298
5299         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5300         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5301         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5302                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5303                          dev_priv->rps.max_freq);
5304
5305         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5306         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5307                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5308                          dev_priv->rps.efficient_freq);
5309
5310         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5311         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5312                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5313                          dev_priv->rps.rp1_freq);
5314
5315         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5316         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5317                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5318                          dev_priv->rps.min_freq);
5319
5320         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5321
5322         /* Preserve min/max settings in case of re-init */
5323         if (dev_priv->rps.max_freq_softlimit == 0)
5324                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5325
5326         if (dev_priv->rps.min_freq_softlimit == 0)
5327                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5328
5329         mutex_unlock(&dev_priv->rps.hw_lock);
5330 }
5331
5332 static void cherryview_init_gt_powersave(struct drm_device *dev)
5333 {
5334         struct drm_i915_private *dev_priv = dev->dev_private;
5335         u32 val;
5336
5337         cherryview_setup_pctx(dev);
5338
5339         mutex_lock(&dev_priv->rps.hw_lock);
5340
5341         mutex_lock(&dev_priv->sb_lock);
5342         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5343         mutex_unlock(&dev_priv->sb_lock);
5344
5345         switch ((val >> 2) & 0x7) {
5346         case 3:
5347                 dev_priv->mem_freq = 2000;
5348                 break;
5349         default:
5350                 dev_priv->mem_freq = 1600;
5351                 break;
5352         }
5353         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5354
5355         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5356         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5357         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5358                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5359                          dev_priv->rps.max_freq);
5360
5361         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5362         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5363                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5364                          dev_priv->rps.efficient_freq);
5365
5366         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5367         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5368                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5369                          dev_priv->rps.rp1_freq);
5370
5371         /* PUnit validated range is only [RPe, RP0] */
5372         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5373         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5374                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5375                          dev_priv->rps.min_freq);
5376
5377         WARN_ONCE((dev_priv->rps.max_freq |
5378                    dev_priv->rps.efficient_freq |
5379                    dev_priv->rps.rp1_freq |
5380                    dev_priv->rps.min_freq) & 1,
5381                   "Odd GPU freq values\n");
5382
5383         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5384
5385         /* Preserve min/max settings in case of re-init */
5386         if (dev_priv->rps.max_freq_softlimit == 0)
5387                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5388
5389         if (dev_priv->rps.min_freq_softlimit == 0)
5390                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5391
5392         mutex_unlock(&dev_priv->rps.hw_lock);
5393 }
5394
5395 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5396 {
5397         valleyview_cleanup_pctx(dev);
5398 }
5399
5400 static void cherryview_enable_rps(struct drm_device *dev)
5401 {
5402         struct drm_i915_private *dev_priv = dev->dev_private;
5403         struct intel_engine_cs *ring;
5404         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5405         int i;
5406
5407         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5408
5409         gtfifodbg = I915_READ(GTFIFODBG);
5410         if (gtfifodbg) {
5411                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5412                                  gtfifodbg);
5413                 I915_WRITE(GTFIFODBG, gtfifodbg);
5414         }
5415
5416         cherryview_check_pctx(dev_priv);
5417
5418         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5419          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5420         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5421
5422         /*  Disable RC states. */
5423         I915_WRITE(GEN6_RC_CONTROL, 0);
5424
5425         /* 2a: Program RC6 thresholds.*/
5426         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5427         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5428         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5429
5430         for_each_ring(ring, dev_priv, i)
5431                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5432         I915_WRITE(GEN6_RC_SLEEP, 0);
5433
5434         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5435         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5436
5437         /* allows RC6 residency counter to work */
5438         I915_WRITE(VLV_COUNTER_CONTROL,
5439                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5440                                       VLV_MEDIA_RC6_COUNT_EN |
5441                                       VLV_RENDER_RC6_COUNT_EN));
5442
5443         /* For now we assume BIOS is allocating and populating the PCBR  */
5444         pcbr = I915_READ(VLV_PCBR);
5445
5446         /* 3: Enable RC6 */
5447         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5448                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5449                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5450
5451         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5452
5453         /* 4 Program defaults and thresholds for RPS*/
5454         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5455         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5456         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5457         I915_WRITE(GEN6_RP_UP_EI, 66000);
5458         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5459
5460         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5461
5462         /* 5: Enable RPS */
5463         I915_WRITE(GEN6_RP_CONTROL,
5464                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5465                    GEN6_RP_MEDIA_IS_GFX |
5466                    GEN6_RP_ENABLE |
5467                    GEN6_RP_UP_BUSY_AVG |
5468                    GEN6_RP_DOWN_IDLE_AVG);
5469
5470         /* Setting Fixed Bias */
5471         val = VLV_OVERRIDE_EN |
5472                   VLV_SOC_TDP_EN |
5473                   CHV_BIAS_CPU_50_SOC_50;
5474         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5475
5476         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5477
5478         /* RPS code assumes GPLL is used */
5479         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5480
5481         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5482         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5483
5484         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5485         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5486                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5487                          dev_priv->rps.cur_freq);
5488
5489         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5490                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5491                          dev_priv->rps.efficient_freq);
5492
5493         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5494
5495         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5496 }
5497
5498 static void valleyview_enable_rps(struct drm_device *dev)
5499 {
5500         struct drm_i915_private *dev_priv = dev->dev_private;
5501         struct intel_engine_cs *ring;
5502         u32 gtfifodbg, val, rc6_mode = 0;
5503         int i;
5504
5505         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5506
5507         valleyview_check_pctx(dev_priv);
5508
5509         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5510                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5511                                  gtfifodbg);
5512                 I915_WRITE(GTFIFODBG, gtfifodbg);
5513         }
5514
5515         /* If VLV, Forcewake all wells, else re-direct to regular path */
5516         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5517
5518         /*  Disable RC states. */
5519         I915_WRITE(GEN6_RC_CONTROL, 0);
5520
5521         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5522         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5523         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5524         I915_WRITE(GEN6_RP_UP_EI, 66000);
5525         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5526
5527         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5528
5529         I915_WRITE(GEN6_RP_CONTROL,
5530                    GEN6_RP_MEDIA_TURBO |
5531                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5532                    GEN6_RP_MEDIA_IS_GFX |
5533                    GEN6_RP_ENABLE |
5534                    GEN6_RP_UP_BUSY_AVG |
5535                    GEN6_RP_DOWN_IDLE_CONT);
5536
5537         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5538         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5539         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5540
5541         for_each_ring(ring, dev_priv, i)
5542                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5543
5544         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5545
5546         /* allows RC6 residency counter to work */
5547         I915_WRITE(VLV_COUNTER_CONTROL,
5548                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5549                                       VLV_RENDER_RC0_COUNT_EN |
5550                                       VLV_MEDIA_RC6_COUNT_EN |
5551                                       VLV_RENDER_RC6_COUNT_EN));
5552
5553         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5554                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5555
5556         intel_print_rc6_info(dev, rc6_mode);
5557
5558         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5559
5560         /* Setting Fixed Bias */
5561         val = VLV_OVERRIDE_EN |
5562                   VLV_SOC_TDP_EN |
5563                   VLV_BIAS_CPU_125_SOC_875;
5564         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5565
5566         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5567
5568         /* RPS code assumes GPLL is used */
5569         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5570
5571         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5572         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5573
5574         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5575         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5576                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5577                          dev_priv->rps.cur_freq);
5578
5579         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5580                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5581                          dev_priv->rps.efficient_freq);
5582
5583         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5584
5585         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5586 }
5587
5588 static unsigned long intel_pxfreq(u32 vidfreq)
5589 {
5590         unsigned long freq;
5591         int div = (vidfreq & 0x3f0000) >> 16;
5592         int post = (vidfreq & 0x3000) >> 12;
5593         int pre = (vidfreq & 0x7);
5594
5595         if (!pre)
5596                 return 0;
5597
5598         freq = ((div * 133333) / ((1<<post) * pre));
5599
5600         return freq;
5601 }
5602
5603 static const struct cparams {
5604         u16 i;
5605         u16 t;
5606         u16 m;
5607         u16 c;
5608 } cparams[] = {
5609         { 1, 1333, 301, 28664 },
5610         { 1, 1066, 294, 24460 },
5611         { 1, 800, 294, 25192 },
5612         { 0, 1333, 276, 27605 },
5613         { 0, 1066, 276, 27605 },
5614         { 0, 800, 231, 23784 },
5615 };
5616
5617 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5618 {
5619         u64 total_count, diff, ret;
5620         u32 count1, count2, count3, m = 0, c = 0;
5621         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5622         int i;
5623
5624         assert_spin_locked(&mchdev_lock);
5625
5626         diff1 = now - dev_priv->ips.last_time1;
5627
5628         /* Prevent division-by-zero if we are asking too fast.
5629          * Also, we don't get interesting results if we are polling
5630          * faster than once in 10ms, so just return the saved value
5631          * in such cases.
5632          */
5633         if (diff1 <= 10)
5634                 return dev_priv->ips.chipset_power;
5635
5636         count1 = I915_READ(DMIEC);
5637         count2 = I915_READ(DDREC);
5638         count3 = I915_READ(CSIEC);
5639
5640         total_count = count1 + count2 + count3;
5641
5642         /* FIXME: handle per-counter overflow */
5643         if (total_count < dev_priv->ips.last_count1) {
5644                 diff = ~0UL - dev_priv->ips.last_count1;
5645                 diff += total_count;
5646         } else {
5647                 diff = total_count - dev_priv->ips.last_count1;
5648         }
5649
5650         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5651                 if (cparams[i].i == dev_priv->ips.c_m &&
5652                     cparams[i].t == dev_priv->ips.r_t) {
5653                         m = cparams[i].m;
5654                         c = cparams[i].c;
5655                         break;
5656                 }
5657         }
5658
5659         diff = div_u64(diff, diff1);
5660         ret = ((m * diff) + c);
5661         ret = div_u64(ret, 10);
5662
5663         dev_priv->ips.last_count1 = total_count;
5664         dev_priv->ips.last_time1 = now;
5665
5666         dev_priv->ips.chipset_power = ret;
5667
5668         return ret;
5669 }
5670
5671 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5672 {
5673         struct drm_device *dev = dev_priv->dev;
5674         unsigned long val;
5675
5676         if (INTEL_INFO(dev)->gen != 5)
5677                 return 0;
5678
5679         spin_lock_irq(&mchdev_lock);
5680
5681         val = __i915_chipset_val(dev_priv);
5682
5683         spin_unlock_irq(&mchdev_lock);
5684
5685         return val;
5686 }
5687
5688 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5689 {
5690         unsigned long m, x, b;
5691         u32 tsfs;
5692
5693         tsfs = I915_READ(TSFS);
5694
5695         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5696         x = I915_READ8(TR1);
5697
5698         b = tsfs & TSFS_INTR_MASK;
5699
5700         return ((m * x) / 127) - b;
5701 }
5702
5703 static int _pxvid_to_vd(u8 pxvid)
5704 {
5705         if (pxvid == 0)
5706                 return 0;
5707
5708         if (pxvid >= 8 && pxvid < 31)
5709                 pxvid = 31;
5710
5711         return (pxvid + 2) * 125;
5712 }
5713
5714 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5715 {
5716         struct drm_device *dev = dev_priv->dev;
5717         const int vd = _pxvid_to_vd(pxvid);
5718         const int vm = vd - 1125;
5719
5720         if (INTEL_INFO(dev)->is_mobile)
5721                 return vm > 0 ? vm : 0;
5722
5723         return vd;
5724 }
5725
5726 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5727 {
5728         u64 now, diff, diffms;
5729         u32 count;
5730
5731         assert_spin_locked(&mchdev_lock);
5732
5733         now = ktime_get_raw_ns();
5734         diffms = now - dev_priv->ips.last_time2;
5735         do_div(diffms, NSEC_PER_MSEC);
5736
5737         /* Don't divide by 0 */
5738         if (!diffms)
5739                 return;
5740
5741         count = I915_READ(GFXEC);
5742
5743         if (count < dev_priv->ips.last_count2) {
5744                 diff = ~0UL - dev_priv->ips.last_count2;
5745                 diff += count;
5746         } else {
5747                 diff = count - dev_priv->ips.last_count2;
5748         }
5749
5750         dev_priv->ips.last_count2 = count;
5751         dev_priv->ips.last_time2 = now;
5752
5753         /* More magic constants... */
5754         diff = diff * 1181;
5755         diff = div_u64(diff, diffms * 10);
5756         dev_priv->ips.gfx_power = diff;
5757 }
5758
5759 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5760 {
5761         struct drm_device *dev = dev_priv->dev;
5762
5763         if (INTEL_INFO(dev)->gen != 5)
5764                 return;
5765
5766         spin_lock_irq(&mchdev_lock);
5767
5768         __i915_update_gfx_val(dev_priv);
5769
5770         spin_unlock_irq(&mchdev_lock);
5771 }
5772
5773 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5774 {
5775         unsigned long t, corr, state1, corr2, state2;
5776         u32 pxvid, ext_v;
5777
5778         assert_spin_locked(&mchdev_lock);
5779
5780         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5781         pxvid = (pxvid >> 24) & 0x7f;
5782         ext_v = pvid_to_extvid(dev_priv, pxvid);
5783
5784         state1 = ext_v;
5785
5786         t = i915_mch_val(dev_priv);
5787
5788         /* Revel in the empirically derived constants */
5789
5790         /* Correction factor in 1/100000 units */
5791         if (t > 80)
5792                 corr = ((t * 2349) + 135940);
5793         else if (t >= 50)
5794                 corr = ((t * 964) + 29317);
5795         else /* < 50 */
5796                 corr = ((t * 301) + 1004);
5797
5798         corr = corr * ((150142 * state1) / 10000 - 78642);
5799         corr /= 100000;
5800         corr2 = (corr * dev_priv->ips.corr);
5801
5802         state2 = (corr2 * state1) / 10000;
5803         state2 /= 100; /* convert to mW */
5804
5805         __i915_update_gfx_val(dev_priv);
5806
5807         return dev_priv->ips.gfx_power + state2;
5808 }
5809
5810 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5811 {
5812         struct drm_device *dev = dev_priv->dev;
5813         unsigned long val;
5814
5815         if (INTEL_INFO(dev)->gen != 5)
5816                 return 0;
5817
5818         spin_lock_irq(&mchdev_lock);
5819
5820         val = __i915_gfx_val(dev_priv);
5821
5822         spin_unlock_irq(&mchdev_lock);
5823
5824         return val;
5825 }
5826
5827 /**
5828  * i915_read_mch_val - return value for IPS use
5829  *
5830  * Calculate and return a value for the IPS driver to use when deciding whether
5831  * we have thermal and power headroom to increase CPU or GPU power budget.
5832  */
5833 unsigned long i915_read_mch_val(void)
5834 {
5835         struct drm_i915_private *dev_priv;
5836         unsigned long chipset_val, graphics_val, ret = 0;
5837
5838         spin_lock_irq(&mchdev_lock);
5839         if (!i915_mch_dev)
5840                 goto out_unlock;
5841         dev_priv = i915_mch_dev;
5842
5843         chipset_val = __i915_chipset_val(dev_priv);
5844         graphics_val = __i915_gfx_val(dev_priv);
5845
5846         ret = chipset_val + graphics_val;
5847
5848 out_unlock:
5849         spin_unlock_irq(&mchdev_lock);
5850
5851         return ret;
5852 }
5853 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5854
5855 /**
5856  * i915_gpu_raise - raise GPU frequency limit
5857  *
5858  * Raise the limit; IPS indicates we have thermal headroom.
5859  */
5860 bool i915_gpu_raise(void)
5861 {
5862         struct drm_i915_private *dev_priv;
5863         bool ret = true;
5864
5865         spin_lock_irq(&mchdev_lock);
5866         if (!i915_mch_dev) {
5867                 ret = false;
5868                 goto out_unlock;
5869         }
5870         dev_priv = i915_mch_dev;
5871
5872         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5873                 dev_priv->ips.max_delay--;
5874
5875 out_unlock:
5876         spin_unlock_irq(&mchdev_lock);
5877
5878         return ret;
5879 }
5880 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5881
5882 /**
5883  * i915_gpu_lower - lower GPU frequency limit
5884  *
5885  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5886  * frequency maximum.
5887  */
5888 bool i915_gpu_lower(void)
5889 {
5890         struct drm_i915_private *dev_priv;
5891         bool ret = true;
5892
5893         spin_lock_irq(&mchdev_lock);
5894         if (!i915_mch_dev) {
5895                 ret = false;
5896                 goto out_unlock;
5897         }
5898         dev_priv = i915_mch_dev;
5899
5900         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5901                 dev_priv->ips.max_delay++;
5902
5903 out_unlock:
5904         spin_unlock_irq(&mchdev_lock);
5905
5906         return ret;
5907 }
5908 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5909
5910 /**
5911  * i915_gpu_busy - indicate GPU business to IPS
5912  *
5913  * Tell the IPS driver whether or not the GPU is busy.
5914  */
5915 bool i915_gpu_busy(void)
5916 {
5917         struct drm_i915_private *dev_priv;
5918         struct intel_engine_cs *ring;
5919         bool ret = false;
5920         int i;
5921
5922         spin_lock_irq(&mchdev_lock);
5923         if (!i915_mch_dev)
5924                 goto out_unlock;
5925         dev_priv = i915_mch_dev;
5926
5927         for_each_ring(ring, dev_priv, i)
5928                 ret |= !list_empty(&ring->request_list);
5929
5930 out_unlock:
5931         spin_unlock_irq(&mchdev_lock);
5932
5933         return ret;
5934 }
5935 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5936
5937 /**
5938  * i915_gpu_turbo_disable - disable graphics turbo
5939  *
5940  * Disable graphics turbo by resetting the max frequency and setting the
5941  * current frequency to the default.
5942  */
5943 bool i915_gpu_turbo_disable(void)
5944 {
5945         struct drm_i915_private *dev_priv;
5946         bool ret = true;
5947
5948         spin_lock_irq(&mchdev_lock);
5949         if (!i915_mch_dev) {
5950                 ret = false;
5951                 goto out_unlock;
5952         }
5953         dev_priv = i915_mch_dev;
5954
5955         dev_priv->ips.max_delay = dev_priv->ips.fstart;
5956
5957         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5958                 ret = false;
5959
5960 out_unlock:
5961         spin_unlock_irq(&mchdev_lock);
5962
5963         return ret;
5964 }
5965 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5966
5967 /**
5968  * Tells the intel_ips driver that the i915 driver is now loaded, if
5969  * IPS got loaded first.
5970  *
5971  * This awkward dance is so that neither module has to depend on the
5972  * other in order for IPS to do the appropriate communication of
5973  * GPU turbo limits to i915.
5974  */
5975 static void
5976 ips_ping_for_i915_load(void)
5977 {
5978         void (*link)(void);
5979
5980         link = symbol_get(ips_link_to_i915_driver);
5981         if (link) {
5982                 link();
5983                 symbol_put(ips_link_to_i915_driver);
5984         }
5985 }
5986
5987 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5988 {
5989         /* We only register the i915 ips part with intel-ips once everything is
5990          * set up, to avoid intel-ips sneaking in and reading bogus values. */
5991         spin_lock_irq(&mchdev_lock);
5992         i915_mch_dev = dev_priv;
5993         spin_unlock_irq(&mchdev_lock);
5994
5995         ips_ping_for_i915_load();
5996 }
5997
5998 void intel_gpu_ips_teardown(void)
5999 {
6000         spin_lock_irq(&mchdev_lock);
6001         i915_mch_dev = NULL;
6002         spin_unlock_irq(&mchdev_lock);
6003 }
6004
6005 static void intel_init_emon(struct drm_device *dev)
6006 {
6007         struct drm_i915_private *dev_priv = dev->dev_private;
6008         u32 lcfuse;
6009         u8 pxw[16];
6010         int i;
6011
6012         /* Disable to program */
6013         I915_WRITE(ECR, 0);
6014         POSTING_READ(ECR);
6015
6016         /* Program energy weights for various events */
6017         I915_WRITE(SDEW, 0x15040d00);
6018         I915_WRITE(CSIEW0, 0x007f0000);
6019         I915_WRITE(CSIEW1, 0x1e220004);
6020         I915_WRITE(CSIEW2, 0x04000004);
6021
6022         for (i = 0; i < 5; i++)
6023                 I915_WRITE(PEW(i), 0);
6024         for (i = 0; i < 3; i++)
6025                 I915_WRITE(DEW(i), 0);
6026
6027         /* Program P-state weights to account for frequency power adjustment */
6028         for (i = 0; i < 16; i++) {
6029                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6030                 unsigned long freq = intel_pxfreq(pxvidfreq);
6031                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6032                         PXVFREQ_PX_SHIFT;
6033                 unsigned long val;
6034
6035                 val = vid * vid;
6036                 val *= (freq / 1000);
6037                 val *= 255;
6038                 val /= (127*127*900);
6039                 if (val > 0xff)
6040                         DRM_ERROR("bad pxval: %ld\n", val);
6041                 pxw[i] = val;
6042         }
6043         /* Render standby states get 0 weight */
6044         pxw[14] = 0;
6045         pxw[15] = 0;
6046
6047         for (i = 0; i < 4; i++) {
6048                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6049                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6050                 I915_WRITE(PXW(i), val);
6051         }
6052
6053         /* Adjust magic regs to magic values (more experimental results) */
6054         I915_WRITE(OGW0, 0);
6055         I915_WRITE(OGW1, 0);
6056         I915_WRITE(EG0, 0x00007f00);
6057         I915_WRITE(EG1, 0x0000000e);
6058         I915_WRITE(EG2, 0x000e0000);
6059         I915_WRITE(EG3, 0x68000300);
6060         I915_WRITE(EG4, 0x42000000);
6061         I915_WRITE(EG5, 0x00140031);
6062         I915_WRITE(EG6, 0);
6063         I915_WRITE(EG7, 0);
6064
6065         for (i = 0; i < 8; i++)
6066                 I915_WRITE(PXWL(i), 0);
6067
6068         /* Enable PMON + select events */
6069         I915_WRITE(ECR, 0x80000019);
6070
6071         lcfuse = I915_READ(LCFUSE02);
6072
6073         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6074 }
6075
6076 void intel_init_gt_powersave(struct drm_device *dev)
6077 {
6078         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6079
6080         if (IS_CHERRYVIEW(dev))
6081                 cherryview_init_gt_powersave(dev);
6082         else if (IS_VALLEYVIEW(dev))
6083                 valleyview_init_gt_powersave(dev);
6084 }
6085
6086 void intel_cleanup_gt_powersave(struct drm_device *dev)
6087 {
6088         if (IS_CHERRYVIEW(dev))
6089                 return;
6090         else if (IS_VALLEYVIEW(dev))
6091                 valleyview_cleanup_gt_powersave(dev);
6092 }
6093
6094 static void gen6_suspend_rps(struct drm_device *dev)
6095 {
6096         struct drm_i915_private *dev_priv = dev->dev_private;
6097
6098         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6099
6100         gen6_disable_rps_interrupts(dev);
6101 }
6102
6103 /**
6104  * intel_suspend_gt_powersave - suspend PM work and helper threads
6105  * @dev: drm device
6106  *
6107  * We don't want to disable RC6 or other features here, we just want
6108  * to make sure any work we've queued has finished and won't bother
6109  * us while we're suspended.
6110  */
6111 void intel_suspend_gt_powersave(struct drm_device *dev)
6112 {
6113         struct drm_i915_private *dev_priv = dev->dev_private;
6114
6115         if (INTEL_INFO(dev)->gen < 6)
6116                 return;
6117
6118         gen6_suspend_rps(dev);
6119
6120         /* Force GPU to min freq during suspend */
6121         gen6_rps_idle(dev_priv);
6122 }
6123
6124 void intel_disable_gt_powersave(struct drm_device *dev)
6125 {
6126         struct drm_i915_private *dev_priv = dev->dev_private;
6127
6128         if (IS_IRONLAKE_M(dev)) {
6129                 ironlake_disable_drps(dev);
6130         } else if (INTEL_INFO(dev)->gen >= 6) {
6131                 intel_suspend_gt_powersave(dev);
6132
6133                 mutex_lock(&dev_priv->rps.hw_lock);
6134                 if (INTEL_INFO(dev)->gen >= 9)
6135                         gen9_disable_rps(dev);
6136                 else if (IS_CHERRYVIEW(dev))
6137                         cherryview_disable_rps(dev);
6138                 else if (IS_VALLEYVIEW(dev))
6139                         valleyview_disable_rps(dev);
6140                 else
6141                         gen6_disable_rps(dev);
6142
6143                 dev_priv->rps.enabled = false;
6144                 mutex_unlock(&dev_priv->rps.hw_lock);
6145         }
6146 }
6147
6148 static void intel_gen6_powersave_work(struct work_struct *work)
6149 {
6150         struct drm_i915_private *dev_priv =
6151                 container_of(work, struct drm_i915_private,
6152                              rps.delayed_resume_work.work);
6153         struct drm_device *dev = dev_priv->dev;
6154
6155         mutex_lock(&dev_priv->rps.hw_lock);
6156
6157         gen6_reset_rps_interrupts(dev);
6158
6159         if (IS_CHERRYVIEW(dev)) {
6160                 cherryview_enable_rps(dev);
6161         } else if (IS_VALLEYVIEW(dev)) {
6162                 valleyview_enable_rps(dev);
6163         } else if (INTEL_INFO(dev)->gen >= 9) {
6164                 gen9_enable_rc6(dev);
6165                 gen9_enable_rps(dev);
6166                 if (IS_SKYLAKE(dev))
6167                         __gen6_update_ring_freq(dev);
6168         } else if (IS_BROADWELL(dev)) {
6169                 gen8_enable_rps(dev);
6170                 __gen6_update_ring_freq(dev);
6171         } else {
6172                 gen6_enable_rps(dev);
6173                 __gen6_update_ring_freq(dev);
6174         }
6175
6176         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6177         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6178
6179         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6180         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6181
6182         dev_priv->rps.enabled = true;
6183
6184         gen6_enable_rps_interrupts(dev);
6185
6186         mutex_unlock(&dev_priv->rps.hw_lock);
6187
6188         intel_runtime_pm_put(dev_priv);
6189 }
6190
6191 void intel_enable_gt_powersave(struct drm_device *dev)
6192 {
6193         struct drm_i915_private *dev_priv = dev->dev_private;
6194
6195         /* Powersaving is controlled by the host when inside a VM */
6196         if (intel_vgpu_active(dev))
6197                 return;
6198
6199         if (IS_IRONLAKE_M(dev)) {
6200                 mutex_lock(&dev->struct_mutex);
6201                 ironlake_enable_drps(dev);
6202                 intel_init_emon(dev);
6203                 mutex_unlock(&dev->struct_mutex);
6204         } else if (INTEL_INFO(dev)->gen >= 6) {
6205                 /*
6206                  * PCU communication is slow and this doesn't need to be
6207                  * done at any specific time, so do this out of our fast path
6208                  * to make resume and init faster.
6209                  *
6210                  * We depend on the HW RC6 power context save/restore
6211                  * mechanism when entering D3 through runtime PM suspend. So
6212                  * disable RPM until RPS/RC6 is properly setup. We can only
6213                  * get here via the driver load/system resume/runtime resume
6214                  * paths, so the _noresume version is enough (and in case of
6215                  * runtime resume it's necessary).
6216                  */
6217                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6218                                            round_jiffies_up_relative(HZ)))
6219                         intel_runtime_pm_get_noresume(dev_priv);
6220         }
6221 }
6222
6223 void intel_reset_gt_powersave(struct drm_device *dev)
6224 {
6225         struct drm_i915_private *dev_priv = dev->dev_private;
6226
6227         if (INTEL_INFO(dev)->gen < 6)
6228                 return;
6229
6230         gen6_suspend_rps(dev);
6231         dev_priv->rps.enabled = false;
6232 }
6233
6234 static void ibx_init_clock_gating(struct drm_device *dev)
6235 {
6236         struct drm_i915_private *dev_priv = dev->dev_private;
6237
6238         /*
6239          * On Ibex Peak and Cougar Point, we need to disable clock
6240          * gating for the panel power sequencer or it will fail to
6241          * start up when no ports are active.
6242          */
6243         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6244 }
6245
6246 static void g4x_disable_trickle_feed(struct drm_device *dev)
6247 {
6248         struct drm_i915_private *dev_priv = dev->dev_private;
6249         enum pipe pipe;
6250
6251         for_each_pipe(dev_priv, pipe) {
6252                 I915_WRITE(DSPCNTR(pipe),
6253                            I915_READ(DSPCNTR(pipe)) |
6254                            DISPPLANE_TRICKLE_FEED_DISABLE);
6255
6256                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6257                 POSTING_READ(DSPSURF(pipe));
6258         }
6259 }
6260
6261 static void ilk_init_lp_watermarks(struct drm_device *dev)
6262 {
6263         struct drm_i915_private *dev_priv = dev->dev_private;
6264
6265         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6266         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6267         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6268
6269         /*
6270          * Don't touch WM1S_LP_EN here.
6271          * Doing so could cause underruns.
6272          */
6273 }
6274
6275 static void ironlake_init_clock_gating(struct drm_device *dev)
6276 {
6277         struct drm_i915_private *dev_priv = dev->dev_private;
6278         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6279
6280         /*
6281          * Required for FBC
6282          * WaFbcDisableDpfcClockGating:ilk
6283          */
6284         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6285                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6286                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6287
6288         I915_WRITE(PCH_3DCGDIS0,
6289                    MARIUNIT_CLOCK_GATE_DISABLE |
6290                    SVSMUNIT_CLOCK_GATE_DISABLE);
6291         I915_WRITE(PCH_3DCGDIS1,
6292                    VFMUNIT_CLOCK_GATE_DISABLE);
6293
6294         /*
6295          * According to the spec the following bits should be set in
6296          * order to enable memory self-refresh
6297          * The bit 22/21 of 0x42004
6298          * The bit 5 of 0x42020
6299          * The bit 15 of 0x45000
6300          */
6301         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6302                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6303                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6304         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6305         I915_WRITE(DISP_ARB_CTL,
6306                    (I915_READ(DISP_ARB_CTL) |
6307                     DISP_FBC_WM_DIS));
6308
6309         ilk_init_lp_watermarks(dev);
6310
6311         /*
6312          * Based on the document from hardware guys the following bits
6313          * should be set unconditionally in order to enable FBC.
6314          * The bit 22 of 0x42000
6315          * The bit 22 of 0x42004
6316          * The bit 7,8,9 of 0x42020.
6317          */
6318         if (IS_IRONLAKE_M(dev)) {
6319                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6320                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6321                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6322                            ILK_FBCQ_DIS);
6323                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6324                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6325                            ILK_DPARB_GATE);
6326         }
6327
6328         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6329
6330         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6331                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6332                    ILK_ELPIN_409_SELECT);
6333         I915_WRITE(_3D_CHICKEN2,
6334                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6335                    _3D_CHICKEN2_WM_READ_PIPELINED);
6336
6337         /* WaDisableRenderCachePipelinedFlush:ilk */
6338         I915_WRITE(CACHE_MODE_0,
6339                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6340
6341         /* WaDisable_RenderCache_OperationalFlush:ilk */
6342         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6343
6344         g4x_disable_trickle_feed(dev);
6345
6346         ibx_init_clock_gating(dev);
6347 }
6348
6349 static void cpt_init_clock_gating(struct drm_device *dev)
6350 {
6351         struct drm_i915_private *dev_priv = dev->dev_private;
6352         int pipe;
6353         uint32_t val;
6354
6355         /*
6356          * On Ibex Peak and Cougar Point, we need to disable clock
6357          * gating for the panel power sequencer or it will fail to
6358          * start up when no ports are active.
6359          */
6360         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6361                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6362                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6363         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6364                    DPLS_EDP_PPS_FIX_DIS);
6365         /* The below fixes the weird display corruption, a few pixels shifted
6366          * downward, on (only) LVDS of some HP laptops with IVY.
6367          */
6368         for_each_pipe(dev_priv, pipe) {
6369                 val = I915_READ(TRANS_CHICKEN2(pipe));
6370                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6371                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6372                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6373                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6374                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6375                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6376                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6377                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6378         }
6379         /* WADP0ClockGatingDisable */
6380         for_each_pipe(dev_priv, pipe) {
6381                 I915_WRITE(TRANS_CHICKEN1(pipe),
6382                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6383         }
6384 }
6385
6386 static void gen6_check_mch_setup(struct drm_device *dev)
6387 {
6388         struct drm_i915_private *dev_priv = dev->dev_private;
6389         uint32_t tmp;
6390
6391         tmp = I915_READ(MCH_SSKPD);
6392         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6393                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6394                               tmp);
6395 }
6396
6397 static void gen6_init_clock_gating(struct drm_device *dev)
6398 {
6399         struct drm_i915_private *dev_priv = dev->dev_private;
6400         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6401
6402         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6403
6404         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6405                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6406                    ILK_ELPIN_409_SELECT);
6407
6408         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6409         I915_WRITE(_3D_CHICKEN,
6410                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6411
6412         /* WaDisable_RenderCache_OperationalFlush:snb */
6413         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6414
6415         /*
6416          * BSpec recoomends 8x4 when MSAA is used,
6417          * however in practice 16x4 seems fastest.
6418          *
6419          * Note that PS/WM thread counts depend on the WIZ hashing
6420          * disable bit, which we don't touch here, but it's good
6421          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6422          */
6423         I915_WRITE(GEN6_GT_MODE,
6424                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6425
6426         ilk_init_lp_watermarks(dev);
6427
6428         I915_WRITE(CACHE_MODE_0,
6429                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6430
6431         I915_WRITE(GEN6_UCGCTL1,
6432                    I915_READ(GEN6_UCGCTL1) |
6433                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6434                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6435
6436         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6437          * gating disable must be set.  Failure to set it results in
6438          * flickering pixels due to Z write ordering failures after
6439          * some amount of runtime in the Mesa "fire" demo, and Unigine
6440          * Sanctuary and Tropics, and apparently anything else with
6441          * alpha test or pixel discard.
6442          *
6443          * According to the spec, bit 11 (RCCUNIT) must also be set,
6444          * but we didn't debug actual testcases to find it out.
6445          *
6446          * WaDisableRCCUnitClockGating:snb
6447          * WaDisableRCPBUnitClockGating:snb
6448          */
6449         I915_WRITE(GEN6_UCGCTL2,
6450                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6451                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6452
6453         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6454         I915_WRITE(_3D_CHICKEN3,
6455                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6456
6457         /*
6458          * Bspec says:
6459          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6460          * 3DSTATE_SF number of SF output attributes is more than 16."
6461          */
6462         I915_WRITE(_3D_CHICKEN3,
6463                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6464
6465         /*
6466          * According to the spec the following bits should be
6467          * set in order to enable memory self-refresh and fbc:
6468          * The bit21 and bit22 of 0x42000
6469          * The bit21 and bit22 of 0x42004
6470          * The bit5 and bit7 of 0x42020
6471          * The bit14 of 0x70180
6472          * The bit14 of 0x71180
6473          *
6474          * WaFbcAsynchFlipDisableFbcQueue:snb
6475          */
6476         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6477                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6478                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6479         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6480                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6481                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6482         I915_WRITE(ILK_DSPCLK_GATE_D,
6483                    I915_READ(ILK_DSPCLK_GATE_D) |
6484                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6485                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6486
6487         g4x_disable_trickle_feed(dev);
6488
6489         cpt_init_clock_gating(dev);
6490
6491         gen6_check_mch_setup(dev);
6492 }
6493
6494 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6495 {
6496         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6497
6498         /*
6499          * WaVSThreadDispatchOverride:ivb,vlv
6500          *
6501          * This actually overrides the dispatch
6502          * mode for all thread types.
6503          */
6504         reg &= ~GEN7_FF_SCHED_MASK;
6505         reg |= GEN7_FF_TS_SCHED_HW;
6506         reg |= GEN7_FF_VS_SCHED_HW;
6507         reg |= GEN7_FF_DS_SCHED_HW;
6508
6509         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6510 }
6511
6512 static void lpt_init_clock_gating(struct drm_device *dev)
6513 {
6514         struct drm_i915_private *dev_priv = dev->dev_private;
6515
6516         /*
6517          * TODO: this bit should only be enabled when really needed, then
6518          * disabled when not needed anymore in order to save power.
6519          */
6520         if (HAS_PCH_LPT_LP(dev))
6521                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6522                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6523                            PCH_LP_PARTITION_LEVEL_DISABLE);
6524
6525         /* WADPOClockGatingDisable:hsw */
6526         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6527                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6528                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6529 }
6530
6531 static void lpt_suspend_hw(struct drm_device *dev)
6532 {
6533         struct drm_i915_private *dev_priv = dev->dev_private;
6534
6535         if (HAS_PCH_LPT_LP(dev)) {
6536                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6537
6538                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6539                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6540         }
6541 }
6542
6543 static void broadwell_init_clock_gating(struct drm_device *dev)
6544 {
6545         struct drm_i915_private *dev_priv = dev->dev_private;
6546         enum pipe pipe;
6547         uint32_t misccpctl;
6548
6549         ilk_init_lp_watermarks(dev);
6550
6551         /* WaSwitchSolVfFArbitrationPriority:bdw */
6552         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6553
6554         /* WaPsrDPAMaskVBlankInSRD:bdw */
6555         I915_WRITE(CHICKEN_PAR1_1,
6556                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6557
6558         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6559         for_each_pipe(dev_priv, pipe) {
6560                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6561                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6562                            BDW_DPRS_MASK_VBLANK_SRD);
6563         }
6564
6565         /* WaVSRefCountFullforceMissDisable:bdw */
6566         /* WaDSRefCountFullforceMissDisable:bdw */
6567         I915_WRITE(GEN7_FF_THREAD_MODE,
6568                    I915_READ(GEN7_FF_THREAD_MODE) &
6569                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6570
6571         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6572                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6573
6574         /* WaDisableSDEUnitClockGating:bdw */
6575         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6576                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6577
6578         /*
6579          * WaProgramL3SqcReg1Default:bdw
6580          * WaTempDisableDOPClkGating:bdw
6581          */
6582         misccpctl = I915_READ(GEN7_MISCCPCTL);
6583         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6584         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6585         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6586
6587         /*
6588          * WaGttCachingOffByDefault:bdw
6589          * GTT cache may not work with big pages, so if those
6590          * are ever enabled GTT cache may need to be disabled.
6591          */
6592         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6593
6594         lpt_init_clock_gating(dev);
6595 }
6596
6597 static void haswell_init_clock_gating(struct drm_device *dev)
6598 {
6599         struct drm_i915_private *dev_priv = dev->dev_private;
6600
6601         ilk_init_lp_watermarks(dev);
6602
6603         /* L3 caching of data atomics doesn't work -- disable it. */
6604         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6605         I915_WRITE(HSW_ROW_CHICKEN3,
6606                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6607
6608         /* This is required by WaCatErrorRejectionIssue:hsw */
6609         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6610                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6611                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6612
6613         /* WaVSRefCountFullforceMissDisable:hsw */
6614         I915_WRITE(GEN7_FF_THREAD_MODE,
6615                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6616
6617         /* WaDisable_RenderCache_OperationalFlush:hsw */
6618         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6619
6620         /* enable HiZ Raw Stall Optimization */
6621         I915_WRITE(CACHE_MODE_0_GEN7,
6622                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6623
6624         /* WaDisable4x2SubspanOptimization:hsw */
6625         I915_WRITE(CACHE_MODE_1,
6626                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6627
6628         /*
6629          * BSpec recommends 8x4 when MSAA is used,
6630          * however in practice 16x4 seems fastest.
6631          *
6632          * Note that PS/WM thread counts depend on the WIZ hashing
6633          * disable bit, which we don't touch here, but it's good
6634          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6635          */
6636         I915_WRITE(GEN7_GT_MODE,
6637                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6638
6639         /* WaSampleCChickenBitEnable:hsw */
6640         I915_WRITE(HALF_SLICE_CHICKEN3,
6641                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6642
6643         /* WaSwitchSolVfFArbitrationPriority:hsw */
6644         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6645
6646         /* WaRsPkgCStateDisplayPMReq:hsw */
6647         I915_WRITE(CHICKEN_PAR1_1,
6648                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6649
6650         lpt_init_clock_gating(dev);
6651 }
6652
6653 static void ivybridge_init_clock_gating(struct drm_device *dev)
6654 {
6655         struct drm_i915_private *dev_priv = dev->dev_private;
6656         uint32_t snpcr;
6657
6658         ilk_init_lp_watermarks(dev);
6659
6660         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6661
6662         /* WaDisableEarlyCull:ivb */
6663         I915_WRITE(_3D_CHICKEN3,
6664                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6665
6666         /* WaDisableBackToBackFlipFix:ivb */
6667         I915_WRITE(IVB_CHICKEN3,
6668                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6669                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6670
6671         /* WaDisablePSDDualDispatchEnable:ivb */
6672         if (IS_IVB_GT1(dev))
6673                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6674                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6675
6676         /* WaDisable_RenderCache_OperationalFlush:ivb */
6677         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6678
6679         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6680         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6681                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6682
6683         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6684         I915_WRITE(GEN7_L3CNTLREG1,
6685                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6686         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6687                    GEN7_WA_L3_CHICKEN_MODE);
6688         if (IS_IVB_GT1(dev))
6689                 I915_WRITE(GEN7_ROW_CHICKEN2,
6690                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6691         else {
6692                 /* must write both registers */
6693                 I915_WRITE(GEN7_ROW_CHICKEN2,
6694                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6695                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6696                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6697         }
6698
6699         /* WaForceL3Serialization:ivb */
6700         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6701                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6702
6703         /*
6704          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6705          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6706          */
6707         I915_WRITE(GEN6_UCGCTL2,
6708                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6709
6710         /* This is required by WaCatErrorRejectionIssue:ivb */
6711         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6712                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6713                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6714
6715         g4x_disable_trickle_feed(dev);
6716
6717         gen7_setup_fixed_func_scheduler(dev_priv);
6718
6719         if (0) { /* causes HiZ corruption on ivb:gt1 */
6720                 /* enable HiZ Raw Stall Optimization */
6721                 I915_WRITE(CACHE_MODE_0_GEN7,
6722                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6723         }
6724
6725         /* WaDisable4x2SubspanOptimization:ivb */
6726         I915_WRITE(CACHE_MODE_1,
6727                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6728
6729         /*
6730          * BSpec recommends 8x4 when MSAA is used,
6731          * however in practice 16x4 seems fastest.
6732          *
6733          * Note that PS/WM thread counts depend on the WIZ hashing
6734          * disable bit, which we don't touch here, but it's good
6735          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6736          */
6737         I915_WRITE(GEN7_GT_MODE,
6738                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6739
6740         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6741         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6742         snpcr |= GEN6_MBC_SNPCR_MED;
6743         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6744
6745         if (!HAS_PCH_NOP(dev))
6746                 cpt_init_clock_gating(dev);
6747
6748         gen6_check_mch_setup(dev);
6749 }
6750
6751 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6752 {
6753         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6754
6755         /*
6756          * Disable trickle feed and enable pnd deadline calculation
6757          */
6758         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6759         I915_WRITE(CBR1_VLV, 0);
6760 }
6761
6762 static void valleyview_init_clock_gating(struct drm_device *dev)
6763 {
6764         struct drm_i915_private *dev_priv = dev->dev_private;
6765
6766         vlv_init_display_clock_gating(dev_priv);
6767
6768         /* WaDisableEarlyCull:vlv */
6769         I915_WRITE(_3D_CHICKEN3,
6770                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6771
6772         /* WaDisableBackToBackFlipFix:vlv */
6773         I915_WRITE(IVB_CHICKEN3,
6774                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6775                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6776
6777         /* WaPsdDispatchEnable:vlv */
6778         /* WaDisablePSDDualDispatchEnable:vlv */
6779         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6780                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6781                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6782
6783         /* WaDisable_RenderCache_OperationalFlush:vlv */
6784         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6785
6786         /* WaForceL3Serialization:vlv */
6787         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6788                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6789
6790         /* WaDisableDopClockGating:vlv */
6791         I915_WRITE(GEN7_ROW_CHICKEN2,
6792                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6793
6794         /* This is required by WaCatErrorRejectionIssue:vlv */
6795         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6796                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6797                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6798
6799         gen7_setup_fixed_func_scheduler(dev_priv);
6800
6801         /*
6802          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6803          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6804          */
6805         I915_WRITE(GEN6_UCGCTL2,
6806                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6807
6808         /* WaDisableL3Bank2xClockGate:vlv
6809          * Disabling L3 clock gating- MMIO 940c[25] = 1
6810          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6811         I915_WRITE(GEN7_UCGCTL4,
6812                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6813
6814         /*
6815          * BSpec says this must be set, even though
6816          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6817          */
6818         I915_WRITE(CACHE_MODE_1,
6819                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6820
6821         /*
6822          * BSpec recommends 8x4 when MSAA is used,
6823          * however in practice 16x4 seems fastest.
6824          *
6825          * Note that PS/WM thread counts depend on the WIZ hashing
6826          * disable bit, which we don't touch here, but it's good
6827          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6828          */
6829         I915_WRITE(GEN7_GT_MODE,
6830                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6831
6832         /*
6833          * WaIncreaseL3CreditsForVLVB0:vlv
6834          * This is the hardware default actually.
6835          */
6836         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6837
6838         /*
6839          * WaDisableVLVClockGating_VBIIssue:vlv
6840          * Disable clock gating on th GCFG unit to prevent a delay
6841          * in the reporting of vblank events.
6842          */
6843         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6844 }
6845
6846 static void cherryview_init_clock_gating(struct drm_device *dev)
6847 {
6848         struct drm_i915_private *dev_priv = dev->dev_private;
6849
6850         vlv_init_display_clock_gating(dev_priv);
6851
6852         /* WaVSRefCountFullforceMissDisable:chv */
6853         /* WaDSRefCountFullforceMissDisable:chv */
6854         I915_WRITE(GEN7_FF_THREAD_MODE,
6855                    I915_READ(GEN7_FF_THREAD_MODE) &
6856                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6857
6858         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6859         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6860                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6861
6862         /* WaDisableCSUnitClockGating:chv */
6863         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6864                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6865
6866         /* WaDisableSDEUnitClockGating:chv */
6867         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6868                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6869
6870         /*
6871          * GTT cache may not work with big pages, so if those
6872          * are ever enabled GTT cache may need to be disabled.
6873          */
6874         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6875 }
6876
6877 static void g4x_init_clock_gating(struct drm_device *dev)
6878 {
6879         struct drm_i915_private *dev_priv = dev->dev_private;
6880         uint32_t dspclk_gate;
6881
6882         I915_WRITE(RENCLK_GATE_D1, 0);
6883         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6884                    GS_UNIT_CLOCK_GATE_DISABLE |
6885                    CL_UNIT_CLOCK_GATE_DISABLE);
6886         I915_WRITE(RAMCLK_GATE_D, 0);
6887         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6888                 OVRUNIT_CLOCK_GATE_DISABLE |
6889                 OVCUNIT_CLOCK_GATE_DISABLE;
6890         if (IS_GM45(dev))
6891                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6892         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6893
6894         /* WaDisableRenderCachePipelinedFlush */
6895         I915_WRITE(CACHE_MODE_0,
6896                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6897
6898         /* WaDisable_RenderCache_OperationalFlush:g4x */
6899         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6900
6901         g4x_disable_trickle_feed(dev);
6902 }
6903
6904 static void crestline_init_clock_gating(struct drm_device *dev)
6905 {
6906         struct drm_i915_private *dev_priv = dev->dev_private;
6907
6908         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6909         I915_WRITE(RENCLK_GATE_D2, 0);
6910         I915_WRITE(DSPCLK_GATE_D, 0);
6911         I915_WRITE(RAMCLK_GATE_D, 0);
6912         I915_WRITE16(DEUC, 0);
6913         I915_WRITE(MI_ARB_STATE,
6914                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6915
6916         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6917         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6918 }
6919
6920 static void broadwater_init_clock_gating(struct drm_device *dev)
6921 {
6922         struct drm_i915_private *dev_priv = dev->dev_private;
6923
6924         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6925                    I965_RCC_CLOCK_GATE_DISABLE |
6926                    I965_RCPB_CLOCK_GATE_DISABLE |
6927                    I965_ISC_CLOCK_GATE_DISABLE |
6928                    I965_FBC_CLOCK_GATE_DISABLE);
6929         I915_WRITE(RENCLK_GATE_D2, 0);
6930         I915_WRITE(MI_ARB_STATE,
6931                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6932
6933         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6934         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6935 }
6936
6937 static void gen3_init_clock_gating(struct drm_device *dev)
6938 {
6939         struct drm_i915_private *dev_priv = dev->dev_private;
6940         u32 dstate = I915_READ(D_STATE);
6941
6942         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6943                 DSTATE_DOT_CLOCK_GATING;
6944         I915_WRITE(D_STATE, dstate);
6945
6946         if (IS_PINEVIEW(dev))
6947                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6948
6949         /* IIR "flip pending" means done if this bit is set */
6950         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6951
6952         /* interrupts should cause a wake up from C3 */
6953         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6954
6955         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6956         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6957
6958         I915_WRITE(MI_ARB_STATE,
6959                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6960 }
6961
6962 static void i85x_init_clock_gating(struct drm_device *dev)
6963 {
6964         struct drm_i915_private *dev_priv = dev->dev_private;
6965
6966         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6967
6968         /* interrupts should cause a wake up from C3 */
6969         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6970                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6971
6972         I915_WRITE(MEM_MODE,
6973                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6974 }
6975
6976 static void i830_init_clock_gating(struct drm_device *dev)
6977 {
6978         struct drm_i915_private *dev_priv = dev->dev_private;
6979
6980         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6981
6982         I915_WRITE(MEM_MODE,
6983                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6984                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6985 }
6986
6987 void intel_init_clock_gating(struct drm_device *dev)
6988 {
6989         struct drm_i915_private *dev_priv = dev->dev_private;
6990
6991         if (dev_priv->display.init_clock_gating)
6992                 dev_priv->display.init_clock_gating(dev);
6993 }
6994
6995 void intel_suspend_hw(struct drm_device *dev)
6996 {
6997         if (HAS_PCH_LPT(dev))
6998                 lpt_suspend_hw(dev);
6999 }
7000
7001 /* Set up chip specific power management-related functions */
7002 void intel_init_pm(struct drm_device *dev)
7003 {
7004         struct drm_i915_private *dev_priv = dev->dev_private;
7005
7006         intel_fbc_init(dev_priv);
7007
7008         /* For cxsr */
7009         if (IS_PINEVIEW(dev))
7010                 i915_pineview_get_mem_freq(dev);
7011         else if (IS_GEN5(dev))
7012                 i915_ironlake_get_mem_freq(dev);
7013
7014         /* For FIFO watermark updates */
7015         if (INTEL_INFO(dev)->gen >= 9) {
7016                 skl_setup_wm_latency(dev);
7017
7018                 if (IS_BROXTON(dev))
7019                         dev_priv->display.init_clock_gating =
7020                                 bxt_init_clock_gating;
7021                 else if (IS_SKYLAKE(dev))
7022                         dev_priv->display.init_clock_gating =
7023                                 skl_init_clock_gating;
7024                 dev_priv->display.update_wm = skl_update_wm;
7025         } else if (HAS_PCH_SPLIT(dev)) {
7026                 ilk_setup_wm_latency(dev);
7027
7028                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7029                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7030                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7031                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7032                         dev_priv->display.update_wm = ilk_update_wm;
7033                 } else {
7034                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7035                                       "Disable CxSR\n");
7036                 }
7037
7038                 if (IS_GEN5(dev))
7039                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7040                 else if (IS_GEN6(dev))
7041                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7042                 else if (IS_IVYBRIDGE(dev))
7043                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7044                 else if (IS_HASWELL(dev))
7045                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7046                 else if (INTEL_INFO(dev)->gen == 8)
7047                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7048         } else if (IS_CHERRYVIEW(dev)) {
7049                 vlv_setup_wm_latency(dev);
7050
7051                 dev_priv->display.update_wm = vlv_update_wm;
7052                 dev_priv->display.init_clock_gating =
7053                         cherryview_init_clock_gating;
7054         } else if (IS_VALLEYVIEW(dev)) {
7055                 vlv_setup_wm_latency(dev);
7056
7057                 dev_priv->display.update_wm = vlv_update_wm;
7058                 dev_priv->display.init_clock_gating =
7059                         valleyview_init_clock_gating;
7060         } else if (IS_PINEVIEW(dev)) {
7061                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7062                                             dev_priv->is_ddr3,
7063                                             dev_priv->fsb_freq,
7064                                             dev_priv->mem_freq)) {
7065                         DRM_INFO("failed to find known CxSR latency "
7066                                  "(found ddr%s fsb freq %d, mem freq %d), "
7067                                  "disabling CxSR\n",
7068                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7069                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7070                         /* Disable CxSR and never update its watermark again */
7071                         intel_set_memory_cxsr(dev_priv, false);
7072                         dev_priv->display.update_wm = NULL;
7073                 } else
7074                         dev_priv->display.update_wm = pineview_update_wm;
7075                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7076         } else if (IS_G4X(dev)) {
7077                 dev_priv->display.update_wm = g4x_update_wm;
7078                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7079         } else if (IS_GEN4(dev)) {
7080                 dev_priv->display.update_wm = i965_update_wm;
7081                 if (IS_CRESTLINE(dev))
7082                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7083                 else if (IS_BROADWATER(dev))
7084                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7085         } else if (IS_GEN3(dev)) {
7086                 dev_priv->display.update_wm = i9xx_update_wm;
7087                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7088                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7089         } else if (IS_GEN2(dev)) {
7090                 if (INTEL_INFO(dev)->num_pipes == 1) {
7091                         dev_priv->display.update_wm = i845_update_wm;
7092                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7093                 } else {
7094                         dev_priv->display.update_wm = i9xx_update_wm;
7095                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7096                 }
7097
7098                 if (IS_I85X(dev) || IS_I865G(dev))
7099                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7100                 else
7101                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7102         } else {
7103                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7104         }
7105 }
7106
7107 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7108 {
7109         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7110
7111         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7112                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7113                 return -EAGAIN;
7114         }
7115
7116         I915_WRITE(GEN6_PCODE_DATA, *val);
7117         I915_WRITE(GEN6_PCODE_DATA1, 0);
7118         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7119
7120         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7121                      500)) {
7122                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7123                 return -ETIMEDOUT;
7124         }
7125
7126         *val = I915_READ(GEN6_PCODE_DATA);
7127         I915_WRITE(GEN6_PCODE_DATA, 0);
7128
7129         return 0;
7130 }
7131
7132 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7133 {
7134         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7135
7136         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7137                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7138                 return -EAGAIN;
7139         }
7140
7141         I915_WRITE(GEN6_PCODE_DATA, val);
7142         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7143
7144         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7145                      500)) {
7146                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7147                 return -ETIMEDOUT;
7148         }
7149
7150         I915_WRITE(GEN6_PCODE_DATA, 0);
7151
7152         return 0;
7153 }
7154
7155 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7156 {
7157         switch (czclk_freq) {
7158         case 200:
7159                 return 10;
7160         case 267:
7161                 return 12;
7162         case 320:
7163         case 333:
7164                 return 16;
7165         case 400:
7166                 return 20;
7167         default:
7168                 return -1;
7169         }
7170 }
7171
7172 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7173 {
7174         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7175
7176         div = vlv_gpu_freq_div(czclk_freq);
7177         if (div < 0)
7178                 return div;
7179
7180         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7181 }
7182
7183 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7184 {
7185         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7186
7187         mul = vlv_gpu_freq_div(czclk_freq);
7188         if (mul < 0)
7189                 return mul;
7190
7191         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7192 }
7193
7194 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7195 {
7196         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7197
7198         div = vlv_gpu_freq_div(czclk_freq) / 2;
7199         if (div < 0)
7200                 return div;
7201
7202         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7203 }
7204
7205 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7206 {
7207         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7208
7209         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7210         if (mul < 0)
7211                 return mul;
7212
7213         /* CHV needs even values */
7214         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7215 }
7216
7217 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7218 {
7219         if (IS_GEN9(dev_priv->dev))
7220                 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7221         else if (IS_CHERRYVIEW(dev_priv->dev))
7222                 return chv_gpu_freq(dev_priv, val);
7223         else if (IS_VALLEYVIEW(dev_priv->dev))
7224                 return byt_gpu_freq(dev_priv, val);
7225         else
7226                 return val * GT_FREQUENCY_MULTIPLIER;
7227 }
7228
7229 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7230 {
7231         if (IS_GEN9(dev_priv->dev))
7232                 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7233         else if (IS_CHERRYVIEW(dev_priv->dev))
7234                 return chv_freq_opcode(dev_priv, val);
7235         else if (IS_VALLEYVIEW(dev_priv->dev))
7236                 return byt_freq_opcode(dev_priv, val);
7237         else
7238                 return val / GT_FREQUENCY_MULTIPLIER;
7239 }
7240
7241 struct request_boost {
7242         struct work_struct work;
7243         struct drm_i915_gem_request *req;
7244 };
7245
7246 static void __intel_rps_boost_work(struct work_struct *work)
7247 {
7248         struct request_boost *boost = container_of(work, struct request_boost, work);
7249         struct drm_i915_gem_request *req = boost->req;
7250
7251         if (!i915_gem_request_completed(req, true))
7252                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7253                                req->emitted_jiffies);
7254
7255         i915_gem_request_unreference__unlocked(req);
7256         kfree(boost);
7257 }
7258
7259 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7260                                        struct drm_i915_gem_request *req)
7261 {
7262         struct request_boost *boost;
7263
7264         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7265                 return;
7266
7267         if (i915_gem_request_completed(req, true))
7268                 return;
7269
7270         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7271         if (boost == NULL)
7272                 return;
7273
7274         i915_gem_request_reference(req);
7275         boost->req = req;
7276
7277         INIT_WORK(&boost->work, __intel_rps_boost_work);
7278         queue_work(to_i915(dev)->wq, &boost->work);
7279 }
7280
7281 void intel_pm_setup(struct drm_device *dev)
7282 {
7283         struct drm_i915_private *dev_priv = dev->dev_private;
7284
7285         mutex_init(&dev_priv->rps.hw_lock);
7286         spin_lock_init(&dev_priv->rps.client_lock);
7287
7288         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7289                           intel_gen6_powersave_work);
7290         INIT_LIST_HEAD(&dev_priv->rps.clients);
7291         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7292         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7293
7294         dev_priv->pm.suspended = false;
7295 }