drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void i8xx_disable_fbc(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         u32 fbc_ctl;
  73
  74         /* Disable compression */
  75         fbc_ctl = I915_READ(FBC_CONTROL);
  76         if ((fbc_ctl & FBC_CTL_EN) == 0)
  77                 return;
  78
  79         fbc_ctl &= ~FBC_CTL_EN;
  80         I915_WRITE(FBC_CONTROL, fbc_ctl);
  81
  82         /* Wait for compressing bit to clear */
  83         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  84                 DRM_DEBUG_KMS("FBC idle timed out\n");
  85                 return;
  86         }
  87
  88         DRM_DEBUG_KMS("disabled FBC\n");
  89 }
  90
  91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct drm_i915_private *dev_priv = dev->dev_private;
  95         struct drm_framebuffer *fb = crtc->fb;
  96         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  97         struct drm_i915_gem_object *obj = intel_fb->obj;
  98         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  99         int cfb_pitch;
 100         int plane, i;
 101         u32 fbc_ctl;
 102
 103         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 104         if (fb->pitches[0] < cfb_pitch)
 105                 cfb_pitch = fb->pitches[0];
 106
 107         /* FBC_CTL wants 32B or 64B units */
 108         if (IS_GEN2(dev))
 109                 cfb_pitch = (cfb_pitch / 32) - 1;
 110         else
 111                 cfb_pitch = (cfb_pitch / 64) - 1;
 112         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 113
 114         /* Clear old tags */
 115         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 116                 I915_WRITE(FBC_TAG + (i * 4), 0);
 117
 118         if (IS_GEN4(dev)) {
 119                 u32 fbc_ctl2;
 120
 121                 /* Set it up... */
 122                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 123                 fbc_ctl2 |= plane;
 124                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 125                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 126         }
 127
 128         /* enable it... */
 129         fbc_ctl = I915_READ(FBC_CONTROL);
 130         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 131         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 132         if (IS_I945GM(dev))
 133                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 134         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 135         fbc_ctl |= obj->fence_reg;
 136         I915_WRITE(FBC_CONTROL, fbc_ctl);
 137
 138         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 139                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 140 }
 141
 142 static bool i8xx_fbc_enabled(struct drm_device *dev)
 143 {
 144         struct drm_i915_private *dev_priv = dev->dev_private;
 145
 146         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 147 }
 148
 149 static void g4x_enable_fbc(struct drm_crtc *crtc)
 150 {
 151         struct drm_device *dev = crtc->dev;
 152         struct drm_i915_private *dev_priv = dev->dev_private;
 153         struct drm_framebuffer *fb = crtc->fb;
 154         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 155         struct drm_i915_gem_object *obj = intel_fb->obj;
 156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 157         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 158         u32 dpfc_ctl;
 159
 160         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 161         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 162         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 163
 164         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 165
 166         /* enable it... */
 167         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 168
 169         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 170 }
 171
 172 static void g4x_disable_fbc(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175         u32 dpfc_ctl;
 176
 177         /* Disable compression */
 178         dpfc_ctl = I915_READ(DPFC_CONTROL);
 179         if (dpfc_ctl & DPFC_CTL_EN) {
 180                 dpfc_ctl &= ~DPFC_CTL_EN;
 181                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 182
 183                 DRM_DEBUG_KMS("disabled FBC\n");
 184         }
 185 }
 186
 187 static bool g4x_fbc_enabled(struct drm_device *dev)
 188 {
 189         struct drm_i915_private *dev_priv = dev->dev_private;
 190
 191         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 192 }
 193
 194 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 195 {
 196         struct drm_i915_private *dev_priv = dev->dev_private;
 197         u32 blt_ecoskpd;
 198
 199         /* Make sure blitter notifies FBC of writes */
 200
 201         /* Blitter is part of Media powerwell on VLV. No impact of
 202          * his param in other platforms for now */
 203         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 204
 205         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 206         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 207                 GEN6_BLITTER_LOCK_SHIFT;
 208         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 209         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 210         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 211         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 212                          GEN6_BLITTER_LOCK_SHIFT);
 213         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 214         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 215
 216         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 217 }
 218
 219 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 220 {
 221         struct drm_device *dev = crtc->dev;
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         struct drm_framebuffer *fb = crtc->fb;
 224         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 225         struct drm_i915_gem_object *obj = intel_fb->obj;
 226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 227         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 228         u32 dpfc_ctl;
 229
 230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 231         dpfc_ctl &= DPFC_RESERVED;
 232         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 233         /* Set persistent mode for front-buffer rendering, ala X. */
 234         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 235         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236         if (IS_GEN5(dev))
 237                 dpfc_ctl |= obj->fence_reg;
 238         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 239
 240         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 241         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 242         /* enable it... */
 243         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 244
 245         if (IS_GEN6(dev)) {
 246                 I915_WRITE(SNB_DPFC_CTL_SA,
 247                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 248                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 249                 sandybridge_blit_fbc_update(dev);
 250         }
 251
 252         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 253 }
 254
 255 static void ironlake_disable_fbc(struct drm_device *dev)
 256 {
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         u32 dpfc_ctl;
 259
 260         /* Disable compression */
 261         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 262         if (dpfc_ctl & DPFC_CTL_EN) {
 263                 dpfc_ctl &= ~DPFC_CTL_EN;
 264                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 265
 266                 DRM_DEBUG_KMS("disabled FBC\n");
 267         }
 268 }
 269
 270 static bool ironlake_fbc_enabled(struct drm_device *dev)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273
 274         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 275 }
 276
 277 static void gen7_enable_fbc(struct drm_crtc *crtc)
 278 {
 279         struct drm_device *dev = crtc->dev;
 280         struct drm_i915_private *dev_priv = dev->dev_private;
 281         struct drm_framebuffer *fb = crtc->fb;
 282         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 283         struct drm_i915_gem_object *obj = intel_fb->obj;
 284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 285
 286         I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
 287
 288         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 289                    IVB_DPFC_CTL_FENCE_EN |
 290                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 291
 292         if (IS_IVYBRIDGE(dev)) {
 293                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 294                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 295         } else {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 297                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 298                            HSW_BYPASS_FBC_QUEUE);
 299         }
 300
 301         I915_WRITE(SNB_DPFC_CTL_SA,
 302                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 303         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 304
 305         sandybridge_blit_fbc_update(dev);
 306
 307         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 308 }
 309
 310 bool intel_fbc_enabled(struct drm_device *dev)
 311 {
 312         struct drm_i915_private *dev_priv = dev->dev_private;
 313
 314         if (!dev_priv->display.fbc_enabled)
 315                 return false;
 316
 317         return dev_priv->display.fbc_enabled(dev);
 318 }
 319
 320 static void intel_fbc_work_fn(struct work_struct *__work)
 321 {
 322         struct intel_fbc_work *work =
 323                 container_of(to_delayed_work(__work),
 324                              struct intel_fbc_work, work);
 325         struct drm_device *dev = work->crtc->dev;
 326         struct drm_i915_private *dev_priv = dev->dev_private;
 327
 328         mutex_lock(&dev->struct_mutex);
 329         if (work == dev_priv->fbc.fbc_work) {
 330                 /* Double check that we haven't switched fb without cancelling
 331                  * the prior work.
 332                  */
 333                 if (work->crtc->fb == work->fb) {
 334                         dev_priv->display.enable_fbc(work->crtc);
 335
 336                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 337                         dev_priv->fbc.fb_id = work->crtc->fb->base.id;
 338                         dev_priv->fbc.y = work->crtc->y;
 339                 }
 340
 341                 dev_priv->fbc.fbc_work = NULL;
 342         }
 343         mutex_unlock(&dev->struct_mutex);
 344
 345         kfree(work);
 346 }
 347
 348 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 349 {
 350         if (dev_priv->fbc.fbc_work == NULL)
 351                 return;
 352
 353         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 354
 355         /* Synchronisation is provided by struct_mutex and checking of
 356          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 357          * entirely asynchronously.
 358          */
 359         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 360                 /* tasklet was killed before being run, clean up */
 361                 kfree(dev_priv->fbc.fbc_work);
 362
 363         /* Mark the work as no longer wanted so that if it does
 364          * wake-up (because the work was already running and waiting
 365          * for our mutex), it will discover that is no longer
 366          * necessary to run.
 367          */
 368         dev_priv->fbc.fbc_work = NULL;
 369 }
 370
 371 static void intel_enable_fbc(struct drm_crtc *crtc)
 372 {
 373         struct intel_fbc_work *work;
 374         struct drm_device *dev = crtc->dev;
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376
 377         if (!dev_priv->display.enable_fbc)
 378                 return;
 379
 380         intel_cancel_fbc_work(dev_priv);
 381
 382         work = kzalloc(sizeof(*work), GFP_KERNEL);
 383         if (work == NULL) {
 384                 DRM_ERROR("Failed to allocate FBC work structure\n");
 385                 dev_priv->display.enable_fbc(crtc);
 386                 return;
 387         }
 388
 389         work->crtc = crtc;
 390         work->fb = crtc->fb;
 391         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 392
 393         dev_priv->fbc.fbc_work = work;
 394
 395         /* Delay the actual enabling to let pageflipping cease and the
 396          * display to settle before starting the compression. Note that
 397          * this delay also serves a second purpose: it allows for a
 398          * vblank to pass after disabling the FBC before we attempt
 399          * to modify the control registers.
 400          *
 401          * A more complicated solution would involve tracking vblanks
 402          * following the termination of the page-flipping sequence
 403          * and indeed performing the enable as a co-routine and not
 404          * waiting synchronously upon the vblank.
 405          *
 406          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 407          */
 408         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 409 }
 410
 411 void intel_disable_fbc(struct drm_device *dev)
 412 {
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414
 415         intel_cancel_fbc_work(dev_priv);
 416
 417         if (!dev_priv->display.disable_fbc)
 418                 return;
 419
 420         dev_priv->display.disable_fbc(dev);
 421         dev_priv->fbc.plane = -1;
 422 }
 423
 424 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 425                               enum no_fbc_reason reason)
 426 {
 427         if (dev_priv->fbc.no_fbc_reason == reason)
 428                 return false;
 429
 430         dev_priv->fbc.no_fbc_reason = reason;
 431         return true;
 432 }
 433
 434 /**
 435  * intel_update_fbc - enable/disable FBC as needed
 436  * @dev: the drm_device
 437  *
 438  * Set up the framebuffer compression hardware at mode set time.  We
 439  * enable it if possible:
 440  *   - plane A only (on pre-965)
 441  *   - no pixel mulitply/line duplication
 442  *   - no alpha buffer discard
 443  *   - no dual wide
 444  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 445  *
 446  * We can't assume that any compression will take place (worst case),
 447  * so the compressed buffer has to be the same size as the uncompressed
 448  * one.  It also must reside (along with the line length buffer) in
 449  * stolen memory.
 450  *
 451  * We need to enable/disable FBC on a global basis.
 452  */
 453 void intel_update_fbc(struct drm_device *dev)
 454 {
 455         struct drm_i915_private *dev_priv = dev->dev_private;
 456         struct drm_crtc *crtc = NULL, *tmp_crtc;
 457         struct intel_crtc *intel_crtc;
 458         struct drm_framebuffer *fb;
 459         struct intel_framebuffer *intel_fb;
 460         struct drm_i915_gem_object *obj;
 461         const struct drm_display_mode *adjusted_mode;
 462         unsigned int max_width, max_height;
 463
 464         if (!HAS_FBC(dev)) {
 465                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 466                 return;
 467         }
 468
 469         if (!i915_powersave) {
 470                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 471                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 472                 return;
 473         }
 474
 475         /*
 476          * If FBC is already on, we just have to verify that we can
 477          * keep it that way...
 478          * Need to disable if:
 479          *   - more than one pipe is active
 480          *   - changing FBC params (stride, fence, mode)
 481          *   - new fb is too large to fit in compressed buffer
 482          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 483          */
 484         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 485                 if (intel_crtc_active(tmp_crtc) &&
 486                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 487                         if (crtc) {
 488                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 489                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 490                                 goto out_disable;
 491                         }
 492                         crtc = tmp_crtc;
 493                 }
 494         }
 495
 496         if (!crtc || crtc->fb == NULL) {
 497                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 498                         DRM_DEBUG_KMS("no output, disabling\n");
 499                 goto out_disable;
 500         }
 501
 502         intel_crtc = to_intel_crtc(crtc);
 503         fb = crtc->fb;
 504         intel_fb = to_intel_framebuffer(fb);
 505         obj = intel_fb->obj;
 506         adjusted_mode = &intel_crtc->config.adjusted_mode;
 507
 508         if (i915_enable_fbc < 0 &&
 509             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 510                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 511                         DRM_DEBUG_KMS("disabled per chip default\n");
 512                 goto out_disable;
 513         }
 514         if (!i915_enable_fbc) {
 515                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 516                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 517                 goto out_disable;
 518         }
 519         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 520             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 521                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 522                         DRM_DEBUG_KMS("mode incompatible with compression, "
 523                                       "disabling\n");
 524                 goto out_disable;
 525         }
 526
 527         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 528                 max_width = 4096;
 529                 max_height = 2048;
 530         } else {
 531                 max_width = 2048;
 532                 max_height = 1536;
 533         }
 534         if (intel_crtc->config.pipe_src_w > max_width ||
 535             intel_crtc->config.pipe_src_h > max_height) {
 536                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 537                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 538                 goto out_disable;
 539         }
 540         if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
 541             intel_crtc->plane != PLANE_A) {
 542                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 543                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 544                 goto out_disable;
 545         }
 546
 547         /* The use of a CPU fence is mandatory in order to detect writes
 548          * by the CPU to the scanout and trigger updates to the FBC.
 549          */
 550         if (obj->tiling_mode != I915_TILING_X ||
 551             obj->fence_reg == I915_FENCE_REG_NONE) {
 552                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 553                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 554                 goto out_disable;
 555         }
 556
 557         /* If the kernel debugger is active, always disable compression */
 558         if (in_dbg_master())
 559                 goto out_disable;
 560
 561         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 562                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 563                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 564                 goto out_disable;
 565         }
 566
 567         /* If the scanout has not changed, don't modify the FBC settings.
 568          * Note that we make the fundamental assumption that the fb->obj
 569          * cannot be unpinned (and have its GTT offset and fence revoked)
 570          * without first being decoupled from the scanout and FBC disabled.
 571          */
 572         if (dev_priv->fbc.plane == intel_crtc->plane &&
 573             dev_priv->fbc.fb_id == fb->base.id &&
 574             dev_priv->fbc.y == crtc->y)
 575                 return;
 576
 577         if (intel_fbc_enabled(dev)) {
 578                 /* We update FBC along two paths, after changing fb/crtc
 579                  * configuration (modeswitching) and after page-flipping
 580                  * finishes. For the latter, we know that not only did
 581                  * we disable the FBC at the start of the page-flip
 582                  * sequence, but also more than one vblank has passed.
 583                  *
 584                  * For the former case of modeswitching, it is possible
 585                  * to switch between two FBC valid configurations
 586                  * instantaneously so we do need to disable the FBC
 587                  * before we can modify its control registers. We also
 588                  * have to wait for the next vblank for that to take
 589                  * effect. However, since we delay enabling FBC we can
 590                  * assume that a vblank has passed since disabling and
 591                  * that we can safely alter the registers in the deferred
 592                  * callback.
 593                  *
 594                  * In the scenario that we go from a valid to invalid
 595                  * and then back to valid FBC configuration we have
 596                  * no strict enforcement that a vblank occurred since
 597                  * disabling the FBC. However, along all current pipe
 598                  * disabling paths we do need to wait for a vblank at
 599                  * some point. And we wait before enabling FBC anyway.
 600                  */
 601                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 602                 intel_disable_fbc(dev);
 603         }
 604
 605         intel_enable_fbc(crtc);
 606         dev_priv->fbc.no_fbc_reason = FBC_OK;
 607         return;
 608
 609 out_disable:
 610         /* Multiple disables should be harmless */
 611         if (intel_fbc_enabled(dev)) {
 612                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 613                 intel_disable_fbc(dev);
 614         }
 615         i915_gem_stolen_cleanup_compression(dev);
 616 }
 617
 618 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 619 {
 620         drm_i915_private_t *dev_priv = dev->dev_private;
 621         u32 tmp;
 622
 623         tmp = I915_READ(CLKCFG);
 624
 625         switch (tmp & CLKCFG_FSB_MASK) {
 626         case CLKCFG_FSB_533:
 627                 dev_priv->fsb_freq = 533; /* 133*4 */
 628                 break;
 629         case CLKCFG_FSB_800:
 630                 dev_priv->fsb_freq = 800; /* 200*4 */
 631                 break;
 632         case CLKCFG_FSB_667:
 633                 dev_priv->fsb_freq =  667; /* 167*4 */
 634                 break;
 635         case CLKCFG_FSB_400:
 636                 dev_priv->fsb_freq = 400; /* 100*4 */
 637                 break;
 638         }
 639
 640         switch (tmp & CLKCFG_MEM_MASK) {
 641         case CLKCFG_MEM_533:
 642                 dev_priv->mem_freq = 533;
 643                 break;
 644         case CLKCFG_MEM_667:
 645                 dev_priv->mem_freq = 667;
 646                 break;
 647         case CLKCFG_MEM_800:
 648                 dev_priv->mem_freq = 800;
 649                 break;
 650         }
 651
 652         /* detect pineview DDR3 setting */
 653         tmp = I915_READ(CSHRDDR3CTL);
 654         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 655 }
 656
 657 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 658 {
 659         drm_i915_private_t *dev_priv = dev->dev_private;
 660         u16 ddrpll, csipll;
 661
 662         ddrpll = I915_READ16(DDRMPLL1);
 663         csipll = I915_READ16(CSIPLL0);
 664
 665         switch (ddrpll & 0xff) {
 666         case 0xc:
 667                 dev_priv->mem_freq = 800;
 668                 break;
 669         case 0x10:
 670                 dev_priv->mem_freq = 1066;
 671                 break;
 672         case 0x14:
 673                 dev_priv->mem_freq = 1333;
 674                 break;
 675         case 0x18:
 676                 dev_priv->mem_freq = 1600;
 677                 break;
 678         default:
 679                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 680                                  ddrpll & 0xff);
 681                 dev_priv->mem_freq = 0;
 682                 break;
 683         }
 684
 685         dev_priv->ips.r_t = dev_priv->mem_freq;
 686
 687         switch (csipll & 0x3ff) {
 688         case 0x00c:
 689                 dev_priv->fsb_freq = 3200;
 690                 break;
 691         case 0x00e:
 692                 dev_priv->fsb_freq = 3733;
 693                 break;
 694         case 0x010:
 695                 dev_priv->fsb_freq = 4266;
 696                 break;
 697         case 0x012:
 698                 dev_priv->fsb_freq = 4800;
 699                 break;
 700         case 0x014:
 701                 dev_priv->fsb_freq = 5333;
 702                 break;
 703         case 0x016:
 704                 dev_priv->fsb_freq = 5866;
 705                 break;
 706         case 0x018:
 707                 dev_priv->fsb_freq = 6400;
 708                 break;
 709         default:
 710                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 711                                  csipll & 0x3ff);
 712                 dev_priv->fsb_freq = 0;
 713                 break;
 714         }
 715
 716         if (dev_priv->fsb_freq == 3200) {
 717                 dev_priv->ips.c_m = 0;
 718         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 719                 dev_priv->ips.c_m = 1;
 720         } else {
 721                 dev_priv->ips.c_m = 2;
 722         }
 723 }
 724
 725 static const struct cxsr_latency cxsr_latency_table[] = {
 726         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 727         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 728         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 729         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 730         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 731
 732         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 733         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 734         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 735         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 736         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 737
 738         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 739         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 740         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 741         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 742         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 743
 744         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 745         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 746         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 747         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 748         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 749
 750         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 751         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 752         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 753         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 754         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 755
 756         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 757         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 758         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 759         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 760         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 761 };
 762
 763 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 764                                                          int is_ddr3,
 765                                                          int fsb,
 766                                                          int mem)
 767 {
 768         const struct cxsr_latency *latency;
 769         int i;
 770
 771         if (fsb == 0 || mem == 0)
 772                 return NULL;
 773
 774         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 775                 latency = &cxsr_latency_table[i];
 776                 if (is_desktop == latency->is_desktop &&
 777                     is_ddr3 == latency->is_ddr3 &&
 778                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 779                         return latency;
 780         }
 781
 782         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 783
 784         return NULL;
 785 }
 786
 787 static void pineview_disable_cxsr(struct drm_device *dev)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790
 791         /* deactivate cxsr */
 792         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 793 }
 794
 795 /*
 796  * Latency for FIFO fetches is dependent on several factors:
 797  *   - memory configuration (speed, channels)
 798  *   - chipset
 799  *   - current MCH state
 800  * It can be fairly high in some situations, so here we assume a fairly
 801  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 802  * set this value too high, the FIFO will fetch frequently to stay full)
 803  * and power consumption (set it too low to save power and we might see
 804  * FIFO underruns and display "flicker").
 805  *
 806  * A value of 5us seems to be a good balance; safe for very low end
 807  * platforms but not overly aggressive on lower latency configs.
 808  */
 809 static const int latency_ns = 5000;
 810
 811 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 812 {
 813         struct drm_i915_private *dev_priv = dev->dev_private;
 814         uint32_t dsparb = I915_READ(DSPARB);
 815         int size;
 816
 817         size = dsparb & 0x7f;
 818         if (plane)
 819                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 820
 821         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 822                       plane ? "B" : "A", size);
 823
 824         return size;
 825 }
 826
 827 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 828 {
 829         struct drm_i915_private *dev_priv = dev->dev_private;
 830         uint32_t dsparb = I915_READ(DSPARB);
 831         int size;
 832
 833         size = dsparb & 0x1ff;
 834         if (plane)
 835                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 836         size >>= 1; /* Convert to cachelines */
 837
 838         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 839                       plane ? "B" : "A", size);
 840
 841         return size;
 842 }
 843
 844 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         uint32_t dsparb = I915_READ(DSPARB);
 848         int size;
 849
 850         size = dsparb & 0x7f;
 851         size >>= 2; /* Convert to cachelines */
 852
 853         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 854                       plane ? "B" : "A",
 855                       size);
 856
 857         return size;
 858 }
 859
 860 /* Pineview has different values for various configs */
 861 static const struct intel_watermark_params pineview_display_wm = {
 862         PINEVIEW_DISPLAY_FIFO,
 863         PINEVIEW_MAX_WM,
 864         PINEVIEW_DFT_WM,
 865         PINEVIEW_GUARD_WM,
 866         PINEVIEW_FIFO_LINE_SIZE
 867 };
 868 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 869         PINEVIEW_DISPLAY_FIFO,
 870         PINEVIEW_MAX_WM,
 871         PINEVIEW_DFT_HPLLOFF_WM,
 872         PINEVIEW_GUARD_WM,
 873         PINEVIEW_FIFO_LINE_SIZE
 874 };
 875 static const struct intel_watermark_params pineview_cursor_wm = {
 876         PINEVIEW_CURSOR_FIFO,
 877         PINEVIEW_CURSOR_MAX_WM,
 878         PINEVIEW_CURSOR_DFT_WM,
 879         PINEVIEW_CURSOR_GUARD_WM,
 880         PINEVIEW_FIFO_LINE_SIZE,
 881 };
 882 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 883         PINEVIEW_CURSOR_FIFO,
 884         PINEVIEW_CURSOR_MAX_WM,
 885         PINEVIEW_CURSOR_DFT_WM,
 886         PINEVIEW_CURSOR_GUARD_WM,
 887         PINEVIEW_FIFO_LINE_SIZE
 888 };
 889 static const struct intel_watermark_params g4x_wm_info = {
 890         G4X_FIFO_SIZE,
 891         G4X_MAX_WM,
 892         G4X_MAX_WM,
 893         2,
 894         G4X_FIFO_LINE_SIZE,
 895 };
 896 static const struct intel_watermark_params g4x_cursor_wm_info = {
 897         I965_CURSOR_FIFO,
 898         I965_CURSOR_MAX_WM,
 899         I965_CURSOR_DFT_WM,
 900         2,
 901         G4X_FIFO_LINE_SIZE,
 902 };
 903 static const struct intel_watermark_params valleyview_wm_info = {
 904         VALLEYVIEW_FIFO_SIZE,
 905         VALLEYVIEW_MAX_WM,
 906         VALLEYVIEW_MAX_WM,
 907         2,
 908         G4X_FIFO_LINE_SIZE,
 909 };
 910 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 911         I965_CURSOR_FIFO,
 912         VALLEYVIEW_CURSOR_MAX_WM,
 913         I965_CURSOR_DFT_WM,
 914         2,
 915         G4X_FIFO_LINE_SIZE,
 916 };
 917 static const struct intel_watermark_params i965_cursor_wm_info = {
 918         I965_CURSOR_FIFO,
 919         I965_CURSOR_MAX_WM,
 920         I965_CURSOR_DFT_WM,
 921         2,
 922         I915_FIFO_LINE_SIZE,
 923 };
 924 static const struct intel_watermark_params i945_wm_info = {
 925         I945_FIFO_SIZE,
 926         I915_MAX_WM,
 927         1,
 928         2,
 929         I915_FIFO_LINE_SIZE
 930 };
 931 static const struct intel_watermark_params i915_wm_info = {
 932         I915_FIFO_SIZE,
 933         I915_MAX_WM,
 934         1,
 935         2,
 936         I915_FIFO_LINE_SIZE
 937 };
 938 static const struct intel_watermark_params i830_wm_info = {
 939         I855GM_FIFO_SIZE,
 940         I915_MAX_WM,
 941         1,
 942         2,
 943         I830_FIFO_LINE_SIZE
 944 };
 945 static const struct intel_watermark_params i845_wm_info = {
 946         I830_FIFO_SIZE,
 947         I915_MAX_WM,
 948         1,
 949         2,
 950         I830_FIFO_LINE_SIZE
 951 };
 952
 953 /**
 954  * intel_calculate_wm - calculate watermark level
 955  * @clock_in_khz: pixel clock
 956  * @wm: chip FIFO params
 957  * @pixel_size: display pixel size
 958  * @latency_ns: memory latency for the platform
 959  *
 960  * Calculate the watermark level (the level at which the display plane will
 961  * start fetching from memory again).  Each chip has a different display
 962  * FIFO size and allocation, so the caller needs to figure that out and pass
 963  * in the correct intel_watermark_params structure.
 964  *
 965  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 966  * on the pixel size.  When it reaches the watermark level, it'll start
 967  * fetching FIFO line sized based chunks from memory until the FIFO fills
 968  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 969  * will occur, and a display engine hang could result.
 970  */
 971 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 972                                         const struct intel_watermark_params *wm,
 973                                         int fifo_size,
 974                                         int pixel_size,
 975                                         unsigned long latency_ns)
 976 {
 977         long entries_required, wm_size;
 978
 979         /*
 980          * Note: we need to make sure we don't overflow for various clock &
 981          * latency values.
 982          * clocks go from a few thousand to several hundred thousand.
 983          * latency is usually a few thousand
 984          */
 985         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 986                 1000;
 987         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 988
 989         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 990
 991         wm_size = fifo_size - (entries_required + wm->guard_size);
 992
 993         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 994
 995         /* Don't promote wm_size to unsigned... */
 996         if (wm_size > (long)wm->max_wm)
 997                 wm_size = wm->max_wm;
 998         if (wm_size <= 0)
 999                 wm_size = wm->default_wm;
1000         return wm_size;
1001 }
1002
1003 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1004 {
1005         struct drm_crtc *crtc, *enabled = NULL;
1006
1007         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1008                 if (intel_crtc_active(crtc)) {
1009                         if (enabled)
1010                                 return NULL;
1011                         enabled = crtc;
1012                 }
1013         }
1014
1015         return enabled;
1016 }
1017
1018 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1019 {
1020         struct drm_device *dev = unused_crtc->dev;
1021         struct drm_i915_private *dev_priv = dev->dev_private;
1022         struct drm_crtc *crtc;
1023         const struct cxsr_latency *latency;
1024         u32 reg;
1025         unsigned long wm;
1026
1027         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1028                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1029         if (!latency) {
1030                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1031                 pineview_disable_cxsr(dev);
1032                 return;
1033         }
1034
1035         crtc = single_enabled_crtc(dev);
1036         if (crtc) {
1037                 const struct drm_display_mode *adjusted_mode;
1038                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1039                 int clock;
1040
1041                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1042                 clock = adjusted_mode->crtc_clock;
1043
1044                 /* Display SR */
1045                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1046                                         pineview_display_wm.fifo_size,
1047                                         pixel_size, latency->display_sr);
1048                 reg = I915_READ(DSPFW1);
1049                 reg &= ~DSPFW_SR_MASK;
1050                 reg |= wm << DSPFW_SR_SHIFT;
1051                 I915_WRITE(DSPFW1, reg);
1052                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1053
1054                 /* cursor SR */
1055                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1056                                         pineview_display_wm.fifo_size,
1057                                         pixel_size, latency->cursor_sr);
1058                 reg = I915_READ(DSPFW3);
1059                 reg &= ~DSPFW_CURSOR_SR_MASK;
1060                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1061                 I915_WRITE(DSPFW3, reg);
1062
1063                 /* Display HPLL off SR */
1064                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1065                                         pineview_display_hplloff_wm.fifo_size,
1066                                         pixel_size, latency->display_hpll_disable);
1067                 reg = I915_READ(DSPFW3);
1068                 reg &= ~DSPFW_HPLL_SR_MASK;
1069                 reg |= wm & DSPFW_HPLL_SR_MASK;
1070                 I915_WRITE(DSPFW3, reg);
1071
1072                 /* cursor HPLL off SR */
1073                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1074                                         pineview_display_hplloff_wm.fifo_size,
1075                                         pixel_size, latency->cursor_hpll_disable);
1076                 reg = I915_READ(DSPFW3);
1077                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1078                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1079                 I915_WRITE(DSPFW3, reg);
1080                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1081
1082                 /* activate cxsr */
1083                 I915_WRITE(DSPFW3,
1084                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1085                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1086         } else {
1087                 pineview_disable_cxsr(dev);
1088                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1089         }
1090 }
1091
1092 static bool g4x_compute_wm0(struct drm_device *dev,
1093                             int plane,
1094                             const struct intel_watermark_params *display,
1095                             int display_latency_ns,
1096                             const struct intel_watermark_params *cursor,
1097                             int cursor_latency_ns,
1098                             int *plane_wm,
1099                             int *cursor_wm)
1100 {
1101         struct drm_crtc *crtc;
1102         const struct drm_display_mode *adjusted_mode;
1103         int htotal, hdisplay, clock, pixel_size;
1104         int line_time_us, line_count;
1105         int entries, tlb_miss;
1106
1107         crtc = intel_get_crtc_for_plane(dev, plane);
1108         if (!intel_crtc_active(crtc)) {
1109                 *cursor_wm = cursor->guard_size;
1110                 *plane_wm = display->guard_size;
1111                 return false;
1112         }
1113
1114         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1115         clock = adjusted_mode->crtc_clock;
1116         htotal = adjusted_mode->htotal;
1117         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1118         pixel_size = crtc->fb->bits_per_pixel / 8;
1119
1120         /* Use the small buffer method to calculate plane watermark */
1121         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1122         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1123         if (tlb_miss > 0)
1124                 entries += tlb_miss;
1125         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1126         *plane_wm = entries + display->guard_size;
1127         if (*plane_wm > (int)display->max_wm)
1128                 *plane_wm = display->max_wm;
1129
1130         /* Use the large buffer method to calculate cursor watermark */
1131         line_time_us = ((htotal * 1000) / clock);
1132         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1133         entries = line_count * 64 * pixel_size;
1134         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1135         if (tlb_miss > 0)
1136                 entries += tlb_miss;
1137         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1138         *cursor_wm = entries + cursor->guard_size;
1139         if (*cursor_wm > (int)cursor->max_wm)
1140                 *cursor_wm = (int)cursor->max_wm;
1141
1142         return true;
1143 }
1144
1145 /*
1146  * Check the wm result.
1147  *
1148  * If any calculated watermark values is larger than the maximum value that
1149  * can be programmed into the associated watermark register, that watermark
1150  * must be disabled.
1151  */
1152 static bool g4x_check_srwm(struct drm_device *dev,
1153                            int display_wm, int cursor_wm,
1154                            const struct intel_watermark_params *display,
1155                            const struct intel_watermark_params *cursor)
1156 {
1157         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1158                       display_wm, cursor_wm);
1159
1160         if (display_wm > display->max_wm) {
1161                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1162                               display_wm, display->max_wm);
1163                 return false;
1164         }
1165
1166         if (cursor_wm > cursor->max_wm) {
1167                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1168                               cursor_wm, cursor->max_wm);
1169                 return false;
1170         }
1171
1172         if (!(display_wm || cursor_wm)) {
1173                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1174                 return false;
1175         }
1176
1177         return true;
1178 }
1179
1180 static bool g4x_compute_srwm(struct drm_device *dev,
1181                              int plane,
1182                              int latency_ns,
1183                              const struct intel_watermark_params *display,
1184                              const struct intel_watermark_params *cursor,
1185                              int *display_wm, int *cursor_wm)
1186 {
1187         struct drm_crtc *crtc;
1188         const struct drm_display_mode *adjusted_mode;
1189         int hdisplay, htotal, pixel_size, clock;
1190         unsigned long line_time_us;
1191         int line_count, line_size;
1192         int small, large;
1193         int entries;
1194
1195         if (!latency_ns) {
1196                 *display_wm = *cursor_wm = 0;
1197                 return false;
1198         }
1199
1200         crtc = intel_get_crtc_for_plane(dev, plane);
1201         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1202         clock = adjusted_mode->crtc_clock;
1203         htotal = adjusted_mode->htotal;
1204         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1205         pixel_size = crtc->fb->bits_per_pixel / 8;
1206
1207         line_time_us = (htotal * 1000) / clock;
1208         line_count = (latency_ns / line_time_us + 1000) / 1000;
1209         line_size = hdisplay * pixel_size;
1210
1211         /* Use the minimum of the small and large buffer method for primary */
1212         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1213         large = line_count * line_size;
1214
1215         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1216         *display_wm = entries + display->guard_size;
1217
1218         /* calculate the self-refresh watermark for display cursor */
1219         entries = line_count * pixel_size * 64;
1220         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1221         *cursor_wm = entries + cursor->guard_size;
1222
1223         return g4x_check_srwm(dev,
1224                               *display_wm, *cursor_wm,
1225                               display, cursor);
1226 }
1227
1228 static bool vlv_compute_drain_latency(struct drm_device *dev,
1229                                      int plane,
1230                                      int *plane_prec_mult,
1231                                      int *plane_dl,
1232                                      int *cursor_prec_mult,
1233                                      int *cursor_dl)
1234 {
1235         struct drm_crtc *crtc;
1236         int clock, pixel_size;
1237         int entries;
1238
1239         crtc = intel_get_crtc_for_plane(dev, plane);
1240         if (!intel_crtc_active(crtc))
1241                 return false;
1242
1243         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1244         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1245
1246         entries = (clock / 1000) * pixel_size;
1247         *plane_prec_mult = (entries > 256) ?
1248                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1249         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1250                                                      pixel_size);
1251
1252         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1253         *cursor_prec_mult = (entries > 256) ?
1254                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1256
1257         return true;
1258 }
1259
1260 /*
1261  * Update drain latency registers of memory arbiter
1262  *
1263  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1264  * to be programmed. Each plane has a drain latency multiplier and a drain
1265  * latency value.
1266  */
1267
1268 static void vlv_update_drain_latency(struct drm_device *dev)
1269 {
1270         struct drm_i915_private *dev_priv = dev->dev_private;
1271         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1272         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1273         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1274                                                         either 16 or 32 */
1275
1276         /* For plane A, Cursor A */
1277         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1278                                       &cursor_prec_mult, &cursora_dl)) {
1279                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1280                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1281                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1282                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1283
1284                 I915_WRITE(VLV_DDL1, cursora_prec |
1285                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1286                                 planea_prec | planea_dl);
1287         }
1288
1289         /* For plane B, Cursor B */
1290         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1291                                       &cursor_prec_mult, &cursorb_dl)) {
1292                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1293                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1294                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1295                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1296
1297                 I915_WRITE(VLV_DDL2, cursorb_prec |
1298                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1299                                 planeb_prec | planeb_dl);
1300         }
1301 }
1302
1303 #define single_plane_enabled(mask) is_power_of_2(mask)
1304
1305 static void valleyview_update_wm(struct drm_crtc *crtc)
1306 {
1307         struct drm_device *dev = crtc->dev;
1308         static const int sr_latency_ns = 12000;
1309         struct drm_i915_private *dev_priv = dev->dev_private;
1310         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1311         int plane_sr, cursor_sr;
1312         int ignore_plane_sr, ignore_cursor_sr;
1313         unsigned int enabled = 0;
1314
1315         vlv_update_drain_latency(dev);
1316
1317         if (g4x_compute_wm0(dev, PIPE_A,
1318                             &valleyview_wm_info, latency_ns,
1319                             &valleyview_cursor_wm_info, latency_ns,
1320                             &planea_wm, &cursora_wm))
1321                 enabled |= 1 << PIPE_A;
1322
1323         if (g4x_compute_wm0(dev, PIPE_B,
1324                             &valleyview_wm_info, latency_ns,
1325                             &valleyview_cursor_wm_info, latency_ns,
1326                             &planeb_wm, &cursorb_wm))
1327                 enabled |= 1 << PIPE_B;
1328
1329         if (single_plane_enabled(enabled) &&
1330             g4x_compute_srwm(dev, ffs(enabled) - 1,
1331                              sr_latency_ns,
1332                              &valleyview_wm_info,
1333                              &valleyview_cursor_wm_info,
1334                              &plane_sr, &ignore_cursor_sr) &&
1335             g4x_compute_srwm(dev, ffs(enabled) - 1,
1336                              2*sr_latency_ns,
1337                              &valleyview_wm_info,
1338                              &valleyview_cursor_wm_info,
1339                              &ignore_plane_sr, &cursor_sr)) {
1340                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1341         } else {
1342                 I915_WRITE(FW_BLC_SELF_VLV,
1343                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1344                 plane_sr = cursor_sr = 0;
1345         }
1346
1347         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1348                       planea_wm, cursora_wm,
1349                       planeb_wm, cursorb_wm,
1350                       plane_sr, cursor_sr);
1351
1352         I915_WRITE(DSPFW1,
1353                    (plane_sr << DSPFW_SR_SHIFT) |
1354                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1355                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1356                    planea_wm);
1357         I915_WRITE(DSPFW2,
1358                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1359                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1360         I915_WRITE(DSPFW3,
1361                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1362                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1363 }
1364
1365 static void g4x_update_wm(struct drm_crtc *crtc)
1366 {
1367         struct drm_device *dev = crtc->dev;
1368         static const int sr_latency_ns = 12000;
1369         struct drm_i915_private *dev_priv = dev->dev_private;
1370         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1371         int plane_sr, cursor_sr;
1372         unsigned int enabled = 0;
1373
1374         if (g4x_compute_wm0(dev, PIPE_A,
1375                             &g4x_wm_info, latency_ns,
1376                             &g4x_cursor_wm_info, latency_ns,
1377                             &planea_wm, &cursora_wm))
1378                 enabled |= 1 << PIPE_A;
1379
1380         if (g4x_compute_wm0(dev, PIPE_B,
1381                             &g4x_wm_info, latency_ns,
1382                             &g4x_cursor_wm_info, latency_ns,
1383                             &planeb_wm, &cursorb_wm))
1384                 enabled |= 1 << PIPE_B;
1385
1386         if (single_plane_enabled(enabled) &&
1387             g4x_compute_srwm(dev, ffs(enabled) - 1,
1388                              sr_latency_ns,
1389                              &g4x_wm_info,
1390                              &g4x_cursor_wm_info,
1391                              &plane_sr, &cursor_sr)) {
1392                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1393         } else {
1394                 I915_WRITE(FW_BLC_SELF,
1395                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1396                 plane_sr = cursor_sr = 0;
1397         }
1398
1399         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1400                       planea_wm, cursora_wm,
1401                       planeb_wm, cursorb_wm,
1402                       plane_sr, cursor_sr);
1403
1404         I915_WRITE(DSPFW1,
1405                    (plane_sr << DSPFW_SR_SHIFT) |
1406                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1407                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1408                    planea_wm);
1409         I915_WRITE(DSPFW2,
1410                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1411                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1412         /* HPLL off in SR has some issues on G4x... disable it */
1413         I915_WRITE(DSPFW3,
1414                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1415                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1416 }
1417
1418 static void i965_update_wm(struct drm_crtc *unused_crtc)
1419 {
1420         struct drm_device *dev = unused_crtc->dev;
1421         struct drm_i915_private *dev_priv = dev->dev_private;
1422         struct drm_crtc *crtc;
1423         int srwm = 1;
1424         int cursor_sr = 16;
1425
1426         /* Calc sr entries for one plane configs */
1427         crtc = single_enabled_crtc(dev);
1428         if (crtc) {
1429                 /* self-refresh has much higher latency */
1430                 static const int sr_latency_ns = 12000;
1431                 const struct drm_display_mode *adjusted_mode =
1432                         &to_intel_crtc(crtc)->config.adjusted_mode;
1433                 int clock = adjusted_mode->crtc_clock;
1434                 int htotal = adjusted_mode->htotal;
1435                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1436                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1437                 unsigned long line_time_us;
1438                 int entries;
1439
1440                 line_time_us = ((htotal * 1000) / clock);
1441
1442                 /* Use ns/us then divide to preserve precision */
1443                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1444                         pixel_size * hdisplay;
1445                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1446                 srwm = I965_FIFO_SIZE - entries;
1447                 if (srwm < 0)
1448                         srwm = 1;
1449                 srwm &= 0x1ff;
1450                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1451                               entries, srwm);
1452
1453                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1454                         pixel_size * 64;
1455                 entries = DIV_ROUND_UP(entries,
1456                                           i965_cursor_wm_info.cacheline_size);
1457                 cursor_sr = i965_cursor_wm_info.fifo_size -
1458                         (entries + i965_cursor_wm_info.guard_size);
1459
1460                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1461                         cursor_sr = i965_cursor_wm_info.max_wm;
1462
1463                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1464                               "cursor %d\n", srwm, cursor_sr);
1465
1466                 if (IS_CRESTLINE(dev))
1467                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1468         } else {
1469                 /* Turn off self refresh if both pipes are enabled */
1470                 if (IS_CRESTLINE(dev))
1471                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1472                                    & ~FW_BLC_SELF_EN);
1473         }
1474
1475         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1476                       srwm);
1477
1478         /* 965 has limitations... */
1479         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1480                    (8 << 16) | (8 << 8) | (8 << 0));
1481         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1482         /* update cursor SR watermark */
1483         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1484 }
1485
1486 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1487 {
1488         struct drm_device *dev = unused_crtc->dev;
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490         const struct intel_watermark_params *wm_info;
1491         uint32_t fwater_lo;
1492         uint32_t fwater_hi;
1493         int cwm, srwm = 1;
1494         int fifo_size;
1495         int planea_wm, planeb_wm;
1496         struct drm_crtc *crtc, *enabled = NULL;
1497
1498         if (IS_I945GM(dev))
1499                 wm_info = &i945_wm_info;
1500         else if (!IS_GEN2(dev))
1501                 wm_info = &i915_wm_info;
1502         else
1503                 wm_info = &i830_wm_info;
1504
1505         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1506         crtc = intel_get_crtc_for_plane(dev, 0);
1507         if (intel_crtc_active(crtc)) {
1508                 const struct drm_display_mode *adjusted_mode;
1509                 int cpp = crtc->fb->bits_per_pixel / 8;
1510                 if (IS_GEN2(dev))
1511                         cpp = 4;
1512
1513                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1514                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1515                                                wm_info, fifo_size, cpp,
1516                                                latency_ns);
1517                 enabled = crtc;
1518         } else
1519                 planea_wm = fifo_size - wm_info->guard_size;
1520
1521         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1522         crtc = intel_get_crtc_for_plane(dev, 1);
1523         if (intel_crtc_active(crtc)) {
1524                 const struct drm_display_mode *adjusted_mode;
1525                 int cpp = crtc->fb->bits_per_pixel / 8;
1526                 if (IS_GEN2(dev))
1527                         cpp = 4;
1528
1529                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1530                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1531                                                wm_info, fifo_size, cpp,
1532                                                latency_ns);
1533                 if (enabled == NULL)
1534                         enabled = crtc;
1535                 else
1536                         enabled = NULL;
1537         } else
1538                 planeb_wm = fifo_size - wm_info->guard_size;
1539
1540         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1541
1542         /*
1543          * Overlay gets an aggressive default since video jitter is bad.
1544          */
1545         cwm = 2;
1546
1547         /* Play safe and disable self-refresh before adjusting watermarks. */
1548         if (IS_I945G(dev) || IS_I945GM(dev))
1549                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1550         else if (IS_I915GM(dev))
1551                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1552
1553         /* Calc sr entries for one plane configs */
1554         if (HAS_FW_BLC(dev) && enabled) {
1555                 /* self-refresh has much higher latency */
1556                 static const int sr_latency_ns = 6000;
1557                 const struct drm_display_mode *adjusted_mode =
1558                         &to_intel_crtc(enabled)->config.adjusted_mode;
1559                 int clock = adjusted_mode->crtc_clock;
1560                 int htotal = adjusted_mode->htotal;
1561                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1562                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1563                 unsigned long line_time_us;
1564                 int entries;
1565
1566                 line_time_us = (htotal * 1000) / clock;
1567
1568                 /* Use ns/us then divide to preserve precision */
1569                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1570                         pixel_size * hdisplay;
1571                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1572                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1573                 srwm = wm_info->fifo_size - entries;
1574                 if (srwm < 0)
1575                         srwm = 1;
1576
1577                 if (IS_I945G(dev) || IS_I945GM(dev))
1578                         I915_WRITE(FW_BLC_SELF,
1579                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1580                 else if (IS_I915GM(dev))
1581                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1582         }
1583
1584         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1585                       planea_wm, planeb_wm, cwm, srwm);
1586
1587         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1588         fwater_hi = (cwm & 0x1f);
1589
1590         /* Set request length to 8 cachelines per fetch */
1591         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1592         fwater_hi = fwater_hi | (1 << 8);
1593
1594         I915_WRITE(FW_BLC, fwater_lo);
1595         I915_WRITE(FW_BLC2, fwater_hi);
1596
1597         if (HAS_FW_BLC(dev)) {
1598                 if (enabled) {
1599                         if (IS_I945G(dev) || IS_I945GM(dev))
1600                                 I915_WRITE(FW_BLC_SELF,
1601                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1602                         else if (IS_I915GM(dev))
1603                                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1604                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1605                 } else
1606                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1607         }
1608 }
1609
1610 static void i845_update_wm(struct drm_crtc *unused_crtc)
1611 {
1612         struct drm_device *dev = unused_crtc->dev;
1613         struct drm_i915_private *dev_priv = dev->dev_private;
1614         struct drm_crtc *crtc;
1615         const struct drm_display_mode *adjusted_mode;
1616         uint32_t fwater_lo;
1617         int planea_wm;
1618
1619         crtc = single_enabled_crtc(dev);
1620         if (crtc == NULL)
1621                 return;
1622
1623         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1624         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1625                                        &i845_wm_info,
1626                                        dev_priv->display.get_fifo_size(dev, 0),
1627                                        4, latency_ns);
1628         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1629         fwater_lo |= (3<<8) | planea_wm;
1630
1631         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1632
1633         I915_WRITE(FW_BLC, fwater_lo);
1634 }
1635
1636 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1637                                     struct drm_crtc *crtc)
1638 {
1639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1640         uint32_t pixel_rate;
1641
1642         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1643
1644         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1645          * adjust the pixel_rate here. */
1646
1647         if (intel_crtc->config.pch_pfit.enabled) {
1648                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1649                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1650
1651                 pipe_w = intel_crtc->config.pipe_src_w;
1652                 pipe_h = intel_crtc->config.pipe_src_h;
1653                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1654                 pfit_h = pfit_size & 0xFFFF;
1655                 if (pipe_w < pfit_w)
1656                         pipe_w = pfit_w;
1657                 if (pipe_h < pfit_h)
1658                         pipe_h = pfit_h;
1659
1660                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1661                                      pfit_w * pfit_h);
1662         }
1663
1664         return pixel_rate;
1665 }
1666
1667 /* latency must be in 0.1us units. */
1668 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1669                                uint32_t latency)
1670 {
1671         uint64_t ret;
1672
1673         if (WARN(latency == 0, "Latency value missing\n"))
1674                 return UINT_MAX;
1675
1676         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1677         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1678
1679         return ret;
1680 }
1681
1682 /* latency must be in 0.1us units. */
1683 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1684                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1685                                uint32_t latency)
1686 {
1687         uint32_t ret;
1688
1689         if (WARN(latency == 0, "Latency value missing\n"))
1690                 return UINT_MAX;
1691
1692         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1693         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1694         ret = DIV_ROUND_UP(ret, 64) + 2;
1695         return ret;
1696 }
1697
1698 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1699                            uint8_t bytes_per_pixel)
1700 {
1701         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1702 }
1703
1704 struct ilk_pipe_wm_parameters {
1705         bool active;
1706         uint32_t pipe_htotal;
1707         uint32_t pixel_rate;
1708         struct intel_plane_wm_parameters pri;
1709         struct intel_plane_wm_parameters spr;
1710         struct intel_plane_wm_parameters cur;
1711 };
1712
1713 struct ilk_wm_maximums {
1714         uint16_t pri;
1715         uint16_t spr;
1716         uint16_t cur;
1717         uint16_t fbc;
1718 };
1719
1720 /* used in computing the new watermarks state */
1721 struct intel_wm_config {
1722         unsigned int num_pipes_active;
1723         bool sprites_enabled;
1724         bool sprites_scaled;
1725 };
1726
1727 /*
1728  * For both WM_PIPE and WM_LP.
1729  * mem_value must be in 0.1us units.
1730  */
1731 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1732                                    uint32_t mem_value,
1733                                    bool is_lp)
1734 {
1735         uint32_t method1, method2;
1736
1737         if (!params->active || !params->pri.enabled)
1738                 return 0;
1739
1740         method1 = ilk_wm_method1(params->pixel_rate,
1741                                  params->pri.bytes_per_pixel,
1742                                  mem_value);
1743
1744         if (!is_lp)
1745                 return method1;
1746
1747         method2 = ilk_wm_method2(params->pixel_rate,
1748                                  params->pipe_htotal,
1749                                  params->pri.horiz_pixels,
1750                                  params->pri.bytes_per_pixel,
1751                                  mem_value);
1752
1753         return min(method1, method2);
1754 }
1755
1756 /*
1757  * For both WM_PIPE and WM_LP.
1758  * mem_value must be in 0.1us units.
1759  */
1760 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1761                                    uint32_t mem_value)
1762 {
1763         uint32_t method1, method2;
1764
1765         if (!params->active || !params->spr.enabled)
1766                 return 0;
1767
1768         method1 = ilk_wm_method1(params->pixel_rate,
1769                                  params->spr.bytes_per_pixel,
1770                                  mem_value);
1771         method2 = ilk_wm_method2(params->pixel_rate,
1772                                  params->pipe_htotal,
1773                                  params->spr.horiz_pixels,
1774                                  params->spr.bytes_per_pixel,
1775                                  mem_value);
1776         return min(method1, method2);
1777 }
1778
1779 /*
1780  * For both WM_PIPE and WM_LP.
1781  * mem_value must be in 0.1us units.
1782  */
1783 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1784                                    uint32_t mem_value)
1785 {
1786         if (!params->active || !params->cur.enabled)
1787                 return 0;
1788
1789         return ilk_wm_method2(params->pixel_rate,
1790                               params->pipe_htotal,
1791                               params->cur.horiz_pixels,
1792                               params->cur.bytes_per_pixel,
1793                               mem_value);
1794 }
1795
1796 /* Only for WM_LP. */
1797 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1798                                    uint32_t pri_val)
1799 {
1800         if (!params->active || !params->pri.enabled)
1801                 return 0;
1802
1803         return ilk_wm_fbc(pri_val,
1804                           params->pri.horiz_pixels,
1805                           params->pri.bytes_per_pixel);
1806 }
1807
1808 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1809 {
1810         if (INTEL_INFO(dev)->gen >= 8)
1811                 return 3072;
1812         else if (INTEL_INFO(dev)->gen >= 7)
1813                 return 768;
1814         else
1815                 return 512;
1816 }
1817
1818 /* Calculate the maximum primary/sprite plane watermark */
1819 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1820                                      int level,
1821                                      const struct intel_wm_config *config,
1822                                      enum intel_ddb_partitioning ddb_partitioning,
1823                                      bool is_sprite)
1824 {
1825         unsigned int fifo_size = ilk_display_fifo_size(dev);
1826         unsigned int max;
1827
1828         /* if sprites aren't enabled, sprites get nothing */
1829         if (is_sprite && !config->sprites_enabled)
1830                 return 0;
1831
1832         /* HSW allows LP1+ watermarks even with multiple pipes */
1833         if (level == 0 || config->num_pipes_active > 1) {
1834                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1835
1836                 /*
1837                  * For some reason the non self refresh
1838                  * FIFO size is only half of the self
1839                  * refresh FIFO size on ILK/SNB.
1840                  */
1841                 if (INTEL_INFO(dev)->gen <= 6)
1842                         fifo_size /= 2;
1843         }
1844
1845         if (config->sprites_enabled) {
1846                 /* level 0 is always calculated with 1:1 split */
1847                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1848                         if (is_sprite)
1849                                 fifo_size *= 5;
1850                         fifo_size /= 6;
1851                 } else {
1852                         fifo_size /= 2;
1853                 }
1854         }
1855
1856         /* clamp to max that the registers can hold */
1857         if (INTEL_INFO(dev)->gen >= 8)
1858                 max = level == 0 ? 255 : 2047;
1859         else if (INTEL_INFO(dev)->gen >= 7)
1860                 /* IVB/HSW primary/sprite plane watermarks */
1861                 max = level == 0 ? 127 : 1023;
1862         else if (!is_sprite)
1863                 /* ILK/SNB primary plane watermarks */
1864                 max = level == 0 ? 127 : 511;
1865         else
1866                 /* ILK/SNB sprite plane watermarks */
1867                 max = level == 0 ? 63 : 255;
1868
1869         return min(fifo_size, max);
1870 }
1871
1872 /* Calculate the maximum cursor plane watermark */
1873 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1874                                       int level,
1875                                       const struct intel_wm_config *config)
1876 {
1877         /* HSW LP1+ watermarks w/ multiple pipes */
1878         if (level > 0 && config->num_pipes_active > 1)
1879                 return 64;
1880
1881         /* otherwise just report max that registers can hold */
1882         if (INTEL_INFO(dev)->gen >= 7)
1883                 return level == 0 ? 63 : 255;
1884         else
1885                 return level == 0 ? 31 : 63;
1886 }
1887
1888 /* Calculate the maximum FBC watermark */
1889 static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
1890 {
1891         /* max that registers can hold */
1892         if (INTEL_INFO(dev)->gen >= 8)
1893                 return 31;
1894         else
1895                 return 15;
1896 }
1897
1898 static void ilk_compute_wm_maximums(struct drm_device *dev,
1899                                     int level,
1900                                     const struct intel_wm_config *config,
1901                                     enum intel_ddb_partitioning ddb_partitioning,
1902                                     struct ilk_wm_maximums *max)
1903 {
1904         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1905         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1906         max->cur = ilk_cursor_wm_max(dev, level, config);
1907         max->fbc = ilk_fbc_wm_max(dev);
1908 }
1909
1910 static bool ilk_validate_wm_level(int level,
1911                                   const struct ilk_wm_maximums *max,
1912                                   struct intel_wm_level *result)
1913 {
1914         bool ret;
1915
1916         /* already determined to be invalid? */
1917         if (!result->enable)
1918                 return false;
1919
1920         result->enable = result->pri_val <= max->pri &&
1921                          result->spr_val <= max->spr &&
1922                          result->cur_val <= max->cur;
1923
1924         ret = result->enable;
1925
1926         /*
1927          * HACK until we can pre-compute everything,
1928          * and thus fail gracefully if LP0 watermarks
1929          * are exceeded...
1930          */
1931         if (level == 0 && !result->enable) {
1932                 if (result->pri_val > max->pri)
1933                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1934                                       level, result->pri_val, max->pri);
1935                 if (result->spr_val > max->spr)
1936                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1937                                       level, result->spr_val, max->spr);
1938                 if (result->cur_val > max->cur)
1939                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1940                                       level, result->cur_val, max->cur);
1941
1942                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1943                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1944                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1945                 result->enable = true;
1946         }
1947
1948         return ret;
1949 }
1950
1951 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
1952                                  int level,
1953                                  const struct ilk_pipe_wm_parameters *p,
1954                                  struct intel_wm_level *result)
1955 {
1956         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1957         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1958         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1959
1960         /* WM1+ latency values stored in 0.5us units */
1961         if (level > 0) {
1962                 pri_latency *= 5;
1963                 spr_latency *= 5;
1964                 cur_latency *= 5;
1965         }
1966
1967         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1968         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1969         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1970         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1971         result->enable = true;
1972 }
1973
1974 static uint32_t
1975 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1976 {
1977         struct drm_i915_private *dev_priv = dev->dev_private;
1978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1979         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
1980         u32 linetime, ips_linetime;
1981
1982         if (!intel_crtc_active(crtc))
1983                 return 0;
1984
1985         /* The WM are computed with base on how long it takes to fill a single
1986          * row at the given clock rate, multiplied by 8.
1987          * */
1988         linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
1989         ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
1990                                          intel_ddi_get_cdclk_freq(dev_priv));
1991
1992         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1993                PIPE_WM_LINETIME_TIME(linetime);
1994 }
1995
1996 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
1997 {
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999
2000         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2001                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2002
2003                 wm[0] = (sskpd >> 56) & 0xFF;
2004                 if (wm[0] == 0)
2005                         wm[0] = sskpd & 0xF;
2006                 wm[1] = (sskpd >> 4) & 0xFF;
2007                 wm[2] = (sskpd >> 12) & 0xFF;
2008                 wm[3] = (sskpd >> 20) & 0x1FF;
2009                 wm[4] = (sskpd >> 32) & 0x1FF;
2010         } else if (INTEL_INFO(dev)->gen >= 6) {
2011                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2012
2013                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2014                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2015                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2016                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2017         } else if (INTEL_INFO(dev)->gen >= 5) {
2018                 uint32_t mltr = I915_READ(MLTR_ILK);
2019
2020                 /* ILK primary LP0 latency is 700 ns */
2021                 wm[0] = 7;
2022                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2023                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2024         }
2025 }
2026
2027 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2028 {
2029         /* ILK sprite LP0 latency is 1300 ns */
2030         if (INTEL_INFO(dev)->gen == 5)
2031                 wm[0] = 13;
2032 }
2033
2034 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2035 {
2036         /* ILK cursor LP0 latency is 1300 ns */
2037         if (INTEL_INFO(dev)->gen == 5)
2038                 wm[0] = 13;
2039
2040         /* WaDoubleCursorLP3Latency:ivb */
2041         if (IS_IVYBRIDGE(dev))
2042                 wm[3] *= 2;
2043 }
2044
2045 static int ilk_wm_max_level(const struct drm_device *dev)
2046 {
2047         /* how many WM levels are we expecting */
2048         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2049                 return 4;
2050         else if (INTEL_INFO(dev)->gen >= 6)
2051                 return 3;
2052         else
2053                 return 2;
2054 }
2055
2056 static void intel_print_wm_latency(struct drm_device *dev,
2057                                    const char *name,
2058                                    const uint16_t wm[5])
2059 {
2060         int level, max_level = ilk_wm_max_level(dev);
2061
2062         for (level = 0; level <= max_level; level++) {
2063                 unsigned int latency = wm[level];
2064
2065                 if (latency == 0) {
2066                         DRM_ERROR("%s WM%d latency not provided\n",
2067                                   name, level);
2068                         continue;
2069                 }
2070
2071                 /* WM1+ latency values in 0.5us units */
2072                 if (level > 0)
2073                         latency *= 5;
2074
2075                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2076                               name, level, wm[level],
2077                               latency / 10, latency % 10);
2078         }
2079 }
2080
2081 static void intel_setup_wm_latency(struct drm_device *dev)
2082 {
2083         struct drm_i915_private *dev_priv = dev->dev_private;
2084
2085         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2086
2087         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2088                sizeof(dev_priv->wm.pri_latency));
2089         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2090                sizeof(dev_priv->wm.pri_latency));
2091
2092         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2093         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2094
2095         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2096         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2097         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2098 }
2099
2100 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2101                                       struct ilk_pipe_wm_parameters *p,
2102                                       struct intel_wm_config *config)
2103 {
2104         struct drm_device *dev = crtc->dev;
2105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2106         enum pipe pipe = intel_crtc->pipe;
2107         struct drm_plane *plane;
2108
2109         p->active = intel_crtc_active(crtc);
2110         if (p->active) {
2111                 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2112                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2113                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2114                 p->cur.bytes_per_pixel = 4;
2115                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2116                 p->cur.horiz_pixels = 64;
2117                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2118                 p->pri.enabled = true;
2119                 p->cur.enabled = true;
2120         }
2121
2122         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2123                 config->num_pipes_active += intel_crtc_active(crtc);
2124
2125         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2126                 struct intel_plane *intel_plane = to_intel_plane(plane);
2127
2128                 if (intel_plane->pipe == pipe)
2129                         p->spr = intel_plane->wm;
2130
2131                 config->sprites_enabled |= intel_plane->wm.enabled;
2132                 config->sprites_scaled |= intel_plane->wm.scaled;
2133         }
2134 }
2135
2136 /* Compute new watermarks for the pipe */
2137 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2138                                   const struct ilk_pipe_wm_parameters *params,
2139                                   struct intel_pipe_wm *pipe_wm)
2140 {
2141         struct drm_device *dev = crtc->dev;
2142         struct drm_i915_private *dev_priv = dev->dev_private;
2143         int level, max_level = ilk_wm_max_level(dev);
2144         /* LP0 watermark maximums depend on this pipe alone */
2145         struct intel_wm_config config = {
2146                 .num_pipes_active = 1,
2147                 .sprites_enabled = params->spr.enabled,
2148                 .sprites_scaled = params->spr.scaled,
2149         };
2150         struct ilk_wm_maximums max;
2151
2152         /* LP0 watermarks always use 1/2 DDB partitioning */
2153         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2154
2155         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2156         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2157                 max_level = 1;
2158
2159         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2160         if (params->spr.scaled)
2161                 max_level = 0;
2162
2163         for (level = 0; level <= max_level; level++)
2164                 ilk_compute_wm_level(dev_priv, level, params,
2165                                      &pipe_wm->wm[level]);
2166
2167         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2168                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2169
2170         /* At least LP0 must be valid */
2171         return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2172 }
2173
2174 /*
2175  * Merge the watermarks from all active pipes for a specific level.
2176  */
2177 static void ilk_merge_wm_level(struct drm_device *dev,
2178                                int level,
2179                                struct intel_wm_level *ret_wm)
2180 {
2181         const struct intel_crtc *intel_crtc;
2182
2183         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2184                 const struct intel_wm_level *wm =
2185                         &intel_crtc->wm.active.wm[level];
2186
2187                 if (!wm->enable)
2188                         return;
2189
2190                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2191                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2192                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2193                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2194         }
2195
2196         ret_wm->enable = true;
2197 }
2198
2199 /*
2200  * Merge all low power watermarks for all active pipes.
2201  */
2202 static void ilk_wm_merge(struct drm_device *dev,
2203                          const struct intel_wm_config *config,
2204                          const struct ilk_wm_maximums *max,
2205                          struct intel_pipe_wm *merged)
2206 {
2207         int level, max_level = ilk_wm_max_level(dev);
2208
2209         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2210         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2211             config->num_pipes_active > 1)
2212                 return;
2213
2214         /* ILK: FBC WM must be disabled always */
2215         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2216
2217         /* merge each WM1+ level */
2218         for (level = 1; level <= max_level; level++) {
2219                 struct intel_wm_level *wm = &merged->wm[level];
2220
2221                 ilk_merge_wm_level(dev, level, wm);
2222
2223                 if (!ilk_validate_wm_level(level, max, wm))
2224                         break;
2225
2226                 /*
2227                  * The spec says it is preferred to disable
2228                  * FBC WMs instead of disabling a WM level.
2229                  */
2230                 if (wm->fbc_val > max->fbc) {
2231                         merged->fbc_wm_enabled = false;
2232                         wm->fbc_val = 0;
2233                 }
2234         }
2235
2236         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2237         /*
2238          * FIXME this is racy. FBC might get enabled later.
2239          * What we should check here is whether FBC can be
2240          * enabled sometime later.
2241          */
2242         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2243                 for (level = 2; level <= max_level; level++) {
2244                         struct intel_wm_level *wm = &merged->wm[level];
2245
2246                         wm->enable = false;
2247                 }
2248         }
2249 }
2250
2251 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2252 {
2253         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2254         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2255 }
2256
2257 /* The value we need to program into the WM_LPx latency field */
2258 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2259 {
2260         struct drm_i915_private *dev_priv = dev->dev_private;
2261
2262         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2263                 return 2 * level;
2264         else
2265                 return dev_priv->wm.pri_latency[level];
2266 }
2267
2268 static void ilk_compute_wm_results(struct drm_device *dev,
2269                                    const struct intel_pipe_wm *merged,
2270                                    enum intel_ddb_partitioning partitioning,
2271                                    struct ilk_wm_values *results)
2272 {
2273         struct intel_crtc *intel_crtc;
2274         int level, wm_lp;
2275
2276         results->enable_fbc_wm = merged->fbc_wm_enabled;
2277         results->partitioning = partitioning;
2278
2279         /* LP1+ register values */
2280         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2281                 const struct intel_wm_level *r;
2282
2283                 level = ilk_wm_lp_to_level(wm_lp, merged);
2284
2285                 r = &merged->wm[level];
2286                 if (!r->enable)
2287                         break;
2288
2289                 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2290                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2291                         (r->pri_val << WM1_LP_SR_SHIFT) |
2292                         r->cur_val;
2293
2294                 if (INTEL_INFO(dev)->gen >= 8)
2295                         results->wm_lp[wm_lp - 1] |=
2296                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2297                 else
2298                         results->wm_lp[wm_lp - 1] |=
2299                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2300
2301                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2302                         WARN_ON(wm_lp != 1);
2303                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2304                 } else
2305                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2306         }
2307
2308         /* LP0 register values */
2309         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2310                 enum pipe pipe = intel_crtc->pipe;
2311                 const struct intel_wm_level *r =
2312                         &intel_crtc->wm.active.wm[0];
2313
2314                 if (WARN_ON(!r->enable))
2315                         continue;
2316
2317                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2318
2319                 results->wm_pipe[pipe] =
2320                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2321                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2322                         r->cur_val;
2323         }
2324 }
2325
2326 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2327  * case both are at the same level. Prefer r1 in case they're the same. */
2328 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2329                                                   struct intel_pipe_wm *r1,
2330                                                   struct intel_pipe_wm *r2)
2331 {
2332         int level, max_level = ilk_wm_max_level(dev);
2333         int level1 = 0, level2 = 0;
2334
2335         for (level = 1; level <= max_level; level++) {
2336                 if (r1->wm[level].enable)
2337                         level1 = level;
2338                 if (r2->wm[level].enable)
2339                         level2 = level;
2340         }
2341
2342         if (level1 == level2) {
2343                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2344                         return r2;
2345                 else
2346                         return r1;
2347         } else if (level1 > level2) {
2348                 return r1;
2349         } else {
2350                 return r2;
2351         }
2352 }
2353
2354 /* dirty bits used to track which watermarks need changes */
2355 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2356 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2357 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2358 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2359 #define WM_DIRTY_FBC (1 << 24)
2360 #define WM_DIRTY_DDB (1 << 25)
2361
2362 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2363                                          const struct ilk_wm_values *old,
2364                                          const struct ilk_wm_values *new)
2365 {
2366         unsigned int dirty = 0;
2367         enum pipe pipe;
2368         int wm_lp;
2369
2370         for_each_pipe(pipe) {
2371                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2372                         dirty |= WM_DIRTY_LINETIME(pipe);
2373                         /* Must disable LP1+ watermarks too */
2374                         dirty |= WM_DIRTY_LP_ALL;
2375                 }
2376
2377                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2378                         dirty |= WM_DIRTY_PIPE(pipe);
2379                         /* Must disable LP1+ watermarks too */
2380                         dirty |= WM_DIRTY_LP_ALL;
2381                 }
2382         }
2383
2384         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2385                 dirty |= WM_DIRTY_FBC;
2386                 /* Must disable LP1+ watermarks too */
2387                 dirty |= WM_DIRTY_LP_ALL;
2388         }
2389
2390         if (old->partitioning != new->partitioning) {
2391                 dirty |= WM_DIRTY_DDB;
2392                 /* Must disable LP1+ watermarks too */
2393                 dirty |= WM_DIRTY_LP_ALL;
2394         }
2395
2396         /* LP1+ watermarks already deemed dirty, no need to continue */
2397         if (dirty & WM_DIRTY_LP_ALL)
2398                 return dirty;
2399
2400         /* Find the lowest numbered LP1+ watermark in need of an update... */
2401         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2402                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2403                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2404                         break;
2405         }
2406
2407         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2408         for (; wm_lp <= 3; wm_lp++)
2409                 dirty |= WM_DIRTY_LP(wm_lp);
2410
2411         return dirty;
2412 }
2413
2414 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2415                                unsigned int dirty)
2416 {
2417         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2418         bool changed = false;
2419
2420         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2421                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2422                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2423                 changed = true;
2424         }
2425         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2426                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2427                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2428                 changed = true;
2429         }
2430         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2431                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2432                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2433                 changed = true;
2434         }
2435
2436         /*
2437          * Don't touch WM1S_LP_EN here.
2438          * Doing so could cause underruns.
2439          */
2440
2441         return changed;
2442 }
2443
2444 /*
2445  * The spec says we shouldn't write when we don't need, because every write
2446  * causes WMs to be re-evaluated, expending some power.
2447  */
2448 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2449                                 struct ilk_wm_values *results)
2450 {
2451         struct drm_device *dev = dev_priv->dev;
2452         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2453         unsigned int dirty;
2454         uint32_t val;
2455
2456         dirty = ilk_compute_wm_dirty(dev, previous, results);
2457         if (!dirty)
2458                 return;
2459
2460         _ilk_disable_lp_wm(dev_priv, dirty);
2461
2462         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2463                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2464         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2465                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2466         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2467                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2468
2469         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2470                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2471         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2472                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2473         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2474                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2475
2476         if (dirty & WM_DIRTY_DDB) {
2477                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2478                         val = I915_READ(WM_MISC);
2479                         if (results->partitioning == INTEL_DDB_PART_1_2)
2480                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2481                         else
2482                                 val |= WM_MISC_DATA_PARTITION_5_6;
2483                         I915_WRITE(WM_MISC, val);
2484                 } else {
2485                         val = I915_READ(DISP_ARB_CTL2);
2486                         if (results->partitioning == INTEL_DDB_PART_1_2)
2487                                 val &= ~DISP_DATA_PARTITION_5_6;
2488                         else
2489                                 val |= DISP_DATA_PARTITION_5_6;
2490                         I915_WRITE(DISP_ARB_CTL2, val);
2491                 }
2492         }
2493
2494         if (dirty & WM_DIRTY_FBC) {
2495                 val = I915_READ(DISP_ARB_CTL);
2496                 if (results->enable_fbc_wm)
2497                         val &= ~DISP_FBC_WM_DIS;
2498                 else
2499                         val |= DISP_FBC_WM_DIS;
2500                 I915_WRITE(DISP_ARB_CTL, val);
2501         }
2502
2503         if (dirty & WM_DIRTY_LP(1) &&
2504             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2505                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2506
2507         if (INTEL_INFO(dev)->gen >= 7) {
2508                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2509                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2510                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2511                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2512         }
2513
2514         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2515                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2516         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2517                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2518         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2519                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2520
2521         dev_priv->wm.hw = *results;
2522 }
2523
2524 static bool ilk_disable_lp_wm(struct drm_device *dev)
2525 {
2526         struct drm_i915_private *dev_priv = dev->dev_private;
2527
2528         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2529 }
2530
2531 static void ilk_update_wm(struct drm_crtc *crtc)
2532 {
2533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2534         struct drm_device *dev = crtc->dev;
2535         struct drm_i915_private *dev_priv = dev->dev_private;
2536         struct ilk_wm_maximums max;
2537         struct ilk_pipe_wm_parameters params = {};
2538         struct ilk_wm_values results = {};
2539         enum intel_ddb_partitioning partitioning;
2540         struct intel_pipe_wm pipe_wm = {};
2541         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2542         struct intel_wm_config config = {};
2543
2544         ilk_compute_wm_parameters(crtc, &params, &config);
2545
2546         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2547
2548         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2549                 return;
2550
2551         intel_crtc->wm.active = pipe_wm;
2552
2553         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2554         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2555
2556         /* 5/6 split only in single pipe config on IVB+ */
2557         if (INTEL_INFO(dev)->gen >= 7 &&
2558             config.num_pipes_active == 1 && config.sprites_enabled) {
2559                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2560                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2561
2562                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2563         } else {
2564                 best_lp_wm = &lp_wm_1_2;
2565         }
2566
2567         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2568                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2569
2570         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2571
2572         ilk_write_wm_values(dev_priv, &results);
2573 }
2574
2575 static void ilk_update_sprite_wm(struct drm_plane *plane,
2576                                      struct drm_crtc *crtc,
2577                                      uint32_t sprite_width, int pixel_size,
2578                                      bool enabled, bool scaled)
2579 {
2580         struct drm_device *dev = plane->dev;
2581         struct intel_plane *intel_plane = to_intel_plane(plane);
2582
2583         intel_plane->wm.enabled = enabled;
2584         intel_plane->wm.scaled = scaled;
2585         intel_plane->wm.horiz_pixels = sprite_width;
2586         intel_plane->wm.bytes_per_pixel = pixel_size;
2587
2588         /*
2589          * IVB workaround: must disable low power watermarks for at least
2590          * one frame before enabling scaling.  LP watermarks can be re-enabled
2591          * when scaling is disabled.
2592          *
2593          * WaCxSRDisabledForSpriteScaling:ivb
2594          */
2595         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2596                 intel_wait_for_vblank(dev, intel_plane->pipe);
2597
2598         ilk_update_wm(crtc);
2599 }
2600
2601 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2602 {
2603         struct drm_device *dev = crtc->dev;
2604         struct drm_i915_private *dev_priv = dev->dev_private;
2605         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2607         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2608         enum pipe pipe = intel_crtc->pipe;
2609         static const unsigned int wm0_pipe_reg[] = {
2610                 [PIPE_A] = WM0_PIPEA_ILK,
2611                 [PIPE_B] = WM0_PIPEB_ILK,
2612                 [PIPE_C] = WM0_PIPEC_IVB,
2613         };
2614
2615         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2616         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2617                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2618
2619         if (intel_crtc_active(crtc)) {
2620                 u32 tmp = hw->wm_pipe[pipe];
2621
2622                 /*
2623                  * For active pipes LP0 watermark is marked as
2624                  * enabled, and LP1+ watermaks as disabled since
2625                  * we can't really reverse compute them in case
2626                  * multiple pipes are active.
2627                  */
2628                 active->wm[0].enable = true;
2629                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2630                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2631                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2632                 active->linetime = hw->wm_linetime[pipe];
2633         } else {
2634                 int level, max_level = ilk_wm_max_level(dev);
2635
2636                 /*
2637                  * For inactive pipes, all watermark levels
2638                  * should be marked as enabled but zeroed,
2639                  * which is what we'd compute them to.
2640                  */
2641                 for (level = 0; level <= max_level; level++)
2642                         active->wm[level].enable = true;
2643         }
2644 }
2645
2646 void ilk_wm_get_hw_state(struct drm_device *dev)
2647 {
2648         struct drm_i915_private *dev_priv = dev->dev_private;
2649         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2650         struct drm_crtc *crtc;
2651
2652         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2653                 ilk_pipe_wm_get_hw_state(crtc);
2654
2655         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2656         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2657         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2658
2659         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2660         hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2661         hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2662
2663         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2664                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2665                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2666         else if (IS_IVYBRIDGE(dev))
2667                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2668                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2669
2670         hw->enable_fbc_wm =
2671                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2672 }
2673
2674 /**
2675  * intel_update_watermarks - update FIFO watermark values based on current modes
2676  *
2677  * Calculate watermark values for the various WM regs based on current mode
2678  * and plane configuration.
2679  *
2680  * There are several cases to deal with here:
2681  *   - normal (i.e. non-self-refresh)
2682  *   - self-refresh (SR) mode
2683  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2684  *   - lines are small relative to FIFO size (buffer can hold more than 2
2685  *     lines), so need to account for TLB latency
2686  *
2687  *   The normal calculation is:
2688  *     watermark = dotclock * bytes per pixel * latency
2689  *   where latency is platform & configuration dependent (we assume pessimal
2690  *   values here).
2691  *
2692  *   The SR calculation is:
2693  *     watermark = (trunc(latency/line time)+1) * surface width *
2694  *       bytes per pixel
2695  *   where
2696  *     line time = htotal / dotclock
2697  *     surface width = hdisplay for normal plane and 64 for cursor
2698  *   and latency is assumed to be high, as above.
2699  *
2700  * The final value programmed to the register should always be rounded up,
2701  * and include an extra 2 entries to account for clock crossings.
2702  *
2703  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2704  * to set the non-SR watermarks to 8.
2705  */
2706 void intel_update_watermarks(struct drm_crtc *crtc)
2707 {
2708         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2709
2710         if (dev_priv->display.update_wm)
2711                 dev_priv->display.update_wm(crtc);
2712 }
2713
2714 void intel_update_sprite_watermarks(struct drm_plane *plane,
2715                                     struct drm_crtc *crtc,
2716                                     uint32_t sprite_width, int pixel_size,
2717                                     bool enabled, bool scaled)
2718 {
2719         struct drm_i915_private *dev_priv = plane->dev->dev_private;
2720
2721         if (dev_priv->display.update_sprite_wm)
2722                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2723                                                    pixel_size, enabled, scaled);
2724 }
2725
2726 static struct drm_i915_gem_object *
2727 intel_alloc_context_page(struct drm_device *dev)
2728 {
2729         struct drm_i915_gem_object *ctx;
2730         int ret;
2731
2732         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2733
2734         ctx = i915_gem_alloc_object(dev, 4096);
2735         if (!ctx) {
2736                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2737                 return NULL;
2738         }
2739
2740         ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2741         if (ret) {
2742                 DRM_ERROR("failed to pin power context: %d\n", ret);
2743                 goto err_unref;
2744         }
2745
2746         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2747         if (ret) {
2748                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2749                 goto err_unpin;
2750         }
2751
2752         return ctx;
2753
2754 err_unpin:
2755         i915_gem_object_unpin(ctx);
2756 err_unref:
2757         drm_gem_object_unreference(&ctx->base);
2758         return NULL;
2759 }
2760
2761 /**
2762  * Lock protecting IPS related data structures
2763  */
2764 DEFINE_SPINLOCK(mchdev_lock);
2765
2766 /* Global for IPS driver to get at the current i915 device. Protected by
2767  * mchdev_lock. */
2768 static struct drm_i915_private *i915_mch_dev;
2769
2770 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2771 {
2772         struct drm_i915_private *dev_priv = dev->dev_private;
2773         u16 rgvswctl;
2774
2775         assert_spin_locked(&mchdev_lock);
2776
2777         rgvswctl = I915_READ16(MEMSWCTL);
2778         if (rgvswctl & MEMCTL_CMD_STS) {
2779                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2780                 return false; /* still busy with another command */
2781         }
2782
2783         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2784                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2785         I915_WRITE16(MEMSWCTL, rgvswctl);
2786         POSTING_READ16(MEMSWCTL);
2787
2788         rgvswctl |= MEMCTL_CMD_STS;
2789         I915_WRITE16(MEMSWCTL, rgvswctl);
2790
2791         return true;
2792 }
2793
2794 static void ironlake_enable_drps(struct drm_device *dev)
2795 {
2796         struct drm_i915_private *dev_priv = dev->dev_private;
2797         u32 rgvmodectl = I915_READ(MEMMODECTL);
2798         u8 fmax, fmin, fstart, vstart;
2799
2800         spin_lock_irq(&mchdev_lock);
2801
2802         /* Enable temp reporting */
2803         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2804         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2805
2806         /* 100ms RC evaluation intervals */
2807         I915_WRITE(RCUPEI, 100000);
2808         I915_WRITE(RCDNEI, 100000);
2809
2810         /* Set max/min thresholds to 90ms and 80ms respectively */
2811         I915_WRITE(RCBMAXAVG, 90000);
2812         I915_WRITE(RCBMINAVG, 80000);
2813
2814         I915_WRITE(MEMIHYST, 1);
2815
2816         /* Set up min, max, and cur for interrupt handling */
2817         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2818         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2819         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2820                 MEMMODE_FSTART_SHIFT;
2821
2822         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2823                 PXVFREQ_PX_SHIFT;
2824
2825         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2826         dev_priv->ips.fstart = fstart;
2827
2828         dev_priv->ips.max_delay = fstart;
2829         dev_priv->ips.min_delay = fmin;
2830         dev_priv->ips.cur_delay = fstart;
2831
2832         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2833                          fmax, fmin, fstart);
2834
2835         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2836
2837         /*
2838          * Interrupts will be enabled in ironlake_irq_postinstall
2839          */
2840
2841         I915_WRITE(VIDSTART, vstart);
2842         POSTING_READ(VIDSTART);
2843
2844         rgvmodectl |= MEMMODE_SWMODE_EN;
2845         I915_WRITE(MEMMODECTL, rgvmodectl);
2846
2847         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2848                 DRM_ERROR("stuck trying to change perf mode\n");
2849         mdelay(1);
2850
2851         ironlake_set_drps(dev, fstart);
2852
2853         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2854                 I915_READ(0x112e0);
2855         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2856         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2857         getrawmonotonic(&dev_priv->ips.last_time2);
2858
2859         spin_unlock_irq(&mchdev_lock);
2860 }
2861
2862 static void ironlake_disable_drps(struct drm_device *dev)
2863 {
2864         struct drm_i915_private *dev_priv = dev->dev_private;
2865         u16 rgvswctl;
2866
2867         spin_lock_irq(&mchdev_lock);
2868
2869         rgvswctl = I915_READ16(MEMSWCTL);
2870
2871         /* Ack interrupts, disable EFC interrupt */
2872         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2873         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2874         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2875         I915_WRITE(DEIIR, DE_PCU_EVENT);
2876         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2877
2878         /* Go back to the starting frequency */
2879         ironlake_set_drps(dev, dev_priv->ips.fstart);
2880         mdelay(1);
2881         rgvswctl |= MEMCTL_CMD_STS;
2882         I915_WRITE(MEMSWCTL, rgvswctl);
2883         mdelay(1);
2884
2885         spin_unlock_irq(&mchdev_lock);
2886 }
2887
2888 /* There's a funny hw issue where the hw returns all 0 when reading from
2889  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2890  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2891  * all limits and the gpu stuck at whatever frequency it is at atm).
2892  */
2893 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2894 {
2895         u32 limits;
2896
2897         /* Only set the down limit when we've reached the lowest level to avoid
2898          * getting more interrupts, otherwise leave this clear. This prevents a
2899          * race in the hw when coming out of rc6: There's a tiny window where
2900          * the hw runs at the minimal clock before selecting the desired
2901          * frequency, if the down threshold expires in that window we will not
2902          * receive a down interrupt. */
2903         limits = dev_priv->rps.max_delay << 24;
2904         if (val <= dev_priv->rps.min_delay)
2905                 limits |= dev_priv->rps.min_delay << 16;
2906
2907         return limits;
2908 }
2909
2910 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2911 {
2912         int new_power;
2913
2914         new_power = dev_priv->rps.power;
2915         switch (dev_priv->rps.power) {
2916         case LOW_POWER:
2917                 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
2918                         new_power = BETWEEN;
2919                 break;
2920
2921         case BETWEEN:
2922                 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
2923                         new_power = LOW_POWER;
2924                 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
2925                         new_power = HIGH_POWER;
2926                 break;
2927
2928         case HIGH_POWER:
2929                 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
2930                         new_power = BETWEEN;
2931                 break;
2932         }
2933         /* Max/min bins are special */
2934         if (val == dev_priv->rps.min_delay)
2935                 new_power = LOW_POWER;
2936         if (val == dev_priv->rps.max_delay)
2937                 new_power = HIGH_POWER;
2938         if (new_power == dev_priv->rps.power)
2939                 return;
2940
2941         /* Note the units here are not exactly 1us, but 1280ns. */
2942         switch (new_power) {
2943         case LOW_POWER:
2944                 /* Upclock if more than 95% busy over 16ms */
2945                 I915_WRITE(GEN6_RP_UP_EI, 12500);
2946                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2947
2948                 /* Downclock if less than 85% busy over 32ms */
2949                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2950                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
2951
2952                 I915_WRITE(GEN6_RP_CONTROL,
2953                            GEN6_RP_MEDIA_TURBO |
2954                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2955                            GEN6_RP_MEDIA_IS_GFX |
2956                            GEN6_RP_ENABLE |
2957                            GEN6_RP_UP_BUSY_AVG |
2958                            GEN6_RP_DOWN_IDLE_AVG);
2959                 break;
2960
2961         case BETWEEN:
2962                 /* Upclock if more than 90% busy over 13ms */
2963                 I915_WRITE(GEN6_RP_UP_EI, 10250);
2964                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
2965
2966                 /* Downclock if less than 75% busy over 32ms */
2967                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2968                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
2969
2970                 I915_WRITE(GEN6_RP_CONTROL,
2971                            GEN6_RP_MEDIA_TURBO |
2972                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2973                            GEN6_RP_MEDIA_IS_GFX |
2974                            GEN6_RP_ENABLE |
2975                            GEN6_RP_UP_BUSY_AVG |
2976                            GEN6_RP_DOWN_IDLE_AVG);
2977                 break;
2978
2979         case HIGH_POWER:
2980                 /* Upclock if more than 85% busy over 10ms */
2981                 I915_WRITE(GEN6_RP_UP_EI, 8000);
2982                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
2983
2984                 /* Downclock if less than 60% busy over 32ms */
2985                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2986                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
2987
2988                 I915_WRITE(GEN6_RP_CONTROL,
2989                            GEN6_RP_MEDIA_TURBO |
2990                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2991                            GEN6_RP_MEDIA_IS_GFX |
2992                            GEN6_RP_ENABLE |
2993                            GEN6_RP_UP_BUSY_AVG |
2994                            GEN6_RP_DOWN_IDLE_AVG);
2995                 break;
2996         }
2997
2998         dev_priv->rps.power = new_power;
2999         dev_priv->rps.last_adj = 0;
3000 }
3001
3002 void gen6_set_rps(struct drm_device *dev, u8 val)
3003 {
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005
3006         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3007         WARN_ON(val > dev_priv->rps.max_delay);
3008         WARN_ON(val < dev_priv->rps.min_delay);
3009
3010         if (val == dev_priv->rps.cur_delay)
3011                 return;
3012
3013         gen6_set_rps_thresholds(dev_priv, val);
3014
3015         if (IS_HASWELL(dev))
3016                 I915_WRITE(GEN6_RPNSWREQ,
3017                            HSW_FREQUENCY(val));
3018         else
3019                 I915_WRITE(GEN6_RPNSWREQ,
3020                            GEN6_FREQUENCY(val) |
3021                            GEN6_OFFSET(0) |
3022                            GEN6_AGGRESSIVE_TURBO);
3023
3024         /* Make sure we continue to get interrupts
3025          * until we hit the minimum or maximum frequencies.
3026          */
3027         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3028                    gen6_rps_limits(dev_priv, val));
3029
3030         POSTING_READ(GEN6_RPNSWREQ);
3031
3032         dev_priv->rps.cur_delay = val;
3033
3034         trace_intel_gpu_freq_change(val * 50);
3035 }
3036
3037 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3038 {
3039         struct drm_device *dev = dev_priv->dev;
3040
3041         mutex_lock(&dev_priv->rps.hw_lock);
3042         if (dev_priv->rps.enabled) {
3043                 if (IS_VALLEYVIEW(dev))
3044                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3045                 else
3046                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3047                 dev_priv->rps.last_adj = 0;
3048         }
3049         mutex_unlock(&dev_priv->rps.hw_lock);
3050 }
3051
3052 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3053 {
3054         struct drm_device *dev = dev_priv->dev;
3055
3056         mutex_lock(&dev_priv->rps.hw_lock);
3057         if (dev_priv->rps.enabled) {
3058                 if (IS_VALLEYVIEW(dev))
3059                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3060                 else
3061                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3062                 dev_priv->rps.last_adj = 0;
3063         }
3064         mutex_unlock(&dev_priv->rps.hw_lock);
3065 }
3066
3067 void valleyview_set_rps(struct drm_device *dev, u8 val)
3068 {
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070
3071         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3072         WARN_ON(val > dev_priv->rps.max_delay);
3073         WARN_ON(val < dev_priv->rps.min_delay);
3074
3075         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3076                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3077                          dev_priv->rps.cur_delay,
3078                          vlv_gpu_freq(dev_priv, val), val);
3079
3080         if (val == dev_priv->rps.cur_delay)
3081                 return;
3082
3083         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3084
3085         dev_priv->rps.cur_delay = val;
3086
3087         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3088 }
3089
3090 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3091 {
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093
3094         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3095         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3096         /* Complete PM interrupt masking here doesn't race with the rps work
3097          * item again unmasking PM interrupts because that is using a different
3098          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3099          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3100
3101         spin_lock_irq(&dev_priv->irq_lock);
3102         dev_priv->rps.pm_iir = 0;
3103         spin_unlock_irq(&dev_priv->irq_lock);
3104
3105         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3106 }
3107
3108 static void gen6_disable_rps(struct drm_device *dev)
3109 {
3110         struct drm_i915_private *dev_priv = dev->dev_private;
3111
3112         I915_WRITE(GEN6_RC_CONTROL, 0);
3113         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3114
3115         gen6_disable_rps_interrupts(dev);
3116 }
3117
3118 static void valleyview_disable_rps(struct drm_device *dev)
3119 {
3120         struct drm_i915_private *dev_priv = dev->dev_private;
3121
3122         I915_WRITE(GEN6_RC_CONTROL, 0);
3123
3124         gen6_disable_rps_interrupts(dev);
3125
3126         if (dev_priv->vlv_pctx) {
3127                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3128                 dev_priv->vlv_pctx = NULL;
3129         }
3130 }
3131
3132 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3133 {
3134         if (IS_GEN6(dev))
3135                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3136
3137         if (IS_HASWELL(dev))
3138                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3139
3140         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3141                         (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3142                         (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3143                         (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3144 }
3145
3146 int intel_enable_rc6(const struct drm_device *dev)
3147 {
3148         /* No RC6 before Ironlake */
3149         if (INTEL_INFO(dev)->gen < 5)
3150                 return 0;
3151
3152         /* Respect the kernel parameter if it is set */
3153         if (i915_enable_rc6 >= 0)
3154                 return i915_enable_rc6;
3155
3156         /* Disable RC6 on Ironlake */
3157         if (INTEL_INFO(dev)->gen == 5)
3158                 return 0;
3159
3160         if (IS_HASWELL(dev))
3161                 return INTEL_RC6_ENABLE;
3162
3163         /* snb/ivb have more than one rc6 state. */
3164         if (INTEL_INFO(dev)->gen == 6)
3165                 return INTEL_RC6_ENABLE;
3166
3167         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3168 }
3169
3170 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3171 {
3172         struct drm_i915_private *dev_priv = dev->dev_private;
3173         u32 enabled_intrs;
3174
3175         spin_lock_irq(&dev_priv->irq_lock);
3176         WARN_ON(dev_priv->rps.pm_iir);
3177         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3178         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3179         spin_unlock_irq(&dev_priv->irq_lock);
3180
3181         /* only unmask PM interrupts we need. Mask all others. */
3182         enabled_intrs = GEN6_PM_RPS_EVENTS;
3183
3184         /* IVB and SNB hard hangs on looping batchbuffer
3185          * if GEN6_PM_UP_EI_EXPIRED is masked.
3186          */
3187         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3188                 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3189
3190         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3191 }
3192
3193 static void gen8_enable_rps(struct drm_device *dev)
3194 {
3195         struct drm_i915_private *dev_priv = dev->dev_private;
3196         struct intel_ring_buffer *ring;
3197         uint32_t rc6_mask = 0, rp_state_cap;
3198         int unused;
3199
3200         /* 1a: Software RC state - RC0 */
3201         I915_WRITE(GEN6_RC_STATE, 0);
3202
3203         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3204          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3205         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3206
3207         /* 2a: Disable RC states. */
3208         I915_WRITE(GEN6_RC_CONTROL, 0);
3209
3210         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3211
3212         /* 2b: Program RC6 thresholds.*/
3213         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3214         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3215         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3216         for_each_ring(ring, dev_priv, unused)
3217                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3218         I915_WRITE(GEN6_RC_SLEEP, 0);
3219         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3220
3221         /* 3: Enable RC6 */
3222         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3223                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3224         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3225         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3226                         GEN6_RC_CTL_EI_MODE(1) |
3227                         rc6_mask);
3228
3229         /* 4 Program defaults and thresholds for RPS*/
3230         I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3231         I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3232         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3233         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3234
3235         /* Docs recommend 900MHz, and 300 MHz respectively */
3236         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3237                    dev_priv->rps.max_delay << 24 |
3238                    dev_priv->rps.min_delay << 16);
3239
3240         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3241         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3242         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3243         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3244
3245         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3246
3247         /* 5: Enable RPS */
3248         I915_WRITE(GEN6_RP_CONTROL,
3249                    GEN6_RP_MEDIA_TURBO |
3250                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3251                    GEN6_RP_MEDIA_IS_GFX |
3252                    GEN6_RP_ENABLE |
3253                    GEN6_RP_UP_BUSY_AVG |
3254                    GEN6_RP_DOWN_IDLE_AVG);
3255
3256         /* 6: Ring frequency + overclocking (our driver does this later */
3257
3258         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3259
3260         gen6_enable_rps_interrupts(dev);
3261
3262         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3263 }
3264
3265 static void gen6_enable_rps(struct drm_device *dev)
3266 {
3267         struct drm_i915_private *dev_priv = dev->dev_private;
3268         struct intel_ring_buffer *ring;
3269         u32 rp_state_cap;
3270         u32 gt_perf_status;
3271         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3272         u32 gtfifodbg;
3273         int rc6_mode;
3274         int i, ret;
3275
3276         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3277
3278         /* Here begins a magic sequence of register writes to enable
3279          * auto-downclocking.
3280          *
3281          * Perhaps there might be some value in exposing these to
3282          * userspace...
3283          */
3284         I915_WRITE(GEN6_RC_STATE, 0);
3285
3286         /* Clear the DBG now so we don't confuse earlier errors */
3287         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3288                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3289                 I915_WRITE(GTFIFODBG, gtfifodbg);
3290         }
3291
3292         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3293
3294         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3295         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3296
3297         /* In units of 50MHz */
3298         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3299         dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3300         dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
3301         dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
3302         dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3303         dev_priv->rps.cur_delay = 0;
3304
3305         /* disable the counters and set deterministic thresholds */
3306         I915_WRITE(GEN6_RC_CONTROL, 0);
3307
3308         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3309         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3310         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3311         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3312         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3313
3314         for_each_ring(ring, dev_priv, i)
3315                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3316
3317         I915_WRITE(GEN6_RC_SLEEP, 0);
3318         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3319         if (IS_IVYBRIDGE(dev))
3320                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3321         else
3322                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3323         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3324         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3325
3326         /* Check if we are enabling RC6 */
3327         rc6_mode = intel_enable_rc6(dev_priv->dev);
3328         if (rc6_mode & INTEL_RC6_ENABLE)
3329                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3330
3331         /* We don't use those on Haswell */
3332         if (!IS_HASWELL(dev)) {
3333                 if (rc6_mode & INTEL_RC6p_ENABLE)
3334                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3335
3336                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3337                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3338         }
3339
3340         intel_print_rc6_info(dev, rc6_mask);
3341
3342         I915_WRITE(GEN6_RC_CONTROL,
3343                    rc6_mask |
3344                    GEN6_RC_CTL_EI_MODE(1) |
3345                    GEN6_RC_CTL_HW_ENABLE);
3346
3347         /* Power down if completely idle for over 50ms */
3348         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3349         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3350
3351         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3352         if (!ret) {
3353                 pcu_mbox = 0;
3354                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3355                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3356                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3357                                          (dev_priv->rps.max_delay & 0xff) * 50,
3358                                          (pcu_mbox & 0xff) * 50);
3359                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3360                 }
3361         } else {
3362                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3363         }
3364
3365         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3366         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3367
3368         gen6_enable_rps_interrupts(dev);
3369
3370         rc6vids = 0;
3371         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3372         if (IS_GEN6(dev) && ret) {
3373                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3374         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3375                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3376                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3377                 rc6vids &= 0xffff00;
3378                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3379                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3380                 if (ret)
3381                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3382         }
3383
3384         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3385 }
3386
3387 void gen6_update_ring_freq(struct drm_device *dev)
3388 {
3389         struct drm_i915_private *dev_priv = dev->dev_private;
3390         int min_freq = 15;
3391         unsigned int gpu_freq;
3392         unsigned int max_ia_freq, min_ring_freq;
3393         int scaling_factor = 180;
3394         struct cpufreq_policy *policy;
3395
3396         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3397
3398         policy = cpufreq_cpu_get(0);
3399         if (policy) {
3400                 max_ia_freq = policy->cpuinfo.max_freq;
3401                 cpufreq_cpu_put(policy);
3402         } else {
3403                 /*
3404                  * Default to measured freq if none found, PCU will ensure we
3405                  * don't go over
3406                  */
3407                 max_ia_freq = tsc_khz;
3408         }
3409
3410         /* Convert from kHz to MHz */
3411         max_ia_freq /= 1000;
3412
3413         min_ring_freq = I915_READ(DCLK) & 0xf;
3414         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3415         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3416
3417         /*
3418          * For each potential GPU frequency, load a ring frequency we'd like
3419          * to use for memory access.  We do this by specifying the IA frequency
3420          * the PCU should use as a reference to determine the ring frequency.
3421          */
3422         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3423              gpu_freq--) {
3424                 int diff = dev_priv->rps.max_delay - gpu_freq;
3425                 unsigned int ia_freq = 0, ring_freq = 0;
3426
3427                 if (INTEL_INFO(dev)->gen >= 8) {
3428                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3429                         ring_freq = max(min_ring_freq, gpu_freq);
3430                 } else if (IS_HASWELL(dev)) {
3431                         ring_freq = mult_frac(gpu_freq, 5, 4);
3432                         ring_freq = max(min_ring_freq, ring_freq);
3433                         /* leave ia_freq as the default, chosen by cpufreq */
3434                 } else {
3435                         /* On older processors, there is no separate ring
3436                          * clock domain, so in order to boost the bandwidth
3437                          * of the ring, we need to upclock the CPU (ia_freq).
3438                          *
3439                          * For GPU frequencies less than 750MHz,
3440                          * just use the lowest ring freq.
3441                          */
3442                         if (gpu_freq < min_freq)
3443                                 ia_freq = 800;
3444                         else
3445                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3446                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3447                 }
3448
3449                 sandybridge_pcode_write(dev_priv,
3450                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3451                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3452                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3453                                         gpu_freq);
3454         }
3455 }
3456
3457 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3458 {
3459         u32 val, rp0;
3460
3461         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3462
3463         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3464         /* Clamp to max */
3465         rp0 = min_t(u32, rp0, 0xea);
3466
3467         return rp0;
3468 }
3469
3470 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3471 {
3472         u32 val, rpe;
3473
3474         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3475         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3476         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3477         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3478
3479         return rpe;
3480 }
3481
3482 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3483 {
3484         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3485 }
3486
3487 static void valleyview_setup_pctx(struct drm_device *dev)
3488 {
3489         struct drm_i915_private *dev_priv = dev->dev_private;
3490         struct drm_i915_gem_object *pctx;
3491         unsigned long pctx_paddr;
3492         u32 pcbr;
3493         int pctx_size = 24*1024;
3494
3495         pcbr = I915_READ(VLV_PCBR);
3496         if (pcbr) {
3497                 /* BIOS set it up already, grab the pre-alloc'd space */
3498                 int pcbr_offset;
3499
3500                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3501                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3502                                                                       pcbr_offset,
3503                                                                       I915_GTT_OFFSET_NONE,
3504                                                                       pctx_size);
3505                 goto out;
3506         }
3507
3508         /*
3509          * From the Gunit register HAS:
3510          * The Gfx driver is expected to program this register and ensure
3511          * proper allocation within Gfx stolen memory.  For example, this
3512          * register should be programmed such than the PCBR range does not
3513          * overlap with other ranges, such as the frame buffer, protected
3514          * memory, or any other relevant ranges.
3515          */
3516         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3517         if (!pctx) {
3518                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3519                 return;
3520         }
3521
3522         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3523         I915_WRITE(VLV_PCBR, pctx_paddr);
3524
3525 out:
3526         dev_priv->vlv_pctx = pctx;
3527 }
3528
3529 static void valleyview_enable_rps(struct drm_device *dev)
3530 {
3531         struct drm_i915_private *dev_priv = dev->dev_private;
3532         struct intel_ring_buffer *ring;
3533         u32 gtfifodbg, val, rc6_mode = 0;
3534         int i;
3535
3536         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3537
3538         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3539                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3540                                  gtfifodbg);
3541                 I915_WRITE(GTFIFODBG, gtfifodbg);
3542         }
3543
3544         valleyview_setup_pctx(dev);
3545
3546         /* If VLV, Forcewake all wells, else re-direct to regular path */
3547         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3548
3549         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3550         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3551         I915_WRITE(GEN6_RP_UP_EI, 66000);
3552         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3553
3554         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3555
3556         I915_WRITE(GEN6_RP_CONTROL,
3557                    GEN6_RP_MEDIA_TURBO |
3558                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3559                    GEN6_RP_MEDIA_IS_GFX |
3560                    GEN6_RP_ENABLE |
3561                    GEN6_RP_UP_BUSY_AVG |
3562                    GEN6_RP_DOWN_IDLE_CONT);
3563
3564         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3565         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3566         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3567
3568         for_each_ring(ring, dev_priv, i)
3569                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3570
3571         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3572
3573         /* allows RC6 residency counter to work */
3574         I915_WRITE(VLV_COUNTER_CONTROL,
3575                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3576                                       VLV_MEDIA_RC6_COUNT_EN |
3577                                       VLV_RENDER_RC6_COUNT_EN));
3578         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3579                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3580
3581         intel_print_rc6_info(dev, rc6_mode);
3582
3583         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3584
3585         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3586
3587         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3588         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3589
3590         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3591         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3592                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3593                          dev_priv->rps.cur_delay);
3594
3595         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3596         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3597         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3598                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
3599                          dev_priv->rps.max_delay);
3600
3601         dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3602         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3603                          vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
3604                          dev_priv->rps.rpe_delay);
3605
3606         dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3607         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3608                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
3609                          dev_priv->rps.min_delay);
3610
3611         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3612                          vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
3613                          dev_priv->rps.rpe_delay);
3614
3615         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3616
3617         gen6_enable_rps_interrupts(dev);
3618
3619         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3620 }
3621
3622 void ironlake_teardown_rc6(struct drm_device *dev)
3623 {
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625
3626         if (dev_priv->ips.renderctx) {
3627                 i915_gem_object_unpin(dev_priv->ips.renderctx);
3628                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3629                 dev_priv->ips.renderctx = NULL;
3630         }
3631
3632         if (dev_priv->ips.pwrctx) {
3633                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3634                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3635                 dev_priv->ips.pwrctx = NULL;
3636         }
3637 }
3638
3639 static void ironlake_disable_rc6(struct drm_device *dev)
3640 {
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642
3643         if (I915_READ(PWRCTXA)) {
3644                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3645                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3646                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3647                          50);
3648
3649                 I915_WRITE(PWRCTXA, 0);
3650                 POSTING_READ(PWRCTXA);
3651
3652                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3653                 POSTING_READ(RSTDBYCTL);
3654         }
3655 }
3656
3657 static int ironlake_setup_rc6(struct drm_device *dev)
3658 {
3659         struct drm_i915_private *dev_priv = dev->dev_private;
3660
3661         if (dev_priv->ips.renderctx == NULL)
3662                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3663         if (!dev_priv->ips.renderctx)
3664                 return -ENOMEM;
3665
3666         if (dev_priv->ips.pwrctx == NULL)
3667                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3668         if (!dev_priv->ips.pwrctx) {
3669                 ironlake_teardown_rc6(dev);
3670                 return -ENOMEM;
3671         }
3672
3673         return 0;
3674 }
3675
3676 static void ironlake_enable_rc6(struct drm_device *dev)
3677 {
3678         struct drm_i915_private *dev_priv = dev->dev_private;
3679         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3680         bool was_interruptible;
3681         int ret;
3682
3683         /* rc6 disabled by default due to repeated reports of hanging during
3684          * boot and resume.
3685          */
3686         if (!intel_enable_rc6(dev))
3687                 return;
3688
3689         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3690
3691         ret = ironlake_setup_rc6(dev);
3692         if (ret)
3693                 return;
3694
3695         was_interruptible = dev_priv->mm.interruptible;
3696         dev_priv->mm.interruptible = false;
3697
3698         /*
3699          * GPU can automatically power down the render unit if given a page
3700          * to save state.
3701          */
3702         ret = intel_ring_begin(ring, 6);
3703         if (ret) {
3704                 ironlake_teardown_rc6(dev);
3705                 dev_priv->mm.interruptible = was_interruptible;
3706                 return;
3707         }
3708
3709         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3710         intel_ring_emit(ring, MI_SET_CONTEXT);
3711         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3712                         MI_MM_SPACE_GTT |
3713                         MI_SAVE_EXT_STATE_EN |
3714                         MI_RESTORE_EXT_STATE_EN |
3715                         MI_RESTORE_INHIBIT);
3716         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3717         intel_ring_emit(ring, MI_NOOP);
3718         intel_ring_emit(ring, MI_FLUSH);
3719         intel_ring_advance(ring);
3720
3721         /*
3722          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3723          * does an implicit flush, combined with MI_FLUSH above, it should be
3724          * safe to assume that renderctx is valid
3725          */
3726         ret = intel_ring_idle(ring);
3727         dev_priv->mm.interruptible = was_interruptible;
3728         if (ret) {
3729                 DRM_ERROR("failed to enable ironlake power savings\n");
3730                 ironlake_teardown_rc6(dev);
3731                 return;
3732         }
3733
3734         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3735         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3736
3737         intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
3738 }
3739
3740 static unsigned long intel_pxfreq(u32 vidfreq)
3741 {
3742         unsigned long freq;
3743         int div = (vidfreq & 0x3f0000) >> 16;
3744         int post = (vidfreq & 0x3000) >> 12;
3745         int pre = (vidfreq & 0x7);
3746
3747         if (!pre)
3748                 return 0;
3749
3750         freq = ((div * 133333) / ((1<<post) * pre));
3751
3752         return freq;
3753 }
3754
3755 static const struct cparams {
3756         u16 i;
3757         u16 t;
3758         u16 m;
3759         u16 c;
3760 } cparams[] = {
3761         { 1, 1333, 301, 28664 },
3762         { 1, 1066, 294, 24460 },
3763         { 1, 800, 294, 25192 },
3764         { 0, 1333, 276, 27605 },
3765         { 0, 1066, 276, 27605 },
3766         { 0, 800, 231, 23784 },
3767 };
3768
3769 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3770 {
3771         u64 total_count, diff, ret;
3772         u32 count1, count2, count3, m = 0, c = 0;
3773         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3774         int i;
3775
3776         assert_spin_locked(&mchdev_lock);
3777
3778         diff1 = now - dev_priv->ips.last_time1;
3779
3780         /* Prevent division-by-zero if we are asking too fast.
3781          * Also, we don't get interesting results if we are polling
3782          * faster than once in 10ms, so just return the saved value
3783          * in such cases.
3784          */
3785         if (diff1 <= 10)
3786                 return dev_priv->ips.chipset_power;
3787
3788         count1 = I915_READ(DMIEC);
3789         count2 = I915_READ(DDREC);
3790         count3 = I915_READ(CSIEC);
3791
3792         total_count = count1 + count2 + count3;
3793
3794         /* FIXME: handle per-counter overflow */
3795         if (total_count < dev_priv->ips.last_count1) {
3796                 diff = ~0UL - dev_priv->ips.last_count1;
3797                 diff += total_count;
3798         } else {
3799                 diff = total_count - dev_priv->ips.last_count1;
3800         }
3801
3802         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3803                 if (cparams[i].i == dev_priv->ips.c_m &&
3804                     cparams[i].t == dev_priv->ips.r_t) {
3805                         m = cparams[i].m;
3806                         c = cparams[i].c;
3807                         break;
3808                 }
3809         }
3810
3811         diff = div_u64(diff, diff1);
3812         ret = ((m * diff) + c);
3813         ret = div_u64(ret, 10);
3814
3815         dev_priv->ips.last_count1 = total_count;
3816         dev_priv->ips.last_time1 = now;
3817
3818         dev_priv->ips.chipset_power = ret;
3819
3820         return ret;
3821 }
3822
3823 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3824 {
3825         unsigned long val;
3826
3827         if (dev_priv->info->gen != 5)
3828                 return 0;
3829
3830         spin_lock_irq(&mchdev_lock);
3831
3832         val = __i915_chipset_val(dev_priv);
3833
3834         spin_unlock_irq(&mchdev_lock);
3835
3836         return val;
3837 }
3838
3839 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3840 {
3841         unsigned long m, x, b;
3842         u32 tsfs;
3843
3844         tsfs = I915_READ(TSFS);
3845
3846         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3847         x = I915_READ8(TR1);
3848
3849         b = tsfs & TSFS_INTR_MASK;
3850
3851         return ((m * x) / 127) - b;
3852 }
3853
3854 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3855 {
3856         static const struct v_table {
3857                 u16 vd; /* in .1 mil */
3858                 u16 vm; /* in .1 mil */
3859         } v_table[] = {
3860                 { 0, 0, },
3861                 { 375, 0, },
3862                 { 500, 0, },
3863                 { 625, 0, },
3864                 { 750, 0, },
3865                 { 875, 0, },
3866                 { 1000, 0, },
3867                 { 1125, 0, },
3868                 { 4125, 3000, },
3869                 { 4125, 3000, },
3870                 { 4125, 3000, },
3871                 { 4125, 3000, },
3872                 { 4125, 3000, },
3873                 { 4125, 3000, },
3874                 { 4125, 3000, },
3875                 { 4125, 3000, },
3876                 { 4125, 3000, },
3877                 { 4125, 3000, },
3878                 { 4125, 3000, },
3879                 { 4125, 3000, },
3880                 { 4125, 3000, },
3881                 { 4125, 3000, },
3882                 { 4125, 3000, },
3883                 { 4125, 3000, },
3884                 { 4125, 3000, },
3885                 { 4125, 3000, },
3886                 { 4125, 3000, },
3887                 { 4125, 3000, },
3888                 { 4125, 3000, },
3889                 { 4125, 3000, },
3890                 { 4125, 3000, },
3891                 { 4125, 3000, },
3892                 { 4250, 3125, },
3893                 { 4375, 3250, },
3894                 { 4500, 3375, },
3895                 { 4625, 3500, },
3896                 { 4750, 3625, },
3897                 { 4875, 3750, },
3898                 { 5000, 3875, },
3899                 { 5125, 4000, },
3900                 { 5250, 4125, },
3901                 { 5375, 4250, },
3902                 { 5500, 4375, },
3903                 { 5625, 4500, },
3904                 { 5750, 4625, },
3905                 { 5875, 4750, },
3906                 { 6000, 4875, },
3907                 { 6125, 5000, },
3908                 { 6250, 5125, },
3909                 { 6375, 5250, },
3910                 { 6500, 5375, },
3911                 { 6625, 5500, },
3912                 { 6750, 5625, },
3913                 { 6875, 5750, },
3914                 { 7000, 5875, },
3915                 { 7125, 6000, },
3916                 { 7250, 6125, },
3917                 { 7375, 6250, },
3918                 { 7500, 6375, },
3919                 { 7625, 6500, },
3920                 { 7750, 6625, },
3921                 { 7875, 6750, },
3922                 { 8000, 6875, },
3923                 { 8125, 7000, },
3924                 { 8250, 7125, },
3925                 { 8375, 7250, },
3926                 { 8500, 7375, },
3927                 { 8625, 7500, },
3928                 { 8750, 7625, },
3929                 { 8875, 7750, },
3930                 { 9000, 7875, },
3931                 { 9125, 8000, },
3932                 { 9250, 8125, },
3933                 { 9375, 8250, },
3934                 { 9500, 8375, },
3935                 { 9625, 8500, },
3936                 { 9750, 8625, },
3937                 { 9875, 8750, },
3938                 { 10000, 8875, },
3939                 { 10125, 9000, },
3940                 { 10250, 9125, },
3941                 { 10375, 9250, },
3942                 { 10500, 9375, },
3943                 { 10625, 9500, },
3944                 { 10750, 9625, },
3945                 { 10875, 9750, },
3946                 { 11000, 9875, },
3947                 { 11125, 10000, },
3948                 { 11250, 10125, },
3949                 { 11375, 10250, },
3950                 { 11500, 10375, },
3951                 { 11625, 10500, },
3952                 { 11750, 10625, },
3953                 { 11875, 10750, },
3954                 { 12000, 10875, },
3955                 { 12125, 11000, },
3956                 { 12250, 11125, },
3957                 { 12375, 11250, },
3958                 { 12500, 11375, },
3959                 { 12625, 11500, },
3960                 { 12750, 11625, },
3961                 { 12875, 11750, },
3962                 { 13000, 11875, },
3963                 { 13125, 12000, },
3964                 { 13250, 12125, },
3965                 { 13375, 12250, },
3966                 { 13500, 12375, },
3967                 { 13625, 12500, },
3968                 { 13750, 12625, },
3969                 { 13875, 12750, },
3970                 { 14000, 12875, },
3971                 { 14125, 13000, },
3972                 { 14250, 13125, },
3973                 { 14375, 13250, },
3974                 { 14500, 13375, },
3975                 { 14625, 13500, },
3976                 { 14750, 13625, },
3977                 { 14875, 13750, },
3978                 { 15000, 13875, },
3979                 { 15125, 14000, },
3980                 { 15250, 14125, },
3981                 { 15375, 14250, },
3982                 { 15500, 14375, },
3983                 { 15625, 14500, },
3984                 { 15750, 14625, },
3985                 { 15875, 14750, },
3986                 { 16000, 14875, },
3987                 { 16125, 15000, },
3988         };
3989         if (dev_priv->info->is_mobile)
3990                 return v_table[pxvid].vm;
3991         else
3992                 return v_table[pxvid].vd;
3993 }
3994
3995 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3996 {
3997         struct timespec now, diff1;
3998         u64 diff;
3999         unsigned long diffms;
4000         u32 count;
4001
4002         assert_spin_locked(&mchdev_lock);
4003
4004         getrawmonotonic(&now);
4005         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4006
4007         /* Don't divide by 0 */
4008         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4009         if (!diffms)
4010                 return;
4011
4012         count = I915_READ(GFXEC);
4013
4014         if (count < dev_priv->ips.last_count2) {
4015                 diff = ~0UL - dev_priv->ips.last_count2;
4016                 diff += count;
4017         } else {
4018                 diff = count - dev_priv->ips.last_count2;
4019         }
4020
4021         dev_priv->ips.last_count2 = count;
4022         dev_priv->ips.last_time2 = now;
4023
4024         /* More magic constants... */
4025         diff = diff * 1181;
4026         diff = div_u64(diff, diffms * 10);
4027         dev_priv->ips.gfx_power = diff;
4028 }
4029
4030 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4031 {
4032         if (dev_priv->info->gen != 5)
4033                 return;
4034
4035         spin_lock_irq(&mchdev_lock);
4036
4037         __i915_update_gfx_val(dev_priv);
4038
4039         spin_unlock_irq(&mchdev_lock);
4040 }
4041
4042 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4043 {
4044         unsigned long t, corr, state1, corr2, state2;
4045         u32 pxvid, ext_v;
4046
4047         assert_spin_locked(&mchdev_lock);
4048
4049         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4050         pxvid = (pxvid >> 24) & 0x7f;
4051         ext_v = pvid_to_extvid(dev_priv, pxvid);
4052
4053         state1 = ext_v;
4054
4055         t = i915_mch_val(dev_priv);
4056
4057         /* Revel in the empirically derived constants */
4058
4059         /* Correction factor in 1/100000 units */
4060         if (t > 80)
4061                 corr = ((t * 2349) + 135940);
4062         else if (t >= 50)
4063                 corr = ((t * 964) + 29317);
4064         else /* < 50 */
4065                 corr = ((t * 301) + 1004);
4066
4067         corr = corr * ((150142 * state1) / 10000 - 78642);
4068         corr /= 100000;
4069         corr2 = (corr * dev_priv->ips.corr);
4070
4071         state2 = (corr2 * state1) / 10000;
4072         state2 /= 100; /* convert to mW */
4073
4074         __i915_update_gfx_val(dev_priv);
4075
4076         return dev_priv->ips.gfx_power + state2;
4077 }
4078
4079 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4080 {
4081         unsigned long val;
4082
4083         if (dev_priv->info->gen != 5)
4084                 return 0;
4085
4086         spin_lock_irq(&mchdev_lock);
4087
4088         val = __i915_gfx_val(dev_priv);
4089
4090         spin_unlock_irq(&mchdev_lock);
4091
4092         return val;
4093 }
4094
4095 /**
4096  * i915_read_mch_val - return value for IPS use
4097  *
4098  * Calculate and return a value for the IPS driver to use when deciding whether
4099  * we have thermal and power headroom to increase CPU or GPU power budget.
4100  */
4101 unsigned long i915_read_mch_val(void)
4102 {
4103         struct drm_i915_private *dev_priv;
4104         unsigned long chipset_val, graphics_val, ret = 0;
4105
4106         spin_lock_irq(&mchdev_lock);
4107         if (!i915_mch_dev)
4108                 goto out_unlock;
4109         dev_priv = i915_mch_dev;
4110
4111         chipset_val = __i915_chipset_val(dev_priv);
4112         graphics_val = __i915_gfx_val(dev_priv);
4113
4114         ret = chipset_val + graphics_val;
4115
4116 out_unlock:
4117         spin_unlock_irq(&mchdev_lock);
4118
4119         return ret;
4120 }
4121 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4122
4123 /**
4124  * i915_gpu_raise - raise GPU frequency limit
4125  *
4126  * Raise the limit; IPS indicates we have thermal headroom.
4127  */
4128 bool i915_gpu_raise(void)
4129 {
4130         struct drm_i915_private *dev_priv;
4131         bool ret = true;
4132
4133         spin_lock_irq(&mchdev_lock);
4134         if (!i915_mch_dev) {
4135                 ret = false;
4136                 goto out_unlock;
4137         }
4138         dev_priv = i915_mch_dev;
4139
4140         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4141                 dev_priv->ips.max_delay--;
4142
4143 out_unlock:
4144         spin_unlock_irq(&mchdev_lock);
4145
4146         return ret;
4147 }
4148 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4149
4150 /**
4151  * i915_gpu_lower - lower GPU frequency limit
4152  *
4153  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4154  * frequency maximum.
4155  */
4156 bool i915_gpu_lower(void)
4157 {
4158         struct drm_i915_private *dev_priv;
4159         bool ret = true;
4160
4161         spin_lock_irq(&mchdev_lock);
4162         if (!i915_mch_dev) {
4163                 ret = false;
4164                 goto out_unlock;
4165         }
4166         dev_priv = i915_mch_dev;
4167
4168         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4169                 dev_priv->ips.max_delay++;
4170
4171 out_unlock:
4172         spin_unlock_irq(&mchdev_lock);
4173
4174         return ret;
4175 }
4176 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4177
4178 /**
4179  * i915_gpu_busy - indicate GPU business to IPS
4180  *
4181  * Tell the IPS driver whether or not the GPU is busy.
4182  */
4183 bool i915_gpu_busy(void)
4184 {
4185         struct drm_i915_private *dev_priv;
4186         struct intel_ring_buffer *ring;
4187         bool ret = false;
4188         int i;
4189
4190         spin_lock_irq(&mchdev_lock);
4191         if (!i915_mch_dev)
4192                 goto out_unlock;
4193         dev_priv = i915_mch_dev;
4194
4195         for_each_ring(ring, dev_priv, i)
4196                 ret |= !list_empty(&ring->request_list);
4197
4198 out_unlock:
4199         spin_unlock_irq(&mchdev_lock);
4200
4201         return ret;
4202 }
4203 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4204
4205 /**
4206  * i915_gpu_turbo_disable - disable graphics turbo
4207  *
4208  * Disable graphics turbo by resetting the max frequency and setting the
4209  * current frequency to the default.
4210  */
4211 bool i915_gpu_turbo_disable(void)
4212 {
4213         struct drm_i915_private *dev_priv;
4214         bool ret = true;
4215
4216         spin_lock_irq(&mchdev_lock);
4217         if (!i915_mch_dev) {
4218                 ret = false;
4219                 goto out_unlock;
4220         }
4221         dev_priv = i915_mch_dev;
4222
4223         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4224
4225         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4226                 ret = false;
4227
4228 out_unlock:
4229         spin_unlock_irq(&mchdev_lock);
4230
4231         return ret;
4232 }
4233 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4234
4235 /**
4236  * Tells the intel_ips driver that the i915 driver is now loaded, if
4237  * IPS got loaded first.
4238  *
4239  * This awkward dance is so that neither module has to depend on the
4240  * other in order for IPS to do the appropriate communication of
4241  * GPU turbo limits to i915.
4242  */
4243 static void
4244 ips_ping_for_i915_load(void)
4245 {
4246         void (*link)(void);
4247
4248         link = symbol_get(ips_link_to_i915_driver);
4249         if (link) {
4250                 link();
4251                 symbol_put(ips_link_to_i915_driver);
4252         }
4253 }
4254
4255 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4256 {
4257         /* We only register the i915 ips part with intel-ips once everything is
4258          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4259         spin_lock_irq(&mchdev_lock);
4260         i915_mch_dev = dev_priv;
4261         spin_unlock_irq(&mchdev_lock);
4262
4263         ips_ping_for_i915_load();
4264 }
4265
4266 void intel_gpu_ips_teardown(void)
4267 {
4268         spin_lock_irq(&mchdev_lock);
4269         i915_mch_dev = NULL;
4270         spin_unlock_irq(&mchdev_lock);
4271 }
4272 static void intel_init_emon(struct drm_device *dev)
4273 {
4274         struct drm_i915_private *dev_priv = dev->dev_private;
4275         u32 lcfuse;
4276         u8 pxw[16];
4277         int i;
4278
4279         /* Disable to program */
4280         I915_WRITE(ECR, 0);
4281         POSTING_READ(ECR);
4282
4283         /* Program energy weights for various events */
4284         I915_WRITE(SDEW, 0x15040d00);
4285         I915_WRITE(CSIEW0, 0x007f0000);
4286         I915_WRITE(CSIEW1, 0x1e220004);
4287         I915_WRITE(CSIEW2, 0x04000004);
4288
4289         for (i = 0; i < 5; i++)
4290                 I915_WRITE(PEW + (i * 4), 0);
4291         for (i = 0; i < 3; i++)
4292                 I915_WRITE(DEW + (i * 4), 0);
4293
4294         /* Program P-state weights to account for frequency power adjustment */
4295         for (i = 0; i < 16; i++) {
4296                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4297                 unsigned long freq = intel_pxfreq(pxvidfreq);
4298                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4299                         PXVFREQ_PX_SHIFT;
4300                 unsigned long val;
4301
4302                 val = vid * vid;
4303                 val *= (freq / 1000);
4304                 val *= 255;
4305                 val /= (127*127*900);
4306                 if (val > 0xff)
4307                         DRM_ERROR("bad pxval: %ld\n", val);
4308                 pxw[i] = val;
4309         }
4310         /* Render standby states get 0 weight */
4311         pxw[14] = 0;
4312         pxw[15] = 0;
4313
4314         for (i = 0; i < 4; i++) {
4315                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4316                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4317                 I915_WRITE(PXW + (i * 4), val);
4318         }
4319
4320         /* Adjust magic regs to magic values (more experimental results) */
4321         I915_WRITE(OGW0, 0);
4322         I915_WRITE(OGW1, 0);
4323         I915_WRITE(EG0, 0x00007f00);
4324         I915_WRITE(EG1, 0x0000000e);
4325         I915_WRITE(EG2, 0x000e0000);
4326         I915_WRITE(EG3, 0x68000300);
4327         I915_WRITE(EG4, 0x42000000);
4328         I915_WRITE(EG5, 0x00140031);
4329         I915_WRITE(EG6, 0);
4330         I915_WRITE(EG7, 0);
4331
4332         for (i = 0; i < 8; i++)
4333                 I915_WRITE(PXWL + (i * 4), 0);
4334
4335         /* Enable PMON + select events */
4336         I915_WRITE(ECR, 0x80000019);
4337
4338         lcfuse = I915_READ(LCFUSE02);
4339
4340         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4341 }
4342
4343 void intel_disable_gt_powersave(struct drm_device *dev)
4344 {
4345         struct drm_i915_private *dev_priv = dev->dev_private;
4346
4347         /* Interrupts should be disabled already to avoid re-arming. */
4348         WARN_ON(dev->irq_enabled);
4349
4350         if (IS_IRONLAKE_M(dev)) {
4351                 ironlake_disable_drps(dev);
4352                 ironlake_disable_rc6(dev);
4353         } else if (INTEL_INFO(dev)->gen >= 6) {
4354                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4355                 cancel_work_sync(&dev_priv->rps.work);
4356                 mutex_lock(&dev_priv->rps.hw_lock);
4357                 if (IS_VALLEYVIEW(dev))
4358                         valleyview_disable_rps(dev);
4359                 else
4360                         gen6_disable_rps(dev);
4361                 dev_priv->rps.enabled = false;
4362                 mutex_unlock(&dev_priv->rps.hw_lock);
4363         }
4364 }
4365
4366 static void intel_gen6_powersave_work(struct work_struct *work)
4367 {
4368         struct drm_i915_private *dev_priv =
4369                 container_of(work, struct drm_i915_private,
4370                              rps.delayed_resume_work.work);
4371         struct drm_device *dev = dev_priv->dev;
4372
4373         mutex_lock(&dev_priv->rps.hw_lock);
4374
4375         if (IS_VALLEYVIEW(dev)) {
4376                 valleyview_enable_rps(dev);
4377         } else if (IS_BROADWELL(dev)) {
4378                 gen8_enable_rps(dev);
4379                 gen6_update_ring_freq(dev);
4380         } else {
4381                 gen6_enable_rps(dev);
4382                 gen6_update_ring_freq(dev);
4383         }
4384         dev_priv->rps.enabled = true;
4385         mutex_unlock(&dev_priv->rps.hw_lock);
4386 }
4387
4388 void intel_enable_gt_powersave(struct drm_device *dev)
4389 {
4390         struct drm_i915_private *dev_priv = dev->dev_private;
4391
4392         if (IS_IRONLAKE_M(dev)) {
4393                 ironlake_enable_drps(dev);
4394                 ironlake_enable_rc6(dev);
4395                 intel_init_emon(dev);
4396         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4397                 /*
4398                  * PCU communication is slow and this doesn't need to be
4399                  * done at any specific time, so do this out of our fast path
4400                  * to make resume and init faster.
4401                  */
4402                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4403                                       round_jiffies_up_relative(HZ));
4404         }
4405 }
4406
4407 static void ibx_init_clock_gating(struct drm_device *dev)
4408 {
4409         struct drm_i915_private *dev_priv = dev->dev_private;
4410
4411         /*
4412          * On Ibex Peak and Cougar Point, we need to disable clock
4413          * gating for the panel power sequencer or it will fail to
4414          * start up when no ports are active.
4415          */
4416         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4417 }
4418
4419 static void g4x_disable_trickle_feed(struct drm_device *dev)
4420 {
4421         struct drm_i915_private *dev_priv = dev->dev_private;
4422         int pipe;
4423
4424         for_each_pipe(pipe) {
4425                 I915_WRITE(DSPCNTR(pipe),
4426                            I915_READ(DSPCNTR(pipe)) |
4427                            DISPPLANE_TRICKLE_FEED_DISABLE);
4428                 intel_flush_primary_plane(dev_priv, pipe);
4429         }
4430 }
4431
4432 static void ilk_init_lp_watermarks(struct drm_device *dev)
4433 {
4434         struct drm_i915_private *dev_priv = dev->dev_private;
4435
4436         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4437         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4438         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4439
4440         /*
4441          * Don't touch WM1S_LP_EN here.
4442          * Doing so could cause underruns.
4443          */
4444 }
4445
4446 static void ironlake_init_clock_gating(struct drm_device *dev)
4447 {
4448         struct drm_i915_private *dev_priv = dev->dev_private;
4449         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4450
4451         /*
4452          * Required for FBC
4453          * WaFbcDisableDpfcClockGating:ilk
4454          */
4455         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4456                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4457                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4458
4459         I915_WRITE(PCH_3DCGDIS0,
4460                    MARIUNIT_CLOCK_GATE_DISABLE |
4461                    SVSMUNIT_CLOCK_GATE_DISABLE);
4462         I915_WRITE(PCH_3DCGDIS1,
4463                    VFMUNIT_CLOCK_GATE_DISABLE);
4464
4465         /*
4466          * According to the spec the following bits should be set in
4467          * order to enable memory self-refresh
4468          * The bit 22/21 of 0x42004
4469          * The bit 5 of 0x42020
4470          * The bit 15 of 0x45000
4471          */
4472         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4473                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4474                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4475         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4476         I915_WRITE(DISP_ARB_CTL,
4477                    (I915_READ(DISP_ARB_CTL) |
4478                     DISP_FBC_WM_DIS));
4479
4480         ilk_init_lp_watermarks(dev);
4481
4482         /*
4483          * Based on the document from hardware guys the following bits
4484          * should be set unconditionally in order to enable FBC.
4485          * The bit 22 of 0x42000
4486          * The bit 22 of 0x42004
4487          * The bit 7,8,9 of 0x42020.
4488          */
4489         if (IS_IRONLAKE_M(dev)) {
4490                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4491                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4492                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4493                            ILK_FBCQ_DIS);
4494                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4495                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4496                            ILK_DPARB_GATE);
4497         }
4498
4499         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4500
4501         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4502                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4503                    ILK_ELPIN_409_SELECT);
4504         I915_WRITE(_3D_CHICKEN2,
4505                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4506                    _3D_CHICKEN2_WM_READ_PIPELINED);
4507
4508         /* WaDisableRenderCachePipelinedFlush:ilk */
4509         I915_WRITE(CACHE_MODE_0,
4510                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4511
4512         g4x_disable_trickle_feed(dev);
4513
4514         ibx_init_clock_gating(dev);
4515 }
4516
4517 static void cpt_init_clock_gating(struct drm_device *dev)
4518 {
4519         struct drm_i915_private *dev_priv = dev->dev_private;
4520         int pipe;
4521         uint32_t val;
4522
4523         /*
4524          * On Ibex Peak and Cougar Point, we need to disable clock
4525          * gating for the panel power sequencer or it will fail to
4526          * start up when no ports are active.
4527          */
4528         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4529                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4530                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
4531         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4532                    DPLS_EDP_PPS_FIX_DIS);
4533         /* The below fixes the weird display corruption, a few pixels shifted
4534          * downward, on (only) LVDS of some HP laptops with IVY.
4535          */
4536         for_each_pipe(pipe) {
4537                 val = I915_READ(TRANS_CHICKEN2(pipe));
4538                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4539                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4540                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4541                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4542                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4543                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4544                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4545                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4546         }
4547         /* WADP0ClockGatingDisable */
4548         for_each_pipe(pipe) {
4549                 I915_WRITE(TRANS_CHICKEN1(pipe),
4550                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4551         }
4552 }
4553
4554 static void gen6_check_mch_setup(struct drm_device *dev)
4555 {
4556         struct drm_i915_private *dev_priv = dev->dev_private;
4557         uint32_t tmp;
4558
4559         tmp = I915_READ(MCH_SSKPD);
4560         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4561                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4562                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4563                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4564         }
4565 }
4566
4567 static void gen6_init_clock_gating(struct drm_device *dev)
4568 {
4569         struct drm_i915_private *dev_priv = dev->dev_private;
4570         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4571
4572         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4573
4574         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4575                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4576                    ILK_ELPIN_409_SELECT);
4577
4578         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4579         I915_WRITE(_3D_CHICKEN,
4580                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4581
4582         /* WaSetupGtModeTdRowDispatch:snb */
4583         if (IS_SNB_GT1(dev))
4584                 I915_WRITE(GEN6_GT_MODE,
4585                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4586
4587         ilk_init_lp_watermarks(dev);
4588
4589         I915_WRITE(CACHE_MODE_0,
4590                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4591
4592         I915_WRITE(GEN6_UCGCTL1,
4593                    I915_READ(GEN6_UCGCTL1) |
4594                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4595                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4596
4597         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4598          * gating disable must be set.  Failure to set it results in
4599          * flickering pixels due to Z write ordering failures after
4600          * some amount of runtime in the Mesa "fire" demo, and Unigine
4601          * Sanctuary and Tropics, and apparently anything else with
4602          * alpha test or pixel discard.
4603          *
4604          * According to the spec, bit 11 (RCCUNIT) must also be set,
4605          * but we didn't debug actual testcases to find it out.
4606          *
4607          * Also apply WaDisableVDSUnitClockGating:snb and
4608          * WaDisableRCPBUnitClockGating:snb.
4609          */
4610         I915_WRITE(GEN6_UCGCTL2,
4611                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4612                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4613                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4614
4615         /* Bspec says we need to always set all mask bits. */
4616         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4617                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4618
4619         /*
4620          * According to the spec the following bits should be
4621          * set in order to enable memory self-refresh and fbc:
4622          * The bit21 and bit22 of 0x42000
4623          * The bit21 and bit22 of 0x42004
4624          * The bit5 and bit7 of 0x42020
4625          * The bit14 of 0x70180
4626          * The bit14 of 0x71180
4627          *
4628          * WaFbcAsynchFlipDisableFbcQueue:snb
4629          */
4630         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4631                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4632                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4633         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4634                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4635                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4636         I915_WRITE(ILK_DSPCLK_GATE_D,
4637                    I915_READ(ILK_DSPCLK_GATE_D) |
4638                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4639                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4640
4641         g4x_disable_trickle_feed(dev);
4642
4643         /* The default value should be 0x200 according to docs, but the two
4644          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4645         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4646         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4647
4648         cpt_init_clock_gating(dev);
4649
4650         gen6_check_mch_setup(dev);
4651 }
4652
4653 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4654 {
4655         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4656
4657         reg &= ~GEN7_FF_SCHED_MASK;
4658         reg |= GEN7_FF_TS_SCHED_HW;
4659         reg |= GEN7_FF_VS_SCHED_HW;
4660         reg |= GEN7_FF_DS_SCHED_HW;
4661
4662         if (IS_HASWELL(dev_priv->dev))
4663                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4664
4665         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4666 }
4667
4668 static void lpt_init_clock_gating(struct drm_device *dev)
4669 {
4670         struct drm_i915_private *dev_priv = dev->dev_private;
4671
4672         /*
4673          * TODO: this bit should only be enabled when really needed, then
4674          * disabled when not needed anymore in order to save power.
4675          */
4676         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4677                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4678                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4679                            PCH_LP_PARTITION_LEVEL_DISABLE);
4680
4681         /* WADPOClockGatingDisable:hsw */
4682         I915_WRITE(_TRANSA_CHICKEN1,
4683                    I915_READ(_TRANSA_CHICKEN1) |
4684                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4685 }
4686
4687 static void lpt_suspend_hw(struct drm_device *dev)
4688 {
4689         struct drm_i915_private *dev_priv = dev->dev_private;
4690
4691         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4692                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4693
4694                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4695                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4696         }
4697 }
4698
4699 static void gen8_init_clock_gating(struct drm_device *dev)
4700 {
4701         struct drm_i915_private *dev_priv = dev->dev_private;
4702         enum pipe i;
4703
4704         I915_WRITE(WM3_LP_ILK, 0);
4705         I915_WRITE(WM2_LP_ILK, 0);
4706         I915_WRITE(WM1_LP_ILK, 0);
4707
4708         /* FIXME(BDW): Check all the w/a, some might only apply to
4709          * pre-production hw. */
4710
4711         WARN(!i915_preliminary_hw_support,
4712              "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
4713         I915_WRITE(HALF_SLICE_CHICKEN3,
4714                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
4715         I915_WRITE(HALF_SLICE_CHICKEN3,
4716                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4717         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4718
4719         I915_WRITE(_3D_CHICKEN3,
4720                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4721
4722         I915_WRITE(COMMON_SLICE_CHICKEN2,
4723                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4724
4725         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4726                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4727
4728         /* WaSwitchSolVfFArbitrationPriority:bdw */
4729         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4730
4731         /* WaPsrDPAMaskVBlankInSRD:bdw */
4732         I915_WRITE(CHICKEN_PAR1_1,
4733                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4734
4735         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
4736         for_each_pipe(i) {
4737                 I915_WRITE(CHICKEN_PIPESL_1(i),
4738                            I915_READ(CHICKEN_PIPESL_1(i) |
4739                                      DPRS_MASK_VBLANK_SRD));
4740         }
4741
4742         /* Use Force Non-Coherent whenever executing a 3D context. This is a
4743          * workaround for for a possible hang in the unlikely event a TLB
4744          * invalidation occurs during a PSD flush.
4745          */
4746         I915_WRITE(HDC_CHICKEN0,
4747                    I915_READ(HDC_CHICKEN0) |
4748                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
4749
4750         /* WaVSRefCountFullforceMissDisable:bdw */
4751         /* WaDSRefCountFullforceMissDisable:bdw */
4752         I915_WRITE(GEN7_FF_THREAD_MODE,
4753                    I915_READ(GEN7_FF_THREAD_MODE) &
4754                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
4755 }
4756
4757 static void haswell_init_clock_gating(struct drm_device *dev)
4758 {
4759         struct drm_i915_private *dev_priv = dev->dev_private;
4760
4761         ilk_init_lp_watermarks(dev);
4762
4763         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4764          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4765          */
4766         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4767
4768         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4769         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4770                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4771
4772         /* WaApplyL3ControlAndL3ChickenMode:hsw */
4773         I915_WRITE(GEN7_L3CNTLREG1,
4774                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4775         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4776                         GEN7_WA_L3_CHICKEN_MODE);
4777
4778         /* L3 caching of data atomics doesn't work -- disable it. */
4779         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4780         I915_WRITE(HSW_ROW_CHICKEN3,
4781                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4782
4783         /* This is required by WaCatErrorRejectionIssue:hsw */
4784         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4785                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4786                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4787
4788         /* WaVSRefCountFullforceMissDisable:hsw */
4789         gen7_setup_fixed_func_scheduler(dev_priv);
4790
4791         /* WaDisable4x2SubspanOptimization:hsw */
4792         I915_WRITE(CACHE_MODE_1,
4793                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4794
4795         /* WaSwitchSolVfFArbitrationPriority:hsw */
4796         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4797
4798         /* WaRsPkgCStateDisplayPMReq:hsw */
4799         I915_WRITE(CHICKEN_PAR1_1,
4800                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4801
4802         lpt_init_clock_gating(dev);
4803 }
4804
4805 static void ivybridge_init_clock_gating(struct drm_device *dev)
4806 {
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         uint32_t snpcr;
4809
4810         ilk_init_lp_watermarks(dev);
4811
4812         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4813
4814         /* WaDisableEarlyCull:ivb */
4815         I915_WRITE(_3D_CHICKEN3,
4816                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4817
4818         /* WaDisableBackToBackFlipFix:ivb */
4819         I915_WRITE(IVB_CHICKEN3,
4820                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4821                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4822
4823         /* WaDisablePSDDualDispatchEnable:ivb */
4824         if (IS_IVB_GT1(dev))
4825                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4826                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4827         else
4828                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4829                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4830
4831         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4832         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4833                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4834
4835         /* WaApplyL3ControlAndL3ChickenMode:ivb */
4836         I915_WRITE(GEN7_L3CNTLREG1,
4837                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4838         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4839                    GEN7_WA_L3_CHICKEN_MODE);
4840         if (IS_IVB_GT1(dev))
4841                 I915_WRITE(GEN7_ROW_CHICKEN2,
4842                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4843         else
4844                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4845                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4846
4847
4848         /* WaForceL3Serialization:ivb */
4849         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4850                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4851
4852         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4853          * gating disable must be set.  Failure to set it results in
4854          * flickering pixels due to Z write ordering failures after
4855          * some amount of runtime in the Mesa "fire" demo, and Unigine
4856          * Sanctuary and Tropics, and apparently anything else with
4857          * alpha test or pixel discard.
4858          *
4859          * According to the spec, bit 11 (RCCUNIT) must also be set,
4860          * but we didn't debug actual testcases to find it out.
4861          *
4862          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4863          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4864          */
4865         I915_WRITE(GEN6_UCGCTL2,
4866                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4867                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4868
4869         /* This is required by WaCatErrorRejectionIssue:ivb */
4870         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4871                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4872                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4873
4874         g4x_disable_trickle_feed(dev);
4875
4876         /* WaVSRefCountFullforceMissDisable:ivb */
4877         gen7_setup_fixed_func_scheduler(dev_priv);
4878
4879         /* WaDisable4x2SubspanOptimization:ivb */
4880         I915_WRITE(CACHE_MODE_1,
4881                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4882
4883         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4884         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4885         snpcr |= GEN6_MBC_SNPCR_MED;
4886         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4887
4888         if (!HAS_PCH_NOP(dev))
4889                 cpt_init_clock_gating(dev);
4890
4891         gen6_check_mch_setup(dev);
4892 }
4893
4894 static void valleyview_init_clock_gating(struct drm_device *dev)
4895 {
4896         struct drm_i915_private *dev_priv = dev->dev_private;
4897         u32 val;
4898
4899         mutex_lock(&dev_priv->rps.hw_lock);
4900         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4901         mutex_unlock(&dev_priv->rps.hw_lock);
4902         switch ((val >> 6) & 3) {
4903         case 0:
4904                 dev_priv->mem_freq = 800;
4905                 break;
4906         case 1:
4907                 dev_priv->mem_freq = 1066;
4908                 break;
4909         case 2:
4910                 dev_priv->mem_freq = 1333;
4911                 break;
4912         case 3:
4913                 dev_priv->mem_freq = 1333;
4914                 break;
4915         }
4916         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4917
4918         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
4919
4920         /* WaDisableEarlyCull:vlv */
4921         I915_WRITE(_3D_CHICKEN3,
4922                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4923
4924         /* WaDisableBackToBackFlipFix:vlv */
4925         I915_WRITE(IVB_CHICKEN3,
4926                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4927                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4928
4929         /* WaDisablePSDDualDispatchEnable:vlv */
4930         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4931                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4932                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4933
4934         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4935         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4936                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4937
4938         /* WaApplyL3ControlAndL3ChickenMode:vlv */
4939         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4940         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4941
4942         /* WaForceL3Serialization:vlv */
4943         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4944                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4945
4946         /* WaDisableDopClockGating:vlv */
4947         I915_WRITE(GEN7_ROW_CHICKEN2,
4948                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4949
4950         /* This is required by WaCatErrorRejectionIssue:vlv */
4951         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4952                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4953                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4954
4955         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4956          * gating disable must be set.  Failure to set it results in
4957          * flickering pixels due to Z write ordering failures after
4958          * some amount of runtime in the Mesa "fire" demo, and Unigine
4959          * Sanctuary and Tropics, and apparently anything else with
4960          * alpha test or pixel discard.
4961          *
4962          * According to the spec, bit 11 (RCCUNIT) must also be set,
4963          * but we didn't debug actual testcases to find it out.
4964          *
4965          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4966          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4967          *
4968          * Also apply WaDisableVDSUnitClockGating:vlv and
4969          * WaDisableRCPBUnitClockGating:vlv.
4970          */
4971         I915_WRITE(GEN6_UCGCTL2,
4972                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4973                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4974                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4975                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4976                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4977
4978         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4979
4980         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
4981
4982         I915_WRITE(CACHE_MODE_1,
4983                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4984
4985         /*
4986          * WaDisableVLVClockGating_VBIIssue:vlv
4987          * Disable clock gating on th GCFG unit to prevent a delay
4988          * in the reporting of vblank events.
4989          */
4990         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4991
4992         /* Conservative clock gating settings for now */
4993         I915_WRITE(0x9400, 0xffffffff);
4994         I915_WRITE(0x9404, 0xffffffff);
4995         I915_WRITE(0x9408, 0xffffffff);
4996         I915_WRITE(0x940c, 0xffffffff);
4997         I915_WRITE(0x9410, 0xffffffff);
4998         I915_WRITE(0x9414, 0xffffffff);
4999         I915_WRITE(0x9418, 0xffffffff);
5000 }
5001
5002 static void g4x_init_clock_gating(struct drm_device *dev)
5003 {
5004         struct drm_i915_private *dev_priv = dev->dev_private;
5005         uint32_t dspclk_gate;
5006
5007         I915_WRITE(RENCLK_GATE_D1, 0);
5008         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5009                    GS_UNIT_CLOCK_GATE_DISABLE |
5010                    CL_UNIT_CLOCK_GATE_DISABLE);
5011         I915_WRITE(RAMCLK_GATE_D, 0);
5012         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5013                 OVRUNIT_CLOCK_GATE_DISABLE |
5014                 OVCUNIT_CLOCK_GATE_DISABLE;
5015         if (IS_GM45(dev))
5016                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5017         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5018
5019         /* WaDisableRenderCachePipelinedFlush */
5020         I915_WRITE(CACHE_MODE_0,
5021                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5022
5023         g4x_disable_trickle_feed(dev);
5024 }
5025
5026 static void crestline_init_clock_gating(struct drm_device *dev)
5027 {
5028         struct drm_i915_private *dev_priv = dev->dev_private;
5029
5030         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5031         I915_WRITE(RENCLK_GATE_D2, 0);
5032         I915_WRITE(DSPCLK_GATE_D, 0);
5033         I915_WRITE(RAMCLK_GATE_D, 0);
5034         I915_WRITE16(DEUC, 0);
5035         I915_WRITE(MI_ARB_STATE,
5036                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5037 }
5038
5039 static void broadwater_init_clock_gating(struct drm_device *dev)
5040 {
5041         struct drm_i915_private *dev_priv = dev->dev_private;
5042
5043         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5044                    I965_RCC_CLOCK_GATE_DISABLE |
5045                    I965_RCPB_CLOCK_GATE_DISABLE |
5046                    I965_ISC_CLOCK_GATE_DISABLE |
5047                    I965_FBC_CLOCK_GATE_DISABLE);
5048         I915_WRITE(RENCLK_GATE_D2, 0);
5049         I915_WRITE(MI_ARB_STATE,
5050                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5051 }
5052
5053 static void gen3_init_clock_gating(struct drm_device *dev)
5054 {
5055         struct drm_i915_private *dev_priv = dev->dev_private;
5056         u32 dstate = I915_READ(D_STATE);
5057
5058         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5059                 DSTATE_DOT_CLOCK_GATING;
5060         I915_WRITE(D_STATE, dstate);
5061
5062         if (IS_PINEVIEW(dev))
5063                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5064
5065         /* IIR "flip pending" means done if this bit is set */
5066         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5067 }
5068
5069 static void i85x_init_clock_gating(struct drm_device *dev)
5070 {
5071         struct drm_i915_private *dev_priv = dev->dev_private;
5072
5073         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5074 }
5075
5076 static void i830_init_clock_gating(struct drm_device *dev)
5077 {
5078         struct drm_i915_private *dev_priv = dev->dev_private;
5079
5080         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5081 }
5082
5083 void intel_init_clock_gating(struct drm_device *dev)
5084 {
5085         struct drm_i915_private *dev_priv = dev->dev_private;
5086
5087         dev_priv->display.init_clock_gating(dev);
5088 }
5089
5090 void intel_suspend_hw(struct drm_device *dev)
5091 {
5092         if (HAS_PCH_LPT(dev))
5093                 lpt_suspend_hw(dev);
5094 }
5095
5096 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5097         for (i = 0;                                                     \
5098              i < (power_domains)->power_well_count &&                   \
5099                  ((power_well) = &(power_domains)->power_wells[i]);     \
5100              i++)                                                       \
5101                 if ((power_well)->domains & (domain_mask))
5102
5103 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5104         for (i = (power_domains)->power_well_count - 1;                  \
5105              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5106              i--)                                                        \
5107                 if ((power_well)->domains & (domain_mask))
5108
5109 /**
5110  * We should only use the power well if we explicitly asked the hardware to
5111  * enable it, so check if it's enabled and also check if we've requested it to
5112  * be enabled.
5113  */
5114 static bool hsw_power_well_enabled(struct drm_device *dev,
5115                                    struct i915_power_well *power_well)
5116 {
5117         struct drm_i915_private *dev_priv = dev->dev_private;
5118
5119         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5120                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5121 }
5122
5123 bool intel_display_power_enabled_sw(struct drm_device *dev,
5124                                     enum intel_display_power_domain domain)
5125 {
5126         struct drm_i915_private *dev_priv = dev->dev_private;
5127         struct i915_power_domains *power_domains;
5128
5129         power_domains = &dev_priv->power_domains;
5130
5131         return power_domains->domain_use_count[domain];
5132 }
5133
5134 bool intel_display_power_enabled(struct drm_device *dev,
5135                                  enum intel_display_power_domain domain)
5136 {
5137         struct drm_i915_private *dev_priv = dev->dev_private;
5138         struct i915_power_domains *power_domains;
5139         struct i915_power_well *power_well;
5140         bool is_enabled;
5141         int i;
5142
5143         power_domains = &dev_priv->power_domains;
5144
5145         is_enabled = true;
5146
5147         mutex_lock(&power_domains->lock);
5148         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5149                 if (power_well->always_on)
5150                         continue;
5151
5152                 if (!power_well->is_enabled(dev, power_well)) {
5153                         is_enabled = false;
5154                         break;
5155                 }
5156         }
5157         mutex_unlock(&power_domains->lock);
5158
5159         return is_enabled;
5160 }
5161
5162 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5163 {
5164         struct drm_device *dev = dev_priv->dev;
5165         unsigned long irqflags;
5166
5167         /*
5168          * After we re-enable the power well, if we touch VGA register 0x3d5
5169          * we'll get unclaimed register interrupts. This stops after we write
5170          * anything to the VGA MSR register. The vgacon module uses this
5171          * register all the time, so if we unbind our driver and, as a
5172          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5173          * console_unlock(). So make here we touch the VGA MSR register, making
5174          * sure vgacon can keep working normally without triggering interrupts
5175          * and error messages.
5176          */
5177         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5178         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5179         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5180
5181         if (IS_BROADWELL(dev)) {
5182                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5183                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5184                            dev_priv->de_irq_mask[PIPE_B]);
5185                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5186                            ~dev_priv->de_irq_mask[PIPE_B] |
5187                            GEN8_PIPE_VBLANK);
5188                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5189                            dev_priv->de_irq_mask[PIPE_C]);
5190                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5191                            ~dev_priv->de_irq_mask[PIPE_C] |
5192                            GEN8_PIPE_VBLANK);
5193                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5194                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5195         }
5196 }
5197
5198 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5199 {
5200         struct drm_device *dev = dev_priv->dev;
5201         enum pipe p;
5202         unsigned long irqflags;
5203
5204         /*
5205          * After this, the registers on the pipes that are part of the power
5206          * well will become zero, so we have to adjust our counters according to
5207          * that.
5208          *
5209          * FIXME: Should we do this in general in drm_vblank_post_modeset?
5210          */
5211         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5212         for_each_pipe(p)
5213                 if (p != PIPE_A)
5214                         dev->vblank[p].last = 0;
5215         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5216 }
5217
5218 static void hsw_set_power_well(struct drm_device *dev,
5219                                struct i915_power_well *power_well, bool enable)
5220 {
5221         struct drm_i915_private *dev_priv = dev->dev_private;
5222         bool is_enabled, enable_requested;
5223         uint32_t tmp;
5224
5225         WARN_ON(dev_priv->pc8.enabled);
5226
5227         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5228         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5229         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5230
5231         if (enable) {
5232                 if (!enable_requested)
5233                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5234                                    HSW_PWR_WELL_ENABLE_REQUEST);
5235
5236                 if (!is_enabled) {
5237                         DRM_DEBUG_KMS("Enabling power well\n");
5238                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5239                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5240                                 DRM_ERROR("Timeout enabling power well\n");
5241                 }
5242
5243                 hsw_power_well_post_enable(dev_priv);
5244         } else {
5245                 if (enable_requested) {
5246                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5247                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5248                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5249
5250                         hsw_power_well_post_disable(dev_priv);
5251                 }
5252         }
5253 }
5254
5255 static void __intel_power_well_get(struct drm_device *dev,
5256                                    struct i915_power_well *power_well)
5257 {
5258         struct drm_i915_private *dev_priv = dev->dev_private;
5259
5260         if (!power_well->count++ && power_well->set) {
5261                 hsw_disable_package_c8(dev_priv);
5262                 power_well->set(dev, power_well, true);
5263         }
5264 }
5265
5266 static void __intel_power_well_put(struct drm_device *dev,
5267                                    struct i915_power_well *power_well)
5268 {
5269         struct drm_i915_private *dev_priv = dev->dev_private;
5270
5271         WARN_ON(!power_well->count);
5272
5273         if (!--power_well->count && power_well->set &&
5274             i915_disable_power_well) {
5275                 power_well->set(dev, power_well, false);
5276                 hsw_enable_package_c8(dev_priv);
5277         }
5278 }
5279
5280 void intel_display_power_get(struct drm_device *dev,
5281                              enum intel_display_power_domain domain)
5282 {
5283         struct drm_i915_private *dev_priv = dev->dev_private;
5284         struct i915_power_domains *power_domains;
5285         struct i915_power_well *power_well;
5286         int i;
5287
5288         power_domains = &dev_priv->power_domains;
5289
5290         mutex_lock(&power_domains->lock);
5291
5292         for_each_power_well(i, power_well, BIT(domain), power_domains)
5293                 __intel_power_well_get(dev, power_well);
5294
5295         power_domains->domain_use_count[domain]++;
5296
5297         mutex_unlock(&power_domains->lock);
5298 }
5299
5300 void intel_display_power_put(struct drm_device *dev,
5301                              enum intel_display_power_domain domain)
5302 {
5303         struct drm_i915_private *dev_priv = dev->dev_private;
5304         struct i915_power_domains *power_domains;
5305         struct i915_power_well *power_well;
5306         int i;
5307
5308         power_domains = &dev_priv->power_domains;
5309
5310         mutex_lock(&power_domains->lock);
5311
5312         WARN_ON(!power_domains->domain_use_count[domain]);
5313         power_domains->domain_use_count[domain]--;
5314
5315         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5316                 __intel_power_well_put(dev, power_well);
5317
5318         mutex_unlock(&power_domains->lock);
5319 }
5320
5321 static struct i915_power_domains *hsw_pwr;
5322
5323 /* Display audio driver power well request */
5324 void i915_request_power_well(void)
5325 {
5326         struct drm_i915_private *dev_priv;
5327
5328         if (WARN_ON(!hsw_pwr))
5329                 return;
5330
5331         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5332                                 power_domains);
5333         intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5334 }
5335 EXPORT_SYMBOL_GPL(i915_request_power_well);
5336
5337 /* Display audio driver power well release */
5338 void i915_release_power_well(void)
5339 {
5340         struct drm_i915_private *dev_priv;
5341
5342         if (WARN_ON(!hsw_pwr))
5343                 return;
5344
5345         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5346                                 power_domains);
5347         intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5348 }
5349 EXPORT_SYMBOL_GPL(i915_release_power_well);
5350
5351 static struct i915_power_well i9xx_always_on_power_well[] = {
5352         {
5353                 .name = "always-on",
5354                 .always_on = 1,
5355                 .domains = POWER_DOMAIN_MASK,
5356         },
5357 };
5358
5359 static struct i915_power_well hsw_power_wells[] = {
5360         {
5361                 .name = "always-on",
5362                 .always_on = 1,
5363                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5364         },
5365         {
5366                 .name = "display",
5367                 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5368                 .is_enabled = hsw_power_well_enabled,
5369                 .set = hsw_set_power_well,
5370         },
5371 };
5372
5373 static struct i915_power_well bdw_power_wells[] = {
5374         {
5375                 .name = "always-on",
5376                 .always_on = 1,
5377                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5378         },
5379         {
5380                 .name = "display",
5381                 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5382                 .is_enabled = hsw_power_well_enabled,
5383                 .set = hsw_set_power_well,
5384         },
5385 };
5386
5387 #define set_power_wells(power_domains, __power_wells) ({                \
5388         (power_domains)->power_wells = (__power_wells);                 \
5389         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
5390 })
5391
5392 int intel_power_domains_init(struct drm_device *dev)
5393 {
5394         struct drm_i915_private *dev_priv = dev->dev_private;
5395         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5396
5397         mutex_init(&power_domains->lock);
5398
5399         /*
5400          * The enabling order will be from lower to higher indexed wells,
5401          * the disabling order is reversed.
5402          */
5403         if (IS_HASWELL(dev)) {
5404                 set_power_wells(power_domains, hsw_power_wells);
5405                 hsw_pwr = power_domains;
5406         } else if (IS_BROADWELL(dev)) {
5407                 set_power_wells(power_domains, bdw_power_wells);
5408                 hsw_pwr = power_domains;
5409         } else {
5410                 set_power_wells(power_domains, i9xx_always_on_power_well);
5411         }
5412
5413         return 0;
5414 }
5415
5416 void intel_power_domains_remove(struct drm_device *dev)
5417 {
5418         hsw_pwr = NULL;
5419 }
5420
5421 static void intel_power_domains_resume(struct drm_device *dev)
5422 {
5423         struct drm_i915_private *dev_priv = dev->dev_private;
5424         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5425         struct i915_power_well *power_well;
5426         int i;
5427
5428         mutex_lock(&power_domains->lock);
5429         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5430                 if (power_well->set)
5431                         power_well->set(dev, power_well, power_well->count > 0);
5432         }
5433         mutex_unlock(&power_domains->lock);
5434 }
5435
5436 /*
5437  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5438  * when not needed anymore. We have 4 registers that can request the power well
5439  * to be enabled, and it will only be disabled if none of the registers is
5440  * requesting it to be enabled.
5441  */
5442 void intel_power_domains_init_hw(struct drm_device *dev)
5443 {
5444         struct drm_i915_private *dev_priv = dev->dev_private;
5445
5446         /* For now, we need the power well to be always enabled. */
5447         intel_display_set_init_power(dev, true);
5448         intel_power_domains_resume(dev);
5449
5450         if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5451                 return;
5452
5453         /* We're taking over the BIOS, so clear any requests made by it since
5454          * the driver is in charge now. */
5455         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5456                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5457 }
5458
5459 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5460 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5461 {
5462         hsw_disable_package_c8(dev_priv);
5463 }
5464
5465 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5466 {
5467         hsw_enable_package_c8(dev_priv);
5468 }
5469
5470 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5471 {
5472         struct drm_device *dev = dev_priv->dev;
5473         struct device *device = &dev->pdev->dev;
5474
5475         if (!HAS_RUNTIME_PM(dev))
5476                 return;
5477
5478         pm_runtime_get_sync(device);
5479         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5480 }
5481
5482 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5483 {
5484         struct drm_device *dev = dev_priv->dev;
5485         struct device *device = &dev->pdev->dev;
5486
5487         if (!HAS_RUNTIME_PM(dev))
5488                 return;
5489
5490         pm_runtime_mark_last_busy(device);
5491         pm_runtime_put_autosuspend(device);
5492 }
5493
5494 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5495 {
5496         struct drm_device *dev = dev_priv->dev;
5497         struct device *device = &dev->pdev->dev;
5498
5499         dev_priv->pm.suspended = false;
5500
5501         if (!HAS_RUNTIME_PM(dev))
5502                 return;
5503
5504         pm_runtime_set_active(device);
5505
5506         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5507         pm_runtime_mark_last_busy(device);
5508         pm_runtime_use_autosuspend(device);
5509 }
5510
5511 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
5512 {
5513         struct drm_device *dev = dev_priv->dev;
5514         struct device *device = &dev->pdev->dev;
5515
5516         if (!HAS_RUNTIME_PM(dev))
5517                 return;
5518
5519         /* Make sure we're not suspended first. */
5520         pm_runtime_get_sync(device);
5521         pm_runtime_disable(device);
5522 }
5523
5524 /* Set up chip specific power management-related functions */
5525 void intel_init_pm(struct drm_device *dev)
5526 {
5527         struct drm_i915_private *dev_priv = dev->dev_private;
5528
5529         if (HAS_FBC(dev)) {
5530                 if (INTEL_INFO(dev)->gen >= 7) {
5531                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5532                         dev_priv->display.enable_fbc = gen7_enable_fbc;
5533                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5534                 } else if (INTEL_INFO(dev)->gen >= 5) {
5535                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5536                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5537                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5538                 } else if (IS_GM45(dev)) {
5539                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5540                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5541                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5542                 } else {
5543                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5544                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5545                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5546
5547                         /* This value was pulled out of someone's hat */
5548                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
5549                 }
5550         }
5551
5552         /* For cxsr */
5553         if (IS_PINEVIEW(dev))
5554                 i915_pineview_get_mem_freq(dev);
5555         else if (IS_GEN5(dev))
5556                 i915_ironlake_get_mem_freq(dev);
5557
5558         /* For FIFO watermark updates */
5559         if (HAS_PCH_SPLIT(dev)) {
5560                 intel_setup_wm_latency(dev);
5561
5562                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
5563                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5564                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
5565                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
5566                         dev_priv->display.update_wm = ilk_update_wm;
5567                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
5568                 } else {
5569                         DRM_DEBUG_KMS("Failed to read display plane latency. "
5570                                       "Disable CxSR\n");
5571                 }
5572
5573                 if (IS_GEN5(dev))
5574                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5575                 else if (IS_GEN6(dev))
5576                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5577                 else if (IS_IVYBRIDGE(dev))
5578                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5579                 else if (IS_HASWELL(dev))
5580                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5581                 else if (INTEL_INFO(dev)->gen == 8)
5582                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
5583         } else if (IS_VALLEYVIEW(dev)) {
5584                 dev_priv->display.update_wm = valleyview_update_wm;
5585                 dev_priv->display.init_clock_gating =
5586                         valleyview_init_clock_gating;
5587         } else if (IS_PINEVIEW(dev)) {
5588                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5589                                             dev_priv->is_ddr3,
5590                                             dev_priv->fsb_freq,
5591                                             dev_priv->mem_freq)) {
5592                         DRM_INFO("failed to find known CxSR latency "
5593                                  "(found ddr%s fsb freq %d, mem freq %d), "
5594                                  "disabling CxSR\n",
5595                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
5596                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5597                         /* Disable CxSR and never update its watermark again */
5598                         pineview_disable_cxsr(dev);
5599                         dev_priv->display.update_wm = NULL;
5600                 } else
5601                         dev_priv->display.update_wm = pineview_update_wm;
5602                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5603         } else if (IS_G4X(dev)) {
5604                 dev_priv->display.update_wm = g4x_update_wm;
5605                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5606         } else if (IS_GEN4(dev)) {
5607                 dev_priv->display.update_wm = i965_update_wm;
5608                 if (IS_CRESTLINE(dev))
5609                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5610                 else if (IS_BROADWATER(dev))
5611                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5612         } else if (IS_GEN3(dev)) {
5613                 dev_priv->display.update_wm = i9xx_update_wm;
5614                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5615                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5616         } else if (IS_GEN2(dev)) {
5617                 if (INTEL_INFO(dev)->num_pipes == 1) {
5618                         dev_priv->display.update_wm = i845_update_wm;
5619                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5620                 } else {
5621                         dev_priv->display.update_wm = i9xx_update_wm;
5622                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5623                 }
5624
5625                 if (IS_I85X(dev) || IS_I865G(dev))
5626                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5627                 else
5628                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
5629         } else {
5630                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
5631         }
5632 }
5633
5634 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5635 {
5636         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5637
5638         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5639                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5640                 return -EAGAIN;
5641         }
5642
5643         I915_WRITE(GEN6_PCODE_DATA, *val);
5644         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5645
5646         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5647                      500)) {
5648                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5649                 return -ETIMEDOUT;
5650         }
5651
5652         *val = I915_READ(GEN6_PCODE_DATA);
5653         I915_WRITE(GEN6_PCODE_DATA, 0);
5654
5655         return 0;
5656 }
5657
5658 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5659 {
5660         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5661
5662         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5663                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5664                 return -EAGAIN;
5665         }
5666
5667         I915_WRITE(GEN6_PCODE_DATA, val);
5668         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5669
5670         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5671                      500)) {
5672                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5673                 return -ETIMEDOUT;
5674         }
5675
5676         I915_WRITE(GEN6_PCODE_DATA, 0);
5677
5678         return 0;
5679 }
5680
5681 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
5682 {
5683         int div;
5684
5685         /* 4 x czclk */
5686         switch (dev_priv->mem_freq) {
5687         case 800:
5688                 div = 10;
5689                 break;
5690         case 1066:
5691                 div = 12;
5692                 break;
5693         case 1333:
5694                 div = 16;
5695                 break;
5696         default:
5697                 return -1;
5698         }
5699
5700         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
5701 }
5702
5703 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
5704 {
5705         int mul;
5706
5707         /* 4 x czclk */
5708         switch (dev_priv->mem_freq) {
5709         case 800:
5710                 mul = 10;
5711                 break;
5712         case 1066:
5713                 mul = 12;
5714                 break;
5715         case 1333:
5716                 mul = 16;
5717                 break;
5718         default:
5719                 return -1;
5720         }
5721
5722         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
5723 }
5724
5725 void intel_pm_init(struct drm_device *dev)
5726 {
5727         struct drm_i915_private *dev_priv = dev->dev_private;
5728
5729         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5730                           intel_gen6_powersave_work);
5731 }