drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 static void gen9_init_clock_gating(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58
  59         /* WaEnableLbsSlaRetryTimerDecrement:skl */
  60         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
  61                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
  62
  63         /* WaDisableKillLogic:bxt,skl */
  64         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  65                    ECOCHK_DIS_TLB);
  66 }
  67
  68 static void skl_init_clock_gating(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         gen9_init_clock_gating(dev);
  73
  74         if (INTEL_REVID(dev) <= SKL_REVID_B0) {
  75                 /*
  76                  * WaDisableSDEUnitClockGating:skl
  77                  * WaSetGAPSunitClckGateDisable:skl
  78                  */
  79                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  80                            GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
  81                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  82
  83                 /* WaDisableVFUnitClockGating:skl */
  84                 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
  85                            GEN6_VFUNIT_CLOCK_GATE_DISABLE);
  86         }
  87
  88         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
  89                 /* WaDisableHDCInvalidation:skl */
  90                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  91                            BDW_DISABLE_HDC_INVALIDATION);
  92
  93                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
  94                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
  95                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
  96         }
  97
  98         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
  99          * involving this register should also be added to WA batch as required.
 100          */
 101         if (INTEL_REVID(dev) <= SKL_REVID_E0)
 102                 /* WaDisableLSQCROPERFforOCL:skl */
 103                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
 104                            GEN8_LQSC_RO_PERF_DIS);
 105
 106         /* WaEnableGapsTsvCreditFix:skl */
 107         if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
 108                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
 109                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
 110         }
 111 }
 112
 113 static void bxt_init_clock_gating(struct drm_device *dev)
 114 {
 115         struct drm_i915_private *dev_priv = dev->dev_private;
 116
 117         gen9_init_clock_gating(dev);
 118
 119         /*
 120          * FIXME:
 121          * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
 122          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 123          */
 124          /* WaDisableSDEUnitClockGating:bxt */
 125         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 126                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
 127                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 128
 129         /* FIXME: apply on A0 only */
 130         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 131 }
 132
 133 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 134 {
 135         struct drm_i915_private *dev_priv = dev->dev_private;
 136         u32 tmp;
 137
 138         tmp = I915_READ(CLKCFG);
 139
 140         switch (tmp & CLKCFG_FSB_MASK) {
 141         case CLKCFG_FSB_533:
 142                 dev_priv->fsb_freq = 533; /* 133*4 */
 143                 break;
 144         case CLKCFG_FSB_800:
 145                 dev_priv->fsb_freq = 800; /* 200*4 */
 146                 break;
 147         case CLKCFG_FSB_667:
 148                 dev_priv->fsb_freq =  667; /* 167*4 */
 149                 break;
 150         case CLKCFG_FSB_400:
 151                 dev_priv->fsb_freq = 400; /* 100*4 */
 152                 break;
 153         }
 154
 155         switch (tmp & CLKCFG_MEM_MASK) {
 156         case CLKCFG_MEM_533:
 157                 dev_priv->mem_freq = 533;
 158                 break;
 159         case CLKCFG_MEM_667:
 160                 dev_priv->mem_freq = 667;
 161                 break;
 162         case CLKCFG_MEM_800:
 163                 dev_priv->mem_freq = 800;
 164                 break;
 165         }
 166
 167         /* detect pineview DDR3 setting */
 168         tmp = I915_READ(CSHRDDR3CTL);
 169         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 170 }
 171
 172 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175         u16 ddrpll, csipll;
 176
 177         ddrpll = I915_READ16(DDRMPLL1);
 178         csipll = I915_READ16(CSIPLL0);
 179
 180         switch (ddrpll & 0xff) {
 181         case 0xc:
 182                 dev_priv->mem_freq = 800;
 183                 break;
 184         case 0x10:
 185                 dev_priv->mem_freq = 1066;
 186                 break;
 187         case 0x14:
 188                 dev_priv->mem_freq = 1333;
 189                 break;
 190         case 0x18:
 191                 dev_priv->mem_freq = 1600;
 192                 break;
 193         default:
 194                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 195                                  ddrpll & 0xff);
 196                 dev_priv->mem_freq = 0;
 197                 break;
 198         }
 199
 200         dev_priv->ips.r_t = dev_priv->mem_freq;
 201
 202         switch (csipll & 0x3ff) {
 203         case 0x00c:
 204                 dev_priv->fsb_freq = 3200;
 205                 break;
 206         case 0x00e:
 207                 dev_priv->fsb_freq = 3733;
 208                 break;
 209         case 0x010:
 210                 dev_priv->fsb_freq = 4266;
 211                 break;
 212         case 0x012:
 213                 dev_priv->fsb_freq = 4800;
 214                 break;
 215         case 0x014:
 216                 dev_priv->fsb_freq = 5333;
 217                 break;
 218         case 0x016:
 219                 dev_priv->fsb_freq = 5866;
 220                 break;
 221         case 0x018:
 222                 dev_priv->fsb_freq = 6400;
 223                 break;
 224         default:
 225                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 226                                  csipll & 0x3ff);
 227                 dev_priv->fsb_freq = 0;
 228                 break;
 229         }
 230
 231         if (dev_priv->fsb_freq == 3200) {
 232                 dev_priv->ips.c_m = 0;
 233         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 234                 dev_priv->ips.c_m = 1;
 235         } else {
 236                 dev_priv->ips.c_m = 2;
 237         }
 238 }
 239
 240 static const struct cxsr_latency cxsr_latency_table[] = {
 241         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 242         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 243         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 244         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 245         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 246
 247         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 248         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 249         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 250         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 251         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 252
 253         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 254         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 255         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 256         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 257         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 258
 259         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 260         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 261         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 262         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 263         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 264
 265         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 266         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 267         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 268         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 269         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 270
 271         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 272         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 273         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 274         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 275         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 276 };
 277
 278 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 279                                                          int is_ddr3,
 280                                                          int fsb,
 281                                                          int mem)
 282 {
 283         const struct cxsr_latency *latency;
 284         int i;
 285
 286         if (fsb == 0 || mem == 0)
 287                 return NULL;
 288
 289         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 290                 latency = &cxsr_latency_table[i];
 291                 if (is_desktop == latency->is_desktop &&
 292                     is_ddr3 == latency->is_ddr3 &&
 293                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 294                         return latency;
 295         }
 296
 297         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 298
 299         return NULL;
 300 }
 301
 302 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 303 {
 304         u32 val;
 305
 306         mutex_lock(&dev_priv->rps.hw_lock);
 307
 308         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 309         if (enable)
 310                 val &= ~FORCE_DDR_HIGH_FREQ;
 311         else
 312                 val |= FORCE_DDR_HIGH_FREQ;
 313         val &= ~FORCE_DDR_LOW_FREQ;
 314         val |= FORCE_DDR_FREQ_REQ_ACK;
 315         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 316
 317         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 318                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 319                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 320
 321         mutex_unlock(&dev_priv->rps.hw_lock);
 322 }
 323
 324 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 325 {
 326         u32 val;
 327
 328         mutex_lock(&dev_priv->rps.hw_lock);
 329
 330         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 331         if (enable)
 332                 val |= DSP_MAXFIFO_PM5_ENABLE;
 333         else
 334                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 335         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 336
 337         mutex_unlock(&dev_priv->rps.hw_lock);
 338 }
 339
 340 #define FW_WM(value, plane) \
 341         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 342
 343 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 344 {
 345         struct drm_device *dev = dev_priv->dev;
 346         u32 val;
 347
 348         if (IS_VALLEYVIEW(dev)) {
 349                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 350                 POSTING_READ(FW_BLC_SELF_VLV);
 351                 dev_priv->wm.vlv.cxsr = enable;
 352         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 353                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 354                 POSTING_READ(FW_BLC_SELF);
 355         } else if (IS_PINEVIEW(dev)) {
 356                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 357                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 358                 I915_WRITE(DSPFW3, val);
 359                 POSTING_READ(DSPFW3);
 360         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 361                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 362                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 363                 I915_WRITE(FW_BLC_SELF, val);
 364                 POSTING_READ(FW_BLC_SELF);
 365         } else if (IS_I915GM(dev)) {
 366                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 367                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 368                 I915_WRITE(INSTPM, val);
 369                 POSTING_READ(INSTPM);
 370         } else {
 371                 return;
 372         }
 373
 374         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 375                       enable ? "enabled" : "disabled");
 376 }
 377
 378
 379 /*
 380  * Latency for FIFO fetches is dependent on several factors:
 381  *   - memory configuration (speed, channels)
 382  *   - chipset
 383  *   - current MCH state
 384  * It can be fairly high in some situations, so here we assume a fairly
 385  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 386  * set this value too high, the FIFO will fetch frequently to stay full)
 387  * and power consumption (set it too low to save power and we might see
 388  * FIFO underruns and display "flicker").
 389  *
 390  * A value of 5us seems to be a good balance; safe for very low end
 391  * platforms but not overly aggressive on lower latency configs.
 392  */
 393 static const int pessimal_latency_ns = 5000;
 394
 395 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 396         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 397
 398 static int vlv_get_fifo_size(struct drm_device *dev,
 399                               enum pipe pipe, int plane)
 400 {
 401         struct drm_i915_private *dev_priv = dev->dev_private;
 402         int sprite0_start, sprite1_start, size;
 403
 404         switch (pipe) {
 405                 uint32_t dsparb, dsparb2, dsparb3;
 406         case PIPE_A:
 407                 dsparb = I915_READ(DSPARB);
 408                 dsparb2 = I915_READ(DSPARB2);
 409                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 410                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 411                 break;
 412         case PIPE_B:
 413                 dsparb = I915_READ(DSPARB);
 414                 dsparb2 = I915_READ(DSPARB2);
 415                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 416                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 417                 break;
 418         case PIPE_C:
 419                 dsparb2 = I915_READ(DSPARB2);
 420                 dsparb3 = I915_READ(DSPARB3);
 421                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 422                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 423                 break;
 424         default:
 425                 return 0;
 426         }
 427
 428         switch (plane) {
 429         case 0:
 430                 size = sprite0_start;
 431                 break;
 432         case 1:
 433                 size = sprite1_start - sprite0_start;
 434                 break;
 435         case 2:
 436                 size = 512 - 1 - sprite1_start;
 437                 break;
 438         default:
 439                 return 0;
 440         }
 441
 442         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 443                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 444                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 445                       size);
 446
 447         return size;
 448 }
 449
 450 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 451 {
 452         struct drm_i915_private *dev_priv = dev->dev_private;
 453         uint32_t dsparb = I915_READ(DSPARB);
 454         int size;
 455
 456         size = dsparb & 0x7f;
 457         if (plane)
 458                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 459
 460         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 461                       plane ? "B" : "A", size);
 462
 463         return size;
 464 }
 465
 466 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469         uint32_t dsparb = I915_READ(DSPARB);
 470         int size;
 471
 472         size = dsparb & 0x1ff;
 473         if (plane)
 474                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 475         size >>= 1; /* Convert to cachelines */
 476
 477         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 478                       plane ? "B" : "A", size);
 479
 480         return size;
 481 }
 482
 483 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 484 {
 485         struct drm_i915_private *dev_priv = dev->dev_private;
 486         uint32_t dsparb = I915_READ(DSPARB);
 487         int size;
 488
 489         size = dsparb & 0x7f;
 490         size >>= 2; /* Convert to cachelines */
 491
 492         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 493                       plane ? "B" : "A",
 494                       size);
 495
 496         return size;
 497 }
 498
 499 /* Pineview has different values for various configs */
 500 static const struct intel_watermark_params pineview_display_wm = {
 501         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 502         .max_wm = PINEVIEW_MAX_WM,
 503         .default_wm = PINEVIEW_DFT_WM,
 504         .guard_size = PINEVIEW_GUARD_WM,
 505         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 506 };
 507 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 508         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 509         .max_wm = PINEVIEW_MAX_WM,
 510         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 511         .guard_size = PINEVIEW_GUARD_WM,
 512         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 513 };
 514 static const struct intel_watermark_params pineview_cursor_wm = {
 515         .fifo_size = PINEVIEW_CURSOR_FIFO,
 516         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 517         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 518         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 519         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 520 };
 521 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 522         .fifo_size = PINEVIEW_CURSOR_FIFO,
 523         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 524         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 525         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 526         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 527 };
 528 static const struct intel_watermark_params g4x_wm_info = {
 529         .fifo_size = G4X_FIFO_SIZE,
 530         .max_wm = G4X_MAX_WM,
 531         .default_wm = G4X_MAX_WM,
 532         .guard_size = 2,
 533         .cacheline_size = G4X_FIFO_LINE_SIZE,
 534 };
 535 static const struct intel_watermark_params g4x_cursor_wm_info = {
 536         .fifo_size = I965_CURSOR_FIFO,
 537         .max_wm = I965_CURSOR_MAX_WM,
 538         .default_wm = I965_CURSOR_DFT_WM,
 539         .guard_size = 2,
 540         .cacheline_size = G4X_FIFO_LINE_SIZE,
 541 };
 542 static const struct intel_watermark_params valleyview_wm_info = {
 543         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 544         .max_wm = VALLEYVIEW_MAX_WM,
 545         .default_wm = VALLEYVIEW_MAX_WM,
 546         .guard_size = 2,
 547         .cacheline_size = G4X_FIFO_LINE_SIZE,
 548 };
 549 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 550         .fifo_size = I965_CURSOR_FIFO,
 551         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 552         .default_wm = I965_CURSOR_DFT_WM,
 553         .guard_size = 2,
 554         .cacheline_size = G4X_FIFO_LINE_SIZE,
 555 };
 556 static const struct intel_watermark_params i965_cursor_wm_info = {
 557         .fifo_size = I965_CURSOR_FIFO,
 558         .max_wm = I965_CURSOR_MAX_WM,
 559         .default_wm = I965_CURSOR_DFT_WM,
 560         .guard_size = 2,
 561         .cacheline_size = I915_FIFO_LINE_SIZE,
 562 };
 563 static const struct intel_watermark_params i945_wm_info = {
 564         .fifo_size = I945_FIFO_SIZE,
 565         .max_wm = I915_MAX_WM,
 566         .default_wm = 1,
 567         .guard_size = 2,
 568         .cacheline_size = I915_FIFO_LINE_SIZE,
 569 };
 570 static const struct intel_watermark_params i915_wm_info = {
 571         .fifo_size = I915_FIFO_SIZE,
 572         .max_wm = I915_MAX_WM,
 573         .default_wm = 1,
 574         .guard_size = 2,
 575         .cacheline_size = I915_FIFO_LINE_SIZE,
 576 };
 577 static const struct intel_watermark_params i830_a_wm_info = {
 578         .fifo_size = I855GM_FIFO_SIZE,
 579         .max_wm = I915_MAX_WM,
 580         .default_wm = 1,
 581         .guard_size = 2,
 582         .cacheline_size = I830_FIFO_LINE_SIZE,
 583 };
 584 static const struct intel_watermark_params i830_bc_wm_info = {
 585         .fifo_size = I855GM_FIFO_SIZE,
 586         .max_wm = I915_MAX_WM/2,
 587         .default_wm = 1,
 588         .guard_size = 2,
 589         .cacheline_size = I830_FIFO_LINE_SIZE,
 590 };
 591 static const struct intel_watermark_params i845_wm_info = {
 592         .fifo_size = I830_FIFO_SIZE,
 593         .max_wm = I915_MAX_WM,
 594         .default_wm = 1,
 595         .guard_size = 2,
 596         .cacheline_size = I830_FIFO_LINE_SIZE,
 597 };
 598
 599 /**
 600  * intel_calculate_wm - calculate watermark level
 601  * @clock_in_khz: pixel clock
 602  * @wm: chip FIFO params
 603  * @pixel_size: display pixel size
 604  * @latency_ns: memory latency for the platform
 605  *
 606  * Calculate the watermark level (the level at which the display plane will
 607  * start fetching from memory again).  Each chip has a different display
 608  * FIFO size and allocation, so the caller needs to figure that out and pass
 609  * in the correct intel_watermark_params structure.
 610  *
 611  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 612  * on the pixel size.  When it reaches the watermark level, it'll start
 613  * fetching FIFO line sized based chunks from memory until the FIFO fills
 614  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 615  * will occur, and a display engine hang could result.
 616  */
 617 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 618                                         const struct intel_watermark_params *wm,
 619                                         int fifo_size,
 620                                         int pixel_size,
 621                                         unsigned long latency_ns)
 622 {
 623         long entries_required, wm_size;
 624
 625         /*
 626          * Note: we need to make sure we don't overflow for various clock &
 627          * latency values.
 628          * clocks go from a few thousand to several hundred thousand.
 629          * latency is usually a few thousand
 630          */
 631         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 632                 1000;
 633         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 634
 635         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 636
 637         wm_size = fifo_size - (entries_required + wm->guard_size);
 638
 639         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 640
 641         /* Don't promote wm_size to unsigned... */
 642         if (wm_size > (long)wm->max_wm)
 643                 wm_size = wm->max_wm;
 644         if (wm_size <= 0)
 645                 wm_size = wm->default_wm;
 646
 647         /*
 648          * Bspec seems to indicate that the value shouldn't be lower than
 649          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 650          * Lets go for 8 which is the burst size since certain platforms
 651          * already use a hardcoded 8 (which is what the spec says should be
 652          * done).
 653          */
 654         if (wm_size <= 8)
 655                 wm_size = 8;
 656
 657         return wm_size;
 658 }
 659
 660 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 661 {
 662         struct drm_crtc *crtc, *enabled = NULL;
 663
 664         for_each_crtc(dev, crtc) {
 665                 if (intel_crtc_active(crtc)) {
 666                         if (enabled)
 667                                 return NULL;
 668                         enabled = crtc;
 669                 }
 670         }
 671
 672         return enabled;
 673 }
 674
 675 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 676 {
 677         struct drm_device *dev = unused_crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         struct drm_crtc *crtc;
 680         const struct cxsr_latency *latency;
 681         u32 reg;
 682         unsigned long wm;
 683
 684         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 685                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 686         if (!latency) {
 687                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 688                 intel_set_memory_cxsr(dev_priv, false);
 689                 return;
 690         }
 691
 692         crtc = single_enabled_crtc(dev);
 693         if (crtc) {
 694                 const struct drm_display_mode *adjusted_mode;
 695                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 696                 int clock;
 697
 698                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 699                 clock = adjusted_mode->crtc_clock;
 700
 701                 /* Display SR */
 702                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 703                                         pineview_display_wm.fifo_size,
 704                                         pixel_size, latency->display_sr);
 705                 reg = I915_READ(DSPFW1);
 706                 reg &= ~DSPFW_SR_MASK;
 707                 reg |= FW_WM(wm, SR);
 708                 I915_WRITE(DSPFW1, reg);
 709                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 710
 711                 /* cursor SR */
 712                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 713                                         pineview_display_wm.fifo_size,
 714                                         pixel_size, latency->cursor_sr);
 715                 reg = I915_READ(DSPFW3);
 716                 reg &= ~DSPFW_CURSOR_SR_MASK;
 717                 reg |= FW_WM(wm, CURSOR_SR);
 718                 I915_WRITE(DSPFW3, reg);
 719
 720                 /* Display HPLL off SR */
 721                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 722                                         pineview_display_hplloff_wm.fifo_size,
 723                                         pixel_size, latency->display_hpll_disable);
 724                 reg = I915_READ(DSPFW3);
 725                 reg &= ~DSPFW_HPLL_SR_MASK;
 726                 reg |= FW_WM(wm, HPLL_SR);
 727                 I915_WRITE(DSPFW3, reg);
 728
 729                 /* cursor HPLL off SR */
 730                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 731                                         pineview_display_hplloff_wm.fifo_size,
 732                                         pixel_size, latency->cursor_hpll_disable);
 733                 reg = I915_READ(DSPFW3);
 734                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 735                 reg |= FW_WM(wm, HPLL_CURSOR);
 736                 I915_WRITE(DSPFW3, reg);
 737                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 738
 739                 intel_set_memory_cxsr(dev_priv, true);
 740         } else {
 741                 intel_set_memory_cxsr(dev_priv, false);
 742         }
 743 }
 744
 745 static bool g4x_compute_wm0(struct drm_device *dev,
 746                             int plane,
 747                             const struct intel_watermark_params *display,
 748                             int display_latency_ns,
 749                             const struct intel_watermark_params *cursor,
 750                             int cursor_latency_ns,
 751                             int *plane_wm,
 752                             int *cursor_wm)
 753 {
 754         struct drm_crtc *crtc;
 755         const struct drm_display_mode *adjusted_mode;
 756         int htotal, hdisplay, clock, pixel_size;
 757         int line_time_us, line_count;
 758         int entries, tlb_miss;
 759
 760         crtc = intel_get_crtc_for_plane(dev, plane);
 761         if (!intel_crtc_active(crtc)) {
 762                 *cursor_wm = cursor->guard_size;
 763                 *plane_wm = display->guard_size;
 764                 return false;
 765         }
 766
 767         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 768         clock = adjusted_mode->crtc_clock;
 769         htotal = adjusted_mode->crtc_htotal;
 770         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 771         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 772
 773         /* Use the small buffer method to calculate plane watermark */
 774         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 775         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 776         if (tlb_miss > 0)
 777                 entries += tlb_miss;
 778         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 779         *plane_wm = entries + display->guard_size;
 780         if (*plane_wm > (int)display->max_wm)
 781                 *plane_wm = display->max_wm;
 782
 783         /* Use the large buffer method to calculate cursor watermark */
 784         line_time_us = max(htotal * 1000 / clock, 1);
 785         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 786         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 787         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 788         if (tlb_miss > 0)
 789                 entries += tlb_miss;
 790         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 791         *cursor_wm = entries + cursor->guard_size;
 792         if (*cursor_wm > (int)cursor->max_wm)
 793                 *cursor_wm = (int)cursor->max_wm;
 794
 795         return true;
 796 }
 797
 798 /*
 799  * Check the wm result.
 800  *
 801  * If any calculated watermark values is larger than the maximum value that
 802  * can be programmed into the associated watermark register, that watermark
 803  * must be disabled.
 804  */
 805 static bool g4x_check_srwm(struct drm_device *dev,
 806                            int display_wm, int cursor_wm,
 807                            const struct intel_watermark_params *display,
 808                            const struct intel_watermark_params *cursor)
 809 {
 810         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 811                       display_wm, cursor_wm);
 812
 813         if (display_wm > display->max_wm) {
 814                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 815                               display_wm, display->max_wm);
 816                 return false;
 817         }
 818
 819         if (cursor_wm > cursor->max_wm) {
 820                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 821                               cursor_wm, cursor->max_wm);
 822                 return false;
 823         }
 824
 825         if (!(display_wm || cursor_wm)) {
 826                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 827                 return false;
 828         }
 829
 830         return true;
 831 }
 832
 833 static bool g4x_compute_srwm(struct drm_device *dev,
 834                              int plane,
 835                              int latency_ns,
 836                              const struct intel_watermark_params *display,
 837                              const struct intel_watermark_params *cursor,
 838                              int *display_wm, int *cursor_wm)
 839 {
 840         struct drm_crtc *crtc;
 841         const struct drm_display_mode *adjusted_mode;
 842         int hdisplay, htotal, pixel_size, clock;
 843         unsigned long line_time_us;
 844         int line_count, line_size;
 845         int small, large;
 846         int entries;
 847
 848         if (!latency_ns) {
 849                 *display_wm = *cursor_wm = 0;
 850                 return false;
 851         }
 852
 853         crtc = intel_get_crtc_for_plane(dev, plane);
 854         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 855         clock = adjusted_mode->crtc_clock;
 856         htotal = adjusted_mode->crtc_htotal;
 857         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 858         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 859
 860         line_time_us = max(htotal * 1000 / clock, 1);
 861         line_count = (latency_ns / line_time_us + 1000) / 1000;
 862         line_size = hdisplay * pixel_size;
 863
 864         /* Use the minimum of the small and large buffer method for primary */
 865         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 866         large = line_count * line_size;
 867
 868         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 869         *display_wm = entries + display->guard_size;
 870
 871         /* calculate the self-refresh watermark for display cursor */
 872         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 873         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 874         *cursor_wm = entries + cursor->guard_size;
 875
 876         return g4x_check_srwm(dev,
 877                               *display_wm, *cursor_wm,
 878                               display, cursor);
 879 }
 880
 881 #define FW_WM_VLV(value, plane) \
 882         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 883
 884 static void vlv_write_wm_values(struct intel_crtc *crtc,
 885                                 const struct vlv_wm_values *wm)
 886 {
 887         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 888         enum pipe pipe = crtc->pipe;
 889
 890         I915_WRITE(VLV_DDL(pipe),
 891                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 892                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 893                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 894                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 895
 896         I915_WRITE(DSPFW1,
 897                    FW_WM(wm->sr.plane, SR) |
 898                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 899                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 900                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 901         I915_WRITE(DSPFW2,
 902                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 903                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 904                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 905         I915_WRITE(DSPFW3,
 906                    FW_WM(wm->sr.cursor, CURSOR_SR));
 907
 908         if (IS_CHERRYVIEW(dev_priv)) {
 909                 I915_WRITE(DSPFW7_CHV,
 910                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 911                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 912                 I915_WRITE(DSPFW8_CHV,
 913                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 914                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 915                 I915_WRITE(DSPFW9_CHV,
 916                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 917                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 918                 I915_WRITE(DSPHOWM,
 919                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 920                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 921                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 922                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 923                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 924                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 925                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 926                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 927                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 928                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 929         } else {
 930                 I915_WRITE(DSPFW7,
 931                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 932                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 933                 I915_WRITE(DSPHOWM,
 934                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 935                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 936                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 937                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 938                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 939                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 940                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 941         }
 942
 943         /* zero (unused) WM1 watermarks */
 944         I915_WRITE(DSPFW4, 0);
 945         I915_WRITE(DSPFW5, 0);
 946         I915_WRITE(DSPFW6, 0);
 947         I915_WRITE(DSPHOWM1, 0);
 948
 949         POSTING_READ(DSPFW1);
 950 }
 951
 952 #undef FW_WM_VLV
 953
 954 enum vlv_wm_level {
 955         VLV_WM_LEVEL_PM2,
 956         VLV_WM_LEVEL_PM5,
 957         VLV_WM_LEVEL_DDR_DVFS,
 958 };
 959
 960 /* latency must be in 0.1us units. */
 961 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 962                                    unsigned int pipe_htotal,
 963                                    unsigned int horiz_pixels,
 964                                    unsigned int bytes_per_pixel,
 965                                    unsigned int latency)
 966 {
 967         unsigned int ret;
 968
 969         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 970         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 971         ret = DIV_ROUND_UP(ret, 64);
 972
 973         return ret;
 974 }
 975
 976 static void vlv_setup_wm_latency(struct drm_device *dev)
 977 {
 978         struct drm_i915_private *dev_priv = dev->dev_private;
 979
 980         /* all latencies in usec */
 981         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 982
 983         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 984
 985         if (IS_CHERRYVIEW(dev_priv)) {
 986                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 987                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 988
 989                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 990         }
 991 }
 992
 993 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 994                                      struct intel_crtc *crtc,
 995                                      const struct intel_plane_state *state,
 996                                      int level)
 997 {
 998         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 999         int clock, htotal, pixel_size, width, wm;
1000
1001         if (dev_priv->wm.pri_latency[level] == 0)
1002                 return USHRT_MAX;
1003
1004         if (!state->visible)
1005                 return 0;
1006
1007         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1008         clock = crtc->config->base.adjusted_mode.crtc_clock;
1009         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1010         width = crtc->config->pipe_src_w;
1011         if (WARN_ON(htotal == 0))
1012                 htotal = 1;
1013
1014         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1015                 /*
1016                  * FIXME the formula gives values that are
1017                  * too big for the cursor FIFO, and hence we
1018                  * would never be able to use cursors. For
1019                  * now just hardcode the watermark.
1020                  */
1021                 wm = 63;
1022         } else {
1023                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1024                                     dev_priv->wm.pri_latency[level] * 10);
1025         }
1026
1027         return min_t(int, wm, USHRT_MAX);
1028 }
1029
1030 static void vlv_compute_fifo(struct intel_crtc *crtc)
1031 {
1032         struct drm_device *dev = crtc->base.dev;
1033         struct vlv_wm_state *wm_state = &crtc->wm_state;
1034         struct intel_plane *plane;
1035         unsigned int total_rate = 0;
1036         const int fifo_size = 512 - 1;
1037         int fifo_extra, fifo_left = fifo_size;
1038
1039         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040                 struct intel_plane_state *state =
1041                         to_intel_plane_state(plane->base.state);
1042
1043                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1044                         continue;
1045
1046                 if (state->visible) {
1047                         wm_state->num_active_planes++;
1048                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1049                 }
1050         }
1051
1052         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1053                 struct intel_plane_state *state =
1054                         to_intel_plane_state(plane->base.state);
1055                 unsigned int rate;
1056
1057                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1058                         plane->wm.fifo_size = 63;
1059                         continue;
1060                 }
1061
1062                 if (!state->visible) {
1063                         plane->wm.fifo_size = 0;
1064                         continue;
1065                 }
1066
1067                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1068                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1069                 fifo_left -= plane->wm.fifo_size;
1070         }
1071
1072         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1073
1074         /* spread the remainder evenly */
1075         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1076                 int plane_extra;
1077
1078                 if (fifo_left == 0)
1079                         break;
1080
1081                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1082                         continue;
1083
1084                 /* give it all to the first plane if none are active */
1085                 if (plane->wm.fifo_size == 0 &&
1086                     wm_state->num_active_planes)
1087                         continue;
1088
1089                 plane_extra = min(fifo_extra, fifo_left);
1090                 plane->wm.fifo_size += plane_extra;
1091                 fifo_left -= plane_extra;
1092         }
1093
1094         WARN_ON(fifo_left != 0);
1095 }
1096
1097 static void vlv_invert_wms(struct intel_crtc *crtc)
1098 {
1099         struct vlv_wm_state *wm_state = &crtc->wm_state;
1100         int level;
1101
1102         for (level = 0; level < wm_state->num_levels; level++) {
1103                 struct drm_device *dev = crtc->base.dev;
1104                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1105                 struct intel_plane *plane;
1106
1107                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1108                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1109
1110                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1111                         switch (plane->base.type) {
1112                                 int sprite;
1113                         case DRM_PLANE_TYPE_CURSOR:
1114                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1115                                         wm_state->wm[level].cursor;
1116                                 break;
1117                         case DRM_PLANE_TYPE_PRIMARY:
1118                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1119                                         wm_state->wm[level].primary;
1120                                 break;
1121                         case DRM_PLANE_TYPE_OVERLAY:
1122                                 sprite = plane->plane;
1123                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1124                                         wm_state->wm[level].sprite[sprite];
1125                                 break;
1126                         }
1127                 }
1128         }
1129 }
1130
1131 static void vlv_compute_wm(struct intel_crtc *crtc)
1132 {
1133         struct drm_device *dev = crtc->base.dev;
1134         struct vlv_wm_state *wm_state = &crtc->wm_state;
1135         struct intel_plane *plane;
1136         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1137         int level;
1138
1139         memset(wm_state, 0, sizeof(*wm_state));
1140
1141         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1142         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1143
1144         wm_state->num_active_planes = 0;
1145
1146         vlv_compute_fifo(crtc);
1147
1148         if (wm_state->num_active_planes != 1)
1149                 wm_state->cxsr = false;
1150
1151         if (wm_state->cxsr) {
1152                 for (level = 0; level < wm_state->num_levels; level++) {
1153                         wm_state->sr[level].plane = sr_fifo_size;
1154                         wm_state->sr[level].cursor = 63;
1155                 }
1156         }
1157
1158         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1159                 struct intel_plane_state *state =
1160                         to_intel_plane_state(plane->base.state);
1161
1162                 if (!state->visible)
1163                         continue;
1164
1165                 /* normal watermarks */
1166                 for (level = 0; level < wm_state->num_levels; level++) {
1167                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1168                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1169
1170                         /* hack */
1171                         if (WARN_ON(level == 0 && wm > max_wm))
1172                                 wm = max_wm;
1173
1174                         if (wm > plane->wm.fifo_size)
1175                                 break;
1176
1177                         switch (plane->base.type) {
1178                                 int sprite;
1179                         case DRM_PLANE_TYPE_CURSOR:
1180                                 wm_state->wm[level].cursor = wm;
1181                                 break;
1182                         case DRM_PLANE_TYPE_PRIMARY:
1183                                 wm_state->wm[level].primary = wm;
1184                                 break;
1185                         case DRM_PLANE_TYPE_OVERLAY:
1186                                 sprite = plane->plane;
1187                                 wm_state->wm[level].sprite[sprite] = wm;
1188                                 break;
1189                         }
1190                 }
1191
1192                 wm_state->num_levels = level;
1193
1194                 if (!wm_state->cxsr)
1195                         continue;
1196
1197                 /* maxfifo watermarks */
1198                 switch (plane->base.type) {
1199                         int sprite, level;
1200                 case DRM_PLANE_TYPE_CURSOR:
1201                         for (level = 0; level < wm_state->num_levels; level++)
1202                                 wm_state->sr[level].cursor =
1203                                         wm_state->sr[level].cursor;
1204                         break;
1205                 case DRM_PLANE_TYPE_PRIMARY:
1206                         for (level = 0; level < wm_state->num_levels; level++)
1207                                 wm_state->sr[level].plane =
1208                                         min(wm_state->sr[level].plane,
1209                                             wm_state->wm[level].primary);
1210                         break;
1211                 case DRM_PLANE_TYPE_OVERLAY:
1212                         sprite = plane->plane;
1213                         for (level = 0; level < wm_state->num_levels; level++)
1214                                 wm_state->sr[level].plane =
1215                                         min(wm_state->sr[level].plane,
1216                                             wm_state->wm[level].sprite[sprite]);
1217                         break;
1218                 }
1219         }
1220
1221         /* clear any (partially) filled invalid levels */
1222         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1223                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1224                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1225         }
1226
1227         vlv_invert_wms(crtc);
1228 }
1229
1230 #define VLV_FIFO(plane, value) \
1231         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1232
1233 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1234 {
1235         struct drm_device *dev = crtc->base.dev;
1236         struct drm_i915_private *dev_priv = to_i915(dev);
1237         struct intel_plane *plane;
1238         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1239
1240         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1241                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1242                         WARN_ON(plane->wm.fifo_size != 63);
1243                         continue;
1244                 }
1245
1246                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1247                         sprite0_start = plane->wm.fifo_size;
1248                 else if (plane->plane == 0)
1249                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1250                 else
1251                         fifo_size = sprite1_start + plane->wm.fifo_size;
1252         }
1253
1254         WARN_ON(fifo_size != 512 - 1);
1255
1256         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1257                       pipe_name(crtc->pipe), sprite0_start,
1258                       sprite1_start, fifo_size);
1259
1260         switch (crtc->pipe) {
1261                 uint32_t dsparb, dsparb2, dsparb3;
1262         case PIPE_A:
1263                 dsparb = I915_READ(DSPARB);
1264                 dsparb2 = I915_READ(DSPARB2);
1265
1266                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1267                             VLV_FIFO(SPRITEB, 0xff));
1268                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1269                            VLV_FIFO(SPRITEB, sprite1_start));
1270
1271                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1272                              VLV_FIFO(SPRITEB_HI, 0x1));
1273                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1274                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1275
1276                 I915_WRITE(DSPARB, dsparb);
1277                 I915_WRITE(DSPARB2, dsparb2);
1278                 break;
1279         case PIPE_B:
1280                 dsparb = I915_READ(DSPARB);
1281                 dsparb2 = I915_READ(DSPARB2);
1282
1283                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1284                             VLV_FIFO(SPRITED, 0xff));
1285                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1286                            VLV_FIFO(SPRITED, sprite1_start));
1287
1288                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1289                              VLV_FIFO(SPRITED_HI, 0xff));
1290                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1291                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1292
1293                 I915_WRITE(DSPARB, dsparb);
1294                 I915_WRITE(DSPARB2, dsparb2);
1295                 break;
1296         case PIPE_C:
1297                 dsparb3 = I915_READ(DSPARB3);
1298                 dsparb2 = I915_READ(DSPARB2);
1299
1300                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1301                              VLV_FIFO(SPRITEF, 0xff));
1302                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1303                             VLV_FIFO(SPRITEF, sprite1_start));
1304
1305                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1306                              VLV_FIFO(SPRITEF_HI, 0xff));
1307                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1308                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1309
1310                 I915_WRITE(DSPARB3, dsparb3);
1311                 I915_WRITE(DSPARB2, dsparb2);
1312                 break;
1313         default:
1314                 break;
1315         }
1316 }
1317
1318 #undef VLV_FIFO
1319
1320 static void vlv_merge_wm(struct drm_device *dev,
1321                          struct vlv_wm_values *wm)
1322 {
1323         struct intel_crtc *crtc;
1324         int num_active_crtcs = 0;
1325
1326         wm->level = to_i915(dev)->wm.max_level;
1327         wm->cxsr = true;
1328
1329         for_each_intel_crtc(dev, crtc) {
1330                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1331
1332                 if (!crtc->active)
1333                         continue;
1334
1335                 if (!wm_state->cxsr)
1336                         wm->cxsr = false;
1337
1338                 num_active_crtcs++;
1339                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1340         }
1341
1342         if (num_active_crtcs != 1)
1343                 wm->cxsr = false;
1344
1345         if (num_active_crtcs > 1)
1346                 wm->level = VLV_WM_LEVEL_PM2;
1347
1348         for_each_intel_crtc(dev, crtc) {
1349                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1350                 enum pipe pipe = crtc->pipe;
1351
1352                 if (!crtc->active)
1353                         continue;
1354
1355                 wm->pipe[pipe] = wm_state->wm[wm->level];
1356                 if (wm->cxsr)
1357                         wm->sr = wm_state->sr[wm->level];
1358
1359                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1360                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1361                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1362                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1363         }
1364 }
1365
1366 static void vlv_update_wm(struct drm_crtc *crtc)
1367 {
1368         struct drm_device *dev = crtc->dev;
1369         struct drm_i915_private *dev_priv = dev->dev_private;
1370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1371         enum pipe pipe = intel_crtc->pipe;
1372         struct vlv_wm_values wm = {};
1373
1374         vlv_compute_wm(intel_crtc);
1375         vlv_merge_wm(dev, &wm);
1376
1377         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1378                 /* FIXME should be part of crtc atomic commit */
1379                 vlv_pipe_set_fifo_size(intel_crtc);
1380                 return;
1381         }
1382
1383         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1384             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1385                 chv_set_memory_dvfs(dev_priv, false);
1386
1387         if (wm.level < VLV_WM_LEVEL_PM5 &&
1388             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1389                 chv_set_memory_pm5(dev_priv, false);
1390
1391         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1392                 intel_set_memory_cxsr(dev_priv, false);
1393
1394         /* FIXME should be part of crtc atomic commit */
1395         vlv_pipe_set_fifo_size(intel_crtc);
1396
1397         vlv_write_wm_values(intel_crtc, &wm);
1398
1399         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1400                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1401                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1402                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1403                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1404
1405         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1406                 intel_set_memory_cxsr(dev_priv, true);
1407
1408         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1409             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1410                 chv_set_memory_pm5(dev_priv, true);
1411
1412         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1413             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1414                 chv_set_memory_dvfs(dev_priv, true);
1415
1416         dev_priv->wm.vlv = wm;
1417 }
1418
1419 #define single_plane_enabled(mask) is_power_of_2(mask)
1420
1421 static void g4x_update_wm(struct drm_crtc *crtc)
1422 {
1423         struct drm_device *dev = crtc->dev;
1424         static const int sr_latency_ns = 12000;
1425         struct drm_i915_private *dev_priv = dev->dev_private;
1426         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1427         int plane_sr, cursor_sr;
1428         unsigned int enabled = 0;
1429         bool cxsr_enabled;
1430
1431         if (g4x_compute_wm0(dev, PIPE_A,
1432                             &g4x_wm_info, pessimal_latency_ns,
1433                             &g4x_cursor_wm_info, pessimal_latency_ns,
1434                             &planea_wm, &cursora_wm))
1435                 enabled |= 1 << PIPE_A;
1436
1437         if (g4x_compute_wm0(dev, PIPE_B,
1438                             &g4x_wm_info, pessimal_latency_ns,
1439                             &g4x_cursor_wm_info, pessimal_latency_ns,
1440                             &planeb_wm, &cursorb_wm))
1441                 enabled |= 1 << PIPE_B;
1442
1443         if (single_plane_enabled(enabled) &&
1444             g4x_compute_srwm(dev, ffs(enabled) - 1,
1445                              sr_latency_ns,
1446                              &g4x_wm_info,
1447                              &g4x_cursor_wm_info,
1448                              &plane_sr, &cursor_sr)) {
1449                 cxsr_enabled = true;
1450         } else {
1451                 cxsr_enabled = false;
1452                 intel_set_memory_cxsr(dev_priv, false);
1453                 plane_sr = cursor_sr = 0;
1454         }
1455
1456         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1457                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1458                       planea_wm, cursora_wm,
1459                       planeb_wm, cursorb_wm,
1460                       plane_sr, cursor_sr);
1461
1462         I915_WRITE(DSPFW1,
1463                    FW_WM(plane_sr, SR) |
1464                    FW_WM(cursorb_wm, CURSORB) |
1465                    FW_WM(planeb_wm, PLANEB) |
1466                    FW_WM(planea_wm, PLANEA));
1467         I915_WRITE(DSPFW2,
1468                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1469                    FW_WM(cursora_wm, CURSORA));
1470         /* HPLL off in SR has some issues on G4x... disable it */
1471         I915_WRITE(DSPFW3,
1472                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1473                    FW_WM(cursor_sr, CURSOR_SR));
1474
1475         if (cxsr_enabled)
1476                 intel_set_memory_cxsr(dev_priv, true);
1477 }
1478
1479 static void i965_update_wm(struct drm_crtc *unused_crtc)
1480 {
1481         struct drm_device *dev = unused_crtc->dev;
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483         struct drm_crtc *crtc;
1484         int srwm = 1;
1485         int cursor_sr = 16;
1486         bool cxsr_enabled;
1487
1488         /* Calc sr entries for one plane configs */
1489         crtc = single_enabled_crtc(dev);
1490         if (crtc) {
1491                 /* self-refresh has much higher latency */
1492                 static const int sr_latency_ns = 12000;
1493                 const struct drm_display_mode *adjusted_mode =
1494                         &to_intel_crtc(crtc)->config->base.adjusted_mode;
1495                 int clock = adjusted_mode->crtc_clock;
1496                 int htotal = adjusted_mode->crtc_htotal;
1497                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1498                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1499                 unsigned long line_time_us;
1500                 int entries;
1501
1502                 line_time_us = max(htotal * 1000 / clock, 1);
1503
1504                 /* Use ns/us then divide to preserve precision */
1505                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1506                         pixel_size * hdisplay;
1507                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1508                 srwm = I965_FIFO_SIZE - entries;
1509                 if (srwm < 0)
1510                         srwm = 1;
1511                 srwm &= 0x1ff;
1512                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1513                               entries, srwm);
1514
1515                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1516                         pixel_size * crtc->cursor->state->crtc_w;
1517                 entries = DIV_ROUND_UP(entries,
1518                                           i965_cursor_wm_info.cacheline_size);
1519                 cursor_sr = i965_cursor_wm_info.fifo_size -
1520                         (entries + i965_cursor_wm_info.guard_size);
1521
1522                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1523                         cursor_sr = i965_cursor_wm_info.max_wm;
1524
1525                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1526                               "cursor %d\n", srwm, cursor_sr);
1527
1528                 cxsr_enabled = true;
1529         } else {
1530                 cxsr_enabled = false;
1531                 /* Turn off self refresh if both pipes are enabled */
1532                 intel_set_memory_cxsr(dev_priv, false);
1533         }
1534
1535         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1536                       srwm);
1537
1538         /* 965 has limitations... */
1539         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1540                    FW_WM(8, CURSORB) |
1541                    FW_WM(8, PLANEB) |
1542                    FW_WM(8, PLANEA));
1543         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1544                    FW_WM(8, PLANEC_OLD));
1545         /* update cursor SR watermark */
1546         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1547
1548         if (cxsr_enabled)
1549                 intel_set_memory_cxsr(dev_priv, true);
1550 }
1551
1552 #undef FW_WM
1553
1554 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1555 {
1556         struct drm_device *dev = unused_crtc->dev;
1557         struct drm_i915_private *dev_priv = dev->dev_private;
1558         const struct intel_watermark_params *wm_info;
1559         uint32_t fwater_lo;
1560         uint32_t fwater_hi;
1561         int cwm, srwm = 1;
1562         int fifo_size;
1563         int planea_wm, planeb_wm;
1564         struct drm_crtc *crtc, *enabled = NULL;
1565
1566         if (IS_I945GM(dev))
1567                 wm_info = &i945_wm_info;
1568         else if (!IS_GEN2(dev))
1569                 wm_info = &i915_wm_info;
1570         else
1571                 wm_info = &i830_a_wm_info;
1572
1573         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1574         crtc = intel_get_crtc_for_plane(dev, 0);
1575         if (intel_crtc_active(crtc)) {
1576                 const struct drm_display_mode *adjusted_mode;
1577                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1578                 if (IS_GEN2(dev))
1579                         cpp = 4;
1580
1581                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1582                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1583                                                wm_info, fifo_size, cpp,
1584                                                pessimal_latency_ns);
1585                 enabled = crtc;
1586         } else {
1587                 planea_wm = fifo_size - wm_info->guard_size;
1588                 if (planea_wm > (long)wm_info->max_wm)
1589                         planea_wm = wm_info->max_wm;
1590         }
1591
1592         if (IS_GEN2(dev))
1593                 wm_info = &i830_bc_wm_info;
1594
1595         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1596         crtc = intel_get_crtc_for_plane(dev, 1);
1597         if (intel_crtc_active(crtc)) {
1598                 const struct drm_display_mode *adjusted_mode;
1599                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1600                 if (IS_GEN2(dev))
1601                         cpp = 4;
1602
1603                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1604                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1605                                                wm_info, fifo_size, cpp,
1606                                                pessimal_latency_ns);
1607                 if (enabled == NULL)
1608                         enabled = crtc;
1609                 else
1610                         enabled = NULL;
1611         } else {
1612                 planeb_wm = fifo_size - wm_info->guard_size;
1613                 if (planeb_wm > (long)wm_info->max_wm)
1614                         planeb_wm = wm_info->max_wm;
1615         }
1616
1617         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1618
1619         if (IS_I915GM(dev) && enabled) {
1620                 struct drm_i915_gem_object *obj;
1621
1622                 obj = intel_fb_obj(enabled->primary->state->fb);
1623
1624                 /* self-refresh seems busted with untiled */
1625                 if (obj->tiling_mode == I915_TILING_NONE)
1626                         enabled = NULL;
1627         }
1628
1629         /*
1630          * Overlay gets an aggressive default since video jitter is bad.
1631          */
1632         cwm = 2;
1633
1634         /* Play safe and disable self-refresh before adjusting watermarks. */
1635         intel_set_memory_cxsr(dev_priv, false);
1636
1637         /* Calc sr entries for one plane configs */
1638         if (HAS_FW_BLC(dev) && enabled) {
1639                 /* self-refresh has much higher latency */
1640                 static const int sr_latency_ns = 6000;
1641                 const struct drm_display_mode *adjusted_mode =
1642                         &to_intel_crtc(enabled)->config->base.adjusted_mode;
1643                 int clock = adjusted_mode->crtc_clock;
1644                 int htotal = adjusted_mode->crtc_htotal;
1645                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1646                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1647                 unsigned long line_time_us;
1648                 int entries;
1649
1650                 line_time_us = max(htotal * 1000 / clock, 1);
1651
1652                 /* Use ns/us then divide to preserve precision */
1653                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1654                         pixel_size * hdisplay;
1655                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1656                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1657                 srwm = wm_info->fifo_size - entries;
1658                 if (srwm < 0)
1659                         srwm = 1;
1660
1661                 if (IS_I945G(dev) || IS_I945GM(dev))
1662                         I915_WRITE(FW_BLC_SELF,
1663                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1664                 else if (IS_I915GM(dev))
1665                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1666         }
1667
1668         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1669                       planea_wm, planeb_wm, cwm, srwm);
1670
1671         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1672         fwater_hi = (cwm & 0x1f);
1673
1674         /* Set request length to 8 cachelines per fetch */
1675         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1676         fwater_hi = fwater_hi | (1 << 8);
1677
1678         I915_WRITE(FW_BLC, fwater_lo);
1679         I915_WRITE(FW_BLC2, fwater_hi);
1680
1681         if (enabled)
1682                 intel_set_memory_cxsr(dev_priv, true);
1683 }
1684
1685 static void i845_update_wm(struct drm_crtc *unused_crtc)
1686 {
1687         struct drm_device *dev = unused_crtc->dev;
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         struct drm_crtc *crtc;
1690         const struct drm_display_mode *adjusted_mode;
1691         uint32_t fwater_lo;
1692         int planea_wm;
1693
1694         crtc = single_enabled_crtc(dev);
1695         if (crtc == NULL)
1696                 return;
1697
1698         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1699         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1700                                        &i845_wm_info,
1701                                        dev_priv->display.get_fifo_size(dev, 0),
1702                                        4, pessimal_latency_ns);
1703         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1704         fwater_lo |= (3<<8) | planea_wm;
1705
1706         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1707
1708         I915_WRITE(FW_BLC, fwater_lo);
1709 }
1710
1711 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1712 {
1713         uint32_t pixel_rate;
1714
1715         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1716
1717         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1718          * adjust the pixel_rate here. */
1719
1720         if (pipe_config->pch_pfit.enabled) {
1721                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1722                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1723
1724                 pipe_w = pipe_config->pipe_src_w;
1725                 pipe_h = pipe_config->pipe_src_h;
1726
1727                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1728                 pfit_h = pfit_size & 0xFFFF;
1729                 if (pipe_w < pfit_w)
1730                         pipe_w = pfit_w;
1731                 if (pipe_h < pfit_h)
1732                         pipe_h = pfit_h;
1733
1734                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1735                                      pfit_w * pfit_h);
1736         }
1737
1738         return pixel_rate;
1739 }
1740
1741 /* latency must be in 0.1us units. */
1742 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1743                                uint32_t latency)
1744 {
1745         uint64_t ret;
1746
1747         if (WARN(latency == 0, "Latency value missing\n"))
1748                 return UINT_MAX;
1749
1750         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1751         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1752
1753         return ret;
1754 }
1755
1756 /* latency must be in 0.1us units. */
1757 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1758                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1759                                uint32_t latency)
1760 {
1761         uint32_t ret;
1762
1763         if (WARN(latency == 0, "Latency value missing\n"))
1764                 return UINT_MAX;
1765
1766         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1767         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1768         ret = DIV_ROUND_UP(ret, 64) + 2;
1769         return ret;
1770 }
1771
1772 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1773                            uint8_t bytes_per_pixel)
1774 {
1775         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1776 }
1777
1778 struct skl_pipe_wm_parameters {
1779         bool active;
1780         uint32_t pipe_htotal;
1781         uint32_t pixel_rate; /* in KHz */
1782         struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1783         struct intel_plane_wm_parameters cursor;
1784 };
1785
1786 struct ilk_pipe_wm_parameters {
1787         bool active;
1788         uint32_t pipe_htotal;
1789         uint32_t pixel_rate;
1790         struct intel_plane_wm_parameters pri;
1791         struct intel_plane_wm_parameters spr;
1792         struct intel_plane_wm_parameters cur;
1793 };
1794
1795 struct ilk_wm_maximums {
1796         uint16_t pri;
1797         uint16_t spr;
1798         uint16_t cur;
1799         uint16_t fbc;
1800 };
1801
1802 /* used in computing the new watermarks state */
1803 struct intel_wm_config {
1804         unsigned int num_pipes_active;
1805         bool sprites_enabled;
1806         bool sprites_scaled;
1807 };
1808
1809 /*
1810  * For both WM_PIPE and WM_LP.
1811  * mem_value must be in 0.1us units.
1812  */
1813 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1814                                    uint32_t mem_value,
1815                                    bool is_lp)
1816 {
1817         uint32_t method1, method2;
1818
1819         if (!params->active || !params->pri.enabled)
1820                 return 0;
1821
1822         method1 = ilk_wm_method1(params->pixel_rate,
1823                                  params->pri.bytes_per_pixel,
1824                                  mem_value);
1825
1826         if (!is_lp)
1827                 return method1;
1828
1829         method2 = ilk_wm_method2(params->pixel_rate,
1830                                  params->pipe_htotal,
1831                                  params->pri.horiz_pixels,
1832                                  params->pri.bytes_per_pixel,
1833                                  mem_value);
1834
1835         return min(method1, method2);
1836 }
1837
1838 /*
1839  * For both WM_PIPE and WM_LP.
1840  * mem_value must be in 0.1us units.
1841  */
1842 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1843                                    uint32_t mem_value)
1844 {
1845         uint32_t method1, method2;
1846
1847         if (!params->active || !params->spr.enabled)
1848                 return 0;
1849
1850         method1 = ilk_wm_method1(params->pixel_rate,
1851                                  params->spr.bytes_per_pixel,
1852                                  mem_value);
1853         method2 = ilk_wm_method2(params->pixel_rate,
1854                                  params->pipe_htotal,
1855                                  params->spr.horiz_pixels,
1856                                  params->spr.bytes_per_pixel,
1857                                  mem_value);
1858         return min(method1, method2);
1859 }
1860
1861 /*
1862  * For both WM_PIPE and WM_LP.
1863  * mem_value must be in 0.1us units.
1864  */
1865 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1866                                    uint32_t mem_value)
1867 {
1868         if (!params->active || !params->cur.enabled)
1869                 return 0;
1870
1871         return ilk_wm_method2(params->pixel_rate,
1872                               params->pipe_htotal,
1873                               params->cur.horiz_pixels,
1874                               params->cur.bytes_per_pixel,
1875                               mem_value);
1876 }
1877
1878 /* Only for WM_LP. */
1879 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1880                                    uint32_t pri_val)
1881 {
1882         if (!params->active || !params->pri.enabled)
1883                 return 0;
1884
1885         return ilk_wm_fbc(pri_val,
1886                           params->pri.horiz_pixels,
1887                           params->pri.bytes_per_pixel);
1888 }
1889
1890 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1891 {
1892         if (INTEL_INFO(dev)->gen >= 8)
1893                 return 3072;
1894         else if (INTEL_INFO(dev)->gen >= 7)
1895                 return 768;
1896         else
1897                 return 512;
1898 }
1899
1900 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1901                                          int level, bool is_sprite)
1902 {
1903         if (INTEL_INFO(dev)->gen >= 8)
1904                 /* BDW primary/sprite plane watermarks */
1905                 return level == 0 ? 255 : 2047;
1906         else if (INTEL_INFO(dev)->gen >= 7)
1907                 /* IVB/HSW primary/sprite plane watermarks */
1908                 return level == 0 ? 127 : 1023;
1909         else if (!is_sprite)
1910                 /* ILK/SNB primary plane watermarks */
1911                 return level == 0 ? 127 : 511;
1912         else
1913                 /* ILK/SNB sprite plane watermarks */
1914                 return level == 0 ? 63 : 255;
1915 }
1916
1917 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1918                                           int level)
1919 {
1920         if (INTEL_INFO(dev)->gen >= 7)
1921                 return level == 0 ? 63 : 255;
1922         else
1923                 return level == 0 ? 31 : 63;
1924 }
1925
1926 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1927 {
1928         if (INTEL_INFO(dev)->gen >= 8)
1929                 return 31;
1930         else
1931                 return 15;
1932 }
1933
1934 /* Calculate the maximum primary/sprite plane watermark */
1935 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1936                                      int level,
1937                                      const struct intel_wm_config *config,
1938                                      enum intel_ddb_partitioning ddb_partitioning,
1939                                      bool is_sprite)
1940 {
1941         unsigned int fifo_size = ilk_display_fifo_size(dev);
1942
1943         /* if sprites aren't enabled, sprites get nothing */
1944         if (is_sprite && !config->sprites_enabled)
1945                 return 0;
1946
1947         /* HSW allows LP1+ watermarks even with multiple pipes */
1948         if (level == 0 || config->num_pipes_active > 1) {
1949                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1950
1951                 /*
1952                  * For some reason the non self refresh
1953                  * FIFO size is only half of the self
1954                  * refresh FIFO size on ILK/SNB.
1955                  */
1956                 if (INTEL_INFO(dev)->gen <= 6)
1957                         fifo_size /= 2;
1958         }
1959
1960         if (config->sprites_enabled) {
1961                 /* level 0 is always calculated with 1:1 split */
1962                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1963                         if (is_sprite)
1964                                 fifo_size *= 5;
1965                         fifo_size /= 6;
1966                 } else {
1967                         fifo_size /= 2;
1968                 }
1969         }
1970
1971         /* clamp to max that the registers can hold */
1972         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1973 }
1974
1975 /* Calculate the maximum cursor plane watermark */
1976 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1977                                       int level,
1978                                       const struct intel_wm_config *config)
1979 {
1980         /* HSW LP1+ watermarks w/ multiple pipes */
1981         if (level > 0 && config->num_pipes_active > 1)
1982                 return 64;
1983
1984         /* otherwise just report max that registers can hold */
1985         return ilk_cursor_wm_reg_max(dev, level);
1986 }
1987
1988 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1989                                     int level,
1990                                     const struct intel_wm_config *config,
1991                                     enum intel_ddb_partitioning ddb_partitioning,
1992                                     struct ilk_wm_maximums *max)
1993 {
1994         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1995         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1996         max->cur = ilk_cursor_wm_max(dev, level, config);
1997         max->fbc = ilk_fbc_wm_reg_max(dev);
1998 }
1999
2000 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2001                                         int level,
2002                                         struct ilk_wm_maximums *max)
2003 {
2004         max->pri = ilk_plane_wm_reg_max(dev, level, false);
2005         max->spr = ilk_plane_wm_reg_max(dev, level, true);
2006         max->cur = ilk_cursor_wm_reg_max(dev, level);
2007         max->fbc = ilk_fbc_wm_reg_max(dev);
2008 }
2009
2010 static bool ilk_validate_wm_level(int level,
2011                                   const struct ilk_wm_maximums *max,
2012                                   struct intel_wm_level *result)
2013 {
2014         bool ret;
2015
2016         /* already determined to be invalid? */
2017         if (!result->enable)
2018                 return false;
2019
2020         result->enable = result->pri_val <= max->pri &&
2021                          result->spr_val <= max->spr &&
2022                          result->cur_val <= max->cur;
2023
2024         ret = result->enable;
2025
2026         /*
2027          * HACK until we can pre-compute everything,
2028          * and thus fail gracefully if LP0 watermarks
2029          * are exceeded...
2030          */
2031         if (level == 0 && !result->enable) {
2032                 if (result->pri_val > max->pri)
2033                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2034                                       level, result->pri_val, max->pri);
2035                 if (result->spr_val > max->spr)
2036                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2037                                       level, result->spr_val, max->spr);
2038                 if (result->cur_val > max->cur)
2039                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2040                                       level, result->cur_val, max->cur);
2041
2042                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2043                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2044                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2045                 result->enable = true;
2046         }
2047
2048         return ret;
2049 }
2050
2051 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2052                                  int level,
2053                                  const struct ilk_pipe_wm_parameters *p,
2054                                  struct intel_wm_level *result)
2055 {
2056         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2057         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2058         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2059
2060         /* WM1+ latency values stored in 0.5us units */
2061         if (level > 0) {
2062                 pri_latency *= 5;
2063                 spr_latency *= 5;
2064                 cur_latency *= 5;
2065         }
2066
2067         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2068         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2069         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2070         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2071         result->enable = true;
2072 }
2073
2074 static uint32_t
2075 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2076 {
2077         struct drm_i915_private *dev_priv = dev->dev_private;
2078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079         struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
2080         u32 linetime, ips_linetime;
2081
2082         if (!intel_crtc->active)
2083                 return 0;
2084
2085         /* The WM are computed with base on how long it takes to fill a single
2086          * row at the given clock rate, multiplied by 8.
2087          * */
2088         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2089                                      mode->crtc_clock);
2090         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2091                                          dev_priv->cdclk_freq);
2092
2093         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2094                PIPE_WM_LINETIME_TIME(linetime);
2095 }
2096
2097 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2098 {
2099         struct drm_i915_private *dev_priv = dev->dev_private;
2100
2101         if (IS_GEN9(dev)) {
2102                 uint32_t val;
2103                 int ret, i;
2104                 int level, max_level = ilk_wm_max_level(dev);
2105
2106                 /* read the first set of memory latencies[0:3] */
2107                 val = 0; /* data0 to be programmed to 0 for first set */
2108                 mutex_lock(&dev_priv->rps.hw_lock);
2109                 ret = sandybridge_pcode_read(dev_priv,
2110                                              GEN9_PCODE_READ_MEM_LATENCY,
2111                                              &val);
2112                 mutex_unlock(&dev_priv->rps.hw_lock);
2113
2114                 if (ret) {
2115                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2116                         return;
2117                 }
2118
2119                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2120                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2121                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2122                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2123                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2124                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2125                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2126
2127                 /* read the second set of memory latencies[4:7] */
2128                 val = 1; /* data0 to be programmed to 1 for second set */
2129                 mutex_lock(&dev_priv->rps.hw_lock);
2130                 ret = sandybridge_pcode_read(dev_priv,
2131                                              GEN9_PCODE_READ_MEM_LATENCY,
2132                                              &val);
2133                 mutex_unlock(&dev_priv->rps.hw_lock);
2134                 if (ret) {
2135                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2136                         return;
2137                 }
2138
2139                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2140                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2141                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2142                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2143                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2144                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2145                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2146
2147                 /*
2148                  * WaWmMemoryReadLatency:skl
2149                  *
2150                  * punit doesn't take into account the read latency so we need
2151                  * to add 2us to the various latency levels we retrieve from
2152                  * the punit.
2153                  *   - W0 is a bit special in that it's the only level that
2154                  *   can't be disabled if we want to have display working, so
2155                  *   we always add 2us there.
2156                  *   - For levels >=1, punit returns 0us latency when they are
2157                  *   disabled, so we respect that and don't add 2us then
2158                  *
2159                  * Additionally, if a level n (n > 1) has a 0us latency, all
2160                  * levels m (m >= n) need to be disabled. We make sure to
2161                  * sanitize the values out of the punit to satisfy this
2162                  * requirement.
2163                  */
2164                 wm[0] += 2;
2165                 for (level = 1; level <= max_level; level++)
2166                         if (wm[level] != 0)
2167                                 wm[level] += 2;
2168                         else {
2169                                 for (i = level + 1; i <= max_level; i++)
2170                                         wm[i] = 0;
2171
2172                                 break;
2173                         }
2174         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2175                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2176
2177                 wm[0] = (sskpd >> 56) & 0xFF;
2178                 if (wm[0] == 0)
2179                         wm[0] = sskpd & 0xF;
2180                 wm[1] = (sskpd >> 4) & 0xFF;
2181                 wm[2] = (sskpd >> 12) & 0xFF;
2182                 wm[3] = (sskpd >> 20) & 0x1FF;
2183                 wm[4] = (sskpd >> 32) & 0x1FF;
2184         } else if (INTEL_INFO(dev)->gen >= 6) {
2185                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2186
2187                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2188                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2189                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2190                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2191         } else if (INTEL_INFO(dev)->gen >= 5) {
2192                 uint32_t mltr = I915_READ(MLTR_ILK);
2193
2194                 /* ILK primary LP0 latency is 700 ns */
2195                 wm[0] = 7;
2196                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2197                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2198         }
2199 }
2200
2201 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2202 {
2203         /* ILK sprite LP0 latency is 1300 ns */
2204         if (INTEL_INFO(dev)->gen == 5)
2205                 wm[0] = 13;
2206 }
2207
2208 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2209 {
2210         /* ILK cursor LP0 latency is 1300 ns */
2211         if (INTEL_INFO(dev)->gen == 5)
2212                 wm[0] = 13;
2213
2214         /* WaDoubleCursorLP3Latency:ivb */
2215         if (IS_IVYBRIDGE(dev))
2216                 wm[3] *= 2;
2217 }
2218
2219 int ilk_wm_max_level(const struct drm_device *dev)
2220 {
2221         /* how many WM levels are we expecting */
2222         if (INTEL_INFO(dev)->gen >= 9)
2223                 return 7;
2224         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2225                 return 4;
2226         else if (INTEL_INFO(dev)->gen >= 6)
2227                 return 3;
2228         else
2229                 return 2;
2230 }
2231
2232 static void intel_print_wm_latency(struct drm_device *dev,
2233                                    const char *name,
2234                                    const uint16_t wm[8])
2235 {
2236         int level, max_level = ilk_wm_max_level(dev);
2237
2238         for (level = 0; level <= max_level; level++) {
2239                 unsigned int latency = wm[level];
2240
2241                 if (latency == 0) {
2242                         DRM_ERROR("%s WM%d latency not provided\n",
2243                                   name, level);
2244                         continue;
2245                 }
2246
2247                 /*
2248                  * - latencies are in us on gen9.
2249                  * - before then, WM1+ latency values are in 0.5us units
2250                  */
2251                 if (IS_GEN9(dev))
2252                         latency *= 10;
2253                 else if (level > 0)
2254                         latency *= 5;
2255
2256                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2257                               name, level, wm[level],
2258                               latency / 10, latency % 10);
2259         }
2260 }
2261
2262 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2263                                     uint16_t wm[5], uint16_t min)
2264 {
2265         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2266
2267         if (wm[0] >= min)
2268                 return false;
2269
2270         wm[0] = max(wm[0], min);
2271         for (level = 1; level <= max_level; level++)
2272                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2273
2274         return true;
2275 }
2276
2277 static void snb_wm_latency_quirk(struct drm_device *dev)
2278 {
2279         struct drm_i915_private *dev_priv = dev->dev_private;
2280         bool changed;
2281
2282         /*
2283          * The BIOS provided WM memory latency values are often
2284          * inadequate for high resolution displays. Adjust them.
2285          */
2286         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2287                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2288                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2289
2290         if (!changed)
2291                 return;
2292
2293         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2294         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2295         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2296         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2297 }
2298
2299 static void ilk_setup_wm_latency(struct drm_device *dev)
2300 {
2301         struct drm_i915_private *dev_priv = dev->dev_private;
2302
2303         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2304
2305         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2306                sizeof(dev_priv->wm.pri_latency));
2307         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2308                sizeof(dev_priv->wm.pri_latency));
2309
2310         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2311         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2312
2313         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2314         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2315         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2316
2317         if (IS_GEN6(dev))
2318                 snb_wm_latency_quirk(dev);
2319 }
2320
2321 static void skl_setup_wm_latency(struct drm_device *dev)
2322 {
2323         struct drm_i915_private *dev_priv = dev->dev_private;
2324
2325         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2326         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2327 }
2328
2329 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2330                                       struct ilk_pipe_wm_parameters *p)
2331 {
2332         struct drm_device *dev = crtc->dev;
2333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2334         enum pipe pipe = intel_crtc->pipe;
2335         struct drm_plane *plane;
2336
2337         if (!intel_crtc->active)
2338                 return;
2339
2340         p->active = true;
2341         p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2342         p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
2343
2344         if (crtc->primary->state->fb)
2345                 p->pri.bytes_per_pixel =
2346                         crtc->primary->state->fb->bits_per_pixel / 8;
2347         else
2348                 p->pri.bytes_per_pixel = 4;
2349
2350         p->cur.bytes_per_pixel = 4;
2351         /*
2352          * TODO: for now, assume primary and cursor planes are always enabled.
2353          * Setting them to false makes the screen flicker.
2354          */
2355         p->pri.enabled = true;
2356         p->cur.enabled = true;
2357
2358         p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2359         p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2360
2361         drm_for_each_legacy_plane(plane, dev) {
2362                 struct intel_plane *intel_plane = to_intel_plane(plane);
2363
2364                 if (intel_plane->pipe == pipe) {
2365                         p->spr = intel_plane->wm;
2366                         break;
2367                 }
2368         }
2369 }
2370
2371 static void ilk_compute_wm_config(struct drm_device *dev,
2372                                   struct intel_wm_config *config)
2373 {
2374         struct intel_crtc *intel_crtc;
2375
2376         /* Compute the currently _active_ config */
2377         for_each_intel_crtc(dev, intel_crtc) {
2378                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2379
2380                 if (!wm->pipe_enabled)
2381                         continue;
2382
2383                 config->sprites_enabled |= wm->sprites_enabled;
2384                 config->sprites_scaled |= wm->sprites_scaled;
2385                 config->num_pipes_active++;
2386         }
2387 }
2388
2389 /* Compute new watermarks for the pipe */
2390 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2391                                   const struct ilk_pipe_wm_parameters *params,
2392                                   struct intel_pipe_wm *pipe_wm)
2393 {
2394         struct drm_device *dev = crtc->dev;
2395         const struct drm_i915_private *dev_priv = dev->dev_private;
2396         int level, max_level = ilk_wm_max_level(dev);
2397         /* LP0 watermark maximums depend on this pipe alone */
2398         struct intel_wm_config config = {
2399                 .num_pipes_active = 1,
2400                 .sprites_enabled = params->spr.enabled,
2401                 .sprites_scaled = params->spr.scaled,
2402         };
2403         struct ilk_wm_maximums max;
2404
2405         pipe_wm->pipe_enabled = params->active;
2406         pipe_wm->sprites_enabled = params->spr.enabled;
2407         pipe_wm->sprites_scaled = params->spr.scaled;
2408
2409         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2410         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2411                 max_level = 1;
2412
2413         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2414         if (params->spr.scaled)
2415                 max_level = 0;
2416
2417         ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2418
2419         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2420                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2421
2422         /* LP0 watermarks always use 1/2 DDB partitioning */
2423         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2424
2425         /* At least LP0 must be valid */
2426         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2427                 return false;
2428
2429         ilk_compute_wm_reg_maximums(dev, 1, &max);
2430
2431         for (level = 1; level <= max_level; level++) {
2432                 struct intel_wm_level wm = {};
2433
2434                 ilk_compute_wm_level(dev_priv, level, params, &wm);
2435
2436                 /*
2437                  * Disable any watermark level that exceeds the
2438                  * register maximums since such watermarks are
2439                  * always invalid.
2440                  */
2441                 if (!ilk_validate_wm_level(level, &max, &wm))
2442                         break;
2443
2444                 pipe_wm->wm[level] = wm;
2445         }
2446
2447         return true;
2448 }
2449
2450 /*
2451  * Merge the watermarks from all active pipes for a specific level.
2452  */
2453 static void ilk_merge_wm_level(struct drm_device *dev,
2454                                int level,
2455                                struct intel_wm_level *ret_wm)
2456 {
2457         const struct intel_crtc *intel_crtc;
2458
2459         ret_wm->enable = true;
2460
2461         for_each_intel_crtc(dev, intel_crtc) {
2462                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2463                 const struct intel_wm_level *wm = &active->wm[level];
2464
2465                 if (!active->pipe_enabled)
2466                         continue;
2467
2468                 /*
2469                  * The watermark values may have been used in the past,
2470                  * so we must maintain them in the registers for some
2471                  * time even if the level is now disabled.
2472                  */
2473                 if (!wm->enable)
2474                         ret_wm->enable = false;
2475
2476                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2477                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2478                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2479                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2480         }
2481 }
2482
2483 /*
2484  * Merge all low power watermarks for all active pipes.
2485  */
2486 static void ilk_wm_merge(struct drm_device *dev,
2487                          const struct intel_wm_config *config,
2488                          const struct ilk_wm_maximums *max,
2489                          struct intel_pipe_wm *merged)
2490 {
2491         struct drm_i915_private *dev_priv = dev->dev_private;
2492         int level, max_level = ilk_wm_max_level(dev);
2493         int last_enabled_level = max_level;
2494
2495         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2496         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2497             config->num_pipes_active > 1)
2498                 return;
2499
2500         /* ILK: FBC WM must be disabled always */
2501         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2502
2503         /* merge each WM1+ level */
2504         for (level = 1; level <= max_level; level++) {
2505                 struct intel_wm_level *wm = &merged->wm[level];
2506
2507                 ilk_merge_wm_level(dev, level, wm);
2508
2509                 if (level > last_enabled_level)
2510                         wm->enable = false;
2511                 else if (!ilk_validate_wm_level(level, max, wm))
2512                         /* make sure all following levels get disabled */
2513                         last_enabled_level = level - 1;
2514
2515                 /*
2516                  * The spec says it is preferred to disable
2517                  * FBC WMs instead of disabling a WM level.
2518                  */
2519                 if (wm->fbc_val > max->fbc) {
2520                         if (wm->enable)
2521                                 merged->fbc_wm_enabled = false;
2522                         wm->fbc_val = 0;
2523                 }
2524         }
2525
2526         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2527         /*
2528          * FIXME this is racy. FBC might get enabled later.
2529          * What we should check here is whether FBC can be
2530          * enabled sometime later.
2531          */
2532         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2533             intel_fbc_enabled(dev_priv)) {
2534                 for (level = 2; level <= max_level; level++) {
2535                         struct intel_wm_level *wm = &merged->wm[level];
2536
2537                         wm->enable = false;
2538                 }
2539         }
2540 }
2541
2542 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2543 {
2544         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2545         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2546 }
2547
2548 /* The value we need to program into the WM_LPx latency field */
2549 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2550 {
2551         struct drm_i915_private *dev_priv = dev->dev_private;
2552
2553         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2554                 return 2 * level;
2555         else
2556                 return dev_priv->wm.pri_latency[level];
2557 }
2558
2559 static void ilk_compute_wm_results(struct drm_device *dev,
2560                                    const struct intel_pipe_wm *merged,
2561                                    enum intel_ddb_partitioning partitioning,
2562                                    struct ilk_wm_values *results)
2563 {
2564         struct intel_crtc *intel_crtc;
2565         int level, wm_lp;
2566
2567         results->enable_fbc_wm = merged->fbc_wm_enabled;
2568         results->partitioning = partitioning;
2569
2570         /* LP1+ register values */
2571         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2572                 const struct intel_wm_level *r;
2573
2574                 level = ilk_wm_lp_to_level(wm_lp, merged);
2575
2576                 r = &merged->wm[level];
2577
2578                 /*
2579                  * Maintain the watermark values even if the level is
2580                  * disabled. Doing otherwise could cause underruns.
2581                  */
2582                 results->wm_lp[wm_lp - 1] =
2583                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2584                         (r->pri_val << WM1_LP_SR_SHIFT) |
2585                         r->cur_val;
2586
2587                 if (r->enable)
2588                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2589
2590                 if (INTEL_INFO(dev)->gen >= 8)
2591                         results->wm_lp[wm_lp - 1] |=
2592                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2593                 else
2594                         results->wm_lp[wm_lp - 1] |=
2595                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2596
2597                 /*
2598                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2599                  * level is disabled. Doing otherwise could cause underruns.
2600                  */
2601                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2602                         WARN_ON(wm_lp != 1);
2603                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2604                 } else
2605                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2606         }
2607
2608         /* LP0 register values */
2609         for_each_intel_crtc(dev, intel_crtc) {
2610                 enum pipe pipe = intel_crtc->pipe;
2611                 const struct intel_wm_level *r =
2612                         &intel_crtc->wm.active.wm[0];
2613
2614                 if (WARN_ON(!r->enable))
2615                         continue;
2616
2617                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2618
2619                 results->wm_pipe[pipe] =
2620                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2621                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2622                         r->cur_val;
2623         }
2624 }
2625
2626 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2627  * case both are at the same level. Prefer r1 in case they're the same. */
2628 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2629                                                   struct intel_pipe_wm *r1,
2630                                                   struct intel_pipe_wm *r2)
2631 {
2632         int level, max_level = ilk_wm_max_level(dev);
2633         int level1 = 0, level2 = 0;
2634
2635         for (level = 1; level <= max_level; level++) {
2636                 if (r1->wm[level].enable)
2637                         level1 = level;
2638                 if (r2->wm[level].enable)
2639                         level2 = level;
2640         }
2641
2642         if (level1 == level2) {
2643                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2644                         return r2;
2645                 else
2646                         return r1;
2647         } else if (level1 > level2) {
2648                 return r1;
2649         } else {
2650                 return r2;
2651         }
2652 }
2653
2654 /* dirty bits used to track which watermarks need changes */
2655 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2656 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2657 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2658 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2659 #define WM_DIRTY_FBC (1 << 24)
2660 #define WM_DIRTY_DDB (1 << 25)
2661
2662 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2663                                          const struct ilk_wm_values *old,
2664                                          const struct ilk_wm_values *new)
2665 {
2666         unsigned int dirty = 0;
2667         enum pipe pipe;
2668         int wm_lp;
2669
2670         for_each_pipe(dev_priv, pipe) {
2671                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2672                         dirty |= WM_DIRTY_LINETIME(pipe);
2673                         /* Must disable LP1+ watermarks too */
2674                         dirty |= WM_DIRTY_LP_ALL;
2675                 }
2676
2677                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2678                         dirty |= WM_DIRTY_PIPE(pipe);
2679                         /* Must disable LP1+ watermarks too */
2680                         dirty |= WM_DIRTY_LP_ALL;
2681                 }
2682         }
2683
2684         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2685                 dirty |= WM_DIRTY_FBC;
2686                 /* Must disable LP1+ watermarks too */
2687                 dirty |= WM_DIRTY_LP_ALL;
2688         }
2689
2690         if (old->partitioning != new->partitioning) {
2691                 dirty |= WM_DIRTY_DDB;
2692                 /* Must disable LP1+ watermarks too */
2693                 dirty |= WM_DIRTY_LP_ALL;
2694         }
2695
2696         /* LP1+ watermarks already deemed dirty, no need to continue */
2697         if (dirty & WM_DIRTY_LP_ALL)
2698                 return dirty;
2699
2700         /* Find the lowest numbered LP1+ watermark in need of an update... */
2701         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2702                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2703                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2704                         break;
2705         }
2706
2707         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2708         for (; wm_lp <= 3; wm_lp++)
2709                 dirty |= WM_DIRTY_LP(wm_lp);
2710
2711         return dirty;
2712 }
2713
2714 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2715                                unsigned int dirty)
2716 {
2717         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2718         bool changed = false;
2719
2720         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2721                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2722                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2723                 changed = true;
2724         }
2725         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2726                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2727                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2728                 changed = true;
2729         }
2730         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2731                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2732                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2733                 changed = true;
2734         }
2735
2736         /*
2737          * Don't touch WM1S_LP_EN here.
2738          * Doing so could cause underruns.
2739          */
2740
2741         return changed;
2742 }
2743
2744 /*
2745  * The spec says we shouldn't write when we don't need, because every write
2746  * causes WMs to be re-evaluated, expending some power.
2747  */
2748 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2749                                 struct ilk_wm_values *results)
2750 {
2751         struct drm_device *dev = dev_priv->dev;
2752         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2753         unsigned int dirty;
2754         uint32_t val;
2755
2756         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2757         if (!dirty)
2758                 return;
2759
2760         _ilk_disable_lp_wm(dev_priv, dirty);
2761
2762         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2763                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2764         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2765                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2766         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2767                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2768
2769         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2770                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2771         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2772                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2773         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2774                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2775
2776         if (dirty & WM_DIRTY_DDB) {
2777                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2778                         val = I915_READ(WM_MISC);
2779                         if (results->partitioning == INTEL_DDB_PART_1_2)
2780                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2781                         else
2782                                 val |= WM_MISC_DATA_PARTITION_5_6;
2783                         I915_WRITE(WM_MISC, val);
2784                 } else {
2785                         val = I915_READ(DISP_ARB_CTL2);
2786                         if (results->partitioning == INTEL_DDB_PART_1_2)
2787                                 val &= ~DISP_DATA_PARTITION_5_6;
2788                         else
2789                                 val |= DISP_DATA_PARTITION_5_6;
2790                         I915_WRITE(DISP_ARB_CTL2, val);
2791                 }
2792         }
2793
2794         if (dirty & WM_DIRTY_FBC) {
2795                 val = I915_READ(DISP_ARB_CTL);
2796                 if (results->enable_fbc_wm)
2797                         val &= ~DISP_FBC_WM_DIS;
2798                 else
2799                         val |= DISP_FBC_WM_DIS;
2800                 I915_WRITE(DISP_ARB_CTL, val);
2801         }
2802
2803         if (dirty & WM_DIRTY_LP(1) &&
2804             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2805                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2806
2807         if (INTEL_INFO(dev)->gen >= 7) {
2808                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2809                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2810                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2811                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2812         }
2813
2814         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2815                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2816         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2817                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2818         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2819                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2820
2821         dev_priv->wm.hw = *results;
2822 }
2823
2824 static bool ilk_disable_lp_wm(struct drm_device *dev)
2825 {
2826         struct drm_i915_private *dev_priv = dev->dev_private;
2827
2828         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2829 }
2830
2831 /*
2832  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2833  * different active planes.
2834  */
2835
2836 #define SKL_DDB_SIZE            896     /* in blocks */
2837 #define BXT_DDB_SIZE            512
2838
2839 static void
2840 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2841                                    struct drm_crtc *for_crtc,
2842                                    const struct intel_wm_config *config,
2843                                    const struct skl_pipe_wm_parameters *params,
2844                                    struct skl_ddb_entry *alloc /* out */)
2845 {
2846         struct drm_crtc *crtc;
2847         unsigned int pipe_size, ddb_size;
2848         int nth_active_pipe;
2849
2850         if (!params->active) {
2851                 alloc->start = 0;
2852                 alloc->end = 0;
2853                 return;
2854         }
2855
2856         if (IS_BROXTON(dev))
2857                 ddb_size = BXT_DDB_SIZE;
2858         else
2859                 ddb_size = SKL_DDB_SIZE;
2860
2861         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2862
2863         nth_active_pipe = 0;
2864         for_each_crtc(dev, crtc) {
2865                 if (!to_intel_crtc(crtc)->active)
2866                         continue;
2867
2868                 if (crtc == for_crtc)
2869                         break;
2870
2871                 nth_active_pipe++;
2872         }
2873
2874         pipe_size = ddb_size / config->num_pipes_active;
2875         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2876         alloc->end = alloc->start + pipe_size;
2877 }
2878
2879 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2880 {
2881         if (config->num_pipes_active == 1)
2882                 return 32;
2883
2884         return 8;
2885 }
2886
2887 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2888 {
2889         entry->start = reg & 0x3ff;
2890         entry->end = (reg >> 16) & 0x3ff;
2891         if (entry->end)
2892                 entry->end += 1;
2893 }
2894
2895 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2896                           struct skl_ddb_allocation *ddb /* out */)
2897 {
2898         enum pipe pipe;
2899         int plane;
2900         u32 val;
2901
2902         memset(ddb, 0, sizeof(*ddb));
2903
2904         for_each_pipe(dev_priv, pipe) {
2905                 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2906                         continue;
2907
2908                 for_each_plane(dev_priv, pipe, plane) {
2909                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2910                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2911                                                    val);
2912                 }
2913
2914                 val = I915_READ(CUR_BUF_CFG(pipe));
2915                 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2916         }
2917 }
2918
2919 static unsigned int
2920 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2921 {
2922
2923         /* for planar format */
2924         if (p->y_bytes_per_pixel) {
2925                 if (y)  /* y-plane data rate */
2926                         return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2927                 else    /* uv-plane data rate */
2928                         return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2929         }
2930
2931         /* for packed formats */
2932         return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2933 }
2934
2935 /*
2936  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2937  * a 8192x4096@32bpp framebuffer:
2938  *   3 * 4096 * 8192  * 4 < 2^32
2939  */
2940 static unsigned int
2941 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2942                                  const struct skl_pipe_wm_parameters *params)
2943 {
2944         unsigned int total_data_rate = 0;
2945         int plane;
2946
2947         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2948                 const struct intel_plane_wm_parameters *p;
2949
2950                 p = &params->plane[plane];
2951                 if (!p->enabled)
2952                         continue;
2953
2954                 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2955                 if (p->y_bytes_per_pixel) {
2956                         total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2957                 }
2958         }
2959
2960         return total_data_rate;
2961 }
2962
2963 static void
2964 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2965                       const struct intel_wm_config *config,
2966                       const struct skl_pipe_wm_parameters *params,
2967                       struct skl_ddb_allocation *ddb /* out */)
2968 {
2969         struct drm_device *dev = crtc->dev;
2970         struct drm_i915_private *dev_priv = dev->dev_private;
2971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2972         enum pipe pipe = intel_crtc->pipe;
2973         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2974         uint16_t alloc_size, start, cursor_blocks;
2975         uint16_t minimum[I915_MAX_PLANES];
2976         uint16_t y_minimum[I915_MAX_PLANES];
2977         unsigned int total_data_rate;
2978         int plane;
2979
2980         skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2981         alloc_size = skl_ddb_entry_size(alloc);
2982         if (alloc_size == 0) {
2983                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2984                 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2985                 return;
2986         }
2987
2988         cursor_blocks = skl_cursor_allocation(config);
2989         ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2990         ddb->cursor[pipe].end = alloc->end;
2991
2992         alloc_size -= cursor_blocks;
2993         alloc->end -= cursor_blocks;
2994
2995         /* 1. Allocate the mininum required blocks for each active plane */
2996         for_each_plane(dev_priv, pipe, plane) {
2997                 const struct intel_plane_wm_parameters *p;
2998
2999                 p = &params->plane[plane];
3000                 if (!p->enabled)
3001                         continue;
3002
3003                 minimum[plane] = 8;
3004                 alloc_size -= minimum[plane];
3005                 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
3006                 alloc_size -= y_minimum[plane];
3007         }
3008
3009         /*
3010          * 2. Distribute the remaining space in proportion to the amount of
3011          * data each plane needs to fetch from memory.
3012          *
3013          * FIXME: we may not allocate every single block here.
3014          */
3015         total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3016
3017         start = alloc->start;
3018         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3019                 const struct intel_plane_wm_parameters *p;
3020                 unsigned int data_rate, y_data_rate;
3021                 uint16_t plane_blocks, y_plane_blocks = 0;
3022
3023                 p = &params->plane[plane];
3024                 if (!p->enabled)
3025                         continue;
3026
3027                 data_rate = skl_plane_relative_data_rate(p, 0);
3028
3029                 /*
3030                  * allocation for (packed formats) or (uv-plane part of planar format):
3031                  * promote the expression to 64 bits to avoid overflowing, the
3032                  * result is < available as data_rate / total_data_rate < 1
3033                  */
3034                 plane_blocks = minimum[plane];
3035                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3036                                         total_data_rate);
3037
3038                 ddb->plane[pipe][plane].start = start;
3039                 ddb->plane[pipe][plane].end = start + plane_blocks;
3040
3041                 start += plane_blocks;
3042
3043                 /*
3044                  * allocation for y_plane part of planar format:
3045                  */
3046                 if (p->y_bytes_per_pixel) {
3047                         y_data_rate = skl_plane_relative_data_rate(p, 1);
3048                         y_plane_blocks = y_minimum[plane];
3049                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3050                                                 total_data_rate);
3051
3052                         ddb->y_plane[pipe][plane].start = start;
3053                         ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3054
3055                         start += y_plane_blocks;
3056                 }
3057
3058         }
3059
3060 }
3061
3062 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3063 {
3064         /* TODO: Take into account the scalers once we support them */
3065         return config->base.adjusted_mode.crtc_clock;
3066 }
3067
3068 /*
3069  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3070  * for the read latency) and bytes_per_pixel should always be <= 8, so that
3071  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3072  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3073 */
3074 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3075                                uint32_t latency)
3076 {
3077         uint32_t wm_intermediate_val, ret;
3078
3079         if (latency == 0)
3080                 return UINT_MAX;
3081
3082         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3083         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3084
3085         return ret;
3086 }
3087
3088 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3089                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3090                                uint64_t tiling, uint32_t latency)
3091 {
3092         uint32_t ret;
3093         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3094         uint32_t wm_intermediate_val;
3095
3096         if (latency == 0)
3097                 return UINT_MAX;
3098
3099         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3100
3101         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3102             tiling == I915_FORMAT_MOD_Yf_TILED) {
3103                 plane_bytes_per_line *= 4;
3104                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3105                 plane_blocks_per_line /= 4;
3106         } else {
3107                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3108         }
3109
3110         wm_intermediate_val = latency * pixel_rate;
3111         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3112                                 plane_blocks_per_line;
3113
3114         return ret;
3115 }
3116
3117 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3118                                        const struct intel_crtc *intel_crtc)
3119 {
3120         struct drm_device *dev = intel_crtc->base.dev;
3121         struct drm_i915_private *dev_priv = dev->dev_private;
3122         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3123         enum pipe pipe = intel_crtc->pipe;
3124
3125         if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3126                    sizeof(new_ddb->plane[pipe])))
3127                 return true;
3128
3129         if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3130                     sizeof(new_ddb->cursor[pipe])))
3131                 return true;
3132
3133         return false;
3134 }
3135
3136 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3137                                              struct intel_wm_config *config)
3138 {
3139         struct drm_crtc *crtc;
3140         struct drm_plane *plane;
3141
3142         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3143                 config->num_pipes_active += to_intel_crtc(crtc)->active;
3144
3145         /* FIXME: I don't think we need those two global parameters on SKL */
3146         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3147                 struct intel_plane *intel_plane = to_intel_plane(plane);
3148
3149                 config->sprites_enabled |= intel_plane->wm.enabled;
3150                 config->sprites_scaled |= intel_plane->wm.scaled;
3151         }
3152 }
3153
3154 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3155                                            struct skl_pipe_wm_parameters *p)
3156 {
3157         struct drm_device *dev = crtc->dev;
3158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3159         enum pipe pipe = intel_crtc->pipe;
3160         struct drm_plane *plane;
3161         struct drm_framebuffer *fb;
3162         int i = 1; /* Index for sprite planes start */
3163
3164         p->active = intel_crtc->active;
3165         if (p->active) {
3166                 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3167                 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3168
3169                 fb = crtc->primary->state->fb;
3170                 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3171                 if (fb) {
3172                         p->plane[0].enabled = true;
3173                         p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3174                                 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
3175                         p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3176                                 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3177                         p->plane[0].tiling = fb->modifier[0];
3178                 } else {
3179                         p->plane[0].enabled = false;
3180                         p->plane[0].bytes_per_pixel = 0;
3181                         p->plane[0].y_bytes_per_pixel = 0;
3182                         p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3183                 }
3184                 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3185                 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3186                 p->plane[0].rotation = crtc->primary->state->rotation;
3187
3188                 fb = crtc->cursor->state->fb;
3189                 p->cursor.y_bytes_per_pixel = 0;
3190                 if (fb) {
3191                         p->cursor.enabled = true;
3192                         p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3193                         p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3194                         p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3195                 } else {
3196                         p->cursor.enabled = false;
3197                         p->cursor.bytes_per_pixel = 0;
3198                         p->cursor.horiz_pixels = 64;
3199                         p->cursor.vert_pixels = 64;
3200                 }
3201         }
3202
3203         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3204                 struct intel_plane *intel_plane = to_intel_plane(plane);
3205
3206                 if (intel_plane->pipe == pipe &&
3207                         plane->type == DRM_PLANE_TYPE_OVERLAY)
3208                         p->plane[i++] = intel_plane->wm;
3209         }
3210 }
3211
3212 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3213                                  struct skl_pipe_wm_parameters *p,
3214                                  struct intel_plane_wm_parameters *p_params,
3215                                  uint16_t ddb_allocation,
3216                                  int level,
3217                                  uint16_t *out_blocks, /* out */
3218                                  uint8_t *out_lines /* out */)
3219 {
3220         uint32_t latency = dev_priv->wm.skl_latency[level];
3221         uint32_t method1, method2;
3222         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3223         uint32_t res_blocks, res_lines;
3224         uint32_t selected_result;
3225         uint8_t bytes_per_pixel;
3226
3227         if (latency == 0 || !p->active || !p_params->enabled)
3228                 return false;
3229
3230         bytes_per_pixel = p_params->y_bytes_per_pixel ?
3231                 p_params->y_bytes_per_pixel :
3232                 p_params->bytes_per_pixel;
3233         method1 = skl_wm_method1(p->pixel_rate,
3234                                  bytes_per_pixel,
3235                                  latency);
3236         method2 = skl_wm_method2(p->pixel_rate,
3237                                  p->pipe_htotal,
3238                                  p_params->horiz_pixels,
3239                                  bytes_per_pixel,
3240                                  p_params->tiling,
3241                                  latency);
3242
3243         plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3244         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3245
3246         if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3247             p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3248                 uint32_t min_scanlines = 4;
3249                 uint32_t y_tile_minimum;
3250                 if (intel_rotation_90_or_270(p_params->rotation)) {
3251                         switch (p_params->bytes_per_pixel) {
3252                         case 1:
3253                                 min_scanlines = 16;
3254                                 break;
3255                         case 2:
3256                                 min_scanlines = 8;
3257                                 break;
3258                         case 8:
3259                                 WARN(1, "Unsupported pixel depth for rotation");
3260                         }
3261                 }
3262                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3263                 selected_result = max(method2, y_tile_minimum);
3264         } else {
3265                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3266                         selected_result = min(method1, method2);
3267                 else
3268                         selected_result = method1;
3269         }
3270
3271         res_blocks = selected_result + 1;
3272         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3273
3274         if (level >= 1 && level <= 7) {
3275                 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3276                     p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3277                         res_lines += 4;
3278                 else
3279                         res_blocks++;
3280         }
3281
3282         if (res_blocks >= ddb_allocation || res_lines > 31)
3283                 return false;
3284
3285         *out_blocks = res_blocks;
3286         *out_lines = res_lines;
3287
3288         return true;
3289 }
3290
3291 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3292                                  struct skl_ddb_allocation *ddb,
3293                                  struct skl_pipe_wm_parameters *p,
3294                                  enum pipe pipe,
3295                                  int level,
3296                                  int num_planes,
3297                                  struct skl_wm_level *result)
3298 {
3299         uint16_t ddb_blocks;
3300         int i;
3301
3302         for (i = 0; i < num_planes; i++) {
3303                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3304
3305                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3306                                                 p, &p->plane[i],
3307                                                 ddb_blocks,
3308                                                 level,
3309                                                 &result->plane_res_b[i],
3310                                                 &result->plane_res_l[i]);
3311         }
3312
3313         ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
3314         result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3315                                                  ddb_blocks, level,
3316                                                  &result->cursor_res_b,
3317                                                  &result->cursor_res_l);
3318 }
3319
3320 static uint32_t
3321 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3322 {
3323         if (!to_intel_crtc(crtc)->active)
3324                 return 0;
3325
3326         if (WARN_ON(p->pixel_rate == 0))
3327                 return 0;
3328
3329         return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3330 }
3331
3332 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3333                                       struct skl_pipe_wm_parameters *params,
3334                                       struct skl_wm_level *trans_wm /* out */)
3335 {
3336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337         int i;
3338
3339         if (!params->active)
3340                 return;
3341
3342         /* Until we know more, just disable transition WMs */
3343         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3344                 trans_wm->plane_en[i] = false;
3345         trans_wm->cursor_en = false;
3346 }
3347
3348 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3349                                 struct skl_ddb_allocation *ddb,
3350                                 struct skl_pipe_wm_parameters *params,
3351                                 struct skl_pipe_wm *pipe_wm)
3352 {
3353         struct drm_device *dev = crtc->dev;
3354         const struct drm_i915_private *dev_priv = dev->dev_private;
3355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356         int level, max_level = ilk_wm_max_level(dev);
3357
3358         for (level = 0; level <= max_level; level++) {
3359                 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3360                                      level, intel_num_planes(intel_crtc),
3361                                      &pipe_wm->wm[level]);
3362         }
3363         pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3364
3365         skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3366 }
3367
3368 static void skl_compute_wm_results(struct drm_device *dev,
3369                                    struct skl_pipe_wm_parameters *p,
3370                                    struct skl_pipe_wm *p_wm,
3371                                    struct skl_wm_values *r,
3372                                    struct intel_crtc *intel_crtc)
3373 {
3374         int level, max_level = ilk_wm_max_level(dev);
3375         enum pipe pipe = intel_crtc->pipe;
3376         uint32_t temp;
3377         int i;
3378
3379         for (level = 0; level <= max_level; level++) {
3380                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3381                         temp = 0;
3382
3383                         temp |= p_wm->wm[level].plane_res_l[i] <<
3384                                         PLANE_WM_LINES_SHIFT;
3385                         temp |= p_wm->wm[level].plane_res_b[i];
3386                         if (p_wm->wm[level].plane_en[i])
3387                                 temp |= PLANE_WM_EN;
3388
3389                         r->plane[pipe][i][level] = temp;
3390                 }
3391
3392                 temp = 0;
3393
3394                 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3395                 temp |= p_wm->wm[level].cursor_res_b;
3396
3397                 if (p_wm->wm[level].cursor_en)
3398                         temp |= PLANE_WM_EN;
3399
3400                 r->cursor[pipe][level] = temp;
3401
3402         }
3403
3404         /* transition WMs */
3405         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3406                 temp = 0;
3407                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3408                 temp |= p_wm->trans_wm.plane_res_b[i];
3409                 if (p_wm->trans_wm.plane_en[i])
3410                         temp |= PLANE_WM_EN;
3411
3412                 r->plane_trans[pipe][i] = temp;
3413         }
3414
3415         temp = 0;
3416         temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3417         temp |= p_wm->trans_wm.cursor_res_b;
3418         if (p_wm->trans_wm.cursor_en)
3419                 temp |= PLANE_WM_EN;
3420
3421         r->cursor_trans[pipe] = temp;
3422
3423         r->wm_linetime[pipe] = p_wm->linetime;
3424 }
3425
3426 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3427                                 const struct skl_ddb_entry *entry)
3428 {
3429         if (entry->end)
3430                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3431         else
3432                 I915_WRITE(reg, 0);
3433 }
3434
3435 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3436                                 const struct skl_wm_values *new)
3437 {
3438         struct drm_device *dev = dev_priv->dev;
3439         struct intel_crtc *crtc;
3440
3441         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3442                 int i, level, max_level = ilk_wm_max_level(dev);
3443                 enum pipe pipe = crtc->pipe;
3444
3445                 if (!new->dirty[pipe])
3446                         continue;
3447
3448                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3449
3450                 for (level = 0; level <= max_level; level++) {
3451                         for (i = 0; i < intel_num_planes(crtc); i++)
3452                                 I915_WRITE(PLANE_WM(pipe, i, level),
3453                                            new->plane[pipe][i][level]);
3454                         I915_WRITE(CUR_WM(pipe, level),
3455                                    new->cursor[pipe][level]);
3456                 }
3457                 for (i = 0; i < intel_num_planes(crtc); i++)
3458                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3459                                    new->plane_trans[pipe][i]);
3460                 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3461
3462                 for (i = 0; i < intel_num_planes(crtc); i++) {
3463                         skl_ddb_entry_write(dev_priv,
3464                                             PLANE_BUF_CFG(pipe, i),
3465                                             &new->ddb.plane[pipe][i]);
3466                         skl_ddb_entry_write(dev_priv,
3467                                             PLANE_NV12_BUF_CFG(pipe, i),
3468                                             &new->ddb.y_plane[pipe][i]);
3469                 }
3470
3471                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3472                                     &new->ddb.cursor[pipe]);
3473         }
3474 }
3475
3476 /*
3477  * When setting up a new DDB allocation arrangement, we need to correctly
3478  * sequence the times at which the new allocations for the pipes are taken into
3479  * account or we'll have pipes fetching from space previously allocated to
3480  * another pipe.
3481  *
3482  * Roughly the sequence looks like:
3483  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3484  *     overlapping with a previous light-up pipe (another way to put it is:
3485  *     pipes with their new allocation strickly included into their old ones).
3486  *  2. re-allocate the other pipes that get their allocation reduced
3487  *  3. allocate the pipes having their allocation increased
3488  *
3489  * Steps 1. and 2. are here to take care of the following case:
3490  * - Initially DDB looks like this:
3491  *     |   B    |   C    |
3492  * - enable pipe A.
3493  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3494  *   allocation
3495  *     |  A  |  B  |  C  |
3496  *
3497  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3498  */
3499
3500 static void
3501 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3502 {
3503         int plane;
3504
3505         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3506
3507         for_each_plane(dev_priv, pipe, plane) {
3508                 I915_WRITE(PLANE_SURF(pipe, plane),
3509                            I915_READ(PLANE_SURF(pipe, plane)));
3510         }
3511         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3512 }
3513
3514 static bool
3515 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3516                             const struct skl_ddb_allocation *new,
3517                             enum pipe pipe)
3518 {
3519         uint16_t old_size, new_size;
3520
3521         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3522         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3523
3524         return old_size != new_size &&
3525                new->pipe[pipe].start >= old->pipe[pipe].start &&
3526                new->pipe[pipe].end <= old->pipe[pipe].end;
3527 }
3528
3529 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3530                                 struct skl_wm_values *new_values)
3531 {
3532         struct drm_device *dev = dev_priv->dev;
3533         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3534         bool reallocated[I915_MAX_PIPES] = {};
3535         struct intel_crtc *crtc;
3536         enum pipe pipe;
3537
3538         new_ddb = &new_values->ddb;
3539         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3540
3541         /*
3542          * First pass: flush the pipes with the new allocation contained into
3543          * the old space.
3544          *
3545          * We'll wait for the vblank on those pipes to ensure we can safely
3546          * re-allocate the freed space without this pipe fetching from it.
3547          */
3548         for_each_intel_crtc(dev, crtc) {
3549                 if (!crtc->active)
3550                         continue;
3551
3552                 pipe = crtc->pipe;
3553
3554                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3555                         continue;
3556
3557                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3558                 intel_wait_for_vblank(dev, pipe);
3559
3560                 reallocated[pipe] = true;
3561         }
3562
3563
3564         /*
3565          * Second pass: flush the pipes that are having their allocation
3566          * reduced, but overlapping with a previous allocation.
3567          *
3568          * Here as well we need to wait for the vblank to make sure the freed
3569          * space is not used anymore.
3570          */
3571         for_each_intel_crtc(dev, crtc) {
3572                 if (!crtc->active)
3573                         continue;
3574
3575                 pipe = crtc->pipe;
3576
3577                 if (reallocated[pipe])
3578                         continue;
3579
3580                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3581                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3582                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3583                         intel_wait_for_vblank(dev, pipe);
3584                         reallocated[pipe] = true;
3585                 }
3586         }
3587
3588         /*
3589          * Third pass: flush the pipes that got more space allocated.
3590          *
3591          * We don't need to actively wait for the update here, next vblank
3592          * will just get more DDB space with the correct WM values.
3593          */
3594         for_each_intel_crtc(dev, crtc) {
3595                 if (!crtc->active)
3596                         continue;
3597
3598                 pipe = crtc->pipe;
3599
3600                 /*
3601                  * At this point, only the pipes more space than before are
3602                  * left to re-allocate.
3603                  */
3604                 if (reallocated[pipe])
3605                         continue;
3606
3607                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3608         }
3609 }
3610
3611 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3612                                struct skl_pipe_wm_parameters *params,
3613                                struct intel_wm_config *config,
3614                                struct skl_ddb_allocation *ddb, /* out */
3615                                struct skl_pipe_wm *pipe_wm /* out */)
3616 {
3617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3618
3619         skl_compute_wm_pipe_parameters(crtc, params);
3620         skl_allocate_pipe_ddb(crtc, config, params, ddb);
3621         skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3622
3623         if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3624                 return false;
3625
3626         intel_crtc->wm.skl_active = *pipe_wm;
3627
3628         return true;
3629 }
3630
3631 static void skl_update_other_pipe_wm(struct drm_device *dev,
3632                                      struct drm_crtc *crtc,
3633                                      struct intel_wm_config *config,
3634                                      struct skl_wm_values *r)
3635 {
3636         struct intel_crtc *intel_crtc;
3637         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3638
3639         /*
3640          * If the WM update hasn't changed the allocation for this_crtc (the
3641          * crtc we are currently computing the new WM values for), other
3642          * enabled crtcs will keep the same allocation and we don't need to
3643          * recompute anything for them.
3644          */
3645         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3646                 return;
3647
3648         /*
3649          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3650          * other active pipes need new DDB allocation and WM values.
3651          */
3652         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3653                                 base.head) {
3654                 struct skl_pipe_wm_parameters params = {};
3655                 struct skl_pipe_wm pipe_wm = {};
3656                 bool wm_changed;
3657
3658                 if (this_crtc->pipe == intel_crtc->pipe)
3659                         continue;
3660
3661                 if (!intel_crtc->active)
3662                         continue;
3663
3664                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3665                                                 &params, config,
3666                                                 &r->ddb, &pipe_wm);
3667
3668                 /*
3669                  * If we end up re-computing the other pipe WM values, it's
3670                  * because it was really needed, so we expect the WM values to
3671                  * be different.
3672                  */
3673                 WARN_ON(!wm_changed);
3674
3675                 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3676                 r->dirty[intel_crtc->pipe] = true;
3677         }
3678 }
3679
3680 static void skl_update_wm(struct drm_crtc *crtc)
3681 {
3682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3683         struct drm_device *dev = crtc->dev;
3684         struct drm_i915_private *dev_priv = dev->dev_private;
3685         struct skl_pipe_wm_parameters params = {};
3686         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3687         struct skl_pipe_wm pipe_wm = {};
3688         struct intel_wm_config config = {};
3689
3690         memset(results, 0, sizeof(*results));
3691
3692         skl_compute_wm_global_parameters(dev, &config);
3693
3694         if (!skl_update_pipe_wm(crtc, &params, &config,
3695                                 &results->ddb, &pipe_wm))
3696                 return;
3697
3698         skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3699         results->dirty[intel_crtc->pipe] = true;
3700
3701         skl_update_other_pipe_wm(dev, crtc, &config, results);
3702         skl_write_wm_values(dev_priv, results);
3703         skl_flush_wm_values(dev_priv, results);
3704
3705         /* store the new configuration */
3706         dev_priv->wm.skl_hw = *results;
3707 }
3708
3709 static void
3710 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3711                      uint32_t sprite_width, uint32_t sprite_height,
3712                      int pixel_size, bool enabled, bool scaled)
3713 {
3714         struct intel_plane *intel_plane = to_intel_plane(plane);
3715         struct drm_framebuffer *fb = plane->state->fb;
3716
3717         intel_plane->wm.enabled = enabled;
3718         intel_plane->wm.scaled = scaled;
3719         intel_plane->wm.horiz_pixels = sprite_width;
3720         intel_plane->wm.vert_pixels = sprite_height;
3721         intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3722
3723         /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3724         intel_plane->wm.bytes_per_pixel =
3725                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3726                 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3727         intel_plane->wm.y_bytes_per_pixel =
3728                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3729                 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3730
3731         /*
3732          * Framebuffer can be NULL on plane disable, but it does not
3733          * matter for watermarks if we assume no tiling in that case.
3734          */
3735         if (fb)
3736                 intel_plane->wm.tiling = fb->modifier[0];
3737         intel_plane->wm.rotation = plane->state->rotation;
3738
3739         skl_update_wm(crtc);
3740 }
3741
3742 static void ilk_update_wm(struct drm_crtc *crtc)
3743 {
3744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3745         struct drm_device *dev = crtc->dev;
3746         struct drm_i915_private *dev_priv = dev->dev_private;
3747         struct ilk_wm_maximums max;
3748         struct ilk_pipe_wm_parameters params = {};
3749         struct ilk_wm_values results = {};
3750         enum intel_ddb_partitioning partitioning;
3751         struct intel_pipe_wm pipe_wm = {};
3752         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3753         struct intel_wm_config config = {};
3754
3755         ilk_compute_wm_parameters(crtc, &params);
3756
3757         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3758
3759         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3760                 return;
3761
3762         intel_crtc->wm.active = pipe_wm;
3763
3764         ilk_compute_wm_config(dev, &config);
3765
3766         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3767         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3768
3769         /* 5/6 split only in single pipe config on IVB+ */
3770         if (INTEL_INFO(dev)->gen >= 7 &&
3771             config.num_pipes_active == 1 && config.sprites_enabled) {
3772                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3773                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3774
3775                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3776         } else {
3777                 best_lp_wm = &lp_wm_1_2;
3778         }
3779
3780         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3781                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3782
3783         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3784
3785         ilk_write_wm_values(dev_priv, &results);
3786 }
3787
3788 static void
3789 ilk_update_sprite_wm(struct drm_plane *plane,
3790                      struct drm_crtc *crtc,
3791                      uint32_t sprite_width, uint32_t sprite_height,
3792                      int pixel_size, bool enabled, bool scaled)
3793 {
3794         struct drm_device *dev = plane->dev;
3795         struct intel_plane *intel_plane = to_intel_plane(plane);
3796
3797         intel_plane->wm.enabled = enabled;
3798         intel_plane->wm.scaled = scaled;
3799         intel_plane->wm.horiz_pixels = sprite_width;
3800         intel_plane->wm.vert_pixels = sprite_width;
3801         intel_plane->wm.bytes_per_pixel = pixel_size;
3802
3803         /*
3804          * IVB workaround: must disable low power watermarks for at least
3805          * one frame before enabling scaling.  LP watermarks can be re-enabled
3806          * when scaling is disabled.
3807          *
3808          * WaCxSRDisabledForSpriteScaling:ivb
3809          */
3810         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3811                 intel_wait_for_vblank(dev, intel_plane->pipe);
3812
3813         ilk_update_wm(crtc);
3814 }
3815
3816 static void skl_pipe_wm_active_state(uint32_t val,
3817                                      struct skl_pipe_wm *active,
3818                                      bool is_transwm,
3819                                      bool is_cursor,
3820                                      int i,
3821                                      int level)
3822 {
3823         bool is_enabled = (val & PLANE_WM_EN) != 0;
3824
3825         if (!is_transwm) {
3826                 if (!is_cursor) {
3827                         active->wm[level].plane_en[i] = is_enabled;
3828                         active->wm[level].plane_res_b[i] =
3829                                         val & PLANE_WM_BLOCKS_MASK;
3830                         active->wm[level].plane_res_l[i] =
3831                                         (val >> PLANE_WM_LINES_SHIFT) &
3832                                                 PLANE_WM_LINES_MASK;
3833                 } else {
3834                         active->wm[level].cursor_en = is_enabled;
3835                         active->wm[level].cursor_res_b =
3836                                         val & PLANE_WM_BLOCKS_MASK;
3837                         active->wm[level].cursor_res_l =
3838                                         (val >> PLANE_WM_LINES_SHIFT) &
3839                                                 PLANE_WM_LINES_MASK;
3840                 }
3841         } else {
3842                 if (!is_cursor) {
3843                         active->trans_wm.plane_en[i] = is_enabled;
3844                         active->trans_wm.plane_res_b[i] =
3845                                         val & PLANE_WM_BLOCKS_MASK;
3846                         active->trans_wm.plane_res_l[i] =
3847                                         (val >> PLANE_WM_LINES_SHIFT) &
3848                                                 PLANE_WM_LINES_MASK;
3849                 } else {
3850                         active->trans_wm.cursor_en = is_enabled;
3851                         active->trans_wm.cursor_res_b =
3852                                         val & PLANE_WM_BLOCKS_MASK;
3853                         active->trans_wm.cursor_res_l =
3854                                         (val >> PLANE_WM_LINES_SHIFT) &
3855                                                 PLANE_WM_LINES_MASK;
3856                 }
3857         }
3858 }
3859
3860 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3861 {
3862         struct drm_device *dev = crtc->dev;
3863         struct drm_i915_private *dev_priv = dev->dev_private;
3864         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3866         struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3867         enum pipe pipe = intel_crtc->pipe;
3868         int level, i, max_level;
3869         uint32_t temp;
3870
3871         max_level = ilk_wm_max_level(dev);
3872
3873         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3874
3875         for (level = 0; level <= max_level; level++) {
3876                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3877                         hw->plane[pipe][i][level] =
3878                                         I915_READ(PLANE_WM(pipe, i, level));
3879                 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3880         }
3881
3882         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3883                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3884         hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3885
3886         if (!intel_crtc->active)
3887                 return;
3888
3889         hw->dirty[pipe] = true;
3890
3891         active->linetime = hw->wm_linetime[pipe];
3892
3893         for (level = 0; level <= max_level; level++) {
3894                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3895                         temp = hw->plane[pipe][i][level];
3896                         skl_pipe_wm_active_state(temp, active, false,
3897                                                 false, i, level);
3898                 }
3899                 temp = hw->cursor[pipe][level];
3900                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3901         }
3902
3903         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3904                 temp = hw->plane_trans[pipe][i];
3905                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3906         }
3907
3908         temp = hw->cursor_trans[pipe];
3909         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3910 }
3911
3912 void skl_wm_get_hw_state(struct drm_device *dev)
3913 {
3914         struct drm_i915_private *dev_priv = dev->dev_private;
3915         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3916         struct drm_crtc *crtc;
3917
3918         skl_ddb_get_hw_state(dev_priv, ddb);
3919         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3920                 skl_pipe_wm_get_hw_state(crtc);
3921 }
3922
3923 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3924 {
3925         struct drm_device *dev = crtc->dev;
3926         struct drm_i915_private *dev_priv = dev->dev_private;
3927         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3929         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3930         enum pipe pipe = intel_crtc->pipe;
3931         static const unsigned int wm0_pipe_reg[] = {
3932                 [PIPE_A] = WM0_PIPEA_ILK,
3933                 [PIPE_B] = WM0_PIPEB_ILK,
3934                 [PIPE_C] = WM0_PIPEC_IVB,
3935         };
3936
3937         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3938         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3939                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3940
3941         active->pipe_enabled = intel_crtc->active;
3942
3943         if (active->pipe_enabled) {
3944                 u32 tmp = hw->wm_pipe[pipe];
3945
3946                 /*
3947                  * For active pipes LP0 watermark is marked as
3948                  * enabled, and LP1+ watermaks as disabled since
3949                  * we can't really reverse compute them in case
3950                  * multiple pipes are active.
3951                  */
3952                 active->wm[0].enable = true;
3953                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3954                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3955                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3956                 active->linetime = hw->wm_linetime[pipe];
3957         } else {
3958                 int level, max_level = ilk_wm_max_level(dev);
3959
3960                 /*
3961                  * For inactive pipes, all watermark levels
3962                  * should be marked as enabled but zeroed,
3963                  * which is what we'd compute them to.
3964                  */
3965                 for (level = 0; level <= max_level; level++)
3966                         active->wm[level].enable = true;
3967         }
3968 }
3969
3970 #define _FW_WM(value, plane) \
3971         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3972 #define _FW_WM_VLV(value, plane) \
3973         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3974
3975 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3976                                struct vlv_wm_values *wm)
3977 {
3978         enum pipe pipe;
3979         uint32_t tmp;
3980
3981         for_each_pipe(dev_priv, pipe) {
3982                 tmp = I915_READ(VLV_DDL(pipe));
3983
3984                 wm->ddl[pipe].primary =
3985                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3986                 wm->ddl[pipe].cursor =
3987                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3988                 wm->ddl[pipe].sprite[0] =
3989                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3990                 wm->ddl[pipe].sprite[1] =
3991                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3992         }
3993
3994         tmp = I915_READ(DSPFW1);
3995         wm->sr.plane = _FW_WM(tmp, SR);
3996         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3997         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3998         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3999
4000         tmp = I915_READ(DSPFW2);
4001         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4002         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4003         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4004
4005         tmp = I915_READ(DSPFW3);
4006         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4007
4008         if (IS_CHERRYVIEW(dev_priv)) {
4009                 tmp = I915_READ(DSPFW7_CHV);
4010                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4011                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4012
4013                 tmp = I915_READ(DSPFW8_CHV);
4014                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4015                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4016
4017                 tmp = I915_READ(DSPFW9_CHV);
4018                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4019                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4020
4021                 tmp = I915_READ(DSPHOWM);
4022                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4023                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4024                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4025                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4026                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4027                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4028                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4029                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4030                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4031                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4032         } else {
4033                 tmp = I915_READ(DSPFW7);
4034                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4035                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4036
4037                 tmp = I915_READ(DSPHOWM);
4038                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4039                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4040                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4041                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4042                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4043                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4044                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4045         }
4046 }
4047
4048 #undef _FW_WM
4049 #undef _FW_WM_VLV
4050
4051 void vlv_wm_get_hw_state(struct drm_device *dev)
4052 {
4053         struct drm_i915_private *dev_priv = to_i915(dev);
4054         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4055         struct intel_plane *plane;
4056         enum pipe pipe;
4057         u32 val;
4058
4059         vlv_read_wm_values(dev_priv, wm);
4060
4061         for_each_intel_plane(dev, plane) {
4062                 switch (plane->base.type) {
4063                         int sprite;
4064                 case DRM_PLANE_TYPE_CURSOR:
4065                         plane->wm.fifo_size = 63;
4066                         break;
4067                 case DRM_PLANE_TYPE_PRIMARY:
4068                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4069                         break;
4070                 case DRM_PLANE_TYPE_OVERLAY:
4071                         sprite = plane->plane;
4072                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4073                         break;
4074                 }
4075         }
4076
4077         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4078         wm->level = VLV_WM_LEVEL_PM2;
4079
4080         if (IS_CHERRYVIEW(dev_priv)) {
4081                 mutex_lock(&dev_priv->rps.hw_lock);
4082
4083                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4084                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4085                         wm->level = VLV_WM_LEVEL_PM5;
4086
4087                 /*
4088                  * If DDR DVFS is disabled in the BIOS, Punit
4089                  * will never ack the request. So if that happens
4090                  * assume we don't have to enable/disable DDR DVFS
4091                  * dynamically. To test that just set the REQ_ACK
4092                  * bit to poke the Punit, but don't change the
4093                  * HIGH/LOW bits so that we don't actually change
4094                  * the current state.
4095                  */
4096                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4097                 val |= FORCE_DDR_FREQ_REQ_ACK;
4098                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4099
4100                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4101                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4102                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4103                                       "assuming DDR DVFS is disabled\n");
4104                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4105                 } else {
4106                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4107                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4108                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4109                 }
4110
4111                 mutex_unlock(&dev_priv->rps.hw_lock);
4112         }
4113
4114         for_each_pipe(dev_priv, pipe)
4115                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4116                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4117                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4118
4119         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4120                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4121 }
4122
4123 void ilk_wm_get_hw_state(struct drm_device *dev)
4124 {
4125         struct drm_i915_private *dev_priv = dev->dev_private;
4126         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4127         struct drm_crtc *crtc;
4128
4129         for_each_crtc(dev, crtc)
4130                 ilk_pipe_wm_get_hw_state(crtc);
4131
4132         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4133         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4134         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4135
4136         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4137         if (INTEL_INFO(dev)->gen >= 7) {
4138                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4139                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4140         }
4141
4142         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4143                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4144                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4145         else if (IS_IVYBRIDGE(dev))
4146                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4147                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4148
4149         hw->enable_fbc_wm =
4150                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4151 }
4152
4153 /**
4154  * intel_update_watermarks - update FIFO watermark values based on current modes
4155  *
4156  * Calculate watermark values for the various WM regs based on current mode
4157  * and plane configuration.
4158  *
4159  * There are several cases to deal with here:
4160  *   - normal (i.e. non-self-refresh)
4161  *   - self-refresh (SR) mode
4162  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4163  *   - lines are small relative to FIFO size (buffer can hold more than 2
4164  *     lines), so need to account for TLB latency
4165  *
4166  *   The normal calculation is:
4167  *     watermark = dotclock * bytes per pixel * latency
4168  *   where latency is platform & configuration dependent (we assume pessimal
4169  *   values here).
4170  *
4171  *   The SR calculation is:
4172  *     watermark = (trunc(latency/line time)+1) * surface width *
4173  *       bytes per pixel
4174  *   where
4175  *     line time = htotal / dotclock
4176  *     surface width = hdisplay for normal plane and 64 for cursor
4177  *   and latency is assumed to be high, as above.
4178  *
4179  * The final value programmed to the register should always be rounded up,
4180  * and include an extra 2 entries to account for clock crossings.
4181  *
4182  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4183  * to set the non-SR watermarks to 8.
4184  */
4185 void intel_update_watermarks(struct drm_crtc *crtc)
4186 {
4187         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4188
4189         if (dev_priv->display.update_wm)
4190                 dev_priv->display.update_wm(crtc);
4191 }
4192
4193 void intel_update_sprite_watermarks(struct drm_plane *plane,
4194                                     struct drm_crtc *crtc,
4195                                     uint32_t sprite_width,
4196                                     uint32_t sprite_height,
4197                                     int pixel_size,
4198                                     bool enabled, bool scaled)
4199 {
4200         struct drm_i915_private *dev_priv = plane->dev->dev_private;
4201
4202         if (dev_priv->display.update_sprite_wm)
4203                 dev_priv->display.update_sprite_wm(plane, crtc,
4204                                                    sprite_width, sprite_height,
4205                                                    pixel_size, enabled, scaled);
4206 }
4207
4208 /**
4209  * Lock protecting IPS related data structures
4210  */
4211 DEFINE_SPINLOCK(mchdev_lock);
4212
4213 /* Global for IPS driver to get at the current i915 device. Protected by
4214  * mchdev_lock. */
4215 static struct drm_i915_private *i915_mch_dev;
4216
4217 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4218 {
4219         struct drm_i915_private *dev_priv = dev->dev_private;
4220         u16 rgvswctl;
4221
4222         assert_spin_locked(&mchdev_lock);
4223
4224         rgvswctl = I915_READ16(MEMSWCTL);
4225         if (rgvswctl & MEMCTL_CMD_STS) {
4226                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4227                 return false; /* still busy with another command */
4228         }
4229
4230         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4231                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4232         I915_WRITE16(MEMSWCTL, rgvswctl);
4233         POSTING_READ16(MEMSWCTL);
4234
4235         rgvswctl |= MEMCTL_CMD_STS;
4236         I915_WRITE16(MEMSWCTL, rgvswctl);
4237
4238         return true;
4239 }
4240
4241 static void ironlake_enable_drps(struct drm_device *dev)
4242 {
4243         struct drm_i915_private *dev_priv = dev->dev_private;
4244         u32 rgvmodectl = I915_READ(MEMMODECTL);
4245         u8 fmax, fmin, fstart, vstart;
4246
4247         spin_lock_irq(&mchdev_lock);
4248
4249         /* Enable temp reporting */
4250         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4251         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4252
4253         /* 100ms RC evaluation intervals */
4254         I915_WRITE(RCUPEI, 100000);
4255         I915_WRITE(RCDNEI, 100000);
4256
4257         /* Set max/min thresholds to 90ms and 80ms respectively */
4258         I915_WRITE(RCBMAXAVG, 90000);
4259         I915_WRITE(RCBMINAVG, 80000);
4260
4261         I915_WRITE(MEMIHYST, 1);
4262
4263         /* Set up min, max, and cur for interrupt handling */
4264         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4265         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4266         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4267                 MEMMODE_FSTART_SHIFT;
4268
4269         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4270                 PXVFREQ_PX_SHIFT;
4271
4272         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4273         dev_priv->ips.fstart = fstart;
4274
4275         dev_priv->ips.max_delay = fstart;
4276         dev_priv->ips.min_delay = fmin;
4277         dev_priv->ips.cur_delay = fstart;
4278
4279         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4280                          fmax, fmin, fstart);
4281
4282         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4283
4284         /*
4285          * Interrupts will be enabled in ironlake_irq_postinstall
4286          */
4287
4288         I915_WRITE(VIDSTART, vstart);
4289         POSTING_READ(VIDSTART);
4290
4291         rgvmodectl |= MEMMODE_SWMODE_EN;
4292         I915_WRITE(MEMMODECTL, rgvmodectl);
4293
4294         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4295                 DRM_ERROR("stuck trying to change perf mode\n");
4296         mdelay(1);
4297
4298         ironlake_set_drps(dev, fstart);
4299
4300         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
4301                 I915_READ(0x112e0);
4302         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4303         dev_priv->ips.last_count2 = I915_READ(0x112f4);
4304         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4305
4306         spin_unlock_irq(&mchdev_lock);
4307 }
4308
4309 static void ironlake_disable_drps(struct drm_device *dev)
4310 {
4311         struct drm_i915_private *dev_priv = dev->dev_private;
4312         u16 rgvswctl;
4313
4314         spin_lock_irq(&mchdev_lock);
4315
4316         rgvswctl = I915_READ16(MEMSWCTL);
4317
4318         /* Ack interrupts, disable EFC interrupt */
4319         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4320         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4321         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4322         I915_WRITE(DEIIR, DE_PCU_EVENT);
4323         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4324
4325         /* Go back to the starting frequency */
4326         ironlake_set_drps(dev, dev_priv->ips.fstart);
4327         mdelay(1);
4328         rgvswctl |= MEMCTL_CMD_STS;
4329         I915_WRITE(MEMSWCTL, rgvswctl);
4330         mdelay(1);
4331
4332         spin_unlock_irq(&mchdev_lock);
4333 }
4334
4335 /* There's a funny hw issue where the hw returns all 0 when reading from
4336  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4337  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4338  * all limits and the gpu stuck at whatever frequency it is at atm).
4339  */
4340 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4341 {
4342         u32 limits;
4343
4344         /* Only set the down limit when we've reached the lowest level to avoid
4345          * getting more interrupts, otherwise leave this clear. This prevents a
4346          * race in the hw when coming out of rc6: There's a tiny window where
4347          * the hw runs at the minimal clock before selecting the desired
4348          * frequency, if the down threshold expires in that window we will not
4349          * receive a down interrupt. */
4350         if (IS_GEN9(dev_priv->dev)) {
4351                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4352                 if (val <= dev_priv->rps.min_freq_softlimit)
4353                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4354         } else {
4355                 limits = dev_priv->rps.max_freq_softlimit << 24;
4356                 if (val <= dev_priv->rps.min_freq_softlimit)
4357                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4358         }
4359
4360         return limits;
4361 }
4362
4363 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4364 {
4365         int new_power;
4366         u32 threshold_up = 0, threshold_down = 0; /* in % */
4367         u32 ei_up = 0, ei_down = 0;
4368
4369         new_power = dev_priv->rps.power;
4370         switch (dev_priv->rps.power) {
4371         case LOW_POWER:
4372                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4373                         new_power = BETWEEN;
4374                 break;
4375
4376         case BETWEEN:
4377                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4378                         new_power = LOW_POWER;
4379                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4380                         new_power = HIGH_POWER;
4381                 break;
4382
4383         case HIGH_POWER:
4384                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4385                         new_power = BETWEEN;
4386                 break;
4387         }
4388         /* Max/min bins are special */
4389         if (val <= dev_priv->rps.min_freq_softlimit)
4390                 new_power = LOW_POWER;
4391         if (val >= dev_priv->rps.max_freq_softlimit)
4392                 new_power = HIGH_POWER;
4393         if (new_power == dev_priv->rps.power)
4394                 return;
4395
4396         /* Note the units here are not exactly 1us, but 1280ns. */
4397         switch (new_power) {
4398         case LOW_POWER:
4399                 /* Upclock if more than 95% busy over 16ms */
4400                 ei_up = 16000;
4401                 threshold_up = 95;
4402
4403                 /* Downclock if less than 85% busy over 32ms */
4404                 ei_down = 32000;
4405                 threshold_down = 85;
4406                 break;
4407
4408         case BETWEEN:
4409                 /* Upclock if more than 90% busy over 13ms */
4410                 ei_up = 13000;
4411                 threshold_up = 90;
4412
4413                 /* Downclock if less than 75% busy over 32ms */
4414                 ei_down = 32000;
4415                 threshold_down = 75;
4416                 break;
4417
4418         case HIGH_POWER:
4419                 /* Upclock if more than 85% busy over 10ms */
4420                 ei_up = 10000;
4421                 threshold_up = 85;
4422
4423                 /* Downclock if less than 60% busy over 32ms */
4424                 ei_down = 32000;
4425                 threshold_down = 60;
4426                 break;
4427         }
4428
4429         I915_WRITE(GEN6_RP_UP_EI,
4430                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4431         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4432                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4433
4434         I915_WRITE(GEN6_RP_DOWN_EI,
4435                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4436         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4437                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4438
4439          I915_WRITE(GEN6_RP_CONTROL,
4440                     GEN6_RP_MEDIA_TURBO |
4441                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4442                     GEN6_RP_MEDIA_IS_GFX |
4443                     GEN6_RP_ENABLE |
4444                     GEN6_RP_UP_BUSY_AVG |
4445                     GEN6_RP_DOWN_IDLE_AVG);
4446
4447         dev_priv->rps.power = new_power;
4448         dev_priv->rps.up_threshold = threshold_up;
4449         dev_priv->rps.down_threshold = threshold_down;
4450         dev_priv->rps.last_adj = 0;
4451 }
4452
4453 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4454 {
4455         u32 mask = 0;
4456
4457         if (val > dev_priv->rps.min_freq_softlimit)
4458                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4459         if (val < dev_priv->rps.max_freq_softlimit)
4460                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4461
4462         mask &= dev_priv->pm_rps_events;
4463
4464         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4465 }
4466
4467 /* gen6_set_rps is called to update the frequency request, but should also be
4468  * called when the range (min_delay and max_delay) is modified so that we can
4469  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4470 static void gen6_set_rps(struct drm_device *dev, u8 val)
4471 {
4472         struct drm_i915_private *dev_priv = dev->dev_private;
4473
4474         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4475         WARN_ON(val > dev_priv->rps.max_freq);
4476         WARN_ON(val < dev_priv->rps.min_freq);
4477
4478         /* min/max delay may still have been modified so be sure to
4479          * write the limits value.
4480          */
4481         if (val != dev_priv->rps.cur_freq) {
4482                 gen6_set_rps_thresholds(dev_priv, val);
4483
4484                 if (IS_GEN9(dev))
4485                         I915_WRITE(GEN6_RPNSWREQ,
4486                                    GEN9_FREQUENCY(val));
4487                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4488                         I915_WRITE(GEN6_RPNSWREQ,
4489                                    HSW_FREQUENCY(val));
4490                 else
4491                         I915_WRITE(GEN6_RPNSWREQ,
4492                                    GEN6_FREQUENCY(val) |
4493                                    GEN6_OFFSET(0) |
4494                                    GEN6_AGGRESSIVE_TURBO);
4495         }
4496
4497         /* Make sure we continue to get interrupts
4498          * until we hit the minimum or maximum frequencies.
4499          */
4500         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4501         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4502
4503         POSTING_READ(GEN6_RPNSWREQ);
4504
4505         dev_priv->rps.cur_freq = val;
4506         trace_intel_gpu_freq_change(val * 50);
4507 }
4508
4509 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4510 {
4511         struct drm_i915_private *dev_priv = dev->dev_private;
4512
4513         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4514         WARN_ON(val > dev_priv->rps.max_freq);
4515         WARN_ON(val < dev_priv->rps.min_freq);
4516
4517         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4518                       "Odd GPU freq value\n"))
4519                 val &= ~1;
4520
4521         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4522
4523         if (val != dev_priv->rps.cur_freq) {
4524                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4525                 if (!IS_CHERRYVIEW(dev_priv))
4526                         gen6_set_rps_thresholds(dev_priv, val);
4527         }
4528
4529         dev_priv->rps.cur_freq = val;
4530         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4531 }
4532
4533 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4534  *
4535  * * If Gfx is Idle, then
4536  * 1. Forcewake Media well.
4537  * 2. Request idle freq.
4538  * 3. Release Forcewake of Media well.
4539 */
4540 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4541 {
4542         u32 val = dev_priv->rps.idle_freq;
4543
4544         if (dev_priv->rps.cur_freq <= val)
4545                 return;
4546
4547         /* Wake up the media well, as that takes a lot less
4548          * power than the Render well. */
4549         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4550         valleyview_set_rps(dev_priv->dev, val);
4551         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4552 }
4553
4554 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4555 {
4556         mutex_lock(&dev_priv->rps.hw_lock);
4557         if (dev_priv->rps.enabled) {
4558                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4559                         gen6_rps_reset_ei(dev_priv);
4560                 I915_WRITE(GEN6_PMINTRMSK,
4561                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4562         }
4563         mutex_unlock(&dev_priv->rps.hw_lock);
4564 }
4565
4566 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4567 {
4568         struct drm_device *dev = dev_priv->dev;
4569
4570         mutex_lock(&dev_priv->rps.hw_lock);
4571         if (dev_priv->rps.enabled) {
4572                 if (IS_VALLEYVIEW(dev))
4573                         vlv_set_rps_idle(dev_priv);
4574                 else
4575                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4576                 dev_priv->rps.last_adj = 0;
4577                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4578         }
4579         mutex_unlock(&dev_priv->rps.hw_lock);
4580
4581         spin_lock(&dev_priv->rps.client_lock);
4582         while (!list_empty(&dev_priv->rps.clients))
4583                 list_del_init(dev_priv->rps.clients.next);
4584         spin_unlock(&dev_priv->rps.client_lock);
4585 }
4586
4587 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4588                     struct intel_rps_client *rps,
4589                     unsigned long submitted)
4590 {
4591         /* This is intentionally racy! We peek at the state here, then
4592          * validate inside the RPS worker.
4593          */
4594         if (!(dev_priv->mm.busy &&
4595               dev_priv->rps.enabled &&
4596               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4597                 return;
4598
4599         /* Force a RPS boost (and don't count it against the client) if
4600          * the GPU is severely congested.
4601          */
4602         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4603                 rps = NULL;
4604
4605         spin_lock(&dev_priv->rps.client_lock);
4606         if (rps == NULL || list_empty(&rps->link)) {
4607                 spin_lock_irq(&dev_priv->irq_lock);
4608                 if (dev_priv->rps.interrupts_enabled) {
4609                         dev_priv->rps.client_boost = true;
4610                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4611                 }
4612                 spin_unlock_irq(&dev_priv->irq_lock);
4613
4614                 if (rps != NULL) {
4615                         list_add(&rps->link, &dev_priv->rps.clients);
4616                         rps->boosts++;
4617                 } else
4618                         dev_priv->rps.boosts++;
4619         }
4620         spin_unlock(&dev_priv->rps.client_lock);
4621 }
4622
4623 void intel_set_rps(struct drm_device *dev, u8 val)
4624 {
4625         if (IS_VALLEYVIEW(dev))
4626                 valleyview_set_rps(dev, val);
4627         else
4628                 gen6_set_rps(dev, val);
4629 }
4630
4631 static void gen9_disable_rps(struct drm_device *dev)
4632 {
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634
4635         I915_WRITE(GEN6_RC_CONTROL, 0);
4636         I915_WRITE(GEN9_PG_ENABLE, 0);
4637 }
4638
4639 static void gen6_disable_rps(struct drm_device *dev)
4640 {
4641         struct drm_i915_private *dev_priv = dev->dev_private;
4642
4643         I915_WRITE(GEN6_RC_CONTROL, 0);
4644         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4645 }
4646
4647 static void cherryview_disable_rps(struct drm_device *dev)
4648 {
4649         struct drm_i915_private *dev_priv = dev->dev_private;
4650
4651         I915_WRITE(GEN6_RC_CONTROL, 0);
4652 }
4653
4654 static void valleyview_disable_rps(struct drm_device *dev)
4655 {
4656         struct drm_i915_private *dev_priv = dev->dev_private;
4657
4658         /* we're doing forcewake before Disabling RC6,
4659          * This what the BIOS expects when going into suspend */
4660         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4661
4662         I915_WRITE(GEN6_RC_CONTROL, 0);
4663
4664         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4665 }
4666
4667 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4668 {
4669         if (IS_VALLEYVIEW(dev)) {
4670                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4671                         mode = GEN6_RC_CTL_RC6_ENABLE;
4672                 else
4673                         mode = 0;
4674         }
4675         if (HAS_RC6p(dev))
4676                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4677                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4678                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4679                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4680
4681         else
4682                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4683                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4684 }
4685
4686 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4687 {
4688         /* No RC6 before Ironlake and code is gone for ilk. */
4689         if (INTEL_INFO(dev)->gen < 6)
4690                 return 0;
4691
4692         /* Respect the kernel parameter if it is set */
4693         if (enable_rc6 >= 0) {
4694                 int mask;
4695
4696                 if (HAS_RC6p(dev))
4697                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4698                                INTEL_RC6pp_ENABLE;
4699                 else
4700                         mask = INTEL_RC6_ENABLE;
4701
4702                 if ((enable_rc6 & mask) != enable_rc6)
4703                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4704                                       enable_rc6 & mask, enable_rc6, mask);
4705
4706                 return enable_rc6 & mask;
4707         }
4708
4709         if (IS_IVYBRIDGE(dev))
4710                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4711
4712         return INTEL_RC6_ENABLE;
4713 }
4714
4715 int intel_enable_rc6(const struct drm_device *dev)
4716 {
4717         return i915.enable_rc6;
4718 }
4719
4720 static void gen6_init_rps_frequencies(struct drm_device *dev)
4721 {
4722         struct drm_i915_private *dev_priv = dev->dev_private;
4723         uint32_t rp_state_cap;
4724         u32 ddcc_status = 0;
4725         int ret;
4726
4727         /* All of these values are in units of 50MHz */
4728         dev_priv->rps.cur_freq          = 0;
4729         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4730         if (IS_BROXTON(dev)) {
4731                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4732                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4733                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4734                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4735         } else {
4736                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4737                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4738                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4739                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4740         }
4741
4742         /* hw_max = RP0 until we check for overclocking */
4743         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4744
4745         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4746         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4747                 ret = sandybridge_pcode_read(dev_priv,
4748                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4749                                         &ddcc_status);
4750                 if (0 == ret)
4751                         dev_priv->rps.efficient_freq =
4752                                 clamp_t(u8,
4753                                         ((ddcc_status >> 8) & 0xff),
4754                                         dev_priv->rps.min_freq,
4755                                         dev_priv->rps.max_freq);
4756         }
4757
4758         if (IS_SKYLAKE(dev)) {
4759                 /* Store the frequency values in 16.66 MHZ units, which is
4760                    the natural hardware unit for SKL */
4761                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4762                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4763                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4764                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4765                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4766         }
4767
4768         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4769
4770         /* Preserve min/max settings in case of re-init */
4771         if (dev_priv->rps.max_freq_softlimit == 0)
4772                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4773
4774         if (dev_priv->rps.min_freq_softlimit == 0) {
4775                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4776                         dev_priv->rps.min_freq_softlimit =
4777                                 max_t(int, dev_priv->rps.efficient_freq,
4778                                       intel_freq_opcode(dev_priv, 450));
4779                 else
4780                         dev_priv->rps.min_freq_softlimit =
4781                                 dev_priv->rps.min_freq;
4782         }
4783 }
4784
4785 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4786 static void gen9_enable_rps(struct drm_device *dev)
4787 {
4788         struct drm_i915_private *dev_priv = dev->dev_private;
4789
4790         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4791
4792         gen6_init_rps_frequencies(dev);
4793
4794         /* Program defaults and thresholds for RPS*/
4795         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4796                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4797
4798         /* 1 second timeout*/
4799         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4800                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4801
4802         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4803
4804         /* Leaning on the below call to gen6_set_rps to program/setup the
4805          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4806          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4807         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4808         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4809
4810         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4811 }
4812
4813 static void gen9_enable_rc6(struct drm_device *dev)
4814 {
4815         struct drm_i915_private *dev_priv = dev->dev_private;
4816         struct intel_engine_cs *ring;
4817         uint32_t rc6_mask = 0;
4818         int unused;
4819
4820         /* 1a: Software RC state - RC0 */
4821         I915_WRITE(GEN6_RC_STATE, 0);
4822
4823         /* 1b: Get forcewake during program sequence. Although the driver
4824          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4825         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4826
4827         /* 2a: Disable RC states. */
4828         I915_WRITE(GEN6_RC_CONTROL, 0);
4829
4830         /* 2b: Program RC6 thresholds.*/
4831         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4832         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4833         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4834         for_each_ring(ring, dev_priv, unused)
4835                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4836         I915_WRITE(GEN6_RC_SLEEP, 0);
4837         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4838
4839         /* 2c: Program Coarse Power Gating Policies. */
4840         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4841         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4842
4843         /* 3a: Enable RC6 */
4844         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4845                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4846         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4847                         "on" : "off");
4848         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4849                                    GEN6_RC_CTL_EI_MODE(1) |
4850                                    rc6_mask);
4851
4852         /*
4853          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4854          * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4855          */
4856         I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4857                         GEN9_MEDIA_PG_ENABLE : 0);
4858
4859
4860         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4861
4862 }
4863
4864 static void gen8_enable_rps(struct drm_device *dev)
4865 {
4866         struct drm_i915_private *dev_priv = dev->dev_private;
4867         struct intel_engine_cs *ring;
4868         uint32_t rc6_mask = 0;
4869         int unused;
4870
4871         /* 1a: Software RC state - RC0 */
4872         I915_WRITE(GEN6_RC_STATE, 0);
4873
4874         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4875          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4876         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4877
4878         /* 2a: Disable RC states. */
4879         I915_WRITE(GEN6_RC_CONTROL, 0);
4880
4881         /* Initialize rps frequencies */
4882         gen6_init_rps_frequencies(dev);
4883
4884         /* 2b: Program RC6 thresholds.*/
4885         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4886         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4887         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4888         for_each_ring(ring, dev_priv, unused)
4889                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4890         I915_WRITE(GEN6_RC_SLEEP, 0);
4891         if (IS_BROADWELL(dev))
4892                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4893         else
4894                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4895
4896         /* 3: Enable RC6 */
4897         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4898                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4899         intel_print_rc6_info(dev, rc6_mask);
4900         if (IS_BROADWELL(dev))
4901                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4902                                 GEN7_RC_CTL_TO_MODE |
4903                                 rc6_mask);
4904         else
4905                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4906                                 GEN6_RC_CTL_EI_MODE(1) |
4907                                 rc6_mask);
4908
4909         /* 4 Program defaults and thresholds for RPS*/
4910         I915_WRITE(GEN6_RPNSWREQ,
4911                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4912         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4913                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4914         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4915         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4916
4917         /* Docs recommend 900MHz, and 300 MHz respectively */
4918         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4919                    dev_priv->rps.max_freq_softlimit << 24 |
4920                    dev_priv->rps.min_freq_softlimit << 16);
4921
4922         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4923         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4924         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4925         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4926
4927         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4928
4929         /* 5: Enable RPS */
4930         I915_WRITE(GEN6_RP_CONTROL,
4931                    GEN6_RP_MEDIA_TURBO |
4932                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4933                    GEN6_RP_MEDIA_IS_GFX |
4934                    GEN6_RP_ENABLE |
4935                    GEN6_RP_UP_BUSY_AVG |
4936                    GEN6_RP_DOWN_IDLE_AVG);
4937
4938         /* 6: Ring frequency + overclocking (our driver does this later */
4939
4940         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4941         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4942
4943         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4944 }
4945
4946 static void gen6_enable_rps(struct drm_device *dev)
4947 {
4948         struct drm_i915_private *dev_priv = dev->dev_private;
4949         struct intel_engine_cs *ring;
4950         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4951         u32 gtfifodbg;
4952         int rc6_mode;
4953         int i, ret;
4954
4955         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4956
4957         /* Here begins a magic sequence of register writes to enable
4958          * auto-downclocking.
4959          *
4960          * Perhaps there might be some value in exposing these to
4961          * userspace...
4962          */
4963         I915_WRITE(GEN6_RC_STATE, 0);
4964
4965         /* Clear the DBG now so we don't confuse earlier errors */
4966         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4967                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4968                 I915_WRITE(GTFIFODBG, gtfifodbg);
4969         }
4970
4971         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4972
4973         /* Initialize rps frequencies */
4974         gen6_init_rps_frequencies(dev);
4975
4976         /* disable the counters and set deterministic thresholds */
4977         I915_WRITE(GEN6_RC_CONTROL, 0);
4978
4979         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4980         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4981         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4982         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4983         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4984
4985         for_each_ring(ring, dev_priv, i)
4986                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4987
4988         I915_WRITE(GEN6_RC_SLEEP, 0);
4989         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4990         if (IS_IVYBRIDGE(dev))
4991                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4992         else
4993                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4994         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4995         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4996
4997         /* Check if we are enabling RC6 */
4998         rc6_mode = intel_enable_rc6(dev_priv->dev);
4999         if (rc6_mode & INTEL_RC6_ENABLE)
5000                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5001
5002         /* We don't use those on Haswell */
5003         if (!IS_HASWELL(dev)) {
5004                 if (rc6_mode & INTEL_RC6p_ENABLE)
5005                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5006
5007                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5008                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5009         }
5010
5011         intel_print_rc6_info(dev, rc6_mask);
5012
5013         I915_WRITE(GEN6_RC_CONTROL,
5014                    rc6_mask |
5015                    GEN6_RC_CTL_EI_MODE(1) |
5016                    GEN6_RC_CTL_HW_ENABLE);
5017
5018         /* Power down if completely idle for over 50ms */
5019         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5020         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5021
5022         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5023         if (ret)
5024                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5025
5026         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5027         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5028                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5029                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5030                                  (pcu_mbox & 0xff) * 50);
5031                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5032         }
5033
5034         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5035         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5036
5037         rc6vids = 0;
5038         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5039         if (IS_GEN6(dev) && ret) {
5040                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5041         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5042                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5043                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5044                 rc6vids &= 0xffff00;
5045                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5046                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5047                 if (ret)
5048                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5049         }
5050
5051         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5052 }
5053
5054 static void __gen6_update_ring_freq(struct drm_device *dev)
5055 {
5056         struct drm_i915_private *dev_priv = dev->dev_private;
5057         int min_freq = 15;
5058         unsigned int gpu_freq;
5059         unsigned int max_ia_freq, min_ring_freq;
5060         unsigned int max_gpu_freq, min_gpu_freq;
5061         int scaling_factor = 180;
5062         struct cpufreq_policy *policy;
5063
5064         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5065
5066         policy = cpufreq_cpu_get(0);
5067         if (policy) {
5068                 max_ia_freq = policy->cpuinfo.max_freq;
5069                 cpufreq_cpu_put(policy);
5070         } else {
5071                 /*
5072                  * Default to measured freq if none found, PCU will ensure we
5073                  * don't go over
5074                  */
5075                 max_ia_freq = tsc_khz;
5076         }
5077
5078         /* Convert from kHz to MHz */
5079         max_ia_freq /= 1000;
5080
5081         min_ring_freq = I915_READ(DCLK) & 0xf;
5082         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5083         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5084
5085         if (IS_SKYLAKE(dev)) {
5086                 /* Convert GT frequency to 50 HZ units */
5087                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5088                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5089         } else {
5090                 min_gpu_freq = dev_priv->rps.min_freq;
5091                 max_gpu_freq = dev_priv->rps.max_freq;
5092         }
5093
5094         /*
5095          * For each potential GPU frequency, load a ring frequency we'd like
5096          * to use for memory access.  We do this by specifying the IA frequency
5097          * the PCU should use as a reference to determine the ring frequency.
5098          */
5099         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5100                 int diff = max_gpu_freq - gpu_freq;
5101                 unsigned int ia_freq = 0, ring_freq = 0;
5102
5103                 if (IS_SKYLAKE(dev)) {
5104                         /*
5105                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5106                          * No floor required for ring frequency on SKL.
5107                          */
5108                         ring_freq = gpu_freq;
5109                 } else if (INTEL_INFO(dev)->gen >= 8) {
5110                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5111                         ring_freq = max(min_ring_freq, gpu_freq);
5112                 } else if (IS_HASWELL(dev)) {
5113                         ring_freq = mult_frac(gpu_freq, 5, 4);
5114                         ring_freq = max(min_ring_freq, ring_freq);
5115                         /* leave ia_freq as the default, chosen by cpufreq */
5116                 } else {
5117                         /* On older processors, there is no separate ring
5118                          * clock domain, so in order to boost the bandwidth
5119                          * of the ring, we need to upclock the CPU (ia_freq).
5120                          *
5121                          * For GPU frequencies less than 750MHz,
5122                          * just use the lowest ring freq.
5123                          */
5124                         if (gpu_freq < min_freq)
5125                                 ia_freq = 800;
5126                         else
5127                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5128                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5129                 }
5130
5131                 sandybridge_pcode_write(dev_priv,
5132                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5133                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5134                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5135                                         gpu_freq);
5136         }
5137 }
5138
5139 void gen6_update_ring_freq(struct drm_device *dev)
5140 {
5141         struct drm_i915_private *dev_priv = dev->dev_private;
5142
5143         if (!HAS_CORE_RING_FREQ(dev))
5144                 return;
5145
5146         mutex_lock(&dev_priv->rps.hw_lock);
5147         __gen6_update_ring_freq(dev);
5148         mutex_unlock(&dev_priv->rps.hw_lock);
5149 }
5150
5151 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5152 {
5153         struct drm_device *dev = dev_priv->dev;
5154         u32 val, rp0;
5155
5156         if (dev->pdev->revision >= 0x20) {
5157                 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5158
5159                 switch (INTEL_INFO(dev)->eu_total) {
5160                 case 8:
5161                                 /* (2 * 4) config */
5162                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5163                                 break;
5164                 case 12:
5165                                 /* (2 * 6) config */
5166                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5167                                 break;
5168                 case 16:
5169                                 /* (2 * 8) config */
5170                 default:
5171                                 /* Setting (2 * 8) Min RP0 for any other combination */
5172                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5173                                 break;
5174                 }
5175                 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5176         } else {
5177                 /* For pre-production hardware */
5178                 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5179                 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5180                        PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5181         }
5182         return rp0;
5183 }
5184
5185 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5186 {
5187         u32 val, rpe;
5188
5189         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5190         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5191
5192         return rpe;
5193 }
5194
5195 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5196 {
5197         struct drm_device *dev = dev_priv->dev;
5198         u32 val, rp1;
5199
5200         if (dev->pdev->revision >= 0x20) {
5201                 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5202                 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5203         } else {
5204                 /* For pre-production hardware */
5205                 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5206                 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5207                        PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5208         }
5209         return rp1;
5210 }
5211
5212 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5213 {
5214         u32 val, rp1;
5215
5216         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5217
5218         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5219
5220         return rp1;
5221 }
5222
5223 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5224 {
5225         u32 val, rp0;
5226
5227         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5228
5229         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5230         /* Clamp to max */
5231         rp0 = min_t(u32, rp0, 0xea);
5232
5233         return rp0;
5234 }
5235
5236 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5237 {
5238         u32 val, rpe;
5239
5240         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5241         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5242         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5243         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5244
5245         return rpe;
5246 }
5247
5248 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5249 {
5250         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5251 }
5252
5253 /* Check that the pctx buffer wasn't move under us. */
5254 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5255 {
5256         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5257
5258         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5259                              dev_priv->vlv_pctx->stolen->start);
5260 }
5261
5262
5263 /* Check that the pcbr address is not empty. */
5264 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5265 {
5266         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5267
5268         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5269 }
5270
5271 static void cherryview_setup_pctx(struct drm_device *dev)
5272 {
5273         struct drm_i915_private *dev_priv = dev->dev_private;
5274         unsigned long pctx_paddr, paddr;
5275         struct i915_gtt *gtt = &dev_priv->gtt;
5276         u32 pcbr;
5277         int pctx_size = 32*1024;
5278
5279         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5280
5281         pcbr = I915_READ(VLV_PCBR);
5282         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5283                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5284                 paddr = (dev_priv->mm.stolen_base +
5285                          (gtt->stolen_size - pctx_size));
5286
5287                 pctx_paddr = (paddr & (~4095));
5288                 I915_WRITE(VLV_PCBR, pctx_paddr);
5289         }
5290
5291         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5292 }
5293
5294 static void valleyview_setup_pctx(struct drm_device *dev)
5295 {
5296         struct drm_i915_private *dev_priv = dev->dev_private;
5297         struct drm_i915_gem_object *pctx;
5298         unsigned long pctx_paddr;
5299         u32 pcbr;
5300         int pctx_size = 24*1024;
5301
5302         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5303
5304         pcbr = I915_READ(VLV_PCBR);
5305         if (pcbr) {
5306                 /* BIOS set it up already, grab the pre-alloc'd space */
5307                 int pcbr_offset;
5308
5309                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5310                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5311                                                                       pcbr_offset,
5312                                                                       I915_GTT_OFFSET_NONE,
5313                                                                       pctx_size);
5314                 goto out;
5315         }
5316
5317         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5318
5319         /*
5320          * From the Gunit register HAS:
5321          * The Gfx driver is expected to program this register and ensure
5322          * proper allocation within Gfx stolen memory.  For example, this
5323          * register should be programmed such than the PCBR range does not
5324          * overlap with other ranges, such as the frame buffer, protected
5325          * memory, or any other relevant ranges.
5326          */
5327         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5328         if (!pctx) {
5329                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5330                 return;
5331         }
5332
5333         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5334         I915_WRITE(VLV_PCBR, pctx_paddr);
5335
5336 out:
5337         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5338         dev_priv->vlv_pctx = pctx;
5339 }
5340
5341 static void valleyview_cleanup_pctx(struct drm_device *dev)
5342 {
5343         struct drm_i915_private *dev_priv = dev->dev_private;
5344
5345         if (WARN_ON(!dev_priv->vlv_pctx))
5346                 return;
5347
5348         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5349         dev_priv->vlv_pctx = NULL;
5350 }
5351
5352 static void valleyview_init_gt_powersave(struct drm_device *dev)
5353 {
5354         struct drm_i915_private *dev_priv = dev->dev_private;
5355         u32 val;
5356
5357         valleyview_setup_pctx(dev);
5358
5359         mutex_lock(&dev_priv->rps.hw_lock);
5360
5361         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5362         switch ((val >> 6) & 3) {
5363         case 0:
5364         case 1:
5365                 dev_priv->mem_freq = 800;
5366                 break;
5367         case 2:
5368                 dev_priv->mem_freq = 1066;
5369                 break;
5370         case 3:
5371                 dev_priv->mem_freq = 1333;
5372                 break;
5373         }
5374         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5375
5376         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5377         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5378         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5379                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5380                          dev_priv->rps.max_freq);
5381
5382         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5383         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5384                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5385                          dev_priv->rps.efficient_freq);
5386
5387         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5388         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5389                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5390                          dev_priv->rps.rp1_freq);
5391
5392         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5393         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5394                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5395                          dev_priv->rps.min_freq);
5396
5397         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5398
5399         /* Preserve min/max settings in case of re-init */
5400         if (dev_priv->rps.max_freq_softlimit == 0)
5401                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5402
5403         if (dev_priv->rps.min_freq_softlimit == 0)
5404                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5405
5406         mutex_unlock(&dev_priv->rps.hw_lock);
5407 }
5408
5409 static void cherryview_init_gt_powersave(struct drm_device *dev)
5410 {
5411         struct drm_i915_private *dev_priv = dev->dev_private;
5412         u32 val;
5413
5414         cherryview_setup_pctx(dev);
5415
5416         mutex_lock(&dev_priv->rps.hw_lock);
5417
5418         mutex_lock(&dev_priv->sb_lock);
5419         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5420         mutex_unlock(&dev_priv->sb_lock);
5421
5422         switch ((val >> 2) & 0x7) {
5423         case 0:
5424         case 1:
5425                 dev_priv->rps.cz_freq = 200;
5426                 dev_priv->mem_freq = 1600;
5427                 break;
5428         case 2:
5429                 dev_priv->rps.cz_freq = 267;
5430                 dev_priv->mem_freq = 1600;
5431                 break;
5432         case 3:
5433                 dev_priv->rps.cz_freq = 333;
5434                 dev_priv->mem_freq = 2000;
5435                 break;
5436         case 4:
5437                 dev_priv->rps.cz_freq = 320;
5438                 dev_priv->mem_freq = 1600;
5439                 break;
5440         case 5:
5441                 dev_priv->rps.cz_freq = 400;
5442                 dev_priv->mem_freq = 1600;
5443                 break;
5444         }
5445         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5446
5447         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5448         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5449         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5450                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5451                          dev_priv->rps.max_freq);
5452
5453         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5454         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5455                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5456                          dev_priv->rps.efficient_freq);
5457
5458         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5459         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5460                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5461                          dev_priv->rps.rp1_freq);
5462
5463         /* PUnit validated range is only [RPe, RP0] */
5464         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5465         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5466                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5467                          dev_priv->rps.min_freq);
5468
5469         WARN_ONCE((dev_priv->rps.max_freq |
5470                    dev_priv->rps.efficient_freq |
5471                    dev_priv->rps.rp1_freq |
5472                    dev_priv->rps.min_freq) & 1,
5473                   "Odd GPU freq values\n");
5474
5475         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5476
5477         /* Preserve min/max settings in case of re-init */
5478         if (dev_priv->rps.max_freq_softlimit == 0)
5479                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5480
5481         if (dev_priv->rps.min_freq_softlimit == 0)
5482                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5483
5484         mutex_unlock(&dev_priv->rps.hw_lock);
5485 }
5486
5487 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5488 {
5489         valleyview_cleanup_pctx(dev);
5490 }
5491
5492 static void cherryview_enable_rps(struct drm_device *dev)
5493 {
5494         struct drm_i915_private *dev_priv = dev->dev_private;
5495         struct intel_engine_cs *ring;
5496         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5497         int i;
5498
5499         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5500
5501         gtfifodbg = I915_READ(GTFIFODBG);
5502         if (gtfifodbg) {
5503                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5504                                  gtfifodbg);
5505                 I915_WRITE(GTFIFODBG, gtfifodbg);
5506         }
5507
5508         cherryview_check_pctx(dev_priv);
5509
5510         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5511          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5512         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5513
5514         /*  Disable RC states. */
5515         I915_WRITE(GEN6_RC_CONTROL, 0);
5516
5517         /* 2a: Program RC6 thresholds.*/
5518         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5519         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5520         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5521
5522         for_each_ring(ring, dev_priv, i)
5523                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5524         I915_WRITE(GEN6_RC_SLEEP, 0);
5525
5526         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5527         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5528
5529         /* allows RC6 residency counter to work */
5530         I915_WRITE(VLV_COUNTER_CONTROL,
5531                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5532                                       VLV_MEDIA_RC6_COUNT_EN |
5533                                       VLV_RENDER_RC6_COUNT_EN));
5534
5535         /* For now we assume BIOS is allocating and populating the PCBR  */
5536         pcbr = I915_READ(VLV_PCBR);
5537
5538         /* 3: Enable RC6 */
5539         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5540                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5541                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5542
5543         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5544
5545         /* 4 Program defaults and thresholds for RPS*/
5546         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5547         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5548         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5549         I915_WRITE(GEN6_RP_UP_EI, 66000);
5550         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5551
5552         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5553
5554         /* 5: Enable RPS */
5555         I915_WRITE(GEN6_RP_CONTROL,
5556                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5557                    GEN6_RP_MEDIA_IS_GFX |
5558                    GEN6_RP_ENABLE |
5559                    GEN6_RP_UP_BUSY_AVG |
5560                    GEN6_RP_DOWN_IDLE_AVG);
5561
5562         /* Setting Fixed Bias */
5563         val = VLV_OVERRIDE_EN |
5564                   VLV_SOC_TDP_EN |
5565                   CHV_BIAS_CPU_50_SOC_50;
5566         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5567
5568         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5569
5570         /* RPS code assumes GPLL is used */
5571         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5572
5573         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
5574         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5575
5576         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5577         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5578                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5579                          dev_priv->rps.cur_freq);
5580
5581         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5582                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5583                          dev_priv->rps.efficient_freq);
5584
5585         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5586
5587         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5588 }
5589
5590 static void valleyview_enable_rps(struct drm_device *dev)
5591 {
5592         struct drm_i915_private *dev_priv = dev->dev_private;
5593         struct intel_engine_cs *ring;
5594         u32 gtfifodbg, val, rc6_mode = 0;
5595         int i;
5596
5597         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5598
5599         valleyview_check_pctx(dev_priv);
5600
5601         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5602                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5603                                  gtfifodbg);
5604                 I915_WRITE(GTFIFODBG, gtfifodbg);
5605         }
5606
5607         /* If VLV, Forcewake all wells, else re-direct to regular path */
5608         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5609
5610         /*  Disable RC states. */
5611         I915_WRITE(GEN6_RC_CONTROL, 0);
5612
5613         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5614         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5615         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5616         I915_WRITE(GEN6_RP_UP_EI, 66000);
5617         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5618
5619         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5620
5621         I915_WRITE(GEN6_RP_CONTROL,
5622                    GEN6_RP_MEDIA_TURBO |
5623                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5624                    GEN6_RP_MEDIA_IS_GFX |
5625                    GEN6_RP_ENABLE |
5626                    GEN6_RP_UP_BUSY_AVG |
5627                    GEN6_RP_DOWN_IDLE_CONT);
5628
5629         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5630         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5631         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5632
5633         for_each_ring(ring, dev_priv, i)
5634                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5635
5636         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5637
5638         /* allows RC6 residency counter to work */
5639         I915_WRITE(VLV_COUNTER_CONTROL,
5640                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5641                                       VLV_RENDER_RC0_COUNT_EN |
5642                                       VLV_MEDIA_RC6_COUNT_EN |
5643                                       VLV_RENDER_RC6_COUNT_EN));
5644
5645         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5646                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5647
5648         intel_print_rc6_info(dev, rc6_mode);
5649
5650         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5651
5652         /* Setting Fixed Bias */
5653         val = VLV_OVERRIDE_EN |
5654                   VLV_SOC_TDP_EN |
5655                   VLV_BIAS_CPU_125_SOC_875;
5656         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5657
5658         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5659
5660         /* RPS code assumes GPLL is used */
5661         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5662
5663         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
5664         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5665
5666         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5667         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5668                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5669                          dev_priv->rps.cur_freq);
5670
5671         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5672                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5673                          dev_priv->rps.efficient_freq);
5674
5675         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5676
5677         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5678 }
5679
5680 static unsigned long intel_pxfreq(u32 vidfreq)
5681 {
5682         unsigned long freq;
5683         int div = (vidfreq & 0x3f0000) >> 16;
5684         int post = (vidfreq & 0x3000) >> 12;
5685         int pre = (vidfreq & 0x7);
5686
5687         if (!pre)
5688                 return 0;
5689
5690         freq = ((div * 133333) / ((1<<post) * pre));
5691
5692         return freq;
5693 }
5694
5695 static const struct cparams {
5696         u16 i;
5697         u16 t;
5698         u16 m;
5699         u16 c;
5700 } cparams[] = {
5701         { 1, 1333, 301, 28664 },
5702         { 1, 1066, 294, 24460 },
5703         { 1, 800, 294, 25192 },
5704         { 0, 1333, 276, 27605 },
5705         { 0, 1066, 276, 27605 },
5706         { 0, 800, 231, 23784 },
5707 };
5708
5709 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5710 {
5711         u64 total_count, diff, ret;
5712         u32 count1, count2, count3, m = 0, c = 0;
5713         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5714         int i;
5715
5716         assert_spin_locked(&mchdev_lock);
5717
5718         diff1 = now - dev_priv->ips.last_time1;
5719
5720         /* Prevent division-by-zero if we are asking too fast.
5721          * Also, we don't get interesting results if we are polling
5722          * faster than once in 10ms, so just return the saved value
5723          * in such cases.
5724          */
5725         if (diff1 <= 10)
5726                 return dev_priv->ips.chipset_power;
5727
5728         count1 = I915_READ(DMIEC);
5729         count2 = I915_READ(DDREC);
5730         count3 = I915_READ(CSIEC);
5731
5732         total_count = count1 + count2 + count3;
5733
5734         /* FIXME: handle per-counter overflow */
5735         if (total_count < dev_priv->ips.last_count1) {
5736                 diff = ~0UL - dev_priv->ips.last_count1;
5737                 diff += total_count;
5738         } else {
5739                 diff = total_count - dev_priv->ips.last_count1;
5740         }
5741
5742         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5743                 if (cparams[i].i == dev_priv->ips.c_m &&
5744                     cparams[i].t == dev_priv->ips.r_t) {
5745                         m = cparams[i].m;
5746                         c = cparams[i].c;
5747                         break;
5748                 }
5749         }
5750
5751         diff = div_u64(diff, diff1);
5752         ret = ((m * diff) + c);
5753         ret = div_u64(ret, 10);
5754
5755         dev_priv->ips.last_count1 = total_count;
5756         dev_priv->ips.last_time1 = now;
5757
5758         dev_priv->ips.chipset_power = ret;
5759
5760         return ret;
5761 }
5762
5763 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5764 {
5765         struct drm_device *dev = dev_priv->dev;
5766         unsigned long val;
5767
5768         if (INTEL_INFO(dev)->gen != 5)
5769                 return 0;
5770
5771         spin_lock_irq(&mchdev_lock);
5772
5773         val = __i915_chipset_val(dev_priv);
5774
5775         spin_unlock_irq(&mchdev_lock);
5776
5777         return val;
5778 }
5779
5780 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5781 {
5782         unsigned long m, x, b;
5783         u32 tsfs;
5784
5785         tsfs = I915_READ(TSFS);
5786
5787         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5788         x = I915_READ8(TR1);
5789
5790         b = tsfs & TSFS_INTR_MASK;
5791
5792         return ((m * x) / 127) - b;
5793 }
5794
5795 static int _pxvid_to_vd(u8 pxvid)
5796 {
5797         if (pxvid == 0)
5798                 return 0;
5799
5800         if (pxvid >= 8 && pxvid < 31)
5801                 pxvid = 31;
5802
5803         return (pxvid + 2) * 125;
5804 }
5805
5806 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5807 {
5808         struct drm_device *dev = dev_priv->dev;
5809         const int vd = _pxvid_to_vd(pxvid);
5810         const int vm = vd - 1125;
5811
5812         if (INTEL_INFO(dev)->is_mobile)
5813                 return vm > 0 ? vm : 0;
5814
5815         return vd;
5816 }
5817
5818 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5819 {
5820         u64 now, diff, diffms;
5821         u32 count;
5822
5823         assert_spin_locked(&mchdev_lock);
5824
5825         now = ktime_get_raw_ns();
5826         diffms = now - dev_priv->ips.last_time2;
5827         do_div(diffms, NSEC_PER_MSEC);
5828
5829         /* Don't divide by 0 */
5830         if (!diffms)
5831                 return;
5832
5833         count = I915_READ(GFXEC);
5834
5835         if (count < dev_priv->ips.last_count2) {
5836                 diff = ~0UL - dev_priv->ips.last_count2;
5837                 diff += count;
5838         } else {
5839                 diff = count - dev_priv->ips.last_count2;
5840         }
5841
5842         dev_priv->ips.last_count2 = count;
5843         dev_priv->ips.last_time2 = now;
5844
5845         /* More magic constants... */
5846         diff = diff * 1181;
5847         diff = div_u64(diff, diffms * 10);
5848         dev_priv->ips.gfx_power = diff;
5849 }
5850
5851 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5852 {
5853         struct drm_device *dev = dev_priv->dev;
5854
5855         if (INTEL_INFO(dev)->gen != 5)
5856                 return;
5857
5858         spin_lock_irq(&mchdev_lock);
5859
5860         __i915_update_gfx_val(dev_priv);
5861
5862         spin_unlock_irq(&mchdev_lock);
5863 }
5864
5865 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5866 {
5867         unsigned long t, corr, state1, corr2, state2;
5868         u32 pxvid, ext_v;
5869
5870         assert_spin_locked(&mchdev_lock);
5871
5872         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5873         pxvid = (pxvid >> 24) & 0x7f;
5874         ext_v = pvid_to_extvid(dev_priv, pxvid);
5875
5876         state1 = ext_v;
5877
5878         t = i915_mch_val(dev_priv);
5879
5880         /* Revel in the empirically derived constants */
5881
5882         /* Correction factor in 1/100000 units */
5883         if (t > 80)
5884                 corr = ((t * 2349) + 135940);
5885         else if (t >= 50)
5886                 corr = ((t * 964) + 29317);
5887         else /* < 50 */
5888                 corr = ((t * 301) + 1004);
5889
5890         corr = corr * ((150142 * state1) / 10000 - 78642);
5891         corr /= 100000;
5892         corr2 = (corr * dev_priv->ips.corr);
5893
5894         state2 = (corr2 * state1) / 10000;
5895         state2 /= 100; /* convert to mW */
5896
5897         __i915_update_gfx_val(dev_priv);
5898
5899         return dev_priv->ips.gfx_power + state2;
5900 }
5901
5902 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5903 {
5904         struct drm_device *dev = dev_priv->dev;
5905         unsigned long val;
5906
5907         if (INTEL_INFO(dev)->gen != 5)
5908                 return 0;
5909
5910         spin_lock_irq(&mchdev_lock);
5911
5912         val = __i915_gfx_val(dev_priv);
5913
5914         spin_unlock_irq(&mchdev_lock);
5915
5916         return val;
5917 }
5918
5919 /**
5920  * i915_read_mch_val - return value for IPS use
5921  *
5922  * Calculate and return a value for the IPS driver to use when deciding whether
5923  * we have thermal and power headroom to increase CPU or GPU power budget.
5924  */
5925 unsigned long i915_read_mch_val(void)
5926 {
5927         struct drm_i915_private *dev_priv;
5928         unsigned long chipset_val, graphics_val, ret = 0;
5929
5930         spin_lock_irq(&mchdev_lock);
5931         if (!i915_mch_dev)
5932                 goto out_unlock;
5933         dev_priv = i915_mch_dev;
5934
5935         chipset_val = __i915_chipset_val(dev_priv);
5936         graphics_val = __i915_gfx_val(dev_priv);
5937
5938         ret = chipset_val + graphics_val;
5939
5940 out_unlock:
5941         spin_unlock_irq(&mchdev_lock);
5942
5943         return ret;
5944 }
5945 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5946
5947 /**
5948  * i915_gpu_raise - raise GPU frequency limit
5949  *
5950  * Raise the limit; IPS indicates we have thermal headroom.
5951  */
5952 bool i915_gpu_raise(void)
5953 {
5954         struct drm_i915_private *dev_priv;
5955         bool ret = true;
5956
5957         spin_lock_irq(&mchdev_lock);
5958         if (!i915_mch_dev) {
5959                 ret = false;
5960                 goto out_unlock;
5961         }
5962         dev_priv = i915_mch_dev;
5963
5964         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5965                 dev_priv->ips.max_delay--;
5966
5967 out_unlock:
5968         spin_unlock_irq(&mchdev_lock);
5969
5970         return ret;
5971 }
5972 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5973
5974 /**
5975  * i915_gpu_lower - lower GPU frequency limit
5976  *
5977  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5978  * frequency maximum.
5979  */
5980 bool i915_gpu_lower(void)
5981 {
5982         struct drm_i915_private *dev_priv;
5983         bool ret = true;
5984
5985         spin_lock_irq(&mchdev_lock);
5986         if (!i915_mch_dev) {
5987                 ret = false;
5988                 goto out_unlock;
5989         }
5990         dev_priv = i915_mch_dev;
5991
5992         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5993                 dev_priv->ips.max_delay++;
5994
5995 out_unlock:
5996         spin_unlock_irq(&mchdev_lock);
5997
5998         return ret;
5999 }
6000 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6001
6002 /**
6003  * i915_gpu_busy - indicate GPU business to IPS
6004  *
6005  * Tell the IPS driver whether or not the GPU is busy.
6006  */
6007 bool i915_gpu_busy(void)
6008 {
6009         struct drm_i915_private *dev_priv;
6010         struct intel_engine_cs *ring;
6011         bool ret = false;
6012         int i;
6013
6014         spin_lock_irq(&mchdev_lock);
6015         if (!i915_mch_dev)
6016                 goto out_unlock;
6017         dev_priv = i915_mch_dev;
6018
6019         for_each_ring(ring, dev_priv, i)
6020                 ret |= !list_empty(&ring->request_list);
6021
6022 out_unlock:
6023         spin_unlock_irq(&mchdev_lock);
6024
6025         return ret;
6026 }
6027 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6028
6029 /**
6030  * i915_gpu_turbo_disable - disable graphics turbo
6031  *
6032  * Disable graphics turbo by resetting the max frequency and setting the
6033  * current frequency to the default.
6034  */
6035 bool i915_gpu_turbo_disable(void)
6036 {
6037         struct drm_i915_private *dev_priv;
6038         bool ret = true;
6039
6040         spin_lock_irq(&mchdev_lock);
6041         if (!i915_mch_dev) {
6042                 ret = false;
6043                 goto out_unlock;
6044         }
6045         dev_priv = i915_mch_dev;
6046
6047         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6048
6049         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6050                 ret = false;
6051
6052 out_unlock:
6053         spin_unlock_irq(&mchdev_lock);
6054
6055         return ret;
6056 }
6057 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6058
6059 /**
6060  * Tells the intel_ips driver that the i915 driver is now loaded, if
6061  * IPS got loaded first.
6062  *
6063  * This awkward dance is so that neither module has to depend on the
6064  * other in order for IPS to do the appropriate communication of
6065  * GPU turbo limits to i915.
6066  */
6067 static void
6068 ips_ping_for_i915_load(void)
6069 {
6070         void (*link)(void);
6071
6072         link = symbol_get(ips_link_to_i915_driver);
6073         if (link) {
6074                 link();
6075                 symbol_put(ips_link_to_i915_driver);
6076         }
6077 }
6078
6079 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6080 {
6081         /* We only register the i915 ips part with intel-ips once everything is
6082          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6083         spin_lock_irq(&mchdev_lock);
6084         i915_mch_dev = dev_priv;
6085         spin_unlock_irq(&mchdev_lock);
6086
6087         ips_ping_for_i915_load();
6088 }
6089
6090 void intel_gpu_ips_teardown(void)
6091 {
6092         spin_lock_irq(&mchdev_lock);
6093         i915_mch_dev = NULL;
6094         spin_unlock_irq(&mchdev_lock);
6095 }
6096
6097 static void intel_init_emon(struct drm_device *dev)
6098 {
6099         struct drm_i915_private *dev_priv = dev->dev_private;
6100         u32 lcfuse;
6101         u8 pxw[16];
6102         int i;
6103
6104         /* Disable to program */
6105         I915_WRITE(ECR, 0);
6106         POSTING_READ(ECR);
6107
6108         /* Program energy weights for various events */
6109         I915_WRITE(SDEW, 0x15040d00);
6110         I915_WRITE(CSIEW0, 0x007f0000);
6111         I915_WRITE(CSIEW1, 0x1e220004);
6112         I915_WRITE(CSIEW2, 0x04000004);
6113
6114         for (i = 0; i < 5; i++)
6115                 I915_WRITE(PEW + (i * 4), 0);
6116         for (i = 0; i < 3; i++)
6117                 I915_WRITE(DEW + (i * 4), 0);
6118
6119         /* Program P-state weights to account for frequency power adjustment */
6120         for (i = 0; i < 16; i++) {
6121                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6122                 unsigned long freq = intel_pxfreq(pxvidfreq);
6123                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6124                         PXVFREQ_PX_SHIFT;
6125                 unsigned long val;
6126
6127                 val = vid * vid;
6128                 val *= (freq / 1000);
6129                 val *= 255;
6130                 val /= (127*127*900);
6131                 if (val > 0xff)
6132                         DRM_ERROR("bad pxval: %ld\n", val);
6133                 pxw[i] = val;
6134         }
6135         /* Render standby states get 0 weight */
6136         pxw[14] = 0;
6137         pxw[15] = 0;
6138
6139         for (i = 0; i < 4; i++) {
6140                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6141                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6142                 I915_WRITE(PXW + (i * 4), val);
6143         }
6144
6145         /* Adjust magic regs to magic values (more experimental results) */
6146         I915_WRITE(OGW0, 0);
6147         I915_WRITE(OGW1, 0);
6148         I915_WRITE(EG0, 0x00007f00);
6149         I915_WRITE(EG1, 0x0000000e);
6150         I915_WRITE(EG2, 0x000e0000);
6151         I915_WRITE(EG3, 0x68000300);
6152         I915_WRITE(EG4, 0x42000000);
6153         I915_WRITE(EG5, 0x00140031);
6154         I915_WRITE(EG6, 0);
6155         I915_WRITE(EG7, 0);
6156
6157         for (i = 0; i < 8; i++)
6158                 I915_WRITE(PXWL + (i * 4), 0);
6159
6160         /* Enable PMON + select events */
6161         I915_WRITE(ECR, 0x80000019);
6162
6163         lcfuse = I915_READ(LCFUSE02);
6164
6165         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6166 }
6167
6168 void intel_init_gt_powersave(struct drm_device *dev)
6169 {
6170         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6171
6172         if (IS_CHERRYVIEW(dev))
6173                 cherryview_init_gt_powersave(dev);
6174         else if (IS_VALLEYVIEW(dev))
6175                 valleyview_init_gt_powersave(dev);
6176 }
6177
6178 void intel_cleanup_gt_powersave(struct drm_device *dev)
6179 {
6180         if (IS_CHERRYVIEW(dev))
6181                 return;
6182         else if (IS_VALLEYVIEW(dev))
6183                 valleyview_cleanup_gt_powersave(dev);
6184 }
6185
6186 static void gen6_suspend_rps(struct drm_device *dev)
6187 {
6188         struct drm_i915_private *dev_priv = dev->dev_private;
6189
6190         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6191
6192         gen6_disable_rps_interrupts(dev);
6193 }
6194
6195 /**
6196  * intel_suspend_gt_powersave - suspend PM work and helper threads
6197  * @dev: drm device
6198  *
6199  * We don't want to disable RC6 or other features here, we just want
6200  * to make sure any work we've queued has finished and won't bother
6201  * us while we're suspended.
6202  */
6203 void intel_suspend_gt_powersave(struct drm_device *dev)
6204 {
6205         struct drm_i915_private *dev_priv = dev->dev_private;
6206
6207         if (INTEL_INFO(dev)->gen < 6)
6208                 return;
6209
6210         gen6_suspend_rps(dev);
6211
6212         /* Force GPU to min freq during suspend */
6213         gen6_rps_idle(dev_priv);
6214 }
6215
6216 void intel_disable_gt_powersave(struct drm_device *dev)
6217 {
6218         struct drm_i915_private *dev_priv = dev->dev_private;
6219
6220         if (IS_IRONLAKE_M(dev)) {
6221                 ironlake_disable_drps(dev);
6222         } else if (INTEL_INFO(dev)->gen >= 6) {
6223                 intel_suspend_gt_powersave(dev);
6224
6225                 mutex_lock(&dev_priv->rps.hw_lock);
6226                 if (INTEL_INFO(dev)->gen >= 9)
6227                         gen9_disable_rps(dev);
6228                 else if (IS_CHERRYVIEW(dev))
6229                         cherryview_disable_rps(dev);
6230                 else if (IS_VALLEYVIEW(dev))
6231                         valleyview_disable_rps(dev);
6232                 else
6233                         gen6_disable_rps(dev);
6234
6235                 dev_priv->rps.enabled = false;
6236                 mutex_unlock(&dev_priv->rps.hw_lock);
6237         }
6238 }
6239
6240 static void intel_gen6_powersave_work(struct work_struct *work)
6241 {
6242         struct drm_i915_private *dev_priv =
6243                 container_of(work, struct drm_i915_private,
6244                              rps.delayed_resume_work.work);
6245         struct drm_device *dev = dev_priv->dev;
6246
6247         mutex_lock(&dev_priv->rps.hw_lock);
6248
6249         gen6_reset_rps_interrupts(dev);
6250
6251         if (IS_CHERRYVIEW(dev)) {
6252                 cherryview_enable_rps(dev);
6253         } else if (IS_VALLEYVIEW(dev)) {
6254                 valleyview_enable_rps(dev);
6255         } else if (INTEL_INFO(dev)->gen >= 9) {
6256                 gen9_enable_rc6(dev);
6257                 gen9_enable_rps(dev);
6258                 if (IS_SKYLAKE(dev))
6259                         __gen6_update_ring_freq(dev);
6260         } else if (IS_BROADWELL(dev)) {
6261                 gen8_enable_rps(dev);
6262                 __gen6_update_ring_freq(dev);
6263         } else {
6264                 gen6_enable_rps(dev);
6265                 __gen6_update_ring_freq(dev);
6266         }
6267
6268         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6269         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6270
6271         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6272         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6273
6274         dev_priv->rps.enabled = true;
6275
6276         gen6_enable_rps_interrupts(dev);
6277
6278         mutex_unlock(&dev_priv->rps.hw_lock);
6279
6280         intel_runtime_pm_put(dev_priv);
6281 }
6282
6283 void intel_enable_gt_powersave(struct drm_device *dev)
6284 {
6285         struct drm_i915_private *dev_priv = dev->dev_private;
6286
6287         /* Powersaving is controlled by the host when inside a VM */
6288         if (intel_vgpu_active(dev))
6289                 return;
6290
6291         if (IS_IRONLAKE_M(dev)) {
6292                 mutex_lock(&dev->struct_mutex);
6293                 ironlake_enable_drps(dev);
6294                 intel_init_emon(dev);
6295                 mutex_unlock(&dev->struct_mutex);
6296         } else if (INTEL_INFO(dev)->gen >= 6) {
6297                 /*
6298                  * PCU communication is slow and this doesn't need to be
6299                  * done at any specific time, so do this out of our fast path
6300                  * to make resume and init faster.
6301                  *
6302                  * We depend on the HW RC6 power context save/restore
6303                  * mechanism when entering D3 through runtime PM suspend. So
6304                  * disable RPM until RPS/RC6 is properly setup. We can only
6305                  * get here via the driver load/system resume/runtime resume
6306                  * paths, so the _noresume version is enough (and in case of
6307                  * runtime resume it's necessary).
6308                  */
6309                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6310                                            round_jiffies_up_relative(HZ)))
6311                         intel_runtime_pm_get_noresume(dev_priv);
6312         }
6313 }
6314
6315 void intel_reset_gt_powersave(struct drm_device *dev)
6316 {
6317         struct drm_i915_private *dev_priv = dev->dev_private;
6318
6319         if (INTEL_INFO(dev)->gen < 6)
6320                 return;
6321
6322         gen6_suspend_rps(dev);
6323         dev_priv->rps.enabled = false;
6324 }
6325
6326 static void ibx_init_clock_gating(struct drm_device *dev)
6327 {
6328         struct drm_i915_private *dev_priv = dev->dev_private;
6329
6330         /*
6331          * On Ibex Peak and Cougar Point, we need to disable clock
6332          * gating for the panel power sequencer or it will fail to
6333          * start up when no ports are active.
6334          */
6335         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6336 }
6337
6338 static void g4x_disable_trickle_feed(struct drm_device *dev)
6339 {
6340         struct drm_i915_private *dev_priv = dev->dev_private;
6341         enum pipe pipe;
6342
6343         for_each_pipe(dev_priv, pipe) {
6344                 I915_WRITE(DSPCNTR(pipe),
6345                            I915_READ(DSPCNTR(pipe)) |
6346                            DISPPLANE_TRICKLE_FEED_DISABLE);
6347
6348                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6349                 POSTING_READ(DSPSURF(pipe));
6350         }
6351 }
6352
6353 static void ilk_init_lp_watermarks(struct drm_device *dev)
6354 {
6355         struct drm_i915_private *dev_priv = dev->dev_private;
6356
6357         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6358         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6359         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6360
6361         /*
6362          * Don't touch WM1S_LP_EN here.
6363          * Doing so could cause underruns.
6364          */
6365 }
6366
6367 static void ironlake_init_clock_gating(struct drm_device *dev)
6368 {
6369         struct drm_i915_private *dev_priv = dev->dev_private;
6370         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6371
6372         /*
6373          * Required for FBC
6374          * WaFbcDisableDpfcClockGating:ilk
6375          */
6376         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6377                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6378                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6379
6380         I915_WRITE(PCH_3DCGDIS0,
6381                    MARIUNIT_CLOCK_GATE_DISABLE |
6382                    SVSMUNIT_CLOCK_GATE_DISABLE);
6383         I915_WRITE(PCH_3DCGDIS1,
6384                    VFMUNIT_CLOCK_GATE_DISABLE);
6385
6386         /*
6387          * According to the spec the following bits should be set in
6388          * order to enable memory self-refresh
6389          * The bit 22/21 of 0x42004
6390          * The bit 5 of 0x42020
6391          * The bit 15 of 0x45000
6392          */
6393         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6394                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6395                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6396         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6397         I915_WRITE(DISP_ARB_CTL,
6398                    (I915_READ(DISP_ARB_CTL) |
6399                     DISP_FBC_WM_DIS));
6400
6401         ilk_init_lp_watermarks(dev);
6402
6403         /*
6404          * Based on the document from hardware guys the following bits
6405          * should be set unconditionally in order to enable FBC.
6406          * The bit 22 of 0x42000
6407          * The bit 22 of 0x42004
6408          * The bit 7,8,9 of 0x42020.
6409          */
6410         if (IS_IRONLAKE_M(dev)) {
6411                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6412                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6413                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6414                            ILK_FBCQ_DIS);
6415                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6416                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6417                            ILK_DPARB_GATE);
6418         }
6419
6420         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6421
6422         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6423                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6424                    ILK_ELPIN_409_SELECT);
6425         I915_WRITE(_3D_CHICKEN2,
6426                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6427                    _3D_CHICKEN2_WM_READ_PIPELINED);
6428
6429         /* WaDisableRenderCachePipelinedFlush:ilk */
6430         I915_WRITE(CACHE_MODE_0,
6431                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6432
6433         /* WaDisable_RenderCache_OperationalFlush:ilk */
6434         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6435
6436         g4x_disable_trickle_feed(dev);
6437
6438         ibx_init_clock_gating(dev);
6439 }
6440
6441 static void cpt_init_clock_gating(struct drm_device *dev)
6442 {
6443         struct drm_i915_private *dev_priv = dev->dev_private;
6444         int pipe;
6445         uint32_t val;
6446
6447         /*
6448          * On Ibex Peak and Cougar Point, we need to disable clock
6449          * gating for the panel power sequencer or it will fail to
6450          * start up when no ports are active.
6451          */
6452         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6453                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6454                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6455         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6456                    DPLS_EDP_PPS_FIX_DIS);
6457         /* The below fixes the weird display corruption, a few pixels shifted
6458          * downward, on (only) LVDS of some HP laptops with IVY.
6459          */
6460         for_each_pipe(dev_priv, pipe) {
6461                 val = I915_READ(TRANS_CHICKEN2(pipe));
6462                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6463                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6464                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6465                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6466                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6467                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6468                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6469                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6470         }
6471         /* WADP0ClockGatingDisable */
6472         for_each_pipe(dev_priv, pipe) {
6473                 I915_WRITE(TRANS_CHICKEN1(pipe),
6474                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6475         }
6476 }
6477
6478 static void gen6_check_mch_setup(struct drm_device *dev)
6479 {
6480         struct drm_i915_private *dev_priv = dev->dev_private;
6481         uint32_t tmp;
6482
6483         tmp = I915_READ(MCH_SSKPD);
6484         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6485                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6486                               tmp);
6487 }
6488
6489 static void gen6_init_clock_gating(struct drm_device *dev)
6490 {
6491         struct drm_i915_private *dev_priv = dev->dev_private;
6492         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6493
6494         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6495
6496         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6497                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6498                    ILK_ELPIN_409_SELECT);
6499
6500         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6501         I915_WRITE(_3D_CHICKEN,
6502                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6503
6504         /* WaDisable_RenderCache_OperationalFlush:snb */
6505         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6506
6507         /*
6508          * BSpec recoomends 8x4 when MSAA is used,
6509          * however in practice 16x4 seems fastest.
6510          *
6511          * Note that PS/WM thread counts depend on the WIZ hashing
6512          * disable bit, which we don't touch here, but it's good
6513          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6514          */
6515         I915_WRITE(GEN6_GT_MODE,
6516                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6517
6518         ilk_init_lp_watermarks(dev);
6519
6520         I915_WRITE(CACHE_MODE_0,
6521                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6522
6523         I915_WRITE(GEN6_UCGCTL1,
6524                    I915_READ(GEN6_UCGCTL1) |
6525                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6526                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6527
6528         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6529          * gating disable must be set.  Failure to set it results in
6530          * flickering pixels due to Z write ordering failures after
6531          * some amount of runtime in the Mesa "fire" demo, and Unigine
6532          * Sanctuary and Tropics, and apparently anything else with
6533          * alpha test or pixel discard.
6534          *
6535          * According to the spec, bit 11 (RCCUNIT) must also be set,
6536          * but we didn't debug actual testcases to find it out.
6537          *
6538          * WaDisableRCCUnitClockGating:snb
6539          * WaDisableRCPBUnitClockGating:snb
6540          */
6541         I915_WRITE(GEN6_UCGCTL2,
6542                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6543                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6544
6545         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6546         I915_WRITE(_3D_CHICKEN3,
6547                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6548
6549         /*
6550          * Bspec says:
6551          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6552          * 3DSTATE_SF number of SF output attributes is more than 16."
6553          */
6554         I915_WRITE(_3D_CHICKEN3,
6555                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6556
6557         /*
6558          * According to the spec the following bits should be
6559          * set in order to enable memory self-refresh and fbc:
6560          * The bit21 and bit22 of 0x42000
6561          * The bit21 and bit22 of 0x42004
6562          * The bit5 and bit7 of 0x42020
6563          * The bit14 of 0x70180
6564          * The bit14 of 0x71180
6565          *
6566          * WaFbcAsynchFlipDisableFbcQueue:snb
6567          */
6568         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6569                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6570                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6571         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6572                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6573                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6574         I915_WRITE(ILK_DSPCLK_GATE_D,
6575                    I915_READ(ILK_DSPCLK_GATE_D) |
6576                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6577                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6578
6579         g4x_disable_trickle_feed(dev);
6580
6581         cpt_init_clock_gating(dev);
6582
6583         gen6_check_mch_setup(dev);
6584 }
6585
6586 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6587 {
6588         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6589
6590         /*
6591          * WaVSThreadDispatchOverride:ivb,vlv
6592          *
6593          * This actually overrides the dispatch
6594          * mode for all thread types.
6595          */
6596         reg &= ~GEN7_FF_SCHED_MASK;
6597         reg |= GEN7_FF_TS_SCHED_HW;
6598         reg |= GEN7_FF_VS_SCHED_HW;
6599         reg |= GEN7_FF_DS_SCHED_HW;
6600
6601         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6602 }
6603
6604 static void lpt_init_clock_gating(struct drm_device *dev)
6605 {
6606         struct drm_i915_private *dev_priv = dev->dev_private;
6607
6608         /*
6609          * TODO: this bit should only be enabled when really needed, then
6610          * disabled when not needed anymore in order to save power.
6611          */
6612         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6613                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6614                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6615                            PCH_LP_PARTITION_LEVEL_DISABLE);
6616
6617         /* WADPOClockGatingDisable:hsw */
6618         I915_WRITE(_TRANSA_CHICKEN1,
6619                    I915_READ(_TRANSA_CHICKEN1) |
6620                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6621 }
6622
6623 static void lpt_suspend_hw(struct drm_device *dev)
6624 {
6625         struct drm_i915_private *dev_priv = dev->dev_private;
6626
6627         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6628                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6629
6630                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6631                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6632         }
6633 }
6634
6635 static void broadwell_init_clock_gating(struct drm_device *dev)
6636 {
6637         struct drm_i915_private *dev_priv = dev->dev_private;
6638         enum pipe pipe;
6639         uint32_t misccpctl;
6640
6641         ilk_init_lp_watermarks(dev);
6642
6643         /* WaSwitchSolVfFArbitrationPriority:bdw */
6644         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6645
6646         /* WaPsrDPAMaskVBlankInSRD:bdw */
6647         I915_WRITE(CHICKEN_PAR1_1,
6648                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6649
6650         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6651         for_each_pipe(dev_priv, pipe) {
6652                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6653                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6654                            BDW_DPRS_MASK_VBLANK_SRD);
6655         }
6656
6657         /* WaVSRefCountFullforceMissDisable:bdw */
6658         /* WaDSRefCountFullforceMissDisable:bdw */
6659         I915_WRITE(GEN7_FF_THREAD_MODE,
6660                    I915_READ(GEN7_FF_THREAD_MODE) &
6661                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6662
6663         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6664                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6665
6666         /* WaDisableSDEUnitClockGating:bdw */
6667         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6668                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6669
6670         /*
6671          * WaProgramL3SqcReg1Default:bdw
6672          * WaTempDisableDOPClkGating:bdw
6673          */
6674         misccpctl = I915_READ(GEN7_MISCCPCTL);
6675         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6676         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6677         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6678
6679         /*
6680          * WaGttCachingOffByDefault:bdw
6681          * GTT cache may not work with big pages, so if those
6682          * are ever enabled GTT cache may need to be disabled.
6683          */
6684         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6685
6686         lpt_init_clock_gating(dev);
6687 }
6688
6689 static void haswell_init_clock_gating(struct drm_device *dev)
6690 {
6691         struct drm_i915_private *dev_priv = dev->dev_private;
6692
6693         ilk_init_lp_watermarks(dev);
6694
6695         /* L3 caching of data atomics doesn't work -- disable it. */
6696         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6697         I915_WRITE(HSW_ROW_CHICKEN3,
6698                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6699
6700         /* This is required by WaCatErrorRejectionIssue:hsw */
6701         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6702                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6703                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6704
6705         /* WaVSRefCountFullforceMissDisable:hsw */
6706         I915_WRITE(GEN7_FF_THREAD_MODE,
6707                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6708
6709         /* WaDisable_RenderCache_OperationalFlush:hsw */
6710         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6711
6712         /* enable HiZ Raw Stall Optimization */
6713         I915_WRITE(CACHE_MODE_0_GEN7,
6714                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6715
6716         /* WaDisable4x2SubspanOptimization:hsw */
6717         I915_WRITE(CACHE_MODE_1,
6718                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6719
6720         /*
6721          * BSpec recommends 8x4 when MSAA is used,
6722          * however in practice 16x4 seems fastest.
6723          *
6724          * Note that PS/WM thread counts depend on the WIZ hashing
6725          * disable bit, which we don't touch here, but it's good
6726          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6727          */
6728         I915_WRITE(GEN7_GT_MODE,
6729                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6730
6731         /* WaSampleCChickenBitEnable:hsw */
6732         I915_WRITE(HALF_SLICE_CHICKEN3,
6733                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6734
6735         /* WaSwitchSolVfFArbitrationPriority:hsw */
6736         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6737
6738         /* WaRsPkgCStateDisplayPMReq:hsw */
6739         I915_WRITE(CHICKEN_PAR1_1,
6740                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6741
6742         lpt_init_clock_gating(dev);
6743 }
6744
6745 static void ivybridge_init_clock_gating(struct drm_device *dev)
6746 {
6747         struct drm_i915_private *dev_priv = dev->dev_private;
6748         uint32_t snpcr;
6749
6750         ilk_init_lp_watermarks(dev);
6751
6752         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6753
6754         /* WaDisableEarlyCull:ivb */
6755         I915_WRITE(_3D_CHICKEN3,
6756                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6757
6758         /* WaDisableBackToBackFlipFix:ivb */
6759         I915_WRITE(IVB_CHICKEN3,
6760                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6761                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6762
6763         /* WaDisablePSDDualDispatchEnable:ivb */
6764         if (IS_IVB_GT1(dev))
6765                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6766                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6767
6768         /* WaDisable_RenderCache_OperationalFlush:ivb */
6769         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6770
6771         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6772         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6773                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6774
6775         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6776         I915_WRITE(GEN7_L3CNTLREG1,
6777                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6778         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6779                    GEN7_WA_L3_CHICKEN_MODE);
6780         if (IS_IVB_GT1(dev))
6781                 I915_WRITE(GEN7_ROW_CHICKEN2,
6782                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6783         else {
6784                 /* must write both registers */
6785                 I915_WRITE(GEN7_ROW_CHICKEN2,
6786                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6787                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6788                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6789         }
6790
6791         /* WaForceL3Serialization:ivb */
6792         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6793                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6794
6795         /*
6796          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6797          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6798          */
6799         I915_WRITE(GEN6_UCGCTL2,
6800                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6801
6802         /* This is required by WaCatErrorRejectionIssue:ivb */
6803         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6804                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6805                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6806
6807         g4x_disable_trickle_feed(dev);
6808
6809         gen7_setup_fixed_func_scheduler(dev_priv);
6810
6811         if (0) { /* causes HiZ corruption on ivb:gt1 */
6812                 /* enable HiZ Raw Stall Optimization */
6813                 I915_WRITE(CACHE_MODE_0_GEN7,
6814                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6815         }
6816
6817         /* WaDisable4x2SubspanOptimization:ivb */
6818         I915_WRITE(CACHE_MODE_1,
6819                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6820
6821         /*
6822          * BSpec recommends 8x4 when MSAA is used,
6823          * however in practice 16x4 seems fastest.
6824          *
6825          * Note that PS/WM thread counts depend on the WIZ hashing
6826          * disable bit, which we don't touch here, but it's good
6827          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6828          */
6829         I915_WRITE(GEN7_GT_MODE,
6830                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6831
6832         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6833         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6834         snpcr |= GEN6_MBC_SNPCR_MED;
6835         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6836
6837         if (!HAS_PCH_NOP(dev))
6838                 cpt_init_clock_gating(dev);
6839
6840         gen6_check_mch_setup(dev);
6841 }
6842
6843 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6844 {
6845         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6846
6847         /*
6848          * Disable trickle feed and enable pnd deadline calculation
6849          */
6850         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6851         I915_WRITE(CBR1_VLV, 0);
6852 }
6853
6854 static void valleyview_init_clock_gating(struct drm_device *dev)
6855 {
6856         struct drm_i915_private *dev_priv = dev->dev_private;
6857
6858         vlv_init_display_clock_gating(dev_priv);
6859
6860         /* WaDisableEarlyCull:vlv */
6861         I915_WRITE(_3D_CHICKEN3,
6862                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6863
6864         /* WaDisableBackToBackFlipFix:vlv */
6865         I915_WRITE(IVB_CHICKEN3,
6866                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6867                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6868
6869         /* WaPsdDispatchEnable:vlv */
6870         /* WaDisablePSDDualDispatchEnable:vlv */
6871         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6872                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6873                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6874
6875         /* WaDisable_RenderCache_OperationalFlush:vlv */
6876         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6877
6878         /* WaForceL3Serialization:vlv */
6879         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6880                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6881
6882         /* WaDisableDopClockGating:vlv */
6883         I915_WRITE(GEN7_ROW_CHICKEN2,
6884                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6885
6886         /* This is required by WaCatErrorRejectionIssue:vlv */
6887         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6888                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6889                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6890
6891         gen7_setup_fixed_func_scheduler(dev_priv);
6892
6893         /*
6894          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6895          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6896          */
6897         I915_WRITE(GEN6_UCGCTL2,
6898                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6899
6900         /* WaDisableL3Bank2xClockGate:vlv
6901          * Disabling L3 clock gating- MMIO 940c[25] = 1
6902          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6903         I915_WRITE(GEN7_UCGCTL4,
6904                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6905
6906         /*
6907          * BSpec says this must be set, even though
6908          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6909          */
6910         I915_WRITE(CACHE_MODE_1,
6911                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6912
6913         /*
6914          * BSpec recommends 8x4 when MSAA is used,
6915          * however in practice 16x4 seems fastest.
6916          *
6917          * Note that PS/WM thread counts depend on the WIZ hashing
6918          * disable bit, which we don't touch here, but it's good
6919          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6920          */
6921         I915_WRITE(GEN7_GT_MODE,
6922                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6923
6924         /*
6925          * WaIncreaseL3CreditsForVLVB0:vlv
6926          * This is the hardware default actually.
6927          */
6928         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6929
6930         /*
6931          * WaDisableVLVClockGating_VBIIssue:vlv
6932          * Disable clock gating on th GCFG unit to prevent a delay
6933          * in the reporting of vblank events.
6934          */
6935         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6936 }
6937
6938 static void cherryview_init_clock_gating(struct drm_device *dev)
6939 {
6940         struct drm_i915_private *dev_priv = dev->dev_private;
6941
6942         vlv_init_display_clock_gating(dev_priv);
6943
6944         /* WaVSRefCountFullforceMissDisable:chv */
6945         /* WaDSRefCountFullforceMissDisable:chv */
6946         I915_WRITE(GEN7_FF_THREAD_MODE,
6947                    I915_READ(GEN7_FF_THREAD_MODE) &
6948                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6949
6950         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6951         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6952                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6953
6954         /* WaDisableCSUnitClockGating:chv */
6955         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6956                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6957
6958         /* WaDisableSDEUnitClockGating:chv */
6959         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6960                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6961
6962         /*
6963          * GTT cache may not work with big pages, so if those
6964          * are ever enabled GTT cache may need to be disabled.
6965          */
6966         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6967 }
6968
6969 static void g4x_init_clock_gating(struct drm_device *dev)
6970 {
6971         struct drm_i915_private *dev_priv = dev->dev_private;
6972         uint32_t dspclk_gate;
6973
6974         I915_WRITE(RENCLK_GATE_D1, 0);
6975         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6976                    GS_UNIT_CLOCK_GATE_DISABLE |
6977                    CL_UNIT_CLOCK_GATE_DISABLE);
6978         I915_WRITE(RAMCLK_GATE_D, 0);
6979         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6980                 OVRUNIT_CLOCK_GATE_DISABLE |
6981                 OVCUNIT_CLOCK_GATE_DISABLE;
6982         if (IS_GM45(dev))
6983                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6984         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6985
6986         /* WaDisableRenderCachePipelinedFlush */
6987         I915_WRITE(CACHE_MODE_0,
6988                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6989
6990         /* WaDisable_RenderCache_OperationalFlush:g4x */
6991         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6992
6993         g4x_disable_trickle_feed(dev);
6994 }
6995
6996 static void crestline_init_clock_gating(struct drm_device *dev)
6997 {
6998         struct drm_i915_private *dev_priv = dev->dev_private;
6999
7000         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7001         I915_WRITE(RENCLK_GATE_D2, 0);
7002         I915_WRITE(DSPCLK_GATE_D, 0);
7003         I915_WRITE(RAMCLK_GATE_D, 0);
7004         I915_WRITE16(DEUC, 0);
7005         I915_WRITE(MI_ARB_STATE,
7006                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7007
7008         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7009         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7010 }
7011
7012 static void broadwater_init_clock_gating(struct drm_device *dev)
7013 {
7014         struct drm_i915_private *dev_priv = dev->dev_private;
7015
7016         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7017                    I965_RCC_CLOCK_GATE_DISABLE |
7018                    I965_RCPB_CLOCK_GATE_DISABLE |
7019                    I965_ISC_CLOCK_GATE_DISABLE |
7020                    I965_FBC_CLOCK_GATE_DISABLE);
7021         I915_WRITE(RENCLK_GATE_D2, 0);
7022         I915_WRITE(MI_ARB_STATE,
7023                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7024
7025         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7026         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7027 }
7028
7029 static void gen3_init_clock_gating(struct drm_device *dev)
7030 {
7031         struct drm_i915_private *dev_priv = dev->dev_private;
7032         u32 dstate = I915_READ(D_STATE);
7033
7034         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7035                 DSTATE_DOT_CLOCK_GATING;
7036         I915_WRITE(D_STATE, dstate);
7037
7038         if (IS_PINEVIEW(dev))
7039                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7040
7041         /* IIR "flip pending" means done if this bit is set */
7042         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7043
7044         /* interrupts should cause a wake up from C3 */
7045         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7046
7047         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7048         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7049
7050         I915_WRITE(MI_ARB_STATE,
7051                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7052 }
7053
7054 static void i85x_init_clock_gating(struct drm_device *dev)
7055 {
7056         struct drm_i915_private *dev_priv = dev->dev_private;
7057
7058         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7059
7060         /* interrupts should cause a wake up from C3 */
7061         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7062                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7063
7064         I915_WRITE(MEM_MODE,
7065                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7066 }
7067
7068 static void i830_init_clock_gating(struct drm_device *dev)
7069 {
7070         struct drm_i915_private *dev_priv = dev->dev_private;
7071
7072         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7073
7074         I915_WRITE(MEM_MODE,
7075                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7076                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7077 }
7078
7079 void intel_init_clock_gating(struct drm_device *dev)
7080 {
7081         struct drm_i915_private *dev_priv = dev->dev_private;
7082
7083         if (dev_priv->display.init_clock_gating)
7084                 dev_priv->display.init_clock_gating(dev);
7085 }
7086
7087 void intel_suspend_hw(struct drm_device *dev)
7088 {
7089         if (HAS_PCH_LPT(dev))
7090                 lpt_suspend_hw(dev);
7091 }
7092
7093 /* Set up chip specific power management-related functions */
7094 void intel_init_pm(struct drm_device *dev)
7095 {
7096         struct drm_i915_private *dev_priv = dev->dev_private;
7097
7098         intel_fbc_init(dev_priv);
7099
7100         /* For cxsr */
7101         if (IS_PINEVIEW(dev))
7102                 i915_pineview_get_mem_freq(dev);
7103         else if (IS_GEN5(dev))
7104                 i915_ironlake_get_mem_freq(dev);
7105
7106         /* For FIFO watermark updates */
7107         if (INTEL_INFO(dev)->gen >= 9) {
7108                 skl_setup_wm_latency(dev);
7109
7110                 if (IS_BROXTON(dev))
7111                         dev_priv->display.init_clock_gating =
7112                                 bxt_init_clock_gating;
7113                 else if (IS_SKYLAKE(dev))
7114                         dev_priv->display.init_clock_gating =
7115                                 skl_init_clock_gating;
7116                 dev_priv->display.update_wm = skl_update_wm;
7117                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7118         } else if (HAS_PCH_SPLIT(dev)) {
7119                 ilk_setup_wm_latency(dev);
7120
7121                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7122                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7123                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7124                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7125                         dev_priv->display.update_wm = ilk_update_wm;
7126                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7127                 } else {
7128                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7129                                       "Disable CxSR\n");
7130                 }
7131
7132                 if (IS_GEN5(dev))
7133                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7134                 else if (IS_GEN6(dev))
7135                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7136                 else if (IS_IVYBRIDGE(dev))
7137                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7138                 else if (IS_HASWELL(dev))
7139                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7140                 else if (INTEL_INFO(dev)->gen == 8)
7141                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7142         } else if (IS_CHERRYVIEW(dev)) {
7143                 vlv_setup_wm_latency(dev);
7144
7145                 dev_priv->display.update_wm = vlv_update_wm;
7146                 dev_priv->display.init_clock_gating =
7147                         cherryview_init_clock_gating;
7148         } else if (IS_VALLEYVIEW(dev)) {
7149                 vlv_setup_wm_latency(dev);
7150
7151                 dev_priv->display.update_wm = vlv_update_wm;
7152                 dev_priv->display.init_clock_gating =
7153                         valleyview_init_clock_gating;
7154         } else if (IS_PINEVIEW(dev)) {
7155                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7156                                             dev_priv->is_ddr3,
7157                                             dev_priv->fsb_freq,
7158                                             dev_priv->mem_freq)) {
7159                         DRM_INFO("failed to find known CxSR latency "
7160                                  "(found ddr%s fsb freq %d, mem freq %d), "
7161                                  "disabling CxSR\n",
7162                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7163                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7164                         /* Disable CxSR and never update its watermark again */
7165                         intel_set_memory_cxsr(dev_priv, false);
7166                         dev_priv->display.update_wm = NULL;
7167                 } else
7168                         dev_priv->display.update_wm = pineview_update_wm;
7169                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7170         } else if (IS_G4X(dev)) {
7171                 dev_priv->display.update_wm = g4x_update_wm;
7172                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7173         } else if (IS_GEN4(dev)) {
7174                 dev_priv->display.update_wm = i965_update_wm;
7175                 if (IS_CRESTLINE(dev))
7176                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7177                 else if (IS_BROADWATER(dev))
7178                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7179         } else if (IS_GEN3(dev)) {
7180                 dev_priv->display.update_wm = i9xx_update_wm;
7181                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7182                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7183         } else if (IS_GEN2(dev)) {
7184                 if (INTEL_INFO(dev)->num_pipes == 1) {
7185                         dev_priv->display.update_wm = i845_update_wm;
7186                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7187                 } else {
7188                         dev_priv->display.update_wm = i9xx_update_wm;
7189                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7190                 }
7191
7192                 if (IS_I85X(dev) || IS_I865G(dev))
7193                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7194                 else
7195                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7196         } else {
7197                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7198         }
7199 }
7200
7201 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7202 {
7203         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7204
7205         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7206                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7207                 return -EAGAIN;
7208         }
7209
7210         I915_WRITE(GEN6_PCODE_DATA, *val);
7211         I915_WRITE(GEN6_PCODE_DATA1, 0);
7212         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7213
7214         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7215                      500)) {
7216                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7217                 return -ETIMEDOUT;
7218         }
7219
7220         *val = I915_READ(GEN6_PCODE_DATA);
7221         I915_WRITE(GEN6_PCODE_DATA, 0);
7222
7223         return 0;
7224 }
7225
7226 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7227 {
7228         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7229
7230         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7231                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7232                 return -EAGAIN;
7233         }
7234
7235         I915_WRITE(GEN6_PCODE_DATA, val);
7236         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7237
7238         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7239                      500)) {
7240                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7241                 return -ETIMEDOUT;
7242         }
7243
7244         I915_WRITE(GEN6_PCODE_DATA, 0);
7245
7246         return 0;
7247 }
7248
7249 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7250 {
7251         switch (czclk_freq) {
7252         case 200:
7253                 return 10;
7254         case 267:
7255                 return 12;
7256         case 320:
7257         case 333:
7258                 return 16;
7259         case 400:
7260                 return 20;
7261         default:
7262                 return -1;
7263         }
7264 }
7265
7266 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7267 {
7268         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7269
7270         div = vlv_gpu_freq_div(czclk_freq);
7271         if (div < 0)
7272                 return div;
7273
7274         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7275 }
7276
7277 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7278 {
7279         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7280
7281         mul = vlv_gpu_freq_div(czclk_freq);
7282         if (mul < 0)
7283                 return mul;
7284
7285         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7286 }
7287
7288 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7289 {
7290         int div, czclk_freq = dev_priv->rps.cz_freq;
7291
7292         div = vlv_gpu_freq_div(czclk_freq) / 2;
7293         if (div < 0)
7294                 return div;
7295
7296         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7297 }
7298
7299 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7300 {
7301         int mul, czclk_freq = dev_priv->rps.cz_freq;
7302
7303         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7304         if (mul < 0)
7305                 return mul;
7306
7307         /* CHV needs even values */
7308         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7309 }
7310
7311 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7312 {
7313         if (IS_GEN9(dev_priv->dev))
7314                 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7315         else if (IS_CHERRYVIEW(dev_priv->dev))
7316                 return chv_gpu_freq(dev_priv, val);
7317         else if (IS_VALLEYVIEW(dev_priv->dev))
7318                 return byt_gpu_freq(dev_priv, val);
7319         else
7320                 return val * GT_FREQUENCY_MULTIPLIER;
7321 }
7322
7323 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7324 {
7325         if (IS_GEN9(dev_priv->dev))
7326                 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7327         else if (IS_CHERRYVIEW(dev_priv->dev))
7328                 return chv_freq_opcode(dev_priv, val);
7329         else if (IS_VALLEYVIEW(dev_priv->dev))
7330                 return byt_freq_opcode(dev_priv, val);
7331         else
7332                 return val / GT_FREQUENCY_MULTIPLIER;
7333 }
7334
7335 struct request_boost {
7336         struct work_struct work;
7337         struct drm_i915_gem_request *req;
7338 };
7339
7340 static void __intel_rps_boost_work(struct work_struct *work)
7341 {
7342         struct request_boost *boost = container_of(work, struct request_boost, work);
7343         struct drm_i915_gem_request *req = boost->req;
7344
7345         if (!i915_gem_request_completed(req, true))
7346                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7347                                req->emitted_jiffies);
7348
7349         i915_gem_request_unreference__unlocked(req);
7350         kfree(boost);
7351 }
7352
7353 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7354                                        struct drm_i915_gem_request *req)
7355 {
7356         struct request_boost *boost;
7357
7358         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7359                 return;
7360
7361         if (i915_gem_request_completed(req, true))
7362                 return;
7363
7364         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7365         if (boost == NULL)
7366                 return;
7367
7368         i915_gem_request_reference(req);
7369         boost->req = req;
7370
7371         INIT_WORK(&boost->work, __intel_rps_boost_work);
7372         queue_work(to_i915(dev)->wq, &boost->work);
7373 }
7374
7375 void intel_pm_setup(struct drm_device *dev)
7376 {
7377         struct drm_i915_private *dev_priv = dev->dev_private;
7378
7379         mutex_init(&dev_priv->rps.hw_lock);
7380         spin_lock_init(&dev_priv->rps.client_lock);
7381
7382         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7383                           intel_gen6_powersave_work);
7384         INIT_LIST_HEAD(&dev_priv->rps.clients);
7385         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7386         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7387
7388         dev_priv->pm.suspended = false;
7389 }