drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 static void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         struct intel_engine_cs *ring = req->ring;
  99         u32 cmd;
 100         int ret;
 101
 102         cmd = MI_FLUSH;
 103         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 104                 cmd |= MI_NO_WRITE_FLUSH;
 105
 106         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 107                 cmd |= MI_READ_FLUSH;
 108
 109         ret = intel_ring_begin(req, 2);
 110         if (ret)
 111                 return ret;
 112
 113         intel_ring_emit(ring, cmd);
 114         intel_ring_emit(ring, MI_NOOP);
 115         intel_ring_advance(ring);
 116
 117         return 0;
 118 }
 119
 120 static int
 121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 122                        u32      invalidate_domains,
 123                        u32      flush_domains)
 124 {
 125         struct intel_engine_cs *ring = req->ring;
 126         struct drm_device *dev = ring->dev;
 127         u32 cmd;
 128         int ret;
 129
 130         /*
 131          * read/write caches:
 132          *
 133          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 134          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 135          * also flushed at 2d versus 3d pipeline switches.
 136          *
 137          * read-only caches:
 138          *
 139          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 140          * MI_READ_FLUSH is set, and is always flushed on 965.
 141          *
 142          * I915_GEM_DOMAIN_COMMAND may not exist?
 143          *
 144          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 145          * invalidated when MI_EXE_FLUSH is set.
 146          *
 147          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 148          * invalidated with every MI_FLUSH.
 149          *
 150          * TLBs:
 151          *
 152          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 153          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 154          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 155          * are flushed at any MI_FLUSH.
 156          */
 157
 158         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 159         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 160                 cmd &= ~MI_NO_WRITE_FLUSH;
 161         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 162                 cmd |= MI_EXE_FLUSH;
 163
 164         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 165             (IS_G4X(dev) || IS_GEN5(dev)))
 166                 cmd |= MI_INVALIDATE_ISP;
 167
 168         ret = intel_ring_begin(req, 2);
 169         if (ret)
 170                 return ret;
 171
 172         intel_ring_emit(ring, cmd);
 173         intel_ring_emit(ring, MI_NOOP);
 174         intel_ring_advance(ring);
 175
 176         return 0;
 177 }
 178
 179 /**
 180  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 181  * implementing two workarounds on gen6.  From section 1.4.7.1
 182  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 183  *
 184  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 185  * produced by non-pipelined state commands), software needs to first
 186  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 187  * 0.
 188  *
 189  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 190  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 191  *
 192  * And the workaround for these two requires this workaround first:
 193  *
 194  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 195  * BEFORE the pipe-control with a post-sync op and no write-cache
 196  * flushes.
 197  *
 198  * And this last workaround is tricky because of the requirements on
 199  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 200  * volume 2 part 1:
 201  *
 202  *     "1 of the following must also be set:
 203  *      - Render Target Cache Flush Enable ([12] of DW1)
 204  *      - Depth Cache Flush Enable ([0] of DW1)
 205  *      - Stall at Pixel Scoreboard ([1] of DW1)
 206  *      - Depth Stall ([13] of DW1)
 207  *      - Post-Sync Operation ([13] of DW1)
 208  *      - Notify Enable ([8] of DW1)"
 209  *
 210  * The cache flushes require the workaround flush that triggered this
 211  * one, so we can't use it.  Depth stall would trigger the same.
 212  * Post-sync nonzero is what triggered this second workaround, so we
 213  * can't use that one either.  Notify enable is IRQs, which aren't
 214  * really our business.  That leaves only stall at scoreboard.
 215  */
 216 static int
 217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 218 {
 219         struct intel_engine_cs *ring = req->ring;
 220         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 221         int ret;
 222
 223         ret = intel_ring_begin(req, 6);
 224         if (ret)
 225                 return ret;
 226
 227         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 228         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 229                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 230         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 231         intel_ring_emit(ring, 0); /* low dword */
 232         intel_ring_emit(ring, 0); /* high dword */
 233         intel_ring_emit(ring, MI_NOOP);
 234         intel_ring_advance(ring);
 235
 236         ret = intel_ring_begin(req, 6);
 237         if (ret)
 238                 return ret;
 239
 240         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 241         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 242         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 243         intel_ring_emit(ring, 0);
 244         intel_ring_emit(ring, 0);
 245         intel_ring_emit(ring, MI_NOOP);
 246         intel_ring_advance(ring);
 247
 248         return 0;
 249 }
 250
 251 static int
 252 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 253                        u32 invalidate_domains, u32 flush_domains)
 254 {
 255         struct intel_engine_cs *ring = req->ring;
 256         u32 flags = 0;
 257         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 258         int ret;
 259
 260         /* Force SNB workarounds for PIPE_CONTROL flushes */
 261         ret = intel_emit_post_sync_nonzero_flush(req);
 262         if (ret)
 263                 return ret;
 264
 265         /* Just flush everything.  Experiments have shown that reducing the
 266          * number of bits based on the write domains has little performance
 267          * impact.
 268          */
 269         if (flush_domains) {
 270                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 271                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 272                 /*
 273                  * Ensure that any following seqno writes only happen
 274                  * when the render cache is indeed flushed.
 275                  */
 276                 flags |= PIPE_CONTROL_CS_STALL;
 277         }
 278         if (invalidate_domains) {
 279                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 280                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 282                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 283                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 284                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 285                 /*
 286                  * TLB invalidate requires a post-sync write.
 287                  */
 288                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 289         }
 290
 291         ret = intel_ring_begin(req, 4);
 292         if (ret)
 293                 return ret;
 294
 295         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 296         intel_ring_emit(ring, flags);
 297         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 298         intel_ring_emit(ring, 0);
 299         intel_ring_advance(ring);
 300
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 306 {
 307         struct intel_engine_cs *ring = req->ring;
 308         int ret;
 309
 310         ret = intel_ring_begin(req, 4);
 311         if (ret)
 312                 return ret;
 313
 314         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 315         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 316                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 317         intel_ring_emit(ring, 0);
 318         intel_ring_emit(ring, 0);
 319         intel_ring_advance(ring);
 320
 321         return 0;
 322 }
 323
 324 static int
 325 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 326                        u32 invalidate_domains, u32 flush_domains)
 327 {
 328         struct intel_engine_cs *ring = req->ring;
 329         u32 flags = 0;
 330         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 331         int ret;
 332
 333         /*
 334          * Ensure that any following seqno writes only happen when the render
 335          * cache is indeed flushed.
 336          *
 337          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 338          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 339          * don't try to be clever and just set it unconditionally.
 340          */
 341         flags |= PIPE_CONTROL_CS_STALL;
 342
 343         /* Just flush everything.  Experiments have shown that reducing the
 344          * number of bits based on the write domains has little performance
 345          * impact.
 346          */
 347         if (flush_domains) {
 348                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 349                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 350         }
 351         if (invalidate_domains) {
 352                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 353                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 354                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 355                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 356                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 357                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 358                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 359                 /*
 360                  * TLB invalidate requires a post-sync write.
 361                  */
 362                 flags |= PIPE_CONTROL_QW_WRITE;
 363                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 364
 365                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 366
 367                 /* Workaround: we must issue a pipe_control with CS-stall bit
 368                  * set before a pipe_control command that has the state cache
 369                  * invalidate bit set. */
 370                 gen7_render_ring_cs_stall_wa(req);
 371         }
 372
 373         ret = intel_ring_begin(req, 4);
 374         if (ret)
 375                 return ret;
 376
 377         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 378         intel_ring_emit(ring, flags);
 379         intel_ring_emit(ring, scratch_addr);
 380         intel_ring_emit(ring, 0);
 381         intel_ring_advance(ring);
 382
 383         return 0;
 384 }
 385
 386 static int
 387 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 388                        u32 flags, u32 scratch_addr)
 389 {
 390         struct intel_engine_cs *ring = req->ring;
 391         int ret;
 392
 393         ret = intel_ring_begin(req, 6);
 394         if (ret)
 395                 return ret;
 396
 397         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 398         intel_ring_emit(ring, flags);
 399         intel_ring_emit(ring, scratch_addr);
 400         intel_ring_emit(ring, 0);
 401         intel_ring_emit(ring, 0);
 402         intel_ring_emit(ring, 0);
 403         intel_ring_advance(ring);
 404
 405         return 0;
 406 }
 407
 408 static int
 409 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 410                        u32 invalidate_domains, u32 flush_domains)
 411 {
 412         u32 flags = 0;
 413         u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 414         int ret;
 415
 416         flags |= PIPE_CONTROL_CS_STALL;
 417
 418         if (flush_domains) {
 419                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 420                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 421         }
 422         if (invalidate_domains) {
 423                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 424                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 425                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 426                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 427                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 428                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 429                 flags |= PIPE_CONTROL_QW_WRITE;
 430                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 431
 432                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 433                 ret = gen8_emit_pipe_control(req,
 434                                              PIPE_CONTROL_CS_STALL |
 435                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 436                                              0);
 437                 if (ret)
 438                         return ret;
 439         }
 440
 441         return gen8_emit_pipe_control(req, flags, scratch_addr);
 442 }
 443
 444 static void ring_write_tail(struct intel_engine_cs *ring,
 445                             u32 value)
 446 {
 447         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 448         I915_WRITE_TAIL(ring, value);
 449 }
 450
 451 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 452 {
 453         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 454         u64 acthd;
 455
 456         if (INTEL_INFO(ring->dev)->gen >= 8)
 457                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 458                                          RING_ACTHD_UDW(ring->mmio_base));
 459         else if (INTEL_INFO(ring->dev)->gen >= 4)
 460                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 461         else
 462                 acthd = I915_READ(ACTHD);
 463
 464         return acthd;
 465 }
 466
 467 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 468 {
 469         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 470         u32 addr;
 471
 472         addr = dev_priv->status_page_dmah->busaddr;
 473         if (INTEL_INFO(ring->dev)->gen >= 4)
 474                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 475         I915_WRITE(HWS_PGA, addr);
 476 }
 477
 478 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 479 {
 480         struct drm_device *dev = ring->dev;
 481         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 482         u32 mmio = 0;
 483
 484         /* The ring status page addresses are no longer next to the rest of
 485          * the ring registers as of gen7.
 486          */
 487         if (IS_GEN7(dev)) {
 488                 switch (ring->id) {
 489                 case RCS:
 490                         mmio = RENDER_HWS_PGA_GEN7;
 491                         break;
 492                 case BCS:
 493                         mmio = BLT_HWS_PGA_GEN7;
 494                         break;
 495                 /*
 496                  * VCS2 actually doesn't exist on Gen7. Only shut up
 497                  * gcc switch check warning
 498                  */
 499                 case VCS2:
 500                 case VCS:
 501                         mmio = BSD_HWS_PGA_GEN7;
 502                         break;
 503                 case VECS:
 504                         mmio = VEBOX_HWS_PGA_GEN7;
 505                         break;
 506                 }
 507         } else if (IS_GEN6(ring->dev)) {
 508                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 509         } else {
 510                 /* XXX: gen8 returns to sanity */
 511                 mmio = RING_HWS_PGA(ring->mmio_base);
 512         }
 513
 514         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 515         POSTING_READ(mmio);
 516
 517         /*
 518          * Flush the TLB for this page
 519          *
 520          * FIXME: These two bits have disappeared on gen8, so a question
 521          * arises: do we still need this and if so how should we go about
 522          * invalidating the TLB?
 523          */
 524         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 525                 u32 reg = RING_INSTPM(ring->mmio_base);
 526
 527                 /* ring should be idle before issuing a sync flush*/
 528                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 529
 530                 I915_WRITE(reg,
 531                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 532                                               INSTPM_SYNC_FLUSH));
 533                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 534                              1000))
 535                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 536                                   ring->name);
 537         }
 538 }
 539
 540 static bool stop_ring(struct intel_engine_cs *ring)
 541 {
 542         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 543
 544         if (!IS_GEN2(ring->dev)) {
 545                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 546                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 547                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 548                         /* Sometimes we observe that the idle flag is not
 549                          * set even though the ring is empty. So double
 550                          * check before giving up.
 551                          */
 552                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 553                                 return false;
 554                 }
 555         }
 556
 557         I915_WRITE_CTL(ring, 0);
 558         I915_WRITE_HEAD(ring, 0);
 559         ring->write_tail(ring, 0);
 560
 561         if (!IS_GEN2(ring->dev)) {
 562                 (void)I915_READ_CTL(ring);
 563                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 564         }
 565
 566         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 567 }
 568
 569 static int init_ring_common(struct intel_engine_cs *ring)
 570 {
 571         struct drm_device *dev = ring->dev;
 572         struct drm_i915_private *dev_priv = dev->dev_private;
 573         struct intel_ringbuffer *ringbuf = ring->buffer;
 574         struct drm_i915_gem_object *obj = ringbuf->obj;
 575         int ret = 0;
 576
 577         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 578
 579         if (!stop_ring(ring)) {
 580                 /* G45 ring initialization often fails to reset head to zero */
 581                 DRM_DEBUG_KMS("%s head not reset to zero "
 582                               "ctl %08x head %08x tail %08x start %08x\n",
 583                               ring->name,
 584                               I915_READ_CTL(ring),
 585                               I915_READ_HEAD(ring),
 586                               I915_READ_TAIL(ring),
 587                               I915_READ_START(ring));
 588
 589                 if (!stop_ring(ring)) {
 590                         DRM_ERROR("failed to set %s head to zero "
 591                                   "ctl %08x head %08x tail %08x start %08x\n",
 592                                   ring->name,
 593                                   I915_READ_CTL(ring),
 594                                   I915_READ_HEAD(ring),
 595                                   I915_READ_TAIL(ring),
 596                                   I915_READ_START(ring));
 597                         ret = -EIO;
 598                         goto out;
 599                 }
 600         }
 601
 602         if (I915_NEED_GFX_HWS(dev))
 603                 intel_ring_setup_status_page(ring);
 604         else
 605                 ring_setup_phys_status_page(ring);
 606
 607         /* Enforce ordering by reading HEAD register back */
 608         I915_READ_HEAD(ring);
 609
 610         /* Initialize the ring. This must happen _after_ we've cleared the ring
 611          * registers with the above sequence (the readback of the HEAD registers
 612          * also enforces ordering), otherwise the hw might lose the new ring
 613          * register values. */
 614         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 615
 616         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 617         if (I915_READ_HEAD(ring))
 618                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 619                           ring->name, I915_READ_HEAD(ring));
 620         I915_WRITE_HEAD(ring, 0);
 621         (void)I915_READ_HEAD(ring);
 622
 623         I915_WRITE_CTL(ring,
 624                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 625                         | RING_VALID);
 626
 627         /* If the head is still not zero, the ring is dead */
 628         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 629                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 630                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 631                 DRM_ERROR("%s initialization failed "
 632                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 633                           ring->name,
 634                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 635                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 636                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 637                 ret = -EIO;
 638                 goto out;
 639         }
 640
 641         ringbuf->last_retired_head = -1;
 642         ringbuf->head = I915_READ_HEAD(ring);
 643         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 644         intel_ring_update_space(ringbuf);
 645
 646         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 647
 648 out:
 649         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 650
 651         return ret;
 652 }
 653
 654 void
 655 intel_fini_pipe_control(struct intel_engine_cs *ring)
 656 {
 657         struct drm_device *dev = ring->dev;
 658
 659         if (ring->scratch.obj == NULL)
 660                 return;
 661
 662         if (INTEL_INFO(dev)->gen >= 5) {
 663                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 664                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 665         }
 666
 667         drm_gem_object_unreference(&ring->scratch.obj->base);
 668         ring->scratch.obj = NULL;
 669 }
 670
 671 int
 672 intel_init_pipe_control(struct intel_engine_cs *ring)
 673 {
 674         int ret;
 675
 676         WARN_ON(ring->scratch.obj);
 677
 678         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 679         if (ring->scratch.obj == NULL) {
 680                 DRM_ERROR("Failed to allocate seqno page\n");
 681                 ret = -ENOMEM;
 682                 goto err;
 683         }
 684
 685         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 686         if (ret)
 687                 goto err_unref;
 688
 689         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 690         if (ret)
 691                 goto err_unref;
 692
 693         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 694         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 695         if (ring->scratch.cpu_page == NULL) {
 696                 ret = -ENOMEM;
 697                 goto err_unpin;
 698         }
 699
 700         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 701                          ring->name, ring->scratch.gtt_offset);
 702         return 0;
 703
 704 err_unpin:
 705         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 706 err_unref:
 707         drm_gem_object_unreference(&ring->scratch.obj->base);
 708 err:
 709         return ret;
 710 }
 711
 712 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 713 {
 714         int ret, i;
 715         struct intel_engine_cs *ring = req->ring;
 716         struct drm_device *dev = ring->dev;
 717         struct drm_i915_private *dev_priv = dev->dev_private;
 718         struct i915_workarounds *w = &dev_priv->workarounds;
 719
 720         if (w->count == 0)
 721                 return 0;
 722
 723         ring->gpu_caches_dirty = true;
 724         ret = intel_ring_flush_all_caches(req);
 725         if (ret)
 726                 return ret;
 727
 728         ret = intel_ring_begin(req, (w->count * 2 + 2));
 729         if (ret)
 730                 return ret;
 731
 732         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 733         for (i = 0; i < w->count; i++) {
 734                 intel_ring_emit(ring, w->reg[i].addr);
 735                 intel_ring_emit(ring, w->reg[i].value);
 736         }
 737         intel_ring_emit(ring, MI_NOOP);
 738
 739         intel_ring_advance(ring);
 740
 741         ring->gpu_caches_dirty = true;
 742         ret = intel_ring_flush_all_caches(req);
 743         if (ret)
 744                 return ret;
 745
 746         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 747
 748         return 0;
 749 }
 750
 751 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 752 {
 753         int ret;
 754
 755         ret = intel_ring_workarounds_emit(req);
 756         if (ret != 0)
 757                 return ret;
 758
 759         ret = i915_gem_render_state_init(req);
 760         if (ret)
 761                 DRM_ERROR("init render state: %d\n", ret);
 762
 763         return ret;
 764 }
 765
 766 static int wa_add(struct drm_i915_private *dev_priv,
 767                   const u32 addr, const u32 mask, const u32 val)
 768 {
 769         const u32 idx = dev_priv->workarounds.count;
 770
 771         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 772                 return -ENOSPC;
 773
 774         dev_priv->workarounds.reg[idx].addr = addr;
 775         dev_priv->workarounds.reg[idx].value = val;
 776         dev_priv->workarounds.reg[idx].mask = mask;
 777
 778         dev_priv->workarounds.count++;
 779
 780         return 0;
 781 }
 782
 783 #define WA_REG(addr, mask, val) do { \
 784                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 785                 if (r) \
 786                         return r; \
 787         } while (0)
 788
 789 #define WA_SET_BIT_MASKED(addr, mask) \
 790         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 791
 792 #define WA_CLR_BIT_MASKED(addr, mask) \
 793         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 794
 795 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 796         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 797
 798 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 799 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 800
 801 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 802
 803 static int gen8_init_workarounds(struct intel_engine_cs *ring)
 804 {
 805         struct drm_device *dev = ring->dev;
 806         struct drm_i915_private *dev_priv = dev->dev_private;
 807
 808         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 809
 810         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 811         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 812
 813         /* WaDisablePartialInstShootdown:bdw,chv */
 814         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 815                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 816
 817         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 818          * workaround for for a possible hang in the unlikely event a TLB
 819          * invalidation occurs during a PSD flush.
 820          */
 821         /* WaForceEnableNonCoherent:bdw,chv */
 822         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 823         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 824                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 825                           HDC_FORCE_NON_COHERENT);
 826
 827         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 828          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 829          *  polygons in the same 8x4 pixel/sample area to be processed without
 830          *  stalling waiting for the earlier ones to write to Hierarchical Z
 831          *  buffer."
 832          *
 833          * This optimization is off by default for BDW and CHV; turn it on.
 834          */
 835         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 836
 837         /* Wa4x4STCOptimizationDisable:bdw,chv */
 838         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 839
 840         /*
 841          * BSpec recommends 8x4 when MSAA is used,
 842          * however in practice 16x4 seems fastest.
 843          *
 844          * Note that PS/WM thread counts depend on the WIZ hashing
 845          * disable bit, which we don't touch here, but it's good
 846          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 847          */
 848         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 849                             GEN6_WIZ_HASHING_MASK,
 850                             GEN6_WIZ_HASHING_16x4);
 851
 852         return 0;
 853 }
 854
 855 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 856 {
 857         int ret;
 858         struct drm_device *dev = ring->dev;
 859         struct drm_i915_private *dev_priv = dev->dev_private;
 860
 861         ret = gen8_init_workarounds(ring);
 862         if (ret)
 863                 return ret;
 864
 865         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 866         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 867
 868         /* WaDisableDopClockGating:bdw */
 869         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 870                           DOP_CLOCK_GATING_DISABLE);
 871
 872         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 873                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 874
 875         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 876                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 877                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 878                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 879                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 880
 881         return 0;
 882 }
 883
 884 static int chv_init_workarounds(struct intel_engine_cs *ring)
 885 {
 886         int ret;
 887         struct drm_device *dev = ring->dev;
 888         struct drm_i915_private *dev_priv = dev->dev_private;
 889
 890         ret = gen8_init_workarounds(ring);
 891         if (ret)
 892                 return ret;
 893
 894         /* WaDisableThreadStallDopClockGating:chv */
 895         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 896
 897         /* Improve HiZ throughput on CHV. */
 898         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 899
 900         return 0;
 901 }
 902
 903 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 904 {
 905         struct drm_device *dev = ring->dev;
 906         struct drm_i915_private *dev_priv = dev->dev_private;
 907         uint32_t tmp;
 908
 909         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 910         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 911                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 912
 913         /* WaDisableKillLogic:bxt,skl */
 914         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 915                    ECOCHK_DIS_TLB);
 916
 917         /* WaDisablePartialInstShootdown:skl,bxt */
 918         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 919                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 920
 921         /* Syncing dependencies between camera and graphics:skl,bxt */
 922         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 923                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 924
 925         if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
 926             INTEL_REVID(dev) == SKL_REVID_B0)) ||
 927             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 928                 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 929                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 930                                   GEN9_DG_MIRROR_FIX_ENABLE);
 931         }
 932
 933         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
 934             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
 935                 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 936                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 937                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 938                 /*
 939                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 940                  * but we do that in per ctx batchbuffer as there is an issue
 941                  * with this register not getting restored on ctx restore
 942                  */
 943         }
 944
 945         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
 946             IS_BROXTON(dev)) {
 947                 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 948                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 949                                   GEN9_ENABLE_YV12_BUGFIX);
 950         }
 951
 952         /* Wa4x4STCOptimizationDisable:skl,bxt */
 953         /* WaDisablePartialResolveInVc:skl,bxt */
 954         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 955                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 956
 957         /* WaCcsTlbPrefetchDisable:skl,bxt */
 958         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 959                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 960
 961         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 962         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
 963             (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
 964                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 965                                   PIXEL_MASK_CAMMING_DISABLE);
 966
 967         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 968         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 969         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
 970             (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
 971                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 972         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 973
 974         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 975         if (IS_SKYLAKE(dev) ||
 976             (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
 977                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 978                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 979         }
 980
 981         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 982         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 983
 984         return 0;
 985 }
 986
 987 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 988 {
 989         struct drm_device *dev = ring->dev;
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         u8 vals[3] = { 0, 0, 0 };
 992         unsigned int i;
 993
 994         for (i = 0; i < 3; i++) {
 995                 u8 ss;
 996
 997                 /*
 998                  * Only consider slices where one, and only one, subslice has 7
 999                  * EUs
1000                  */
1001                 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1002                         continue;
1003
1004                 /*
1005                  * subslice_7eu[i] != 0 (because of the check above) and
1006                  * ss_max == 4 (maximum number of subslices possible per slice)
1007                  *
1008                  * ->    0 <= ss <= 3;
1009                  */
1010                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1011                 vals[i] = 3 - ss;
1012         }
1013
1014         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1015                 return 0;
1016
1017         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1018         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1019                             GEN9_IZ_HASHING_MASK(2) |
1020                             GEN9_IZ_HASHING_MASK(1) |
1021                             GEN9_IZ_HASHING_MASK(0),
1022                             GEN9_IZ_HASHING(2, vals[2]) |
1023                             GEN9_IZ_HASHING(1, vals[1]) |
1024                             GEN9_IZ_HASHING(0, vals[0]));
1025
1026         return 0;
1027 }
1028
1029 static int skl_init_workarounds(struct intel_engine_cs *ring)
1030 {
1031         int ret;
1032         struct drm_device *dev = ring->dev;
1033         struct drm_i915_private *dev_priv = dev->dev_private;
1034
1035         ret = gen9_init_workarounds(ring);
1036         if (ret)
1037                 return ret;
1038
1039         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1040                 /* WaDisableHDCInvalidation:skl */
1041                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1042                            BDW_DISABLE_HDC_INVALIDATION);
1043
1044                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1045                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1046                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1047         }
1048
1049         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1050          * involving this register should also be added to WA batch as required.
1051          */
1052         if (INTEL_REVID(dev) <= SKL_REVID_E0)
1053                 /* WaDisableLSQCROPERFforOCL:skl */
1054                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1055                            GEN8_LQSC_RO_PERF_DIS);
1056
1057         /* WaEnableGapsTsvCreditFix:skl */
1058         if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
1059                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1060                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1061         }
1062
1063         /* WaDisablePowerCompilerClockGating:skl */
1064         if (INTEL_REVID(dev) == SKL_REVID_B0)
1065                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1066                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1067
1068         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1069                 /*
1070                  *Use Force Non-Coherent whenever executing a 3D context. This
1071                  * is a workaround for a possible hang in the unlikely event
1072                  * a TLB invalidation occurs during a PSD flush.
1073                  */
1074                 /* WaForceEnableNonCoherent:skl */
1075                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1076                                   HDC_FORCE_NON_COHERENT);
1077         }
1078
1079         if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1080             INTEL_REVID(dev) == SKL_REVID_D0)
1081                 /* WaBarrierPerformanceFixDisable:skl */
1082                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1083                                   HDC_FENCE_DEST_SLM_DISABLE |
1084                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1085
1086         /* WaDisableSbeCacheDispatchPortSharing:skl */
1087         if (INTEL_REVID(dev) <= SKL_REVID_F0) {
1088                 WA_SET_BIT_MASKED(
1089                         GEN7_HALF_SLICE_CHICKEN1,
1090                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1091         }
1092
1093         return skl_tune_iz_hashing(ring);
1094 }
1095
1096 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1097 {
1098         int ret;
1099         struct drm_device *dev = ring->dev;
1100         struct drm_i915_private *dev_priv = dev->dev_private;
1101
1102         ret = gen9_init_workarounds(ring);
1103         if (ret)
1104                 return ret;
1105
1106         /* WaStoreMultiplePTEenable:bxt */
1107         /* This is a requirement according to Hardware specification */
1108         if (INTEL_REVID(dev) == BXT_REVID_A0)
1109                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1110
1111         /* WaSetClckGatingDisableMedia:bxt */
1112         if (INTEL_REVID(dev) == BXT_REVID_A0) {
1113                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1114                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1115         }
1116
1117         /* WaDisableThreadStallDopClockGating:bxt */
1118         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1119                           STALL_DOP_GATING_DISABLE);
1120
1121         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1122         if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1123                 WA_SET_BIT_MASKED(
1124                         GEN7_HALF_SLICE_CHICKEN1,
1125                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1126         }
1127
1128         return 0;
1129 }
1130
1131 int init_workarounds_ring(struct intel_engine_cs *ring)
1132 {
1133         struct drm_device *dev = ring->dev;
1134         struct drm_i915_private *dev_priv = dev->dev_private;
1135
1136         WARN_ON(ring->id != RCS);
1137
1138         dev_priv->workarounds.count = 0;
1139
1140         if (IS_BROADWELL(dev))
1141                 return bdw_init_workarounds(ring);
1142
1143         if (IS_CHERRYVIEW(dev))
1144                 return chv_init_workarounds(ring);
1145
1146         if (IS_SKYLAKE(dev))
1147                 return skl_init_workarounds(ring);
1148
1149         if (IS_BROXTON(dev))
1150                 return bxt_init_workarounds(ring);
1151
1152         return 0;
1153 }
1154
1155 static int init_render_ring(struct intel_engine_cs *ring)
1156 {
1157         struct drm_device *dev = ring->dev;
1158         struct drm_i915_private *dev_priv = dev->dev_private;
1159         int ret = init_ring_common(ring);
1160         if (ret)
1161                 return ret;
1162
1163         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1164         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1165                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1166
1167         /* We need to disable the AsyncFlip performance optimisations in order
1168          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1169          * programmed to '1' on all products.
1170          *
1171          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1172          */
1173         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1174                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1175
1176         /* Required for the hardware to program scanline values for waiting */
1177         /* WaEnableFlushTlbInvalidationMode:snb */
1178         if (INTEL_INFO(dev)->gen == 6)
1179                 I915_WRITE(GFX_MODE,
1180                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1181
1182         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1183         if (IS_GEN7(dev))
1184                 I915_WRITE(GFX_MODE_GEN7,
1185                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1186                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1187
1188         if (IS_GEN6(dev)) {
1189                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1190                  * "If this bit is set, STCunit will have LRA as replacement
1191                  *  policy. [...] This bit must be reset.  LRA replacement
1192                  *  policy is not supported."
1193                  */
1194                 I915_WRITE(CACHE_MODE_0,
1195                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1196         }
1197
1198         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1199                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1200
1201         if (HAS_L3_DPF(dev))
1202                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1203
1204         return init_workarounds_ring(ring);
1205 }
1206
1207 static void render_ring_cleanup(struct intel_engine_cs *ring)
1208 {
1209         struct drm_device *dev = ring->dev;
1210         struct drm_i915_private *dev_priv = dev->dev_private;
1211
1212         if (dev_priv->semaphore_obj) {
1213                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1214                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1215                 dev_priv->semaphore_obj = NULL;
1216         }
1217
1218         intel_fini_pipe_control(ring);
1219 }
1220
1221 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1222                            unsigned int num_dwords)
1223 {
1224 #define MBOX_UPDATE_DWORDS 8
1225         struct intel_engine_cs *signaller = signaller_req->ring;
1226         struct drm_device *dev = signaller->dev;
1227         struct drm_i915_private *dev_priv = dev->dev_private;
1228         struct intel_engine_cs *waiter;
1229         int i, ret, num_rings;
1230
1231         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1232         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1233 #undef MBOX_UPDATE_DWORDS
1234
1235         ret = intel_ring_begin(signaller_req, num_dwords);
1236         if (ret)
1237                 return ret;
1238
1239         for_each_ring(waiter, dev_priv, i) {
1240                 u32 seqno;
1241                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1242                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1243                         continue;
1244
1245                 seqno = i915_gem_request_get_seqno(signaller_req);
1246                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1247                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1248                                            PIPE_CONTROL_QW_WRITE |
1249                                            PIPE_CONTROL_FLUSH_ENABLE);
1250                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1251                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1252                 intel_ring_emit(signaller, seqno);
1253                 intel_ring_emit(signaller, 0);
1254                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1255                                            MI_SEMAPHORE_TARGET(waiter->id));
1256                 intel_ring_emit(signaller, 0);
1257         }
1258
1259         return 0;
1260 }
1261
1262 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1263                            unsigned int num_dwords)
1264 {
1265 #define MBOX_UPDATE_DWORDS 6
1266         struct intel_engine_cs *signaller = signaller_req->ring;
1267         struct drm_device *dev = signaller->dev;
1268         struct drm_i915_private *dev_priv = dev->dev_private;
1269         struct intel_engine_cs *waiter;
1270         int i, ret, num_rings;
1271
1272         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1273         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1274 #undef MBOX_UPDATE_DWORDS
1275
1276         ret = intel_ring_begin(signaller_req, num_dwords);
1277         if (ret)
1278                 return ret;
1279
1280         for_each_ring(waiter, dev_priv, i) {
1281                 u32 seqno;
1282                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1283                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1284                         continue;
1285
1286                 seqno = i915_gem_request_get_seqno(signaller_req);
1287                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1288                                            MI_FLUSH_DW_OP_STOREDW);
1289                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1290                                            MI_FLUSH_DW_USE_GTT);
1291                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1292                 intel_ring_emit(signaller, seqno);
1293                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1294                                            MI_SEMAPHORE_TARGET(waiter->id));
1295                 intel_ring_emit(signaller, 0);
1296         }
1297
1298         return 0;
1299 }
1300
1301 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1302                        unsigned int num_dwords)
1303 {
1304         struct intel_engine_cs *signaller = signaller_req->ring;
1305         struct drm_device *dev = signaller->dev;
1306         struct drm_i915_private *dev_priv = dev->dev_private;
1307         struct intel_engine_cs *useless;
1308         int i, ret, num_rings;
1309
1310 #define MBOX_UPDATE_DWORDS 3
1311         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1312         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1313 #undef MBOX_UPDATE_DWORDS
1314
1315         ret = intel_ring_begin(signaller_req, num_dwords);
1316         if (ret)
1317                 return ret;
1318
1319         for_each_ring(useless, dev_priv, i) {
1320                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1321                 if (mbox_reg != GEN6_NOSYNC) {
1322                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1323                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1324                         intel_ring_emit(signaller, mbox_reg);
1325                         intel_ring_emit(signaller, seqno);
1326                 }
1327         }
1328
1329         /* If num_dwords was rounded, make sure the tail pointer is correct */
1330         if (num_rings % 2 == 0)
1331                 intel_ring_emit(signaller, MI_NOOP);
1332
1333         return 0;
1334 }
1335
1336 /**
1337  * gen6_add_request - Update the semaphore mailbox registers
1338  *
1339  * @request - request to write to the ring
1340  *
1341  * Update the mailbox registers in the *other* rings with the current seqno.
1342  * This acts like a signal in the canonical semaphore.
1343  */
1344 static int
1345 gen6_add_request(struct drm_i915_gem_request *req)
1346 {
1347         struct intel_engine_cs *ring = req->ring;
1348         int ret;
1349
1350         if (ring->semaphore.signal)
1351                 ret = ring->semaphore.signal(req, 4);
1352         else
1353                 ret = intel_ring_begin(req, 4);
1354
1355         if (ret)
1356                 return ret;
1357
1358         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1359         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1360         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1361         intel_ring_emit(ring, MI_USER_INTERRUPT);
1362         __intel_ring_advance(ring);
1363
1364         return 0;
1365 }
1366
1367 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1368                                               u32 seqno)
1369 {
1370         struct drm_i915_private *dev_priv = dev->dev_private;
1371         return dev_priv->last_seqno < seqno;
1372 }
1373
1374 /**
1375  * intel_ring_sync - sync the waiter to the signaller on seqno
1376  *
1377  * @waiter - ring that is waiting
1378  * @signaller - ring which has, or will signal
1379  * @seqno - seqno which the waiter will block on
1380  */
1381
1382 static int
1383 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1384                struct intel_engine_cs *signaller,
1385                u32 seqno)
1386 {
1387         struct intel_engine_cs *waiter = waiter_req->ring;
1388         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1389         int ret;
1390
1391         ret = intel_ring_begin(waiter_req, 4);
1392         if (ret)
1393                 return ret;
1394
1395         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1396                                 MI_SEMAPHORE_GLOBAL_GTT |
1397                                 MI_SEMAPHORE_POLL |
1398                                 MI_SEMAPHORE_SAD_GTE_SDD);
1399         intel_ring_emit(waiter, seqno);
1400         intel_ring_emit(waiter,
1401                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1402         intel_ring_emit(waiter,
1403                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1404         intel_ring_advance(waiter);
1405         return 0;
1406 }
1407
1408 static int
1409 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1410                struct intel_engine_cs *signaller,
1411                u32 seqno)
1412 {
1413         struct intel_engine_cs *waiter = waiter_req->ring;
1414         u32 dw1 = MI_SEMAPHORE_MBOX |
1415                   MI_SEMAPHORE_COMPARE |
1416                   MI_SEMAPHORE_REGISTER;
1417         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1418         int ret;
1419
1420         /* Throughout all of the GEM code, seqno passed implies our current
1421          * seqno is >= the last seqno executed. However for hardware the
1422          * comparison is strictly greater than.
1423          */
1424         seqno -= 1;
1425
1426         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1427
1428         ret = intel_ring_begin(waiter_req, 4);
1429         if (ret)
1430                 return ret;
1431
1432         /* If seqno wrap happened, omit the wait with no-ops */
1433         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1434                 intel_ring_emit(waiter, dw1 | wait_mbox);
1435                 intel_ring_emit(waiter, seqno);
1436                 intel_ring_emit(waiter, 0);
1437                 intel_ring_emit(waiter, MI_NOOP);
1438         } else {
1439                 intel_ring_emit(waiter, MI_NOOP);
1440                 intel_ring_emit(waiter, MI_NOOP);
1441                 intel_ring_emit(waiter, MI_NOOP);
1442                 intel_ring_emit(waiter, MI_NOOP);
1443         }
1444         intel_ring_advance(waiter);
1445
1446         return 0;
1447 }
1448
1449 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1450 do {                                                                    \
1451         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1452                  PIPE_CONTROL_DEPTH_STALL);                             \
1453         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1454         intel_ring_emit(ring__, 0);                                                     \
1455         intel_ring_emit(ring__, 0);                                                     \
1456 } while (0)
1457
1458 static int
1459 pc_render_add_request(struct drm_i915_gem_request *req)
1460 {
1461         struct intel_engine_cs *ring = req->ring;
1462         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1463         int ret;
1464
1465         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1466          * incoherent with writes to memory, i.e. completely fubar,
1467          * so we need to use PIPE_NOTIFY instead.
1468          *
1469          * However, we also need to workaround the qword write
1470          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1471          * memory before requesting an interrupt.
1472          */
1473         ret = intel_ring_begin(req, 32);
1474         if (ret)
1475                 return ret;
1476
1477         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1478                         PIPE_CONTROL_WRITE_FLUSH |
1479                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1480         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1481         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1482         intel_ring_emit(ring, 0);
1483         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1484         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1485         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1486         scratch_addr += 2 * CACHELINE_BYTES;
1487         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1488         scratch_addr += 2 * CACHELINE_BYTES;
1489         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1490         scratch_addr += 2 * CACHELINE_BYTES;
1491         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1492         scratch_addr += 2 * CACHELINE_BYTES;
1493         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1494
1495         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1496                         PIPE_CONTROL_WRITE_FLUSH |
1497                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1498                         PIPE_CONTROL_NOTIFY);
1499         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1500         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1501         intel_ring_emit(ring, 0);
1502         __intel_ring_advance(ring);
1503
1504         return 0;
1505 }
1506
1507 static u32
1508 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1509 {
1510         /* Workaround to force correct ordering between irq and seqno writes on
1511          * ivb (and maybe also on snb) by reading from a CS register (like
1512          * ACTHD) before reading the status page. */
1513         if (!lazy_coherency) {
1514                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1515                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1516         }
1517
1518         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1519 }
1520
1521 static u32
1522 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1523 {
1524         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1525 }
1526
1527 static void
1528 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1529 {
1530         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1531 }
1532
1533 static u32
1534 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1535 {
1536         return ring->scratch.cpu_page[0];
1537 }
1538
1539 static void
1540 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1541 {
1542         ring->scratch.cpu_page[0] = seqno;
1543 }
1544
1545 static bool
1546 gen5_ring_get_irq(struct intel_engine_cs *ring)
1547 {
1548         struct drm_device *dev = ring->dev;
1549         struct drm_i915_private *dev_priv = dev->dev_private;
1550         unsigned long flags;
1551
1552         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1553                 return false;
1554
1555         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1556         if (ring->irq_refcount++ == 0)
1557                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1558         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1559
1560         return true;
1561 }
1562
1563 static void
1564 gen5_ring_put_irq(struct intel_engine_cs *ring)
1565 {
1566         struct drm_device *dev = ring->dev;
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         unsigned long flags;
1569
1570         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1571         if (--ring->irq_refcount == 0)
1572                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1573         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1574 }
1575
1576 static bool
1577 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1578 {
1579         struct drm_device *dev = ring->dev;
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         unsigned long flags;
1582
1583         if (!intel_irqs_enabled(dev_priv))
1584                 return false;
1585
1586         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1587         if (ring->irq_refcount++ == 0) {
1588                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1589                 I915_WRITE(IMR, dev_priv->irq_mask);
1590                 POSTING_READ(IMR);
1591         }
1592         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1593
1594         return true;
1595 }
1596
1597 static void
1598 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1599 {
1600         struct drm_device *dev = ring->dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         unsigned long flags;
1603
1604         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1605         if (--ring->irq_refcount == 0) {
1606                 dev_priv->irq_mask |= ring->irq_enable_mask;
1607                 I915_WRITE(IMR, dev_priv->irq_mask);
1608                 POSTING_READ(IMR);
1609         }
1610         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1611 }
1612
1613 static bool
1614 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1615 {
1616         struct drm_device *dev = ring->dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618         unsigned long flags;
1619
1620         if (!intel_irqs_enabled(dev_priv))
1621                 return false;
1622
1623         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1624         if (ring->irq_refcount++ == 0) {
1625                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1626                 I915_WRITE16(IMR, dev_priv->irq_mask);
1627                 POSTING_READ16(IMR);
1628         }
1629         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1630
1631         return true;
1632 }
1633
1634 static void
1635 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1636 {
1637         struct drm_device *dev = ring->dev;
1638         struct drm_i915_private *dev_priv = dev->dev_private;
1639         unsigned long flags;
1640
1641         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1642         if (--ring->irq_refcount == 0) {
1643                 dev_priv->irq_mask |= ring->irq_enable_mask;
1644                 I915_WRITE16(IMR, dev_priv->irq_mask);
1645                 POSTING_READ16(IMR);
1646         }
1647         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1648 }
1649
1650 static int
1651 bsd_ring_flush(struct drm_i915_gem_request *req,
1652                u32     invalidate_domains,
1653                u32     flush_domains)
1654 {
1655         struct intel_engine_cs *ring = req->ring;
1656         int ret;
1657
1658         ret = intel_ring_begin(req, 2);
1659         if (ret)
1660                 return ret;
1661
1662         intel_ring_emit(ring, MI_FLUSH);
1663         intel_ring_emit(ring, MI_NOOP);
1664         intel_ring_advance(ring);
1665         return 0;
1666 }
1667
1668 static int
1669 i9xx_add_request(struct drm_i915_gem_request *req)
1670 {
1671         struct intel_engine_cs *ring = req->ring;
1672         int ret;
1673
1674         ret = intel_ring_begin(req, 4);
1675         if (ret)
1676                 return ret;
1677
1678         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1679         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1680         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1681         intel_ring_emit(ring, MI_USER_INTERRUPT);
1682         __intel_ring_advance(ring);
1683
1684         return 0;
1685 }
1686
1687 static bool
1688 gen6_ring_get_irq(struct intel_engine_cs *ring)
1689 {
1690         struct drm_device *dev = ring->dev;
1691         struct drm_i915_private *dev_priv = dev->dev_private;
1692         unsigned long flags;
1693
1694         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1695                 return false;
1696
1697         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1698         if (ring->irq_refcount++ == 0) {
1699                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1700                         I915_WRITE_IMR(ring,
1701                                        ~(ring->irq_enable_mask |
1702                                          GT_PARITY_ERROR(dev)));
1703                 else
1704                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1705                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1706         }
1707         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1708
1709         return true;
1710 }
1711
1712 static void
1713 gen6_ring_put_irq(struct intel_engine_cs *ring)
1714 {
1715         struct drm_device *dev = ring->dev;
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717         unsigned long flags;
1718
1719         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1720         if (--ring->irq_refcount == 0) {
1721                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1722                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1723                 else
1724                         I915_WRITE_IMR(ring, ~0);
1725                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1726         }
1727         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1728 }
1729
1730 static bool
1731 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1732 {
1733         struct drm_device *dev = ring->dev;
1734         struct drm_i915_private *dev_priv = dev->dev_private;
1735         unsigned long flags;
1736
1737         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1738                 return false;
1739
1740         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1741         if (ring->irq_refcount++ == 0) {
1742                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1743                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1744         }
1745         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1746
1747         return true;
1748 }
1749
1750 static void
1751 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1752 {
1753         struct drm_device *dev = ring->dev;
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         unsigned long flags;
1756
1757         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1758         if (--ring->irq_refcount == 0) {
1759                 I915_WRITE_IMR(ring, ~0);
1760                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1761         }
1762         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1763 }
1764
1765 static bool
1766 gen8_ring_get_irq(struct intel_engine_cs *ring)
1767 {
1768         struct drm_device *dev = ring->dev;
1769         struct drm_i915_private *dev_priv = dev->dev_private;
1770         unsigned long flags;
1771
1772         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1773                 return false;
1774
1775         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1776         if (ring->irq_refcount++ == 0) {
1777                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1778                         I915_WRITE_IMR(ring,
1779                                        ~(ring->irq_enable_mask |
1780                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1781                 } else {
1782                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1783                 }
1784                 POSTING_READ(RING_IMR(ring->mmio_base));
1785         }
1786         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1787
1788         return true;
1789 }
1790
1791 static void
1792 gen8_ring_put_irq(struct intel_engine_cs *ring)
1793 {
1794         struct drm_device *dev = ring->dev;
1795         struct drm_i915_private *dev_priv = dev->dev_private;
1796         unsigned long flags;
1797
1798         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1799         if (--ring->irq_refcount == 0) {
1800                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1801                         I915_WRITE_IMR(ring,
1802                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1803                 } else {
1804                         I915_WRITE_IMR(ring, ~0);
1805                 }
1806                 POSTING_READ(RING_IMR(ring->mmio_base));
1807         }
1808         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1809 }
1810
1811 static int
1812 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1813                          u64 offset, u32 length,
1814                          unsigned dispatch_flags)
1815 {
1816         struct intel_engine_cs *ring = req->ring;
1817         int ret;
1818
1819         ret = intel_ring_begin(req, 2);
1820         if (ret)
1821                 return ret;
1822
1823         intel_ring_emit(ring,
1824                         MI_BATCH_BUFFER_START |
1825                         MI_BATCH_GTT |
1826                         (dispatch_flags & I915_DISPATCH_SECURE ?
1827                          0 : MI_BATCH_NON_SECURE_I965));
1828         intel_ring_emit(ring, offset);
1829         intel_ring_advance(ring);
1830
1831         return 0;
1832 }
1833
1834 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1835 #define I830_BATCH_LIMIT (256*1024)
1836 #define I830_TLB_ENTRIES (2)
1837 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1838 static int
1839 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1840                          u64 offset, u32 len,
1841                          unsigned dispatch_flags)
1842 {
1843         struct intel_engine_cs *ring = req->ring;
1844         u32 cs_offset = ring->scratch.gtt_offset;
1845         int ret;
1846
1847         ret = intel_ring_begin(req, 6);
1848         if (ret)
1849                 return ret;
1850
1851         /* Evict the invalid PTE TLBs */
1852         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1853         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1854         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1855         intel_ring_emit(ring, cs_offset);
1856         intel_ring_emit(ring, 0xdeadbeef);
1857         intel_ring_emit(ring, MI_NOOP);
1858         intel_ring_advance(ring);
1859
1860         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1861                 if (len > I830_BATCH_LIMIT)
1862                         return -ENOSPC;
1863
1864                 ret = intel_ring_begin(req, 6 + 2);
1865                 if (ret)
1866                         return ret;
1867
1868                 /* Blit the batch (which has now all relocs applied) to the
1869                  * stable batch scratch bo area (so that the CS never
1870                  * stumbles over its tlb invalidation bug) ...
1871                  */
1872                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1873                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1874                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1875                 intel_ring_emit(ring, cs_offset);
1876                 intel_ring_emit(ring, 4096);
1877                 intel_ring_emit(ring, offset);
1878
1879                 intel_ring_emit(ring, MI_FLUSH);
1880                 intel_ring_emit(ring, MI_NOOP);
1881                 intel_ring_advance(ring);
1882
1883                 /* ... and execute it. */
1884                 offset = cs_offset;
1885         }
1886
1887         ret = intel_ring_begin(req, 4);
1888         if (ret)
1889                 return ret;
1890
1891         intel_ring_emit(ring, MI_BATCH_BUFFER);
1892         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1893                                         0 : MI_BATCH_NON_SECURE));
1894         intel_ring_emit(ring, offset + len - 8);
1895         intel_ring_emit(ring, MI_NOOP);
1896         intel_ring_advance(ring);
1897
1898         return 0;
1899 }
1900
1901 static int
1902 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1903                          u64 offset, u32 len,
1904                          unsigned dispatch_flags)
1905 {
1906         struct intel_engine_cs *ring = req->ring;
1907         int ret;
1908
1909         ret = intel_ring_begin(req, 2);
1910         if (ret)
1911                 return ret;
1912
1913         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1914         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1915                                         0 : MI_BATCH_NON_SECURE));
1916         intel_ring_advance(ring);
1917
1918         return 0;
1919 }
1920
1921 static void cleanup_status_page(struct intel_engine_cs *ring)
1922 {
1923         struct drm_i915_gem_object *obj;
1924
1925         obj = ring->status_page.obj;
1926         if (obj == NULL)
1927                 return;
1928
1929         kunmap(sg_page(obj->pages->sgl));
1930         i915_gem_object_ggtt_unpin(obj);
1931         drm_gem_object_unreference(&obj->base);
1932         ring->status_page.obj = NULL;
1933 }
1934
1935 static int init_status_page(struct intel_engine_cs *ring)
1936 {
1937         struct drm_i915_gem_object *obj;
1938
1939         if ((obj = ring->status_page.obj) == NULL) {
1940                 unsigned flags;
1941                 int ret;
1942
1943                 obj = i915_gem_alloc_object(ring->dev, 4096);
1944                 if (obj == NULL) {
1945                         DRM_ERROR("Failed to allocate status page\n");
1946                         return -ENOMEM;
1947                 }
1948
1949                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1950                 if (ret)
1951                         goto err_unref;
1952
1953                 flags = 0;
1954                 if (!HAS_LLC(ring->dev))
1955                         /* On g33, we cannot place HWS above 256MiB, so
1956                          * restrict its pinning to the low mappable arena.
1957                          * Though this restriction is not documented for
1958                          * gen4, gen5, or byt, they also behave similarly
1959                          * and hang if the HWS is placed at the top of the
1960                          * GTT. To generalise, it appears that all !llc
1961                          * platforms have issues with us placing the HWS
1962                          * above the mappable region (even though we never
1963                          * actualy map it).
1964                          */
1965                         flags |= PIN_MAPPABLE;
1966                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1967                 if (ret) {
1968 err_unref:
1969                         drm_gem_object_unreference(&obj->base);
1970                         return ret;
1971                 }
1972
1973                 ring->status_page.obj = obj;
1974         }
1975
1976         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1977         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1978         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1979
1980         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1981                         ring->name, ring->status_page.gfx_addr);
1982
1983         return 0;
1984 }
1985
1986 static int init_phys_status_page(struct intel_engine_cs *ring)
1987 {
1988         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1989
1990         if (!dev_priv->status_page_dmah) {
1991                 dev_priv->status_page_dmah =
1992                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1993                 if (!dev_priv->status_page_dmah)
1994                         return -ENOMEM;
1995         }
1996
1997         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1998         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1999
2000         return 0;
2001 }
2002
2003 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2004 {
2005         iounmap(ringbuf->virtual_start);
2006         ringbuf->virtual_start = NULL;
2007         i915_gem_object_ggtt_unpin(ringbuf->obj);
2008 }
2009
2010 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2011                                      struct intel_ringbuffer *ringbuf)
2012 {
2013         struct drm_i915_private *dev_priv = to_i915(dev);
2014         struct drm_i915_gem_object *obj = ringbuf->obj;
2015         int ret;
2016
2017         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2018         if (ret)
2019                 return ret;
2020
2021         ret = i915_gem_object_set_to_gtt_domain(obj, true);
2022         if (ret) {
2023                 i915_gem_object_ggtt_unpin(obj);
2024                 return ret;
2025         }
2026
2027         ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2028                         i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2029         if (ringbuf->virtual_start == NULL) {
2030                 i915_gem_object_ggtt_unpin(obj);
2031                 return -EINVAL;
2032         }
2033
2034         return 0;
2035 }
2036
2037 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2038 {
2039         drm_gem_object_unreference(&ringbuf->obj->base);
2040         ringbuf->obj = NULL;
2041 }
2042
2043 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2044                                       struct intel_ringbuffer *ringbuf)
2045 {
2046         struct drm_i915_gem_object *obj;
2047
2048         obj = NULL;
2049         if (!HAS_LLC(dev))
2050                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2051         if (obj == NULL)
2052                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2053         if (obj == NULL)
2054                 return -ENOMEM;
2055
2056         /* mark ring buffers as read-only from GPU side by default */
2057         obj->gt_ro = 1;
2058
2059         ringbuf->obj = obj;
2060
2061         return 0;
2062 }
2063
2064 struct intel_ringbuffer *
2065 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2066 {
2067         struct intel_ringbuffer *ring;
2068         int ret;
2069
2070         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2071         if (ring == NULL)
2072                 return ERR_PTR(-ENOMEM);
2073
2074         ring->ring = engine;
2075
2076         ring->size = size;
2077         /* Workaround an erratum on the i830 which causes a hang if
2078          * the TAIL pointer points to within the last 2 cachelines
2079          * of the buffer.
2080          */
2081         ring->effective_size = size;
2082         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2083                 ring->effective_size -= 2 * CACHELINE_BYTES;
2084
2085         ring->last_retired_head = -1;
2086         intel_ring_update_space(ring);
2087
2088         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2089         if (ret) {
2090                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2091                           engine->name, ret);
2092                 kfree(ring);
2093                 return ERR_PTR(ret);
2094         }
2095
2096         return ring;
2097 }
2098
2099 void
2100 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2101 {
2102         intel_destroy_ringbuffer_obj(ring);
2103         kfree(ring);
2104 }
2105
2106 static int intel_init_ring_buffer(struct drm_device *dev,
2107                                   struct intel_engine_cs *ring)
2108 {
2109         struct intel_ringbuffer *ringbuf;
2110         int ret;
2111
2112         WARN_ON(ring->buffer);
2113
2114         ring->dev = dev;
2115         INIT_LIST_HEAD(&ring->active_list);
2116         INIT_LIST_HEAD(&ring->request_list);
2117         INIT_LIST_HEAD(&ring->execlist_queue);
2118         i915_gem_batch_pool_init(dev, &ring->batch_pool);
2119         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2120
2121         init_waitqueue_head(&ring->irq_queue);
2122
2123         ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2124         if (IS_ERR(ringbuf))
2125                 return PTR_ERR(ringbuf);
2126         ring->buffer = ringbuf;
2127
2128         if (I915_NEED_GFX_HWS(dev)) {
2129                 ret = init_status_page(ring);
2130                 if (ret)
2131                         goto error;
2132         } else {
2133                 BUG_ON(ring->id != RCS);
2134                 ret = init_phys_status_page(ring);
2135                 if (ret)
2136                         goto error;
2137         }
2138
2139         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2140         if (ret) {
2141                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2142                                 ring->name, ret);
2143                 intel_destroy_ringbuffer_obj(ringbuf);
2144                 goto error;
2145         }
2146
2147         ret = i915_cmd_parser_init_ring(ring);
2148         if (ret)
2149                 goto error;
2150
2151         return 0;
2152
2153 error:
2154         intel_ringbuffer_free(ringbuf);
2155         ring->buffer = NULL;
2156         return ret;
2157 }
2158
2159 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2160 {
2161         struct drm_i915_private *dev_priv;
2162
2163         if (!intel_ring_initialized(ring))
2164                 return;
2165
2166         dev_priv = to_i915(ring->dev);
2167
2168         intel_stop_ring_buffer(ring);
2169         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2170
2171         intel_unpin_ringbuffer_obj(ring->buffer);
2172         intel_ringbuffer_free(ring->buffer);
2173         ring->buffer = NULL;
2174
2175         if (ring->cleanup)
2176                 ring->cleanup(ring);
2177
2178         cleanup_status_page(ring);
2179
2180         i915_cmd_parser_fini_ring(ring);
2181         i915_gem_batch_pool_fini(&ring->batch_pool);
2182 }
2183
2184 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2185 {
2186         struct intel_ringbuffer *ringbuf = ring->buffer;
2187         struct drm_i915_gem_request *request;
2188         unsigned space;
2189         int ret;
2190
2191         if (intel_ring_space(ringbuf) >= n)
2192                 return 0;
2193
2194         /* The whole point of reserving space is to not wait! */
2195         WARN_ON(ringbuf->reserved_in_use);
2196
2197         list_for_each_entry(request, &ring->request_list, list) {
2198                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2199                                            ringbuf->size);
2200                 if (space >= n)
2201                         break;
2202         }
2203
2204         if (WARN_ON(&request->list == &ring->request_list))
2205                 return -ENOSPC;
2206
2207         ret = i915_wait_request(request);
2208         if (ret)
2209                 return ret;
2210
2211         ringbuf->space = space;
2212         return 0;
2213 }
2214
2215 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2216 {
2217         uint32_t __iomem *virt;
2218         int rem = ringbuf->size - ringbuf->tail;
2219
2220         virt = ringbuf->virtual_start + ringbuf->tail;
2221         rem /= 4;
2222         while (rem--)
2223                 iowrite32(MI_NOOP, virt++);
2224
2225         ringbuf->tail = 0;
2226         intel_ring_update_space(ringbuf);
2227 }
2228
2229 int intel_ring_idle(struct intel_engine_cs *ring)
2230 {
2231         struct drm_i915_gem_request *req;
2232
2233         /* Wait upon the last request to be completed */
2234         if (list_empty(&ring->request_list))
2235                 return 0;
2236
2237         req = list_entry(ring->request_list.prev,
2238                         struct drm_i915_gem_request,
2239                         list);
2240
2241         /* Make sure we do not trigger any retires */
2242         return __i915_wait_request(req,
2243                                    atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2244                                    to_i915(ring->dev)->mm.interruptible,
2245                                    NULL, NULL);
2246 }
2247
2248 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2249 {
2250         request->ringbuf = request->ring->buffer;
2251         return 0;
2252 }
2253
2254 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2255 {
2256         /*
2257          * The first call merely notes the reserve request and is common for
2258          * all back ends. The subsequent localised _begin() call actually
2259          * ensures that the reservation is available. Without the begin, if
2260          * the request creator immediately submitted the request without
2261          * adding any commands to it then there might not actually be
2262          * sufficient room for the submission commands.
2263          */
2264         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2265
2266         return intel_ring_begin(request, 0);
2267 }
2268
2269 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2270 {
2271         WARN_ON(ringbuf->reserved_size);
2272         WARN_ON(ringbuf->reserved_in_use);
2273
2274         ringbuf->reserved_size = size;
2275 }
2276
2277 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2278 {
2279         WARN_ON(ringbuf->reserved_in_use);
2280
2281         ringbuf->reserved_size   = 0;
2282         ringbuf->reserved_in_use = false;
2283 }
2284
2285 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2286 {
2287         WARN_ON(ringbuf->reserved_in_use);
2288
2289         ringbuf->reserved_in_use = true;
2290         ringbuf->reserved_tail   = ringbuf->tail;
2291 }
2292
2293 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2294 {
2295         WARN_ON(!ringbuf->reserved_in_use);
2296         if (ringbuf->tail > ringbuf->reserved_tail) {
2297                 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2298                      "request reserved size too small: %d vs %d!\n",
2299                      ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2300         } else {
2301                 /*
2302                  * The ring was wrapped while the reserved space was in use.
2303                  * That means that some unknown amount of the ring tail was
2304                  * no-op filled and skipped. Thus simply adding the ring size
2305                  * to the tail and doing the above space check will not work.
2306                  * Rather than attempt to track how much tail was skipped,
2307                  * it is much simpler to say that also skipping the sanity
2308                  * check every once in a while is not a big issue.
2309                  */
2310         }
2311
2312         ringbuf->reserved_size   = 0;
2313         ringbuf->reserved_in_use = false;
2314 }
2315
2316 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2317 {
2318         struct intel_ringbuffer *ringbuf = ring->buffer;
2319         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2320         int remain_actual = ringbuf->size - ringbuf->tail;
2321         int ret, total_bytes, wait_bytes = 0;
2322         bool need_wrap = false;
2323
2324         if (ringbuf->reserved_in_use)
2325                 total_bytes = bytes;
2326         else
2327                 total_bytes = bytes + ringbuf->reserved_size;
2328
2329         if (unlikely(bytes > remain_usable)) {
2330                 /*
2331                  * Not enough space for the basic request. So need to flush
2332                  * out the remainder and then wait for base + reserved.
2333                  */
2334                 wait_bytes = remain_actual + total_bytes;
2335                 need_wrap = true;
2336         } else {
2337                 if (unlikely(total_bytes > remain_usable)) {
2338                         /*
2339                          * The base request will fit but the reserved space
2340                          * falls off the end. So only need to to wait for the
2341                          * reserved size after flushing out the remainder.
2342                          */
2343                         wait_bytes = remain_actual + ringbuf->reserved_size;
2344                         need_wrap = true;
2345                 } else if (total_bytes > ringbuf->space) {
2346                         /* No wrapping required, just waiting. */
2347                         wait_bytes = total_bytes;
2348                 }
2349         }
2350
2351         if (wait_bytes) {
2352                 ret = ring_wait_for_space(ring, wait_bytes);
2353                 if (unlikely(ret))
2354                         return ret;
2355
2356                 if (need_wrap)
2357                         __wrap_ring_buffer(ringbuf);
2358         }
2359
2360         return 0;
2361 }
2362
2363 int intel_ring_begin(struct drm_i915_gem_request *req,
2364                      int num_dwords)
2365 {
2366         struct intel_engine_cs *ring;
2367         struct drm_i915_private *dev_priv;
2368         int ret;
2369
2370         WARN_ON(req == NULL);
2371         ring = req->ring;
2372         dev_priv = ring->dev->dev_private;
2373
2374         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2375                                    dev_priv->mm.interruptible);
2376         if (ret)
2377                 return ret;
2378
2379         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2380         if (ret)
2381                 return ret;
2382
2383         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2384         return 0;
2385 }
2386
2387 /* Align the ring tail to a cacheline boundary */
2388 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2389 {
2390         struct intel_engine_cs *ring = req->ring;
2391         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2392         int ret;
2393
2394         if (num_dwords == 0)
2395                 return 0;
2396
2397         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2398         ret = intel_ring_begin(req, num_dwords);
2399         if (ret)
2400                 return ret;
2401
2402         while (num_dwords--)
2403                 intel_ring_emit(ring, MI_NOOP);
2404
2405         intel_ring_advance(ring);
2406
2407         return 0;
2408 }
2409
2410 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2411 {
2412         struct drm_device *dev = ring->dev;
2413         struct drm_i915_private *dev_priv = dev->dev_private;
2414
2415         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2416                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2417                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2418                 if (HAS_VEBOX(dev))
2419                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2420         }
2421
2422         ring->set_seqno(ring, seqno);
2423         ring->hangcheck.seqno = seqno;
2424 }
2425
2426 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2427                                      u32 value)
2428 {
2429         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2430
2431        /* Every tail move must follow the sequence below */
2432
2433         /* Disable notification that the ring is IDLE. The GT
2434          * will then assume that it is busy and bring it out of rc6.
2435          */
2436         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2437                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2438
2439         /* Clear the context id. Here be magic! */
2440         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2441
2442         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2443         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2444                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2445                      50))
2446                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2447
2448         /* Now that the ring is fully powered up, update the tail */
2449         I915_WRITE_TAIL(ring, value);
2450         POSTING_READ(RING_TAIL(ring->mmio_base));
2451
2452         /* Let the ring send IDLE messages to the GT again,
2453          * and so let it sleep to conserve power when idle.
2454          */
2455         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2456                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2457 }
2458
2459 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2460                                u32 invalidate, u32 flush)
2461 {
2462         struct intel_engine_cs *ring = req->ring;
2463         uint32_t cmd;
2464         int ret;
2465
2466         ret = intel_ring_begin(req, 4);
2467         if (ret)
2468                 return ret;
2469
2470         cmd = MI_FLUSH_DW;
2471         if (INTEL_INFO(ring->dev)->gen >= 8)
2472                 cmd += 1;
2473
2474         /* We always require a command barrier so that subsequent
2475          * commands, such as breadcrumb interrupts, are strictly ordered
2476          * wrt the contents of the write cache being flushed to memory
2477          * (and thus being coherent from the CPU).
2478          */
2479         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2480
2481         /*
2482          * Bspec vol 1c.5 - video engine command streamer:
2483          * "If ENABLED, all TLBs will be invalidated once the flush
2484          * operation is complete. This bit is only valid when the
2485          * Post-Sync Operation field is a value of 1h or 3h."
2486          */
2487         if (invalidate & I915_GEM_GPU_DOMAINS)
2488                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2489
2490         intel_ring_emit(ring, cmd);
2491         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2492         if (INTEL_INFO(ring->dev)->gen >= 8) {
2493                 intel_ring_emit(ring, 0); /* upper addr */
2494                 intel_ring_emit(ring, 0); /* value */
2495         } else  {
2496                 intel_ring_emit(ring, 0);
2497                 intel_ring_emit(ring, MI_NOOP);
2498         }
2499         intel_ring_advance(ring);
2500         return 0;
2501 }
2502
2503 static int
2504 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2505                               u64 offset, u32 len,
2506                               unsigned dispatch_flags)
2507 {
2508         struct intel_engine_cs *ring = req->ring;
2509         bool ppgtt = USES_PPGTT(ring->dev) &&
2510                         !(dispatch_flags & I915_DISPATCH_SECURE);
2511         int ret;
2512
2513         ret = intel_ring_begin(req, 4);
2514         if (ret)
2515                 return ret;
2516
2517         /* FIXME(BDW): Address space and security selectors. */
2518         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2519                         (dispatch_flags & I915_DISPATCH_RS ?
2520                          MI_BATCH_RESOURCE_STREAMER : 0));
2521         intel_ring_emit(ring, lower_32_bits(offset));
2522         intel_ring_emit(ring, upper_32_bits(offset));
2523         intel_ring_emit(ring, MI_NOOP);
2524         intel_ring_advance(ring);
2525
2526         return 0;
2527 }
2528
2529 static int
2530 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2531                              u64 offset, u32 len,
2532                              unsigned dispatch_flags)
2533 {
2534         struct intel_engine_cs *ring = req->ring;
2535         int ret;
2536
2537         ret = intel_ring_begin(req, 2);
2538         if (ret)
2539                 return ret;
2540
2541         intel_ring_emit(ring,
2542                         MI_BATCH_BUFFER_START |
2543                         (dispatch_flags & I915_DISPATCH_SECURE ?
2544                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2545                         (dispatch_flags & I915_DISPATCH_RS ?
2546                          MI_BATCH_RESOURCE_STREAMER : 0));
2547         /* bit0-7 is the length on GEN6+ */
2548         intel_ring_emit(ring, offset);
2549         intel_ring_advance(ring);
2550
2551         return 0;
2552 }
2553
2554 static int
2555 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2556                               u64 offset, u32 len,
2557                               unsigned dispatch_flags)
2558 {
2559         struct intel_engine_cs *ring = req->ring;
2560         int ret;
2561
2562         ret = intel_ring_begin(req, 2);
2563         if (ret)
2564                 return ret;
2565
2566         intel_ring_emit(ring,
2567                         MI_BATCH_BUFFER_START |
2568                         (dispatch_flags & I915_DISPATCH_SECURE ?
2569                          0 : MI_BATCH_NON_SECURE_I965));
2570         /* bit0-7 is the length on GEN6+ */
2571         intel_ring_emit(ring, offset);
2572         intel_ring_advance(ring);
2573
2574         return 0;
2575 }
2576
2577 /* Blitter support (SandyBridge+) */
2578
2579 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2580                            u32 invalidate, u32 flush)
2581 {
2582         struct intel_engine_cs *ring = req->ring;
2583         struct drm_device *dev = ring->dev;
2584         uint32_t cmd;
2585         int ret;
2586
2587         ret = intel_ring_begin(req, 4);
2588         if (ret)
2589                 return ret;
2590
2591         cmd = MI_FLUSH_DW;
2592         if (INTEL_INFO(dev)->gen >= 8)
2593                 cmd += 1;
2594
2595         /* We always require a command barrier so that subsequent
2596          * commands, such as breadcrumb interrupts, are strictly ordered
2597          * wrt the contents of the write cache being flushed to memory
2598          * (and thus being coherent from the CPU).
2599          */
2600         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2601
2602         /*
2603          * Bspec vol 1c.3 - blitter engine command streamer:
2604          * "If ENABLED, all TLBs will be invalidated once the flush
2605          * operation is complete. This bit is only valid when the
2606          * Post-Sync Operation field is a value of 1h or 3h."
2607          */
2608         if (invalidate & I915_GEM_DOMAIN_RENDER)
2609                 cmd |= MI_INVALIDATE_TLB;
2610         intel_ring_emit(ring, cmd);
2611         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2612         if (INTEL_INFO(dev)->gen >= 8) {
2613                 intel_ring_emit(ring, 0); /* upper addr */
2614                 intel_ring_emit(ring, 0); /* value */
2615         } else  {
2616                 intel_ring_emit(ring, 0);
2617                 intel_ring_emit(ring, MI_NOOP);
2618         }
2619         intel_ring_advance(ring);
2620
2621         return 0;
2622 }
2623
2624 int intel_init_render_ring_buffer(struct drm_device *dev)
2625 {
2626         struct drm_i915_private *dev_priv = dev->dev_private;
2627         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2628         struct drm_i915_gem_object *obj;
2629         int ret;
2630
2631         ring->name = "render ring";
2632         ring->id = RCS;
2633         ring->mmio_base = RENDER_RING_BASE;
2634
2635         if (INTEL_INFO(dev)->gen >= 8) {
2636                 if (i915_semaphore_is_enabled(dev)) {
2637                         obj = i915_gem_alloc_object(dev, 4096);
2638                         if (obj == NULL) {
2639                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2640                                 i915.semaphores = 0;
2641                         } else {
2642                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2643                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2644                                 if (ret != 0) {
2645                                         drm_gem_object_unreference(&obj->base);
2646                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2647                                         i915.semaphores = 0;
2648                                 } else
2649                                         dev_priv->semaphore_obj = obj;
2650                         }
2651                 }
2652
2653                 ring->init_context = intel_rcs_ctx_init;
2654                 ring->add_request = gen6_add_request;
2655                 ring->flush = gen8_render_ring_flush;
2656                 ring->irq_get = gen8_ring_get_irq;
2657                 ring->irq_put = gen8_ring_put_irq;
2658                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2659                 ring->get_seqno = gen6_ring_get_seqno;
2660                 ring->set_seqno = ring_set_seqno;
2661                 if (i915_semaphore_is_enabled(dev)) {
2662                         WARN_ON(!dev_priv->semaphore_obj);
2663                         ring->semaphore.sync_to = gen8_ring_sync;
2664                         ring->semaphore.signal = gen8_rcs_signal;
2665                         GEN8_RING_SEMAPHORE_INIT;
2666                 }
2667         } else if (INTEL_INFO(dev)->gen >= 6) {
2668                 ring->init_context = intel_rcs_ctx_init;
2669                 ring->add_request = gen6_add_request;
2670                 ring->flush = gen7_render_ring_flush;
2671                 if (INTEL_INFO(dev)->gen == 6)
2672                         ring->flush = gen6_render_ring_flush;
2673                 ring->irq_get = gen6_ring_get_irq;
2674                 ring->irq_put = gen6_ring_put_irq;
2675                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2676                 ring->get_seqno = gen6_ring_get_seqno;
2677                 ring->set_seqno = ring_set_seqno;
2678                 if (i915_semaphore_is_enabled(dev)) {
2679                         ring->semaphore.sync_to = gen6_ring_sync;
2680                         ring->semaphore.signal = gen6_signal;
2681                         /*
2682                          * The current semaphore is only applied on pre-gen8
2683                          * platform.  And there is no VCS2 ring on the pre-gen8
2684                          * platform. So the semaphore between RCS and VCS2 is
2685                          * initialized as INVALID.  Gen8 will initialize the
2686                          * sema between VCS2 and RCS later.
2687                          */
2688                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2689                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2690                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2691                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2692                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2693                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2694                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2695                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2696                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2697                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2698                 }
2699         } else if (IS_GEN5(dev)) {
2700                 ring->add_request = pc_render_add_request;
2701                 ring->flush = gen4_render_ring_flush;
2702                 ring->get_seqno = pc_render_get_seqno;
2703                 ring->set_seqno = pc_render_set_seqno;
2704                 ring->irq_get = gen5_ring_get_irq;
2705                 ring->irq_put = gen5_ring_put_irq;
2706                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2707                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2708         } else {
2709                 ring->add_request = i9xx_add_request;
2710                 if (INTEL_INFO(dev)->gen < 4)
2711                         ring->flush = gen2_render_ring_flush;
2712                 else
2713                         ring->flush = gen4_render_ring_flush;
2714                 ring->get_seqno = ring_get_seqno;
2715                 ring->set_seqno = ring_set_seqno;
2716                 if (IS_GEN2(dev)) {
2717                         ring->irq_get = i8xx_ring_get_irq;
2718                         ring->irq_put = i8xx_ring_put_irq;
2719                 } else {
2720                         ring->irq_get = i9xx_ring_get_irq;
2721                         ring->irq_put = i9xx_ring_put_irq;
2722                 }
2723                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2724         }
2725         ring->write_tail = ring_write_tail;
2726
2727         if (IS_HASWELL(dev))
2728                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2729         else if (IS_GEN8(dev))
2730                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2731         else if (INTEL_INFO(dev)->gen >= 6)
2732                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2733         else if (INTEL_INFO(dev)->gen >= 4)
2734                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2735         else if (IS_I830(dev) || IS_845G(dev))
2736                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2737         else
2738                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2739         ring->init_hw = init_render_ring;
2740         ring->cleanup = render_ring_cleanup;
2741
2742         /* Workaround batchbuffer to combat CS tlb bug. */
2743         if (HAS_BROKEN_CS_TLB(dev)) {
2744                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2745                 if (obj == NULL) {
2746                         DRM_ERROR("Failed to allocate batch bo\n");
2747                         return -ENOMEM;
2748                 }
2749
2750                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2751                 if (ret != 0) {
2752                         drm_gem_object_unreference(&obj->base);
2753                         DRM_ERROR("Failed to ping batch bo\n");
2754                         return ret;
2755                 }
2756
2757                 ring->scratch.obj = obj;
2758                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2759         }
2760
2761         ret = intel_init_ring_buffer(dev, ring);
2762         if (ret)
2763                 return ret;
2764
2765         if (INTEL_INFO(dev)->gen >= 5) {
2766                 ret = intel_init_pipe_control(ring);
2767                 if (ret)
2768                         return ret;
2769         }
2770
2771         return 0;
2772 }
2773
2774 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2775 {
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2778
2779         ring->name = "bsd ring";
2780         ring->id = VCS;
2781
2782         ring->write_tail = ring_write_tail;
2783         if (INTEL_INFO(dev)->gen >= 6) {
2784                 ring->mmio_base = GEN6_BSD_RING_BASE;
2785                 /* gen6 bsd needs a special wa for tail updates */
2786                 if (IS_GEN6(dev))
2787                         ring->write_tail = gen6_bsd_ring_write_tail;
2788                 ring->flush = gen6_bsd_ring_flush;
2789                 ring->add_request = gen6_add_request;
2790                 ring->get_seqno = gen6_ring_get_seqno;
2791                 ring->set_seqno = ring_set_seqno;
2792                 if (INTEL_INFO(dev)->gen >= 8) {
2793                         ring->irq_enable_mask =
2794                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2795                         ring->irq_get = gen8_ring_get_irq;
2796                         ring->irq_put = gen8_ring_put_irq;
2797                         ring->dispatch_execbuffer =
2798                                 gen8_ring_dispatch_execbuffer;
2799                         if (i915_semaphore_is_enabled(dev)) {
2800                                 ring->semaphore.sync_to = gen8_ring_sync;
2801                                 ring->semaphore.signal = gen8_xcs_signal;
2802                                 GEN8_RING_SEMAPHORE_INIT;
2803                         }
2804                 } else {
2805                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2806                         ring->irq_get = gen6_ring_get_irq;
2807                         ring->irq_put = gen6_ring_put_irq;
2808                         ring->dispatch_execbuffer =
2809                                 gen6_ring_dispatch_execbuffer;
2810                         if (i915_semaphore_is_enabled(dev)) {
2811                                 ring->semaphore.sync_to = gen6_ring_sync;
2812                                 ring->semaphore.signal = gen6_signal;
2813                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2814                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2815                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2816                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2817                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2818                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2819                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2820                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2821                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2822                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2823                         }
2824                 }
2825         } else {
2826                 ring->mmio_base = BSD_RING_BASE;
2827                 ring->flush = bsd_ring_flush;
2828                 ring->add_request = i9xx_add_request;
2829                 ring->get_seqno = ring_get_seqno;
2830                 ring->set_seqno = ring_set_seqno;
2831                 if (IS_GEN5(dev)) {
2832                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2833                         ring->irq_get = gen5_ring_get_irq;
2834                         ring->irq_put = gen5_ring_put_irq;
2835                 } else {
2836                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2837                         ring->irq_get = i9xx_ring_get_irq;
2838                         ring->irq_put = i9xx_ring_put_irq;
2839                 }
2840                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2841         }
2842         ring->init_hw = init_ring_common;
2843
2844         return intel_init_ring_buffer(dev, ring);
2845 }
2846
2847 /**
2848  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2849  */
2850 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2851 {
2852         struct drm_i915_private *dev_priv = dev->dev_private;
2853         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2854
2855         ring->name = "bsd2 ring";
2856         ring->id = VCS2;
2857
2858         ring->write_tail = ring_write_tail;
2859         ring->mmio_base = GEN8_BSD2_RING_BASE;
2860         ring->flush = gen6_bsd_ring_flush;
2861         ring->add_request = gen6_add_request;
2862         ring->get_seqno = gen6_ring_get_seqno;
2863         ring->set_seqno = ring_set_seqno;
2864         ring->irq_enable_mask =
2865                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2866         ring->irq_get = gen8_ring_get_irq;
2867         ring->irq_put = gen8_ring_put_irq;
2868         ring->dispatch_execbuffer =
2869                         gen8_ring_dispatch_execbuffer;
2870         if (i915_semaphore_is_enabled(dev)) {
2871                 ring->semaphore.sync_to = gen8_ring_sync;
2872                 ring->semaphore.signal = gen8_xcs_signal;
2873                 GEN8_RING_SEMAPHORE_INIT;
2874         }
2875         ring->init_hw = init_ring_common;
2876
2877         return intel_init_ring_buffer(dev, ring);
2878 }
2879
2880 int intel_init_blt_ring_buffer(struct drm_device *dev)
2881 {
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2884
2885         ring->name = "blitter ring";
2886         ring->id = BCS;
2887
2888         ring->mmio_base = BLT_RING_BASE;
2889         ring->write_tail = ring_write_tail;
2890         ring->flush = gen6_ring_flush;
2891         ring->add_request = gen6_add_request;
2892         ring->get_seqno = gen6_ring_get_seqno;
2893         ring->set_seqno = ring_set_seqno;
2894         if (INTEL_INFO(dev)->gen >= 8) {
2895                 ring->irq_enable_mask =
2896                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2897                 ring->irq_get = gen8_ring_get_irq;
2898                 ring->irq_put = gen8_ring_put_irq;
2899                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2900                 if (i915_semaphore_is_enabled(dev)) {
2901                         ring->semaphore.sync_to = gen8_ring_sync;
2902                         ring->semaphore.signal = gen8_xcs_signal;
2903                         GEN8_RING_SEMAPHORE_INIT;
2904                 }
2905         } else {
2906                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2907                 ring->irq_get = gen6_ring_get_irq;
2908                 ring->irq_put = gen6_ring_put_irq;
2909                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2910                 if (i915_semaphore_is_enabled(dev)) {
2911                         ring->semaphore.signal = gen6_signal;
2912                         ring->semaphore.sync_to = gen6_ring_sync;
2913                         /*
2914                          * The current semaphore is only applied on pre-gen8
2915                          * platform.  And there is no VCS2 ring on the pre-gen8
2916                          * platform. So the semaphore between BCS and VCS2 is
2917                          * initialized as INVALID.  Gen8 will initialize the
2918                          * sema between BCS and VCS2 later.
2919                          */
2920                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2921                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2922                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2923                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2924                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2925                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2926                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2927                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2928                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2929                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2930                 }
2931         }
2932         ring->init_hw = init_ring_common;
2933
2934         return intel_init_ring_buffer(dev, ring);
2935 }
2936
2937 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2938 {
2939         struct drm_i915_private *dev_priv = dev->dev_private;
2940         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2941
2942         ring->name = "video enhancement ring";
2943         ring->id = VECS;
2944
2945         ring->mmio_base = VEBOX_RING_BASE;
2946         ring->write_tail = ring_write_tail;
2947         ring->flush = gen6_ring_flush;
2948         ring->add_request = gen6_add_request;
2949         ring->get_seqno = gen6_ring_get_seqno;
2950         ring->set_seqno = ring_set_seqno;
2951
2952         if (INTEL_INFO(dev)->gen >= 8) {
2953                 ring->irq_enable_mask =
2954                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2955                 ring->irq_get = gen8_ring_get_irq;
2956                 ring->irq_put = gen8_ring_put_irq;
2957                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2958                 if (i915_semaphore_is_enabled(dev)) {
2959                         ring->semaphore.sync_to = gen8_ring_sync;
2960                         ring->semaphore.signal = gen8_xcs_signal;
2961                         GEN8_RING_SEMAPHORE_INIT;
2962                 }
2963         } else {
2964                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2965                 ring->irq_get = hsw_vebox_get_irq;
2966                 ring->irq_put = hsw_vebox_put_irq;
2967                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2968                 if (i915_semaphore_is_enabled(dev)) {
2969                         ring->semaphore.sync_to = gen6_ring_sync;
2970                         ring->semaphore.signal = gen6_signal;
2971                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2972                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2973                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2974                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2975                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2976                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2977                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2978                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2979                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2980                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2981                 }
2982         }
2983         ring->init_hw = init_ring_common;
2984
2985         return intel_init_ring_buffer(dev, ring);
2986 }
2987
2988 int
2989 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
2990 {
2991         struct intel_engine_cs *ring = req->ring;
2992         int ret;
2993
2994         if (!ring->gpu_caches_dirty)
2995                 return 0;
2996
2997         ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
2998         if (ret)
2999                 return ret;
3000
3001         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3002
3003         ring->gpu_caches_dirty = false;
3004         return 0;
3005 }
3006
3007 int
3008 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3009 {
3010         struct intel_engine_cs *ring = req->ring;
3011         uint32_t flush_domains;
3012         int ret;
3013
3014         flush_domains = 0;
3015         if (ring->gpu_caches_dirty)
3016                 flush_domains = I915_GEM_GPU_DOMAINS;
3017
3018         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3019         if (ret)
3020                 return ret;
3021
3022         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3023
3024         ring->gpu_caches_dirty = false;
3025         return 0;
3026 }
3027
3028 void
3029 intel_stop_ring_buffer(struct intel_engine_cs *ring)
3030 {
3031         int ret;
3032
3033         if (!intel_ring_initialized(ring))
3034                 return;
3035
3036         ret = intel_ring_idle(ring);
3037         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3038                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3039                           ring->name, ret);
3040
3041         stop_ring(ring);
3042 }