drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 int __intel_ring_space(int head, int tail, int size)
  38 {
  39         int space = head - tail;
  40         if (space <= 0)
  41                 space += size;
  42         return space - I915_RING_FREE_SPACE;
  43 }
  44
  45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  46 {
  47         if (ringbuf->last_retired_head != -1) {
  48                 ringbuf->head = ringbuf->last_retired_head;
  49                 ringbuf->last_retired_head = -1;
  50         }
  51
  52         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  53                                             ringbuf->tail, ringbuf->size);
  54 }
  55
  56 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  57 {
  58         intel_ring_update_space(ringbuf);
  59         return ringbuf->space;
  60 }
  61
  62 bool intel_engine_stopped(struct intel_engine_cs *engine)
  63 {
  64         struct drm_i915_private *dev_priv = engine->dev->dev_private;
  65         return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
  66 }
  67
  68 static void __intel_ring_advance(struct intel_engine_cs *engine)
  69 {
  70         struct intel_ringbuffer *ringbuf = engine->buffer;
  71         ringbuf->tail &= ringbuf->size - 1;
  72         if (intel_engine_stopped(engine))
  73                 return;
  74         engine->write_tail(engine, ringbuf->tail);
  75 }
  76
  77 static int
  78 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  79                        u32      invalidate_domains,
  80                        u32      flush_domains)
  81 {
  82         struct intel_engine_cs *engine = req->engine;
  83         u32 cmd;
  84         int ret;
  85
  86         cmd = MI_FLUSH;
  87         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  88                 cmd |= MI_NO_WRITE_FLUSH;
  89
  90         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  91                 cmd |= MI_READ_FLUSH;
  92
  93         ret = intel_ring_begin(req, 2);
  94         if (ret)
  95                 return ret;
  96
  97         intel_ring_emit(engine, cmd);
  98         intel_ring_emit(engine, MI_NOOP);
  99         intel_ring_advance(engine);
 100
 101         return 0;
 102 }
 103
 104 static int
 105 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 106                        u32      invalidate_domains,
 107                        u32      flush_domains)
 108 {
 109         struct intel_engine_cs *engine = req->engine;
 110         struct drm_device *dev = engine->dev;
 111         u32 cmd;
 112         int ret;
 113
 114         /*
 115          * read/write caches:
 116          *
 117          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 118          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 119          * also flushed at 2d versus 3d pipeline switches.
 120          *
 121          * read-only caches:
 122          *
 123          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 124          * MI_READ_FLUSH is set, and is always flushed on 965.
 125          *
 126          * I915_GEM_DOMAIN_COMMAND may not exist?
 127          *
 128          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 129          * invalidated when MI_EXE_FLUSH is set.
 130          *
 131          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 132          * invalidated with every MI_FLUSH.
 133          *
 134          * TLBs:
 135          *
 136          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 137          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 138          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 139          * are flushed at any MI_FLUSH.
 140          */
 141
 142         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 143         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 144                 cmd &= ~MI_NO_WRITE_FLUSH;
 145         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 146                 cmd |= MI_EXE_FLUSH;
 147
 148         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 149             (IS_G4X(dev) || IS_GEN5(dev)))
 150                 cmd |= MI_INVALIDATE_ISP;
 151
 152         ret = intel_ring_begin(req, 2);
 153         if (ret)
 154                 return ret;
 155
 156         intel_ring_emit(engine, cmd);
 157         intel_ring_emit(engine, MI_NOOP);
 158         intel_ring_advance(engine);
 159
 160         return 0;
 161 }
 162
 163 /**
 164  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 165  * implementing two workarounds on gen6.  From section 1.4.7.1
 166  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 167  *
 168  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 169  * produced by non-pipelined state commands), software needs to first
 170  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 171  * 0.
 172  *
 173  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 174  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 175  *
 176  * And the workaround for these two requires this workaround first:
 177  *
 178  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 179  * BEFORE the pipe-control with a post-sync op and no write-cache
 180  * flushes.
 181  *
 182  * And this last workaround is tricky because of the requirements on
 183  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 184  * volume 2 part 1:
 185  *
 186  *     "1 of the following must also be set:
 187  *      - Render Target Cache Flush Enable ([12] of DW1)
 188  *      - Depth Cache Flush Enable ([0] of DW1)
 189  *      - Stall at Pixel Scoreboard ([1] of DW1)
 190  *      - Depth Stall ([13] of DW1)
 191  *      - Post-Sync Operation ([13] of DW1)
 192  *      - Notify Enable ([8] of DW1)"
 193  *
 194  * The cache flushes require the workaround flush that triggered this
 195  * one, so we can't use it.  Depth stall would trigger the same.
 196  * Post-sync nonzero is what triggered this second workaround, so we
 197  * can't use that one either.  Notify enable is IRQs, which aren't
 198  * really our business.  That leaves only stall at scoreboard.
 199  */
 200 static int
 201 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 202 {
 203         struct intel_engine_cs *engine = req->engine;
 204         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 205         int ret;
 206
 207         ret = intel_ring_begin(req, 6);
 208         if (ret)
 209                 return ret;
 210
 211         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 212         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 213                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 214         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 215         intel_ring_emit(engine, 0); /* low dword */
 216         intel_ring_emit(engine, 0); /* high dword */
 217         intel_ring_emit(engine, MI_NOOP);
 218         intel_ring_advance(engine);
 219
 220         ret = intel_ring_begin(req, 6);
 221         if (ret)
 222                 return ret;
 223
 224         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 225         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 226         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 227         intel_ring_emit(engine, 0);
 228         intel_ring_emit(engine, 0);
 229         intel_ring_emit(engine, MI_NOOP);
 230         intel_ring_advance(engine);
 231
 232         return 0;
 233 }
 234
 235 static int
 236 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 237                        u32 invalidate_domains, u32 flush_domains)
 238 {
 239         struct intel_engine_cs *engine = req->engine;
 240         u32 flags = 0;
 241         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 242         int ret;
 243
 244         /* Force SNB workarounds for PIPE_CONTROL flushes */
 245         ret = intel_emit_post_sync_nonzero_flush(req);
 246         if (ret)
 247                 return ret;
 248
 249         /* Just flush everything.  Experiments have shown that reducing the
 250          * number of bits based on the write domains has little performance
 251          * impact.
 252          */
 253         if (flush_domains) {
 254                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 255                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 256                 /*
 257                  * Ensure that any following seqno writes only happen
 258                  * when the render cache is indeed flushed.
 259                  */
 260                 flags |= PIPE_CONTROL_CS_STALL;
 261         }
 262         if (invalidate_domains) {
 263                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 264                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 265                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 266                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 267                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 268                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 269                 /*
 270                  * TLB invalidate requires a post-sync write.
 271                  */
 272                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 273         }
 274
 275         ret = intel_ring_begin(req, 4);
 276         if (ret)
 277                 return ret;
 278
 279         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 280         intel_ring_emit(engine, flags);
 281         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 282         intel_ring_emit(engine, 0);
 283         intel_ring_advance(engine);
 284
 285         return 0;
 286 }
 287
 288 static int
 289 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 290 {
 291         struct intel_engine_cs *engine = req->engine;
 292         int ret;
 293
 294         ret = intel_ring_begin(req, 4);
 295         if (ret)
 296                 return ret;
 297
 298         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 299         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 300                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 301         intel_ring_emit(engine, 0);
 302         intel_ring_emit(engine, 0);
 303         intel_ring_advance(engine);
 304
 305         return 0;
 306 }
 307
 308 static int
 309 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 310                        u32 invalidate_domains, u32 flush_domains)
 311 {
 312         struct intel_engine_cs *engine = req->engine;
 313         u32 flags = 0;
 314         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 315         int ret;
 316
 317         /*
 318          * Ensure that any following seqno writes only happen when the render
 319          * cache is indeed flushed.
 320          *
 321          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 322          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 323          * don't try to be clever and just set it unconditionally.
 324          */
 325         flags |= PIPE_CONTROL_CS_STALL;
 326
 327         /* Just flush everything.  Experiments have shown that reducing the
 328          * number of bits based on the write domains has little performance
 329          * impact.
 330          */
 331         if (flush_domains) {
 332                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 333                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 334                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 335                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 336         }
 337         if (invalidate_domains) {
 338                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 339                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 340                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 341                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 342                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 343                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 344                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 345                 /*
 346                  * TLB invalidate requires a post-sync write.
 347                  */
 348                 flags |= PIPE_CONTROL_QW_WRITE;
 349                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 350
 351                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 352
 353                 /* Workaround: we must issue a pipe_control with CS-stall bit
 354                  * set before a pipe_control command that has the state cache
 355                  * invalidate bit set. */
 356                 gen7_render_ring_cs_stall_wa(req);
 357         }
 358
 359         ret = intel_ring_begin(req, 4);
 360         if (ret)
 361                 return ret;
 362
 363         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 364         intel_ring_emit(engine, flags);
 365         intel_ring_emit(engine, scratch_addr);
 366         intel_ring_emit(engine, 0);
 367         intel_ring_advance(engine);
 368
 369         return 0;
 370 }
 371
 372 static int
 373 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 374                        u32 flags, u32 scratch_addr)
 375 {
 376         struct intel_engine_cs *engine = req->engine;
 377         int ret;
 378
 379         ret = intel_ring_begin(req, 6);
 380         if (ret)
 381                 return ret;
 382
 383         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 384         intel_ring_emit(engine, flags);
 385         intel_ring_emit(engine, scratch_addr);
 386         intel_ring_emit(engine, 0);
 387         intel_ring_emit(engine, 0);
 388         intel_ring_emit(engine, 0);
 389         intel_ring_advance(engine);
 390
 391         return 0;
 392 }
 393
 394 static int
 395 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 396                        u32 invalidate_domains, u32 flush_domains)
 397 {
 398         u32 flags = 0;
 399         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 400         int ret;
 401
 402         flags |= PIPE_CONTROL_CS_STALL;
 403
 404         if (flush_domains) {
 405                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 406                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 407                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 408                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 409         }
 410         if (invalidate_domains) {
 411                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 412                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 413                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 414                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 415                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 416                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 417                 flags |= PIPE_CONTROL_QW_WRITE;
 418                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 419
 420                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 421                 ret = gen8_emit_pipe_control(req,
 422                                              PIPE_CONTROL_CS_STALL |
 423                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 424                                              0);
 425                 if (ret)
 426                         return ret;
 427         }
 428
 429         return gen8_emit_pipe_control(req, flags, scratch_addr);
 430 }
 431
 432 static void ring_write_tail(struct intel_engine_cs *engine,
 433                             u32 value)
 434 {
 435         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 436         I915_WRITE_TAIL(engine, value);
 437 }
 438
 439 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 440 {
 441         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 442         u64 acthd;
 443
 444         if (INTEL_INFO(engine->dev)->gen >= 8)
 445                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 446                                          RING_ACTHD_UDW(engine->mmio_base));
 447         else if (INTEL_INFO(engine->dev)->gen >= 4)
 448                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 449         else
 450                 acthd = I915_READ(ACTHD);
 451
 452         return acthd;
 453 }
 454
 455 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 456 {
 457         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 458         u32 addr;
 459
 460         addr = dev_priv->status_page_dmah->busaddr;
 461         if (INTEL_INFO(engine->dev)->gen >= 4)
 462                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 463         I915_WRITE(HWS_PGA, addr);
 464 }
 465
 466 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 467 {
 468         struct drm_device *dev = engine->dev;
 469         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 470         i915_reg_t mmio;
 471
 472         /* The ring status page addresses are no longer next to the rest of
 473          * the ring registers as of gen7.
 474          */
 475         if (IS_GEN7(dev)) {
 476                 switch (engine->id) {
 477                 case RCS:
 478                         mmio = RENDER_HWS_PGA_GEN7;
 479                         break;
 480                 case BCS:
 481                         mmio = BLT_HWS_PGA_GEN7;
 482                         break;
 483                 /*
 484                  * VCS2 actually doesn't exist on Gen7. Only shut up
 485                  * gcc switch check warning
 486                  */
 487                 case VCS2:
 488                 case VCS:
 489                         mmio = BSD_HWS_PGA_GEN7;
 490                         break;
 491                 case VECS:
 492                         mmio = VEBOX_HWS_PGA_GEN7;
 493                         break;
 494                 }
 495         } else if (IS_GEN6(engine->dev)) {
 496                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 497         } else {
 498                 /* XXX: gen8 returns to sanity */
 499                 mmio = RING_HWS_PGA(engine->mmio_base);
 500         }
 501
 502         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 503         POSTING_READ(mmio);
 504
 505         /*
 506          * Flush the TLB for this page
 507          *
 508          * FIXME: These two bits have disappeared on gen8, so a question
 509          * arises: do we still need this and if so how should we go about
 510          * invalidating the TLB?
 511          */
 512         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 513                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 514
 515                 /* ring should be idle before issuing a sync flush*/
 516                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 517
 518                 I915_WRITE(reg,
 519                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 520                                               INSTPM_SYNC_FLUSH));
 521                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 522                              1000))
 523                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 524                                   engine->name);
 525         }
 526 }
 527
 528 static bool stop_ring(struct intel_engine_cs *engine)
 529 {
 530         struct drm_i915_private *dev_priv = to_i915(engine->dev);
 531
 532         if (!IS_GEN2(engine->dev)) {
 533                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 534                 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
 535                         DRM_ERROR("%s : timed out trying to stop ring\n",
 536                                   engine->name);
 537                         /* Sometimes we observe that the idle flag is not
 538                          * set even though the ring is empty. So double
 539                          * check before giving up.
 540                          */
 541                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 542                                 return false;
 543                 }
 544         }
 545
 546         I915_WRITE_CTL(engine, 0);
 547         I915_WRITE_HEAD(engine, 0);
 548         engine->write_tail(engine, 0);
 549
 550         if (!IS_GEN2(engine->dev)) {
 551                 (void)I915_READ_CTL(engine);
 552                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 553         }
 554
 555         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 556 }
 557
 558 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 559 {
 560         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 561 }
 562
 563 static int init_ring_common(struct intel_engine_cs *engine)
 564 {
 565         struct drm_device *dev = engine->dev;
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct intel_ringbuffer *ringbuf = engine->buffer;
 568         struct drm_i915_gem_object *obj = ringbuf->obj;
 569         int ret = 0;
 570
 571         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 572
 573         if (!stop_ring(engine)) {
 574                 /* G45 ring initialization often fails to reset head to zero */
 575                 DRM_DEBUG_KMS("%s head not reset to zero "
 576                               "ctl %08x head %08x tail %08x start %08x\n",
 577                               engine->name,
 578                               I915_READ_CTL(engine),
 579                               I915_READ_HEAD(engine),
 580                               I915_READ_TAIL(engine),
 581                               I915_READ_START(engine));
 582
 583                 if (!stop_ring(engine)) {
 584                         DRM_ERROR("failed to set %s head to zero "
 585                                   "ctl %08x head %08x tail %08x start %08x\n",
 586                                   engine->name,
 587                                   I915_READ_CTL(engine),
 588                                   I915_READ_HEAD(engine),
 589                                   I915_READ_TAIL(engine),
 590                                   I915_READ_START(engine));
 591                         ret = -EIO;
 592                         goto out;
 593                 }
 594         }
 595
 596         if (I915_NEED_GFX_HWS(dev))
 597                 intel_ring_setup_status_page(engine);
 598         else
 599                 ring_setup_phys_status_page(engine);
 600
 601         /* Enforce ordering by reading HEAD register back */
 602         I915_READ_HEAD(engine);
 603
 604         /* Initialize the ring. This must happen _after_ we've cleared the ring
 605          * registers with the above sequence (the readback of the HEAD registers
 606          * also enforces ordering), otherwise the hw might lose the new ring
 607          * register values. */
 608         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 609
 610         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 611         if (I915_READ_HEAD(engine))
 612                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 613                           engine->name, I915_READ_HEAD(engine));
 614         I915_WRITE_HEAD(engine, 0);
 615         (void)I915_READ_HEAD(engine);
 616
 617         I915_WRITE_CTL(engine,
 618                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 619                         | RING_VALID);
 620
 621         /* If the head is still not zero, the ring is dead */
 622         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 623                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 624                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 625                 DRM_ERROR("%s initialization failed "
 626                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 627                           engine->name,
 628                           I915_READ_CTL(engine),
 629                           I915_READ_CTL(engine) & RING_VALID,
 630                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 631                           I915_READ_START(engine),
 632                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 633                 ret = -EIO;
 634                 goto out;
 635         }
 636
 637         ringbuf->last_retired_head = -1;
 638         ringbuf->head = I915_READ_HEAD(engine);
 639         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 640         intel_ring_update_space(ringbuf);
 641
 642         intel_engine_init_hangcheck(engine);
 643
 644 out:
 645         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 646
 647         return ret;
 648 }
 649
 650 void
 651 intel_fini_pipe_control(struct intel_engine_cs *engine)
 652 {
 653         struct drm_device *dev = engine->dev;
 654
 655         if (engine->scratch.obj == NULL)
 656                 return;
 657
 658         if (INTEL_INFO(dev)->gen >= 5) {
 659                 kunmap(sg_page(engine->scratch.obj->pages->sgl));
 660                 i915_gem_object_ggtt_unpin(engine->scratch.obj);
 661         }
 662
 663         drm_gem_object_unreference(&engine->scratch.obj->base);
 664         engine->scratch.obj = NULL;
 665 }
 666
 667 int
 668 intel_init_pipe_control(struct intel_engine_cs *engine)
 669 {
 670         int ret;
 671
 672         WARN_ON(engine->scratch.obj);
 673
 674         engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
 675         if (engine->scratch.obj == NULL) {
 676                 DRM_ERROR("Failed to allocate seqno page\n");
 677                 ret = -ENOMEM;
 678                 goto err;
 679         }
 680
 681         ret = i915_gem_object_set_cache_level(engine->scratch.obj,
 682                                               I915_CACHE_LLC);
 683         if (ret)
 684                 goto err_unref;
 685
 686         ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
 687         if (ret)
 688                 goto err_unref;
 689
 690         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
 691         engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
 692         if (engine->scratch.cpu_page == NULL) {
 693                 ret = -ENOMEM;
 694                 goto err_unpin;
 695         }
 696
 697         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 698                          engine->name, engine->scratch.gtt_offset);
 699         return 0;
 700
 701 err_unpin:
 702         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 703 err_unref:
 704         drm_gem_object_unreference(&engine->scratch.obj->base);
 705 err:
 706         return ret;
 707 }
 708
 709 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 710 {
 711         int ret, i;
 712         struct intel_engine_cs *engine = req->engine;
 713         struct drm_device *dev = engine->dev;
 714         struct drm_i915_private *dev_priv = dev->dev_private;
 715         struct i915_workarounds *w = &dev_priv->workarounds;
 716
 717         if (w->count == 0)
 718                 return 0;
 719
 720         engine->gpu_caches_dirty = true;
 721         ret = intel_ring_flush_all_caches(req);
 722         if (ret)
 723                 return ret;
 724
 725         ret = intel_ring_begin(req, (w->count * 2 + 2));
 726         if (ret)
 727                 return ret;
 728
 729         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 730         for (i = 0; i < w->count; i++) {
 731                 intel_ring_emit_reg(engine, w->reg[i].addr);
 732                 intel_ring_emit(engine, w->reg[i].value);
 733         }
 734         intel_ring_emit(engine, MI_NOOP);
 735
 736         intel_ring_advance(engine);
 737
 738         engine->gpu_caches_dirty = true;
 739         ret = intel_ring_flush_all_caches(req);
 740         if (ret)
 741                 return ret;
 742
 743         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 744
 745         return 0;
 746 }
 747
 748 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 749 {
 750         int ret;
 751
 752         ret = intel_ring_workarounds_emit(req);
 753         if (ret != 0)
 754                 return ret;
 755
 756         ret = i915_gem_render_state_init(req);
 757         if (ret)
 758                 return ret;
 759
 760         return 0;
 761 }
 762
 763 static int wa_add(struct drm_i915_private *dev_priv,
 764                   i915_reg_t addr,
 765                   const u32 mask, const u32 val)
 766 {
 767         const u32 idx = dev_priv->workarounds.count;
 768
 769         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 770                 return -ENOSPC;
 771
 772         dev_priv->workarounds.reg[idx].addr = addr;
 773         dev_priv->workarounds.reg[idx].value = val;
 774         dev_priv->workarounds.reg[idx].mask = mask;
 775
 776         dev_priv->workarounds.count++;
 777
 778         return 0;
 779 }
 780
 781 #define WA_REG(addr, mask, val) do { \
 782                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 783                 if (r) \
 784                         return r; \
 785         } while (0)
 786
 787 #define WA_SET_BIT_MASKED(addr, mask) \
 788         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 789
 790 #define WA_CLR_BIT_MASKED(addr, mask) \
 791         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 792
 793 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 794         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 795
 796 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 797 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 798
 799 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 800
 801 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 802                                  i915_reg_t reg)
 803 {
 804         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 805         struct i915_workarounds *wa = &dev_priv->workarounds;
 806         const uint32_t index = wa->hw_whitelist_count[engine->id];
 807
 808         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 809                 return -EINVAL;
 810
 811         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 812                  i915_mmio_reg_offset(reg));
 813         wa->hw_whitelist_count[engine->id]++;
 814
 815         return 0;
 816 }
 817
 818 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 819 {
 820         struct drm_device *dev = engine->dev;
 821         struct drm_i915_private *dev_priv = dev->dev_private;
 822
 823         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 824
 825         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 826         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 827
 828         /* WaDisablePartialInstShootdown:bdw,chv */
 829         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 830                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 831
 832         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 833          * workaround for for a possible hang in the unlikely event a TLB
 834          * invalidation occurs during a PSD flush.
 835          */
 836         /* WaForceEnableNonCoherent:bdw,chv */
 837         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 838         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 839                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 840                           HDC_FORCE_NON_COHERENT);
 841
 842         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 843          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 844          *  polygons in the same 8x4 pixel/sample area to be processed without
 845          *  stalling waiting for the earlier ones to write to Hierarchical Z
 846          *  buffer."
 847          *
 848          * This optimization is off by default for BDW and CHV; turn it on.
 849          */
 850         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 851
 852         /* Wa4x4STCOptimizationDisable:bdw,chv */
 853         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 854
 855         /*
 856          * BSpec recommends 8x4 when MSAA is used,
 857          * however in practice 16x4 seems fastest.
 858          *
 859          * Note that PS/WM thread counts depend on the WIZ hashing
 860          * disable bit, which we don't touch here, but it's good
 861          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 862          */
 863         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 864                             GEN6_WIZ_HASHING_MASK,
 865                             GEN6_WIZ_HASHING_16x4);
 866
 867         return 0;
 868 }
 869
 870 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 871 {
 872         int ret;
 873         struct drm_device *dev = engine->dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875
 876         ret = gen8_init_workarounds(engine);
 877         if (ret)
 878                 return ret;
 879
 880         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 881         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 882
 883         /* WaDisableDopClockGating:bdw */
 884         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 885                           DOP_CLOCK_GATING_DISABLE);
 886
 887         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 888                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 889
 890         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 891                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 892                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 893                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 894                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 895
 896         return 0;
 897 }
 898
 899 static int chv_init_workarounds(struct intel_engine_cs *engine)
 900 {
 901         int ret;
 902         struct drm_device *dev = engine->dev;
 903         struct drm_i915_private *dev_priv = dev->dev_private;
 904
 905         ret = gen8_init_workarounds(engine);
 906         if (ret)
 907                 return ret;
 908
 909         /* WaDisableThreadStallDopClockGating:chv */
 910         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 911
 912         /* Improve HiZ throughput on CHV. */
 913         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 914
 915         return 0;
 916 }
 917
 918 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 919 {
 920         struct drm_device *dev = engine->dev;
 921         struct drm_i915_private *dev_priv = dev->dev_private;
 922         uint32_t tmp;
 923         int ret;
 924
 925         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 926         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 927                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 928
 929         /* WaDisableKillLogic:bxt,skl */
 930         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 931                    ECOCHK_DIS_TLB);
 932
 933         /* WaClearFlowControlGpgpuContextSave:skl,bxt */
 934         /* WaDisablePartialInstShootdown:skl,bxt */
 935         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 936                           FLOW_CONTROL_ENABLE |
 937                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 938
 939         /* Syncing dependencies between camera and graphics:skl,bxt */
 940         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 941                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 942
 943         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 944         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 945             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 946                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 947                                   GEN9_DG_MIRROR_FIX_ENABLE);
 948
 949         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 950         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 951             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 952                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 953                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 954                 /*
 955                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 956                  * but we do that in per ctx batchbuffer as there is an issue
 957                  * with this register not getting restored on ctx restore
 958                  */
 959         }
 960
 961         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 962         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
 963         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 964                           GEN9_ENABLE_YV12_BUGFIX |
 965                           GEN9_ENABLE_GPGPU_PREEMPTION);
 966
 967         /* Wa4x4STCOptimizationDisable:skl,bxt */
 968         /* WaDisablePartialResolveInVc:skl,bxt */
 969         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 970                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 971
 972         /* WaCcsTlbPrefetchDisable:skl,bxt */
 973         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 974                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 975
 976         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 977         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 978             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 979                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 980                                   PIXEL_MASK_CAMMING_DISABLE);
 981
 982         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 983         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 984         if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
 985             IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
 986                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 987         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 988
 989         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 990         if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 991                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 992                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 993
 994         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 995         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 996
 997         /* WaOCLCoherentLineFlush:skl,bxt */
 998         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 999                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
1000
1001         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
1002         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1003         if (ret)
1004                 return ret;
1005
1006         /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
1007         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1008         if (ret)
1009                 return ret;
1010
1011         return 0;
1012 }
1013
1014 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1015 {
1016         struct drm_device *dev = engine->dev;
1017         struct drm_i915_private *dev_priv = dev->dev_private;
1018         u8 vals[3] = { 0, 0, 0 };
1019         unsigned int i;
1020
1021         for (i = 0; i < 3; i++) {
1022                 u8 ss;
1023
1024                 /*
1025                  * Only consider slices where one, and only one, subslice has 7
1026                  * EUs
1027                  */
1028                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1029                         continue;
1030
1031                 /*
1032                  * subslice_7eu[i] != 0 (because of the check above) and
1033                  * ss_max == 4 (maximum number of subslices possible per slice)
1034                  *
1035                  * ->    0 <= ss <= 3;
1036                  */
1037                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1038                 vals[i] = 3 - ss;
1039         }
1040
1041         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1042                 return 0;
1043
1044         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1045         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1046                             GEN9_IZ_HASHING_MASK(2) |
1047                             GEN9_IZ_HASHING_MASK(1) |
1048                             GEN9_IZ_HASHING_MASK(0),
1049                             GEN9_IZ_HASHING(2, vals[2]) |
1050                             GEN9_IZ_HASHING(1, vals[1]) |
1051                             GEN9_IZ_HASHING(0, vals[0]));
1052
1053         return 0;
1054 }
1055
1056 static int skl_init_workarounds(struct intel_engine_cs *engine)
1057 {
1058         int ret;
1059         struct drm_device *dev = engine->dev;
1060         struct drm_i915_private *dev_priv = dev->dev_private;
1061
1062         ret = gen9_init_workarounds(engine);
1063         if (ret)
1064                 return ret;
1065
1066         /*
1067          * Actual WA is to disable percontext preemption granularity control
1068          * until D0 which is the default case so this is equivalent to
1069          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1070          */
1071         if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1072                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1073                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1074         }
1075
1076         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1077                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1078                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1079                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1080         }
1081
1082         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1083          * involving this register should also be added to WA batch as required.
1084          */
1085         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1086                 /* WaDisableLSQCROPERFforOCL:skl */
1087                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1088                            GEN8_LQSC_RO_PERF_DIS);
1089
1090         /* WaEnableGapsTsvCreditFix:skl */
1091         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1092                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1093                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1094         }
1095
1096         /* WaDisablePowerCompilerClockGating:skl */
1097         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1098                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1099                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1100
1101         /* This is tied to WaForceContextSaveRestoreNonCoherent */
1102         if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
1103                 /*
1104                  *Use Force Non-Coherent whenever executing a 3D context. This
1105                  * is a workaround for a possible hang in the unlikely event
1106                  * a TLB invalidation occurs during a PSD flush.
1107                  */
1108                 /* WaForceEnableNonCoherent:skl */
1109                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1110                                   HDC_FORCE_NON_COHERENT);
1111
1112                 /* WaDisableHDCInvalidation:skl */
1113                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1114                            BDW_DISABLE_HDC_INVALIDATION);
1115         }
1116
1117         /* WaBarrierPerformanceFixDisable:skl */
1118         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1119                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1120                                   HDC_FENCE_DEST_SLM_DISABLE |
1121                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1122
1123         /* WaDisableSbeCacheDispatchPortSharing:skl */
1124         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1125                 WA_SET_BIT_MASKED(
1126                         GEN7_HALF_SLICE_CHICKEN1,
1127                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1128
1129         /* WaDisableLSQCROPERFforOCL:skl */
1130         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1131         if (ret)
1132                 return ret;
1133
1134         return skl_tune_iz_hashing(engine);
1135 }
1136
1137 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1138 {
1139         int ret;
1140         struct drm_device *dev = engine->dev;
1141         struct drm_i915_private *dev_priv = dev->dev_private;
1142
1143         ret = gen9_init_workarounds(engine);
1144         if (ret)
1145                 return ret;
1146
1147         /* WaStoreMultiplePTEenable:bxt */
1148         /* This is a requirement according to Hardware specification */
1149         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1150                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1151
1152         /* WaSetClckGatingDisableMedia:bxt */
1153         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1154                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1155                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1156         }
1157
1158         /* WaDisableThreadStallDopClockGating:bxt */
1159         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1160                           STALL_DOP_GATING_DISABLE);
1161
1162         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1163         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1164                 WA_SET_BIT_MASKED(
1165                         GEN7_HALF_SLICE_CHICKEN1,
1166                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1167         }
1168
1169         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1170         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1171         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1172         /* WaDisableLSQCROPERFforOCL:bxt */
1173         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1174                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1175                 if (ret)
1176                         return ret;
1177
1178                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1179                 if (ret)
1180                         return ret;
1181         }
1182
1183         return 0;
1184 }
1185
1186 int init_workarounds_ring(struct intel_engine_cs *engine)
1187 {
1188         struct drm_device *dev = engine->dev;
1189         struct drm_i915_private *dev_priv = dev->dev_private;
1190
1191         WARN_ON(engine->id != RCS);
1192
1193         dev_priv->workarounds.count = 0;
1194         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1195
1196         if (IS_BROADWELL(dev))
1197                 return bdw_init_workarounds(engine);
1198
1199         if (IS_CHERRYVIEW(dev))
1200                 return chv_init_workarounds(engine);
1201
1202         if (IS_SKYLAKE(dev))
1203                 return skl_init_workarounds(engine);
1204
1205         if (IS_BROXTON(dev))
1206                 return bxt_init_workarounds(engine);
1207
1208         return 0;
1209 }
1210
1211 static int init_render_ring(struct intel_engine_cs *engine)
1212 {
1213         struct drm_device *dev = engine->dev;
1214         struct drm_i915_private *dev_priv = dev->dev_private;
1215         int ret = init_ring_common(engine);
1216         if (ret)
1217                 return ret;
1218
1219         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1220         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1221                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1222
1223         /* We need to disable the AsyncFlip performance optimisations in order
1224          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1225          * programmed to '1' on all products.
1226          *
1227          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1228          */
1229         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1230                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1231
1232         /* Required for the hardware to program scanline values for waiting */
1233         /* WaEnableFlushTlbInvalidationMode:snb */
1234         if (INTEL_INFO(dev)->gen == 6)
1235                 I915_WRITE(GFX_MODE,
1236                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1237
1238         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1239         if (IS_GEN7(dev))
1240                 I915_WRITE(GFX_MODE_GEN7,
1241                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1242                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1243
1244         if (IS_GEN6(dev)) {
1245                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1246                  * "If this bit is set, STCunit will have LRA as replacement
1247                  *  policy. [...] This bit must be reset.  LRA replacement
1248                  *  policy is not supported."
1249                  */
1250                 I915_WRITE(CACHE_MODE_0,
1251                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1252         }
1253
1254         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1255                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1256
1257         if (HAS_L3_DPF(dev))
1258                 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1259
1260         return init_workarounds_ring(engine);
1261 }
1262
1263 static void render_ring_cleanup(struct intel_engine_cs *engine)
1264 {
1265         struct drm_device *dev = engine->dev;
1266         struct drm_i915_private *dev_priv = dev->dev_private;
1267
1268         if (dev_priv->semaphore_obj) {
1269                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1270                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1271                 dev_priv->semaphore_obj = NULL;
1272         }
1273
1274         intel_fini_pipe_control(engine);
1275 }
1276
1277 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1278                            unsigned int num_dwords)
1279 {
1280 #define MBOX_UPDATE_DWORDS 8
1281         struct intel_engine_cs *signaller = signaller_req->engine;
1282         struct drm_device *dev = signaller->dev;
1283         struct drm_i915_private *dev_priv = dev->dev_private;
1284         struct intel_engine_cs *waiter;
1285         enum intel_engine_id id;
1286         int ret, num_rings;
1287
1288         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1289         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1290 #undef MBOX_UPDATE_DWORDS
1291
1292         ret = intel_ring_begin(signaller_req, num_dwords);
1293         if (ret)
1294                 return ret;
1295
1296         for_each_engine_id(waiter, dev_priv, id) {
1297                 u32 seqno;
1298                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1299                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1300                         continue;
1301
1302                 seqno = i915_gem_request_get_seqno(signaller_req);
1303                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1304                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1305                                            PIPE_CONTROL_QW_WRITE |
1306                                            PIPE_CONTROL_FLUSH_ENABLE);
1307                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1308                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1309                 intel_ring_emit(signaller, seqno);
1310                 intel_ring_emit(signaller, 0);
1311                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1312                                            MI_SEMAPHORE_TARGET(waiter->id));
1313                 intel_ring_emit(signaller, 0);
1314         }
1315
1316         return 0;
1317 }
1318
1319 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1320                            unsigned int num_dwords)
1321 {
1322 #define MBOX_UPDATE_DWORDS 6
1323         struct intel_engine_cs *signaller = signaller_req->engine;
1324         struct drm_device *dev = signaller->dev;
1325         struct drm_i915_private *dev_priv = dev->dev_private;
1326         struct intel_engine_cs *waiter;
1327         enum intel_engine_id id;
1328         int ret, num_rings;
1329
1330         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1331         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1332 #undef MBOX_UPDATE_DWORDS
1333
1334         ret = intel_ring_begin(signaller_req, num_dwords);
1335         if (ret)
1336                 return ret;
1337
1338         for_each_engine_id(waiter, dev_priv, id) {
1339                 u32 seqno;
1340                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1341                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1342                         continue;
1343
1344                 seqno = i915_gem_request_get_seqno(signaller_req);
1345                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1346                                            MI_FLUSH_DW_OP_STOREDW);
1347                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1348                                            MI_FLUSH_DW_USE_GTT);
1349                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1350                 intel_ring_emit(signaller, seqno);
1351                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1352                                            MI_SEMAPHORE_TARGET(waiter->id));
1353                 intel_ring_emit(signaller, 0);
1354         }
1355
1356         return 0;
1357 }
1358
1359 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1360                        unsigned int num_dwords)
1361 {
1362         struct intel_engine_cs *signaller = signaller_req->engine;
1363         struct drm_device *dev = signaller->dev;
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         struct intel_engine_cs *useless;
1366         enum intel_engine_id id;
1367         int ret, num_rings;
1368
1369 #define MBOX_UPDATE_DWORDS 3
1370         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1371         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1372 #undef MBOX_UPDATE_DWORDS
1373
1374         ret = intel_ring_begin(signaller_req, num_dwords);
1375         if (ret)
1376                 return ret;
1377
1378         for_each_engine_id(useless, dev_priv, id) {
1379                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1380
1381                 if (i915_mmio_reg_valid(mbox_reg)) {
1382                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1383
1384                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1385                         intel_ring_emit_reg(signaller, mbox_reg);
1386                         intel_ring_emit(signaller, seqno);
1387                 }
1388         }
1389
1390         /* If num_dwords was rounded, make sure the tail pointer is correct */
1391         if (num_rings % 2 == 0)
1392                 intel_ring_emit(signaller, MI_NOOP);
1393
1394         return 0;
1395 }
1396
1397 /**
1398  * gen6_add_request - Update the semaphore mailbox registers
1399  *
1400  * @request - request to write to the ring
1401  *
1402  * Update the mailbox registers in the *other* rings with the current seqno.
1403  * This acts like a signal in the canonical semaphore.
1404  */
1405 static int
1406 gen6_add_request(struct drm_i915_gem_request *req)
1407 {
1408         struct intel_engine_cs *engine = req->engine;
1409         int ret;
1410
1411         if (engine->semaphore.signal)
1412                 ret = engine->semaphore.signal(req, 4);
1413         else
1414                 ret = intel_ring_begin(req, 4);
1415
1416         if (ret)
1417                 return ret;
1418
1419         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1420         intel_ring_emit(engine,
1421                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1422         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1423         intel_ring_emit(engine, MI_USER_INTERRUPT);
1424         __intel_ring_advance(engine);
1425
1426         return 0;
1427 }
1428
1429 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1430                                               u32 seqno)
1431 {
1432         struct drm_i915_private *dev_priv = dev->dev_private;
1433         return dev_priv->last_seqno < seqno;
1434 }
1435
1436 /**
1437  * intel_ring_sync - sync the waiter to the signaller on seqno
1438  *
1439  * @waiter - ring that is waiting
1440  * @signaller - ring which has, or will signal
1441  * @seqno - seqno which the waiter will block on
1442  */
1443
1444 static int
1445 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1446                struct intel_engine_cs *signaller,
1447                u32 seqno)
1448 {
1449         struct intel_engine_cs *waiter = waiter_req->engine;
1450         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1451         int ret;
1452
1453         ret = intel_ring_begin(waiter_req, 4);
1454         if (ret)
1455                 return ret;
1456
1457         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1458                                 MI_SEMAPHORE_GLOBAL_GTT |
1459                                 MI_SEMAPHORE_POLL |
1460                                 MI_SEMAPHORE_SAD_GTE_SDD);
1461         intel_ring_emit(waiter, seqno);
1462         intel_ring_emit(waiter,
1463                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1464         intel_ring_emit(waiter,
1465                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1466         intel_ring_advance(waiter);
1467         return 0;
1468 }
1469
1470 static int
1471 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1472                struct intel_engine_cs *signaller,
1473                u32 seqno)
1474 {
1475         struct intel_engine_cs *waiter = waiter_req->engine;
1476         u32 dw1 = MI_SEMAPHORE_MBOX |
1477                   MI_SEMAPHORE_COMPARE |
1478                   MI_SEMAPHORE_REGISTER;
1479         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1480         int ret;
1481
1482         /* Throughout all of the GEM code, seqno passed implies our current
1483          * seqno is >= the last seqno executed. However for hardware the
1484          * comparison is strictly greater than.
1485          */
1486         seqno -= 1;
1487
1488         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1489
1490         ret = intel_ring_begin(waiter_req, 4);
1491         if (ret)
1492                 return ret;
1493
1494         /* If seqno wrap happened, omit the wait with no-ops */
1495         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1496                 intel_ring_emit(waiter, dw1 | wait_mbox);
1497                 intel_ring_emit(waiter, seqno);
1498                 intel_ring_emit(waiter, 0);
1499                 intel_ring_emit(waiter, MI_NOOP);
1500         } else {
1501                 intel_ring_emit(waiter, MI_NOOP);
1502                 intel_ring_emit(waiter, MI_NOOP);
1503                 intel_ring_emit(waiter, MI_NOOP);
1504                 intel_ring_emit(waiter, MI_NOOP);
1505         }
1506         intel_ring_advance(waiter);
1507
1508         return 0;
1509 }
1510
1511 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1512 do {                                                                    \
1513         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1514                  PIPE_CONTROL_DEPTH_STALL);                             \
1515         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1516         intel_ring_emit(ring__, 0);                                                     \
1517         intel_ring_emit(ring__, 0);                                                     \
1518 } while (0)
1519
1520 static int
1521 pc_render_add_request(struct drm_i915_gem_request *req)
1522 {
1523         struct intel_engine_cs *engine = req->engine;
1524         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1525         int ret;
1526
1527         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1528          * incoherent with writes to memory, i.e. completely fubar,
1529          * so we need to use PIPE_NOTIFY instead.
1530          *
1531          * However, we also need to workaround the qword write
1532          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1533          * memory before requesting an interrupt.
1534          */
1535         ret = intel_ring_begin(req, 32);
1536         if (ret)
1537                 return ret;
1538
1539         intel_ring_emit(engine,
1540                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1541                         PIPE_CONTROL_WRITE_FLUSH |
1542                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1543         intel_ring_emit(engine,
1544                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1545         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1546         intel_ring_emit(engine, 0);
1547         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1548         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1549         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1550         scratch_addr += 2 * CACHELINE_BYTES;
1551         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1552         scratch_addr += 2 * CACHELINE_BYTES;
1553         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1554         scratch_addr += 2 * CACHELINE_BYTES;
1555         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1556         scratch_addr += 2 * CACHELINE_BYTES;
1557         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1558
1559         intel_ring_emit(engine,
1560                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1561                         PIPE_CONTROL_WRITE_FLUSH |
1562                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1563                         PIPE_CONTROL_NOTIFY);
1564         intel_ring_emit(engine,
1565                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1566         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1567         intel_ring_emit(engine, 0);
1568         __intel_ring_advance(engine);
1569
1570         return 0;
1571 }
1572
1573 static void
1574 gen6_seqno_barrier(struct intel_engine_cs *engine)
1575 {
1576         /* Workaround to force correct ordering between irq and seqno writes on
1577          * ivb (and maybe also on snb) by reading from a CS register (like
1578          * ACTHD) before reading the status page.
1579          *
1580          * Note that this effectively stalls the read by the time it takes to
1581          * do a memory transaction, which more or less ensures that the write
1582          * from the GPU has sufficient time to invalidate the CPU cacheline.
1583          * Alternatively we could delay the interrupt from the CS ring to give
1584          * the write time to land, but that would incur a delay after every
1585          * batch i.e. much more frequent than a delay when waiting for the
1586          * interrupt (with the same net latency).
1587          */
1588         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1589         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1590 }
1591
1592 static u32
1593 ring_get_seqno(struct intel_engine_cs *engine)
1594 {
1595         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1596 }
1597
1598 static void
1599 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1600 {
1601         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1602 }
1603
1604 static u32
1605 pc_render_get_seqno(struct intel_engine_cs *engine)
1606 {
1607         return engine->scratch.cpu_page[0];
1608 }
1609
1610 static void
1611 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1612 {
1613         engine->scratch.cpu_page[0] = seqno;
1614 }
1615
1616 static bool
1617 gen5_ring_get_irq(struct intel_engine_cs *engine)
1618 {
1619         struct drm_device *dev = engine->dev;
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621         unsigned long flags;
1622
1623         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1624                 return false;
1625
1626         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1627         if (engine->irq_refcount++ == 0)
1628                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1629         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1630
1631         return true;
1632 }
1633
1634 static void
1635 gen5_ring_put_irq(struct intel_engine_cs *engine)
1636 {
1637         struct drm_device *dev = engine->dev;
1638         struct drm_i915_private *dev_priv = dev->dev_private;
1639         unsigned long flags;
1640
1641         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1642         if (--engine->irq_refcount == 0)
1643                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1644         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1645 }
1646
1647 static bool
1648 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1649 {
1650         struct drm_device *dev = engine->dev;
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652         unsigned long flags;
1653
1654         if (!intel_irqs_enabled(dev_priv))
1655                 return false;
1656
1657         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1658         if (engine->irq_refcount++ == 0) {
1659                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1660                 I915_WRITE(IMR, dev_priv->irq_mask);
1661                 POSTING_READ(IMR);
1662         }
1663         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1664
1665         return true;
1666 }
1667
1668 static void
1669 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1670 {
1671         struct drm_device *dev = engine->dev;
1672         struct drm_i915_private *dev_priv = dev->dev_private;
1673         unsigned long flags;
1674
1675         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1676         if (--engine->irq_refcount == 0) {
1677                 dev_priv->irq_mask |= engine->irq_enable_mask;
1678                 I915_WRITE(IMR, dev_priv->irq_mask);
1679                 POSTING_READ(IMR);
1680         }
1681         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1682 }
1683
1684 static bool
1685 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1686 {
1687         struct drm_device *dev = engine->dev;
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         unsigned long flags;
1690
1691         if (!intel_irqs_enabled(dev_priv))
1692                 return false;
1693
1694         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1695         if (engine->irq_refcount++ == 0) {
1696                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1697                 I915_WRITE16(IMR, dev_priv->irq_mask);
1698                 POSTING_READ16(IMR);
1699         }
1700         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1701
1702         return true;
1703 }
1704
1705 static void
1706 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1707 {
1708         struct drm_device *dev = engine->dev;
1709         struct drm_i915_private *dev_priv = dev->dev_private;
1710         unsigned long flags;
1711
1712         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1713         if (--engine->irq_refcount == 0) {
1714                 dev_priv->irq_mask |= engine->irq_enable_mask;
1715                 I915_WRITE16(IMR, dev_priv->irq_mask);
1716                 POSTING_READ16(IMR);
1717         }
1718         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1719 }
1720
1721 static int
1722 bsd_ring_flush(struct drm_i915_gem_request *req,
1723                u32     invalidate_domains,
1724                u32     flush_domains)
1725 {
1726         struct intel_engine_cs *engine = req->engine;
1727         int ret;
1728
1729         ret = intel_ring_begin(req, 2);
1730         if (ret)
1731                 return ret;
1732
1733         intel_ring_emit(engine, MI_FLUSH);
1734         intel_ring_emit(engine, MI_NOOP);
1735         intel_ring_advance(engine);
1736         return 0;
1737 }
1738
1739 static int
1740 i9xx_add_request(struct drm_i915_gem_request *req)
1741 {
1742         struct intel_engine_cs *engine = req->engine;
1743         int ret;
1744
1745         ret = intel_ring_begin(req, 4);
1746         if (ret)
1747                 return ret;
1748
1749         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1750         intel_ring_emit(engine,
1751                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1752         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1753         intel_ring_emit(engine, MI_USER_INTERRUPT);
1754         __intel_ring_advance(engine);
1755
1756         return 0;
1757 }
1758
1759 static bool
1760 gen6_ring_get_irq(struct intel_engine_cs *engine)
1761 {
1762         struct drm_device *dev = engine->dev;
1763         struct drm_i915_private *dev_priv = dev->dev_private;
1764         unsigned long flags;
1765
1766         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1767                 return false;
1768
1769         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1770         if (engine->irq_refcount++ == 0) {
1771                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1772                         I915_WRITE_IMR(engine,
1773                                        ~(engine->irq_enable_mask |
1774                                          GT_PARITY_ERROR(dev)));
1775                 else
1776                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1777                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1778         }
1779         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1780
1781         return true;
1782 }
1783
1784 static void
1785 gen6_ring_put_irq(struct intel_engine_cs *engine)
1786 {
1787         struct drm_device *dev = engine->dev;
1788         struct drm_i915_private *dev_priv = dev->dev_private;
1789         unsigned long flags;
1790
1791         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1792         if (--engine->irq_refcount == 0) {
1793                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1794                         I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1795                 else
1796                         I915_WRITE_IMR(engine, ~0);
1797                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1798         }
1799         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1800 }
1801
1802 static bool
1803 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1804 {
1805         struct drm_device *dev = engine->dev;
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         unsigned long flags;
1808
1809         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1810                 return false;
1811
1812         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1813         if (engine->irq_refcount++ == 0) {
1814                 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1815                 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1816         }
1817         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1818
1819         return true;
1820 }
1821
1822 static void
1823 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1824 {
1825         struct drm_device *dev = engine->dev;
1826         struct drm_i915_private *dev_priv = dev->dev_private;
1827         unsigned long flags;
1828
1829         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1830         if (--engine->irq_refcount == 0) {
1831                 I915_WRITE_IMR(engine, ~0);
1832                 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1833         }
1834         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1835 }
1836
1837 static bool
1838 gen8_ring_get_irq(struct intel_engine_cs *engine)
1839 {
1840         struct drm_device *dev = engine->dev;
1841         struct drm_i915_private *dev_priv = dev->dev_private;
1842         unsigned long flags;
1843
1844         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1845                 return false;
1846
1847         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1848         if (engine->irq_refcount++ == 0) {
1849                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1850                         I915_WRITE_IMR(engine,
1851                                        ~(engine->irq_enable_mask |
1852                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1853                 } else {
1854                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1855                 }
1856                 POSTING_READ(RING_IMR(engine->mmio_base));
1857         }
1858         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1859
1860         return true;
1861 }
1862
1863 static void
1864 gen8_ring_put_irq(struct intel_engine_cs *engine)
1865 {
1866         struct drm_device *dev = engine->dev;
1867         struct drm_i915_private *dev_priv = dev->dev_private;
1868         unsigned long flags;
1869
1870         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1871         if (--engine->irq_refcount == 0) {
1872                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1873                         I915_WRITE_IMR(engine,
1874                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1875                 } else {
1876                         I915_WRITE_IMR(engine, ~0);
1877                 }
1878                 POSTING_READ(RING_IMR(engine->mmio_base));
1879         }
1880         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1881 }
1882
1883 static int
1884 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1885                          u64 offset, u32 length,
1886                          unsigned dispatch_flags)
1887 {
1888         struct intel_engine_cs *engine = req->engine;
1889         int ret;
1890
1891         ret = intel_ring_begin(req, 2);
1892         if (ret)
1893                 return ret;
1894
1895         intel_ring_emit(engine,
1896                         MI_BATCH_BUFFER_START |
1897                         MI_BATCH_GTT |
1898                         (dispatch_flags & I915_DISPATCH_SECURE ?
1899                          0 : MI_BATCH_NON_SECURE_I965));
1900         intel_ring_emit(engine, offset);
1901         intel_ring_advance(engine);
1902
1903         return 0;
1904 }
1905
1906 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1907 #define I830_BATCH_LIMIT (256*1024)
1908 #define I830_TLB_ENTRIES (2)
1909 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1910 static int
1911 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1912                          u64 offset, u32 len,
1913                          unsigned dispatch_flags)
1914 {
1915         struct intel_engine_cs *engine = req->engine;
1916         u32 cs_offset = engine->scratch.gtt_offset;
1917         int ret;
1918
1919         ret = intel_ring_begin(req, 6);
1920         if (ret)
1921                 return ret;
1922
1923         /* Evict the invalid PTE TLBs */
1924         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1925         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1926         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1927         intel_ring_emit(engine, cs_offset);
1928         intel_ring_emit(engine, 0xdeadbeef);
1929         intel_ring_emit(engine, MI_NOOP);
1930         intel_ring_advance(engine);
1931
1932         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1933                 if (len > I830_BATCH_LIMIT)
1934                         return -ENOSPC;
1935
1936                 ret = intel_ring_begin(req, 6 + 2);
1937                 if (ret)
1938                         return ret;
1939
1940                 /* Blit the batch (which has now all relocs applied) to the
1941                  * stable batch scratch bo area (so that the CS never
1942                  * stumbles over its tlb invalidation bug) ...
1943                  */
1944                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1945                 intel_ring_emit(engine,
1946                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1947                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1948                 intel_ring_emit(engine, cs_offset);
1949                 intel_ring_emit(engine, 4096);
1950                 intel_ring_emit(engine, offset);
1951
1952                 intel_ring_emit(engine, MI_FLUSH);
1953                 intel_ring_emit(engine, MI_NOOP);
1954                 intel_ring_advance(engine);
1955
1956                 /* ... and execute it. */
1957                 offset = cs_offset;
1958         }
1959
1960         ret = intel_ring_begin(req, 2);
1961         if (ret)
1962                 return ret;
1963
1964         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1965         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1966                                           0 : MI_BATCH_NON_SECURE));
1967         intel_ring_advance(engine);
1968
1969         return 0;
1970 }
1971
1972 static int
1973 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1974                          u64 offset, u32 len,
1975                          unsigned dispatch_flags)
1976 {
1977         struct intel_engine_cs *engine = req->engine;
1978         int ret;
1979
1980         ret = intel_ring_begin(req, 2);
1981         if (ret)
1982                 return ret;
1983
1984         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1985         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1986                                           0 : MI_BATCH_NON_SECURE));
1987         intel_ring_advance(engine);
1988
1989         return 0;
1990 }
1991
1992 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1993 {
1994         struct drm_i915_private *dev_priv = to_i915(engine->dev);
1995
1996         if (!dev_priv->status_page_dmah)
1997                 return;
1998
1999         drm_pci_free(engine->dev, dev_priv->status_page_dmah);
2000         engine->status_page.page_addr = NULL;
2001 }
2002
2003 static void cleanup_status_page(struct intel_engine_cs *engine)
2004 {
2005         struct drm_i915_gem_object *obj;
2006
2007         obj = engine->status_page.obj;
2008         if (obj == NULL)
2009                 return;
2010
2011         kunmap(sg_page(obj->pages->sgl));
2012         i915_gem_object_ggtt_unpin(obj);
2013         drm_gem_object_unreference(&obj->base);
2014         engine->status_page.obj = NULL;
2015 }
2016
2017 static int init_status_page(struct intel_engine_cs *engine)
2018 {
2019         struct drm_i915_gem_object *obj = engine->status_page.obj;
2020
2021         if (obj == NULL) {
2022                 unsigned flags;
2023                 int ret;
2024
2025                 obj = i915_gem_alloc_object(engine->dev, 4096);
2026                 if (obj == NULL) {
2027                         DRM_ERROR("Failed to allocate status page\n");
2028                         return -ENOMEM;
2029                 }
2030
2031                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2032                 if (ret)
2033                         goto err_unref;
2034
2035                 flags = 0;
2036                 if (!HAS_LLC(engine->dev))
2037                         /* On g33, we cannot place HWS above 256MiB, so
2038                          * restrict its pinning to the low mappable arena.
2039                          * Though this restriction is not documented for
2040                          * gen4, gen5, or byt, they also behave similarly
2041                          * and hang if the HWS is placed at the top of the
2042                          * GTT. To generalise, it appears that all !llc
2043                          * platforms have issues with us placing the HWS
2044                          * above the mappable region (even though we never
2045                          * actualy map it).
2046                          */
2047                         flags |= PIN_MAPPABLE;
2048                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2049                 if (ret) {
2050 err_unref:
2051                         drm_gem_object_unreference(&obj->base);
2052                         return ret;
2053                 }
2054
2055                 engine->status_page.obj = obj;
2056         }
2057
2058         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2059         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2060         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2061
2062         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2063                         engine->name, engine->status_page.gfx_addr);
2064
2065         return 0;
2066 }
2067
2068 static int init_phys_status_page(struct intel_engine_cs *engine)
2069 {
2070         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2071
2072         if (!dev_priv->status_page_dmah) {
2073                 dev_priv->status_page_dmah =
2074                         drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2075                 if (!dev_priv->status_page_dmah)
2076                         return -ENOMEM;
2077         }
2078
2079         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2080         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2081
2082         return 0;
2083 }
2084
2085 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2086 {
2087         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2088                 i915_gem_object_unpin_map(ringbuf->obj);
2089         else
2090                 iounmap(ringbuf->virtual_start);
2091         ringbuf->virtual_start = NULL;
2092         ringbuf->vma = NULL;
2093         i915_gem_object_ggtt_unpin(ringbuf->obj);
2094 }
2095
2096 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2097                                      struct intel_ringbuffer *ringbuf)
2098 {
2099         struct drm_i915_private *dev_priv = to_i915(dev);
2100         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2101         struct drm_i915_gem_object *obj = ringbuf->obj;
2102         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2103         unsigned flags = PIN_OFFSET_BIAS | 4096;
2104         void *addr;
2105         int ret;
2106
2107         if (HAS_LLC(dev_priv) && !obj->stolen) {
2108                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2109                 if (ret)
2110                         return ret;
2111
2112                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2113                 if (ret)
2114                         goto err_unpin;
2115
2116                 addr = i915_gem_object_pin_map(obj);
2117                 if (IS_ERR(addr)) {
2118                         ret = PTR_ERR(addr);
2119                         goto err_unpin;
2120                 }
2121         } else {
2122                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2123                                             flags | PIN_MAPPABLE);
2124                 if (ret)
2125                         return ret;
2126
2127                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2128                 if (ret)
2129                         goto err_unpin;
2130
2131                 /* Access through the GTT requires the device to be awake. */
2132                 assert_rpm_wakelock_held(dev_priv);
2133
2134                 addr = ioremap_wc(ggtt->mappable_base +
2135                                   i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2136                 if (addr == NULL) {
2137                         ret = -ENOMEM;
2138                         goto err_unpin;
2139                 }
2140         }
2141
2142         ringbuf->virtual_start = addr;
2143         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2144         return 0;
2145
2146 err_unpin:
2147         i915_gem_object_ggtt_unpin(obj);
2148         return ret;
2149 }
2150
2151 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2152 {
2153         drm_gem_object_unreference(&ringbuf->obj->base);
2154         ringbuf->obj = NULL;
2155 }
2156
2157 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2158                                       struct intel_ringbuffer *ringbuf)
2159 {
2160         struct drm_i915_gem_object *obj;
2161
2162         obj = NULL;
2163         if (!HAS_LLC(dev))
2164                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2165         if (obj == NULL)
2166                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2167         if (obj == NULL)
2168                 return -ENOMEM;
2169
2170         /* mark ring buffers as read-only from GPU side by default */
2171         obj->gt_ro = 1;
2172
2173         ringbuf->obj = obj;
2174
2175         return 0;
2176 }
2177
2178 struct intel_ringbuffer *
2179 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2180 {
2181         struct intel_ringbuffer *ring;
2182         int ret;
2183
2184         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2185         if (ring == NULL) {
2186                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2187                                  engine->name);
2188                 return ERR_PTR(-ENOMEM);
2189         }
2190
2191         ring->engine = engine;
2192         list_add(&ring->link, &engine->buffers);
2193
2194         ring->size = size;
2195         /* Workaround an erratum on the i830 which causes a hang if
2196          * the TAIL pointer points to within the last 2 cachelines
2197          * of the buffer.
2198          */
2199         ring->effective_size = size;
2200         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2201                 ring->effective_size -= 2 * CACHELINE_BYTES;
2202
2203         ring->last_retired_head = -1;
2204         intel_ring_update_space(ring);
2205
2206         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2207         if (ret) {
2208                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2209                                  engine->name, ret);
2210                 list_del(&ring->link);
2211                 kfree(ring);
2212                 return ERR_PTR(ret);
2213         }
2214
2215         return ring;
2216 }
2217
2218 void
2219 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2220 {
2221         intel_destroy_ringbuffer_obj(ring);
2222         list_del(&ring->link);
2223         kfree(ring);
2224 }
2225
2226 static int intel_init_ring_buffer(struct drm_device *dev,
2227                                   struct intel_engine_cs *engine)
2228 {
2229         struct intel_ringbuffer *ringbuf;
2230         int ret;
2231
2232         WARN_ON(engine->buffer);
2233
2234         engine->dev = dev;
2235         INIT_LIST_HEAD(&engine->active_list);
2236         INIT_LIST_HEAD(&engine->request_list);
2237         INIT_LIST_HEAD(&engine->execlist_queue);
2238         INIT_LIST_HEAD(&engine->buffers);
2239         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2240         memset(engine->semaphore.sync_seqno, 0,
2241                sizeof(engine->semaphore.sync_seqno));
2242
2243         init_waitqueue_head(&engine->irq_queue);
2244
2245         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2246         if (IS_ERR(ringbuf)) {
2247                 ret = PTR_ERR(ringbuf);
2248                 goto error;
2249         }
2250         engine->buffer = ringbuf;
2251
2252         if (I915_NEED_GFX_HWS(dev)) {
2253                 ret = init_status_page(engine);
2254                 if (ret)
2255                         goto error;
2256         } else {
2257                 WARN_ON(engine->id != RCS);
2258                 ret = init_phys_status_page(engine);
2259                 if (ret)
2260                         goto error;
2261         }
2262
2263         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2264         if (ret) {
2265                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2266                                 engine->name, ret);
2267                 intel_destroy_ringbuffer_obj(ringbuf);
2268                 goto error;
2269         }
2270
2271         ret = i915_cmd_parser_init_ring(engine);
2272         if (ret)
2273                 goto error;
2274
2275         return 0;
2276
2277 error:
2278         intel_cleanup_engine(engine);
2279         return ret;
2280 }
2281
2282 void intel_cleanup_engine(struct intel_engine_cs *engine)
2283 {
2284         struct drm_i915_private *dev_priv;
2285
2286         if (!intel_engine_initialized(engine))
2287                 return;
2288
2289         dev_priv = to_i915(engine->dev);
2290
2291         if (engine->buffer) {
2292                 intel_stop_engine(engine);
2293                 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2294
2295                 intel_unpin_ringbuffer_obj(engine->buffer);
2296                 intel_ringbuffer_free(engine->buffer);
2297                 engine->buffer = NULL;
2298         }
2299
2300         if (engine->cleanup)
2301                 engine->cleanup(engine);
2302
2303         if (I915_NEED_GFX_HWS(engine->dev)) {
2304                 cleanup_status_page(engine);
2305         } else {
2306                 WARN_ON(engine->id != RCS);
2307                 cleanup_phys_status_page(engine);
2308         }
2309
2310         i915_cmd_parser_fini_ring(engine);
2311         i915_gem_batch_pool_fini(&engine->batch_pool);
2312         engine->dev = NULL;
2313 }
2314
2315 static int ring_wait_for_space(struct intel_engine_cs *engine, int n)
2316 {
2317         struct intel_ringbuffer *ringbuf = engine->buffer;
2318         struct drm_i915_gem_request *request;
2319         unsigned space;
2320         int ret;
2321
2322         if (intel_ring_space(ringbuf) >= n)
2323                 return 0;
2324
2325         /* The whole point of reserving space is to not wait! */
2326         WARN_ON(ringbuf->reserved_in_use);
2327
2328         list_for_each_entry(request, &engine->request_list, list) {
2329                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2330                                            ringbuf->size);
2331                 if (space >= n)
2332                         break;
2333         }
2334
2335         if (WARN_ON(&request->list == &engine->request_list))
2336                 return -ENOSPC;
2337
2338         ret = i915_wait_request(request);
2339         if (ret)
2340                 return ret;
2341
2342         ringbuf->space = space;
2343         return 0;
2344 }
2345
2346 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2347 {
2348         uint32_t __iomem *virt;
2349         int rem = ringbuf->size - ringbuf->tail;
2350
2351         virt = ringbuf->virtual_start + ringbuf->tail;
2352         rem /= 4;
2353         while (rem--)
2354                 iowrite32(MI_NOOP, virt++);
2355
2356         ringbuf->tail = 0;
2357         intel_ring_update_space(ringbuf);
2358 }
2359
2360 int intel_engine_idle(struct intel_engine_cs *engine)
2361 {
2362         struct drm_i915_gem_request *req;
2363
2364         /* Wait upon the last request to be completed */
2365         if (list_empty(&engine->request_list))
2366                 return 0;
2367
2368         req = list_entry(engine->request_list.prev,
2369                          struct drm_i915_gem_request,
2370                          list);
2371
2372         /* Make sure we do not trigger any retires */
2373         return __i915_wait_request(req,
2374                                    req->i915->mm.interruptible,
2375                                    NULL, NULL);
2376 }
2377
2378 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2379 {
2380         request->ringbuf = request->engine->buffer;
2381         return 0;
2382 }
2383
2384 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2385 {
2386         /*
2387          * The first call merely notes the reserve request and is common for
2388          * all back ends. The subsequent localised _begin() call actually
2389          * ensures that the reservation is available. Without the begin, if
2390          * the request creator immediately submitted the request without
2391          * adding any commands to it then there might not actually be
2392          * sufficient room for the submission commands.
2393          */
2394         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2395
2396         return intel_ring_begin(request, 0);
2397 }
2398
2399 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2400 {
2401         WARN_ON(ringbuf->reserved_size);
2402         WARN_ON(ringbuf->reserved_in_use);
2403
2404         ringbuf->reserved_size = size;
2405 }
2406
2407 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2408 {
2409         WARN_ON(ringbuf->reserved_in_use);
2410
2411         ringbuf->reserved_size   = 0;
2412         ringbuf->reserved_in_use = false;
2413 }
2414
2415 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2416 {
2417         WARN_ON(ringbuf->reserved_in_use);
2418
2419         ringbuf->reserved_in_use = true;
2420         ringbuf->reserved_tail   = ringbuf->tail;
2421 }
2422
2423 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2424 {
2425         WARN_ON(!ringbuf->reserved_in_use);
2426         if (ringbuf->tail > ringbuf->reserved_tail) {
2427                 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2428                      "request reserved size too small: %d vs %d!\n",
2429                      ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2430         } else {
2431                 /*
2432                  * The ring was wrapped while the reserved space was in use.
2433                  * That means that some unknown amount of the ring tail was
2434                  * no-op filled and skipped. Thus simply adding the ring size
2435                  * to the tail and doing the above space check will not work.
2436                  * Rather than attempt to track how much tail was skipped,
2437                  * it is much simpler to say that also skipping the sanity
2438                  * check every once in a while is not a big issue.
2439                  */
2440         }
2441
2442         ringbuf->reserved_size   = 0;
2443         ringbuf->reserved_in_use = false;
2444 }
2445
2446 static int __intel_ring_prepare(struct intel_engine_cs *engine, int bytes)
2447 {
2448         struct intel_ringbuffer *ringbuf = engine->buffer;
2449         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2450         int remain_actual = ringbuf->size - ringbuf->tail;
2451         int ret, total_bytes, wait_bytes = 0;
2452         bool need_wrap = false;
2453
2454         if (ringbuf->reserved_in_use)
2455                 total_bytes = bytes;
2456         else
2457                 total_bytes = bytes + ringbuf->reserved_size;
2458
2459         if (unlikely(bytes > remain_usable)) {
2460                 /*
2461                  * Not enough space for the basic request. So need to flush
2462                  * out the remainder and then wait for base + reserved.
2463                  */
2464                 wait_bytes = remain_actual + total_bytes;
2465                 need_wrap = true;
2466         } else {
2467                 if (unlikely(total_bytes > remain_usable)) {
2468                         /*
2469                          * The base request will fit but the reserved space
2470                          * falls off the end. So don't need an immediate wrap
2471                          * and only need to effectively wait for the reserved
2472                          * size space from the start of ringbuffer.
2473                          */
2474                         wait_bytes = remain_actual + ringbuf->reserved_size;
2475                 } else if (total_bytes > ringbuf->space) {
2476                         /* No wrapping required, just waiting. */
2477                         wait_bytes = total_bytes;
2478                 }
2479         }
2480
2481         if (wait_bytes) {
2482                 ret = ring_wait_for_space(engine, wait_bytes);
2483                 if (unlikely(ret))
2484                         return ret;
2485
2486                 if (need_wrap)
2487                         __wrap_ring_buffer(ringbuf);
2488         }
2489
2490         return 0;
2491 }
2492
2493 int intel_ring_begin(struct drm_i915_gem_request *req,
2494                      int num_dwords)
2495 {
2496         struct intel_engine_cs *engine = req->engine;
2497         int ret;
2498
2499         ret = __intel_ring_prepare(engine, num_dwords * sizeof(uint32_t));
2500         if (ret)
2501                 return ret;
2502
2503         engine->buffer->space -= num_dwords * sizeof(uint32_t);
2504         return 0;
2505 }
2506
2507 /* Align the ring tail to a cacheline boundary */
2508 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2509 {
2510         struct intel_engine_cs *engine = req->engine;
2511         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2512         int ret;
2513
2514         if (num_dwords == 0)
2515                 return 0;
2516
2517         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2518         ret = intel_ring_begin(req, num_dwords);
2519         if (ret)
2520                 return ret;
2521
2522         while (num_dwords--)
2523                 intel_ring_emit(engine, MI_NOOP);
2524
2525         intel_ring_advance(engine);
2526
2527         return 0;
2528 }
2529
2530 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2531 {
2532         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2533
2534         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2535          * so long as the semaphore value in the register/page is greater
2536          * than the sync value), so whenever we reset the seqno,
2537          * so long as we reset the tracking semaphore value to 0, it will
2538          * always be before the next request's seqno. If we don't reset
2539          * the semaphore value, then when the seqno moves backwards all
2540          * future waits will complete instantly (causing rendering corruption).
2541          */
2542         if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
2543                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2544                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2545                 if (HAS_VEBOX(dev_priv))
2546                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2547         }
2548         if (dev_priv->semaphore_obj) {
2549                 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2550                 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2551                 void *semaphores = kmap(page);
2552                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2553                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2554                 kunmap(page);
2555         }
2556         memset(engine->semaphore.sync_seqno, 0,
2557                sizeof(engine->semaphore.sync_seqno));
2558
2559         engine->set_seqno(engine, seqno);
2560         engine->last_submitted_seqno = seqno;
2561
2562         engine->hangcheck.seqno = seqno;
2563 }
2564
2565 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2566                                      u32 value)
2567 {
2568         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2569
2570        /* Every tail move must follow the sequence below */
2571
2572         /* Disable notification that the ring is IDLE. The GT
2573          * will then assume that it is busy and bring it out of rc6.
2574          */
2575         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2576                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2577
2578         /* Clear the context id. Here be magic! */
2579         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2580
2581         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2582         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2583                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2584                      50))
2585                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2586
2587         /* Now that the ring is fully powered up, update the tail */
2588         I915_WRITE_TAIL(engine, value);
2589         POSTING_READ(RING_TAIL(engine->mmio_base));
2590
2591         /* Let the ring send IDLE messages to the GT again,
2592          * and so let it sleep to conserve power when idle.
2593          */
2594         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2595                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2596 }
2597
2598 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2599                                u32 invalidate, u32 flush)
2600 {
2601         struct intel_engine_cs *engine = req->engine;
2602         uint32_t cmd;
2603         int ret;
2604
2605         ret = intel_ring_begin(req, 4);
2606         if (ret)
2607                 return ret;
2608
2609         cmd = MI_FLUSH_DW;
2610         if (INTEL_INFO(engine->dev)->gen >= 8)
2611                 cmd += 1;
2612
2613         /* We always require a command barrier so that subsequent
2614          * commands, such as breadcrumb interrupts, are strictly ordered
2615          * wrt the contents of the write cache being flushed to memory
2616          * (and thus being coherent from the CPU).
2617          */
2618         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2619
2620         /*
2621          * Bspec vol 1c.5 - video engine command streamer:
2622          * "If ENABLED, all TLBs will be invalidated once the flush
2623          * operation is complete. This bit is only valid when the
2624          * Post-Sync Operation field is a value of 1h or 3h."
2625          */
2626         if (invalidate & I915_GEM_GPU_DOMAINS)
2627                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2628
2629         intel_ring_emit(engine, cmd);
2630         intel_ring_emit(engine,
2631                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2632         if (INTEL_INFO(engine->dev)->gen >= 8) {
2633                 intel_ring_emit(engine, 0); /* upper addr */
2634                 intel_ring_emit(engine, 0); /* value */
2635         } else  {
2636                 intel_ring_emit(engine, 0);
2637                 intel_ring_emit(engine, MI_NOOP);
2638         }
2639         intel_ring_advance(engine);
2640         return 0;
2641 }
2642
2643 static int
2644 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2645                               u64 offset, u32 len,
2646                               unsigned dispatch_flags)
2647 {
2648         struct intel_engine_cs *engine = req->engine;
2649         bool ppgtt = USES_PPGTT(engine->dev) &&
2650                         !(dispatch_flags & I915_DISPATCH_SECURE);
2651         int ret;
2652
2653         ret = intel_ring_begin(req, 4);
2654         if (ret)
2655                 return ret;
2656
2657         /* FIXME(BDW): Address space and security selectors. */
2658         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2659                         (dispatch_flags & I915_DISPATCH_RS ?
2660                          MI_BATCH_RESOURCE_STREAMER : 0));
2661         intel_ring_emit(engine, lower_32_bits(offset));
2662         intel_ring_emit(engine, upper_32_bits(offset));
2663         intel_ring_emit(engine, MI_NOOP);
2664         intel_ring_advance(engine);
2665
2666         return 0;
2667 }
2668
2669 static int
2670 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2671                              u64 offset, u32 len,
2672                              unsigned dispatch_flags)
2673 {
2674         struct intel_engine_cs *engine = req->engine;
2675         int ret;
2676
2677         ret = intel_ring_begin(req, 2);
2678         if (ret)
2679                 return ret;
2680
2681         intel_ring_emit(engine,
2682                         MI_BATCH_BUFFER_START |
2683                         (dispatch_flags & I915_DISPATCH_SECURE ?
2684                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2685                         (dispatch_flags & I915_DISPATCH_RS ?
2686                          MI_BATCH_RESOURCE_STREAMER : 0));
2687         /* bit0-7 is the length on GEN6+ */
2688         intel_ring_emit(engine, offset);
2689         intel_ring_advance(engine);
2690
2691         return 0;
2692 }
2693
2694 static int
2695 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2696                               u64 offset, u32 len,
2697                               unsigned dispatch_flags)
2698 {
2699         struct intel_engine_cs *engine = req->engine;
2700         int ret;
2701
2702         ret = intel_ring_begin(req, 2);
2703         if (ret)
2704                 return ret;
2705
2706         intel_ring_emit(engine,
2707                         MI_BATCH_BUFFER_START |
2708                         (dispatch_flags & I915_DISPATCH_SECURE ?
2709                          0 : MI_BATCH_NON_SECURE_I965));
2710         /* bit0-7 is the length on GEN6+ */
2711         intel_ring_emit(engine, offset);
2712         intel_ring_advance(engine);
2713
2714         return 0;
2715 }
2716
2717 /* Blitter support (SandyBridge+) */
2718
2719 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2720                            u32 invalidate, u32 flush)
2721 {
2722         struct intel_engine_cs *engine = req->engine;
2723         struct drm_device *dev = engine->dev;
2724         uint32_t cmd;
2725         int ret;
2726
2727         ret = intel_ring_begin(req, 4);
2728         if (ret)
2729                 return ret;
2730
2731         cmd = MI_FLUSH_DW;
2732         if (INTEL_INFO(dev)->gen >= 8)
2733                 cmd += 1;
2734
2735         /* We always require a command barrier so that subsequent
2736          * commands, such as breadcrumb interrupts, are strictly ordered
2737          * wrt the contents of the write cache being flushed to memory
2738          * (and thus being coherent from the CPU).
2739          */
2740         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2741
2742         /*
2743          * Bspec vol 1c.3 - blitter engine command streamer:
2744          * "If ENABLED, all TLBs will be invalidated once the flush
2745          * operation is complete. This bit is only valid when the
2746          * Post-Sync Operation field is a value of 1h or 3h."
2747          */
2748         if (invalidate & I915_GEM_DOMAIN_RENDER)
2749                 cmd |= MI_INVALIDATE_TLB;
2750         intel_ring_emit(engine, cmd);
2751         intel_ring_emit(engine,
2752                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2753         if (INTEL_INFO(dev)->gen >= 8) {
2754                 intel_ring_emit(engine, 0); /* upper addr */
2755                 intel_ring_emit(engine, 0); /* value */
2756         } else  {
2757                 intel_ring_emit(engine, 0);
2758                 intel_ring_emit(engine, MI_NOOP);
2759         }
2760         intel_ring_advance(engine);
2761
2762         return 0;
2763 }
2764
2765 int intel_init_render_ring_buffer(struct drm_device *dev)
2766 {
2767         struct drm_i915_private *dev_priv = dev->dev_private;
2768         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2769         struct drm_i915_gem_object *obj;
2770         int ret;
2771
2772         engine->name = "render ring";
2773         engine->id = RCS;
2774         engine->exec_id = I915_EXEC_RENDER;
2775         engine->mmio_base = RENDER_RING_BASE;
2776
2777         if (INTEL_INFO(dev)->gen >= 8) {
2778                 if (i915_semaphore_is_enabled(dev)) {
2779                         obj = i915_gem_alloc_object(dev, 4096);
2780                         if (obj == NULL) {
2781                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2782                                 i915.semaphores = 0;
2783                         } else {
2784                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2785                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2786                                 if (ret != 0) {
2787                                         drm_gem_object_unreference(&obj->base);
2788                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2789                                         i915.semaphores = 0;
2790                                 } else
2791                                         dev_priv->semaphore_obj = obj;
2792                         }
2793                 }
2794
2795                 engine->init_context = intel_rcs_ctx_init;
2796                 engine->add_request = gen6_add_request;
2797                 engine->flush = gen8_render_ring_flush;
2798                 engine->irq_get = gen8_ring_get_irq;
2799                 engine->irq_put = gen8_ring_put_irq;
2800                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2801                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2802                 engine->get_seqno = ring_get_seqno;
2803                 engine->set_seqno = ring_set_seqno;
2804                 if (i915_semaphore_is_enabled(dev)) {
2805                         WARN_ON(!dev_priv->semaphore_obj);
2806                         engine->semaphore.sync_to = gen8_ring_sync;
2807                         engine->semaphore.signal = gen8_rcs_signal;
2808                         GEN8_RING_SEMAPHORE_INIT(engine);
2809                 }
2810         } else if (INTEL_INFO(dev)->gen >= 6) {
2811                 engine->init_context = intel_rcs_ctx_init;
2812                 engine->add_request = gen6_add_request;
2813                 engine->flush = gen7_render_ring_flush;
2814                 if (INTEL_INFO(dev)->gen == 6)
2815                         engine->flush = gen6_render_ring_flush;
2816                 engine->irq_get = gen6_ring_get_irq;
2817                 engine->irq_put = gen6_ring_put_irq;
2818                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2819                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2820                 engine->get_seqno = ring_get_seqno;
2821                 engine->set_seqno = ring_set_seqno;
2822                 if (i915_semaphore_is_enabled(dev)) {
2823                         engine->semaphore.sync_to = gen6_ring_sync;
2824                         engine->semaphore.signal = gen6_signal;
2825                         /*
2826                          * The current semaphore is only applied on pre-gen8
2827                          * platform.  And there is no VCS2 ring on the pre-gen8
2828                          * platform. So the semaphore between RCS and VCS2 is
2829                          * initialized as INVALID.  Gen8 will initialize the
2830                          * sema between VCS2 and RCS later.
2831                          */
2832                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2833                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2834                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2835                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2836                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2837                         engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2838                         engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2839                         engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2840                         engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2841                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2842                 }
2843         } else if (IS_GEN5(dev)) {
2844                 engine->add_request = pc_render_add_request;
2845                 engine->flush = gen4_render_ring_flush;
2846                 engine->get_seqno = pc_render_get_seqno;
2847                 engine->set_seqno = pc_render_set_seqno;
2848                 engine->irq_get = gen5_ring_get_irq;
2849                 engine->irq_put = gen5_ring_put_irq;
2850                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2851                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2852         } else {
2853                 engine->add_request = i9xx_add_request;
2854                 if (INTEL_INFO(dev)->gen < 4)
2855                         engine->flush = gen2_render_ring_flush;
2856                 else
2857                         engine->flush = gen4_render_ring_flush;
2858                 engine->get_seqno = ring_get_seqno;
2859                 engine->set_seqno = ring_set_seqno;
2860                 if (IS_GEN2(dev)) {
2861                         engine->irq_get = i8xx_ring_get_irq;
2862                         engine->irq_put = i8xx_ring_put_irq;
2863                 } else {
2864                         engine->irq_get = i9xx_ring_get_irq;
2865                         engine->irq_put = i9xx_ring_put_irq;
2866                 }
2867                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2868         }
2869         engine->write_tail = ring_write_tail;
2870
2871         if (IS_HASWELL(dev))
2872                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2873         else if (IS_GEN8(dev))
2874                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2875         else if (INTEL_INFO(dev)->gen >= 6)
2876                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2877         else if (INTEL_INFO(dev)->gen >= 4)
2878                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2879         else if (IS_I830(dev) || IS_845G(dev))
2880                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2881         else
2882                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2883         engine->init_hw = init_render_ring;
2884         engine->cleanup = render_ring_cleanup;
2885
2886         /* Workaround batchbuffer to combat CS tlb bug. */
2887         if (HAS_BROKEN_CS_TLB(dev)) {
2888                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2889                 if (obj == NULL) {
2890                         DRM_ERROR("Failed to allocate batch bo\n");
2891                         return -ENOMEM;
2892                 }
2893
2894                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2895                 if (ret != 0) {
2896                         drm_gem_object_unreference(&obj->base);
2897                         DRM_ERROR("Failed to ping batch bo\n");
2898                         return ret;
2899                 }
2900
2901                 engine->scratch.obj = obj;
2902                 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2903         }
2904
2905         ret = intel_init_ring_buffer(dev, engine);
2906         if (ret)
2907                 return ret;
2908
2909         if (INTEL_INFO(dev)->gen >= 5) {
2910                 ret = intel_init_pipe_control(engine);
2911                 if (ret)
2912                         return ret;
2913         }
2914
2915         return 0;
2916 }
2917
2918 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2919 {
2920         struct drm_i915_private *dev_priv = dev->dev_private;
2921         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2922
2923         engine->name = "bsd ring";
2924         engine->id = VCS;
2925         engine->exec_id = I915_EXEC_BSD;
2926
2927         engine->write_tail = ring_write_tail;
2928         if (INTEL_INFO(dev)->gen >= 6) {
2929                 engine->mmio_base = GEN6_BSD_RING_BASE;
2930                 /* gen6 bsd needs a special wa for tail updates */
2931                 if (IS_GEN6(dev))
2932                         engine->write_tail = gen6_bsd_ring_write_tail;
2933                 engine->flush = gen6_bsd_ring_flush;
2934                 engine->add_request = gen6_add_request;
2935                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2936                 engine->get_seqno = ring_get_seqno;
2937                 engine->set_seqno = ring_set_seqno;
2938                 if (INTEL_INFO(dev)->gen >= 8) {
2939                         engine->irq_enable_mask =
2940                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2941                         engine->irq_get = gen8_ring_get_irq;
2942                         engine->irq_put = gen8_ring_put_irq;
2943                         engine->dispatch_execbuffer =
2944                                 gen8_ring_dispatch_execbuffer;
2945                         if (i915_semaphore_is_enabled(dev)) {
2946                                 engine->semaphore.sync_to = gen8_ring_sync;
2947                                 engine->semaphore.signal = gen8_xcs_signal;
2948                                 GEN8_RING_SEMAPHORE_INIT(engine);
2949                         }
2950                 } else {
2951                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2952                         engine->irq_get = gen6_ring_get_irq;
2953                         engine->irq_put = gen6_ring_put_irq;
2954                         engine->dispatch_execbuffer =
2955                                 gen6_ring_dispatch_execbuffer;
2956                         if (i915_semaphore_is_enabled(dev)) {
2957                                 engine->semaphore.sync_to = gen6_ring_sync;
2958                                 engine->semaphore.signal = gen6_signal;
2959                                 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2960                                 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2961                                 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2962                                 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2963                                 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2964                                 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2965                                 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2966                                 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2967                                 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2968                                 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2969                         }
2970                 }
2971         } else {
2972                 engine->mmio_base = BSD_RING_BASE;
2973                 engine->flush = bsd_ring_flush;
2974                 engine->add_request = i9xx_add_request;
2975                 engine->get_seqno = ring_get_seqno;
2976                 engine->set_seqno = ring_set_seqno;
2977                 if (IS_GEN5(dev)) {
2978                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2979                         engine->irq_get = gen5_ring_get_irq;
2980                         engine->irq_put = gen5_ring_put_irq;
2981                 } else {
2982                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2983                         engine->irq_get = i9xx_ring_get_irq;
2984                         engine->irq_put = i9xx_ring_put_irq;
2985                 }
2986                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2987         }
2988         engine->init_hw = init_ring_common;
2989
2990         return intel_init_ring_buffer(dev, engine);
2991 }
2992
2993 /**
2994  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2995  */
2996 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2997 {
2998         struct drm_i915_private *dev_priv = dev->dev_private;
2999         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
3000
3001         engine->name = "bsd2 ring";
3002         engine->id = VCS2;
3003         engine->exec_id = I915_EXEC_BSD;
3004
3005         engine->write_tail = ring_write_tail;
3006         engine->mmio_base = GEN8_BSD2_RING_BASE;
3007         engine->flush = gen6_bsd_ring_flush;
3008         engine->add_request = gen6_add_request;
3009         engine->irq_seqno_barrier = gen6_seqno_barrier;
3010         engine->get_seqno = ring_get_seqno;
3011         engine->set_seqno = ring_set_seqno;
3012         engine->irq_enable_mask =
3013                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3014         engine->irq_get = gen8_ring_get_irq;
3015         engine->irq_put = gen8_ring_put_irq;
3016         engine->dispatch_execbuffer =
3017                         gen8_ring_dispatch_execbuffer;
3018         if (i915_semaphore_is_enabled(dev)) {
3019                 engine->semaphore.sync_to = gen8_ring_sync;
3020                 engine->semaphore.signal = gen8_xcs_signal;
3021                 GEN8_RING_SEMAPHORE_INIT(engine);
3022         }
3023         engine->init_hw = init_ring_common;
3024
3025         return intel_init_ring_buffer(dev, engine);
3026 }
3027
3028 int intel_init_blt_ring_buffer(struct drm_device *dev)
3029 {
3030         struct drm_i915_private *dev_priv = dev->dev_private;
3031         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3032
3033         engine->name = "blitter ring";
3034         engine->id = BCS;
3035         engine->exec_id = I915_EXEC_BLT;
3036
3037         engine->mmio_base = BLT_RING_BASE;
3038         engine->write_tail = ring_write_tail;
3039         engine->flush = gen6_ring_flush;
3040         engine->add_request = gen6_add_request;
3041         engine->irq_seqno_barrier = gen6_seqno_barrier;
3042         engine->get_seqno = ring_get_seqno;
3043         engine->set_seqno = ring_set_seqno;
3044         if (INTEL_INFO(dev)->gen >= 8) {
3045                 engine->irq_enable_mask =
3046                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3047                 engine->irq_get = gen8_ring_get_irq;
3048                 engine->irq_put = gen8_ring_put_irq;
3049                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3050                 if (i915_semaphore_is_enabled(dev)) {
3051                         engine->semaphore.sync_to = gen8_ring_sync;
3052                         engine->semaphore.signal = gen8_xcs_signal;
3053                         GEN8_RING_SEMAPHORE_INIT(engine);
3054                 }
3055         } else {
3056                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3057                 engine->irq_get = gen6_ring_get_irq;
3058                 engine->irq_put = gen6_ring_put_irq;
3059                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3060                 if (i915_semaphore_is_enabled(dev)) {
3061                         engine->semaphore.signal = gen6_signal;
3062                         engine->semaphore.sync_to = gen6_ring_sync;
3063                         /*
3064                          * The current semaphore is only applied on pre-gen8
3065                          * platform.  And there is no VCS2 ring on the pre-gen8
3066                          * platform. So the semaphore between BCS and VCS2 is
3067                          * initialized as INVALID.  Gen8 will initialize the
3068                          * sema between BCS and VCS2 later.
3069                          */
3070                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3071                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3072                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3073                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3074                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3075                         engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3076                         engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3077                         engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3078                         engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3079                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3080                 }
3081         }
3082         engine->init_hw = init_ring_common;
3083
3084         return intel_init_ring_buffer(dev, engine);
3085 }
3086
3087 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3088 {
3089         struct drm_i915_private *dev_priv = dev->dev_private;
3090         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3091
3092         engine->name = "video enhancement ring";
3093         engine->id = VECS;
3094         engine->exec_id = I915_EXEC_VEBOX;
3095
3096         engine->mmio_base = VEBOX_RING_BASE;
3097         engine->write_tail = ring_write_tail;
3098         engine->flush = gen6_ring_flush;
3099         engine->add_request = gen6_add_request;
3100         engine->irq_seqno_barrier = gen6_seqno_barrier;
3101         engine->get_seqno = ring_get_seqno;
3102         engine->set_seqno = ring_set_seqno;
3103
3104         if (INTEL_INFO(dev)->gen >= 8) {
3105                 engine->irq_enable_mask =
3106                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3107                 engine->irq_get = gen8_ring_get_irq;
3108                 engine->irq_put = gen8_ring_put_irq;
3109                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3110                 if (i915_semaphore_is_enabled(dev)) {
3111                         engine->semaphore.sync_to = gen8_ring_sync;
3112                         engine->semaphore.signal = gen8_xcs_signal;
3113                         GEN8_RING_SEMAPHORE_INIT(engine);
3114                 }
3115         } else {
3116                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3117                 engine->irq_get = hsw_vebox_get_irq;
3118                 engine->irq_put = hsw_vebox_put_irq;
3119                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3120                 if (i915_semaphore_is_enabled(dev)) {
3121                         engine->semaphore.sync_to = gen6_ring_sync;
3122                         engine->semaphore.signal = gen6_signal;
3123                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3124                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3125                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3126                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3127                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3128                         engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3129                         engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3130                         engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3131                         engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3132                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3133                 }
3134         }
3135         engine->init_hw = init_ring_common;
3136
3137         return intel_init_ring_buffer(dev, engine);
3138 }
3139
3140 int
3141 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3142 {
3143         struct intel_engine_cs *engine = req->engine;
3144         int ret;
3145
3146         if (!engine->gpu_caches_dirty)
3147                 return 0;
3148
3149         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3150         if (ret)
3151                 return ret;
3152
3153         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3154
3155         engine->gpu_caches_dirty = false;
3156         return 0;
3157 }
3158
3159 int
3160 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3161 {
3162         struct intel_engine_cs *engine = req->engine;
3163         uint32_t flush_domains;
3164         int ret;
3165
3166         flush_domains = 0;
3167         if (engine->gpu_caches_dirty)
3168                 flush_domains = I915_GEM_GPU_DOMAINS;
3169
3170         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3171         if (ret)
3172                 return ret;
3173
3174         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3175
3176         engine->gpu_caches_dirty = false;
3177         return 0;
3178 }
3179
3180 void
3181 intel_stop_engine(struct intel_engine_cs *engine)
3182 {
3183         int ret;
3184
3185         if (!intel_engine_initialized(engine))
3186                 return;
3187
3188         ret = intel_engine_idle(engine);
3189         if (ret)
3190                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3191                           engine->name, ret);
3192
3193         stop_ring(engine);
3194 }