drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
  37  * but keeps the logic simple. Indeed, the whole purpose of this macro is just
  38  * to give some inclination as to some of the magic values used in the various
  39  * workarounds!
  40  */
  41 #define CACHELINE_BYTES 64
  42
  43 static inline int __ring_space(int head, int tail, int size)
  44 {
  45         int space = head - (tail + I915_RING_FREE_SPACE);
  46         if (space < 0)
  47                 space += size;
  48         return space;
  49 }
  50
  51 static inline int ring_space(struct intel_ringbuffer *ringbuf)
  52 {
  53         return __ring_space(ringbuf->head & HEAD_ADDR, ringbuf->tail, ringbuf->size);
  54 }
  55
  56 static bool intel_ring_stopped(struct intel_engine_cs *ring)
  57 {
  58         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  59         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  60 }
  61
  62 void __intel_ring_advance(struct intel_engine_cs *ring)
  63 {
  64         struct intel_ringbuffer *ringbuf = ring->buffer;
  65         ringbuf->tail &= ringbuf->size - 1;
  66         if (intel_ring_stopped(ring))
  67                 return;
  68         ring->write_tail(ring, ringbuf->tail);
  69 }
  70
  71 static int
  72 gen2_render_ring_flush(struct intel_engine_cs *ring,
  73                        u32      invalidate_domains,
  74                        u32      flush_domains)
  75 {
  76         u32 cmd;
  77         int ret;
  78
  79         cmd = MI_FLUSH;
  80         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  81                 cmd |= MI_NO_WRITE_FLUSH;
  82
  83         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  84                 cmd |= MI_READ_FLUSH;
  85
  86         ret = intel_ring_begin(ring, 2);
  87         if (ret)
  88                 return ret;
  89
  90         intel_ring_emit(ring, cmd);
  91         intel_ring_emit(ring, MI_NOOP);
  92         intel_ring_advance(ring);
  93
  94         return 0;
  95 }
  96
  97 static int
  98 gen4_render_ring_flush(struct intel_engine_cs *ring,
  99                        u32      invalidate_domains,
 100                        u32      flush_domains)
 101 {
 102         struct drm_device *dev = ring->dev;
 103         u32 cmd;
 104         int ret;
 105
 106         /*
 107          * read/write caches:
 108          *
 109          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 110          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 111          * also flushed at 2d versus 3d pipeline switches.
 112          *
 113          * read-only caches:
 114          *
 115          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 116          * MI_READ_FLUSH is set, and is always flushed on 965.
 117          *
 118          * I915_GEM_DOMAIN_COMMAND may not exist?
 119          *
 120          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 121          * invalidated when MI_EXE_FLUSH is set.
 122          *
 123          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 124          * invalidated with every MI_FLUSH.
 125          *
 126          * TLBs:
 127          *
 128          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 129          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 130          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 131          * are flushed at any MI_FLUSH.
 132          */
 133
 134         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 135         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 136                 cmd &= ~MI_NO_WRITE_FLUSH;
 137         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 138                 cmd |= MI_EXE_FLUSH;
 139
 140         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 141             (IS_G4X(dev) || IS_GEN5(dev)))
 142                 cmd |= MI_INVALIDATE_ISP;
 143
 144         ret = intel_ring_begin(ring, 2);
 145         if (ret)
 146                 return ret;
 147
 148         intel_ring_emit(ring, cmd);
 149         intel_ring_emit(ring, MI_NOOP);
 150         intel_ring_advance(ring);
 151
 152         return 0;
 153 }
 154
 155 /**
 156  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 157  * implementing two workarounds on gen6.  From section 1.4.7.1
 158  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 159  *
 160  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 161  * produced by non-pipelined state commands), software needs to first
 162  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 163  * 0.
 164  *
 165  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 166  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 167  *
 168  * And the workaround for these two requires this workaround first:
 169  *
 170  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 171  * BEFORE the pipe-control with a post-sync op and no write-cache
 172  * flushes.
 173  *
 174  * And this last workaround is tricky because of the requirements on
 175  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 176  * volume 2 part 1:
 177  *
 178  *     "1 of the following must also be set:
 179  *      - Render Target Cache Flush Enable ([12] of DW1)
 180  *      - Depth Cache Flush Enable ([0] of DW1)
 181  *      - Stall at Pixel Scoreboard ([1] of DW1)
 182  *      - Depth Stall ([13] of DW1)
 183  *      - Post-Sync Operation ([13] of DW1)
 184  *      - Notify Enable ([8] of DW1)"
 185  *
 186  * The cache flushes require the workaround flush that triggered this
 187  * one, so we can't use it.  Depth stall would trigger the same.
 188  * Post-sync nonzero is what triggered this second workaround, so we
 189  * can't use that one either.  Notify enable is IRQs, which aren't
 190  * really our business.  That leaves only stall at scoreboard.
 191  */
 192 static int
 193 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 194 {
 195         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 196         int ret;
 197
 198
 199         ret = intel_ring_begin(ring, 6);
 200         if (ret)
 201                 return ret;
 202
 203         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 204         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 205                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 206         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 207         intel_ring_emit(ring, 0); /* low dword */
 208         intel_ring_emit(ring, 0); /* high dword */
 209         intel_ring_emit(ring, MI_NOOP);
 210         intel_ring_advance(ring);
 211
 212         ret = intel_ring_begin(ring, 6);
 213         if (ret)
 214                 return ret;
 215
 216         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 217         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 218         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 219         intel_ring_emit(ring, 0);
 220         intel_ring_emit(ring, 0);
 221         intel_ring_emit(ring, MI_NOOP);
 222         intel_ring_advance(ring);
 223
 224         return 0;
 225 }
 226
 227 static int
 228 gen6_render_ring_flush(struct intel_engine_cs *ring,
 229                          u32 invalidate_domains, u32 flush_domains)
 230 {
 231         u32 flags = 0;
 232         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 233         int ret;
 234
 235         /* Force SNB workarounds for PIPE_CONTROL flushes */
 236         ret = intel_emit_post_sync_nonzero_flush(ring);
 237         if (ret)
 238                 return ret;
 239
 240         /* Just flush everything.  Experiments have shown that reducing the
 241          * number of bits based on the write domains has little performance
 242          * impact.
 243          */
 244         if (flush_domains) {
 245                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 246                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 247                 /*
 248                  * Ensure that any following seqno writes only happen
 249                  * when the render cache is indeed flushed.
 250                  */
 251                 flags |= PIPE_CONTROL_CS_STALL;
 252         }
 253         if (invalidate_domains) {
 254                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 255                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 256                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 257                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 258                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 259                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 260                 /*
 261                  * TLB invalidate requires a post-sync write.
 262                  */
 263                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 264         }
 265
 266         ret = intel_ring_begin(ring, 4);
 267         if (ret)
 268                 return ret;
 269
 270         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 271         intel_ring_emit(ring, flags);
 272         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 273         intel_ring_emit(ring, 0);
 274         intel_ring_advance(ring);
 275
 276         return 0;
 277 }
 278
 279 static int
 280 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 281 {
 282         int ret;
 283
 284         ret = intel_ring_begin(ring, 4);
 285         if (ret)
 286                 return ret;
 287
 288         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 289         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 290                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 291         intel_ring_emit(ring, 0);
 292         intel_ring_emit(ring, 0);
 293         intel_ring_advance(ring);
 294
 295         return 0;
 296 }
 297
 298 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 299 {
 300         int ret;
 301
 302         if (!ring->fbc_dirty)
 303                 return 0;
 304
 305         ret = intel_ring_begin(ring, 6);
 306         if (ret)
 307                 return ret;
 308         /* WaFbcNukeOn3DBlt:ivb/hsw */
 309         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 310         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 311         intel_ring_emit(ring, value);
 312         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 313         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 314         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 315         intel_ring_advance(ring);
 316
 317         ring->fbc_dirty = false;
 318         return 0;
 319 }
 320
 321 static int
 322 gen7_render_ring_flush(struct intel_engine_cs *ring,
 323                        u32 invalidate_domains, u32 flush_domains)
 324 {
 325         u32 flags = 0;
 326         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 327         int ret;
 328
 329         /*
 330          * Ensure that any following seqno writes only happen when the render
 331          * cache is indeed flushed.
 332          *
 333          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 334          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 335          * don't try to be clever and just set it unconditionally.
 336          */
 337         flags |= PIPE_CONTROL_CS_STALL;
 338
 339         /* Just flush everything.  Experiments have shown that reducing the
 340          * number of bits based on the write domains has little performance
 341          * impact.
 342          */
 343         if (flush_domains) {
 344                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 345                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 346         }
 347         if (invalidate_domains) {
 348                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 349                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 350                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 351                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 352                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 353                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 354                 /*
 355                  * TLB invalidate requires a post-sync write.
 356                  */
 357                 flags |= PIPE_CONTROL_QW_WRITE;
 358                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 359
 360                 /* Workaround: we must issue a pipe_control with CS-stall bit
 361                  * set before a pipe_control command that has the state cache
 362                  * invalidate bit set. */
 363                 gen7_render_ring_cs_stall_wa(ring);
 364         }
 365
 366         ret = intel_ring_begin(ring, 4);
 367         if (ret)
 368                 return ret;
 369
 370         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 371         intel_ring_emit(ring, flags);
 372         intel_ring_emit(ring, scratch_addr);
 373         intel_ring_emit(ring, 0);
 374         intel_ring_advance(ring);
 375
 376         if (!invalidate_domains && flush_domains)
 377                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 378
 379         return 0;
 380 }
 381
 382 static int
 383 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 384                        u32 flags, u32 scratch_addr)
 385 {
 386         int ret;
 387
 388         ret = intel_ring_begin(ring, 6);
 389         if (ret)
 390                 return ret;
 391
 392         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 393         intel_ring_emit(ring, flags);
 394         intel_ring_emit(ring, scratch_addr);
 395         intel_ring_emit(ring, 0);
 396         intel_ring_emit(ring, 0);
 397         intel_ring_emit(ring, 0);
 398         intel_ring_advance(ring);
 399
 400         return 0;
 401 }
 402
 403 static int
 404 gen8_render_ring_flush(struct intel_engine_cs *ring,
 405                        u32 invalidate_domains, u32 flush_domains)
 406 {
 407         u32 flags = 0;
 408         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 409
 410         flags |= PIPE_CONTROL_CS_STALL;
 411
 412         if (flush_domains) {
 413                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 414                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 415         }
 416         if (invalidate_domains) {
 417                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 418                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 419                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 420                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 421                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 422                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 423                 flags |= PIPE_CONTROL_QW_WRITE;
 424                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 425         }
 426
 427         return gen8_emit_pipe_control(ring, flags, scratch_addr);
 428 }
 429
 430 static void ring_write_tail(struct intel_engine_cs *ring,
 431                             u32 value)
 432 {
 433         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 434         I915_WRITE_TAIL(ring, value);
 435 }
 436
 437 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 438 {
 439         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 440         u64 acthd;
 441
 442         if (INTEL_INFO(ring->dev)->gen >= 8)
 443                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 444                                          RING_ACTHD_UDW(ring->mmio_base));
 445         else if (INTEL_INFO(ring->dev)->gen >= 4)
 446                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 447         else
 448                 acthd = I915_READ(ACTHD);
 449
 450         return acthd;
 451 }
 452
 453 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 454 {
 455         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 456         u32 addr;
 457
 458         addr = dev_priv->status_page_dmah->busaddr;
 459         if (INTEL_INFO(ring->dev)->gen >= 4)
 460                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 461         I915_WRITE(HWS_PGA, addr);
 462 }
 463
 464 static bool stop_ring(struct intel_engine_cs *ring)
 465 {
 466         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 467
 468         if (!IS_GEN2(ring->dev)) {
 469                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 470                 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 471                         DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 472                         return false;
 473                 }
 474         }
 475
 476         I915_WRITE_CTL(ring, 0);
 477         I915_WRITE_HEAD(ring, 0);
 478         ring->write_tail(ring, 0);
 479
 480         if (!IS_GEN2(ring->dev)) {
 481                 (void)I915_READ_CTL(ring);
 482                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 483         }
 484
 485         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 486 }
 487
 488 static int init_ring_common(struct intel_engine_cs *ring)
 489 {
 490         struct drm_device *dev = ring->dev;
 491         struct drm_i915_private *dev_priv = dev->dev_private;
 492         struct intel_ringbuffer *ringbuf = ring->buffer;
 493         struct drm_i915_gem_object *obj = ringbuf->obj;
 494         int ret = 0;
 495
 496         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 497
 498         if (!stop_ring(ring)) {
 499                 /* G45 ring initialization often fails to reset head to zero */
 500                 DRM_DEBUG_KMS("%s head not reset to zero "
 501                               "ctl %08x head %08x tail %08x start %08x\n",
 502                               ring->name,
 503                               I915_READ_CTL(ring),
 504                               I915_READ_HEAD(ring),
 505                               I915_READ_TAIL(ring),
 506                               I915_READ_START(ring));
 507
 508                 if (!stop_ring(ring)) {
 509                         DRM_ERROR("failed to set %s head to zero "
 510                                   "ctl %08x head %08x tail %08x start %08x\n",
 511                                   ring->name,
 512                                   I915_READ_CTL(ring),
 513                                   I915_READ_HEAD(ring),
 514                                   I915_READ_TAIL(ring),
 515                                   I915_READ_START(ring));
 516                         ret = -EIO;
 517                         goto out;
 518                 }
 519         }
 520
 521         if (I915_NEED_GFX_HWS(dev))
 522                 intel_ring_setup_status_page(ring);
 523         else
 524                 ring_setup_phys_status_page(ring);
 525
 526         /* Initialize the ring. This must happen _after_ we've cleared the ring
 527          * registers with the above sequence (the readback of the HEAD registers
 528          * also enforces ordering), otherwise the hw might lose the new ring
 529          * register values. */
 530         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 531         I915_WRITE_CTL(ring,
 532                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 533                         | RING_VALID);
 534
 535         /* If the head is still not zero, the ring is dead */
 536         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 537                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 538                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 539                 DRM_ERROR("%s initialization failed "
 540                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 541                           ring->name,
 542                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 543                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 544                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 545                 ret = -EIO;
 546                 goto out;
 547         }
 548
 549         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 550                 i915_kernel_lost_context(ring->dev);
 551         else {
 552                 ringbuf->head = I915_READ_HEAD(ring);
 553                 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 554                 ringbuf->space = ring_space(ringbuf);
 555                 ringbuf->last_retired_head = -1;
 556         }
 557
 558         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 559
 560 out:
 561         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 562
 563         return ret;
 564 }
 565
 566 static int
 567 init_pipe_control(struct intel_engine_cs *ring)
 568 {
 569         int ret;
 570
 571         if (ring->scratch.obj)
 572                 return 0;
 573
 574         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 575         if (ring->scratch.obj == NULL) {
 576                 DRM_ERROR("Failed to allocate seqno page\n");
 577                 ret = -ENOMEM;
 578                 goto err;
 579         }
 580
 581         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 582         if (ret)
 583                 goto err_unref;
 584
 585         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 586         if (ret)
 587                 goto err_unref;
 588
 589         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 590         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 591         if (ring->scratch.cpu_page == NULL) {
 592                 ret = -ENOMEM;
 593                 goto err_unpin;
 594         }
 595
 596         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 597                          ring->name, ring->scratch.gtt_offset);
 598         return 0;
 599
 600 err_unpin:
 601         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 602 err_unref:
 603         drm_gem_object_unreference(&ring->scratch.obj->base);
 604 err:
 605         return ret;
 606 }
 607
 608 static int init_render_ring(struct intel_engine_cs *ring)
 609 {
 610         struct drm_device *dev = ring->dev;
 611         struct drm_i915_private *dev_priv = dev->dev_private;
 612         int ret = init_ring_common(ring);
 613         if (ret)
 614                 return ret;
 615
 616         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 617         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
 618                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 619
 620         /* We need to disable the AsyncFlip performance optimisations in order
 621          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 622          * programmed to '1' on all products.
 623          *
 624          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
 625          */
 626         if (INTEL_INFO(dev)->gen >= 6)
 627                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 628
 629         /* Required for the hardware to program scanline values for waiting */
 630         /* WaEnableFlushTlbInvalidationMode:snb */
 631         if (INTEL_INFO(dev)->gen == 6)
 632                 I915_WRITE(GFX_MODE,
 633                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 634
 635         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 636         if (IS_GEN7(dev))
 637                 I915_WRITE(GFX_MODE_GEN7,
 638                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 639                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 640
 641         if (INTEL_INFO(dev)->gen >= 5) {
 642                 ret = init_pipe_control(ring);
 643                 if (ret)
 644                         return ret;
 645         }
 646
 647         if (IS_GEN6(dev)) {
 648                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 649                  * "If this bit is set, STCunit will have LRA as replacement
 650                  *  policy. [...] This bit must be reset.  LRA replacement
 651                  *  policy is not supported."
 652                  */
 653                 I915_WRITE(CACHE_MODE_0,
 654                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 655         }
 656
 657         if (INTEL_INFO(dev)->gen >= 6)
 658                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 659
 660         if (HAS_L3_DPF(dev))
 661                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 662
 663         return ret;
 664 }
 665
 666 static void render_ring_cleanup(struct intel_engine_cs *ring)
 667 {
 668         struct drm_device *dev = ring->dev;
 669         struct drm_i915_private *dev_priv = dev->dev_private;
 670
 671         if (dev_priv->semaphore_obj) {
 672                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
 673                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
 674                 dev_priv->semaphore_obj = NULL;
 675         }
 676
 677         if (ring->scratch.obj == NULL)
 678                 return;
 679
 680         if (INTEL_INFO(dev)->gen >= 5) {
 681                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 682                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 683         }
 684
 685         drm_gem_object_unreference(&ring->scratch.obj->base);
 686         ring->scratch.obj = NULL;
 687 }
 688
 689 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
 690                            unsigned int num_dwords)
 691 {
 692 #define MBOX_UPDATE_DWORDS 8
 693         struct drm_device *dev = signaller->dev;
 694         struct drm_i915_private *dev_priv = dev->dev_private;
 695         struct intel_engine_cs *waiter;
 696         int i, ret, num_rings;
 697
 698         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 699         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 700 #undef MBOX_UPDATE_DWORDS
 701
 702         ret = intel_ring_begin(signaller, num_dwords);
 703         if (ret)
 704                 return ret;
 705
 706         for_each_ring(waiter, dev_priv, i) {
 707                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 708                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 709                         continue;
 710
 711                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
 712                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
 713                                            PIPE_CONTROL_QW_WRITE |
 714                                            PIPE_CONTROL_FLUSH_ENABLE);
 715                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
 716                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 717                 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
 718                 intel_ring_emit(signaller, 0);
 719                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 720                                            MI_SEMAPHORE_TARGET(waiter->id));
 721                 intel_ring_emit(signaller, 0);
 722         }
 723
 724         return 0;
 725 }
 726
 727 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
 728                            unsigned int num_dwords)
 729 {
 730 #define MBOX_UPDATE_DWORDS 6
 731         struct drm_device *dev = signaller->dev;
 732         struct drm_i915_private *dev_priv = dev->dev_private;
 733         struct intel_engine_cs *waiter;
 734         int i, ret, num_rings;
 735
 736         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 737         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 738 #undef MBOX_UPDATE_DWORDS
 739
 740         ret = intel_ring_begin(signaller, num_dwords);
 741         if (ret)
 742                 return ret;
 743
 744         for_each_ring(waiter, dev_priv, i) {
 745                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 746                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 747                         continue;
 748
 749                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
 750                                            MI_FLUSH_DW_OP_STOREDW);
 751                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
 752                                            MI_FLUSH_DW_USE_GTT);
 753                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 754                 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
 755                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 756                                            MI_SEMAPHORE_TARGET(waiter->id));
 757                 intel_ring_emit(signaller, 0);
 758         }
 759
 760         return 0;
 761 }
 762
 763 static int gen6_signal(struct intel_engine_cs *signaller,
 764                        unsigned int num_dwords)
 765 {
 766         struct drm_device *dev = signaller->dev;
 767         struct drm_i915_private *dev_priv = dev->dev_private;
 768         struct intel_engine_cs *useless;
 769         int i, ret, num_rings;
 770
 771 #define MBOX_UPDATE_DWORDS 3
 772         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 773         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
 774 #undef MBOX_UPDATE_DWORDS
 775
 776         ret = intel_ring_begin(signaller, num_dwords);
 777         if (ret)
 778                 return ret;
 779
 780         for_each_ring(useless, dev_priv, i) {
 781                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
 782                 if (mbox_reg != GEN6_NOSYNC) {
 783                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
 784                         intel_ring_emit(signaller, mbox_reg);
 785                         intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
 786                 }
 787         }
 788
 789         /* If num_dwords was rounded, make sure the tail pointer is correct */
 790         if (num_rings % 2 == 0)
 791                 intel_ring_emit(signaller, MI_NOOP);
 792
 793         return 0;
 794 }
 795
 796 /**
 797  * gen6_add_request - Update the semaphore mailbox registers
 798  *
 799  * @ring - ring that is adding a request
 800  * @seqno - return seqno stuck into the ring
 801  *
 802  * Update the mailbox registers in the *other* rings with the current seqno.
 803  * This acts like a signal in the canonical semaphore.
 804  */
 805 static int
 806 gen6_add_request(struct intel_engine_cs *ring)
 807 {
 808         int ret;
 809
 810         if (ring->semaphore.signal)
 811                 ret = ring->semaphore.signal(ring, 4);
 812         else
 813                 ret = intel_ring_begin(ring, 4);
 814
 815         if (ret)
 816                 return ret;
 817
 818         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 819         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 820         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 821         intel_ring_emit(ring, MI_USER_INTERRUPT);
 822         __intel_ring_advance(ring);
 823
 824         return 0;
 825 }
 826
 827 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 828                                               u32 seqno)
 829 {
 830         struct drm_i915_private *dev_priv = dev->dev_private;
 831         return dev_priv->last_seqno < seqno;
 832 }
 833
 834 /**
 835  * intel_ring_sync - sync the waiter to the signaller on seqno
 836  *
 837  * @waiter - ring that is waiting
 838  * @signaller - ring which has, or will signal
 839  * @seqno - seqno which the waiter will block on
 840  */
 841
 842 static int
 843 gen8_ring_sync(struct intel_engine_cs *waiter,
 844                struct intel_engine_cs *signaller,
 845                u32 seqno)
 846 {
 847         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
 848         int ret;
 849
 850         ret = intel_ring_begin(waiter, 4);
 851         if (ret)
 852                 return ret;
 853
 854         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
 855                                 MI_SEMAPHORE_GLOBAL_GTT |
 856                                 MI_SEMAPHORE_POLL |
 857                                 MI_SEMAPHORE_SAD_GTE_SDD);
 858         intel_ring_emit(waiter, seqno);
 859         intel_ring_emit(waiter,
 860                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
 861         intel_ring_emit(waiter,
 862                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
 863         intel_ring_advance(waiter);
 864         return 0;
 865 }
 866
 867 static int
 868 gen6_ring_sync(struct intel_engine_cs *waiter,
 869                struct intel_engine_cs *signaller,
 870                u32 seqno)
 871 {
 872         u32 dw1 = MI_SEMAPHORE_MBOX |
 873                   MI_SEMAPHORE_COMPARE |
 874                   MI_SEMAPHORE_REGISTER;
 875         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
 876         int ret;
 877
 878         /* Throughout all of the GEM code, seqno passed implies our current
 879          * seqno is >= the last seqno executed. However for hardware the
 880          * comparison is strictly greater than.
 881          */
 882         seqno -= 1;
 883
 884         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
 885
 886         ret = intel_ring_begin(waiter, 4);
 887         if (ret)
 888                 return ret;
 889
 890         /* If seqno wrap happened, omit the wait with no-ops */
 891         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 892                 intel_ring_emit(waiter, dw1 | wait_mbox);
 893                 intel_ring_emit(waiter, seqno);
 894                 intel_ring_emit(waiter, 0);
 895                 intel_ring_emit(waiter, MI_NOOP);
 896         } else {
 897                 intel_ring_emit(waiter, MI_NOOP);
 898                 intel_ring_emit(waiter, MI_NOOP);
 899                 intel_ring_emit(waiter, MI_NOOP);
 900                 intel_ring_emit(waiter, MI_NOOP);
 901         }
 902         intel_ring_advance(waiter);
 903
 904         return 0;
 905 }
 906
 907 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 908 do {                                                                    \
 909         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 910                  PIPE_CONTROL_DEPTH_STALL);                             \
 911         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 912         intel_ring_emit(ring__, 0);                                                     \
 913         intel_ring_emit(ring__, 0);                                                     \
 914 } while (0)
 915
 916 static int
 917 pc_render_add_request(struct intel_engine_cs *ring)
 918 {
 919         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 920         int ret;
 921
 922         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 923          * incoherent with writes to memory, i.e. completely fubar,
 924          * so we need to use PIPE_NOTIFY instead.
 925          *
 926          * However, we also need to workaround the qword write
 927          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 928          * memory before requesting an interrupt.
 929          */
 930         ret = intel_ring_begin(ring, 32);
 931         if (ret)
 932                 return ret;
 933
 934         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 935                         PIPE_CONTROL_WRITE_FLUSH |
 936                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 937         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 938         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 939         intel_ring_emit(ring, 0);
 940         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 941         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
 942         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 943         scratch_addr += 2 * CACHELINE_BYTES;
 944         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 945         scratch_addr += 2 * CACHELINE_BYTES;
 946         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 947         scratch_addr += 2 * CACHELINE_BYTES;
 948         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 949         scratch_addr += 2 * CACHELINE_BYTES;
 950         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 951
 952         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 953                         PIPE_CONTROL_WRITE_FLUSH |
 954                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 955                         PIPE_CONTROL_NOTIFY);
 956         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 957         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 958         intel_ring_emit(ring, 0);
 959         __intel_ring_advance(ring);
 960
 961         return 0;
 962 }
 963
 964 static u32
 965 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
 966 {
 967         /* Workaround to force correct ordering between irq and seqno writes on
 968          * ivb (and maybe also on snb) by reading from a CS register (like
 969          * ACTHD) before reading the status page. */
 970         if (!lazy_coherency) {
 971                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
 972                 POSTING_READ(RING_ACTHD(ring->mmio_base));
 973         }
 974
 975         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 976 }
 977
 978 static u32
 979 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
 980 {
 981         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 982 }
 983
 984 static void
 985 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
 986 {
 987         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 988 }
 989
 990 static u32
 991 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
 992 {
 993         return ring->scratch.cpu_page[0];
 994 }
 995
 996 static void
 997 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
 998 {
 999         ring->scratch.cpu_page[0] = seqno;
1000 }
1001
1002 static bool
1003 gen5_ring_get_irq(struct intel_engine_cs *ring)
1004 {
1005         struct drm_device *dev = ring->dev;
1006         struct drm_i915_private *dev_priv = dev->dev_private;
1007         unsigned long flags;
1008
1009         if (!dev->irq_enabled)
1010                 return false;
1011
1012         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1013         if (ring->irq_refcount++ == 0)
1014                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1015         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1016
1017         return true;
1018 }
1019
1020 static void
1021 gen5_ring_put_irq(struct intel_engine_cs *ring)
1022 {
1023         struct drm_device *dev = ring->dev;
1024         struct drm_i915_private *dev_priv = dev->dev_private;
1025         unsigned long flags;
1026
1027         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1028         if (--ring->irq_refcount == 0)
1029                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1030         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1031 }
1032
1033 static bool
1034 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1035 {
1036         struct drm_device *dev = ring->dev;
1037         struct drm_i915_private *dev_priv = dev->dev_private;
1038         unsigned long flags;
1039
1040         if (!dev->irq_enabled)
1041                 return false;
1042
1043         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1044         if (ring->irq_refcount++ == 0) {
1045                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1046                 I915_WRITE(IMR, dev_priv->irq_mask);
1047                 POSTING_READ(IMR);
1048         }
1049         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1050
1051         return true;
1052 }
1053
1054 static void
1055 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1056 {
1057         struct drm_device *dev = ring->dev;
1058         struct drm_i915_private *dev_priv = dev->dev_private;
1059         unsigned long flags;
1060
1061         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1062         if (--ring->irq_refcount == 0) {
1063                 dev_priv->irq_mask |= ring->irq_enable_mask;
1064                 I915_WRITE(IMR, dev_priv->irq_mask);
1065                 POSTING_READ(IMR);
1066         }
1067         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1068 }
1069
1070 static bool
1071 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1072 {
1073         struct drm_device *dev = ring->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         unsigned long flags;
1076
1077         if (!dev->irq_enabled)
1078                 return false;
1079
1080         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1081         if (ring->irq_refcount++ == 0) {
1082                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1083                 I915_WRITE16(IMR, dev_priv->irq_mask);
1084                 POSTING_READ16(IMR);
1085         }
1086         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1087
1088         return true;
1089 }
1090
1091 static void
1092 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1093 {
1094         struct drm_device *dev = ring->dev;
1095         struct drm_i915_private *dev_priv = dev->dev_private;
1096         unsigned long flags;
1097
1098         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1099         if (--ring->irq_refcount == 0) {
1100                 dev_priv->irq_mask |= ring->irq_enable_mask;
1101                 I915_WRITE16(IMR, dev_priv->irq_mask);
1102                 POSTING_READ16(IMR);
1103         }
1104         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1105 }
1106
1107 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1108 {
1109         struct drm_device *dev = ring->dev;
1110         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1111         u32 mmio = 0;
1112
1113         /* The ring status page addresses are no longer next to the rest of
1114          * the ring registers as of gen7.
1115          */
1116         if (IS_GEN7(dev)) {
1117                 switch (ring->id) {
1118                 case RCS:
1119                         mmio = RENDER_HWS_PGA_GEN7;
1120                         break;
1121                 case BCS:
1122                         mmio = BLT_HWS_PGA_GEN7;
1123                         break;
1124                 /*
1125                  * VCS2 actually doesn't exist on Gen7. Only shut up
1126                  * gcc switch check warning
1127                  */
1128                 case VCS2:
1129                 case VCS:
1130                         mmio = BSD_HWS_PGA_GEN7;
1131                         break;
1132                 case VECS:
1133                         mmio = VEBOX_HWS_PGA_GEN7;
1134                         break;
1135                 }
1136         } else if (IS_GEN6(ring->dev)) {
1137                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1138         } else {
1139                 /* XXX: gen8 returns to sanity */
1140                 mmio = RING_HWS_PGA(ring->mmio_base);
1141         }
1142
1143         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1144         POSTING_READ(mmio);
1145
1146         /*
1147          * Flush the TLB for this page
1148          *
1149          * FIXME: These two bits have disappeared on gen8, so a question
1150          * arises: do we still need this and if so how should we go about
1151          * invalidating the TLB?
1152          */
1153         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1154                 u32 reg = RING_INSTPM(ring->mmio_base);
1155
1156                 /* ring should be idle before issuing a sync flush*/
1157                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1158
1159                 I915_WRITE(reg,
1160                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1161                                               INSTPM_SYNC_FLUSH));
1162                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1163                              1000))
1164                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1165                                   ring->name);
1166         }
1167 }
1168
1169 static int
1170 bsd_ring_flush(struct intel_engine_cs *ring,
1171                u32     invalidate_domains,
1172                u32     flush_domains)
1173 {
1174         int ret;
1175
1176         ret = intel_ring_begin(ring, 2);
1177         if (ret)
1178                 return ret;
1179
1180         intel_ring_emit(ring, MI_FLUSH);
1181         intel_ring_emit(ring, MI_NOOP);
1182         intel_ring_advance(ring);
1183         return 0;
1184 }
1185
1186 static int
1187 i9xx_add_request(struct intel_engine_cs *ring)
1188 {
1189         int ret;
1190
1191         ret = intel_ring_begin(ring, 4);
1192         if (ret)
1193                 return ret;
1194
1195         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1196         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1197         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1198         intel_ring_emit(ring, MI_USER_INTERRUPT);
1199         __intel_ring_advance(ring);
1200
1201         return 0;
1202 }
1203
1204 static bool
1205 gen6_ring_get_irq(struct intel_engine_cs *ring)
1206 {
1207         struct drm_device *dev = ring->dev;
1208         struct drm_i915_private *dev_priv = dev->dev_private;
1209         unsigned long flags;
1210
1211         if (!dev->irq_enabled)
1212                return false;
1213
1214         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1215         if (ring->irq_refcount++ == 0) {
1216                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1217                         I915_WRITE_IMR(ring,
1218                                        ~(ring->irq_enable_mask |
1219                                          GT_PARITY_ERROR(dev)));
1220                 else
1221                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1222                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1223         }
1224         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1225
1226         return true;
1227 }
1228
1229 static void
1230 gen6_ring_put_irq(struct intel_engine_cs *ring)
1231 {
1232         struct drm_device *dev = ring->dev;
1233         struct drm_i915_private *dev_priv = dev->dev_private;
1234         unsigned long flags;
1235
1236         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1237         if (--ring->irq_refcount == 0) {
1238                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1239                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1240                 else
1241                         I915_WRITE_IMR(ring, ~0);
1242                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1243         }
1244         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1245 }
1246
1247 static bool
1248 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1249 {
1250         struct drm_device *dev = ring->dev;
1251         struct drm_i915_private *dev_priv = dev->dev_private;
1252         unsigned long flags;
1253
1254         if (!dev->irq_enabled)
1255                 return false;
1256
1257         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1258         if (ring->irq_refcount++ == 0) {
1259                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1260                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1261         }
1262         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1263
1264         return true;
1265 }
1266
1267 static void
1268 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1269 {
1270         struct drm_device *dev = ring->dev;
1271         struct drm_i915_private *dev_priv = dev->dev_private;
1272         unsigned long flags;
1273
1274         if (!dev->irq_enabled)
1275                 return;
1276
1277         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1278         if (--ring->irq_refcount == 0) {
1279                 I915_WRITE_IMR(ring, ~0);
1280                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1281         }
1282         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1283 }
1284
1285 static bool
1286 gen8_ring_get_irq(struct intel_engine_cs *ring)
1287 {
1288         struct drm_device *dev = ring->dev;
1289         struct drm_i915_private *dev_priv = dev->dev_private;
1290         unsigned long flags;
1291
1292         if (!dev->irq_enabled)
1293                 return false;
1294
1295         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1296         if (ring->irq_refcount++ == 0) {
1297                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1298                         I915_WRITE_IMR(ring,
1299                                        ~(ring->irq_enable_mask |
1300                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1301                 } else {
1302                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1303                 }
1304                 POSTING_READ(RING_IMR(ring->mmio_base));
1305         }
1306         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1307
1308         return true;
1309 }
1310
1311 static void
1312 gen8_ring_put_irq(struct intel_engine_cs *ring)
1313 {
1314         struct drm_device *dev = ring->dev;
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         unsigned long flags;
1317
1318         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1319         if (--ring->irq_refcount == 0) {
1320                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1321                         I915_WRITE_IMR(ring,
1322                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1323                 } else {
1324                         I915_WRITE_IMR(ring, ~0);
1325                 }
1326                 POSTING_READ(RING_IMR(ring->mmio_base));
1327         }
1328         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1329 }
1330
1331 static int
1332 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1333                          u64 offset, u32 length,
1334                          unsigned flags)
1335 {
1336         int ret;
1337
1338         ret = intel_ring_begin(ring, 2);
1339         if (ret)
1340                 return ret;
1341
1342         intel_ring_emit(ring,
1343                         MI_BATCH_BUFFER_START |
1344                         MI_BATCH_GTT |
1345                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1346         intel_ring_emit(ring, offset);
1347         intel_ring_advance(ring);
1348
1349         return 0;
1350 }
1351
1352 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1353 #define I830_BATCH_LIMIT (256*1024)
1354 static int
1355 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1356                                 u64 offset, u32 len,
1357                                 unsigned flags)
1358 {
1359         int ret;
1360
1361         if (flags & I915_DISPATCH_PINNED) {
1362                 ret = intel_ring_begin(ring, 4);
1363                 if (ret)
1364                         return ret;
1365
1366                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1367                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1368                 intel_ring_emit(ring, offset + len - 8);
1369                 intel_ring_emit(ring, MI_NOOP);
1370                 intel_ring_advance(ring);
1371         } else {
1372                 u32 cs_offset = ring->scratch.gtt_offset;
1373
1374                 if (len > I830_BATCH_LIMIT)
1375                         return -ENOSPC;
1376
1377                 ret = intel_ring_begin(ring, 9+3);
1378                 if (ret)
1379                         return ret;
1380                 /* Blit the batch (which has now all relocs applied) to the stable batch
1381                  * scratch bo area (so that the CS never stumbles over its tlb
1382                  * invalidation bug) ... */
1383                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1384                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1385                                 XY_SRC_COPY_BLT_WRITE_RGB);
1386                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1387                 intel_ring_emit(ring, 0);
1388                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1389                 intel_ring_emit(ring, cs_offset);
1390                 intel_ring_emit(ring, 0);
1391                 intel_ring_emit(ring, 4096);
1392                 intel_ring_emit(ring, offset);
1393                 intel_ring_emit(ring, MI_FLUSH);
1394
1395                 /* ... and execute it. */
1396                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1397                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1398                 intel_ring_emit(ring, cs_offset + len - 8);
1399                 intel_ring_advance(ring);
1400         }
1401
1402         return 0;
1403 }
1404
1405 static int
1406 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1407                          u64 offset, u32 len,
1408                          unsigned flags)
1409 {
1410         int ret;
1411
1412         ret = intel_ring_begin(ring, 2);
1413         if (ret)
1414                 return ret;
1415
1416         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1417         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1418         intel_ring_advance(ring);
1419
1420         return 0;
1421 }
1422
1423 static void cleanup_status_page(struct intel_engine_cs *ring)
1424 {
1425         struct drm_i915_gem_object *obj;
1426
1427         obj = ring->status_page.obj;
1428         if (obj == NULL)
1429                 return;
1430
1431         kunmap(sg_page(obj->pages->sgl));
1432         i915_gem_object_ggtt_unpin(obj);
1433         drm_gem_object_unreference(&obj->base);
1434         ring->status_page.obj = NULL;
1435 }
1436
1437 static int init_status_page(struct intel_engine_cs *ring)
1438 {
1439         struct drm_i915_gem_object *obj;
1440
1441         if ((obj = ring->status_page.obj) == NULL) {
1442                 unsigned flags;
1443                 int ret;
1444
1445                 obj = i915_gem_alloc_object(ring->dev, 4096);
1446                 if (obj == NULL) {
1447                         DRM_ERROR("Failed to allocate status page\n");
1448                         return -ENOMEM;
1449                 }
1450
1451                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1452                 if (ret)
1453                         goto err_unref;
1454
1455                 flags = 0;
1456                 if (!HAS_LLC(ring->dev))
1457                         /* On g33, we cannot place HWS above 256MiB, so
1458                          * restrict its pinning to the low mappable arena.
1459                          * Though this restriction is not documented for
1460                          * gen4, gen5, or byt, they also behave similarly
1461                          * and hang if the HWS is placed at the top of the
1462                          * GTT. To generalise, it appears that all !llc
1463                          * platforms have issues with us placing the HWS
1464                          * above the mappable region (even though we never
1465                          * actualy map it).
1466                          */
1467                         flags |= PIN_MAPPABLE;
1468                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1469                 if (ret) {
1470 err_unref:
1471                         drm_gem_object_unreference(&obj->base);
1472                         return ret;
1473                 }
1474
1475                 ring->status_page.obj = obj;
1476         }
1477
1478         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1479         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1480         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1481
1482         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1483                         ring->name, ring->status_page.gfx_addr);
1484
1485         return 0;
1486 }
1487
1488 static int init_phys_status_page(struct intel_engine_cs *ring)
1489 {
1490         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1491
1492         if (!dev_priv->status_page_dmah) {
1493                 dev_priv->status_page_dmah =
1494                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1495                 if (!dev_priv->status_page_dmah)
1496                         return -ENOMEM;
1497         }
1498
1499         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1500         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1501
1502         return 0;
1503 }
1504
1505 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1506 {
1507         if (!ringbuf->obj)
1508                 return;
1509
1510         iounmap(ringbuf->virtual_start);
1511         i915_gem_object_ggtt_unpin(ringbuf->obj);
1512         drm_gem_object_unreference(&ringbuf->obj->base);
1513         ringbuf->obj = NULL;
1514 }
1515
1516 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1517                                       struct intel_ringbuffer *ringbuf)
1518 {
1519         struct drm_i915_private *dev_priv = to_i915(dev);
1520         struct drm_i915_gem_object *obj;
1521         int ret;
1522
1523         if (ringbuf->obj)
1524                 return 0;
1525
1526         obj = NULL;
1527         if (!HAS_LLC(dev))
1528                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1529         if (obj == NULL)
1530                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1531         if (obj == NULL)
1532                 return -ENOMEM;
1533
1534         /* mark ring buffers as read-only from GPU side by default */
1535         obj->gt_ro = 1;
1536
1537         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1538         if (ret)
1539                 goto err_unref;
1540
1541         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1542         if (ret)
1543                 goto err_unpin;
1544
1545         ringbuf->virtual_start =
1546                 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1547                                 ringbuf->size);
1548         if (ringbuf->virtual_start == NULL) {
1549                 ret = -EINVAL;
1550                 goto err_unpin;
1551         }
1552
1553         ringbuf->obj = obj;
1554         return 0;
1555
1556 err_unpin:
1557         i915_gem_object_ggtt_unpin(obj);
1558 err_unref:
1559         drm_gem_object_unreference(&obj->base);
1560         return ret;
1561 }
1562
1563 static int intel_init_ring_buffer(struct drm_device *dev,
1564                                   struct intel_engine_cs *ring)
1565 {
1566         struct intel_ringbuffer *ringbuf = ring->buffer;
1567         int ret;
1568
1569         if (ringbuf == NULL) {
1570                 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1571                 if (!ringbuf)
1572                         return -ENOMEM;
1573                 ring->buffer = ringbuf;
1574         }
1575
1576         ring->dev = dev;
1577         INIT_LIST_HEAD(&ring->active_list);
1578         INIT_LIST_HEAD(&ring->request_list);
1579         ringbuf->size = 32 * PAGE_SIZE;
1580         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1581
1582         init_waitqueue_head(&ring->irq_queue);
1583
1584         if (I915_NEED_GFX_HWS(dev)) {
1585                 ret = init_status_page(ring);
1586                 if (ret)
1587                         goto error;
1588         } else {
1589                 BUG_ON(ring->id != RCS);
1590                 ret = init_phys_status_page(ring);
1591                 if (ret)
1592                         goto error;
1593         }
1594
1595         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1596         if (ret) {
1597                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1598                 goto error;
1599         }
1600
1601         /* Workaround an erratum on the i830 which causes a hang if
1602          * the TAIL pointer points to within the last 2 cachelines
1603          * of the buffer.
1604          */
1605         ringbuf->effective_size = ringbuf->size;
1606         if (IS_I830(dev) || IS_845G(dev))
1607                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1608
1609         ret = i915_cmd_parser_init_ring(ring);
1610         if (ret)
1611                 goto error;
1612
1613         ret = ring->init(ring);
1614         if (ret)
1615                 goto error;
1616
1617         return 0;
1618
1619 error:
1620         kfree(ringbuf);
1621         ring->buffer = NULL;
1622         return ret;
1623 }
1624
1625 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1626 {
1627         struct drm_i915_private *dev_priv = to_i915(ring->dev);
1628         struct intel_ringbuffer *ringbuf = ring->buffer;
1629
1630         if (!intel_ring_initialized(ring))
1631                 return;
1632
1633         intel_stop_ring_buffer(ring);
1634         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1635
1636         intel_destroy_ringbuffer_obj(ringbuf);
1637         ring->preallocated_lazy_request = NULL;
1638         ring->outstanding_lazy_seqno = 0;
1639
1640         if (ring->cleanup)
1641                 ring->cleanup(ring);
1642
1643         cleanup_status_page(ring);
1644
1645         i915_cmd_parser_fini_ring(ring);
1646
1647         kfree(ringbuf);
1648         ring->buffer = NULL;
1649 }
1650
1651 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1652 {
1653         struct intel_ringbuffer *ringbuf = ring->buffer;
1654         struct drm_i915_gem_request *request;
1655         u32 seqno = 0;
1656         int ret;
1657
1658         if (ringbuf->last_retired_head != -1) {
1659                 ringbuf->head = ringbuf->last_retired_head;
1660                 ringbuf->last_retired_head = -1;
1661
1662                 ringbuf->space = ring_space(ringbuf);
1663                 if (ringbuf->space >= n)
1664                         return 0;
1665         }
1666
1667         list_for_each_entry(request, &ring->request_list, list) {
1668                 if (__ring_space(request->tail, ringbuf->tail, ringbuf->size) >= n) {
1669                         seqno = request->seqno;
1670                         break;
1671                 }
1672         }
1673
1674         if (seqno == 0)
1675                 return -ENOSPC;
1676
1677         ret = i915_wait_seqno(ring, seqno);
1678         if (ret)
1679                 return ret;
1680
1681         i915_gem_retire_requests_ring(ring);
1682         ringbuf->head = ringbuf->last_retired_head;
1683         ringbuf->last_retired_head = -1;
1684
1685         ringbuf->space = ring_space(ringbuf);
1686         return 0;
1687 }
1688
1689 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1690 {
1691         struct drm_device *dev = ring->dev;
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         struct intel_ringbuffer *ringbuf = ring->buffer;
1694         unsigned long end;
1695         int ret;
1696
1697         ret = intel_ring_wait_request(ring, n);
1698         if (ret != -ENOSPC)
1699                 return ret;
1700
1701         /* force the tail write in case we have been skipping them */
1702         __intel_ring_advance(ring);
1703
1704         /* With GEM the hangcheck timer should kick us out of the loop,
1705          * leaving it early runs the risk of corrupting GEM state (due
1706          * to running on almost untested codepaths). But on resume
1707          * timers don't work yet, so prevent a complete hang in that
1708          * case by choosing an insanely large timeout. */
1709         end = jiffies + 60 * HZ;
1710
1711         trace_i915_ring_wait_begin(ring);
1712         do {
1713                 ringbuf->head = I915_READ_HEAD(ring);
1714                 ringbuf->space = ring_space(ringbuf);
1715                 if (ringbuf->space >= n) {
1716                         ret = 0;
1717                         break;
1718                 }
1719
1720                 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1721                     dev->primary->master) {
1722                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1723                         if (master_priv->sarea_priv)
1724                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1725                 }
1726
1727                 msleep(1);
1728
1729                 if (dev_priv->mm.interruptible && signal_pending(current)) {
1730                         ret = -ERESTARTSYS;
1731                         break;
1732                 }
1733
1734                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1735                                            dev_priv->mm.interruptible);
1736                 if (ret)
1737                         break;
1738
1739                 if (time_after(jiffies, end)) {
1740                         ret = -EBUSY;
1741                         break;
1742                 }
1743         } while (1);
1744         trace_i915_ring_wait_end(ring);
1745         return ret;
1746 }
1747
1748 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
1749 {
1750         uint32_t __iomem *virt;
1751         struct intel_ringbuffer *ringbuf = ring->buffer;
1752         int rem = ringbuf->size - ringbuf->tail;
1753
1754         if (ringbuf->space < rem) {
1755                 int ret = ring_wait_for_space(ring, rem);
1756                 if (ret)
1757                         return ret;
1758         }
1759
1760         virt = ringbuf->virtual_start + ringbuf->tail;
1761         rem /= 4;
1762         while (rem--)
1763                 iowrite32(MI_NOOP, virt++);
1764
1765         ringbuf->tail = 0;
1766         ringbuf->space = ring_space(ringbuf);
1767
1768         return 0;
1769 }
1770
1771 int intel_ring_idle(struct intel_engine_cs *ring)
1772 {
1773         u32 seqno;
1774         int ret;
1775
1776         /* We need to add any requests required to flush the objects and ring */
1777         if (ring->outstanding_lazy_seqno) {
1778                 ret = i915_add_request(ring, NULL);
1779                 if (ret)
1780                         return ret;
1781         }
1782
1783         /* Wait upon the last request to be completed */
1784         if (list_empty(&ring->request_list))
1785                 return 0;
1786
1787         seqno = list_entry(ring->request_list.prev,
1788                            struct drm_i915_gem_request,
1789                            list)->seqno;
1790
1791         return i915_wait_seqno(ring, seqno);
1792 }
1793
1794 static int
1795 intel_ring_alloc_seqno(struct intel_engine_cs *ring)
1796 {
1797         if (ring->outstanding_lazy_seqno)
1798                 return 0;
1799
1800         if (ring->preallocated_lazy_request == NULL) {
1801                 struct drm_i915_gem_request *request;
1802
1803                 request = kmalloc(sizeof(*request), GFP_KERNEL);
1804                 if (request == NULL)
1805                         return -ENOMEM;
1806
1807                 ring->preallocated_lazy_request = request;
1808         }
1809
1810         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1811 }
1812
1813 static int __intel_ring_prepare(struct intel_engine_cs *ring,
1814                                 int bytes)
1815 {
1816         struct intel_ringbuffer *ringbuf = ring->buffer;
1817         int ret;
1818
1819         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1820                 ret = intel_wrap_ring_buffer(ring);
1821                 if (unlikely(ret))
1822                         return ret;
1823         }
1824
1825         if (unlikely(ringbuf->space < bytes)) {
1826                 ret = ring_wait_for_space(ring, bytes);
1827                 if (unlikely(ret))
1828                         return ret;
1829         }
1830
1831         return 0;
1832 }
1833
1834 int intel_ring_begin(struct intel_engine_cs *ring,
1835                      int num_dwords)
1836 {
1837         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1838         int ret;
1839
1840         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1841                                    dev_priv->mm.interruptible);
1842         if (ret)
1843                 return ret;
1844
1845         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1846         if (ret)
1847                 return ret;
1848
1849         /* Preallocate the olr before touching the ring */
1850         ret = intel_ring_alloc_seqno(ring);
1851         if (ret)
1852                 return ret;
1853
1854         ring->buffer->space -= num_dwords * sizeof(uint32_t);
1855         return 0;
1856 }
1857
1858 /* Align the ring tail to a cacheline boundary */
1859 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
1860 {
1861         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
1862         int ret;
1863
1864         if (num_dwords == 0)
1865                 return 0;
1866
1867         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
1868         ret = intel_ring_begin(ring, num_dwords);
1869         if (ret)
1870                 return ret;
1871
1872         while (num_dwords--)
1873                 intel_ring_emit(ring, MI_NOOP);
1874
1875         intel_ring_advance(ring);
1876
1877         return 0;
1878 }
1879
1880 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
1881 {
1882         struct drm_device *dev = ring->dev;
1883         struct drm_i915_private *dev_priv = dev->dev_private;
1884
1885         BUG_ON(ring->outstanding_lazy_seqno);
1886
1887         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
1888                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1889                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1890                 if (HAS_VEBOX(dev))
1891                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1892         }
1893
1894         ring->set_seqno(ring, seqno);
1895         ring->hangcheck.seqno = seqno;
1896 }
1897
1898 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
1899                                      u32 value)
1900 {
1901         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1902
1903        /* Every tail move must follow the sequence below */
1904
1905         /* Disable notification that the ring is IDLE. The GT
1906          * will then assume that it is busy and bring it out of rc6.
1907          */
1908         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1909                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1910
1911         /* Clear the context id. Here be magic! */
1912         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1913
1914         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1915         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1916                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1917                      50))
1918                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1919
1920         /* Now that the ring is fully powered up, update the tail */
1921         I915_WRITE_TAIL(ring, value);
1922         POSTING_READ(RING_TAIL(ring->mmio_base));
1923
1924         /* Let the ring send IDLE messages to the GT again,
1925          * and so let it sleep to conserve power when idle.
1926          */
1927         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1928                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1929 }
1930
1931 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
1932                                u32 invalidate, u32 flush)
1933 {
1934         uint32_t cmd;
1935         int ret;
1936
1937         ret = intel_ring_begin(ring, 4);
1938         if (ret)
1939                 return ret;
1940
1941         cmd = MI_FLUSH_DW;
1942         if (INTEL_INFO(ring->dev)->gen >= 8)
1943                 cmd += 1;
1944         /*
1945          * Bspec vol 1c.5 - video engine command streamer:
1946          * "If ENABLED, all TLBs will be invalidated once the flush
1947          * operation is complete. This bit is only valid when the
1948          * Post-Sync Operation field is a value of 1h or 3h."
1949          */
1950         if (invalidate & I915_GEM_GPU_DOMAINS)
1951                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1952                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1953         intel_ring_emit(ring, cmd);
1954         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1955         if (INTEL_INFO(ring->dev)->gen >= 8) {
1956                 intel_ring_emit(ring, 0); /* upper addr */
1957                 intel_ring_emit(ring, 0); /* value */
1958         } else  {
1959                 intel_ring_emit(ring, 0);
1960                 intel_ring_emit(ring, MI_NOOP);
1961         }
1962         intel_ring_advance(ring);
1963         return 0;
1964 }
1965
1966 static int
1967 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
1968                               u64 offset, u32 len,
1969                               unsigned flags)
1970 {
1971         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1972         bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1973                 !(flags & I915_DISPATCH_SECURE);
1974         int ret;
1975
1976         ret = intel_ring_begin(ring, 4);
1977         if (ret)
1978                 return ret;
1979
1980         /* FIXME(BDW): Address space and security selectors. */
1981         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1982         intel_ring_emit(ring, lower_32_bits(offset));
1983         intel_ring_emit(ring, upper_32_bits(offset));
1984         intel_ring_emit(ring, MI_NOOP);
1985         intel_ring_advance(ring);
1986
1987         return 0;
1988 }
1989
1990 static int
1991 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
1992                               u64 offset, u32 len,
1993                               unsigned flags)
1994 {
1995         int ret;
1996
1997         ret = intel_ring_begin(ring, 2);
1998         if (ret)
1999                 return ret;
2000
2001         intel_ring_emit(ring,
2002                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
2003                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
2004         /* bit0-7 is the length on GEN6+ */
2005         intel_ring_emit(ring, offset);
2006         intel_ring_advance(ring);
2007
2008         return 0;
2009 }
2010
2011 static int
2012 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2013                               u64 offset, u32 len,
2014                               unsigned flags)
2015 {
2016         int ret;
2017
2018         ret = intel_ring_begin(ring, 2);
2019         if (ret)
2020                 return ret;
2021
2022         intel_ring_emit(ring,
2023                         MI_BATCH_BUFFER_START |
2024                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2025         /* bit0-7 is the length on GEN6+ */
2026         intel_ring_emit(ring, offset);
2027         intel_ring_advance(ring);
2028
2029         return 0;
2030 }
2031
2032 /* Blitter support (SandyBridge+) */
2033
2034 static int gen6_ring_flush(struct intel_engine_cs *ring,
2035                            u32 invalidate, u32 flush)
2036 {
2037         struct drm_device *dev = ring->dev;
2038         uint32_t cmd;
2039         int ret;
2040
2041         ret = intel_ring_begin(ring, 4);
2042         if (ret)
2043                 return ret;
2044
2045         cmd = MI_FLUSH_DW;
2046         if (INTEL_INFO(ring->dev)->gen >= 8)
2047                 cmd += 1;
2048         /*
2049          * Bspec vol 1c.3 - blitter engine command streamer:
2050          * "If ENABLED, all TLBs will be invalidated once the flush
2051          * operation is complete. This bit is only valid when the
2052          * Post-Sync Operation field is a value of 1h or 3h."
2053          */
2054         if (invalidate & I915_GEM_DOMAIN_RENDER)
2055                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2056                         MI_FLUSH_DW_OP_STOREDW;
2057         intel_ring_emit(ring, cmd);
2058         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2059         if (INTEL_INFO(ring->dev)->gen >= 8) {
2060                 intel_ring_emit(ring, 0); /* upper addr */
2061                 intel_ring_emit(ring, 0); /* value */
2062         } else  {
2063                 intel_ring_emit(ring, 0);
2064                 intel_ring_emit(ring, MI_NOOP);
2065         }
2066         intel_ring_advance(ring);
2067
2068         if (IS_GEN7(dev) && !invalidate && flush)
2069                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2070
2071         return 0;
2072 }
2073
2074 int intel_init_render_ring_buffer(struct drm_device *dev)
2075 {
2076         struct drm_i915_private *dev_priv = dev->dev_private;
2077         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2078         struct drm_i915_gem_object *obj;
2079         int ret;
2080
2081         ring->name = "render ring";
2082         ring->id = RCS;
2083         ring->mmio_base = RENDER_RING_BASE;
2084
2085         if (INTEL_INFO(dev)->gen >= 8) {
2086                 if (i915_semaphore_is_enabled(dev)) {
2087                         obj = i915_gem_alloc_object(dev, 4096);
2088                         if (obj == NULL) {
2089                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2090                                 i915.semaphores = 0;
2091                         } else {
2092                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2093                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2094                                 if (ret != 0) {
2095                                         drm_gem_object_unreference(&obj->base);
2096                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2097                                         i915.semaphores = 0;
2098                                 } else
2099                                         dev_priv->semaphore_obj = obj;
2100                         }
2101                 }
2102                 ring->add_request = gen6_add_request;
2103                 ring->flush = gen8_render_ring_flush;
2104                 ring->irq_get = gen8_ring_get_irq;
2105                 ring->irq_put = gen8_ring_put_irq;
2106                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2107                 ring->get_seqno = gen6_ring_get_seqno;
2108                 ring->set_seqno = ring_set_seqno;
2109                 if (i915_semaphore_is_enabled(dev)) {
2110                         WARN_ON(!dev_priv->semaphore_obj);
2111                         ring->semaphore.sync_to = gen8_ring_sync;
2112                         ring->semaphore.signal = gen8_rcs_signal;
2113                         GEN8_RING_SEMAPHORE_INIT;
2114                 }
2115         } else if (INTEL_INFO(dev)->gen >= 6) {
2116                 ring->add_request = gen6_add_request;
2117                 ring->flush = gen7_render_ring_flush;
2118                 if (INTEL_INFO(dev)->gen == 6)
2119                         ring->flush = gen6_render_ring_flush;
2120                 ring->irq_get = gen6_ring_get_irq;
2121                 ring->irq_put = gen6_ring_put_irq;
2122                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2123                 ring->get_seqno = gen6_ring_get_seqno;
2124                 ring->set_seqno = ring_set_seqno;
2125                 if (i915_semaphore_is_enabled(dev)) {
2126                         ring->semaphore.sync_to = gen6_ring_sync;
2127                         ring->semaphore.signal = gen6_signal;
2128                         /*
2129                          * The current semaphore is only applied on pre-gen8
2130                          * platform.  And there is no VCS2 ring on the pre-gen8
2131                          * platform. So the semaphore between RCS and VCS2 is
2132                          * initialized as INVALID.  Gen8 will initialize the
2133                          * sema between VCS2 and RCS later.
2134                          */
2135                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2136                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2137                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2138                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2139                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2140                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2141                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2142                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2143                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2144                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2145                 }
2146         } else if (IS_GEN5(dev)) {
2147                 ring->add_request = pc_render_add_request;
2148                 ring->flush = gen4_render_ring_flush;
2149                 ring->get_seqno = pc_render_get_seqno;
2150                 ring->set_seqno = pc_render_set_seqno;
2151                 ring->irq_get = gen5_ring_get_irq;
2152                 ring->irq_put = gen5_ring_put_irq;
2153                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2154                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2155         } else {
2156                 ring->add_request = i9xx_add_request;
2157                 if (INTEL_INFO(dev)->gen < 4)
2158                         ring->flush = gen2_render_ring_flush;
2159                 else
2160                         ring->flush = gen4_render_ring_flush;
2161                 ring->get_seqno = ring_get_seqno;
2162                 ring->set_seqno = ring_set_seqno;
2163                 if (IS_GEN2(dev)) {
2164                         ring->irq_get = i8xx_ring_get_irq;
2165                         ring->irq_put = i8xx_ring_put_irq;
2166                 } else {
2167                         ring->irq_get = i9xx_ring_get_irq;
2168                         ring->irq_put = i9xx_ring_put_irq;
2169                 }
2170                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2171         }
2172         ring->write_tail = ring_write_tail;
2173
2174         if (IS_HASWELL(dev))
2175                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2176         else if (IS_GEN8(dev))
2177                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2178         else if (INTEL_INFO(dev)->gen >= 6)
2179                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2180         else if (INTEL_INFO(dev)->gen >= 4)
2181                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2182         else if (IS_I830(dev) || IS_845G(dev))
2183                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2184         else
2185                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2186         ring->init = init_render_ring;
2187         ring->cleanup = render_ring_cleanup;
2188
2189         /* Workaround batchbuffer to combat CS tlb bug. */
2190         if (HAS_BROKEN_CS_TLB(dev)) {
2191                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
2192                 if (obj == NULL) {
2193                         DRM_ERROR("Failed to allocate batch bo\n");
2194                         return -ENOMEM;
2195                 }
2196
2197                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2198                 if (ret != 0) {
2199                         drm_gem_object_unreference(&obj->base);
2200                         DRM_ERROR("Failed to ping batch bo\n");
2201                         return ret;
2202                 }
2203
2204                 ring->scratch.obj = obj;
2205                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2206         }
2207
2208         return intel_init_ring_buffer(dev, ring);
2209 }
2210
2211 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2212 {
2213         struct drm_i915_private *dev_priv = dev->dev_private;
2214         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2215         struct intel_ringbuffer *ringbuf = ring->buffer;
2216         int ret;
2217
2218         if (ringbuf == NULL) {
2219                 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2220                 if (!ringbuf)
2221                         return -ENOMEM;
2222                 ring->buffer = ringbuf;
2223         }
2224
2225         ring->name = "render ring";
2226         ring->id = RCS;
2227         ring->mmio_base = RENDER_RING_BASE;
2228
2229         if (INTEL_INFO(dev)->gen >= 6) {
2230                 /* non-kms not supported on gen6+ */
2231                 ret = -ENODEV;
2232                 goto err_ringbuf;
2233         }
2234
2235         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2236          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2237          * the special gen5 functions. */
2238         ring->add_request = i9xx_add_request;
2239         if (INTEL_INFO(dev)->gen < 4)
2240                 ring->flush = gen2_render_ring_flush;
2241         else
2242                 ring->flush = gen4_render_ring_flush;
2243         ring->get_seqno = ring_get_seqno;
2244         ring->set_seqno = ring_set_seqno;
2245         if (IS_GEN2(dev)) {
2246                 ring->irq_get = i8xx_ring_get_irq;
2247                 ring->irq_put = i8xx_ring_put_irq;
2248         } else {
2249                 ring->irq_get = i9xx_ring_get_irq;
2250                 ring->irq_put = i9xx_ring_put_irq;
2251         }
2252         ring->irq_enable_mask = I915_USER_INTERRUPT;
2253         ring->write_tail = ring_write_tail;
2254         if (INTEL_INFO(dev)->gen >= 4)
2255                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2256         else if (IS_I830(dev) || IS_845G(dev))
2257                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2258         else
2259                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2260         ring->init = init_render_ring;
2261         ring->cleanup = render_ring_cleanup;
2262
2263         ring->dev = dev;
2264         INIT_LIST_HEAD(&ring->active_list);
2265         INIT_LIST_HEAD(&ring->request_list);
2266
2267         ringbuf->size = size;
2268         ringbuf->effective_size = ringbuf->size;
2269         if (IS_I830(ring->dev) || IS_845G(ring->dev))
2270                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2271
2272         ringbuf->virtual_start = ioremap_wc(start, size);
2273         if (ringbuf->virtual_start == NULL) {
2274                 DRM_ERROR("can not ioremap virtual address for"
2275                           " ring buffer\n");
2276                 ret = -ENOMEM;
2277                 goto err_ringbuf;
2278         }
2279
2280         if (!I915_NEED_GFX_HWS(dev)) {
2281                 ret = init_phys_status_page(ring);
2282                 if (ret)
2283                         goto err_vstart;
2284         }
2285
2286         return 0;
2287
2288 err_vstart:
2289         iounmap(ringbuf->virtual_start);
2290 err_ringbuf:
2291         kfree(ringbuf);
2292         ring->buffer = NULL;
2293         return ret;
2294 }
2295
2296 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2297 {
2298         struct drm_i915_private *dev_priv = dev->dev_private;
2299         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2300
2301         ring->name = "bsd ring";
2302         ring->id = VCS;
2303
2304         ring->write_tail = ring_write_tail;
2305         if (INTEL_INFO(dev)->gen >= 6) {
2306                 ring->mmio_base = GEN6_BSD_RING_BASE;
2307                 /* gen6 bsd needs a special wa for tail updates */
2308                 if (IS_GEN6(dev))
2309                         ring->write_tail = gen6_bsd_ring_write_tail;
2310                 ring->flush = gen6_bsd_ring_flush;
2311                 ring->add_request = gen6_add_request;
2312                 ring->get_seqno = gen6_ring_get_seqno;
2313                 ring->set_seqno = ring_set_seqno;
2314                 if (INTEL_INFO(dev)->gen >= 8) {
2315                         ring->irq_enable_mask =
2316                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2317                         ring->irq_get = gen8_ring_get_irq;
2318                         ring->irq_put = gen8_ring_put_irq;
2319                         ring->dispatch_execbuffer =
2320                                 gen8_ring_dispatch_execbuffer;
2321                         if (i915_semaphore_is_enabled(dev)) {
2322                                 ring->semaphore.sync_to = gen8_ring_sync;
2323                                 ring->semaphore.signal = gen8_xcs_signal;
2324                                 GEN8_RING_SEMAPHORE_INIT;
2325                         }
2326                 } else {
2327                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2328                         ring->irq_get = gen6_ring_get_irq;
2329                         ring->irq_put = gen6_ring_put_irq;
2330                         ring->dispatch_execbuffer =
2331                                 gen6_ring_dispatch_execbuffer;
2332                         if (i915_semaphore_is_enabled(dev)) {
2333                                 ring->semaphore.sync_to = gen6_ring_sync;
2334                                 ring->semaphore.signal = gen6_signal;
2335                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2336                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2337                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2338                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2339                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2340                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2341                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2342                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2343                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2344                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2345                         }
2346                 }
2347         } else {
2348                 ring->mmio_base = BSD_RING_BASE;
2349                 ring->flush = bsd_ring_flush;
2350                 ring->add_request = i9xx_add_request;
2351                 ring->get_seqno = ring_get_seqno;
2352                 ring->set_seqno = ring_set_seqno;
2353                 if (IS_GEN5(dev)) {
2354                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2355                         ring->irq_get = gen5_ring_get_irq;
2356                         ring->irq_put = gen5_ring_put_irq;
2357                 } else {
2358                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2359                         ring->irq_get = i9xx_ring_get_irq;
2360                         ring->irq_put = i9xx_ring_put_irq;
2361                 }
2362                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2363         }
2364         ring->init = init_ring_common;
2365
2366         return intel_init_ring_buffer(dev, ring);
2367 }
2368
2369 /**
2370  * Initialize the second BSD ring for Broadwell GT3.
2371  * It is noted that this only exists on Broadwell GT3.
2372  */
2373 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2374 {
2375         struct drm_i915_private *dev_priv = dev->dev_private;
2376         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2377
2378         if ((INTEL_INFO(dev)->gen != 8)) {
2379                 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2380                 return -EINVAL;
2381         }
2382
2383         ring->name = "bsd2 ring";
2384         ring->id = VCS2;
2385
2386         ring->write_tail = ring_write_tail;
2387         ring->mmio_base = GEN8_BSD2_RING_BASE;
2388         ring->flush = gen6_bsd_ring_flush;
2389         ring->add_request = gen6_add_request;
2390         ring->get_seqno = gen6_ring_get_seqno;
2391         ring->set_seqno = ring_set_seqno;
2392         ring->irq_enable_mask =
2393                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2394         ring->irq_get = gen8_ring_get_irq;
2395         ring->irq_put = gen8_ring_put_irq;
2396         ring->dispatch_execbuffer =
2397                         gen8_ring_dispatch_execbuffer;
2398         if (i915_semaphore_is_enabled(dev)) {
2399                 ring->semaphore.sync_to = gen8_ring_sync;
2400                 ring->semaphore.signal = gen8_xcs_signal;
2401                 GEN8_RING_SEMAPHORE_INIT;
2402         }
2403         ring->init = init_ring_common;
2404
2405         return intel_init_ring_buffer(dev, ring);
2406 }
2407
2408 int intel_init_blt_ring_buffer(struct drm_device *dev)
2409 {
2410         struct drm_i915_private *dev_priv = dev->dev_private;
2411         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2412
2413         ring->name = "blitter ring";
2414         ring->id = BCS;
2415
2416         ring->mmio_base = BLT_RING_BASE;
2417         ring->write_tail = ring_write_tail;
2418         ring->flush = gen6_ring_flush;
2419         ring->add_request = gen6_add_request;
2420         ring->get_seqno = gen6_ring_get_seqno;
2421         ring->set_seqno = ring_set_seqno;
2422         if (INTEL_INFO(dev)->gen >= 8) {
2423                 ring->irq_enable_mask =
2424                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2425                 ring->irq_get = gen8_ring_get_irq;
2426                 ring->irq_put = gen8_ring_put_irq;
2427                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2428                 if (i915_semaphore_is_enabled(dev)) {
2429                         ring->semaphore.sync_to = gen8_ring_sync;
2430                         ring->semaphore.signal = gen8_xcs_signal;
2431                         GEN8_RING_SEMAPHORE_INIT;
2432                 }
2433         } else {
2434                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2435                 ring->irq_get = gen6_ring_get_irq;
2436                 ring->irq_put = gen6_ring_put_irq;
2437                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2438                 if (i915_semaphore_is_enabled(dev)) {
2439                         ring->semaphore.signal = gen6_signal;
2440                         ring->semaphore.sync_to = gen6_ring_sync;
2441                         /*
2442                          * The current semaphore is only applied on pre-gen8
2443                          * platform.  And there is no VCS2 ring on the pre-gen8
2444                          * platform. So the semaphore between BCS and VCS2 is
2445                          * initialized as INVALID.  Gen8 will initialize the
2446                          * sema between BCS and VCS2 later.
2447                          */
2448                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2449                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2450                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2451                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2452                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2453                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2454                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2455                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2456                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2457                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2458                 }
2459         }
2460         ring->init = init_ring_common;
2461
2462         return intel_init_ring_buffer(dev, ring);
2463 }
2464
2465 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2466 {
2467         struct drm_i915_private *dev_priv = dev->dev_private;
2468         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2469
2470         ring->name = "video enhancement ring";
2471         ring->id = VECS;
2472
2473         ring->mmio_base = VEBOX_RING_BASE;
2474         ring->write_tail = ring_write_tail;
2475         ring->flush = gen6_ring_flush;
2476         ring->add_request = gen6_add_request;
2477         ring->get_seqno = gen6_ring_get_seqno;
2478         ring->set_seqno = ring_set_seqno;
2479
2480         if (INTEL_INFO(dev)->gen >= 8) {
2481                 ring->irq_enable_mask =
2482                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2483                 ring->irq_get = gen8_ring_get_irq;
2484                 ring->irq_put = gen8_ring_put_irq;
2485                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2486                 if (i915_semaphore_is_enabled(dev)) {
2487                         ring->semaphore.sync_to = gen8_ring_sync;
2488                         ring->semaphore.signal = gen8_xcs_signal;
2489                         GEN8_RING_SEMAPHORE_INIT;
2490                 }
2491         } else {
2492                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2493                 ring->irq_get = hsw_vebox_get_irq;
2494                 ring->irq_put = hsw_vebox_put_irq;
2495                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2496                 if (i915_semaphore_is_enabled(dev)) {
2497                         ring->semaphore.sync_to = gen6_ring_sync;
2498                         ring->semaphore.signal = gen6_signal;
2499                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2500                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2501                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2502                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2503                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2504                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2505                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2506                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2507                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2508                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2509                 }
2510         }
2511         ring->init = init_ring_common;
2512
2513         return intel_init_ring_buffer(dev, ring);
2514 }
2515
2516 int
2517 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2518 {
2519         int ret;
2520
2521         if (!ring->gpu_caches_dirty)
2522                 return 0;
2523
2524         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2525         if (ret)
2526                 return ret;
2527
2528         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2529
2530         ring->gpu_caches_dirty = false;
2531         return 0;
2532 }
2533
2534 int
2535 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2536 {
2537         uint32_t flush_domains;
2538         int ret;
2539
2540         flush_domains = 0;
2541         if (ring->gpu_caches_dirty)
2542                 flush_domains = I915_GEM_GPU_DOMAINS;
2543
2544         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2545         if (ret)
2546                 return ret;
2547
2548         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2549
2550         ring->gpu_caches_dirty = false;
2551         return 0;
2552 }
2553
2554 void
2555 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2556 {
2557         int ret;
2558
2559         if (!intel_ring_initialized(ring))
2560                 return;
2561
2562         ret = intel_ring_idle(ring);
2563         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2564                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2565                           ring->name, ret);
2566
2567         stop_ring(ring);
2568 }