2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
47 static inline int ring_space(struct intel_ring_buffer *ring)
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
56 render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
60 struct drm_device *dev = ring->dev;
67 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
68 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
69 * also flushed at 2d versus 3d pipeline switches.
73 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
74 * MI_READ_FLUSH is set, and is always flushed on 965.
76 * I915_GEM_DOMAIN_COMMAND may not exist?
78 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
79 * invalidated when MI_EXE_FLUSH is set.
81 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
82 * invalidated with every MI_FLUSH.
86 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
87 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
88 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
89 * are flushed at any MI_FLUSH.
92 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
93 if ((invalidate_domains|flush_domains) &
94 I915_GEM_DOMAIN_RENDER)
95 cmd &= ~MI_NO_WRITE_FLUSH;
96 if (INTEL_INFO(dev)->gen < 4) {
98 * On the 965, the sampler cache always gets flushed
99 * and this bit is reserved.
101 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
102 cmd |= MI_READ_FLUSH;
104 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
107 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
108 (IS_G4X(dev) || IS_GEN5(dev)))
109 cmd |= MI_INVALIDATE_ISP;
111 ret = intel_ring_begin(ring, 2);
115 intel_ring_emit(ring, cmd);
116 intel_ring_emit(ring, MI_NOOP);
117 intel_ring_advance(ring);
123 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
124 * implementing two workarounds on gen6. From section 1.4.7.1
125 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
127 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
128 * produced by non-pipelined state commands), software needs to first
129 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
132 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
133 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
135 * And the workaround for these two requires this workaround first:
137 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
138 * BEFORE the pipe-control with a post-sync op and no write-cache
141 * And this last workaround is tricky because of the requirements on
142 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
145 * "1 of the following must also be set:
146 * - Render Target Cache Flush Enable ([12] of DW1)
147 * - Depth Cache Flush Enable ([0] of DW1)
148 * - Stall at Pixel Scoreboard ([1] of DW1)
149 * - Depth Stall ([13] of DW1)
150 * - Post-Sync Operation ([13] of DW1)
151 * - Notify Enable ([8] of DW1)"
153 * The cache flushes require the workaround flush that triggered this
154 * one, so we can't use it. Depth stall would trigger the same.
155 * Post-sync nonzero is what triggered this second workaround, so we
156 * can't use that one either. Notify enable is IRQs, which aren't
157 * really our business. That leaves only stall at scoreboard.
160 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
162 struct pipe_control *pc = ring->private;
163 u32 scratch_addr = pc->gtt_offset + 128;
167 ret = intel_ring_begin(ring, 6);
171 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
172 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
173 PIPE_CONTROL_STALL_AT_SCOREBOARD);
174 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
175 intel_ring_emit(ring, 0); /* low dword */
176 intel_ring_emit(ring, 0); /* high dword */
177 intel_ring_emit(ring, MI_NOOP);
178 intel_ring_advance(ring);
180 ret = intel_ring_begin(ring, 6);
184 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
185 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
186 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
187 intel_ring_emit(ring, 0);
188 intel_ring_emit(ring, 0);
189 intel_ring_emit(ring, MI_NOOP);
190 intel_ring_advance(ring);
196 gen6_render_ring_flush(struct intel_ring_buffer *ring,
197 u32 invalidate_domains, u32 flush_domains)
200 struct pipe_control *pc = ring->private;
201 u32 scratch_addr = pc->gtt_offset + 128;
204 /* Force SNB workarounds for PIPE_CONTROL flushes */
205 intel_emit_post_sync_nonzero_flush(ring);
207 /* Just flush everything. Experiments have shown that reducing the
208 * number of bits based on the write domains has little performance
211 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
212 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
213 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
214 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
215 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
216 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
217 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
219 ret = intel_ring_begin(ring, 6);
223 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
224 intel_ring_emit(ring, flags);
225 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
226 intel_ring_emit(ring, 0); /* lower dword */
227 intel_ring_emit(ring, 0); /* uppwer dword */
228 intel_ring_emit(ring, MI_NOOP);
229 intel_ring_advance(ring);
234 static void ring_write_tail(struct intel_ring_buffer *ring,
237 drm_i915_private_t *dev_priv = ring->dev->dev_private;
238 I915_WRITE_TAIL(ring, value);
241 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
243 drm_i915_private_t *dev_priv = ring->dev->dev_private;
244 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
245 RING_ACTHD(ring->mmio_base) : ACTHD;
247 return I915_READ(acthd_reg);
250 static int init_ring_common(struct intel_ring_buffer *ring)
252 struct drm_device *dev = ring->dev;
253 drm_i915_private_t *dev_priv = dev->dev_private;
254 struct drm_i915_gem_object *obj = ring->obj;
258 if (HAS_FORCE_WAKE(dev))
259 gen6_gt_force_wake_get(dev_priv);
261 /* Stop the ring if it's running. */
262 I915_WRITE_CTL(ring, 0);
263 I915_WRITE_HEAD(ring, 0);
264 ring->write_tail(ring, 0);
266 head = I915_READ_HEAD(ring) & HEAD_ADDR;
268 /* G45 ring initialization fails to reset head to zero */
270 DRM_DEBUG_KMS("%s head not reset to zero "
271 "ctl %08x head %08x tail %08x start %08x\n",
274 I915_READ_HEAD(ring),
275 I915_READ_TAIL(ring),
276 I915_READ_START(ring));
278 I915_WRITE_HEAD(ring, 0);
280 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
281 DRM_ERROR("failed to set %s head to zero "
282 "ctl %08x head %08x tail %08x start %08x\n",
285 I915_READ_HEAD(ring),
286 I915_READ_TAIL(ring),
287 I915_READ_START(ring));
291 /* Initialize the ring. This must happen _after_ we've cleared the ring
292 * registers with the above sequence (the readback of the HEAD registers
293 * also enforces ordering), otherwise the hw might lose the new ring
294 * register values. */
295 I915_WRITE_START(ring, obj->gtt_offset);
297 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
300 /* If the head is still not zero, the ring is dead */
301 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
302 I915_READ_START(ring) == obj->gtt_offset &&
303 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
304 DRM_ERROR("%s initialization failed "
305 "ctl %08x head %08x tail %08x start %08x\n",
308 I915_READ_HEAD(ring),
309 I915_READ_TAIL(ring),
310 I915_READ_START(ring));
315 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
316 i915_kernel_lost_context(ring->dev);
318 ring->head = I915_READ_HEAD(ring);
319 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
320 ring->space = ring_space(ring);
324 if (HAS_FORCE_WAKE(dev))
325 gen6_gt_force_wake_put(dev_priv);
331 init_pipe_control(struct intel_ring_buffer *ring)
333 struct pipe_control *pc;
334 struct drm_i915_gem_object *obj;
340 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
344 obj = i915_gem_alloc_object(ring->dev, 4096);
346 DRM_ERROR("Failed to allocate seqno page\n");
351 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
353 ret = i915_gem_object_pin(obj, 4096, true);
357 pc->gtt_offset = obj->gtt_offset;
358 pc->cpu_page = kmap(obj->pages[0]);
359 if (pc->cpu_page == NULL)
367 i915_gem_object_unpin(obj);
369 drm_gem_object_unreference(&obj->base);
376 cleanup_pipe_control(struct intel_ring_buffer *ring)
378 struct pipe_control *pc = ring->private;
379 struct drm_i915_gem_object *obj;
385 kunmap(obj->pages[0]);
386 i915_gem_object_unpin(obj);
387 drm_gem_object_unreference(&obj->base);
390 ring->private = NULL;
393 static int init_render_ring(struct intel_ring_buffer *ring)
395 struct drm_device *dev = ring->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 int ret = init_ring_common(ring);
399 if (INTEL_INFO(dev)->gen > 3) {
400 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
401 I915_WRITE(MI_MODE, mode);
404 /* We need to disable the AsyncFlip performance optimisations in order
405 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
406 * programmed to '1' on all products.
408 if (INTEL_INFO(dev)->gen >= 6)
409 I915_WRITE(MI_MODE, GFX_MODE_ENABLE(ASYNC_FLIP_PERF_DISABLE));
412 I915_WRITE(GFX_MODE_GEN7,
413 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
414 GFX_MODE_ENABLE(GFX_REPLAY_MODE));
416 if (INTEL_INFO(dev)->gen >= 5) {
417 ret = init_pipe_control(ring);
424 /* From the Sandybridge PRM, volume 1 part 3, page 24:
425 * "If this bit is set, STCunit will have LRA as replacement
426 * policy. [...] This bit must be reset. LRA replacement
427 * policy is not supported."
429 I915_WRITE(CACHE_MODE_0,
430 CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
433 if (INTEL_INFO(dev)->gen >= 6) {
435 INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
441 static void render_ring_cleanup(struct intel_ring_buffer *ring)
446 cleanup_pipe_control(ring);
450 update_mboxes(struct intel_ring_buffer *ring,
454 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
455 MI_SEMAPHORE_GLOBAL_GTT |
456 MI_SEMAPHORE_REGISTER |
457 MI_SEMAPHORE_UPDATE);
458 intel_ring_emit(ring, seqno);
459 intel_ring_emit(ring, mmio_offset);
463 * gen6_add_request - Update the semaphore mailbox registers
465 * @ring - ring that is adding a request
466 * @seqno - return seqno stuck into the ring
468 * Update the mailbox registers in the *other* rings with the current seqno.
469 * This acts like a signal in the canonical semaphore.
472 gen6_add_request(struct intel_ring_buffer *ring,
479 ret = intel_ring_begin(ring, 10);
483 mbox1_reg = ring->signal_mbox[0];
484 mbox2_reg = ring->signal_mbox[1];
486 *seqno = i915_gem_next_request_seqno(ring);
488 update_mboxes(ring, *seqno, mbox1_reg);
489 update_mboxes(ring, *seqno, mbox2_reg);
490 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
491 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
492 intel_ring_emit(ring, *seqno);
493 intel_ring_emit(ring, MI_USER_INTERRUPT);
494 intel_ring_advance(ring);
500 * intel_ring_sync - sync the waiter to the signaller on seqno
502 * @waiter - ring that is waiting
503 * @signaller - ring which has, or will signal
504 * @seqno - seqno which the waiter will block on
507 intel_ring_sync(struct intel_ring_buffer *waiter,
508 struct intel_ring_buffer *signaller,
513 u32 dw1 = MI_SEMAPHORE_MBOX |
514 MI_SEMAPHORE_COMPARE |
515 MI_SEMAPHORE_REGISTER;
517 ret = intel_ring_begin(waiter, 4);
521 intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
522 intel_ring_emit(waiter, seqno);
523 intel_ring_emit(waiter, 0);
524 intel_ring_emit(waiter, MI_NOOP);
525 intel_ring_advance(waiter);
530 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
532 render_ring_sync_to(struct intel_ring_buffer *waiter,
533 struct intel_ring_buffer *signaller,
536 WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
537 return intel_ring_sync(waiter,
543 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
545 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
546 struct intel_ring_buffer *signaller,
549 WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
550 return intel_ring_sync(waiter,
556 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
558 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
559 struct intel_ring_buffer *signaller,
562 WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
563 return intel_ring_sync(waiter,
571 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
573 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
574 PIPE_CONTROL_DEPTH_STALL); \
575 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
576 intel_ring_emit(ring__, 0); \
577 intel_ring_emit(ring__, 0); \
581 pc_render_add_request(struct intel_ring_buffer *ring,
584 u32 seqno = i915_gem_next_request_seqno(ring);
585 struct pipe_control *pc = ring->private;
586 u32 scratch_addr = pc->gtt_offset + 128;
589 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
590 * incoherent with writes to memory, i.e. completely fubar,
591 * so we need to use PIPE_NOTIFY instead.
593 * However, we also need to workaround the qword write
594 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
595 * memory before requesting an interrupt.
597 ret = intel_ring_begin(ring, 32);
601 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
602 PIPE_CONTROL_WRITE_FLUSH |
603 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
604 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
605 intel_ring_emit(ring, seqno);
606 intel_ring_emit(ring, 0);
607 PIPE_CONTROL_FLUSH(ring, scratch_addr);
608 scratch_addr += 128; /* write to separate cachelines */
609 PIPE_CONTROL_FLUSH(ring, scratch_addr);
611 PIPE_CONTROL_FLUSH(ring, scratch_addr);
613 PIPE_CONTROL_FLUSH(ring, scratch_addr);
615 PIPE_CONTROL_FLUSH(ring, scratch_addr);
617 PIPE_CONTROL_FLUSH(ring, scratch_addr);
618 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
619 PIPE_CONTROL_WRITE_FLUSH |
620 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
621 PIPE_CONTROL_NOTIFY);
622 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
623 intel_ring_emit(ring, seqno);
624 intel_ring_emit(ring, 0);
625 intel_ring_advance(ring);
632 render_ring_add_request(struct intel_ring_buffer *ring,
635 u32 seqno = i915_gem_next_request_seqno(ring);
638 ret = intel_ring_begin(ring, 4);
642 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
643 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
644 intel_ring_emit(ring, seqno);
645 intel_ring_emit(ring, MI_USER_INTERRUPT);
646 intel_ring_advance(ring);
653 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
655 struct drm_device *dev = ring->dev;
657 /* Workaround to force correct ordering between irq and seqno writes on
658 * ivb (and maybe also on snb) by reading from a CS register (like
659 * ACTHD) before reading the status page. */
661 intel_ring_get_active_head(ring);
662 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
666 ring_get_seqno(struct intel_ring_buffer *ring)
668 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
672 pc_render_get_seqno(struct intel_ring_buffer *ring)
674 struct pipe_control *pc = ring->private;
675 return pc->cpu_page[0];
679 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
681 dev_priv->gt_irq_mask &= ~mask;
682 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
687 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
689 dev_priv->gt_irq_mask |= mask;
690 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
695 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
697 dev_priv->irq_mask &= ~mask;
698 I915_WRITE(IMR, dev_priv->irq_mask);
703 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
705 dev_priv->irq_mask |= mask;
706 I915_WRITE(IMR, dev_priv->irq_mask);
711 render_ring_get_irq(struct intel_ring_buffer *ring)
713 struct drm_device *dev = ring->dev;
714 drm_i915_private_t *dev_priv = dev->dev_private;
716 if (!dev->irq_enabled)
719 spin_lock(&ring->irq_lock);
720 if (ring->irq_refcount++ == 0) {
721 if (HAS_PCH_SPLIT(dev))
722 ironlake_enable_irq(dev_priv,
723 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
725 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
727 spin_unlock(&ring->irq_lock);
733 render_ring_put_irq(struct intel_ring_buffer *ring)
735 struct drm_device *dev = ring->dev;
736 drm_i915_private_t *dev_priv = dev->dev_private;
738 spin_lock(&ring->irq_lock);
739 if (--ring->irq_refcount == 0) {
740 if (HAS_PCH_SPLIT(dev))
741 ironlake_disable_irq(dev_priv,
745 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
747 spin_unlock(&ring->irq_lock);
750 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
752 struct drm_device *dev = ring->dev;
753 drm_i915_private_t *dev_priv = ring->dev->dev_private;
756 /* The ring status page addresses are no longer next to the rest of
757 * the ring registers as of gen7.
762 mmio = RENDER_HWS_PGA_GEN7;
765 mmio = BLT_HWS_PGA_GEN7;
768 mmio = BSD_HWS_PGA_GEN7;
771 } else if (IS_GEN6(ring->dev)) {
772 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
774 mmio = RING_HWS_PGA(ring->mmio_base);
777 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
782 bsd_ring_flush(struct intel_ring_buffer *ring,
783 u32 invalidate_domains,
788 ret = intel_ring_begin(ring, 2);
792 intel_ring_emit(ring, MI_FLUSH);
793 intel_ring_emit(ring, MI_NOOP);
794 intel_ring_advance(ring);
799 ring_add_request(struct intel_ring_buffer *ring,
805 ret = intel_ring_begin(ring, 4);
809 seqno = i915_gem_next_request_seqno(ring);
811 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
812 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
813 intel_ring_emit(ring, seqno);
814 intel_ring_emit(ring, MI_USER_INTERRUPT);
815 intel_ring_advance(ring);
822 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
824 struct drm_device *dev = ring->dev;
825 drm_i915_private_t *dev_priv = dev->dev_private;
827 if (!dev->irq_enabled)
830 /* It looks like we need to prevent the gt from suspending while waiting
831 * for an notifiy irq, otherwise irqs seem to get lost on at least the
832 * blt/bsd rings on ivb. */
834 gen6_gt_force_wake_get(dev_priv);
836 spin_lock(&ring->irq_lock);
837 if (ring->irq_refcount++ == 0) {
838 ring->irq_mask &= ~rflag;
839 I915_WRITE_IMR(ring, ring->irq_mask);
840 ironlake_enable_irq(dev_priv, gflag);
842 spin_unlock(&ring->irq_lock);
848 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
850 struct drm_device *dev = ring->dev;
851 drm_i915_private_t *dev_priv = dev->dev_private;
853 spin_lock(&ring->irq_lock);
854 if (--ring->irq_refcount == 0) {
855 ring->irq_mask |= rflag;
856 I915_WRITE_IMR(ring, ring->irq_mask);
857 ironlake_disable_irq(dev_priv, gflag);
859 spin_unlock(&ring->irq_lock);
862 gen6_gt_force_wake_put(dev_priv);
866 bsd_ring_get_irq(struct intel_ring_buffer *ring)
868 struct drm_device *dev = ring->dev;
869 drm_i915_private_t *dev_priv = dev->dev_private;
871 if (!dev->irq_enabled)
874 spin_lock(&ring->irq_lock);
875 if (ring->irq_refcount++ == 0) {
877 i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
879 ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
881 spin_unlock(&ring->irq_lock);
886 bsd_ring_put_irq(struct intel_ring_buffer *ring)
888 struct drm_device *dev = ring->dev;
889 drm_i915_private_t *dev_priv = dev->dev_private;
891 spin_lock(&ring->irq_lock);
892 if (--ring->irq_refcount == 0) {
894 i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
896 ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
898 spin_unlock(&ring->irq_lock);
902 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
906 ret = intel_ring_begin(ring, 2);
910 intel_ring_emit(ring,
911 MI_BATCH_BUFFER_START | (2 << 6) |
912 MI_BATCH_NON_SECURE_I965);
913 intel_ring_emit(ring, offset);
914 intel_ring_advance(ring);
920 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
923 struct drm_device *dev = ring->dev;
926 if (IS_I830(dev) || IS_845G(dev)) {
927 ret = intel_ring_begin(ring, 4);
931 intel_ring_emit(ring, MI_BATCH_BUFFER);
932 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
933 intel_ring_emit(ring, offset + len - 8);
934 intel_ring_emit(ring, 0);
936 ret = intel_ring_begin(ring, 2);
940 if (INTEL_INFO(dev)->gen >= 4) {
941 intel_ring_emit(ring,
942 MI_BATCH_BUFFER_START | (2 << 6) |
943 MI_BATCH_NON_SECURE_I965);
944 intel_ring_emit(ring, offset);
946 intel_ring_emit(ring,
947 MI_BATCH_BUFFER_START | (2 << 6));
948 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
951 intel_ring_advance(ring);
956 static void cleanup_status_page(struct intel_ring_buffer *ring)
958 drm_i915_private_t *dev_priv = ring->dev->dev_private;
959 struct drm_i915_gem_object *obj;
961 obj = ring->status_page.obj;
965 kunmap(obj->pages[0]);
966 i915_gem_object_unpin(obj);
967 drm_gem_object_unreference(&obj->base);
968 ring->status_page.obj = NULL;
970 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
973 static int init_status_page(struct intel_ring_buffer *ring)
975 struct drm_device *dev = ring->dev;
976 drm_i915_private_t *dev_priv = dev->dev_private;
977 struct drm_i915_gem_object *obj;
980 obj = i915_gem_alloc_object(dev, 4096);
982 DRM_ERROR("Failed to allocate status page\n");
987 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
989 ret = i915_gem_object_pin(obj, 4096, true);
994 ring->status_page.gfx_addr = obj->gtt_offset;
995 ring->status_page.page_addr = kmap(obj->pages[0]);
996 if (ring->status_page.page_addr == NULL) {
997 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
1000 ring->status_page.obj = obj;
1001 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1003 intel_ring_setup_status_page(ring);
1004 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1005 ring->name, ring->status_page.gfx_addr);
1010 i915_gem_object_unpin(obj);
1012 drm_gem_object_unreference(&obj->base);
1017 int intel_init_ring_buffer(struct drm_device *dev,
1018 struct intel_ring_buffer *ring)
1020 struct drm_i915_gem_object *obj;
1024 INIT_LIST_HEAD(&ring->active_list);
1025 INIT_LIST_HEAD(&ring->request_list);
1026 INIT_LIST_HEAD(&ring->gpu_write_list);
1028 init_waitqueue_head(&ring->irq_queue);
1029 spin_lock_init(&ring->irq_lock);
1030 ring->irq_mask = ~0;
1032 if (I915_NEED_GFX_HWS(dev)) {
1033 ret = init_status_page(ring);
1038 obj = i915_gem_alloc_object(dev, ring->size);
1040 DRM_ERROR("Failed to allocate ringbuffer\n");
1047 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1051 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1055 ring->map.size = ring->size;
1056 ring->map.offset = dev->agp->base + obj->gtt_offset;
1058 ring->map.flags = 0;
1061 drm_core_ioremap_wc(&ring->map, dev);
1062 if (ring->map.handle == NULL) {
1063 DRM_ERROR("Failed to map ringbuffer.\n");
1068 ring->virtual_start = ring->map.handle;
1069 ret = ring->init(ring);
1073 /* Workaround an erratum on the i830 which causes a hang if
1074 * the TAIL pointer points to within the last 2 cachelines
1077 ring->effective_size = ring->size;
1078 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1079 ring->effective_size -= 128;
1084 drm_core_ioremapfree(&ring->map, dev);
1086 i915_gem_object_unpin(obj);
1088 drm_gem_object_unreference(&obj->base);
1091 cleanup_status_page(ring);
1095 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1097 struct drm_i915_private *dev_priv;
1100 if (ring->obj == NULL)
1103 /* Disable the ring buffer. The ring must be idle at this point */
1104 dev_priv = ring->dev->dev_private;
1105 ret = intel_wait_ring_idle(ring);
1107 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1110 I915_WRITE_CTL(ring, 0);
1112 drm_core_ioremapfree(&ring->map, ring->dev);
1114 i915_gem_object_unpin(ring->obj);
1115 drm_gem_object_unreference(&ring->obj->base);
1119 ring->cleanup(ring);
1121 cleanup_status_page(ring);
1124 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1127 int rem = ring->size - ring->tail;
1129 if (ring->space < rem) {
1130 int ret = intel_wait_ring_buffer(ring, rem);
1135 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1143 ring->space = ring_space(ring);
1148 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1150 struct drm_device *dev = ring->dev;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1154 trace_i915_ring_wait_begin(ring);
1155 end = jiffies + 3 * HZ;
1157 ring->head = I915_READ_HEAD(ring);
1158 ring->space = ring_space(ring);
1159 if (ring->space >= n) {
1160 trace_i915_ring_wait_end(ring);
1164 if (dev->primary->master) {
1165 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1166 if (master_priv->sarea_priv)
1167 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1171 if (atomic_read(&dev_priv->mm.wedged))
1173 } while (!time_after(jiffies, end));
1174 trace_i915_ring_wait_end(ring);
1178 int intel_ring_begin(struct intel_ring_buffer *ring,
1181 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1182 int n = 4*num_dwords;
1185 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1188 if (unlikely(ring->tail + n > ring->effective_size)) {
1189 ret = intel_wrap_ring_buffer(ring);
1194 if (unlikely(ring->space < n)) {
1195 ret = intel_wait_ring_buffer(ring, n);
1204 void intel_ring_advance(struct intel_ring_buffer *ring)
1206 ring->tail &= ring->size - 1;
1207 ring->write_tail(ring, ring->tail);
1210 static const struct intel_ring_buffer render_ring = {
1211 .name = "render ring",
1213 .mmio_base = RENDER_RING_BASE,
1214 .size = 32 * PAGE_SIZE,
1215 .init = init_render_ring,
1216 .write_tail = ring_write_tail,
1217 .flush = render_ring_flush,
1218 .add_request = render_ring_add_request,
1219 .get_seqno = ring_get_seqno,
1220 .irq_get = render_ring_get_irq,
1221 .irq_put = render_ring_put_irq,
1222 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
1223 .cleanup = render_ring_cleanup,
1224 .sync_to = render_ring_sync_to,
1225 .semaphore_register = {MI_SEMAPHORE_SYNC_INVALID,
1226 MI_SEMAPHORE_SYNC_RV,
1227 MI_SEMAPHORE_SYNC_RB},
1228 .signal_mbox = {GEN6_VRSYNC, GEN6_BRSYNC},
1231 /* ring buffer for bit-stream decoder */
1233 static const struct intel_ring_buffer bsd_ring = {
1236 .mmio_base = BSD_RING_BASE,
1237 .size = 32 * PAGE_SIZE,
1238 .init = init_ring_common,
1239 .write_tail = ring_write_tail,
1240 .flush = bsd_ring_flush,
1241 .add_request = ring_add_request,
1242 .get_seqno = ring_get_seqno,
1243 .irq_get = bsd_ring_get_irq,
1244 .irq_put = bsd_ring_put_irq,
1245 .dispatch_execbuffer = ring_dispatch_execbuffer,
1249 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1252 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1254 /* Every tail move must follow the sequence below */
1255 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1256 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1257 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1258 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1260 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1261 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1263 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1265 I915_WRITE_TAIL(ring, value);
1266 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1267 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1268 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1271 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1272 u32 invalidate, u32 flush)
1277 ret = intel_ring_begin(ring, 4);
1282 if (invalidate & I915_GEM_GPU_DOMAINS)
1283 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1284 intel_ring_emit(ring, cmd);
1285 intel_ring_emit(ring, 0);
1286 intel_ring_emit(ring, 0);
1287 intel_ring_emit(ring, MI_NOOP);
1288 intel_ring_advance(ring);
1293 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1294 u32 offset, u32 len)
1298 ret = intel_ring_begin(ring, 2);
1302 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1303 /* bit0-7 is the length on GEN6+ */
1304 intel_ring_emit(ring, offset);
1305 intel_ring_advance(ring);
1311 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1313 return gen6_ring_get_irq(ring,
1315 GEN6_RENDER_USER_INTERRUPT);
1319 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1321 return gen6_ring_put_irq(ring,
1323 GEN6_RENDER_USER_INTERRUPT);
1327 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1329 return gen6_ring_get_irq(ring,
1330 GT_GEN6_BSD_USER_INTERRUPT,
1331 GEN6_BSD_USER_INTERRUPT);
1335 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1337 return gen6_ring_put_irq(ring,
1338 GT_GEN6_BSD_USER_INTERRUPT,
1339 GEN6_BSD_USER_INTERRUPT);
1342 /* ring buffer for Video Codec for Gen6+ */
1343 static const struct intel_ring_buffer gen6_bsd_ring = {
1344 .name = "gen6 bsd ring",
1346 .mmio_base = GEN6_BSD_RING_BASE,
1347 .size = 32 * PAGE_SIZE,
1348 .init = init_ring_common,
1349 .write_tail = gen6_bsd_ring_write_tail,
1350 .flush = gen6_ring_flush,
1351 .add_request = gen6_add_request,
1352 .get_seqno = gen6_ring_get_seqno,
1353 .irq_get = gen6_bsd_ring_get_irq,
1354 .irq_put = gen6_bsd_ring_put_irq,
1355 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1356 .sync_to = gen6_bsd_ring_sync_to,
1357 .semaphore_register = {MI_SEMAPHORE_SYNC_VR,
1358 MI_SEMAPHORE_SYNC_INVALID,
1359 MI_SEMAPHORE_SYNC_VB},
1360 .signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC},
1363 /* Blitter support (SandyBridge+) */
1366 blt_ring_get_irq(struct intel_ring_buffer *ring)
1368 return gen6_ring_get_irq(ring,
1369 GT_BLT_USER_INTERRUPT,
1370 GEN6_BLITTER_USER_INTERRUPT);
1374 blt_ring_put_irq(struct intel_ring_buffer *ring)
1376 gen6_ring_put_irq(ring,
1377 GT_BLT_USER_INTERRUPT,
1378 GEN6_BLITTER_USER_INTERRUPT);
1382 /* Workaround for some stepping of SNB,
1383 * each time when BLT engine ring tail moved,
1384 * the first command in the ring to be parsed
1385 * should be MI_BATCH_BUFFER_START
1387 #define NEED_BLT_WORKAROUND(dev) \
1388 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1390 static inline struct drm_i915_gem_object *
1391 to_blt_workaround(struct intel_ring_buffer *ring)
1393 return ring->private;
1396 static int blt_ring_init(struct intel_ring_buffer *ring)
1398 if (NEED_BLT_WORKAROUND(ring->dev)) {
1399 struct drm_i915_gem_object *obj;
1403 obj = i915_gem_alloc_object(ring->dev, 4096);
1407 ret = i915_gem_object_pin(obj, 4096, true);
1409 drm_gem_object_unreference(&obj->base);
1413 ptr = kmap(obj->pages[0]);
1414 *ptr++ = MI_BATCH_BUFFER_END;
1416 kunmap(obj->pages[0]);
1418 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1420 i915_gem_object_unpin(obj);
1421 drm_gem_object_unreference(&obj->base);
1425 ring->private = obj;
1428 return init_ring_common(ring);
1431 static int blt_ring_begin(struct intel_ring_buffer *ring,
1434 if (ring->private) {
1435 int ret = intel_ring_begin(ring, num_dwords+2);
1439 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1440 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1444 return intel_ring_begin(ring, 4);
1447 static int blt_ring_flush(struct intel_ring_buffer *ring,
1448 u32 invalidate, u32 flush)
1453 ret = blt_ring_begin(ring, 4);
1458 if (invalidate & I915_GEM_DOMAIN_RENDER)
1459 cmd |= MI_INVALIDATE_TLB;
1460 intel_ring_emit(ring, cmd);
1461 intel_ring_emit(ring, 0);
1462 intel_ring_emit(ring, 0);
1463 intel_ring_emit(ring, MI_NOOP);
1464 intel_ring_advance(ring);
1468 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1473 i915_gem_object_unpin(ring->private);
1474 drm_gem_object_unreference(ring->private);
1475 ring->private = NULL;
1478 static const struct intel_ring_buffer gen6_blt_ring = {
1481 .mmio_base = BLT_RING_BASE,
1482 .size = 32 * PAGE_SIZE,
1483 .init = blt_ring_init,
1484 .write_tail = ring_write_tail,
1485 .flush = blt_ring_flush,
1486 .add_request = gen6_add_request,
1487 .get_seqno = gen6_ring_get_seqno,
1488 .irq_get = blt_ring_get_irq,
1489 .irq_put = blt_ring_put_irq,
1490 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1491 .cleanup = blt_ring_cleanup,
1492 .sync_to = gen6_blt_ring_sync_to,
1493 .semaphore_register = {MI_SEMAPHORE_SYNC_BR,
1494 MI_SEMAPHORE_SYNC_BV,
1495 MI_SEMAPHORE_SYNC_INVALID},
1496 .signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC},
1499 int intel_init_render_ring_buffer(struct drm_device *dev)
1501 drm_i915_private_t *dev_priv = dev->dev_private;
1502 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1504 *ring = render_ring;
1505 if (INTEL_INFO(dev)->gen >= 6) {
1506 ring->add_request = gen6_add_request;
1507 ring->flush = gen6_render_ring_flush;
1508 ring->irq_get = gen6_render_ring_get_irq;
1509 ring->irq_put = gen6_render_ring_put_irq;
1510 ring->get_seqno = gen6_ring_get_seqno;
1511 } else if (IS_GEN5(dev)) {
1512 ring->add_request = pc_render_add_request;
1513 ring->get_seqno = pc_render_get_seqno;
1516 if (!I915_NEED_GFX_HWS(dev)) {
1517 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1518 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1521 return intel_init_ring_buffer(dev, ring);
1524 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1526 drm_i915_private_t *dev_priv = dev->dev_private;
1527 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1529 *ring = render_ring;
1530 if (INTEL_INFO(dev)->gen >= 6) {
1531 ring->add_request = gen6_add_request;
1532 ring->irq_get = gen6_render_ring_get_irq;
1533 ring->irq_put = gen6_render_ring_put_irq;
1534 } else if (IS_GEN5(dev)) {
1535 ring->add_request = pc_render_add_request;
1536 ring->get_seqno = pc_render_get_seqno;
1539 if (!I915_NEED_GFX_HWS(dev))
1540 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1543 INIT_LIST_HEAD(&ring->active_list);
1544 INIT_LIST_HEAD(&ring->request_list);
1545 INIT_LIST_HEAD(&ring->gpu_write_list);
1548 ring->effective_size = ring->size;
1549 if (IS_I830(ring->dev))
1550 ring->effective_size -= 128;
1552 ring->map.offset = start;
1553 ring->map.size = size;
1555 ring->map.flags = 0;
1558 drm_core_ioremap_wc(&ring->map, dev);
1559 if (ring->map.handle == NULL) {
1560 DRM_ERROR("can not ioremap virtual address for"
1565 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1569 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1571 drm_i915_private_t *dev_priv = dev->dev_private;
1572 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1574 if (IS_GEN6(dev) || IS_GEN7(dev))
1575 *ring = gen6_bsd_ring;
1579 return intel_init_ring_buffer(dev, ring);
1582 int intel_init_blt_ring_buffer(struct drm_device *dev)
1584 drm_i915_private_t *dev_priv = dev->dev_private;
1585 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1587 *ring = gen6_blt_ring;
1589 return intel_init_ring_buffer(dev, ring);