drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
  37  * but keeps the logic simple. Indeed, the whole purpose of this macro is just
  38  * to give some inclination as to some of the magic values used in the various
  39  * workarounds!
  40  */
  41 #define CACHELINE_BYTES 64
  42
  43 static inline int ring_space(struct intel_ring_buffer *ring)
  44 {
  45         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  46         if (space < 0)
  47                 space += ring->size;
  48         return space;
  49 }
  50
  51 static bool intel_ring_stopped(struct intel_ring_buffer *ring)
  52 {
  53         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  54         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  55 }
  56
  57 void __intel_ring_advance(struct intel_ring_buffer *ring)
  58 {
  59         ring->tail &= ring->size - 1;
  60         if (intel_ring_stopped(ring))
  61                 return;
  62         ring->write_tail(ring, ring->tail);
  63 }
  64
  65 static int
  66 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  67                        u32      invalidate_domains,
  68                        u32      flush_domains)
  69 {
  70         u32 cmd;
  71         int ret;
  72
  73         cmd = MI_FLUSH;
  74         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  75                 cmd |= MI_NO_WRITE_FLUSH;
  76
  77         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  78                 cmd |= MI_READ_FLUSH;
  79
  80         ret = intel_ring_begin(ring, 2);
  81         if (ret)
  82                 return ret;
  83
  84         intel_ring_emit(ring, cmd);
  85         intel_ring_emit(ring, MI_NOOP);
  86         intel_ring_advance(ring);
  87
  88         return 0;
  89 }
  90
  91 static int
  92 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  93                        u32      invalidate_domains,
  94                        u32      flush_domains)
  95 {
  96         struct drm_device *dev = ring->dev;
  97         u32 cmd;
  98         int ret;
  99
 100         /*
 101          * read/write caches:
 102          *
 103          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 104          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 105          * also flushed at 2d versus 3d pipeline switches.
 106          *
 107          * read-only caches:
 108          *
 109          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 110          * MI_READ_FLUSH is set, and is always flushed on 965.
 111          *
 112          * I915_GEM_DOMAIN_COMMAND may not exist?
 113          *
 114          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 115          * invalidated when MI_EXE_FLUSH is set.
 116          *
 117          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 118          * invalidated with every MI_FLUSH.
 119          *
 120          * TLBs:
 121          *
 122          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 123          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 124          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 125          * are flushed at any MI_FLUSH.
 126          */
 127
 128         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 129         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 130                 cmd &= ~MI_NO_WRITE_FLUSH;
 131         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 132                 cmd |= MI_EXE_FLUSH;
 133
 134         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 135             (IS_G4X(dev) || IS_GEN5(dev)))
 136                 cmd |= MI_INVALIDATE_ISP;
 137
 138         ret = intel_ring_begin(ring, 2);
 139         if (ret)
 140                 return ret;
 141
 142         intel_ring_emit(ring, cmd);
 143         intel_ring_emit(ring, MI_NOOP);
 144         intel_ring_advance(ring);
 145
 146         return 0;
 147 }
 148
 149 /**
 150  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 151  * implementing two workarounds on gen6.  From section 1.4.7.1
 152  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 153  *
 154  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 155  * produced by non-pipelined state commands), software needs to first
 156  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 157  * 0.
 158  *
 159  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 160  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 161  *
 162  * And the workaround for these two requires this workaround first:
 163  *
 164  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 165  * BEFORE the pipe-control with a post-sync op and no write-cache
 166  * flushes.
 167  *
 168  * And this last workaround is tricky because of the requirements on
 169  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 170  * volume 2 part 1:
 171  *
 172  *     "1 of the following must also be set:
 173  *      - Render Target Cache Flush Enable ([12] of DW1)
 174  *      - Depth Cache Flush Enable ([0] of DW1)
 175  *      - Stall at Pixel Scoreboard ([1] of DW1)
 176  *      - Depth Stall ([13] of DW1)
 177  *      - Post-Sync Operation ([13] of DW1)
 178  *      - Notify Enable ([8] of DW1)"
 179  *
 180  * The cache flushes require the workaround flush that triggered this
 181  * one, so we can't use it.  Depth stall would trigger the same.
 182  * Post-sync nonzero is what triggered this second workaround, so we
 183  * can't use that one either.  Notify enable is IRQs, which aren't
 184  * really our business.  That leaves only stall at scoreboard.
 185  */
 186 static int
 187 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 188 {
 189         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 190         int ret;
 191
 192
 193         ret = intel_ring_begin(ring, 6);
 194         if (ret)
 195                 return ret;
 196
 197         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 198         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 199                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 200         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 201         intel_ring_emit(ring, 0); /* low dword */
 202         intel_ring_emit(ring, 0); /* high dword */
 203         intel_ring_emit(ring, MI_NOOP);
 204         intel_ring_advance(ring);
 205
 206         ret = intel_ring_begin(ring, 6);
 207         if (ret)
 208                 return ret;
 209
 210         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 211         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 212         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 213         intel_ring_emit(ring, 0);
 214         intel_ring_emit(ring, 0);
 215         intel_ring_emit(ring, MI_NOOP);
 216         intel_ring_advance(ring);
 217
 218         return 0;
 219 }
 220
 221 static int
 222 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 223                          u32 invalidate_domains, u32 flush_domains)
 224 {
 225         u32 flags = 0;
 226         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 227         int ret;
 228
 229         /* Force SNB workarounds for PIPE_CONTROL flushes */
 230         ret = intel_emit_post_sync_nonzero_flush(ring);
 231         if (ret)
 232                 return ret;
 233
 234         /* Just flush everything.  Experiments have shown that reducing the
 235          * number of bits based on the write domains has little performance
 236          * impact.
 237          */
 238         if (flush_domains) {
 239                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 240                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 241                 /*
 242                  * Ensure that any following seqno writes only happen
 243                  * when the render cache is indeed flushed.
 244                  */
 245                 flags |= PIPE_CONTROL_CS_STALL;
 246         }
 247         if (invalidate_domains) {
 248                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 249                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 250                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 251                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 252                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 253                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 254                 /*
 255                  * TLB invalidate requires a post-sync write.
 256                  */
 257                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 258         }
 259
 260         ret = intel_ring_begin(ring, 4);
 261         if (ret)
 262                 return ret;
 263
 264         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 265         intel_ring_emit(ring, flags);
 266         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 267         intel_ring_emit(ring, 0);
 268         intel_ring_advance(ring);
 269
 270         return 0;
 271 }
 272
 273 static int
 274 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 275 {
 276         int ret;
 277
 278         ret = intel_ring_begin(ring, 4);
 279         if (ret)
 280                 return ret;
 281
 282         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 283         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 284                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 285         intel_ring_emit(ring, 0);
 286         intel_ring_emit(ring, 0);
 287         intel_ring_advance(ring);
 288
 289         return 0;
 290 }
 291
 292 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 293 {
 294         int ret;
 295
 296         if (!ring->fbc_dirty)
 297                 return 0;
 298
 299         ret = intel_ring_begin(ring, 6);
 300         if (ret)
 301                 return ret;
 302         /* WaFbcNukeOn3DBlt:ivb/hsw */
 303         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 304         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 305         intel_ring_emit(ring, value);
 306         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 307         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 308         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 309         intel_ring_advance(ring);
 310
 311         ring->fbc_dirty = false;
 312         return 0;
 313 }
 314
 315 static int
 316 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 317                        u32 invalidate_domains, u32 flush_domains)
 318 {
 319         u32 flags = 0;
 320         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 321         int ret;
 322
 323         /*
 324          * Ensure that any following seqno writes only happen when the render
 325          * cache is indeed flushed.
 326          *
 327          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 328          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 329          * don't try to be clever and just set it unconditionally.
 330          */
 331         flags |= PIPE_CONTROL_CS_STALL;
 332
 333         /* Just flush everything.  Experiments have shown that reducing the
 334          * number of bits based on the write domains has little performance
 335          * impact.
 336          */
 337         if (flush_domains) {
 338                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 339                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 340         }
 341         if (invalidate_domains) {
 342                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 343                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 344                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 345                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 346                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 347                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 348                 /*
 349                  * TLB invalidate requires a post-sync write.
 350                  */
 351                 flags |= PIPE_CONTROL_QW_WRITE;
 352                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 353
 354                 /* Workaround: we must issue a pipe_control with CS-stall bit
 355                  * set before a pipe_control command that has the state cache
 356                  * invalidate bit set. */
 357                 gen7_render_ring_cs_stall_wa(ring);
 358         }
 359
 360         ret = intel_ring_begin(ring, 4);
 361         if (ret)
 362                 return ret;
 363
 364         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 365         intel_ring_emit(ring, flags);
 366         intel_ring_emit(ring, scratch_addr);
 367         intel_ring_emit(ring, 0);
 368         intel_ring_advance(ring);
 369
 370         if (!invalidate_domains && flush_domains)
 371                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 372
 373         return 0;
 374 }
 375
 376 static int
 377 gen8_render_ring_flush(struct intel_ring_buffer *ring,
 378                        u32 invalidate_domains, u32 flush_domains)
 379 {
 380         u32 flags = 0;
 381         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 382         int ret;
 383
 384         flags |= PIPE_CONTROL_CS_STALL;
 385
 386         if (flush_domains) {
 387                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 388                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 389         }
 390         if (invalidate_domains) {
 391                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 392                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 393                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 394                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 395                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 396                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 397                 flags |= PIPE_CONTROL_QW_WRITE;
 398                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 399         }
 400
 401         ret = intel_ring_begin(ring, 6);
 402         if (ret)
 403                 return ret;
 404
 405         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 406         intel_ring_emit(ring, flags);
 407         intel_ring_emit(ring, scratch_addr);
 408         intel_ring_emit(ring, 0);
 409         intel_ring_emit(ring, 0);
 410         intel_ring_emit(ring, 0);
 411         intel_ring_advance(ring);
 412
 413         return 0;
 414
 415 }
 416
 417 static void ring_write_tail(struct intel_ring_buffer *ring,
 418                             u32 value)
 419 {
 420         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 421         I915_WRITE_TAIL(ring, value);
 422 }
 423
 424 u64 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 425 {
 426         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 427         u64 acthd;
 428
 429         if (INTEL_INFO(ring->dev)->gen >= 8)
 430                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 431                                          RING_ACTHD_UDW(ring->mmio_base));
 432         else if (INTEL_INFO(ring->dev)->gen >= 4)
 433                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 434         else
 435                 acthd = I915_READ(ACTHD);
 436
 437         return acthd;
 438 }
 439
 440 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
 441 {
 442         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 443         u32 addr;
 444
 445         addr = dev_priv->status_page_dmah->busaddr;
 446         if (INTEL_INFO(ring->dev)->gen >= 4)
 447                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 448         I915_WRITE(HWS_PGA, addr);
 449 }
 450
 451 static bool stop_ring(struct intel_ring_buffer *ring)
 452 {
 453         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 454
 455         if (!IS_GEN2(ring->dev)) {
 456                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 457                 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 458                         DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 459                         return false;
 460                 }
 461         }
 462
 463         I915_WRITE_CTL(ring, 0);
 464         I915_WRITE_HEAD(ring, 0);
 465         ring->write_tail(ring, 0);
 466
 467         if (!IS_GEN2(ring->dev)) {
 468                 (void)I915_READ_CTL(ring);
 469                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 470         }
 471
 472         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 473 }
 474
 475 static int init_ring_common(struct intel_ring_buffer *ring)
 476 {
 477         struct drm_device *dev = ring->dev;
 478         struct drm_i915_private *dev_priv = dev->dev_private;
 479         struct drm_i915_gem_object *obj = ring->obj;
 480         int ret = 0;
 481
 482         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 483
 484         if (!stop_ring(ring)) {
 485                 /* G45 ring initialization often fails to reset head to zero */
 486                 DRM_DEBUG_KMS("%s head not reset to zero "
 487                               "ctl %08x head %08x tail %08x start %08x\n",
 488                               ring->name,
 489                               I915_READ_CTL(ring),
 490                               I915_READ_HEAD(ring),
 491                               I915_READ_TAIL(ring),
 492                               I915_READ_START(ring));
 493
 494                 if (!stop_ring(ring)) {
 495                         DRM_ERROR("failed to set %s head to zero "
 496                                   "ctl %08x head %08x tail %08x start %08x\n",
 497                                   ring->name,
 498                                   I915_READ_CTL(ring),
 499                                   I915_READ_HEAD(ring),
 500                                   I915_READ_TAIL(ring),
 501                                   I915_READ_START(ring));
 502                         ret = -EIO;
 503                         goto out;
 504                 }
 505         }
 506
 507         if (I915_NEED_GFX_HWS(dev))
 508                 intel_ring_setup_status_page(ring);
 509         else
 510                 ring_setup_phys_status_page(ring);
 511
 512         /* Initialize the ring. This must happen _after_ we've cleared the ring
 513          * registers with the above sequence (the readback of the HEAD registers
 514          * also enforces ordering), otherwise the hw might lose the new ring
 515          * register values. */
 516         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 517         I915_WRITE_CTL(ring,
 518                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 519                         | RING_VALID);
 520
 521         /* If the head is still not zero, the ring is dead */
 522         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 523                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 524                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 525                 DRM_ERROR("%s initialization failed "
 526                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 527                           ring->name,
 528                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 529                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 530                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 531                 ret = -EIO;
 532                 goto out;
 533         }
 534
 535         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 536                 i915_kernel_lost_context(ring->dev);
 537         else {
 538                 ring->head = I915_READ_HEAD(ring);
 539                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 540                 ring->space = ring_space(ring);
 541                 ring->last_retired_head = -1;
 542         }
 543
 544         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 545
 546 out:
 547         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 548
 549         return ret;
 550 }
 551
 552 static int
 553 init_pipe_control(struct intel_ring_buffer *ring)
 554 {
 555         int ret;
 556
 557         if (ring->scratch.obj)
 558                 return 0;
 559
 560         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 561         if (ring->scratch.obj == NULL) {
 562                 DRM_ERROR("Failed to allocate seqno page\n");
 563                 ret = -ENOMEM;
 564                 goto err;
 565         }
 566
 567         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 568         if (ret)
 569                 goto err_unref;
 570
 571         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 572         if (ret)
 573                 goto err_unref;
 574
 575         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 576         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 577         if (ring->scratch.cpu_page == NULL) {
 578                 ret = -ENOMEM;
 579                 goto err_unpin;
 580         }
 581
 582         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 583                          ring->name, ring->scratch.gtt_offset);
 584         return 0;
 585
 586 err_unpin:
 587         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 588 err_unref:
 589         drm_gem_object_unreference(&ring->scratch.obj->base);
 590 err:
 591         return ret;
 592 }
 593
 594 static int init_render_ring(struct intel_ring_buffer *ring)
 595 {
 596         struct drm_device *dev = ring->dev;
 597         struct drm_i915_private *dev_priv = dev->dev_private;
 598         int ret = init_ring_common(ring);
 599
 600         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 601         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
 602                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 603
 604         /* We need to disable the AsyncFlip performance optimisations in order
 605          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 606          * programmed to '1' on all products.
 607          *
 608          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
 609          */
 610         if (INTEL_INFO(dev)->gen >= 6)
 611                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 612
 613         /* Required for the hardware to program scanline values for waiting */
 614         /* WaEnableFlushTlbInvalidationMode:snb */
 615         if (INTEL_INFO(dev)->gen == 6)
 616                 I915_WRITE(GFX_MODE,
 617                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 618
 619         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 620         if (IS_GEN7(dev))
 621                 I915_WRITE(GFX_MODE_GEN7,
 622                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 623                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 624
 625         if (INTEL_INFO(dev)->gen >= 5) {
 626                 ret = init_pipe_control(ring);
 627                 if (ret)
 628                         return ret;
 629         }
 630
 631         if (IS_GEN6(dev)) {
 632                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 633                  * "If this bit is set, STCunit will have LRA as replacement
 634                  *  policy. [...] This bit must be reset.  LRA replacement
 635                  *  policy is not supported."
 636                  */
 637                 I915_WRITE(CACHE_MODE_0,
 638                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 639         }
 640
 641         if (INTEL_INFO(dev)->gen >= 6)
 642                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 643
 644         if (HAS_L3_DPF(dev))
 645                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 646
 647         return ret;
 648 }
 649
 650 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 651 {
 652         struct drm_device *dev = ring->dev;
 653
 654         if (ring->scratch.obj == NULL)
 655                 return;
 656
 657         if (INTEL_INFO(dev)->gen >= 5) {
 658                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 659                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 660         }
 661
 662         drm_gem_object_unreference(&ring->scratch.obj->base);
 663         ring->scratch.obj = NULL;
 664 }
 665
 666 static int gen6_signal(struct intel_ring_buffer *signaller,
 667                        unsigned int num_dwords)
 668 {
 669         struct drm_device *dev = signaller->dev;
 670         struct drm_i915_private *dev_priv = dev->dev_private;
 671         struct intel_ring_buffer *useless;
 672         int i, ret;
 673
 674         /* NB: In order to be able to do semaphore MBOX updates for varying
 675          * number of rings, it's easiest if we round up each individual update
 676          * to a multiple of 2 (since ring updates must always be a multiple of
 677          * 2) even though the actual update only requires 3 dwords.
 678          */
 679 #define MBOX_UPDATE_DWORDS 4
 680         if (i915_semaphore_is_enabled(dev))
 681                 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
 682
 683         ret = intel_ring_begin(signaller, num_dwords);
 684         if (ret)
 685                 return ret;
 686 #undef MBOX_UPDATE_DWORDS
 687
 688         for_each_ring(useless, dev_priv, i) {
 689                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
 690                 if (mbox_reg != GEN6_NOSYNC) {
 691                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
 692                         intel_ring_emit(signaller, mbox_reg);
 693                         intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
 694                         intel_ring_emit(signaller, MI_NOOP);
 695                 } else {
 696                         intel_ring_emit(signaller, MI_NOOP);
 697                         intel_ring_emit(signaller, MI_NOOP);
 698                         intel_ring_emit(signaller, MI_NOOP);
 699                         intel_ring_emit(signaller, MI_NOOP);
 700                 }
 701         }
 702
 703         return 0;
 704 }
 705
 706 /**
 707  * gen6_add_request - Update the semaphore mailbox registers
 708  *
 709  * @ring - ring that is adding a request
 710  * @seqno - return seqno stuck into the ring
 711  *
 712  * Update the mailbox registers in the *other* rings with the current seqno.
 713  * This acts like a signal in the canonical semaphore.
 714  */
 715 static int
 716 gen6_add_request(struct intel_ring_buffer *ring)
 717 {
 718         int ret;
 719
 720         ret = ring->semaphore.signal(ring, 4);
 721         if (ret)
 722                 return ret;
 723
 724         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 725         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 726         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 727         intel_ring_emit(ring, MI_USER_INTERRUPT);
 728         __intel_ring_advance(ring);
 729
 730         return 0;
 731 }
 732
 733 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 734                                               u32 seqno)
 735 {
 736         struct drm_i915_private *dev_priv = dev->dev_private;
 737         return dev_priv->last_seqno < seqno;
 738 }
 739
 740 /**
 741  * intel_ring_sync - sync the waiter to the signaller on seqno
 742  *
 743  * @waiter - ring that is waiting
 744  * @signaller - ring which has, or will signal
 745  * @seqno - seqno which the waiter will block on
 746  */
 747 static int
 748 gen6_ring_sync(struct intel_ring_buffer *waiter,
 749                struct intel_ring_buffer *signaller,
 750                u32 seqno)
 751 {
 752         u32 dw1 = MI_SEMAPHORE_MBOX |
 753                   MI_SEMAPHORE_COMPARE |
 754                   MI_SEMAPHORE_REGISTER;
 755         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
 756         int ret;
 757
 758         /* Throughout all of the GEM code, seqno passed implies our current
 759          * seqno is >= the last seqno executed. However for hardware the
 760          * comparison is strictly greater than.
 761          */
 762         seqno -= 1;
 763
 764         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
 765
 766         ret = intel_ring_begin(waiter, 4);
 767         if (ret)
 768                 return ret;
 769
 770         /* If seqno wrap happened, omit the wait with no-ops */
 771         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 772                 intel_ring_emit(waiter, dw1 | wait_mbox);
 773                 intel_ring_emit(waiter, seqno);
 774                 intel_ring_emit(waiter, 0);
 775                 intel_ring_emit(waiter, MI_NOOP);
 776         } else {
 777                 intel_ring_emit(waiter, MI_NOOP);
 778                 intel_ring_emit(waiter, MI_NOOP);
 779                 intel_ring_emit(waiter, MI_NOOP);
 780                 intel_ring_emit(waiter, MI_NOOP);
 781         }
 782         intel_ring_advance(waiter);
 783
 784         return 0;
 785 }
 786
 787 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 788 do {                                                                    \
 789         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 790                  PIPE_CONTROL_DEPTH_STALL);                             \
 791         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 792         intel_ring_emit(ring__, 0);                                                     \
 793         intel_ring_emit(ring__, 0);                                                     \
 794 } while (0)
 795
 796 static int
 797 pc_render_add_request(struct intel_ring_buffer *ring)
 798 {
 799         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 800         int ret;
 801
 802         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 803          * incoherent with writes to memory, i.e. completely fubar,
 804          * so we need to use PIPE_NOTIFY instead.
 805          *
 806          * However, we also need to workaround the qword write
 807          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 808          * memory before requesting an interrupt.
 809          */
 810         ret = intel_ring_begin(ring, 32);
 811         if (ret)
 812                 return ret;
 813
 814         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 815                         PIPE_CONTROL_WRITE_FLUSH |
 816                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 817         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 818         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 819         intel_ring_emit(ring, 0);
 820         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 821         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
 822         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 823         scratch_addr += 2 * CACHELINE_BYTES;
 824         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 825         scratch_addr += 2 * CACHELINE_BYTES;
 826         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 827         scratch_addr += 2 * CACHELINE_BYTES;
 828         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 829         scratch_addr += 2 * CACHELINE_BYTES;
 830         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 831
 832         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 833                         PIPE_CONTROL_WRITE_FLUSH |
 834                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 835                         PIPE_CONTROL_NOTIFY);
 836         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 837         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 838         intel_ring_emit(ring, 0);
 839         __intel_ring_advance(ring);
 840
 841         return 0;
 842 }
 843
 844 static u32
 845 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 846 {
 847         /* Workaround to force correct ordering between irq and seqno writes on
 848          * ivb (and maybe also on snb) by reading from a CS register (like
 849          * ACTHD) before reading the status page. */
 850         if (!lazy_coherency) {
 851                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
 852                 POSTING_READ(RING_ACTHD(ring->mmio_base));
 853         }
 854
 855         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 856 }
 857
 858 static u32
 859 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 860 {
 861         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 862 }
 863
 864 static void
 865 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 866 {
 867         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 868 }
 869
 870 static u32
 871 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 872 {
 873         return ring->scratch.cpu_page[0];
 874 }
 875
 876 static void
 877 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 878 {
 879         ring->scratch.cpu_page[0] = seqno;
 880 }
 881
 882 static bool
 883 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 884 {
 885         struct drm_device *dev = ring->dev;
 886         struct drm_i915_private *dev_priv = dev->dev_private;
 887         unsigned long flags;
 888
 889         if (!dev->irq_enabled)
 890                 return false;
 891
 892         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 893         if (ring->irq_refcount++ == 0)
 894                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
 895         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 896
 897         return true;
 898 }
 899
 900 static void
 901 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 902 {
 903         struct drm_device *dev = ring->dev;
 904         struct drm_i915_private *dev_priv = dev->dev_private;
 905         unsigned long flags;
 906
 907         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 908         if (--ring->irq_refcount == 0)
 909                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
 910         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 911 }
 912
 913 static bool
 914 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 915 {
 916         struct drm_device *dev = ring->dev;
 917         struct drm_i915_private *dev_priv = dev->dev_private;
 918         unsigned long flags;
 919
 920         if (!dev->irq_enabled)
 921                 return false;
 922
 923         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 924         if (ring->irq_refcount++ == 0) {
 925                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 926                 I915_WRITE(IMR, dev_priv->irq_mask);
 927                 POSTING_READ(IMR);
 928         }
 929         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 930
 931         return true;
 932 }
 933
 934 static void
 935 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 936 {
 937         struct drm_device *dev = ring->dev;
 938         struct drm_i915_private *dev_priv = dev->dev_private;
 939         unsigned long flags;
 940
 941         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 942         if (--ring->irq_refcount == 0) {
 943                 dev_priv->irq_mask |= ring->irq_enable_mask;
 944                 I915_WRITE(IMR, dev_priv->irq_mask);
 945                 POSTING_READ(IMR);
 946         }
 947         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 948 }
 949
 950 static bool
 951 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 952 {
 953         struct drm_device *dev = ring->dev;
 954         struct drm_i915_private *dev_priv = dev->dev_private;
 955         unsigned long flags;
 956
 957         if (!dev->irq_enabled)
 958                 return false;
 959
 960         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 961         if (ring->irq_refcount++ == 0) {
 962                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 963                 I915_WRITE16(IMR, dev_priv->irq_mask);
 964                 POSTING_READ16(IMR);
 965         }
 966         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 967
 968         return true;
 969 }
 970
 971 static void
 972 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 973 {
 974         struct drm_device *dev = ring->dev;
 975         struct drm_i915_private *dev_priv = dev->dev_private;
 976         unsigned long flags;
 977
 978         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 979         if (--ring->irq_refcount == 0) {
 980                 dev_priv->irq_mask |= ring->irq_enable_mask;
 981                 I915_WRITE16(IMR, dev_priv->irq_mask);
 982                 POSTING_READ16(IMR);
 983         }
 984         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 985 }
 986
 987 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 988 {
 989         struct drm_device *dev = ring->dev;
 990         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 991         u32 mmio = 0;
 992
 993         /* The ring status page addresses are no longer next to the rest of
 994          * the ring registers as of gen7.
 995          */
 996         if (IS_GEN7(dev)) {
 997                 switch (ring->id) {
 998                 case RCS:
 999                         mmio = RENDER_HWS_PGA_GEN7;
1000                         break;
1001                 case BCS:
1002                         mmio = BLT_HWS_PGA_GEN7;
1003                         break;
1004                 /*
1005                  * VCS2 actually doesn't exist on Gen7. Only shut up
1006                  * gcc switch check warning
1007                  */
1008                 case VCS2:
1009                 case VCS:
1010                         mmio = BSD_HWS_PGA_GEN7;
1011                         break;
1012                 case VECS:
1013                         mmio = VEBOX_HWS_PGA_GEN7;
1014                         break;
1015                 }
1016         } else if (IS_GEN6(ring->dev)) {
1017                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1018         } else {
1019                 /* XXX: gen8 returns to sanity */
1020                 mmio = RING_HWS_PGA(ring->mmio_base);
1021         }
1022
1023         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1024         POSTING_READ(mmio);
1025
1026         /*
1027          * Flush the TLB for this page
1028          *
1029          * FIXME: These two bits have disappeared on gen8, so a question
1030          * arises: do we still need this and if so how should we go about
1031          * invalidating the TLB?
1032          */
1033         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1034                 u32 reg = RING_INSTPM(ring->mmio_base);
1035
1036                 /* ring should be idle before issuing a sync flush*/
1037                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1038
1039                 I915_WRITE(reg,
1040                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1041                                               INSTPM_SYNC_FLUSH));
1042                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1043                              1000))
1044                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1045                                   ring->name);
1046         }
1047 }
1048
1049 static int
1050 bsd_ring_flush(struct intel_ring_buffer *ring,
1051                u32     invalidate_domains,
1052                u32     flush_domains)
1053 {
1054         int ret;
1055
1056         ret = intel_ring_begin(ring, 2);
1057         if (ret)
1058                 return ret;
1059
1060         intel_ring_emit(ring, MI_FLUSH);
1061         intel_ring_emit(ring, MI_NOOP);
1062         intel_ring_advance(ring);
1063         return 0;
1064 }
1065
1066 static int
1067 i9xx_add_request(struct intel_ring_buffer *ring)
1068 {
1069         int ret;
1070
1071         ret = intel_ring_begin(ring, 4);
1072         if (ret)
1073                 return ret;
1074
1075         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1076         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1077         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1078         intel_ring_emit(ring, MI_USER_INTERRUPT);
1079         __intel_ring_advance(ring);
1080
1081         return 0;
1082 }
1083
1084 static bool
1085 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1086 {
1087         struct drm_device *dev = ring->dev;
1088         struct drm_i915_private *dev_priv = dev->dev_private;
1089         unsigned long flags;
1090
1091         if (!dev->irq_enabled)
1092                return false;
1093
1094         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1095         if (ring->irq_refcount++ == 0) {
1096                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1097                         I915_WRITE_IMR(ring,
1098                                        ~(ring->irq_enable_mask |
1099                                          GT_PARITY_ERROR(dev)));
1100                 else
1101                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1102                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1103         }
1104         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1105
1106         return true;
1107 }
1108
1109 static void
1110 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1111 {
1112         struct drm_device *dev = ring->dev;
1113         struct drm_i915_private *dev_priv = dev->dev_private;
1114         unsigned long flags;
1115
1116         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1117         if (--ring->irq_refcount == 0) {
1118                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1119                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1120                 else
1121                         I915_WRITE_IMR(ring, ~0);
1122                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1123         }
1124         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1125 }
1126
1127 static bool
1128 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1129 {
1130         struct drm_device *dev = ring->dev;
1131         struct drm_i915_private *dev_priv = dev->dev_private;
1132         unsigned long flags;
1133
1134         if (!dev->irq_enabled)
1135                 return false;
1136
1137         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1138         if (ring->irq_refcount++ == 0) {
1139                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1140                 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1141         }
1142         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1143
1144         return true;
1145 }
1146
1147 static void
1148 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1149 {
1150         struct drm_device *dev = ring->dev;
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         unsigned long flags;
1153
1154         if (!dev->irq_enabled)
1155                 return;
1156
1157         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1158         if (--ring->irq_refcount == 0) {
1159                 I915_WRITE_IMR(ring, ~0);
1160                 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1161         }
1162         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1163 }
1164
1165 static bool
1166 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1167 {
1168         struct drm_device *dev = ring->dev;
1169         struct drm_i915_private *dev_priv = dev->dev_private;
1170         unsigned long flags;
1171
1172         if (!dev->irq_enabled)
1173                 return false;
1174
1175         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1176         if (ring->irq_refcount++ == 0) {
1177                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1178                         I915_WRITE_IMR(ring,
1179                                        ~(ring->irq_enable_mask |
1180                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1181                 } else {
1182                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1183                 }
1184                 POSTING_READ(RING_IMR(ring->mmio_base));
1185         }
1186         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1187
1188         return true;
1189 }
1190
1191 static void
1192 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1193 {
1194         struct drm_device *dev = ring->dev;
1195         struct drm_i915_private *dev_priv = dev->dev_private;
1196         unsigned long flags;
1197
1198         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1199         if (--ring->irq_refcount == 0) {
1200                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1201                         I915_WRITE_IMR(ring,
1202                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1203                 } else {
1204                         I915_WRITE_IMR(ring, ~0);
1205                 }
1206                 POSTING_READ(RING_IMR(ring->mmio_base));
1207         }
1208         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1209 }
1210
1211 static int
1212 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1213                          u64 offset, u32 length,
1214                          unsigned flags)
1215 {
1216         int ret;
1217
1218         ret = intel_ring_begin(ring, 2);
1219         if (ret)
1220                 return ret;
1221
1222         intel_ring_emit(ring,
1223                         MI_BATCH_BUFFER_START |
1224                         MI_BATCH_GTT |
1225                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1226         intel_ring_emit(ring, offset);
1227         intel_ring_advance(ring);
1228
1229         return 0;
1230 }
1231
1232 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1233 #define I830_BATCH_LIMIT (256*1024)
1234 static int
1235 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1236                                 u64 offset, u32 len,
1237                                 unsigned flags)
1238 {
1239         int ret;
1240
1241         if (flags & I915_DISPATCH_PINNED) {
1242                 ret = intel_ring_begin(ring, 4);
1243                 if (ret)
1244                         return ret;
1245
1246                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1247                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1248                 intel_ring_emit(ring, offset + len - 8);
1249                 intel_ring_emit(ring, MI_NOOP);
1250                 intel_ring_advance(ring);
1251         } else {
1252                 u32 cs_offset = ring->scratch.gtt_offset;
1253
1254                 if (len > I830_BATCH_LIMIT)
1255                         return -ENOSPC;
1256
1257                 ret = intel_ring_begin(ring, 9+3);
1258                 if (ret)
1259                         return ret;
1260                 /* Blit the batch (which has now all relocs applied) to the stable batch
1261                  * scratch bo area (so that the CS never stumbles over its tlb
1262                  * invalidation bug) ... */
1263                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1264                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1265                                 XY_SRC_COPY_BLT_WRITE_RGB);
1266                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1267                 intel_ring_emit(ring, 0);
1268                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1269                 intel_ring_emit(ring, cs_offset);
1270                 intel_ring_emit(ring, 0);
1271                 intel_ring_emit(ring, 4096);
1272                 intel_ring_emit(ring, offset);
1273                 intel_ring_emit(ring, MI_FLUSH);
1274
1275                 /* ... and execute it. */
1276                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1277                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1278                 intel_ring_emit(ring, cs_offset + len - 8);
1279                 intel_ring_advance(ring);
1280         }
1281
1282         return 0;
1283 }
1284
1285 static int
1286 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1287                          u64 offset, u32 len,
1288                          unsigned flags)
1289 {
1290         int ret;
1291
1292         ret = intel_ring_begin(ring, 2);
1293         if (ret)
1294                 return ret;
1295
1296         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1297         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1298         intel_ring_advance(ring);
1299
1300         return 0;
1301 }
1302
1303 static void cleanup_status_page(struct intel_ring_buffer *ring)
1304 {
1305         struct drm_i915_gem_object *obj;
1306
1307         obj = ring->status_page.obj;
1308         if (obj == NULL)
1309                 return;
1310
1311         kunmap(sg_page(obj->pages->sgl));
1312         i915_gem_object_ggtt_unpin(obj);
1313         drm_gem_object_unreference(&obj->base);
1314         ring->status_page.obj = NULL;
1315 }
1316
1317 static int init_status_page(struct intel_ring_buffer *ring)
1318 {
1319         struct drm_i915_gem_object *obj;
1320
1321         if ((obj = ring->status_page.obj) == NULL) {
1322                 int ret;
1323
1324                 obj = i915_gem_alloc_object(ring->dev, 4096);
1325                 if (obj == NULL) {
1326                         DRM_ERROR("Failed to allocate status page\n");
1327                         return -ENOMEM;
1328                 }
1329
1330                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1331                 if (ret)
1332                         goto err_unref;
1333
1334                 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1335                 if (ret) {
1336 err_unref:
1337                         drm_gem_object_unreference(&obj->base);
1338                         return ret;
1339                 }
1340
1341                 ring->status_page.obj = obj;
1342         }
1343
1344         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1345         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1346         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1347
1348         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1349                         ring->name, ring->status_page.gfx_addr);
1350
1351         return 0;
1352 }
1353
1354 static int init_phys_status_page(struct intel_ring_buffer *ring)
1355 {
1356         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1357
1358         if (!dev_priv->status_page_dmah) {
1359                 dev_priv->status_page_dmah =
1360                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1361                 if (!dev_priv->status_page_dmah)
1362                         return -ENOMEM;
1363         }
1364
1365         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1366         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1367
1368         return 0;
1369 }
1370
1371 static int allocate_ring_buffer(struct intel_ring_buffer *ring)
1372 {
1373         struct drm_device *dev = ring->dev;
1374         struct drm_i915_private *dev_priv = to_i915(dev);
1375         struct drm_i915_gem_object *obj;
1376         int ret;
1377
1378         if (ring->obj)
1379                 return 0;
1380
1381         obj = NULL;
1382         if (!HAS_LLC(dev))
1383                 obj = i915_gem_object_create_stolen(dev, ring->size);
1384         if (obj == NULL)
1385                 obj = i915_gem_alloc_object(dev, ring->size);
1386         if (obj == NULL)
1387                 return -ENOMEM;
1388
1389         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1390         if (ret)
1391                 goto err_unref;
1392
1393         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1394         if (ret)
1395                 goto err_unpin;
1396
1397         ring->virtual_start =
1398                 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1399                            ring->size);
1400         if (ring->virtual_start == NULL) {
1401                 ret = -EINVAL;
1402                 goto err_unpin;
1403         }
1404
1405         ring->obj = obj;
1406         return 0;
1407
1408 err_unpin:
1409         i915_gem_object_ggtt_unpin(obj);
1410 err_unref:
1411         drm_gem_object_unreference(&obj->base);
1412         return ret;
1413 }
1414
1415 static int intel_init_ring_buffer(struct drm_device *dev,
1416                                   struct intel_ring_buffer *ring)
1417 {
1418         int ret;
1419
1420         ring->dev = dev;
1421         INIT_LIST_HEAD(&ring->active_list);
1422         INIT_LIST_HEAD(&ring->request_list);
1423         ring->size = 32 * PAGE_SIZE;
1424         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1425
1426         init_waitqueue_head(&ring->irq_queue);
1427
1428         if (I915_NEED_GFX_HWS(dev)) {
1429                 ret = init_status_page(ring);
1430                 if (ret)
1431                         return ret;
1432         } else {
1433                 BUG_ON(ring->id != RCS);
1434                 ret = init_phys_status_page(ring);
1435                 if (ret)
1436                         return ret;
1437         }
1438
1439         ret = allocate_ring_buffer(ring);
1440         if (ret) {
1441                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1442                 return ret;
1443         }
1444
1445         /* Workaround an erratum on the i830 which causes a hang if
1446          * the TAIL pointer points to within the last 2 cachelines
1447          * of the buffer.
1448          */
1449         ring->effective_size = ring->size;
1450         if (IS_I830(dev) || IS_845G(dev))
1451                 ring->effective_size -= 2 * CACHELINE_BYTES;
1452
1453         i915_cmd_parser_init_ring(ring);
1454
1455         return ring->init(ring);
1456 }
1457
1458 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1459 {
1460         struct drm_i915_private *dev_priv = to_i915(ring->dev);
1461
1462         if (ring->obj == NULL)
1463                 return;
1464
1465         intel_stop_ring_buffer(ring);
1466         WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1467
1468         iounmap(ring->virtual_start);
1469
1470         i915_gem_object_ggtt_unpin(ring->obj);
1471         drm_gem_object_unreference(&ring->obj->base);
1472         ring->obj = NULL;
1473         ring->preallocated_lazy_request = NULL;
1474         ring->outstanding_lazy_seqno = 0;
1475
1476         if (ring->cleanup)
1477                 ring->cleanup(ring);
1478
1479         cleanup_status_page(ring);
1480 }
1481
1482 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1483 {
1484         struct drm_i915_gem_request *request;
1485         u32 seqno = 0, tail;
1486         int ret;
1487
1488         if (ring->last_retired_head != -1) {
1489                 ring->head = ring->last_retired_head;
1490                 ring->last_retired_head = -1;
1491
1492                 ring->space = ring_space(ring);
1493                 if (ring->space >= n)
1494                         return 0;
1495         }
1496
1497         list_for_each_entry(request, &ring->request_list, list) {
1498                 int space;
1499
1500                 if (request->tail == -1)
1501                         continue;
1502
1503                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1504                 if (space < 0)
1505                         space += ring->size;
1506                 if (space >= n) {
1507                         seqno = request->seqno;
1508                         tail = request->tail;
1509                         break;
1510                 }
1511
1512                 /* Consume this request in case we need more space than
1513                  * is available and so need to prevent a race between
1514                  * updating last_retired_head and direct reads of
1515                  * I915_RING_HEAD. It also provides a nice sanity check.
1516                  */
1517                 request->tail = -1;
1518         }
1519
1520         if (seqno == 0)
1521                 return -ENOSPC;
1522
1523         ret = i915_wait_seqno(ring, seqno);
1524         if (ret)
1525                 return ret;
1526
1527         ring->head = tail;
1528         ring->space = ring_space(ring);
1529         if (WARN_ON(ring->space < n))
1530                 return -ENOSPC;
1531
1532         return 0;
1533 }
1534
1535 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1536 {
1537         struct drm_device *dev = ring->dev;
1538         struct drm_i915_private *dev_priv = dev->dev_private;
1539         unsigned long end;
1540         int ret;
1541
1542         ret = intel_ring_wait_request(ring, n);
1543         if (ret != -ENOSPC)
1544                 return ret;
1545
1546         /* force the tail write in case we have been skipping them */
1547         __intel_ring_advance(ring);
1548
1549         trace_i915_ring_wait_begin(ring);
1550         /* With GEM the hangcheck timer should kick us out of the loop,
1551          * leaving it early runs the risk of corrupting GEM state (due
1552          * to running on almost untested codepaths). But on resume
1553          * timers don't work yet, so prevent a complete hang in that
1554          * case by choosing an insanely large timeout. */
1555         end = jiffies + 60 * HZ;
1556
1557         do {
1558                 ring->head = I915_READ_HEAD(ring);
1559                 ring->space = ring_space(ring);
1560                 if (ring->space >= n) {
1561                         trace_i915_ring_wait_end(ring);
1562                         return 0;
1563                 }
1564
1565                 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1566                     dev->primary->master) {
1567                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1568                         if (master_priv->sarea_priv)
1569                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1570                 }
1571
1572                 msleep(1);
1573
1574                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1575                                            dev_priv->mm.interruptible);
1576                 if (ret)
1577                         return ret;
1578         } while (!time_after(jiffies, end));
1579         trace_i915_ring_wait_end(ring);
1580         return -EBUSY;
1581 }
1582
1583 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1584 {
1585         uint32_t __iomem *virt;
1586         int rem = ring->size - ring->tail;
1587
1588         if (ring->space < rem) {
1589                 int ret = ring_wait_for_space(ring, rem);
1590                 if (ret)
1591                         return ret;
1592         }
1593
1594         virt = ring->virtual_start + ring->tail;
1595         rem /= 4;
1596         while (rem--)
1597                 iowrite32(MI_NOOP, virt++);
1598
1599         ring->tail = 0;
1600         ring->space = ring_space(ring);
1601
1602         return 0;
1603 }
1604
1605 int intel_ring_idle(struct intel_ring_buffer *ring)
1606 {
1607         u32 seqno;
1608         int ret;
1609
1610         /* We need to add any requests required to flush the objects and ring */
1611         if (ring->outstanding_lazy_seqno) {
1612                 ret = i915_add_request(ring, NULL);
1613                 if (ret)
1614                         return ret;
1615         }
1616
1617         /* Wait upon the last request to be completed */
1618         if (list_empty(&ring->request_list))
1619                 return 0;
1620
1621         seqno = list_entry(ring->request_list.prev,
1622                            struct drm_i915_gem_request,
1623                            list)->seqno;
1624
1625         return i915_wait_seqno(ring, seqno);
1626 }
1627
1628 static int
1629 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1630 {
1631         if (ring->outstanding_lazy_seqno)
1632                 return 0;
1633
1634         if (ring->preallocated_lazy_request == NULL) {
1635                 struct drm_i915_gem_request *request;
1636
1637                 request = kmalloc(sizeof(*request), GFP_KERNEL);
1638                 if (request == NULL)
1639                         return -ENOMEM;
1640
1641                 ring->preallocated_lazy_request = request;
1642         }
1643
1644         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1645 }
1646
1647 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1648                                 int bytes)
1649 {
1650         int ret;
1651
1652         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1653                 ret = intel_wrap_ring_buffer(ring);
1654                 if (unlikely(ret))
1655                         return ret;
1656         }
1657
1658         if (unlikely(ring->space < bytes)) {
1659                 ret = ring_wait_for_space(ring, bytes);
1660                 if (unlikely(ret))
1661                         return ret;
1662         }
1663
1664         return 0;
1665 }
1666
1667 int intel_ring_begin(struct intel_ring_buffer *ring,
1668                      int num_dwords)
1669 {
1670         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1671         int ret;
1672
1673         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1674                                    dev_priv->mm.interruptible);
1675         if (ret)
1676                 return ret;
1677
1678         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1679         if (ret)
1680                 return ret;
1681
1682         /* Preallocate the olr before touching the ring */
1683         ret = intel_ring_alloc_seqno(ring);
1684         if (ret)
1685                 return ret;
1686
1687         ring->space -= num_dwords * sizeof(uint32_t);
1688         return 0;
1689 }
1690
1691 /* Align the ring tail to a cacheline boundary */
1692 int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1693 {
1694         int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
1695         int ret;
1696
1697         if (num_dwords == 0)
1698                 return 0;
1699
1700         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
1701         ret = intel_ring_begin(ring, num_dwords);
1702         if (ret)
1703                 return ret;
1704
1705         while (num_dwords--)
1706                 intel_ring_emit(ring, MI_NOOP);
1707
1708         intel_ring_advance(ring);
1709
1710         return 0;
1711 }
1712
1713 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1714 {
1715         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1716
1717         BUG_ON(ring->outstanding_lazy_seqno);
1718
1719         if (INTEL_INFO(ring->dev)->gen >= 6) {
1720                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1721                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1722                 if (HAS_VEBOX(ring->dev))
1723                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1724         }
1725
1726         ring->set_seqno(ring, seqno);
1727         ring->hangcheck.seqno = seqno;
1728 }
1729
1730 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1731                                      u32 value)
1732 {
1733         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1734
1735        /* Every tail move must follow the sequence below */
1736
1737         /* Disable notification that the ring is IDLE. The GT
1738          * will then assume that it is busy and bring it out of rc6.
1739          */
1740         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1741                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1742
1743         /* Clear the context id. Here be magic! */
1744         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1745
1746         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1747         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1748                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1749                      50))
1750                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1751
1752         /* Now that the ring is fully powered up, update the tail */
1753         I915_WRITE_TAIL(ring, value);
1754         POSTING_READ(RING_TAIL(ring->mmio_base));
1755
1756         /* Let the ring send IDLE messages to the GT again,
1757          * and so let it sleep to conserve power when idle.
1758          */
1759         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1760                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1761 }
1762
1763 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1764                                u32 invalidate, u32 flush)
1765 {
1766         uint32_t cmd;
1767         int ret;
1768
1769         ret = intel_ring_begin(ring, 4);
1770         if (ret)
1771                 return ret;
1772
1773         cmd = MI_FLUSH_DW;
1774         if (INTEL_INFO(ring->dev)->gen >= 8)
1775                 cmd += 1;
1776         /*
1777          * Bspec vol 1c.5 - video engine command streamer:
1778          * "If ENABLED, all TLBs will be invalidated once the flush
1779          * operation is complete. This bit is only valid when the
1780          * Post-Sync Operation field is a value of 1h or 3h."
1781          */
1782         if (invalidate & I915_GEM_GPU_DOMAINS)
1783                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1784                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1785         intel_ring_emit(ring, cmd);
1786         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1787         if (INTEL_INFO(ring->dev)->gen >= 8) {
1788                 intel_ring_emit(ring, 0); /* upper addr */
1789                 intel_ring_emit(ring, 0); /* value */
1790         } else  {
1791                 intel_ring_emit(ring, 0);
1792                 intel_ring_emit(ring, MI_NOOP);
1793         }
1794         intel_ring_advance(ring);
1795         return 0;
1796 }
1797
1798 static int
1799 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1800                               u64 offset, u32 len,
1801                               unsigned flags)
1802 {
1803         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1804         bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1805                 !(flags & I915_DISPATCH_SECURE);
1806         int ret;
1807
1808         ret = intel_ring_begin(ring, 4);
1809         if (ret)
1810                 return ret;
1811
1812         /* FIXME(BDW): Address space and security selectors. */
1813         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1814         intel_ring_emit(ring, lower_32_bits(offset));
1815         intel_ring_emit(ring, upper_32_bits(offset));
1816         intel_ring_emit(ring, MI_NOOP);
1817         intel_ring_advance(ring);
1818
1819         return 0;
1820 }
1821
1822 static int
1823 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1824                               u64 offset, u32 len,
1825                               unsigned flags)
1826 {
1827         int ret;
1828
1829         ret = intel_ring_begin(ring, 2);
1830         if (ret)
1831                 return ret;
1832
1833         intel_ring_emit(ring,
1834                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1835                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1836         /* bit0-7 is the length on GEN6+ */
1837         intel_ring_emit(ring, offset);
1838         intel_ring_advance(ring);
1839
1840         return 0;
1841 }
1842
1843 static int
1844 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1845                               u64 offset, u32 len,
1846                               unsigned flags)
1847 {
1848         int ret;
1849
1850         ret = intel_ring_begin(ring, 2);
1851         if (ret)
1852                 return ret;
1853
1854         intel_ring_emit(ring,
1855                         MI_BATCH_BUFFER_START |
1856                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1857         /* bit0-7 is the length on GEN6+ */
1858         intel_ring_emit(ring, offset);
1859         intel_ring_advance(ring);
1860
1861         return 0;
1862 }
1863
1864 /* Blitter support (SandyBridge+) */
1865
1866 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1867                            u32 invalidate, u32 flush)
1868 {
1869         struct drm_device *dev = ring->dev;
1870         uint32_t cmd;
1871         int ret;
1872
1873         ret = intel_ring_begin(ring, 4);
1874         if (ret)
1875                 return ret;
1876
1877         cmd = MI_FLUSH_DW;
1878         if (INTEL_INFO(ring->dev)->gen >= 8)
1879                 cmd += 1;
1880         /*
1881          * Bspec vol 1c.3 - blitter engine command streamer:
1882          * "If ENABLED, all TLBs will be invalidated once the flush
1883          * operation is complete. This bit is only valid when the
1884          * Post-Sync Operation field is a value of 1h or 3h."
1885          */
1886         if (invalidate & I915_GEM_DOMAIN_RENDER)
1887                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1888                         MI_FLUSH_DW_OP_STOREDW;
1889         intel_ring_emit(ring, cmd);
1890         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1891         if (INTEL_INFO(ring->dev)->gen >= 8) {
1892                 intel_ring_emit(ring, 0); /* upper addr */
1893                 intel_ring_emit(ring, 0); /* value */
1894         } else  {
1895                 intel_ring_emit(ring, 0);
1896                 intel_ring_emit(ring, MI_NOOP);
1897         }
1898         intel_ring_advance(ring);
1899
1900         if (IS_GEN7(dev) && !invalidate && flush)
1901                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1902
1903         return 0;
1904 }
1905
1906 int intel_init_render_ring_buffer(struct drm_device *dev)
1907 {
1908         struct drm_i915_private *dev_priv = dev->dev_private;
1909         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1910
1911         ring->name = "render ring";
1912         ring->id = RCS;
1913         ring->mmio_base = RENDER_RING_BASE;
1914
1915         if (INTEL_INFO(dev)->gen >= 6) {
1916                 ring->add_request = gen6_add_request;
1917                 ring->flush = gen7_render_ring_flush;
1918                 if (INTEL_INFO(dev)->gen == 6)
1919                         ring->flush = gen6_render_ring_flush;
1920                 if (INTEL_INFO(dev)->gen >= 8) {
1921                         ring->flush = gen8_render_ring_flush;
1922                         ring->irq_get = gen8_ring_get_irq;
1923                         ring->irq_put = gen8_ring_put_irq;
1924                 } else {
1925                         ring->irq_get = gen6_ring_get_irq;
1926                         ring->irq_put = gen6_ring_put_irq;
1927                 }
1928                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1929                 ring->get_seqno = gen6_ring_get_seqno;
1930                 ring->set_seqno = ring_set_seqno;
1931                 ring->semaphore.sync_to = gen6_ring_sync;
1932                 ring->semaphore.signal = gen6_signal;
1933                 /*
1934                  * The current semaphore is only applied on pre-gen8 platform.
1935                  * And there is no VCS2 ring on the pre-gen8 platform. So the
1936                  * semaphore between RCS and VCS2 is initialized as INVALID.
1937                  * Gen8 will initialize the sema between VCS2 and RCS later.
1938                  */
1939                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1940                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
1941                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
1942                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
1943                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
1944                 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
1945                 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
1946                 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
1947                 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
1948                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
1949         } else if (IS_GEN5(dev)) {
1950                 ring->add_request = pc_render_add_request;
1951                 ring->flush = gen4_render_ring_flush;
1952                 ring->get_seqno = pc_render_get_seqno;
1953                 ring->set_seqno = pc_render_set_seqno;
1954                 ring->irq_get = gen5_ring_get_irq;
1955                 ring->irq_put = gen5_ring_put_irq;
1956                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1957                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1958         } else {
1959                 ring->add_request = i9xx_add_request;
1960                 if (INTEL_INFO(dev)->gen < 4)
1961                         ring->flush = gen2_render_ring_flush;
1962                 else
1963                         ring->flush = gen4_render_ring_flush;
1964                 ring->get_seqno = ring_get_seqno;
1965                 ring->set_seqno = ring_set_seqno;
1966                 if (IS_GEN2(dev)) {
1967                         ring->irq_get = i8xx_ring_get_irq;
1968                         ring->irq_put = i8xx_ring_put_irq;
1969                 } else {
1970                         ring->irq_get = i9xx_ring_get_irq;
1971                         ring->irq_put = i9xx_ring_put_irq;
1972                 }
1973                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1974         }
1975         ring->write_tail = ring_write_tail;
1976         if (IS_HASWELL(dev))
1977                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1978         else if (IS_GEN8(dev))
1979                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1980         else if (INTEL_INFO(dev)->gen >= 6)
1981                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1982         else if (INTEL_INFO(dev)->gen >= 4)
1983                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1984         else if (IS_I830(dev) || IS_845G(dev))
1985                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1986         else
1987                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1988         ring->init = init_render_ring;
1989         ring->cleanup = render_ring_cleanup;
1990
1991         /* Workaround batchbuffer to combat CS tlb bug. */
1992         if (HAS_BROKEN_CS_TLB(dev)) {
1993                 struct drm_i915_gem_object *obj;
1994                 int ret;
1995
1996                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1997                 if (obj == NULL) {
1998                         DRM_ERROR("Failed to allocate batch bo\n");
1999                         return -ENOMEM;
2000                 }
2001
2002                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2003                 if (ret != 0) {
2004                         drm_gem_object_unreference(&obj->base);
2005                         DRM_ERROR("Failed to ping batch bo\n");
2006                         return ret;
2007                 }
2008
2009                 ring->scratch.obj = obj;
2010                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2011         }
2012
2013         return intel_init_ring_buffer(dev, ring);
2014 }
2015
2016 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2017 {
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2020         int ret;
2021
2022         ring->name = "render ring";
2023         ring->id = RCS;
2024         ring->mmio_base = RENDER_RING_BASE;
2025
2026         if (INTEL_INFO(dev)->gen >= 6) {
2027                 /* non-kms not supported on gen6+ */
2028                 return -ENODEV;
2029         }
2030
2031         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2032          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2033          * the special gen5 functions. */
2034         ring->add_request = i9xx_add_request;
2035         if (INTEL_INFO(dev)->gen < 4)
2036                 ring->flush = gen2_render_ring_flush;
2037         else
2038                 ring->flush = gen4_render_ring_flush;
2039         ring->get_seqno = ring_get_seqno;
2040         ring->set_seqno = ring_set_seqno;
2041         if (IS_GEN2(dev)) {
2042                 ring->irq_get = i8xx_ring_get_irq;
2043                 ring->irq_put = i8xx_ring_put_irq;
2044         } else {
2045                 ring->irq_get = i9xx_ring_get_irq;
2046                 ring->irq_put = i9xx_ring_put_irq;
2047         }
2048         ring->irq_enable_mask = I915_USER_INTERRUPT;
2049         ring->write_tail = ring_write_tail;
2050         if (INTEL_INFO(dev)->gen >= 4)
2051                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2052         else if (IS_I830(dev) || IS_845G(dev))
2053                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2054         else
2055                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2056         ring->init = init_render_ring;
2057         ring->cleanup = render_ring_cleanup;
2058
2059         ring->dev = dev;
2060         INIT_LIST_HEAD(&ring->active_list);
2061         INIT_LIST_HEAD(&ring->request_list);
2062
2063         ring->size = size;
2064         ring->effective_size = ring->size;
2065         if (IS_I830(ring->dev) || IS_845G(ring->dev))
2066                 ring->effective_size -= 2 * CACHELINE_BYTES;
2067
2068         ring->virtual_start = ioremap_wc(start, size);
2069         if (ring->virtual_start == NULL) {
2070                 DRM_ERROR("can not ioremap virtual address for"
2071                           " ring buffer\n");
2072                 return -ENOMEM;
2073         }
2074
2075         if (!I915_NEED_GFX_HWS(dev)) {
2076                 ret = init_phys_status_page(ring);
2077                 if (ret)
2078                         return ret;
2079         }
2080
2081         return 0;
2082 }
2083
2084 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2085 {
2086         struct drm_i915_private *dev_priv = dev->dev_private;
2087         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2088
2089         ring->name = "bsd ring";
2090         ring->id = VCS;
2091
2092         ring->write_tail = ring_write_tail;
2093         if (INTEL_INFO(dev)->gen >= 6) {
2094                 ring->mmio_base = GEN6_BSD_RING_BASE;
2095                 /* gen6 bsd needs a special wa for tail updates */
2096                 if (IS_GEN6(dev))
2097                         ring->write_tail = gen6_bsd_ring_write_tail;
2098                 ring->flush = gen6_bsd_ring_flush;
2099                 ring->add_request = gen6_add_request;
2100                 ring->get_seqno = gen6_ring_get_seqno;
2101                 ring->set_seqno = ring_set_seqno;
2102                 if (INTEL_INFO(dev)->gen >= 8) {
2103                         ring->irq_enable_mask =
2104                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2105                         ring->irq_get = gen8_ring_get_irq;
2106                         ring->irq_put = gen8_ring_put_irq;
2107                         ring->dispatch_execbuffer =
2108                                 gen8_ring_dispatch_execbuffer;
2109                 } else {
2110                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2111                         ring->irq_get = gen6_ring_get_irq;
2112                         ring->irq_put = gen6_ring_put_irq;
2113                         ring->dispatch_execbuffer =
2114                                 gen6_ring_dispatch_execbuffer;
2115                 }
2116                 ring->semaphore.sync_to = gen6_ring_sync;
2117                 ring->semaphore.signal = gen6_signal;
2118                 /*
2119                  * The current semaphore is only applied on pre-gen8 platform.
2120                  * And there is no VCS2 ring on the pre-gen8 platform. So the
2121                  * semaphore between VCS and VCS2 is initialized as INVALID.
2122                  * Gen8 will initialize the sema between VCS2 and VCS later.
2123                  */
2124                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2125                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2126                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2127                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2128                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2129                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2130                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2131                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2132                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2133                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2134         } else {
2135                 ring->mmio_base = BSD_RING_BASE;
2136                 ring->flush = bsd_ring_flush;
2137                 ring->add_request = i9xx_add_request;
2138                 ring->get_seqno = ring_get_seqno;
2139                 ring->set_seqno = ring_set_seqno;
2140                 if (IS_GEN5(dev)) {
2141                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2142                         ring->irq_get = gen5_ring_get_irq;
2143                         ring->irq_put = gen5_ring_put_irq;
2144                 } else {
2145                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2146                         ring->irq_get = i9xx_ring_get_irq;
2147                         ring->irq_put = i9xx_ring_put_irq;
2148                 }
2149                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2150         }
2151         ring->init = init_ring_common;
2152
2153         return intel_init_ring_buffer(dev, ring);
2154 }
2155
2156 /**
2157  * Initialize the second BSD ring for Broadwell GT3.
2158  * It is noted that this only exists on Broadwell GT3.
2159  */
2160 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2161 {
2162         struct drm_i915_private *dev_priv = dev->dev_private;
2163         struct intel_ring_buffer *ring = &dev_priv->ring[VCS2];
2164
2165         if ((INTEL_INFO(dev)->gen != 8)) {
2166                 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2167                 return -EINVAL;
2168         }
2169
2170         ring->name = "bds2_ring";
2171         ring->id = VCS2;
2172
2173         ring->write_tail = ring_write_tail;
2174         ring->mmio_base = GEN8_BSD2_RING_BASE;
2175         ring->flush = gen6_bsd_ring_flush;
2176         ring->add_request = gen6_add_request;
2177         ring->get_seqno = gen6_ring_get_seqno;
2178         ring->set_seqno = ring_set_seqno;
2179         ring->irq_enable_mask =
2180                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2181         ring->irq_get = gen8_ring_get_irq;
2182         ring->irq_put = gen8_ring_put_irq;
2183         ring->dispatch_execbuffer =
2184                         gen8_ring_dispatch_execbuffer;
2185         ring->semaphore.sync_to = gen6_ring_sync;
2186         /*
2187          * The current semaphore is only applied on the pre-gen8. And there
2188          * is no bsd2 ring on the pre-gen8. So now the semaphore_register
2189          * between VCS2 and other ring is initialized as invalid.
2190          * Gen8 will initialize the sema between VCS2 and other ring later.
2191          */
2192         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2193         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2194         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2195         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2196         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2197         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2198         ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2199         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2200         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2201         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2202
2203         ring->init = init_ring_common;
2204
2205         return intel_init_ring_buffer(dev, ring);
2206 }
2207
2208 int intel_init_blt_ring_buffer(struct drm_device *dev)
2209 {
2210         struct drm_i915_private *dev_priv = dev->dev_private;
2211         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2212
2213         ring->name = "blitter ring";
2214         ring->id = BCS;
2215
2216         ring->mmio_base = BLT_RING_BASE;
2217         ring->write_tail = ring_write_tail;
2218         ring->flush = gen6_ring_flush;
2219         ring->add_request = gen6_add_request;
2220         ring->get_seqno = gen6_ring_get_seqno;
2221         ring->set_seqno = ring_set_seqno;
2222         if (INTEL_INFO(dev)->gen >= 8) {
2223                 ring->irq_enable_mask =
2224                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2225                 ring->irq_get = gen8_ring_get_irq;
2226                 ring->irq_put = gen8_ring_put_irq;
2227                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2228         } else {
2229                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2230                 ring->irq_get = gen6_ring_get_irq;
2231                 ring->irq_put = gen6_ring_put_irq;
2232                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2233         }
2234         ring->semaphore.sync_to = gen6_ring_sync;
2235         ring->semaphore.signal = gen6_signal;
2236         /*
2237          * The current semaphore is only applied on pre-gen8 platform. And
2238          * there is no VCS2 ring on the pre-gen8 platform. So the semaphore
2239          * between BCS and VCS2 is initialized as INVALID.
2240          * Gen8 will initialize the sema between BCS and VCS2 later.
2241          */
2242         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2243         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2244         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2245         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2246         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2247         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2248         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2249         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2250         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2251         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2252         ring->init = init_ring_common;
2253
2254         return intel_init_ring_buffer(dev, ring);
2255 }
2256
2257 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2258 {
2259         struct drm_i915_private *dev_priv = dev->dev_private;
2260         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2261
2262         ring->name = "video enhancement ring";
2263         ring->id = VECS;
2264
2265         ring->mmio_base = VEBOX_RING_BASE;
2266         ring->write_tail = ring_write_tail;
2267         ring->flush = gen6_ring_flush;
2268         ring->add_request = gen6_add_request;
2269         ring->get_seqno = gen6_ring_get_seqno;
2270         ring->set_seqno = ring_set_seqno;
2271
2272         if (INTEL_INFO(dev)->gen >= 8) {
2273                 ring->irq_enable_mask =
2274                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2275                 ring->irq_get = gen8_ring_get_irq;
2276                 ring->irq_put = gen8_ring_put_irq;
2277                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2278         } else {
2279                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2280                 ring->irq_get = hsw_vebox_get_irq;
2281                 ring->irq_put = hsw_vebox_put_irq;
2282                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2283         }
2284         ring->semaphore.sync_to = gen6_ring_sync;
2285         ring->semaphore.signal = gen6_signal;
2286         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2287         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2288         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2289         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2290         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2291         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2292         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2293         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2294         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2295         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2296         ring->init = init_ring_common;
2297
2298         return intel_init_ring_buffer(dev, ring);
2299 }
2300
2301 int
2302 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2303 {
2304         int ret;
2305
2306         if (!ring->gpu_caches_dirty)
2307                 return 0;
2308
2309         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2310         if (ret)
2311                 return ret;
2312
2313         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2314
2315         ring->gpu_caches_dirty = false;
2316         return 0;
2317 }
2318
2319 int
2320 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2321 {
2322         uint32_t flush_domains;
2323         int ret;
2324
2325         flush_domains = 0;
2326         if (ring->gpu_caches_dirty)
2327                 flush_domains = I915_GEM_GPU_DOMAINS;
2328
2329         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2330         if (ret)
2331                 return ret;
2332
2333         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2334
2335         ring->gpu_caches_dirty = false;
2336         return 0;
2337 }
2338
2339 void
2340 intel_stop_ring_buffer(struct intel_ring_buffer *ring)
2341 {
2342         int ret;
2343
2344         if (!intel_ring_initialized(ring))
2345                 return;
2346
2347         ret = intel_ring_idle(ring);
2348         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2349                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2350                           ring->name, ret);
2351
2352         stop_ring(ring);
2353 }