drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /* Rough estimate of the typical request size, performing a flush,
  38  * set-context and then emitting the batch.
  39  */
  40 #define LEGACY_REQUEST_SIZE 200
  41
  42 int __intel_ring_space(int head, int tail, int size)
  43 {
  44         int space = head - tail;
  45         if (space <= 0)
  46                 space += size;
  47         return space - I915_RING_FREE_SPACE;
  48 }
  49
  50 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  51 {
  52         if (ringbuf->last_retired_head != -1) {
  53                 ringbuf->head = ringbuf->last_retired_head;
  54                 ringbuf->last_retired_head = -1;
  55         }
  56
  57         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  58                                             ringbuf->tail, ringbuf->size);
  59 }
  60
  61 bool intel_engine_stopped(struct intel_engine_cs *engine)
  62 {
  63         struct drm_i915_private *dev_priv = engine->i915;
  64         return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
  65 }
  66
  67 static void __intel_ring_advance(struct intel_engine_cs *engine)
  68 {
  69         struct intel_ringbuffer *ringbuf = engine->buffer;
  70         ringbuf->tail &= ringbuf->size - 1;
  71         if (intel_engine_stopped(engine))
  72                 return;
  73         engine->write_tail(engine, ringbuf->tail);
  74 }
  75
  76 static int
  77 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  78                        u32      invalidate_domains,
  79                        u32      flush_domains)
  80 {
  81         struct intel_engine_cs *engine = req->engine;
  82         u32 cmd;
  83         int ret;
  84
  85         cmd = MI_FLUSH;
  86         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  87                 cmd |= MI_NO_WRITE_FLUSH;
  88
  89         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  90                 cmd |= MI_READ_FLUSH;
  91
  92         ret = intel_ring_begin(req, 2);
  93         if (ret)
  94                 return ret;
  95
  96         intel_ring_emit(engine, cmd);
  97         intel_ring_emit(engine, MI_NOOP);
  98         intel_ring_advance(engine);
  99
 100         return 0;
 101 }
 102
 103 static int
 104 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 105                        u32      invalidate_domains,
 106                        u32      flush_domains)
 107 {
 108         struct intel_engine_cs *engine = req->engine;
 109         u32 cmd;
 110         int ret;
 111
 112         /*
 113          * read/write caches:
 114          *
 115          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 116          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 117          * also flushed at 2d versus 3d pipeline switches.
 118          *
 119          * read-only caches:
 120          *
 121          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 122          * MI_READ_FLUSH is set, and is always flushed on 965.
 123          *
 124          * I915_GEM_DOMAIN_COMMAND may not exist?
 125          *
 126          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 127          * invalidated when MI_EXE_FLUSH is set.
 128          *
 129          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 130          * invalidated with every MI_FLUSH.
 131          *
 132          * TLBs:
 133          *
 134          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 135          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 136          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 137          * are flushed at any MI_FLUSH.
 138          */
 139
 140         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 141         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 142                 cmd &= ~MI_NO_WRITE_FLUSH;
 143         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 144                 cmd |= MI_EXE_FLUSH;
 145
 146         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 147             (IS_G4X(req->i915) || IS_GEN5(req->i915)))
 148                 cmd |= MI_INVALIDATE_ISP;
 149
 150         ret = intel_ring_begin(req, 2);
 151         if (ret)
 152                 return ret;
 153
 154         intel_ring_emit(engine, cmd);
 155         intel_ring_emit(engine, MI_NOOP);
 156         intel_ring_advance(engine);
 157
 158         return 0;
 159 }
 160
 161 /**
 162  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 163  * implementing two workarounds on gen6.  From section 1.4.7.1
 164  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 165  *
 166  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 167  * produced by non-pipelined state commands), software needs to first
 168  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 169  * 0.
 170  *
 171  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 172  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 173  *
 174  * And the workaround for these two requires this workaround first:
 175  *
 176  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 177  * BEFORE the pipe-control with a post-sync op and no write-cache
 178  * flushes.
 179  *
 180  * And this last workaround is tricky because of the requirements on
 181  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 182  * volume 2 part 1:
 183  *
 184  *     "1 of the following must also be set:
 185  *      - Render Target Cache Flush Enable ([12] of DW1)
 186  *      - Depth Cache Flush Enable ([0] of DW1)
 187  *      - Stall at Pixel Scoreboard ([1] of DW1)
 188  *      - Depth Stall ([13] of DW1)
 189  *      - Post-Sync Operation ([13] of DW1)
 190  *      - Notify Enable ([8] of DW1)"
 191  *
 192  * The cache flushes require the workaround flush that triggered this
 193  * one, so we can't use it.  Depth stall would trigger the same.
 194  * Post-sync nonzero is what triggered this second workaround, so we
 195  * can't use that one either.  Notify enable is IRQs, which aren't
 196  * really our business.  That leaves only stall at scoreboard.
 197  */
 198 static int
 199 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 200 {
 201         struct intel_engine_cs *engine = req->engine;
 202         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 203         int ret;
 204
 205         ret = intel_ring_begin(req, 6);
 206         if (ret)
 207                 return ret;
 208
 209         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 210         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 211                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 212         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 213         intel_ring_emit(engine, 0); /* low dword */
 214         intel_ring_emit(engine, 0); /* high dword */
 215         intel_ring_emit(engine, MI_NOOP);
 216         intel_ring_advance(engine);
 217
 218         ret = intel_ring_begin(req, 6);
 219         if (ret)
 220                 return ret;
 221
 222         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 223         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 224         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 225         intel_ring_emit(engine, 0);
 226         intel_ring_emit(engine, 0);
 227         intel_ring_emit(engine, MI_NOOP);
 228         intel_ring_advance(engine);
 229
 230         return 0;
 231 }
 232
 233 static int
 234 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 235                        u32 invalidate_domains, u32 flush_domains)
 236 {
 237         struct intel_engine_cs *engine = req->engine;
 238         u32 flags = 0;
 239         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 240         int ret;
 241
 242         /* Force SNB workarounds for PIPE_CONTROL flushes */
 243         ret = intel_emit_post_sync_nonzero_flush(req);
 244         if (ret)
 245                 return ret;
 246
 247         /* Just flush everything.  Experiments have shown that reducing the
 248          * number of bits based on the write domains has little performance
 249          * impact.
 250          */
 251         if (flush_domains) {
 252                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 253                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 254                 /*
 255                  * Ensure that any following seqno writes only happen
 256                  * when the render cache is indeed flushed.
 257                  */
 258                 flags |= PIPE_CONTROL_CS_STALL;
 259         }
 260         if (invalidate_domains) {
 261                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 262                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 263                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 264                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 265                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 266                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 267                 /*
 268                  * TLB invalidate requires a post-sync write.
 269                  */
 270                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 271         }
 272
 273         ret = intel_ring_begin(req, 4);
 274         if (ret)
 275                 return ret;
 276
 277         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 278         intel_ring_emit(engine, flags);
 279         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 280         intel_ring_emit(engine, 0);
 281         intel_ring_advance(engine);
 282
 283         return 0;
 284 }
 285
 286 static int
 287 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 288 {
 289         struct intel_engine_cs *engine = req->engine;
 290         int ret;
 291
 292         ret = intel_ring_begin(req, 4);
 293         if (ret)
 294                 return ret;
 295
 296         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 297         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 298                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 299         intel_ring_emit(engine, 0);
 300         intel_ring_emit(engine, 0);
 301         intel_ring_advance(engine);
 302
 303         return 0;
 304 }
 305
 306 static int
 307 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 308                        u32 invalidate_domains, u32 flush_domains)
 309 {
 310         struct intel_engine_cs *engine = req->engine;
 311         u32 flags = 0;
 312         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 313         int ret;
 314
 315         /*
 316          * Ensure that any following seqno writes only happen when the render
 317          * cache is indeed flushed.
 318          *
 319          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 320          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 321          * don't try to be clever and just set it unconditionally.
 322          */
 323         flags |= PIPE_CONTROL_CS_STALL;
 324
 325         /* Just flush everything.  Experiments have shown that reducing the
 326          * number of bits based on the write domains has little performance
 327          * impact.
 328          */
 329         if (flush_domains) {
 330                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 331                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 332                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 333                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 334         }
 335         if (invalidate_domains) {
 336                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 337                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 338                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 339                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 340                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 341                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 342                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 343                 /*
 344                  * TLB invalidate requires a post-sync write.
 345                  */
 346                 flags |= PIPE_CONTROL_QW_WRITE;
 347                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 348
 349                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 350
 351                 /* Workaround: we must issue a pipe_control with CS-stall bit
 352                  * set before a pipe_control command that has the state cache
 353                  * invalidate bit set. */
 354                 gen7_render_ring_cs_stall_wa(req);
 355         }
 356
 357         ret = intel_ring_begin(req, 4);
 358         if (ret)
 359                 return ret;
 360
 361         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 362         intel_ring_emit(engine, flags);
 363         intel_ring_emit(engine, scratch_addr);
 364         intel_ring_emit(engine, 0);
 365         intel_ring_advance(engine);
 366
 367         return 0;
 368 }
 369
 370 static int
 371 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 372                        u32 flags, u32 scratch_addr)
 373 {
 374         struct intel_engine_cs *engine = req->engine;
 375         int ret;
 376
 377         ret = intel_ring_begin(req, 6);
 378         if (ret)
 379                 return ret;
 380
 381         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 382         intel_ring_emit(engine, flags);
 383         intel_ring_emit(engine, scratch_addr);
 384         intel_ring_emit(engine, 0);
 385         intel_ring_emit(engine, 0);
 386         intel_ring_emit(engine, 0);
 387         intel_ring_advance(engine);
 388
 389         return 0;
 390 }
 391
 392 static int
 393 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 394                        u32 invalidate_domains, u32 flush_domains)
 395 {
 396         u32 flags = 0;
 397         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 398         int ret;
 399
 400         flags |= PIPE_CONTROL_CS_STALL;
 401
 402         if (flush_domains) {
 403                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 404                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 405                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 406                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 407         }
 408         if (invalidate_domains) {
 409                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 410                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 411                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 412                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 413                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 414                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 415                 flags |= PIPE_CONTROL_QW_WRITE;
 416                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 417
 418                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 419                 ret = gen8_emit_pipe_control(req,
 420                                              PIPE_CONTROL_CS_STALL |
 421                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 422                                              0);
 423                 if (ret)
 424                         return ret;
 425         }
 426
 427         return gen8_emit_pipe_control(req, flags, scratch_addr);
 428 }
 429
 430 static void ring_write_tail(struct intel_engine_cs *engine,
 431                             u32 value)
 432 {
 433         struct drm_i915_private *dev_priv = engine->i915;
 434         I915_WRITE_TAIL(engine, value);
 435 }
 436
 437 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 438 {
 439         struct drm_i915_private *dev_priv = engine->i915;
 440         u64 acthd;
 441
 442         if (INTEL_GEN(dev_priv) >= 8)
 443                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 444                                          RING_ACTHD_UDW(engine->mmio_base));
 445         else if (INTEL_GEN(dev_priv) >= 4)
 446                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 447         else
 448                 acthd = I915_READ(ACTHD);
 449
 450         return acthd;
 451 }
 452
 453 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 454 {
 455         struct drm_i915_private *dev_priv = engine->i915;
 456         u32 addr;
 457
 458         addr = dev_priv->status_page_dmah->busaddr;
 459         if (INTEL_GEN(dev_priv) >= 4)
 460                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 461         I915_WRITE(HWS_PGA, addr);
 462 }
 463
 464 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 465 {
 466         struct drm_i915_private *dev_priv = engine->i915;
 467         i915_reg_t mmio;
 468
 469         /* The ring status page addresses are no longer next to the rest of
 470          * the ring registers as of gen7.
 471          */
 472         if (IS_GEN7(dev_priv)) {
 473                 switch (engine->id) {
 474                 case RCS:
 475                         mmio = RENDER_HWS_PGA_GEN7;
 476                         break;
 477                 case BCS:
 478                         mmio = BLT_HWS_PGA_GEN7;
 479                         break;
 480                 /*
 481                  * VCS2 actually doesn't exist on Gen7. Only shut up
 482                  * gcc switch check warning
 483                  */
 484                 case VCS2:
 485                 case VCS:
 486                         mmio = BSD_HWS_PGA_GEN7;
 487                         break;
 488                 case VECS:
 489                         mmio = VEBOX_HWS_PGA_GEN7;
 490                         break;
 491                 }
 492         } else if (IS_GEN6(dev_priv)) {
 493                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 494         } else {
 495                 /* XXX: gen8 returns to sanity */
 496                 mmio = RING_HWS_PGA(engine->mmio_base);
 497         }
 498
 499         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 500         POSTING_READ(mmio);
 501
 502         /*
 503          * Flush the TLB for this page
 504          *
 505          * FIXME: These two bits have disappeared on gen8, so a question
 506          * arises: do we still need this and if so how should we go about
 507          * invalidating the TLB?
 508          */
 509         if (IS_GEN(dev_priv, 6, 7)) {
 510                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 511
 512                 /* ring should be idle before issuing a sync flush*/
 513                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 514
 515                 I915_WRITE(reg,
 516                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 517                                               INSTPM_SYNC_FLUSH));
 518                 if (intel_wait_for_register(dev_priv,
 519                                             reg, INSTPM_SYNC_FLUSH, 0,
 520                                             1000))
 521                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 522                                   engine->name);
 523         }
 524 }
 525
 526 static bool stop_ring(struct intel_engine_cs *engine)
 527 {
 528         struct drm_i915_private *dev_priv = engine->i915;
 529
 530         if (!IS_GEN2(dev_priv)) {
 531                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 532                 if (intel_wait_for_register(dev_priv,
 533                                             RING_MI_MODE(engine->mmio_base),
 534                                             MODE_IDLE,
 535                                             MODE_IDLE,
 536                                             1000)) {
 537                         DRM_ERROR("%s : timed out trying to stop ring\n",
 538                                   engine->name);
 539                         /* Sometimes we observe that the idle flag is not
 540                          * set even though the ring is empty. So double
 541                          * check before giving up.
 542                          */
 543                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 544                                 return false;
 545                 }
 546         }
 547
 548         I915_WRITE_CTL(engine, 0);
 549         I915_WRITE_HEAD(engine, 0);
 550         engine->write_tail(engine, 0);
 551
 552         if (!IS_GEN2(dev_priv)) {
 553                 (void)I915_READ_CTL(engine);
 554                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 555         }
 556
 557         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 558 }
 559
 560 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 561 {
 562         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 563 }
 564
 565 static int init_ring_common(struct intel_engine_cs *engine)
 566 {
 567         struct drm_i915_private *dev_priv = engine->i915;
 568         struct intel_ringbuffer *ringbuf = engine->buffer;
 569         struct drm_i915_gem_object *obj = ringbuf->obj;
 570         int ret = 0;
 571
 572         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 573
 574         if (!stop_ring(engine)) {
 575                 /* G45 ring initialization often fails to reset head to zero */
 576                 DRM_DEBUG_KMS("%s head not reset to zero "
 577                               "ctl %08x head %08x tail %08x start %08x\n",
 578                               engine->name,
 579                               I915_READ_CTL(engine),
 580                               I915_READ_HEAD(engine),
 581                               I915_READ_TAIL(engine),
 582                               I915_READ_START(engine));
 583
 584                 if (!stop_ring(engine)) {
 585                         DRM_ERROR("failed to set %s head to zero "
 586                                   "ctl %08x head %08x tail %08x start %08x\n",
 587                                   engine->name,
 588                                   I915_READ_CTL(engine),
 589                                   I915_READ_HEAD(engine),
 590                                   I915_READ_TAIL(engine),
 591                                   I915_READ_START(engine));
 592                         ret = -EIO;
 593                         goto out;
 594                 }
 595         }
 596
 597         if (I915_NEED_GFX_HWS(dev_priv))
 598                 intel_ring_setup_status_page(engine);
 599         else
 600                 ring_setup_phys_status_page(engine);
 601
 602         /* Enforce ordering by reading HEAD register back */
 603         I915_READ_HEAD(engine);
 604
 605         /* Initialize the ring. This must happen _after_ we've cleared the ring
 606          * registers with the above sequence (the readback of the HEAD registers
 607          * also enforces ordering), otherwise the hw might lose the new ring
 608          * register values. */
 609         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 610
 611         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 612         if (I915_READ_HEAD(engine))
 613                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 614                           engine->name, I915_READ_HEAD(engine));
 615         I915_WRITE_HEAD(engine, 0);
 616         (void)I915_READ_HEAD(engine);
 617
 618         I915_WRITE_CTL(engine,
 619                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 620                         | RING_VALID);
 621
 622         /* If the head is still not zero, the ring is dead */
 623         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 624                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 625                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 626                 DRM_ERROR("%s initialization failed "
 627                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 628                           engine->name,
 629                           I915_READ_CTL(engine),
 630                           I915_READ_CTL(engine) & RING_VALID,
 631                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 632                           I915_READ_START(engine),
 633                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 634                 ret = -EIO;
 635                 goto out;
 636         }
 637
 638         ringbuf->last_retired_head = -1;
 639         ringbuf->head = I915_READ_HEAD(engine);
 640         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 641         intel_ring_update_space(ringbuf);
 642
 643         intel_engine_init_hangcheck(engine);
 644
 645 out:
 646         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 647
 648         return ret;
 649 }
 650
 651 void
 652 intel_fini_pipe_control(struct intel_engine_cs *engine)
 653 {
 654         if (engine->scratch.obj == NULL)
 655                 return;
 656
 657         if (INTEL_GEN(engine->i915) >= 5) {
 658                 kunmap(sg_page(engine->scratch.obj->pages->sgl));
 659                 i915_gem_object_ggtt_unpin(engine->scratch.obj);
 660         }
 661
 662         drm_gem_object_unreference(&engine->scratch.obj->base);
 663         engine->scratch.obj = NULL;
 664 }
 665
 666 int
 667 intel_init_pipe_control(struct intel_engine_cs *engine)
 668 {
 669         int ret;
 670
 671         WARN_ON(engine->scratch.obj);
 672
 673         engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
 674         if (IS_ERR(engine->scratch.obj)) {
 675                 DRM_ERROR("Failed to allocate seqno page\n");
 676                 ret = PTR_ERR(engine->scratch.obj);
 677                 engine->scratch.obj = NULL;
 678                 goto err;
 679         }
 680
 681         ret = i915_gem_object_set_cache_level(engine->scratch.obj,
 682                                               I915_CACHE_LLC);
 683         if (ret)
 684                 goto err_unref;
 685
 686         ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
 687         if (ret)
 688                 goto err_unref;
 689
 690         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
 691         engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
 692         if (engine->scratch.cpu_page == NULL) {
 693                 ret = -ENOMEM;
 694                 goto err_unpin;
 695         }
 696
 697         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 698                          engine->name, engine->scratch.gtt_offset);
 699         return 0;
 700
 701 err_unpin:
 702         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 703 err_unref:
 704         drm_gem_object_unreference(&engine->scratch.obj->base);
 705 err:
 706         return ret;
 707 }
 708
 709 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 710 {
 711         struct intel_engine_cs *engine = req->engine;
 712         struct i915_workarounds *w = &req->i915->workarounds;
 713         int ret, i;
 714
 715         if (w->count == 0)
 716                 return 0;
 717
 718         engine->gpu_caches_dirty = true;
 719         ret = intel_ring_flush_all_caches(req);
 720         if (ret)
 721                 return ret;
 722
 723         ret = intel_ring_begin(req, (w->count * 2 + 2));
 724         if (ret)
 725                 return ret;
 726
 727         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 728         for (i = 0; i < w->count; i++) {
 729                 intel_ring_emit_reg(engine, w->reg[i].addr);
 730                 intel_ring_emit(engine, w->reg[i].value);
 731         }
 732         intel_ring_emit(engine, MI_NOOP);
 733
 734         intel_ring_advance(engine);
 735
 736         engine->gpu_caches_dirty = true;
 737         ret = intel_ring_flush_all_caches(req);
 738         if (ret)
 739                 return ret;
 740
 741         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 742
 743         return 0;
 744 }
 745
 746 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 747 {
 748         int ret;
 749
 750         ret = intel_ring_workarounds_emit(req);
 751         if (ret != 0)
 752                 return ret;
 753
 754         ret = i915_gem_render_state_init(req);
 755         if (ret)
 756                 return ret;
 757
 758         return 0;
 759 }
 760
 761 static int wa_add(struct drm_i915_private *dev_priv,
 762                   i915_reg_t addr,
 763                   const u32 mask, const u32 val)
 764 {
 765         const u32 idx = dev_priv->workarounds.count;
 766
 767         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 768                 return -ENOSPC;
 769
 770         dev_priv->workarounds.reg[idx].addr = addr;
 771         dev_priv->workarounds.reg[idx].value = val;
 772         dev_priv->workarounds.reg[idx].mask = mask;
 773
 774         dev_priv->workarounds.count++;
 775
 776         return 0;
 777 }
 778
 779 #define WA_REG(addr, mask, val) do { \
 780                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 781                 if (r) \
 782                         return r; \
 783         } while (0)
 784
 785 #define WA_SET_BIT_MASKED(addr, mask) \
 786         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 787
 788 #define WA_CLR_BIT_MASKED(addr, mask) \
 789         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 790
 791 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 792         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 793
 794 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 795 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 796
 797 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 798
 799 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 800                                  i915_reg_t reg)
 801 {
 802         struct drm_i915_private *dev_priv = engine->i915;
 803         struct i915_workarounds *wa = &dev_priv->workarounds;
 804         const uint32_t index = wa->hw_whitelist_count[engine->id];
 805
 806         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 807                 return -EINVAL;
 808
 809         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 810                  i915_mmio_reg_offset(reg));
 811         wa->hw_whitelist_count[engine->id]++;
 812
 813         return 0;
 814 }
 815
 816 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 817 {
 818         struct drm_i915_private *dev_priv = engine->i915;
 819
 820         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 821
 822         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 823         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 824
 825         /* WaDisablePartialInstShootdown:bdw,chv */
 826         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 827                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 828
 829         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 830          * workaround for for a possible hang in the unlikely event a TLB
 831          * invalidation occurs during a PSD flush.
 832          */
 833         /* WaForceEnableNonCoherent:bdw,chv */
 834         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 835         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 836                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 837                           HDC_FORCE_NON_COHERENT);
 838
 839         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 840          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 841          *  polygons in the same 8x4 pixel/sample area to be processed without
 842          *  stalling waiting for the earlier ones to write to Hierarchical Z
 843          *  buffer."
 844          *
 845          * This optimization is off by default for BDW and CHV; turn it on.
 846          */
 847         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 848
 849         /* Wa4x4STCOptimizationDisable:bdw,chv */
 850         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 851
 852         /*
 853          * BSpec recommends 8x4 when MSAA is used,
 854          * however in practice 16x4 seems fastest.
 855          *
 856          * Note that PS/WM thread counts depend on the WIZ hashing
 857          * disable bit, which we don't touch here, but it's good
 858          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 859          */
 860         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 861                             GEN6_WIZ_HASHING_MASK,
 862                             GEN6_WIZ_HASHING_16x4);
 863
 864         return 0;
 865 }
 866
 867 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 868 {
 869         struct drm_i915_private *dev_priv = engine->i915;
 870         int ret;
 871
 872         ret = gen8_init_workarounds(engine);
 873         if (ret)
 874                 return ret;
 875
 876         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 877         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 878
 879         /* WaDisableDopClockGating:bdw */
 880         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 881                           DOP_CLOCK_GATING_DISABLE);
 882
 883         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 884                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 885
 886         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 887                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 888                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 889                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 890                           (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 891
 892         return 0;
 893 }
 894
 895 static int chv_init_workarounds(struct intel_engine_cs *engine)
 896 {
 897         struct drm_i915_private *dev_priv = engine->i915;
 898         int ret;
 899
 900         ret = gen8_init_workarounds(engine);
 901         if (ret)
 902                 return ret;
 903
 904         /* WaDisableThreadStallDopClockGating:chv */
 905         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 906
 907         /* Improve HiZ throughput on CHV. */
 908         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 909
 910         return 0;
 911 }
 912
 913 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 914 {
 915         struct drm_i915_private *dev_priv = engine->i915;
 916         int ret;
 917
 918         /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
 919         I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
 920
 921         /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
 922         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 923                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 924
 925         /* WaDisableKillLogic:bxt,skl,kbl */
 926         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 927                    ECOCHK_DIS_TLB);
 928
 929         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
 930         /* WaDisablePartialInstShootdown:skl,bxt,kbl */
 931         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 932                           FLOW_CONTROL_ENABLE |
 933                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 934
 935         /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
 936         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 937                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 938
 939         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 940         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
 941             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 942                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 943                                   GEN9_DG_MIRROR_FIX_ENABLE);
 944
 945         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 946         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
 947             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
 948                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 949                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 950                 /*
 951                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 952                  * but we do that in per ctx batchbuffer as there is an issue
 953                  * with this register not getting restored on ctx restore
 954                  */
 955         }
 956
 957         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
 958         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
 959         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 960                           GEN9_ENABLE_YV12_BUGFIX |
 961                           GEN9_ENABLE_GPGPU_PREEMPTION);
 962
 963         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
 964         /* WaDisablePartialResolveInVc:skl,bxt,kbl */
 965         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 966                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 967
 968         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
 969         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 970                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 971
 972         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 973         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
 974             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 975                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 976                                   PIXEL_MASK_CAMMING_DISABLE);
 977
 978         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
 979         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 980                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 981                           HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 982
 983         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 984          * both tied to WaForceContextSaveRestoreNonCoherent
 985          * in some hsds for skl. We keep the tie for all gen9. The
 986          * documentation is a bit hazy and so we want to get common behaviour,
 987          * even though there is no clear evidence we would need both on kbl/bxt.
 988          * This area has been source of system hangs so we play it safe
 989          * and mimic the skl regardless of what bspec says.
 990          *
 991          * Use Force Non-Coherent whenever executing a 3D context. This
 992          * is a workaround for a possible hang in the unlikely event
 993          * a TLB invalidation occurs during a PSD flush.
 994          */
 995
 996         /* WaForceEnableNonCoherent:skl,bxt,kbl */
 997         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 998                           HDC_FORCE_NON_COHERENT);
 999
1000         /* WaDisableHDCInvalidation:skl,bxt,kbl */
1001         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1002                    BDW_DISABLE_HDC_INVALIDATION);
1003
1004         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1005         if (IS_SKYLAKE(dev_priv) ||
1006             IS_KABYLAKE(dev_priv) ||
1007             IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1008                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1009                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
1010
1011         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
1012         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1013
1014         /* WaOCLCoherentLineFlush:skl,bxt,kbl */
1015         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
1016                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
1017
1018         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1019         ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1020         if (ret)
1021                 return ret;
1022
1023         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1024         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1025         if (ret)
1026                 return ret;
1027
1028         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1029         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1030         if (ret)
1031                 return ret;
1032
1033         return 0;
1034 }
1035
1036 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1037 {
1038         struct drm_i915_private *dev_priv = engine->i915;
1039         u8 vals[3] = { 0, 0, 0 };
1040         unsigned int i;
1041
1042         for (i = 0; i < 3; i++) {
1043                 u8 ss;
1044
1045                 /*
1046                  * Only consider slices where one, and only one, subslice has 7
1047                  * EUs
1048                  */
1049                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1050                         continue;
1051
1052                 /*
1053                  * subslice_7eu[i] != 0 (because of the check above) and
1054                  * ss_max == 4 (maximum number of subslices possible per slice)
1055                  *
1056                  * ->    0 <= ss <= 3;
1057                  */
1058                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1059                 vals[i] = 3 - ss;
1060         }
1061
1062         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1063                 return 0;
1064
1065         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1066         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1067                             GEN9_IZ_HASHING_MASK(2) |
1068                             GEN9_IZ_HASHING_MASK(1) |
1069                             GEN9_IZ_HASHING_MASK(0),
1070                             GEN9_IZ_HASHING(2, vals[2]) |
1071                             GEN9_IZ_HASHING(1, vals[1]) |
1072                             GEN9_IZ_HASHING(0, vals[0]));
1073
1074         return 0;
1075 }
1076
1077 static int skl_init_workarounds(struct intel_engine_cs *engine)
1078 {
1079         struct drm_i915_private *dev_priv = engine->i915;
1080         int ret;
1081
1082         ret = gen9_init_workarounds(engine);
1083         if (ret)
1084                 return ret;
1085
1086         /*
1087          * Actual WA is to disable percontext preemption granularity control
1088          * until D0 which is the default case so this is equivalent to
1089          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1090          */
1091         if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
1092                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1093                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1094         }
1095
1096         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
1097                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1098                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1099                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1100         }
1101
1102         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1103          * involving this register should also be added to WA batch as required.
1104          */
1105         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
1106                 /* WaDisableLSQCROPERFforOCL:skl */
1107                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1108                            GEN8_LQSC_RO_PERF_DIS);
1109
1110         /* WaEnableGapsTsvCreditFix:skl */
1111         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
1112                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1113                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1114         }
1115
1116         /* WaDisablePowerCompilerClockGating:skl */
1117         if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
1118                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1119                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1120
1121         /* WaBarrierPerformanceFixDisable:skl */
1122         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
1123                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1124                                   HDC_FENCE_DEST_SLM_DISABLE |
1125                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1126
1127         /* WaDisableSbeCacheDispatchPortSharing:skl */
1128         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
1129                 WA_SET_BIT_MASKED(
1130                         GEN7_HALF_SLICE_CHICKEN1,
1131                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1132
1133         /* WaDisableGafsUnitClkGating:skl */
1134         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1135
1136         /* WaDisableLSQCROPERFforOCL:skl */
1137         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1138         if (ret)
1139                 return ret;
1140
1141         return skl_tune_iz_hashing(engine);
1142 }
1143
1144 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1145 {
1146         struct drm_i915_private *dev_priv = engine->i915;
1147         int ret;
1148
1149         ret = gen9_init_workarounds(engine);
1150         if (ret)
1151                 return ret;
1152
1153         /* WaStoreMultiplePTEenable:bxt */
1154         /* This is a requirement according to Hardware specification */
1155         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1156                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1157
1158         /* WaSetClckGatingDisableMedia:bxt */
1159         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1160                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1161                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1162         }
1163
1164         /* WaDisableThreadStallDopClockGating:bxt */
1165         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1166                           STALL_DOP_GATING_DISABLE);
1167
1168         /* WaDisablePooledEuLoadBalancingFix:bxt */
1169         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
1170                 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
1171                                   GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1172         }
1173
1174         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1175         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
1176                 WA_SET_BIT_MASKED(
1177                         GEN7_HALF_SLICE_CHICKEN1,
1178                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1179         }
1180
1181         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1182         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1183         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1184         /* WaDisableLSQCROPERFforOCL:bxt */
1185         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1186                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1187                 if (ret)
1188                         return ret;
1189
1190                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1191                 if (ret)
1192                         return ret;
1193         }
1194
1195         /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1196         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
1197                 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1198                                            L3_HIGH_PRIO_CREDITS(2));
1199
1200         /* WaInsertDummyPushConstPs:bxt */
1201         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1202                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1203                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1204
1205         return 0;
1206 }
1207
1208 static int kbl_init_workarounds(struct intel_engine_cs *engine)
1209 {
1210         struct drm_i915_private *dev_priv = engine->i915;
1211         int ret;
1212
1213         ret = gen9_init_workarounds(engine);
1214         if (ret)
1215                 return ret;
1216
1217         /* WaEnableGapsTsvCreditFix:kbl */
1218         I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1219                                    GEN9_GAPS_TSV_CREDIT_DISABLE));
1220
1221         /* WaDisableDynamicCreditSharing:kbl */
1222         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1223                 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1224                            GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1225
1226         /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1227         if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1228                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1229                                   HDC_FENCE_DEST_SLM_DISABLE);
1230
1231         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1232          * involving this register should also be added to WA batch as required.
1233          */
1234         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1235                 /* WaDisableLSQCROPERFforOCL:kbl */
1236                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1237                            GEN8_LQSC_RO_PERF_DIS);
1238
1239         /* WaInsertDummyPushConstPs:kbl */
1240         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1241                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1242                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1243
1244         /* WaDisableGafsUnitClkGating:kbl */
1245         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1246
1247         /* WaDisableSbeCacheDispatchPortSharing:kbl */
1248         WA_SET_BIT_MASKED(
1249                 GEN7_HALF_SLICE_CHICKEN1,
1250                 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1251
1252         /* WaDisableLSQCROPERFforOCL:kbl */
1253         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1254         if (ret)
1255                 return ret;
1256
1257         return 0;
1258 }
1259
1260 int init_workarounds_ring(struct intel_engine_cs *engine)
1261 {
1262         struct drm_i915_private *dev_priv = engine->i915;
1263
1264         WARN_ON(engine->id != RCS);
1265
1266         dev_priv->workarounds.count = 0;
1267         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1268
1269         if (IS_BROADWELL(dev_priv))
1270                 return bdw_init_workarounds(engine);
1271
1272         if (IS_CHERRYVIEW(dev_priv))
1273                 return chv_init_workarounds(engine);
1274
1275         if (IS_SKYLAKE(dev_priv))
1276                 return skl_init_workarounds(engine);
1277
1278         if (IS_BROXTON(dev_priv))
1279                 return bxt_init_workarounds(engine);
1280
1281         if (IS_KABYLAKE(dev_priv))
1282                 return kbl_init_workarounds(engine);
1283
1284         return 0;
1285 }
1286
1287 static int init_render_ring(struct intel_engine_cs *engine)
1288 {
1289         struct drm_i915_private *dev_priv = engine->i915;
1290         int ret = init_ring_common(engine);
1291         if (ret)
1292                 return ret;
1293
1294         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1295         if (IS_GEN(dev_priv, 4, 6))
1296                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1297
1298         /* We need to disable the AsyncFlip performance optimisations in order
1299          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1300          * programmed to '1' on all products.
1301          *
1302          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1303          */
1304         if (IS_GEN(dev_priv, 6, 7))
1305                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1306
1307         /* Required for the hardware to program scanline values for waiting */
1308         /* WaEnableFlushTlbInvalidationMode:snb */
1309         if (IS_GEN6(dev_priv))
1310                 I915_WRITE(GFX_MODE,
1311                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1312
1313         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1314         if (IS_GEN7(dev_priv))
1315                 I915_WRITE(GFX_MODE_GEN7,
1316                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1317                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1318
1319         if (IS_GEN6(dev_priv)) {
1320                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1321                  * "If this bit is set, STCunit will have LRA as replacement
1322                  *  policy. [...] This bit must be reset.  LRA replacement
1323                  *  policy is not supported."
1324                  */
1325                 I915_WRITE(CACHE_MODE_0,
1326                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1327         }
1328
1329         if (IS_GEN(dev_priv, 6, 7))
1330                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1331
1332         if (HAS_L3_DPF(dev_priv))
1333                 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
1334
1335         return init_workarounds_ring(engine);
1336 }
1337
1338 static void render_ring_cleanup(struct intel_engine_cs *engine)
1339 {
1340         struct drm_i915_private *dev_priv = engine->i915;
1341
1342         if (dev_priv->semaphore_obj) {
1343                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1344                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1345                 dev_priv->semaphore_obj = NULL;
1346         }
1347
1348         intel_fini_pipe_control(engine);
1349 }
1350
1351 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1352                            unsigned int num_dwords)
1353 {
1354 #define MBOX_UPDATE_DWORDS 8
1355         struct intel_engine_cs *signaller = signaller_req->engine;
1356         struct drm_i915_private *dev_priv = signaller_req->i915;
1357         struct intel_engine_cs *waiter;
1358         enum intel_engine_id id;
1359         int ret, num_rings;
1360
1361         num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1362         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1363 #undef MBOX_UPDATE_DWORDS
1364
1365         ret = intel_ring_begin(signaller_req, num_dwords);
1366         if (ret)
1367                 return ret;
1368
1369         for_each_engine_id(waiter, dev_priv, id) {
1370                 u32 seqno;
1371                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1372                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1373                         continue;
1374
1375                 seqno = i915_gem_request_get_seqno(signaller_req);
1376                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1377                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1378                                            PIPE_CONTROL_QW_WRITE |
1379                                            PIPE_CONTROL_CS_STALL);
1380                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1381                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1382                 intel_ring_emit(signaller, seqno);
1383                 intel_ring_emit(signaller, 0);
1384                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1385                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1386                 intel_ring_emit(signaller, 0);
1387         }
1388
1389         return 0;
1390 }
1391
1392 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1393                            unsigned int num_dwords)
1394 {
1395 #define MBOX_UPDATE_DWORDS 6
1396         struct intel_engine_cs *signaller = signaller_req->engine;
1397         struct drm_i915_private *dev_priv = signaller_req->i915;
1398         struct intel_engine_cs *waiter;
1399         enum intel_engine_id id;
1400         int ret, num_rings;
1401
1402         num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1403         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1404 #undef MBOX_UPDATE_DWORDS
1405
1406         ret = intel_ring_begin(signaller_req, num_dwords);
1407         if (ret)
1408                 return ret;
1409
1410         for_each_engine_id(waiter, dev_priv, id) {
1411                 u32 seqno;
1412                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1413                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1414                         continue;
1415
1416                 seqno = i915_gem_request_get_seqno(signaller_req);
1417                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1418                                            MI_FLUSH_DW_OP_STOREDW);
1419                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1420                                            MI_FLUSH_DW_USE_GTT);
1421                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1422                 intel_ring_emit(signaller, seqno);
1423                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1424                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1425                 intel_ring_emit(signaller, 0);
1426         }
1427
1428         return 0;
1429 }
1430
1431 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1432                        unsigned int num_dwords)
1433 {
1434         struct intel_engine_cs *signaller = signaller_req->engine;
1435         struct drm_i915_private *dev_priv = signaller_req->i915;
1436         struct intel_engine_cs *useless;
1437         enum intel_engine_id id;
1438         int ret, num_rings;
1439
1440 #define MBOX_UPDATE_DWORDS 3
1441         num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1442         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1443 #undef MBOX_UPDATE_DWORDS
1444
1445         ret = intel_ring_begin(signaller_req, num_dwords);
1446         if (ret)
1447                 return ret;
1448
1449         for_each_engine_id(useless, dev_priv, id) {
1450                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1451
1452                 if (i915_mmio_reg_valid(mbox_reg)) {
1453                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1454
1455                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1456                         intel_ring_emit_reg(signaller, mbox_reg);
1457                         intel_ring_emit(signaller, seqno);
1458                 }
1459         }
1460
1461         /* If num_dwords was rounded, make sure the tail pointer is correct */
1462         if (num_rings % 2 == 0)
1463                 intel_ring_emit(signaller, MI_NOOP);
1464
1465         return 0;
1466 }
1467
1468 /**
1469  * gen6_add_request - Update the semaphore mailbox registers
1470  *
1471  * @request - request to write to the ring
1472  *
1473  * Update the mailbox registers in the *other* rings with the current seqno.
1474  * This acts like a signal in the canonical semaphore.
1475  */
1476 static int
1477 gen6_add_request(struct drm_i915_gem_request *req)
1478 {
1479         struct intel_engine_cs *engine = req->engine;
1480         int ret;
1481
1482         if (engine->semaphore.signal)
1483                 ret = engine->semaphore.signal(req, 4);
1484         else
1485                 ret = intel_ring_begin(req, 4);
1486
1487         if (ret)
1488                 return ret;
1489
1490         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1491         intel_ring_emit(engine,
1492                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1493         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1494         intel_ring_emit(engine, MI_USER_INTERRUPT);
1495         __intel_ring_advance(engine);
1496
1497         return 0;
1498 }
1499
1500 static int
1501 gen8_render_add_request(struct drm_i915_gem_request *req)
1502 {
1503         struct intel_engine_cs *engine = req->engine;
1504         int ret;
1505
1506         if (engine->semaphore.signal)
1507                 ret = engine->semaphore.signal(req, 8);
1508         else
1509                 ret = intel_ring_begin(req, 8);
1510         if (ret)
1511                 return ret;
1512
1513         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
1514         intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB |
1515                                  PIPE_CONTROL_CS_STALL |
1516                                  PIPE_CONTROL_QW_WRITE));
1517         intel_ring_emit(engine, intel_hws_seqno_address(req->engine));
1518         intel_ring_emit(engine, 0);
1519         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1520         /* We're thrashing one dword of HWS. */
1521         intel_ring_emit(engine, 0);
1522         intel_ring_emit(engine, MI_USER_INTERRUPT);
1523         intel_ring_emit(engine, MI_NOOP);
1524         __intel_ring_advance(engine);
1525
1526         return 0;
1527 }
1528
1529 static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
1530                                               u32 seqno)
1531 {
1532         return dev_priv->last_seqno < seqno;
1533 }
1534
1535 /**
1536  * intel_ring_sync - sync the waiter to the signaller on seqno
1537  *
1538  * @waiter - ring that is waiting
1539  * @signaller - ring which has, or will signal
1540  * @seqno - seqno which the waiter will block on
1541  */
1542
1543 static int
1544 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1545                struct intel_engine_cs *signaller,
1546                u32 seqno)
1547 {
1548         struct intel_engine_cs *waiter = waiter_req->engine;
1549         struct drm_i915_private *dev_priv = waiter_req->i915;
1550         struct i915_hw_ppgtt *ppgtt;
1551         int ret;
1552
1553         ret = intel_ring_begin(waiter_req, 4);
1554         if (ret)
1555                 return ret;
1556
1557         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1558                                 MI_SEMAPHORE_GLOBAL_GTT |
1559                                 MI_SEMAPHORE_SAD_GTE_SDD);
1560         intel_ring_emit(waiter, seqno);
1561         intel_ring_emit(waiter,
1562                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1563         intel_ring_emit(waiter,
1564                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1565         intel_ring_advance(waiter);
1566
1567         /* When the !RCS engines idle waiting upon a semaphore, they lose their
1568          * pagetables and we must reload them before executing the batch.
1569          * We do this on the i915_switch_context() following the wait and
1570          * before the dispatch.
1571          */
1572         ppgtt = waiter_req->ctx->ppgtt;
1573         if (ppgtt && waiter_req->engine->id != RCS)
1574                 ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine);
1575         return 0;
1576 }
1577
1578 static int
1579 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1580                struct intel_engine_cs *signaller,
1581                u32 seqno)
1582 {
1583         struct intel_engine_cs *waiter = waiter_req->engine;
1584         u32 dw1 = MI_SEMAPHORE_MBOX |
1585                   MI_SEMAPHORE_COMPARE |
1586                   MI_SEMAPHORE_REGISTER;
1587         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1588         int ret;
1589
1590         /* Throughout all of the GEM code, seqno passed implies our current
1591          * seqno is >= the last seqno executed. However for hardware the
1592          * comparison is strictly greater than.
1593          */
1594         seqno -= 1;
1595
1596         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1597
1598         ret = intel_ring_begin(waiter_req, 4);
1599         if (ret)
1600                 return ret;
1601
1602         /* If seqno wrap happened, omit the wait with no-ops */
1603         if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
1604                 intel_ring_emit(waiter, dw1 | wait_mbox);
1605                 intel_ring_emit(waiter, seqno);
1606                 intel_ring_emit(waiter, 0);
1607                 intel_ring_emit(waiter, MI_NOOP);
1608         } else {
1609                 intel_ring_emit(waiter, MI_NOOP);
1610                 intel_ring_emit(waiter, MI_NOOP);
1611                 intel_ring_emit(waiter, MI_NOOP);
1612                 intel_ring_emit(waiter, MI_NOOP);
1613         }
1614         intel_ring_advance(waiter);
1615
1616         return 0;
1617 }
1618
1619 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1620 do {                                                                    \
1621         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1622                  PIPE_CONTROL_DEPTH_STALL);                             \
1623         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1624         intel_ring_emit(ring__, 0);                                                     \
1625         intel_ring_emit(ring__, 0);                                                     \
1626 } while (0)
1627
1628 static int
1629 pc_render_add_request(struct drm_i915_gem_request *req)
1630 {
1631         struct intel_engine_cs *engine = req->engine;
1632         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1633         int ret;
1634
1635         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1636          * incoherent with writes to memory, i.e. completely fubar,
1637          * so we need to use PIPE_NOTIFY instead.
1638          *
1639          * However, we also need to workaround the qword write
1640          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1641          * memory before requesting an interrupt.
1642          */
1643         ret = intel_ring_begin(req, 32);
1644         if (ret)
1645                 return ret;
1646
1647         intel_ring_emit(engine,
1648                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1649                         PIPE_CONTROL_WRITE_FLUSH |
1650                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1651         intel_ring_emit(engine,
1652                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1653         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1654         intel_ring_emit(engine, 0);
1655         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1656         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1657         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1658         scratch_addr += 2 * CACHELINE_BYTES;
1659         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1660         scratch_addr += 2 * CACHELINE_BYTES;
1661         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1662         scratch_addr += 2 * CACHELINE_BYTES;
1663         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1664         scratch_addr += 2 * CACHELINE_BYTES;
1665         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1666
1667         intel_ring_emit(engine,
1668                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1669                         PIPE_CONTROL_WRITE_FLUSH |
1670                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1671                         PIPE_CONTROL_NOTIFY);
1672         intel_ring_emit(engine,
1673                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1674         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1675         intel_ring_emit(engine, 0);
1676         __intel_ring_advance(engine);
1677
1678         return 0;
1679 }
1680
1681 static void
1682 gen6_seqno_barrier(struct intel_engine_cs *engine)
1683 {
1684         struct drm_i915_private *dev_priv = engine->i915;
1685
1686         /* Workaround to force correct ordering between irq and seqno writes on
1687          * ivb (and maybe also on snb) by reading from a CS register (like
1688          * ACTHD) before reading the status page.
1689          *
1690          * Note that this effectively stalls the read by the time it takes to
1691          * do a memory transaction, which more or less ensures that the write
1692          * from the GPU has sufficient time to invalidate the CPU cacheline.
1693          * Alternatively we could delay the interrupt from the CS ring to give
1694          * the write time to land, but that would incur a delay after every
1695          * batch i.e. much more frequent than a delay when waiting for the
1696          * interrupt (with the same net latency).
1697          *
1698          * Also note that to prevent whole machine hangs on gen7, we have to
1699          * take the spinlock to guard against concurrent cacheline access.
1700          */
1701         spin_lock_irq(&dev_priv->uncore.lock);
1702         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1703         spin_unlock_irq(&dev_priv->uncore.lock);
1704 }
1705
1706 static u32
1707 ring_get_seqno(struct intel_engine_cs *engine)
1708 {
1709         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1710 }
1711
1712 static void
1713 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1714 {
1715         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1716 }
1717
1718 static u32
1719 pc_render_get_seqno(struct intel_engine_cs *engine)
1720 {
1721         return engine->scratch.cpu_page[0];
1722 }
1723
1724 static void
1725 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1726 {
1727         engine->scratch.cpu_page[0] = seqno;
1728 }
1729
1730 static bool
1731 gen5_ring_get_irq(struct intel_engine_cs *engine)
1732 {
1733         struct drm_i915_private *dev_priv = engine->i915;
1734         unsigned long flags;
1735
1736         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1737                 return false;
1738
1739         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1740         if (engine->irq_refcount++ == 0)
1741                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1742         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1743
1744         return true;
1745 }
1746
1747 static void
1748 gen5_ring_put_irq(struct intel_engine_cs *engine)
1749 {
1750         struct drm_i915_private *dev_priv = engine->i915;
1751         unsigned long flags;
1752
1753         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1754         if (--engine->irq_refcount == 0)
1755                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1756         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1757 }
1758
1759 static bool
1760 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1761 {
1762         struct drm_i915_private *dev_priv = engine->i915;
1763         unsigned long flags;
1764
1765         if (!intel_irqs_enabled(dev_priv))
1766                 return false;
1767
1768         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1769         if (engine->irq_refcount++ == 0) {
1770                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1771                 I915_WRITE(IMR, dev_priv->irq_mask);
1772                 POSTING_READ(IMR);
1773         }
1774         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1775
1776         return true;
1777 }
1778
1779 static void
1780 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1781 {
1782         struct drm_i915_private *dev_priv = engine->i915;
1783         unsigned long flags;
1784
1785         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1786         if (--engine->irq_refcount == 0) {
1787                 dev_priv->irq_mask |= engine->irq_enable_mask;
1788                 I915_WRITE(IMR, dev_priv->irq_mask);
1789                 POSTING_READ(IMR);
1790         }
1791         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1792 }
1793
1794 static bool
1795 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1796 {
1797         struct drm_i915_private *dev_priv = engine->i915;
1798         unsigned long flags;
1799
1800         if (!intel_irqs_enabled(dev_priv))
1801                 return false;
1802
1803         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1804         if (engine->irq_refcount++ == 0) {
1805                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1806                 I915_WRITE16(IMR, dev_priv->irq_mask);
1807                 POSTING_READ16(IMR);
1808         }
1809         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1810
1811         return true;
1812 }
1813
1814 static void
1815 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1816 {
1817         struct drm_i915_private *dev_priv = engine->i915;
1818         unsigned long flags;
1819
1820         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1821         if (--engine->irq_refcount == 0) {
1822                 dev_priv->irq_mask |= engine->irq_enable_mask;
1823                 I915_WRITE16(IMR, dev_priv->irq_mask);
1824                 POSTING_READ16(IMR);
1825         }
1826         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1827 }
1828
1829 static int
1830 bsd_ring_flush(struct drm_i915_gem_request *req,
1831                u32     invalidate_domains,
1832                u32     flush_domains)
1833 {
1834         struct intel_engine_cs *engine = req->engine;
1835         int ret;
1836
1837         ret = intel_ring_begin(req, 2);
1838         if (ret)
1839                 return ret;
1840
1841         intel_ring_emit(engine, MI_FLUSH);
1842         intel_ring_emit(engine, MI_NOOP);
1843         intel_ring_advance(engine);
1844         return 0;
1845 }
1846
1847 static int
1848 i9xx_add_request(struct drm_i915_gem_request *req)
1849 {
1850         struct intel_engine_cs *engine = req->engine;
1851         int ret;
1852
1853         ret = intel_ring_begin(req, 4);
1854         if (ret)
1855                 return ret;
1856
1857         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1858         intel_ring_emit(engine,
1859                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1860         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1861         intel_ring_emit(engine, MI_USER_INTERRUPT);
1862         __intel_ring_advance(engine);
1863
1864         return 0;
1865 }
1866
1867 static bool
1868 gen6_ring_get_irq(struct intel_engine_cs *engine)
1869 {
1870         struct drm_i915_private *dev_priv = engine->i915;
1871         unsigned long flags;
1872
1873         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1874                 return false;
1875
1876         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1877         if (engine->irq_refcount++ == 0) {
1878                 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1879                         I915_WRITE_IMR(engine,
1880                                        ~(engine->irq_enable_mask |
1881                                          GT_PARITY_ERROR(dev_priv)));
1882                 else
1883                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1884                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1885         }
1886         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1887
1888         return true;
1889 }
1890
1891 static void
1892 gen6_ring_put_irq(struct intel_engine_cs *engine)
1893 {
1894         struct drm_i915_private *dev_priv = engine->i915;
1895         unsigned long flags;
1896
1897         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1898         if (--engine->irq_refcount == 0) {
1899                 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1900                         I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
1901                 else
1902                         I915_WRITE_IMR(engine, ~0);
1903                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1904         }
1905         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1906 }
1907
1908 static bool
1909 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1910 {
1911         struct drm_i915_private *dev_priv = engine->i915;
1912         unsigned long flags;
1913
1914         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1915                 return false;
1916
1917         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1918         if (engine->irq_refcount++ == 0) {
1919                 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1920                 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1921         }
1922         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1923
1924         return true;
1925 }
1926
1927 static void
1928 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1929 {
1930         struct drm_i915_private *dev_priv = engine->i915;
1931         unsigned long flags;
1932
1933         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1934         if (--engine->irq_refcount == 0) {
1935                 I915_WRITE_IMR(engine, ~0);
1936                 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1937         }
1938         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1939 }
1940
1941 static bool
1942 gen8_ring_get_irq(struct intel_engine_cs *engine)
1943 {
1944         struct drm_i915_private *dev_priv = engine->i915;
1945         unsigned long flags;
1946
1947         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1948                 return false;
1949
1950         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1951         if (engine->irq_refcount++ == 0) {
1952                 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
1953                         I915_WRITE_IMR(engine,
1954                                        ~(engine->irq_enable_mask |
1955                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1956                 } else {
1957                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1958                 }
1959                 POSTING_READ(RING_IMR(engine->mmio_base));
1960         }
1961         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1962
1963         return true;
1964 }
1965
1966 static void
1967 gen8_ring_put_irq(struct intel_engine_cs *engine)
1968 {
1969         struct drm_i915_private *dev_priv = engine->i915;
1970         unsigned long flags;
1971
1972         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1973         if (--engine->irq_refcount == 0) {
1974                 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
1975                         I915_WRITE_IMR(engine,
1976                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1977                 } else {
1978                         I915_WRITE_IMR(engine, ~0);
1979                 }
1980                 POSTING_READ(RING_IMR(engine->mmio_base));
1981         }
1982         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1983 }
1984
1985 static int
1986 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1987                          u64 offset, u32 length,
1988                          unsigned dispatch_flags)
1989 {
1990         struct intel_engine_cs *engine = req->engine;
1991         int ret;
1992
1993         ret = intel_ring_begin(req, 2);
1994         if (ret)
1995                 return ret;
1996
1997         intel_ring_emit(engine,
1998                         MI_BATCH_BUFFER_START |
1999                         MI_BATCH_GTT |
2000                         (dispatch_flags & I915_DISPATCH_SECURE ?
2001                          0 : MI_BATCH_NON_SECURE_I965));
2002         intel_ring_emit(engine, offset);
2003         intel_ring_advance(engine);
2004
2005         return 0;
2006 }
2007
2008 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
2009 #define I830_BATCH_LIMIT (256*1024)
2010 #define I830_TLB_ENTRIES (2)
2011 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
2012 static int
2013 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
2014                          u64 offset, u32 len,
2015                          unsigned dispatch_flags)
2016 {
2017         struct intel_engine_cs *engine = req->engine;
2018         u32 cs_offset = engine->scratch.gtt_offset;
2019         int ret;
2020
2021         ret = intel_ring_begin(req, 6);
2022         if (ret)
2023                 return ret;
2024
2025         /* Evict the invalid PTE TLBs */
2026         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
2027         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
2028         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
2029         intel_ring_emit(engine, cs_offset);
2030         intel_ring_emit(engine, 0xdeadbeef);
2031         intel_ring_emit(engine, MI_NOOP);
2032         intel_ring_advance(engine);
2033
2034         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
2035                 if (len > I830_BATCH_LIMIT)
2036                         return -ENOSPC;
2037
2038                 ret = intel_ring_begin(req, 6 + 2);
2039                 if (ret)
2040                         return ret;
2041
2042                 /* Blit the batch (which has now all relocs applied) to the
2043                  * stable batch scratch bo area (so that the CS never
2044                  * stumbles over its tlb invalidation bug) ...
2045                  */
2046                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
2047                 intel_ring_emit(engine,
2048                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
2049                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
2050                 intel_ring_emit(engine, cs_offset);
2051                 intel_ring_emit(engine, 4096);
2052                 intel_ring_emit(engine, offset);
2053
2054                 intel_ring_emit(engine, MI_FLUSH);
2055                 intel_ring_emit(engine, MI_NOOP);
2056                 intel_ring_advance(engine);
2057
2058                 /* ... and execute it. */
2059                 offset = cs_offset;
2060         }
2061
2062         ret = intel_ring_begin(req, 2);
2063         if (ret)
2064                 return ret;
2065
2066         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2067         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2068                                           0 : MI_BATCH_NON_SECURE));
2069         intel_ring_advance(engine);
2070
2071         return 0;
2072 }
2073
2074 static int
2075 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
2076                          u64 offset, u32 len,
2077                          unsigned dispatch_flags)
2078 {
2079         struct intel_engine_cs *engine = req->engine;
2080         int ret;
2081
2082         ret = intel_ring_begin(req, 2);
2083         if (ret)
2084                 return ret;
2085
2086         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2087         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2088                                           0 : MI_BATCH_NON_SECURE));
2089         intel_ring_advance(engine);
2090
2091         return 0;
2092 }
2093
2094 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
2095 {
2096         struct drm_i915_private *dev_priv = engine->i915;
2097
2098         if (!dev_priv->status_page_dmah)
2099                 return;
2100
2101         drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
2102         engine->status_page.page_addr = NULL;
2103 }
2104
2105 static void cleanup_status_page(struct intel_engine_cs *engine)
2106 {
2107         struct drm_i915_gem_object *obj;
2108
2109         obj = engine->status_page.obj;
2110         if (obj == NULL)
2111                 return;
2112
2113         kunmap(sg_page(obj->pages->sgl));
2114         i915_gem_object_ggtt_unpin(obj);
2115         drm_gem_object_unreference(&obj->base);
2116         engine->status_page.obj = NULL;
2117 }
2118
2119 static int init_status_page(struct intel_engine_cs *engine)
2120 {
2121         struct drm_i915_gem_object *obj = engine->status_page.obj;
2122
2123         if (obj == NULL) {
2124                 unsigned flags;
2125                 int ret;
2126
2127                 obj = i915_gem_object_create(engine->i915->dev, 4096);
2128                 if (IS_ERR(obj)) {
2129                         DRM_ERROR("Failed to allocate status page\n");
2130                         return PTR_ERR(obj);
2131                 }
2132
2133                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2134                 if (ret)
2135                         goto err_unref;
2136
2137                 flags = 0;
2138                 if (!HAS_LLC(engine->i915))
2139                         /* On g33, we cannot place HWS above 256MiB, so
2140                          * restrict its pinning to the low mappable arena.
2141                          * Though this restriction is not documented for
2142                          * gen4, gen5, or byt, they also behave similarly
2143                          * and hang if the HWS is placed at the top of the
2144                          * GTT. To generalise, it appears that all !llc
2145                          * platforms have issues with us placing the HWS
2146                          * above the mappable region (even though we never
2147                          * actualy map it).
2148                          */
2149                         flags |= PIN_MAPPABLE;
2150                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2151                 if (ret) {
2152 err_unref:
2153                         drm_gem_object_unreference(&obj->base);
2154                         return ret;
2155                 }
2156
2157                 engine->status_page.obj = obj;
2158         }
2159
2160         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2161         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2162         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2163
2164         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2165                         engine->name, engine->status_page.gfx_addr);
2166
2167         return 0;
2168 }
2169
2170 static int init_phys_status_page(struct intel_engine_cs *engine)
2171 {
2172         struct drm_i915_private *dev_priv = engine->i915;
2173
2174         if (!dev_priv->status_page_dmah) {
2175                 dev_priv->status_page_dmah =
2176                         drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
2177                 if (!dev_priv->status_page_dmah)
2178                         return -ENOMEM;
2179         }
2180
2181         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2182         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2183
2184         return 0;
2185 }
2186
2187 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2188 {
2189         GEM_BUG_ON(ringbuf->vma == NULL);
2190         GEM_BUG_ON(ringbuf->virtual_start == NULL);
2191
2192         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2193                 i915_gem_object_unpin_map(ringbuf->obj);
2194         else
2195                 i915_vma_unpin_iomap(ringbuf->vma);
2196         ringbuf->virtual_start = NULL;
2197
2198         i915_gem_object_ggtt_unpin(ringbuf->obj);
2199         ringbuf->vma = NULL;
2200 }
2201
2202 int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
2203                                      struct intel_ringbuffer *ringbuf)
2204 {
2205         struct drm_i915_gem_object *obj = ringbuf->obj;
2206         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2207         unsigned flags = PIN_OFFSET_BIAS | 4096;
2208         void *addr;
2209         int ret;
2210
2211         if (HAS_LLC(dev_priv) && !obj->stolen) {
2212                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2213                 if (ret)
2214                         return ret;
2215
2216                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2217                 if (ret)
2218                         goto err_unpin;
2219
2220                 addr = i915_gem_object_pin_map(obj);
2221                 if (IS_ERR(addr)) {
2222                         ret = PTR_ERR(addr);
2223                         goto err_unpin;
2224                 }
2225         } else {
2226                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2227                                             flags | PIN_MAPPABLE);
2228                 if (ret)
2229                         return ret;
2230
2231                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2232                 if (ret)
2233                         goto err_unpin;
2234
2235                 /* Access through the GTT requires the device to be awake. */
2236                 assert_rpm_wakelock_held(dev_priv);
2237
2238                 addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
2239                 if (IS_ERR(addr)) {
2240                         ret = PTR_ERR(addr);
2241                         goto err_unpin;
2242                 }
2243         }
2244
2245         ringbuf->virtual_start = addr;
2246         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2247         return 0;
2248
2249 err_unpin:
2250         i915_gem_object_ggtt_unpin(obj);
2251         return ret;
2252 }
2253
2254 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2255 {
2256         drm_gem_object_unreference(&ringbuf->obj->base);
2257         ringbuf->obj = NULL;
2258 }
2259
2260 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2261                                       struct intel_ringbuffer *ringbuf)
2262 {
2263         struct drm_i915_gem_object *obj;
2264
2265         obj = NULL;
2266         if (!HAS_LLC(dev))
2267                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2268         if (obj == NULL)
2269                 obj = i915_gem_object_create(dev, ringbuf->size);
2270         if (IS_ERR(obj))
2271                 return PTR_ERR(obj);
2272
2273         /* mark ring buffers as read-only from GPU side by default */
2274         obj->gt_ro = 1;
2275
2276         ringbuf->obj = obj;
2277
2278         return 0;
2279 }
2280
2281 struct intel_ringbuffer *
2282 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2283 {
2284         struct intel_ringbuffer *ring;
2285         int ret;
2286
2287         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2288         if (ring == NULL) {
2289                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2290                                  engine->name);
2291                 return ERR_PTR(-ENOMEM);
2292         }
2293
2294         ring->engine = engine;
2295         list_add(&ring->link, &engine->buffers);
2296
2297         ring->size = size;
2298         /* Workaround an erratum on the i830 which causes a hang if
2299          * the TAIL pointer points to within the last 2 cachelines
2300          * of the buffer.
2301          */
2302         ring->effective_size = size;
2303         if (IS_I830(engine->i915) || IS_845G(engine->i915))
2304                 ring->effective_size -= 2 * CACHELINE_BYTES;
2305
2306         ring->last_retired_head = -1;
2307         intel_ring_update_space(ring);
2308
2309         ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
2310         if (ret) {
2311                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2312                                  engine->name, ret);
2313                 list_del(&ring->link);
2314                 kfree(ring);
2315                 return ERR_PTR(ret);
2316         }
2317
2318         return ring;
2319 }
2320
2321 void
2322 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2323 {
2324         intel_destroy_ringbuffer_obj(ring);
2325         list_del(&ring->link);
2326         kfree(ring);
2327 }
2328
2329 static int intel_ring_context_pin(struct i915_gem_context *ctx,
2330                                   struct intel_engine_cs *engine)
2331 {
2332         struct intel_context *ce = &ctx->engine[engine->id];
2333         int ret;
2334
2335         lockdep_assert_held(&ctx->i915->dev->struct_mutex);
2336
2337         if (ce->pin_count++)
2338                 return 0;
2339
2340         if (ce->state) {
2341                 ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0);
2342                 if (ret)
2343                         goto error;
2344         }
2345
2346         /* The kernel context is only used as a placeholder for flushing the
2347          * active context. It is never used for submitting user rendering and
2348          * as such never requires the golden render context, and so we can skip
2349          * emitting it when we switch to the kernel context. This is required
2350          * as during eviction we cannot allocate and pin the renderstate in
2351          * order to initialise the context.
2352          */
2353         if (ctx == ctx->i915->kernel_context)
2354                 ce->initialised = true;
2355
2356         i915_gem_context_reference(ctx);
2357         return 0;
2358
2359 error:
2360         ce->pin_count = 0;
2361         return ret;
2362 }
2363
2364 static void intel_ring_context_unpin(struct i915_gem_context *ctx,
2365                                      struct intel_engine_cs *engine)
2366 {
2367         struct intel_context *ce = &ctx->engine[engine->id];
2368
2369         lockdep_assert_held(&ctx->i915->dev->struct_mutex);
2370
2371         if (--ce->pin_count)
2372                 return;
2373
2374         if (ce->state)
2375                 i915_gem_object_ggtt_unpin(ce->state);
2376
2377         i915_gem_context_unreference(ctx);
2378 }
2379
2380 static int intel_init_ring_buffer(struct drm_device *dev,
2381                                   struct intel_engine_cs *engine)
2382 {
2383         struct drm_i915_private *dev_priv = to_i915(dev);
2384         struct intel_ringbuffer *ringbuf;
2385         int ret;
2386
2387         WARN_ON(engine->buffer);
2388
2389         engine->i915 = dev_priv;
2390         INIT_LIST_HEAD(&engine->active_list);
2391         INIT_LIST_HEAD(&engine->request_list);
2392         INIT_LIST_HEAD(&engine->execlist_queue);
2393         INIT_LIST_HEAD(&engine->buffers);
2394         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2395         memset(engine->semaphore.sync_seqno, 0,
2396                sizeof(engine->semaphore.sync_seqno));
2397
2398         init_waitqueue_head(&engine->irq_queue);
2399
2400         /* We may need to do things with the shrinker which
2401          * require us to immediately switch back to the default
2402          * context. This can cause a problem as pinning the
2403          * default context also requires GTT space which may not
2404          * be available. To avoid this we always pin the default
2405          * context.
2406          */
2407         ret = intel_ring_context_pin(dev_priv->kernel_context, engine);
2408         if (ret)
2409                 goto error;
2410
2411         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2412         if (IS_ERR(ringbuf)) {
2413                 ret = PTR_ERR(ringbuf);
2414                 goto error;
2415         }
2416         engine->buffer = ringbuf;
2417
2418         if (I915_NEED_GFX_HWS(dev_priv)) {
2419                 ret = init_status_page(engine);
2420                 if (ret)
2421                         goto error;
2422         } else {
2423                 WARN_ON(engine->id != RCS);
2424                 ret = init_phys_status_page(engine);
2425                 if (ret)
2426                         goto error;
2427         }
2428
2429         ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
2430         if (ret) {
2431                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2432                                 engine->name, ret);
2433                 intel_destroy_ringbuffer_obj(ringbuf);
2434                 goto error;
2435         }
2436
2437         ret = i915_cmd_parser_init_ring(engine);
2438         if (ret)
2439                 goto error;
2440
2441         return 0;
2442
2443 error:
2444         intel_cleanup_engine(engine);
2445         return ret;
2446 }
2447
2448 void intel_cleanup_engine(struct intel_engine_cs *engine)
2449 {
2450         struct drm_i915_private *dev_priv;
2451
2452         if (!intel_engine_initialized(engine))
2453                 return;
2454
2455         dev_priv = engine->i915;
2456
2457         if (engine->buffer) {
2458                 intel_stop_engine(engine);
2459                 WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2460
2461                 intel_unpin_ringbuffer_obj(engine->buffer);
2462                 intel_ringbuffer_free(engine->buffer);
2463                 engine->buffer = NULL;
2464         }
2465
2466         if (engine->cleanup)
2467                 engine->cleanup(engine);
2468
2469         if (I915_NEED_GFX_HWS(dev_priv)) {
2470                 cleanup_status_page(engine);
2471         } else {
2472                 WARN_ON(engine->id != RCS);
2473                 cleanup_phys_status_page(engine);
2474         }
2475
2476         i915_cmd_parser_fini_ring(engine);
2477         i915_gem_batch_pool_fini(&engine->batch_pool);
2478
2479         intel_ring_context_unpin(dev_priv->kernel_context, engine);
2480
2481         engine->i915 = NULL;
2482 }
2483
2484 int intel_engine_idle(struct intel_engine_cs *engine)
2485 {
2486         struct drm_i915_gem_request *req;
2487
2488         /* Wait upon the last request to be completed */
2489         if (list_empty(&engine->request_list))
2490                 return 0;
2491
2492         req = list_entry(engine->request_list.prev,
2493                          struct drm_i915_gem_request,
2494                          list);
2495
2496         /* Make sure we do not trigger any retires */
2497         return __i915_wait_request(req,
2498                                    req->i915->mm.interruptible,
2499                                    NULL, NULL);
2500 }
2501
2502 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2503 {
2504         int ret;
2505
2506         /* Flush enough space to reduce the likelihood of waiting after
2507          * we start building the request - in which case we will just
2508          * have to repeat work.
2509          */
2510         request->reserved_space += LEGACY_REQUEST_SIZE;
2511
2512         request->ringbuf = request->engine->buffer;
2513
2514         ret = intel_ring_begin(request, 0);
2515         if (ret)
2516                 return ret;
2517
2518         request->reserved_space -= LEGACY_REQUEST_SIZE;
2519         return 0;
2520 }
2521
2522 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2523 {
2524         struct intel_ringbuffer *ringbuf = req->ringbuf;
2525         struct intel_engine_cs *engine = req->engine;
2526         struct drm_i915_gem_request *target;
2527
2528         intel_ring_update_space(ringbuf);
2529         if (ringbuf->space >= bytes)
2530                 return 0;
2531
2532         /*
2533          * Space is reserved in the ringbuffer for finalising the request,
2534          * as that cannot be allowed to fail. During request finalisation,
2535          * reserved_space is set to 0 to stop the overallocation and the
2536          * assumption is that then we never need to wait (which has the
2537          * risk of failing with EINTR).
2538          *
2539          * See also i915_gem_request_alloc() and i915_add_request().
2540          */
2541         GEM_BUG_ON(!req->reserved_space);
2542
2543         list_for_each_entry(target, &engine->request_list, list) {
2544                 unsigned space;
2545
2546                 /*
2547                  * The request queue is per-engine, so can contain requests
2548                  * from multiple ringbuffers. Here, we must ignore any that
2549                  * aren't from the ringbuffer we're considering.
2550                  */
2551                 if (target->ringbuf != ringbuf)
2552                         continue;
2553
2554                 /* Would completion of this request free enough space? */
2555                 space = __intel_ring_space(target->postfix, ringbuf->tail,
2556                                            ringbuf->size);
2557                 if (space >= bytes)
2558                         break;
2559         }
2560
2561         if (WARN_ON(&target->list == &engine->request_list))
2562                 return -ENOSPC;
2563
2564         return i915_wait_request(target);
2565 }
2566
2567 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2568 {
2569         struct intel_ringbuffer *ringbuf = req->ringbuf;
2570         int remain_actual = ringbuf->size - ringbuf->tail;
2571         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2572         int bytes = num_dwords * sizeof(u32);
2573         int total_bytes, wait_bytes;
2574         bool need_wrap = false;
2575
2576         total_bytes = bytes + req->reserved_space;
2577
2578         if (unlikely(bytes > remain_usable)) {
2579                 /*
2580                  * Not enough space for the basic request. So need to flush
2581                  * out the remainder and then wait for base + reserved.
2582                  */
2583                 wait_bytes = remain_actual + total_bytes;
2584                 need_wrap = true;
2585         } else if (unlikely(total_bytes > remain_usable)) {
2586                 /*
2587                  * The base request will fit but the reserved space
2588                  * falls off the end. So we don't need an immediate wrap
2589                  * and only need to effectively wait for the reserved
2590                  * size space from the start of ringbuffer.
2591                  */
2592                 wait_bytes = remain_actual + req->reserved_space;
2593         } else {
2594                 /* No wrapping required, just waiting. */
2595                 wait_bytes = total_bytes;
2596         }
2597
2598         if (wait_bytes > ringbuf->space) {
2599                 int ret = wait_for_space(req, wait_bytes);
2600                 if (unlikely(ret))
2601                         return ret;
2602
2603                 intel_ring_update_space(ringbuf);
2604                 if (unlikely(ringbuf->space < wait_bytes))
2605                         return -EAGAIN;
2606         }
2607
2608         if (unlikely(need_wrap)) {
2609                 GEM_BUG_ON(remain_actual > ringbuf->space);
2610                 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2611
2612                 /* Fill the tail with MI_NOOP */
2613                 memset(ringbuf->virtual_start + ringbuf->tail,
2614                        0, remain_actual);
2615                 ringbuf->tail = 0;
2616                 ringbuf->space -= remain_actual;
2617         }
2618
2619         ringbuf->space -= bytes;
2620         GEM_BUG_ON(ringbuf->space < 0);
2621         return 0;
2622 }
2623
2624 /* Align the ring tail to a cacheline boundary */
2625 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2626 {
2627         struct intel_engine_cs *engine = req->engine;
2628         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2629         int ret;
2630
2631         if (num_dwords == 0)
2632                 return 0;
2633
2634         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2635         ret = intel_ring_begin(req, num_dwords);
2636         if (ret)
2637                 return ret;
2638
2639         while (num_dwords--)
2640                 intel_ring_emit(engine, MI_NOOP);
2641
2642         intel_ring_advance(engine);
2643
2644         return 0;
2645 }
2646
2647 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2648 {
2649         struct drm_i915_private *dev_priv = engine->i915;
2650
2651         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2652          * so long as the semaphore value in the register/page is greater
2653          * than the sync value), so whenever we reset the seqno,
2654          * so long as we reset the tracking semaphore value to 0, it will
2655          * always be before the next request's seqno. If we don't reset
2656          * the semaphore value, then when the seqno moves backwards all
2657          * future waits will complete instantly (causing rendering corruption).
2658          */
2659         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
2660                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2661                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2662                 if (HAS_VEBOX(dev_priv))
2663                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2664         }
2665         if (dev_priv->semaphore_obj) {
2666                 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2667                 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2668                 void *semaphores = kmap(page);
2669                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2670                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2671                 kunmap(page);
2672         }
2673         memset(engine->semaphore.sync_seqno, 0,
2674                sizeof(engine->semaphore.sync_seqno));
2675
2676         engine->set_seqno(engine, seqno);
2677         engine->last_submitted_seqno = seqno;
2678
2679         engine->hangcheck.seqno = seqno;
2680 }
2681
2682 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2683                                      u32 value)
2684 {
2685         struct drm_i915_private *dev_priv = engine->i915;
2686
2687         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2688
2689        /* Every tail move must follow the sequence below */
2690
2691         /* Disable notification that the ring is IDLE. The GT
2692          * will then assume that it is busy and bring it out of rc6.
2693          */
2694         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
2695                       _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2696
2697         /* Clear the context id. Here be magic! */
2698         I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
2699
2700         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2701         if (intel_wait_for_register_fw(dev_priv,
2702                                        GEN6_BSD_SLEEP_PSMI_CONTROL,
2703                                        GEN6_BSD_SLEEP_INDICATOR,
2704                                        0,
2705                                        50))
2706                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2707
2708         /* Now that the ring is fully powered up, update the tail */
2709         I915_WRITE_FW(RING_TAIL(engine->mmio_base), value);
2710         POSTING_READ_FW(RING_TAIL(engine->mmio_base));
2711
2712         /* Let the ring send IDLE messages to the GT again,
2713          * and so let it sleep to conserve power when idle.
2714          */
2715         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
2716                       _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2717
2718         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2719 }
2720
2721 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2722                                u32 invalidate, u32 flush)
2723 {
2724         struct intel_engine_cs *engine = req->engine;
2725         uint32_t cmd;
2726         int ret;
2727
2728         ret = intel_ring_begin(req, 4);
2729         if (ret)
2730                 return ret;
2731
2732         cmd = MI_FLUSH_DW;
2733         if (INTEL_GEN(req->i915) >= 8)
2734                 cmd += 1;
2735
2736         /* We always require a command barrier so that subsequent
2737          * commands, such as breadcrumb interrupts, are strictly ordered
2738          * wrt the contents of the write cache being flushed to memory
2739          * (and thus being coherent from the CPU).
2740          */
2741         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2742
2743         /*
2744          * Bspec vol 1c.5 - video engine command streamer:
2745          * "If ENABLED, all TLBs will be invalidated once the flush
2746          * operation is complete. This bit is only valid when the
2747          * Post-Sync Operation field is a value of 1h or 3h."
2748          */
2749         if (invalidate & I915_GEM_GPU_DOMAINS)
2750                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2751
2752         intel_ring_emit(engine, cmd);
2753         intel_ring_emit(engine,
2754                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2755         if (INTEL_GEN(req->i915) >= 8) {
2756                 intel_ring_emit(engine, 0); /* upper addr */
2757                 intel_ring_emit(engine, 0); /* value */
2758         } else  {
2759                 intel_ring_emit(engine, 0);
2760                 intel_ring_emit(engine, MI_NOOP);
2761         }
2762         intel_ring_advance(engine);
2763         return 0;
2764 }
2765
2766 static int
2767 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2768                               u64 offset, u32 len,
2769                               unsigned dispatch_flags)
2770 {
2771         struct intel_engine_cs *engine = req->engine;
2772         bool ppgtt = USES_PPGTT(engine->dev) &&
2773                         !(dispatch_flags & I915_DISPATCH_SECURE);
2774         int ret;
2775
2776         ret = intel_ring_begin(req, 4);
2777         if (ret)
2778                 return ret;
2779
2780         /* FIXME(BDW): Address space and security selectors. */
2781         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2782                         (dispatch_flags & I915_DISPATCH_RS ?
2783                          MI_BATCH_RESOURCE_STREAMER : 0));
2784         intel_ring_emit(engine, lower_32_bits(offset));
2785         intel_ring_emit(engine, upper_32_bits(offset));
2786         intel_ring_emit(engine, MI_NOOP);
2787         intel_ring_advance(engine);
2788
2789         return 0;
2790 }
2791
2792 static int
2793 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2794                              u64 offset, u32 len,
2795                              unsigned dispatch_flags)
2796 {
2797         struct intel_engine_cs *engine = req->engine;
2798         int ret;
2799
2800         ret = intel_ring_begin(req, 2);
2801         if (ret)
2802                 return ret;
2803
2804         intel_ring_emit(engine,
2805                         MI_BATCH_BUFFER_START |
2806                         (dispatch_flags & I915_DISPATCH_SECURE ?
2807                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2808                         (dispatch_flags & I915_DISPATCH_RS ?
2809                          MI_BATCH_RESOURCE_STREAMER : 0));
2810         /* bit0-7 is the length on GEN6+ */
2811         intel_ring_emit(engine, offset);
2812         intel_ring_advance(engine);
2813
2814         return 0;
2815 }
2816
2817 static int
2818 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2819                               u64 offset, u32 len,
2820                               unsigned dispatch_flags)
2821 {
2822         struct intel_engine_cs *engine = req->engine;
2823         int ret;
2824
2825         ret = intel_ring_begin(req, 2);
2826         if (ret)
2827                 return ret;
2828
2829         intel_ring_emit(engine,
2830                         MI_BATCH_BUFFER_START |
2831                         (dispatch_flags & I915_DISPATCH_SECURE ?
2832                          0 : MI_BATCH_NON_SECURE_I965));
2833         /* bit0-7 is the length on GEN6+ */
2834         intel_ring_emit(engine, offset);
2835         intel_ring_advance(engine);
2836
2837         return 0;
2838 }
2839
2840 /* Blitter support (SandyBridge+) */
2841
2842 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2843                            u32 invalidate, u32 flush)
2844 {
2845         struct intel_engine_cs *engine = req->engine;
2846         uint32_t cmd;
2847         int ret;
2848
2849         ret = intel_ring_begin(req, 4);
2850         if (ret)
2851                 return ret;
2852
2853         cmd = MI_FLUSH_DW;
2854         if (INTEL_GEN(req->i915) >= 8)
2855                 cmd += 1;
2856
2857         /* We always require a command barrier so that subsequent
2858          * commands, such as breadcrumb interrupts, are strictly ordered
2859          * wrt the contents of the write cache being flushed to memory
2860          * (and thus being coherent from the CPU).
2861          */
2862         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2863
2864         /*
2865          * Bspec vol 1c.3 - blitter engine command streamer:
2866          * "If ENABLED, all TLBs will be invalidated once the flush
2867          * operation is complete. This bit is only valid when the
2868          * Post-Sync Operation field is a value of 1h or 3h."
2869          */
2870         if (invalidate & I915_GEM_DOMAIN_RENDER)
2871                 cmd |= MI_INVALIDATE_TLB;
2872         intel_ring_emit(engine, cmd);
2873         intel_ring_emit(engine,
2874                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2875         if (INTEL_GEN(req->i915) >= 8) {
2876                 intel_ring_emit(engine, 0); /* upper addr */
2877                 intel_ring_emit(engine, 0); /* value */
2878         } else  {
2879                 intel_ring_emit(engine, 0);
2880                 intel_ring_emit(engine, MI_NOOP);
2881         }
2882         intel_ring_advance(engine);
2883
2884         return 0;
2885 }
2886
2887 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2888                                       struct intel_engine_cs *engine)
2889 {
2890         engine->write_tail = ring_write_tail;
2891         engine->get_seqno = ring_get_seqno;
2892         engine->set_seqno = ring_set_seqno;
2893
2894         if (INTEL_GEN(dev_priv) >= 6) {
2895                 engine->add_request = gen6_add_request;
2896                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2897         } else {
2898                 engine->add_request = i9xx_add_request;
2899         }
2900
2901         if (INTEL_GEN(dev_priv) >= 8) {
2902                 engine->irq_get = gen8_ring_get_irq;
2903                 engine->irq_put = gen8_ring_put_irq;
2904         } else if (INTEL_GEN(dev_priv) >= 6) {
2905                 engine->irq_get = gen6_ring_get_irq;
2906                 engine->irq_put = gen6_ring_put_irq;
2907         } else if (INTEL_GEN(dev_priv) >= 5) {
2908                 engine->irq_get = gen5_ring_get_irq;
2909                 engine->irq_put = gen5_ring_put_irq;
2910         } else if (INTEL_GEN(dev_priv) >= 3) {
2911                 engine->irq_get = i9xx_ring_get_irq;
2912                 engine->irq_put = i9xx_ring_put_irq;
2913         } else {
2914                 engine->irq_get = i8xx_ring_get_irq;
2915                 engine->irq_put = i8xx_ring_put_irq;
2916         }
2917 }
2918
2919 int intel_init_render_ring_buffer(struct drm_device *dev)
2920 {
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2923         struct drm_i915_gem_object *obj;
2924         int ret;
2925
2926         engine->name = "render ring";
2927         engine->id = RCS;
2928         engine->exec_id = I915_EXEC_RENDER;
2929         engine->hw_id = 0;
2930         engine->mmio_base = RENDER_RING_BASE;
2931
2932         intel_ring_default_vfuncs(dev_priv, engine);
2933
2934         if (INTEL_GEN(dev_priv) >= 8) {
2935                 if (i915_semaphore_is_enabled(dev_priv)) {
2936                         obj = i915_gem_object_create(dev, 4096);
2937                         if (IS_ERR(obj)) {
2938                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2939                                 i915.semaphores = 0;
2940                         } else {
2941                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2942                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2943                                 if (ret != 0) {
2944                                         drm_gem_object_unreference(&obj->base);
2945                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2946                                         i915.semaphores = 0;
2947                                 } else
2948                                         dev_priv->semaphore_obj = obj;
2949                         }
2950                 }
2951
2952                 engine->init_context = intel_rcs_ctx_init;
2953                 engine->add_request = gen8_render_add_request;
2954                 engine->flush = gen8_render_ring_flush;
2955                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2956                 if (i915_semaphore_is_enabled(dev_priv)) {
2957                         WARN_ON(!dev_priv->semaphore_obj);
2958                         engine->semaphore.sync_to = gen8_ring_sync;
2959                         engine->semaphore.signal = gen8_rcs_signal;
2960                         GEN8_RING_SEMAPHORE_INIT(engine);
2961                 }
2962         } else if (INTEL_GEN(dev_priv) >= 6) {
2963                 engine->init_context = intel_rcs_ctx_init;
2964                 engine->flush = gen7_render_ring_flush;
2965                 if (IS_GEN6(dev_priv))
2966                         engine->flush = gen6_render_ring_flush;
2967                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2968                 if (i915_semaphore_is_enabled(dev_priv)) {
2969                         engine->semaphore.sync_to = gen6_ring_sync;
2970                         engine->semaphore.signal = gen6_signal;
2971                         /*
2972                          * The current semaphore is only applied on pre-gen8
2973                          * platform.  And there is no VCS2 ring on the pre-gen8
2974                          * platform. So the semaphore between RCS and VCS2 is
2975                          * initialized as INVALID.  Gen8 will initialize the
2976                          * sema between VCS2 and RCS later.
2977                          */
2978                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2979                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2980                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2981                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2982                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2983                         engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2984                         engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2985                         engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2986                         engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2987                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2988                 }
2989         } else if (IS_GEN5(dev_priv)) {
2990                 engine->add_request = pc_render_add_request;
2991                 engine->flush = gen4_render_ring_flush;
2992                 engine->get_seqno = pc_render_get_seqno;
2993                 engine->set_seqno = pc_render_set_seqno;
2994                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2995                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2996         } else {
2997                 if (INTEL_GEN(dev_priv) < 4)
2998                         engine->flush = gen2_render_ring_flush;
2999                 else
3000                         engine->flush = gen4_render_ring_flush;
3001                 engine->irq_enable_mask = I915_USER_INTERRUPT;
3002         }
3003
3004         if (IS_HASWELL(dev_priv))
3005                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
3006         else if (IS_GEN8(dev_priv))
3007                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3008         else if (INTEL_GEN(dev_priv) >= 6)
3009                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3010         else if (INTEL_GEN(dev_priv) >= 4)
3011                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
3012         else if (IS_I830(dev_priv) || IS_845G(dev_priv))
3013                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
3014         else
3015                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
3016         engine->init_hw = init_render_ring;
3017         engine->cleanup = render_ring_cleanup;
3018
3019         /* Workaround batchbuffer to combat CS tlb bug. */
3020         if (HAS_BROKEN_CS_TLB(dev_priv)) {
3021                 obj = i915_gem_object_create(dev, I830_WA_SIZE);
3022                 if (IS_ERR(obj)) {
3023                         DRM_ERROR("Failed to allocate batch bo\n");
3024                         return PTR_ERR(obj);
3025                 }
3026
3027                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
3028                 if (ret != 0) {
3029                         drm_gem_object_unreference(&obj->base);
3030                         DRM_ERROR("Failed to ping batch bo\n");
3031                         return ret;
3032                 }
3033
3034                 engine->scratch.obj = obj;
3035                 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
3036         }
3037
3038         ret = intel_init_ring_buffer(dev, engine);
3039         if (ret)
3040                 return ret;
3041
3042         if (INTEL_GEN(dev_priv) >= 5) {
3043                 ret = intel_init_pipe_control(engine);
3044                 if (ret)
3045                         return ret;
3046         }
3047
3048         return 0;
3049 }
3050
3051 int intel_init_bsd_ring_buffer(struct drm_device *dev)
3052 {
3053         struct drm_i915_private *dev_priv = dev->dev_private;
3054         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
3055
3056         engine->name = "bsd ring";
3057         engine->id = VCS;
3058         engine->exec_id = I915_EXEC_BSD;
3059         engine->hw_id = 1;
3060
3061         intel_ring_default_vfuncs(dev_priv, engine);
3062
3063         if (INTEL_GEN(dev_priv) >= 6) {
3064                 engine->mmio_base = GEN6_BSD_RING_BASE;
3065                 /* gen6 bsd needs a special wa for tail updates */
3066                 if (IS_GEN6(dev_priv))
3067                         engine->write_tail = gen6_bsd_ring_write_tail;
3068                 engine->flush = gen6_bsd_ring_flush;
3069                 if (INTEL_GEN(dev_priv) >= 8) {
3070                         engine->irq_enable_mask =
3071                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
3072                         engine->dispatch_execbuffer =
3073                                 gen8_ring_dispatch_execbuffer;
3074                         if (i915_semaphore_is_enabled(dev_priv)) {
3075                                 engine->semaphore.sync_to = gen8_ring_sync;
3076                                 engine->semaphore.signal = gen8_xcs_signal;
3077                                 GEN8_RING_SEMAPHORE_INIT(engine);
3078                         }
3079                 } else {
3080                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
3081                         engine->dispatch_execbuffer =
3082                                 gen6_ring_dispatch_execbuffer;
3083                         if (i915_semaphore_is_enabled(dev_priv)) {
3084                                 engine->semaphore.sync_to = gen6_ring_sync;
3085                                 engine->semaphore.signal = gen6_signal;
3086                                 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
3087                                 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
3088                                 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
3089                                 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
3090                                 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3091                                 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
3092                                 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
3093                                 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
3094                                 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
3095                                 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3096                         }
3097                 }
3098         } else {
3099                 engine->mmio_base = BSD_RING_BASE;
3100                 engine->flush = bsd_ring_flush;
3101                 if (IS_GEN5(dev_priv)) {
3102                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
3103                 } else {
3104                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
3105                 }
3106                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
3107         }
3108         engine->init_hw = init_ring_common;
3109
3110         return intel_init_ring_buffer(dev, engine);
3111 }
3112
3113 /**
3114  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
3115  */
3116 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
3117 {
3118         struct drm_i915_private *dev_priv = dev->dev_private;
3119         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
3120
3121         engine->name = "bsd2 ring";
3122         engine->id = VCS2;
3123         engine->exec_id = I915_EXEC_BSD;
3124         engine->hw_id = 4;
3125         engine->mmio_base = GEN8_BSD2_RING_BASE;
3126
3127         intel_ring_default_vfuncs(dev_priv, engine);
3128
3129         engine->flush = gen6_bsd_ring_flush;
3130         engine->irq_enable_mask =
3131                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3132         engine->dispatch_execbuffer =
3133                         gen8_ring_dispatch_execbuffer;
3134         if (i915_semaphore_is_enabled(dev_priv)) {
3135                 engine->semaphore.sync_to = gen8_ring_sync;
3136                 engine->semaphore.signal = gen8_xcs_signal;
3137                 GEN8_RING_SEMAPHORE_INIT(engine);
3138         }
3139         engine->init_hw = init_ring_common;
3140
3141         return intel_init_ring_buffer(dev, engine);
3142 }
3143
3144 int intel_init_blt_ring_buffer(struct drm_device *dev)
3145 {
3146         struct drm_i915_private *dev_priv = dev->dev_private;
3147         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3148
3149         engine->name = "blitter ring";
3150         engine->id = BCS;
3151         engine->exec_id = I915_EXEC_BLT;
3152         engine->hw_id = 2;
3153         engine->mmio_base = BLT_RING_BASE;
3154
3155         intel_ring_default_vfuncs(dev_priv, engine);
3156
3157         engine->flush = gen6_ring_flush;
3158         if (INTEL_GEN(dev_priv) >= 8) {
3159                 engine->irq_enable_mask =
3160                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3161                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3162                 if (i915_semaphore_is_enabled(dev_priv)) {
3163                         engine->semaphore.sync_to = gen8_ring_sync;
3164                         engine->semaphore.signal = gen8_xcs_signal;
3165                         GEN8_RING_SEMAPHORE_INIT(engine);
3166                 }
3167         } else {
3168                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3169                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3170                 if (i915_semaphore_is_enabled(dev_priv)) {
3171                         engine->semaphore.signal = gen6_signal;
3172                         engine->semaphore.sync_to = gen6_ring_sync;
3173                         /*
3174                          * The current semaphore is only applied on pre-gen8
3175                          * platform.  And there is no VCS2 ring on the pre-gen8
3176                          * platform. So the semaphore between BCS and VCS2 is
3177                          * initialized as INVALID.  Gen8 will initialize the
3178                          * sema between BCS and VCS2 later.
3179                          */
3180                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3181                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3182                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3183                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3184                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3185                         engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3186                         engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3187                         engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3188                         engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3189                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3190                 }
3191         }
3192         engine->init_hw = init_ring_common;
3193
3194         return intel_init_ring_buffer(dev, engine);
3195 }
3196
3197 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3198 {
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3201
3202         engine->name = "video enhancement ring";
3203         engine->id = VECS;
3204         engine->exec_id = I915_EXEC_VEBOX;
3205         engine->hw_id = 3;
3206         engine->mmio_base = VEBOX_RING_BASE;
3207
3208         intel_ring_default_vfuncs(dev_priv, engine);
3209
3210         engine->flush = gen6_ring_flush;
3211
3212         if (INTEL_GEN(dev_priv) >= 8) {
3213                 engine->irq_enable_mask =
3214                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3215                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3216                 if (i915_semaphore_is_enabled(dev_priv)) {
3217                         engine->semaphore.sync_to = gen8_ring_sync;
3218                         engine->semaphore.signal = gen8_xcs_signal;
3219                         GEN8_RING_SEMAPHORE_INIT(engine);
3220                 }
3221         } else {
3222                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3223                 engine->irq_get = hsw_vebox_get_irq;
3224                 engine->irq_put = hsw_vebox_put_irq;
3225                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3226                 if (i915_semaphore_is_enabled(dev_priv)) {
3227                         engine->semaphore.sync_to = gen6_ring_sync;
3228                         engine->semaphore.signal = gen6_signal;
3229                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3230                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3231                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3232                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3233                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3234                         engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3235                         engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3236                         engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3237                         engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3238                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3239                 }
3240         }
3241         engine->init_hw = init_ring_common;
3242
3243         return intel_init_ring_buffer(dev, engine);
3244 }
3245
3246 int
3247 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3248 {
3249         struct intel_engine_cs *engine = req->engine;
3250         int ret;
3251
3252         if (!engine->gpu_caches_dirty)
3253                 return 0;
3254
3255         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3256         if (ret)
3257                 return ret;
3258
3259         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3260
3261         engine->gpu_caches_dirty = false;
3262         return 0;
3263 }
3264
3265 int
3266 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3267 {
3268         struct intel_engine_cs *engine = req->engine;
3269         uint32_t flush_domains;
3270         int ret;
3271
3272         flush_domains = 0;
3273         if (engine->gpu_caches_dirty)
3274                 flush_domains = I915_GEM_GPU_DOMAINS;
3275
3276         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3277         if (ret)
3278                 return ret;
3279
3280         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3281
3282         engine->gpu_caches_dirty = false;
3283         return 0;
3284 }
3285
3286 void
3287 intel_stop_engine(struct intel_engine_cs *engine)
3288 {
3289         int ret;
3290
3291         if (!intel_engine_initialized(engine))
3292                 return;
3293
3294         ret = intel_engine_idle(engine);
3295         if (ret)
3296                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3297                           engine->name, ret);
3298
3299         stop_ring(engine);
3300 }