drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 int __intel_ring_space(int head, int tail, int size)
  38 {
  39         int space = head - tail;
  40         if (space <= 0)
  41                 space += size;
  42         return space - I915_RING_FREE_SPACE;
  43 }
  44
  45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  46 {
  47         if (ringbuf->last_retired_head != -1) {
  48                 ringbuf->head = ringbuf->last_retired_head;
  49                 ringbuf->last_retired_head = -1;
  50         }
  51
  52         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  53                                             ringbuf->tail, ringbuf->size);
  54 }
  55
  56 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  57 {
  58         intel_ring_update_space(ringbuf);
  59         return ringbuf->space;
  60 }
  61
  62 bool intel_ring_stopped(struct intel_engine_cs *ring)
  63 {
  64         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  65         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  66 }
  67
  68 static void __intel_ring_advance(struct intel_engine_cs *ring)
  69 {
  70         struct intel_ringbuffer *ringbuf = ring->buffer;
  71         ringbuf->tail &= ringbuf->size - 1;
  72         if (intel_ring_stopped(ring))
  73                 return;
  74         ring->write_tail(ring, ringbuf->tail);
  75 }
  76
  77 static int
  78 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  79                        u32      invalidate_domains,
  80                        u32      flush_domains)
  81 {
  82         struct intel_engine_cs *ring = req->ring;
  83         u32 cmd;
  84         int ret;
  85
  86         cmd = MI_FLUSH;
  87         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  88                 cmd |= MI_NO_WRITE_FLUSH;
  89
  90         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  91                 cmd |= MI_READ_FLUSH;
  92
  93         ret = intel_ring_begin(req, 2);
  94         if (ret)
  95                 return ret;
  96
  97         intel_ring_emit(ring, cmd);
  98         intel_ring_emit(ring, MI_NOOP);
  99         intel_ring_advance(ring);
 100
 101         return 0;
 102 }
 103
 104 static int
 105 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 106                        u32      invalidate_domains,
 107                        u32      flush_domains)
 108 {
 109         struct intel_engine_cs *ring = req->ring;
 110         struct drm_device *dev = ring->dev;
 111         u32 cmd;
 112         int ret;
 113
 114         /*
 115          * read/write caches:
 116          *
 117          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 118          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 119          * also flushed at 2d versus 3d pipeline switches.
 120          *
 121          * read-only caches:
 122          *
 123          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 124          * MI_READ_FLUSH is set, and is always flushed on 965.
 125          *
 126          * I915_GEM_DOMAIN_COMMAND may not exist?
 127          *
 128          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 129          * invalidated when MI_EXE_FLUSH is set.
 130          *
 131          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 132          * invalidated with every MI_FLUSH.
 133          *
 134          * TLBs:
 135          *
 136          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 137          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 138          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 139          * are flushed at any MI_FLUSH.
 140          */
 141
 142         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 143         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 144                 cmd &= ~MI_NO_WRITE_FLUSH;
 145         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 146                 cmd |= MI_EXE_FLUSH;
 147
 148         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 149             (IS_G4X(dev) || IS_GEN5(dev)))
 150                 cmd |= MI_INVALIDATE_ISP;
 151
 152         ret = intel_ring_begin(req, 2);
 153         if (ret)
 154                 return ret;
 155
 156         intel_ring_emit(ring, cmd);
 157         intel_ring_emit(ring, MI_NOOP);
 158         intel_ring_advance(ring);
 159
 160         return 0;
 161 }
 162
 163 /**
 164  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 165  * implementing two workarounds on gen6.  From section 1.4.7.1
 166  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 167  *
 168  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 169  * produced by non-pipelined state commands), software needs to first
 170  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 171  * 0.
 172  *
 173  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 174  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 175  *
 176  * And the workaround for these two requires this workaround first:
 177  *
 178  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 179  * BEFORE the pipe-control with a post-sync op and no write-cache
 180  * flushes.
 181  *
 182  * And this last workaround is tricky because of the requirements on
 183  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 184  * volume 2 part 1:
 185  *
 186  *     "1 of the following must also be set:
 187  *      - Render Target Cache Flush Enable ([12] of DW1)
 188  *      - Depth Cache Flush Enable ([0] of DW1)
 189  *      - Stall at Pixel Scoreboard ([1] of DW1)
 190  *      - Depth Stall ([13] of DW1)
 191  *      - Post-Sync Operation ([13] of DW1)
 192  *      - Notify Enable ([8] of DW1)"
 193  *
 194  * The cache flushes require the workaround flush that triggered this
 195  * one, so we can't use it.  Depth stall would trigger the same.
 196  * Post-sync nonzero is what triggered this second workaround, so we
 197  * can't use that one either.  Notify enable is IRQs, which aren't
 198  * really our business.  That leaves only stall at scoreboard.
 199  */
 200 static int
 201 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 202 {
 203         struct intel_engine_cs *ring = req->ring;
 204         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 205         int ret;
 206
 207         ret = intel_ring_begin(req, 6);
 208         if (ret)
 209                 return ret;
 210
 211         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 212         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 213                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 214         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 215         intel_ring_emit(ring, 0); /* low dword */
 216         intel_ring_emit(ring, 0); /* high dword */
 217         intel_ring_emit(ring, MI_NOOP);
 218         intel_ring_advance(ring);
 219
 220         ret = intel_ring_begin(req, 6);
 221         if (ret)
 222                 return ret;
 223
 224         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 225         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 226         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 227         intel_ring_emit(ring, 0);
 228         intel_ring_emit(ring, 0);
 229         intel_ring_emit(ring, MI_NOOP);
 230         intel_ring_advance(ring);
 231
 232         return 0;
 233 }
 234
 235 static int
 236 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 237                        u32 invalidate_domains, u32 flush_domains)
 238 {
 239         struct intel_engine_cs *ring = req->ring;
 240         u32 flags = 0;
 241         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 242         int ret;
 243
 244         /* Force SNB workarounds for PIPE_CONTROL flushes */
 245         ret = intel_emit_post_sync_nonzero_flush(req);
 246         if (ret)
 247                 return ret;
 248
 249         /* Just flush everything.  Experiments have shown that reducing the
 250          * number of bits based on the write domains has little performance
 251          * impact.
 252          */
 253         if (flush_domains) {
 254                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 255                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 256                 /*
 257                  * Ensure that any following seqno writes only happen
 258                  * when the render cache is indeed flushed.
 259                  */
 260                 flags |= PIPE_CONTROL_CS_STALL;
 261         }
 262         if (invalidate_domains) {
 263                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 264                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 265                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 266                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 267                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 268                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 269                 /*
 270                  * TLB invalidate requires a post-sync write.
 271                  */
 272                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 273         }
 274
 275         ret = intel_ring_begin(req, 4);
 276         if (ret)
 277                 return ret;
 278
 279         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 280         intel_ring_emit(ring, flags);
 281         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 282         intel_ring_emit(ring, 0);
 283         intel_ring_advance(ring);
 284
 285         return 0;
 286 }
 287
 288 static int
 289 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 290 {
 291         struct intel_engine_cs *ring = req->ring;
 292         int ret;
 293
 294         ret = intel_ring_begin(req, 4);
 295         if (ret)
 296                 return ret;
 297
 298         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 299         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 300                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 301         intel_ring_emit(ring, 0);
 302         intel_ring_emit(ring, 0);
 303         intel_ring_advance(ring);
 304
 305         return 0;
 306 }
 307
 308 static int
 309 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 310                        u32 invalidate_domains, u32 flush_domains)
 311 {
 312         struct intel_engine_cs *ring = req->ring;
 313         u32 flags = 0;
 314         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 315         int ret;
 316
 317         /*
 318          * Ensure that any following seqno writes only happen when the render
 319          * cache is indeed flushed.
 320          *
 321          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 322          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 323          * don't try to be clever and just set it unconditionally.
 324          */
 325         flags |= PIPE_CONTROL_CS_STALL;
 326
 327         /* Just flush everything.  Experiments have shown that reducing the
 328          * number of bits based on the write domains has little performance
 329          * impact.
 330          */
 331         if (flush_domains) {
 332                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 333                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 334                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 335                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 336         }
 337         if (invalidate_domains) {
 338                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 339                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 340                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 341                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 342                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 343                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 344                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 345                 /*
 346                  * TLB invalidate requires a post-sync write.
 347                  */
 348                 flags |= PIPE_CONTROL_QW_WRITE;
 349                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 350
 351                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 352
 353                 /* Workaround: we must issue a pipe_control with CS-stall bit
 354                  * set before a pipe_control command that has the state cache
 355                  * invalidate bit set. */
 356                 gen7_render_ring_cs_stall_wa(req);
 357         }
 358
 359         ret = intel_ring_begin(req, 4);
 360         if (ret)
 361                 return ret;
 362
 363         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 364         intel_ring_emit(ring, flags);
 365         intel_ring_emit(ring, scratch_addr);
 366         intel_ring_emit(ring, 0);
 367         intel_ring_advance(ring);
 368
 369         return 0;
 370 }
 371
 372 static int
 373 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 374                        u32 flags, u32 scratch_addr)
 375 {
 376         struct intel_engine_cs *ring = req->ring;
 377         int ret;
 378
 379         ret = intel_ring_begin(req, 6);
 380         if (ret)
 381                 return ret;
 382
 383         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 384         intel_ring_emit(ring, flags);
 385         intel_ring_emit(ring, scratch_addr);
 386         intel_ring_emit(ring, 0);
 387         intel_ring_emit(ring, 0);
 388         intel_ring_emit(ring, 0);
 389         intel_ring_advance(ring);
 390
 391         return 0;
 392 }
 393
 394 static int
 395 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 396                        u32 invalidate_domains, u32 flush_domains)
 397 {
 398         u32 flags = 0;
 399         u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 400         int ret;
 401
 402         flags |= PIPE_CONTROL_CS_STALL;
 403
 404         if (flush_domains) {
 405                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 406                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 407                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 408                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 409         }
 410         if (invalidate_domains) {
 411                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 412                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 413                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 414                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 415                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 416                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 417                 flags |= PIPE_CONTROL_QW_WRITE;
 418                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 419
 420                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 421                 ret = gen8_emit_pipe_control(req,
 422                                              PIPE_CONTROL_CS_STALL |
 423                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 424                                              0);
 425                 if (ret)
 426                         return ret;
 427         }
 428
 429         return gen8_emit_pipe_control(req, flags, scratch_addr);
 430 }
 431
 432 static void ring_write_tail(struct intel_engine_cs *ring,
 433                             u32 value)
 434 {
 435         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 436         I915_WRITE_TAIL(ring, value);
 437 }
 438
 439 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 440 {
 441         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 442         u64 acthd;
 443
 444         if (INTEL_INFO(ring->dev)->gen >= 8)
 445                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 446                                          RING_ACTHD_UDW(ring->mmio_base));
 447         else if (INTEL_INFO(ring->dev)->gen >= 4)
 448                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 449         else
 450                 acthd = I915_READ(ACTHD);
 451
 452         return acthd;
 453 }
 454
 455 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 456 {
 457         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 458         u32 addr;
 459
 460         addr = dev_priv->status_page_dmah->busaddr;
 461         if (INTEL_INFO(ring->dev)->gen >= 4)
 462                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 463         I915_WRITE(HWS_PGA, addr);
 464 }
 465
 466 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 467 {
 468         struct drm_device *dev = ring->dev;
 469         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 470         i915_reg_t mmio;
 471
 472         /* The ring status page addresses are no longer next to the rest of
 473          * the ring registers as of gen7.
 474          */
 475         if (IS_GEN7(dev)) {
 476                 switch (ring->id) {
 477                 case RCS:
 478                         mmio = RENDER_HWS_PGA_GEN7;
 479                         break;
 480                 case BCS:
 481                         mmio = BLT_HWS_PGA_GEN7;
 482                         break;
 483                 /*
 484                  * VCS2 actually doesn't exist on Gen7. Only shut up
 485                  * gcc switch check warning
 486                  */
 487                 case VCS2:
 488                 case VCS:
 489                         mmio = BSD_HWS_PGA_GEN7;
 490                         break;
 491                 case VECS:
 492                         mmio = VEBOX_HWS_PGA_GEN7;
 493                         break;
 494                 }
 495         } else if (IS_GEN6(ring->dev)) {
 496                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 497         } else {
 498                 /* XXX: gen8 returns to sanity */
 499                 mmio = RING_HWS_PGA(ring->mmio_base);
 500         }
 501
 502         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 503         POSTING_READ(mmio);
 504
 505         /*
 506          * Flush the TLB for this page
 507          *
 508          * FIXME: These two bits have disappeared on gen8, so a question
 509          * arises: do we still need this and if so how should we go about
 510          * invalidating the TLB?
 511          */
 512         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 513                 i915_reg_t reg = RING_INSTPM(ring->mmio_base);
 514
 515                 /* ring should be idle before issuing a sync flush*/
 516                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 517
 518                 I915_WRITE(reg,
 519                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 520                                               INSTPM_SYNC_FLUSH));
 521                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 522                              1000))
 523                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 524                                   ring->name);
 525         }
 526 }
 527
 528 static bool stop_ring(struct intel_engine_cs *ring)
 529 {
 530         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 531
 532         if (!IS_GEN2(ring->dev)) {
 533                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 534                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 535                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 536                         /* Sometimes we observe that the idle flag is not
 537                          * set even though the ring is empty. So double
 538                          * check before giving up.
 539                          */
 540                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 541                                 return false;
 542                 }
 543         }
 544
 545         I915_WRITE_CTL(ring, 0);
 546         I915_WRITE_HEAD(ring, 0);
 547         ring->write_tail(ring, 0);
 548
 549         if (!IS_GEN2(ring->dev)) {
 550                 (void)I915_READ_CTL(ring);
 551                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 552         }
 553
 554         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 555 }
 556
 557 static int init_ring_common(struct intel_engine_cs *ring)
 558 {
 559         struct drm_device *dev = ring->dev;
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561         struct intel_ringbuffer *ringbuf = ring->buffer;
 562         struct drm_i915_gem_object *obj = ringbuf->obj;
 563         int ret = 0;
 564
 565         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 566
 567         if (!stop_ring(ring)) {
 568                 /* G45 ring initialization often fails to reset head to zero */
 569                 DRM_DEBUG_KMS("%s head not reset to zero "
 570                               "ctl %08x head %08x tail %08x start %08x\n",
 571                               ring->name,
 572                               I915_READ_CTL(ring),
 573                               I915_READ_HEAD(ring),
 574                               I915_READ_TAIL(ring),
 575                               I915_READ_START(ring));
 576
 577                 if (!stop_ring(ring)) {
 578                         DRM_ERROR("failed to set %s head to zero "
 579                                   "ctl %08x head %08x tail %08x start %08x\n",
 580                                   ring->name,
 581                                   I915_READ_CTL(ring),
 582                                   I915_READ_HEAD(ring),
 583                                   I915_READ_TAIL(ring),
 584                                   I915_READ_START(ring));
 585                         ret = -EIO;
 586                         goto out;
 587                 }
 588         }
 589
 590         if (I915_NEED_GFX_HWS(dev))
 591                 intel_ring_setup_status_page(ring);
 592         else
 593                 ring_setup_phys_status_page(ring);
 594
 595         /* Enforce ordering by reading HEAD register back */
 596         I915_READ_HEAD(ring);
 597
 598         /* Initialize the ring. This must happen _after_ we've cleared the ring
 599          * registers with the above sequence (the readback of the HEAD registers
 600          * also enforces ordering), otherwise the hw might lose the new ring
 601          * register values. */
 602         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 603
 604         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 605         if (I915_READ_HEAD(ring))
 606                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 607                           ring->name, I915_READ_HEAD(ring));
 608         I915_WRITE_HEAD(ring, 0);
 609         (void)I915_READ_HEAD(ring);
 610
 611         I915_WRITE_CTL(ring,
 612                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 613                         | RING_VALID);
 614
 615         /* If the head is still not zero, the ring is dead */
 616         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 617                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 618                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 619                 DRM_ERROR("%s initialization failed "
 620                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 621                           ring->name,
 622                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 623                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 624                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 625                 ret = -EIO;
 626                 goto out;
 627         }
 628
 629         ringbuf->last_retired_head = -1;
 630         ringbuf->head = I915_READ_HEAD(ring);
 631         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 632         intel_ring_update_space(ringbuf);
 633
 634         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 635
 636 out:
 637         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 638
 639         return ret;
 640 }
 641
 642 void
 643 intel_fini_pipe_control(struct intel_engine_cs *ring)
 644 {
 645         struct drm_device *dev = ring->dev;
 646
 647         if (ring->scratch.obj == NULL)
 648                 return;
 649
 650         if (INTEL_INFO(dev)->gen >= 5) {
 651                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 652                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 653         }
 654
 655         drm_gem_object_unreference(&ring->scratch.obj->base);
 656         ring->scratch.obj = NULL;
 657 }
 658
 659 int
 660 intel_init_pipe_control(struct intel_engine_cs *ring)
 661 {
 662         int ret;
 663
 664         WARN_ON(ring->scratch.obj);
 665
 666         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 667         if (ring->scratch.obj == NULL) {
 668                 DRM_ERROR("Failed to allocate seqno page\n");
 669                 ret = -ENOMEM;
 670                 goto err;
 671         }
 672
 673         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 674         if (ret)
 675                 goto err_unref;
 676
 677         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 678         if (ret)
 679                 goto err_unref;
 680
 681         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 682         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 683         if (ring->scratch.cpu_page == NULL) {
 684                 ret = -ENOMEM;
 685                 goto err_unpin;
 686         }
 687
 688         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 689                          ring->name, ring->scratch.gtt_offset);
 690         return 0;
 691
 692 err_unpin:
 693         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 694 err_unref:
 695         drm_gem_object_unreference(&ring->scratch.obj->base);
 696 err:
 697         return ret;
 698 }
 699
 700 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 701 {
 702         int ret, i;
 703         struct intel_engine_cs *ring = req->ring;
 704         struct drm_device *dev = ring->dev;
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706         struct i915_workarounds *w = &dev_priv->workarounds;
 707
 708         if (w->count == 0)
 709                 return 0;
 710
 711         ring->gpu_caches_dirty = true;
 712         ret = intel_ring_flush_all_caches(req);
 713         if (ret)
 714                 return ret;
 715
 716         ret = intel_ring_begin(req, (w->count * 2 + 2));
 717         if (ret)
 718                 return ret;
 719
 720         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 721         for (i = 0; i < w->count; i++) {
 722                 intel_ring_emit_reg(ring, w->reg[i].addr);
 723                 intel_ring_emit(ring, w->reg[i].value);
 724         }
 725         intel_ring_emit(ring, MI_NOOP);
 726
 727         intel_ring_advance(ring);
 728
 729         ring->gpu_caches_dirty = true;
 730         ret = intel_ring_flush_all_caches(req);
 731         if (ret)
 732                 return ret;
 733
 734         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 735
 736         return 0;
 737 }
 738
 739 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 740 {
 741         int ret;
 742
 743         ret = intel_ring_workarounds_emit(req);
 744         if (ret != 0)
 745                 return ret;
 746
 747         ret = i915_gem_render_state_init(req);
 748         if (ret)
 749                 DRM_ERROR("init render state: %d\n", ret);
 750
 751         return ret;
 752 }
 753
 754 static int wa_add(struct drm_i915_private *dev_priv,
 755                   i915_reg_t addr,
 756                   const u32 mask, const u32 val)
 757 {
 758         const u32 idx = dev_priv->workarounds.count;
 759
 760         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 761                 return -ENOSPC;
 762
 763         dev_priv->workarounds.reg[idx].addr = addr;
 764         dev_priv->workarounds.reg[idx].value = val;
 765         dev_priv->workarounds.reg[idx].mask = mask;
 766
 767         dev_priv->workarounds.count++;
 768
 769         return 0;
 770 }
 771
 772 #define WA_REG(addr, mask, val) do { \
 773                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 774                 if (r) \
 775                         return r; \
 776         } while (0)
 777
 778 #define WA_SET_BIT_MASKED(addr, mask) \
 779         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 780
 781 #define WA_CLR_BIT_MASKED(addr, mask) \
 782         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 783
 784 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 785         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 786
 787 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 788 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 789
 790 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 791
 792 static int wa_ring_whitelist_reg(struct intel_engine_cs *ring, i915_reg_t reg)
 793 {
 794         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 795         struct i915_workarounds *wa = &dev_priv->workarounds;
 796         const uint32_t index = wa->hw_whitelist_count[ring->id];
 797
 798         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 799                 return -EINVAL;
 800
 801         WA_WRITE(RING_FORCE_TO_NONPRIV(ring->mmio_base, index),
 802                  i915_mmio_reg_offset(reg));
 803         wa->hw_whitelist_count[ring->id]++;
 804
 805         return 0;
 806 }
 807
 808 static int gen8_init_workarounds(struct intel_engine_cs *ring)
 809 {
 810         struct drm_device *dev = ring->dev;
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812
 813         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 814
 815         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 816         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 817
 818         /* WaDisablePartialInstShootdown:bdw,chv */
 819         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 820                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 821
 822         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 823          * workaround for for a possible hang in the unlikely event a TLB
 824          * invalidation occurs during a PSD flush.
 825          */
 826         /* WaForceEnableNonCoherent:bdw,chv */
 827         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 828         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 829                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 830                           HDC_FORCE_NON_COHERENT);
 831
 832         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 833          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 834          *  polygons in the same 8x4 pixel/sample area to be processed without
 835          *  stalling waiting for the earlier ones to write to Hierarchical Z
 836          *  buffer."
 837          *
 838          * This optimization is off by default for BDW and CHV; turn it on.
 839          */
 840         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 841
 842         /* Wa4x4STCOptimizationDisable:bdw,chv */
 843         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 844
 845         /*
 846          * BSpec recommends 8x4 when MSAA is used,
 847          * however in practice 16x4 seems fastest.
 848          *
 849          * Note that PS/WM thread counts depend on the WIZ hashing
 850          * disable bit, which we don't touch here, but it's good
 851          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 852          */
 853         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 854                             GEN6_WIZ_HASHING_MASK,
 855                             GEN6_WIZ_HASHING_16x4);
 856
 857         return 0;
 858 }
 859
 860 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 861 {
 862         int ret;
 863         struct drm_device *dev = ring->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865
 866         ret = gen8_init_workarounds(ring);
 867         if (ret)
 868                 return ret;
 869
 870         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 871         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 872
 873         /* WaDisableDopClockGating:bdw */
 874         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 875                           DOP_CLOCK_GATING_DISABLE);
 876
 877         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 878                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 879
 880         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 881                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 882                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 883                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 884                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 885
 886         return 0;
 887 }
 888
 889 static int chv_init_workarounds(struct intel_engine_cs *ring)
 890 {
 891         int ret;
 892         struct drm_device *dev = ring->dev;
 893         struct drm_i915_private *dev_priv = dev->dev_private;
 894
 895         ret = gen8_init_workarounds(ring);
 896         if (ret)
 897                 return ret;
 898
 899         /* WaDisableThreadStallDopClockGating:chv */
 900         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 901
 902         /* Improve HiZ throughput on CHV. */
 903         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 904
 905         return 0;
 906 }
 907
 908 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 909 {
 910         struct drm_device *dev = ring->dev;
 911         struct drm_i915_private *dev_priv = dev->dev_private;
 912         uint32_t tmp;
 913         int ret;
 914
 915         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 916         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 917                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 918
 919         /* WaDisableKillLogic:bxt,skl */
 920         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 921                    ECOCHK_DIS_TLB);
 922
 923         /* WaDisablePartialInstShootdown:skl,bxt */
 924         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 925                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 926
 927         /* Syncing dependencies between camera and graphics:skl,bxt */
 928         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 929                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 930
 931         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 932         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 933             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 934                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 935                                   GEN9_DG_MIRROR_FIX_ENABLE);
 936
 937         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 938         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 939             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 940                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 941                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 942                 /*
 943                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 944                  * but we do that in per ctx batchbuffer as there is an issue
 945                  * with this register not getting restored on ctx restore
 946                  */
 947         }
 948
 949         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 950         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
 951                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 952                                   GEN9_ENABLE_YV12_BUGFIX);
 953
 954         /* Wa4x4STCOptimizationDisable:skl,bxt */
 955         /* WaDisablePartialResolveInVc:skl,bxt */
 956         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 957                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 958
 959         /* WaCcsTlbPrefetchDisable:skl,bxt */
 960         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 961                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 962
 963         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 964         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 965             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 966                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 967                                   PIXEL_MASK_CAMMING_DISABLE);
 968
 969         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 970         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 971         if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
 972             IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
 973                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 974         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 975
 976         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 977         if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 978                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 979                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 980
 981         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 982         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 983
 984         /* WaOCLCoherentLineFlush:skl,bxt */
 985         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 986                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
 987
 988         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
 989         ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1);
 990         if (ret)
 991                 return ret;
 992
 993         /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
 994         ret = wa_ring_whitelist_reg(ring, GEN8_HDC_CHICKEN1);
 995         if (ret)
 996                 return ret;
 997
 998         return 0;
 999 }
1000
1001 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
1002 {
1003         struct drm_device *dev = ring->dev;
1004         struct drm_i915_private *dev_priv = dev->dev_private;
1005         u8 vals[3] = { 0, 0, 0 };
1006         unsigned int i;
1007
1008         for (i = 0; i < 3; i++) {
1009                 u8 ss;
1010
1011                 /*
1012                  * Only consider slices where one, and only one, subslice has 7
1013                  * EUs
1014                  */
1015                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1016                         continue;
1017
1018                 /*
1019                  * subslice_7eu[i] != 0 (because of the check above) and
1020                  * ss_max == 4 (maximum number of subslices possible per slice)
1021                  *
1022                  * ->    0 <= ss <= 3;
1023                  */
1024                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1025                 vals[i] = 3 - ss;
1026         }
1027
1028         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1029                 return 0;
1030
1031         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1032         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1033                             GEN9_IZ_HASHING_MASK(2) |
1034                             GEN9_IZ_HASHING_MASK(1) |
1035                             GEN9_IZ_HASHING_MASK(0),
1036                             GEN9_IZ_HASHING(2, vals[2]) |
1037                             GEN9_IZ_HASHING(1, vals[1]) |
1038                             GEN9_IZ_HASHING(0, vals[0]));
1039
1040         return 0;
1041 }
1042
1043 static int skl_init_workarounds(struct intel_engine_cs *ring)
1044 {
1045         int ret;
1046         struct drm_device *dev = ring->dev;
1047         struct drm_i915_private *dev_priv = dev->dev_private;
1048
1049         ret = gen9_init_workarounds(ring);
1050         if (ret)
1051                 return ret;
1052
1053         /*
1054          * Actual WA is to disable percontext preemption granularity control
1055          * until D0 which is the default case so this is equivalent to
1056          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1057          */
1058         if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1059                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1060                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1061         }
1062
1063         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1064                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1065                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1066                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1067         }
1068
1069         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1070          * involving this register should also be added to WA batch as required.
1071          */
1072         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1073                 /* WaDisableLSQCROPERFforOCL:skl */
1074                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1075                            GEN8_LQSC_RO_PERF_DIS);
1076
1077         /* WaEnableGapsTsvCreditFix:skl */
1078         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1079                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1080                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1081         }
1082
1083         /* WaDisablePowerCompilerClockGating:skl */
1084         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1085                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1086                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1087
1088         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
1089                 /*
1090                  *Use Force Non-Coherent whenever executing a 3D context. This
1091                  * is a workaround for a possible hang in the unlikely event
1092                  * a TLB invalidation occurs during a PSD flush.
1093                  */
1094                 /* WaForceEnableNonCoherent:skl */
1095                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1096                                   HDC_FORCE_NON_COHERENT);
1097
1098                 /* WaDisableHDCInvalidation:skl */
1099                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1100                            BDW_DISABLE_HDC_INVALIDATION);
1101         }
1102
1103         /* WaBarrierPerformanceFixDisable:skl */
1104         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1105                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1106                                   HDC_FENCE_DEST_SLM_DISABLE |
1107                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1108
1109         /* WaDisableSbeCacheDispatchPortSharing:skl */
1110         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1111                 WA_SET_BIT_MASKED(
1112                         GEN7_HALF_SLICE_CHICKEN1,
1113                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1114
1115         /* WaDisableLSQCROPERFforOCL:skl */
1116         ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
1117         if (ret)
1118                 return ret;
1119
1120         return skl_tune_iz_hashing(ring);
1121 }
1122
1123 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1124 {
1125         int ret;
1126         struct drm_device *dev = ring->dev;
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129         ret = gen9_init_workarounds(ring);
1130         if (ret)
1131                 return ret;
1132
1133         /* WaStoreMultiplePTEenable:bxt */
1134         /* This is a requirement according to Hardware specification */
1135         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1136                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1137
1138         /* WaSetClckGatingDisableMedia:bxt */
1139         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1140                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1141                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1142         }
1143
1144         /* WaDisableThreadStallDopClockGating:bxt */
1145         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1146                           STALL_DOP_GATING_DISABLE);
1147
1148         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1149         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1150                 WA_SET_BIT_MASKED(
1151                         GEN7_HALF_SLICE_CHICKEN1,
1152                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1153         }
1154
1155         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1156         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1157         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1158         /* WaDisableLSQCROPERFforOCL:bxt */
1159         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1160                 ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1);
1161                 if (ret)
1162                         return ret;
1163
1164                 ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
1165                 if (ret)
1166                         return ret;
1167         }
1168
1169         return 0;
1170 }
1171
1172 int init_workarounds_ring(struct intel_engine_cs *ring)
1173 {
1174         struct drm_device *dev = ring->dev;
1175         struct drm_i915_private *dev_priv = dev->dev_private;
1176
1177         WARN_ON(ring->id != RCS);
1178
1179         dev_priv->workarounds.count = 0;
1180         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1181
1182         if (IS_BROADWELL(dev))
1183                 return bdw_init_workarounds(ring);
1184
1185         if (IS_CHERRYVIEW(dev))
1186                 return chv_init_workarounds(ring);
1187
1188         if (IS_SKYLAKE(dev))
1189                 return skl_init_workarounds(ring);
1190
1191         if (IS_BROXTON(dev))
1192                 return bxt_init_workarounds(ring);
1193
1194         return 0;
1195 }
1196
1197 static int init_render_ring(struct intel_engine_cs *ring)
1198 {
1199         struct drm_device *dev = ring->dev;
1200         struct drm_i915_private *dev_priv = dev->dev_private;
1201         int ret = init_ring_common(ring);
1202         if (ret)
1203                 return ret;
1204
1205         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1206         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1207                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1208
1209         /* We need to disable the AsyncFlip performance optimisations in order
1210          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1211          * programmed to '1' on all products.
1212          *
1213          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1214          */
1215         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1216                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1217
1218         /* Required for the hardware to program scanline values for waiting */
1219         /* WaEnableFlushTlbInvalidationMode:snb */
1220         if (INTEL_INFO(dev)->gen == 6)
1221                 I915_WRITE(GFX_MODE,
1222                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1223
1224         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1225         if (IS_GEN7(dev))
1226                 I915_WRITE(GFX_MODE_GEN7,
1227                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1228                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1229
1230         if (IS_GEN6(dev)) {
1231                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1232                  * "If this bit is set, STCunit will have LRA as replacement
1233                  *  policy. [...] This bit must be reset.  LRA replacement
1234                  *  policy is not supported."
1235                  */
1236                 I915_WRITE(CACHE_MODE_0,
1237                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1238         }
1239
1240         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1241                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1242
1243         if (HAS_L3_DPF(dev))
1244                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1245
1246         return init_workarounds_ring(ring);
1247 }
1248
1249 static void render_ring_cleanup(struct intel_engine_cs *ring)
1250 {
1251         struct drm_device *dev = ring->dev;
1252         struct drm_i915_private *dev_priv = dev->dev_private;
1253
1254         if (dev_priv->semaphore_obj) {
1255                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1256                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1257                 dev_priv->semaphore_obj = NULL;
1258         }
1259
1260         intel_fini_pipe_control(ring);
1261 }
1262
1263 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1264                            unsigned int num_dwords)
1265 {
1266 #define MBOX_UPDATE_DWORDS 8
1267         struct intel_engine_cs *signaller = signaller_req->ring;
1268         struct drm_device *dev = signaller->dev;
1269         struct drm_i915_private *dev_priv = dev->dev_private;
1270         struct intel_engine_cs *waiter;
1271         int i, ret, num_rings;
1272
1273         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1274         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1275 #undef MBOX_UPDATE_DWORDS
1276
1277         ret = intel_ring_begin(signaller_req, num_dwords);
1278         if (ret)
1279                 return ret;
1280
1281         for_each_ring(waiter, dev_priv, i) {
1282                 u32 seqno;
1283                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1284                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1285                         continue;
1286
1287                 seqno = i915_gem_request_get_seqno(signaller_req);
1288                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1289                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1290                                            PIPE_CONTROL_QW_WRITE |
1291                                            PIPE_CONTROL_FLUSH_ENABLE);
1292                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1293                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1294                 intel_ring_emit(signaller, seqno);
1295                 intel_ring_emit(signaller, 0);
1296                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1297                                            MI_SEMAPHORE_TARGET(waiter->id));
1298                 intel_ring_emit(signaller, 0);
1299         }
1300
1301         return 0;
1302 }
1303
1304 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1305                            unsigned int num_dwords)
1306 {
1307 #define MBOX_UPDATE_DWORDS 6
1308         struct intel_engine_cs *signaller = signaller_req->ring;
1309         struct drm_device *dev = signaller->dev;
1310         struct drm_i915_private *dev_priv = dev->dev_private;
1311         struct intel_engine_cs *waiter;
1312         int i, ret, num_rings;
1313
1314         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1315         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1316 #undef MBOX_UPDATE_DWORDS
1317
1318         ret = intel_ring_begin(signaller_req, num_dwords);
1319         if (ret)
1320                 return ret;
1321
1322         for_each_ring(waiter, dev_priv, i) {
1323                 u32 seqno;
1324                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1325                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1326                         continue;
1327
1328                 seqno = i915_gem_request_get_seqno(signaller_req);
1329                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1330                                            MI_FLUSH_DW_OP_STOREDW);
1331                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1332                                            MI_FLUSH_DW_USE_GTT);
1333                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1334                 intel_ring_emit(signaller, seqno);
1335                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1336                                            MI_SEMAPHORE_TARGET(waiter->id));
1337                 intel_ring_emit(signaller, 0);
1338         }
1339
1340         return 0;
1341 }
1342
1343 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1344                        unsigned int num_dwords)
1345 {
1346         struct intel_engine_cs *signaller = signaller_req->ring;
1347         struct drm_device *dev = signaller->dev;
1348         struct drm_i915_private *dev_priv = dev->dev_private;
1349         struct intel_engine_cs *useless;
1350         int i, ret, num_rings;
1351
1352 #define MBOX_UPDATE_DWORDS 3
1353         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1354         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1355 #undef MBOX_UPDATE_DWORDS
1356
1357         ret = intel_ring_begin(signaller_req, num_dwords);
1358         if (ret)
1359                 return ret;
1360
1361         for_each_ring(useless, dev_priv, i) {
1362                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
1363
1364                 if (i915_mmio_reg_valid(mbox_reg)) {
1365                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1366
1367                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1368                         intel_ring_emit_reg(signaller, mbox_reg);
1369                         intel_ring_emit(signaller, seqno);
1370                 }
1371         }
1372
1373         /* If num_dwords was rounded, make sure the tail pointer is correct */
1374         if (num_rings % 2 == 0)
1375                 intel_ring_emit(signaller, MI_NOOP);
1376
1377         return 0;
1378 }
1379
1380 /**
1381  * gen6_add_request - Update the semaphore mailbox registers
1382  *
1383  * @request - request to write to the ring
1384  *
1385  * Update the mailbox registers in the *other* rings with the current seqno.
1386  * This acts like a signal in the canonical semaphore.
1387  */
1388 static int
1389 gen6_add_request(struct drm_i915_gem_request *req)
1390 {
1391         struct intel_engine_cs *ring = req->ring;
1392         int ret;
1393
1394         if (ring->semaphore.signal)
1395                 ret = ring->semaphore.signal(req, 4);
1396         else
1397                 ret = intel_ring_begin(req, 4);
1398
1399         if (ret)
1400                 return ret;
1401
1402         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1403         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1404         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1405         intel_ring_emit(ring, MI_USER_INTERRUPT);
1406         __intel_ring_advance(ring);
1407
1408         return 0;
1409 }
1410
1411 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1412                                               u32 seqno)
1413 {
1414         struct drm_i915_private *dev_priv = dev->dev_private;
1415         return dev_priv->last_seqno < seqno;
1416 }
1417
1418 /**
1419  * intel_ring_sync - sync the waiter to the signaller on seqno
1420  *
1421  * @waiter - ring that is waiting
1422  * @signaller - ring which has, or will signal
1423  * @seqno - seqno which the waiter will block on
1424  */
1425
1426 static int
1427 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1428                struct intel_engine_cs *signaller,
1429                u32 seqno)
1430 {
1431         struct intel_engine_cs *waiter = waiter_req->ring;
1432         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1433         int ret;
1434
1435         ret = intel_ring_begin(waiter_req, 4);
1436         if (ret)
1437                 return ret;
1438
1439         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1440                                 MI_SEMAPHORE_GLOBAL_GTT |
1441                                 MI_SEMAPHORE_POLL |
1442                                 MI_SEMAPHORE_SAD_GTE_SDD);
1443         intel_ring_emit(waiter, seqno);
1444         intel_ring_emit(waiter,
1445                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1446         intel_ring_emit(waiter,
1447                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1448         intel_ring_advance(waiter);
1449         return 0;
1450 }
1451
1452 static int
1453 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1454                struct intel_engine_cs *signaller,
1455                u32 seqno)
1456 {
1457         struct intel_engine_cs *waiter = waiter_req->ring;
1458         u32 dw1 = MI_SEMAPHORE_MBOX |
1459                   MI_SEMAPHORE_COMPARE |
1460                   MI_SEMAPHORE_REGISTER;
1461         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1462         int ret;
1463
1464         /* Throughout all of the GEM code, seqno passed implies our current
1465          * seqno is >= the last seqno executed. However for hardware the
1466          * comparison is strictly greater than.
1467          */
1468         seqno -= 1;
1469
1470         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1471
1472         ret = intel_ring_begin(waiter_req, 4);
1473         if (ret)
1474                 return ret;
1475
1476         /* If seqno wrap happened, omit the wait with no-ops */
1477         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1478                 intel_ring_emit(waiter, dw1 | wait_mbox);
1479                 intel_ring_emit(waiter, seqno);
1480                 intel_ring_emit(waiter, 0);
1481                 intel_ring_emit(waiter, MI_NOOP);
1482         } else {
1483                 intel_ring_emit(waiter, MI_NOOP);
1484                 intel_ring_emit(waiter, MI_NOOP);
1485                 intel_ring_emit(waiter, MI_NOOP);
1486                 intel_ring_emit(waiter, MI_NOOP);
1487         }
1488         intel_ring_advance(waiter);
1489
1490         return 0;
1491 }
1492
1493 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1494 do {                                                                    \
1495         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1496                  PIPE_CONTROL_DEPTH_STALL);                             \
1497         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1498         intel_ring_emit(ring__, 0);                                                     \
1499         intel_ring_emit(ring__, 0);                                                     \
1500 } while (0)
1501
1502 static int
1503 pc_render_add_request(struct drm_i915_gem_request *req)
1504 {
1505         struct intel_engine_cs *ring = req->ring;
1506         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1507         int ret;
1508
1509         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1510          * incoherent with writes to memory, i.e. completely fubar,
1511          * so we need to use PIPE_NOTIFY instead.
1512          *
1513          * However, we also need to workaround the qword write
1514          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1515          * memory before requesting an interrupt.
1516          */
1517         ret = intel_ring_begin(req, 32);
1518         if (ret)
1519                 return ret;
1520
1521         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1522                         PIPE_CONTROL_WRITE_FLUSH |
1523                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1524         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1525         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1526         intel_ring_emit(ring, 0);
1527         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1528         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1529         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1530         scratch_addr += 2 * CACHELINE_BYTES;
1531         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1532         scratch_addr += 2 * CACHELINE_BYTES;
1533         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1534         scratch_addr += 2 * CACHELINE_BYTES;
1535         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1536         scratch_addr += 2 * CACHELINE_BYTES;
1537         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1538
1539         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1540                         PIPE_CONTROL_WRITE_FLUSH |
1541                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1542                         PIPE_CONTROL_NOTIFY);
1543         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1544         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1545         intel_ring_emit(ring, 0);
1546         __intel_ring_advance(ring);
1547
1548         return 0;
1549 }
1550
1551 static u32
1552 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1553 {
1554         /* Workaround to force correct ordering between irq and seqno writes on
1555          * ivb (and maybe also on snb) by reading from a CS register (like
1556          * ACTHD) before reading the status page. */
1557         if (!lazy_coherency) {
1558                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1559                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1560         }
1561
1562         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1563 }
1564
1565 static u32
1566 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1567 {
1568         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1569 }
1570
1571 static void
1572 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1573 {
1574         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1575 }
1576
1577 static u32
1578 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1579 {
1580         return ring->scratch.cpu_page[0];
1581 }
1582
1583 static void
1584 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1585 {
1586         ring->scratch.cpu_page[0] = seqno;
1587 }
1588
1589 static bool
1590 gen5_ring_get_irq(struct intel_engine_cs *ring)
1591 {
1592         struct drm_device *dev = ring->dev;
1593         struct drm_i915_private *dev_priv = dev->dev_private;
1594         unsigned long flags;
1595
1596         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1597                 return false;
1598
1599         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1600         if (ring->irq_refcount++ == 0)
1601                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1602         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1603
1604         return true;
1605 }
1606
1607 static void
1608 gen5_ring_put_irq(struct intel_engine_cs *ring)
1609 {
1610         struct drm_device *dev = ring->dev;
1611         struct drm_i915_private *dev_priv = dev->dev_private;
1612         unsigned long flags;
1613
1614         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1615         if (--ring->irq_refcount == 0)
1616                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1617         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1618 }
1619
1620 static bool
1621 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1622 {
1623         struct drm_device *dev = ring->dev;
1624         struct drm_i915_private *dev_priv = dev->dev_private;
1625         unsigned long flags;
1626
1627         if (!intel_irqs_enabled(dev_priv))
1628                 return false;
1629
1630         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1631         if (ring->irq_refcount++ == 0) {
1632                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1633                 I915_WRITE(IMR, dev_priv->irq_mask);
1634                 POSTING_READ(IMR);
1635         }
1636         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1637
1638         return true;
1639 }
1640
1641 static void
1642 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1643 {
1644         struct drm_device *dev = ring->dev;
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646         unsigned long flags;
1647
1648         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1649         if (--ring->irq_refcount == 0) {
1650                 dev_priv->irq_mask |= ring->irq_enable_mask;
1651                 I915_WRITE(IMR, dev_priv->irq_mask);
1652                 POSTING_READ(IMR);
1653         }
1654         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1655 }
1656
1657 static bool
1658 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1659 {
1660         struct drm_device *dev = ring->dev;
1661         struct drm_i915_private *dev_priv = dev->dev_private;
1662         unsigned long flags;
1663
1664         if (!intel_irqs_enabled(dev_priv))
1665                 return false;
1666
1667         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1668         if (ring->irq_refcount++ == 0) {
1669                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1670                 I915_WRITE16(IMR, dev_priv->irq_mask);
1671                 POSTING_READ16(IMR);
1672         }
1673         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1674
1675         return true;
1676 }
1677
1678 static void
1679 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1680 {
1681         struct drm_device *dev = ring->dev;
1682         struct drm_i915_private *dev_priv = dev->dev_private;
1683         unsigned long flags;
1684
1685         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1686         if (--ring->irq_refcount == 0) {
1687                 dev_priv->irq_mask |= ring->irq_enable_mask;
1688                 I915_WRITE16(IMR, dev_priv->irq_mask);
1689                 POSTING_READ16(IMR);
1690         }
1691         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1692 }
1693
1694 static int
1695 bsd_ring_flush(struct drm_i915_gem_request *req,
1696                u32     invalidate_domains,
1697                u32     flush_domains)
1698 {
1699         struct intel_engine_cs *ring = req->ring;
1700         int ret;
1701
1702         ret = intel_ring_begin(req, 2);
1703         if (ret)
1704                 return ret;
1705
1706         intel_ring_emit(ring, MI_FLUSH);
1707         intel_ring_emit(ring, MI_NOOP);
1708         intel_ring_advance(ring);
1709         return 0;
1710 }
1711
1712 static int
1713 i9xx_add_request(struct drm_i915_gem_request *req)
1714 {
1715         struct intel_engine_cs *ring = req->ring;
1716         int ret;
1717
1718         ret = intel_ring_begin(req, 4);
1719         if (ret)
1720                 return ret;
1721
1722         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1723         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1724         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1725         intel_ring_emit(ring, MI_USER_INTERRUPT);
1726         __intel_ring_advance(ring);
1727
1728         return 0;
1729 }
1730
1731 static bool
1732 gen6_ring_get_irq(struct intel_engine_cs *ring)
1733 {
1734         struct drm_device *dev = ring->dev;
1735         struct drm_i915_private *dev_priv = dev->dev_private;
1736         unsigned long flags;
1737
1738         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1739                 return false;
1740
1741         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1742         if (ring->irq_refcount++ == 0) {
1743                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1744                         I915_WRITE_IMR(ring,
1745                                        ~(ring->irq_enable_mask |
1746                                          GT_PARITY_ERROR(dev)));
1747                 else
1748                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1749                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1750         }
1751         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1752
1753         return true;
1754 }
1755
1756 static void
1757 gen6_ring_put_irq(struct intel_engine_cs *ring)
1758 {
1759         struct drm_device *dev = ring->dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         unsigned long flags;
1762
1763         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1764         if (--ring->irq_refcount == 0) {
1765                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1766                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1767                 else
1768                         I915_WRITE_IMR(ring, ~0);
1769                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1770         }
1771         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1772 }
1773
1774 static bool
1775 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1776 {
1777         struct drm_device *dev = ring->dev;
1778         struct drm_i915_private *dev_priv = dev->dev_private;
1779         unsigned long flags;
1780
1781         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1782                 return false;
1783
1784         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1785         if (ring->irq_refcount++ == 0) {
1786                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1787                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1788         }
1789         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1790
1791         return true;
1792 }
1793
1794 static void
1795 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1796 {
1797         struct drm_device *dev = ring->dev;
1798         struct drm_i915_private *dev_priv = dev->dev_private;
1799         unsigned long flags;
1800
1801         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1802         if (--ring->irq_refcount == 0) {
1803                 I915_WRITE_IMR(ring, ~0);
1804                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1805         }
1806         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1807 }
1808
1809 static bool
1810 gen8_ring_get_irq(struct intel_engine_cs *ring)
1811 {
1812         struct drm_device *dev = ring->dev;
1813         struct drm_i915_private *dev_priv = dev->dev_private;
1814         unsigned long flags;
1815
1816         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1817                 return false;
1818
1819         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1820         if (ring->irq_refcount++ == 0) {
1821                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1822                         I915_WRITE_IMR(ring,
1823                                        ~(ring->irq_enable_mask |
1824                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1825                 } else {
1826                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1827                 }
1828                 POSTING_READ(RING_IMR(ring->mmio_base));
1829         }
1830         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1831
1832         return true;
1833 }
1834
1835 static void
1836 gen8_ring_put_irq(struct intel_engine_cs *ring)
1837 {
1838         struct drm_device *dev = ring->dev;
1839         struct drm_i915_private *dev_priv = dev->dev_private;
1840         unsigned long flags;
1841
1842         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1843         if (--ring->irq_refcount == 0) {
1844                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1845                         I915_WRITE_IMR(ring,
1846                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1847                 } else {
1848                         I915_WRITE_IMR(ring, ~0);
1849                 }
1850                 POSTING_READ(RING_IMR(ring->mmio_base));
1851         }
1852         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1853 }
1854
1855 static int
1856 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1857                          u64 offset, u32 length,
1858                          unsigned dispatch_flags)
1859 {
1860         struct intel_engine_cs *ring = req->ring;
1861         int ret;
1862
1863         ret = intel_ring_begin(req, 2);
1864         if (ret)
1865                 return ret;
1866
1867         intel_ring_emit(ring,
1868                         MI_BATCH_BUFFER_START |
1869                         MI_BATCH_GTT |
1870                         (dispatch_flags & I915_DISPATCH_SECURE ?
1871                          0 : MI_BATCH_NON_SECURE_I965));
1872         intel_ring_emit(ring, offset);
1873         intel_ring_advance(ring);
1874
1875         return 0;
1876 }
1877
1878 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1879 #define I830_BATCH_LIMIT (256*1024)
1880 #define I830_TLB_ENTRIES (2)
1881 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1882 static int
1883 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1884                          u64 offset, u32 len,
1885                          unsigned dispatch_flags)
1886 {
1887         struct intel_engine_cs *ring = req->ring;
1888         u32 cs_offset = ring->scratch.gtt_offset;
1889         int ret;
1890
1891         ret = intel_ring_begin(req, 6);
1892         if (ret)
1893                 return ret;
1894
1895         /* Evict the invalid PTE TLBs */
1896         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1897         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1898         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1899         intel_ring_emit(ring, cs_offset);
1900         intel_ring_emit(ring, 0xdeadbeef);
1901         intel_ring_emit(ring, MI_NOOP);
1902         intel_ring_advance(ring);
1903
1904         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1905                 if (len > I830_BATCH_LIMIT)
1906                         return -ENOSPC;
1907
1908                 ret = intel_ring_begin(req, 6 + 2);
1909                 if (ret)
1910                         return ret;
1911
1912                 /* Blit the batch (which has now all relocs applied) to the
1913                  * stable batch scratch bo area (so that the CS never
1914                  * stumbles over its tlb invalidation bug) ...
1915                  */
1916                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1917                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1918                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1919                 intel_ring_emit(ring, cs_offset);
1920                 intel_ring_emit(ring, 4096);
1921                 intel_ring_emit(ring, offset);
1922
1923                 intel_ring_emit(ring, MI_FLUSH);
1924                 intel_ring_emit(ring, MI_NOOP);
1925                 intel_ring_advance(ring);
1926
1927                 /* ... and execute it. */
1928                 offset = cs_offset;
1929         }
1930
1931         ret = intel_ring_begin(req, 2);
1932         if (ret)
1933                 return ret;
1934
1935         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1936         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1937                                         0 : MI_BATCH_NON_SECURE));
1938         intel_ring_advance(ring);
1939
1940         return 0;
1941 }
1942
1943 static int
1944 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1945                          u64 offset, u32 len,
1946                          unsigned dispatch_flags)
1947 {
1948         struct intel_engine_cs *ring = req->ring;
1949         int ret;
1950
1951         ret = intel_ring_begin(req, 2);
1952         if (ret)
1953                 return ret;
1954
1955         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1956         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1957                                         0 : MI_BATCH_NON_SECURE));
1958         intel_ring_advance(ring);
1959
1960         return 0;
1961 }
1962
1963 static void cleanup_phys_status_page(struct intel_engine_cs *ring)
1964 {
1965         struct drm_i915_private *dev_priv = to_i915(ring->dev);
1966
1967         if (!dev_priv->status_page_dmah)
1968                 return;
1969
1970         drm_pci_free(ring->dev, dev_priv->status_page_dmah);
1971         ring->status_page.page_addr = NULL;
1972 }
1973
1974 static void cleanup_status_page(struct intel_engine_cs *ring)
1975 {
1976         struct drm_i915_gem_object *obj;
1977
1978         obj = ring->status_page.obj;
1979         if (obj == NULL)
1980                 return;
1981
1982         kunmap(sg_page(obj->pages->sgl));
1983         i915_gem_object_ggtt_unpin(obj);
1984         drm_gem_object_unreference(&obj->base);
1985         ring->status_page.obj = NULL;
1986 }
1987
1988 static int init_status_page(struct intel_engine_cs *ring)
1989 {
1990         struct drm_i915_gem_object *obj = ring->status_page.obj;
1991
1992         if (obj == NULL) {
1993                 unsigned flags;
1994                 int ret;
1995
1996                 obj = i915_gem_alloc_object(ring->dev, 4096);
1997                 if (obj == NULL) {
1998                         DRM_ERROR("Failed to allocate status page\n");
1999                         return -ENOMEM;
2000                 }
2001
2002                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2003                 if (ret)
2004                         goto err_unref;
2005
2006                 flags = 0;
2007                 if (!HAS_LLC(ring->dev))
2008                         /* On g33, we cannot place HWS above 256MiB, so
2009                          * restrict its pinning to the low mappable arena.
2010                          * Though this restriction is not documented for
2011                          * gen4, gen5, or byt, they also behave similarly
2012                          * and hang if the HWS is placed at the top of the
2013                          * GTT. To generalise, it appears that all !llc
2014                          * platforms have issues with us placing the HWS
2015                          * above the mappable region (even though we never
2016                          * actualy map it).
2017                          */
2018                         flags |= PIN_MAPPABLE;
2019                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2020                 if (ret) {
2021 err_unref:
2022                         drm_gem_object_unreference(&obj->base);
2023                         return ret;
2024                 }
2025
2026                 ring->status_page.obj = obj;
2027         }
2028
2029         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2030         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2031         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
2032
2033         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2034                         ring->name, ring->status_page.gfx_addr);
2035
2036         return 0;
2037 }
2038
2039 static int init_phys_status_page(struct intel_engine_cs *ring)
2040 {
2041         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2042
2043         if (!dev_priv->status_page_dmah) {
2044                 dev_priv->status_page_dmah =
2045                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
2046                 if (!dev_priv->status_page_dmah)
2047                         return -ENOMEM;
2048         }
2049
2050         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2051         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
2052
2053         return 0;
2054 }
2055
2056 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2057 {
2058         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2059                 vunmap(ringbuf->virtual_start);
2060         else
2061                 iounmap(ringbuf->virtual_start);
2062         ringbuf->virtual_start = NULL;
2063         ringbuf->vma = NULL;
2064         i915_gem_object_ggtt_unpin(ringbuf->obj);
2065 }
2066
2067 static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2068 {
2069         struct sg_page_iter sg_iter;
2070         struct page **pages;
2071         void *addr;
2072         int i;
2073
2074         pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2075         if (pages == NULL)
2076                 return NULL;
2077
2078         i = 0;
2079         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2080                 pages[i++] = sg_page_iter_page(&sg_iter);
2081
2082         addr = vmap(pages, i, 0, PAGE_KERNEL);
2083         drm_free_large(pages);
2084
2085         return addr;
2086 }
2087
2088 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2089                                      struct intel_ringbuffer *ringbuf)
2090 {
2091         struct drm_i915_private *dev_priv = to_i915(dev);
2092         struct drm_i915_gem_object *obj = ringbuf->obj;
2093         int ret;
2094
2095         if (HAS_LLC(dev_priv) && !obj->stolen) {
2096                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2097                 if (ret)
2098                         return ret;
2099
2100                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2101                 if (ret) {
2102                         i915_gem_object_ggtt_unpin(obj);
2103                         return ret;
2104                 }
2105
2106                 ringbuf->virtual_start = vmap_obj(obj);
2107                 if (ringbuf->virtual_start == NULL) {
2108                         i915_gem_object_ggtt_unpin(obj);
2109                         return -ENOMEM;
2110                 }
2111         } else {
2112                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2113                 if (ret)
2114                         return ret;
2115
2116                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2117                 if (ret) {
2118                         i915_gem_object_ggtt_unpin(obj);
2119                         return ret;
2120                 }
2121
2122                 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2123                                                     i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2124                 if (ringbuf->virtual_start == NULL) {
2125                         i915_gem_object_ggtt_unpin(obj);
2126                         return -EINVAL;
2127                 }
2128         }
2129
2130         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2131
2132         return 0;
2133 }
2134
2135 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2136 {
2137         drm_gem_object_unreference(&ringbuf->obj->base);
2138         ringbuf->obj = NULL;
2139 }
2140
2141 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2142                                       struct intel_ringbuffer *ringbuf)
2143 {
2144         struct drm_i915_gem_object *obj;
2145
2146         obj = NULL;
2147         if (!HAS_LLC(dev))
2148                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2149         if (obj == NULL)
2150                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2151         if (obj == NULL)
2152                 return -ENOMEM;
2153
2154         /* mark ring buffers as read-only from GPU side by default */
2155         obj->gt_ro = 1;
2156
2157         ringbuf->obj = obj;
2158
2159         return 0;
2160 }
2161
2162 struct intel_ringbuffer *
2163 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2164 {
2165         struct intel_ringbuffer *ring;
2166         int ret;
2167
2168         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2169         if (ring == NULL) {
2170                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2171                                  engine->name);
2172                 return ERR_PTR(-ENOMEM);
2173         }
2174
2175         ring->ring = engine;
2176         list_add(&ring->link, &engine->buffers);
2177
2178         ring->size = size;
2179         /* Workaround an erratum on the i830 which causes a hang if
2180          * the TAIL pointer points to within the last 2 cachelines
2181          * of the buffer.
2182          */
2183         ring->effective_size = size;
2184         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2185                 ring->effective_size -= 2 * CACHELINE_BYTES;
2186
2187         ring->last_retired_head = -1;
2188         intel_ring_update_space(ring);
2189
2190         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2191         if (ret) {
2192                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2193                                  engine->name, ret);
2194                 list_del(&ring->link);
2195                 kfree(ring);
2196                 return ERR_PTR(ret);
2197         }
2198
2199         return ring;
2200 }
2201
2202 void
2203 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2204 {
2205         intel_destroy_ringbuffer_obj(ring);
2206         list_del(&ring->link);
2207         kfree(ring);
2208 }
2209
2210 static int intel_init_ring_buffer(struct drm_device *dev,
2211                                   struct intel_engine_cs *ring)
2212 {
2213         struct intel_ringbuffer *ringbuf;
2214         int ret;
2215
2216         WARN_ON(ring->buffer);
2217
2218         ring->dev = dev;
2219         INIT_LIST_HEAD(&ring->active_list);
2220         INIT_LIST_HEAD(&ring->request_list);
2221         INIT_LIST_HEAD(&ring->execlist_queue);
2222         INIT_LIST_HEAD(&ring->buffers);
2223         i915_gem_batch_pool_init(dev, &ring->batch_pool);
2224         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2225
2226         init_waitqueue_head(&ring->irq_queue);
2227
2228         ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2229         if (IS_ERR(ringbuf)) {
2230                 ret = PTR_ERR(ringbuf);
2231                 goto error;
2232         }
2233         ring->buffer = ringbuf;
2234
2235         if (I915_NEED_GFX_HWS(dev)) {
2236                 ret = init_status_page(ring);
2237                 if (ret)
2238                         goto error;
2239         } else {
2240                 WARN_ON(ring->id != RCS);
2241                 ret = init_phys_status_page(ring);
2242                 if (ret)
2243                         goto error;
2244         }
2245
2246         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2247         if (ret) {
2248                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2249                                 ring->name, ret);
2250                 intel_destroy_ringbuffer_obj(ringbuf);
2251                 goto error;
2252         }
2253
2254         ret = i915_cmd_parser_init_ring(ring);
2255         if (ret)
2256                 goto error;
2257
2258         return 0;
2259
2260 error:
2261         intel_cleanup_ring_buffer(ring);
2262         return ret;
2263 }
2264
2265 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2266 {
2267         struct drm_i915_private *dev_priv;
2268
2269         if (!intel_ring_initialized(ring))
2270                 return;
2271
2272         dev_priv = to_i915(ring->dev);
2273
2274         if (ring->buffer) {
2275                 intel_stop_ring_buffer(ring);
2276                 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2277
2278                 intel_unpin_ringbuffer_obj(ring->buffer);
2279                 intel_ringbuffer_free(ring->buffer);
2280                 ring->buffer = NULL;
2281         }
2282
2283         if (ring->cleanup)
2284                 ring->cleanup(ring);
2285
2286         if (I915_NEED_GFX_HWS(ring->dev)) {
2287                 cleanup_status_page(ring);
2288         } else {
2289                 WARN_ON(ring->id != RCS);
2290                 cleanup_phys_status_page(ring);
2291         }
2292
2293         i915_cmd_parser_fini_ring(ring);
2294         i915_gem_batch_pool_fini(&ring->batch_pool);
2295         ring->dev = NULL;
2296 }
2297
2298 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2299 {
2300         struct intel_ringbuffer *ringbuf = ring->buffer;
2301         struct drm_i915_gem_request *request;
2302         unsigned space;
2303         int ret;
2304
2305         if (intel_ring_space(ringbuf) >= n)
2306                 return 0;
2307
2308         /* The whole point of reserving space is to not wait! */
2309         WARN_ON(ringbuf->reserved_in_use);
2310
2311         list_for_each_entry(request, &ring->request_list, list) {
2312                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2313                                            ringbuf->size);
2314                 if (space >= n)
2315                         break;
2316         }
2317
2318         if (WARN_ON(&request->list == &ring->request_list))
2319                 return -ENOSPC;
2320
2321         ret = i915_wait_request(request);
2322         if (ret)
2323                 return ret;
2324
2325         ringbuf->space = space;
2326         return 0;
2327 }
2328
2329 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2330 {
2331         uint32_t __iomem *virt;
2332         int rem = ringbuf->size - ringbuf->tail;
2333
2334         virt = ringbuf->virtual_start + ringbuf->tail;
2335         rem /= 4;
2336         while (rem--)
2337                 iowrite32(MI_NOOP, virt++);
2338
2339         ringbuf->tail = 0;
2340         intel_ring_update_space(ringbuf);
2341 }
2342
2343 int intel_ring_idle(struct intel_engine_cs *ring)
2344 {
2345         struct drm_i915_gem_request *req;
2346
2347         /* Wait upon the last request to be completed */
2348         if (list_empty(&ring->request_list))
2349                 return 0;
2350
2351         req = list_entry(ring->request_list.prev,
2352                         struct drm_i915_gem_request,
2353                         list);
2354
2355         /* Make sure we do not trigger any retires */
2356         return __i915_wait_request(req,
2357                                    atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2358                                    to_i915(ring->dev)->mm.interruptible,
2359                                    NULL, NULL);
2360 }
2361
2362 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2363 {
2364         request->ringbuf = request->ring->buffer;
2365         return 0;
2366 }
2367
2368 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2369 {
2370         /*
2371          * The first call merely notes the reserve request and is common for
2372          * all back ends. The subsequent localised _begin() call actually
2373          * ensures that the reservation is available. Without the begin, if
2374          * the request creator immediately submitted the request without
2375          * adding any commands to it then there might not actually be
2376          * sufficient room for the submission commands.
2377          */
2378         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2379
2380         return intel_ring_begin(request, 0);
2381 }
2382
2383 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2384 {
2385         WARN_ON(ringbuf->reserved_size);
2386         WARN_ON(ringbuf->reserved_in_use);
2387
2388         ringbuf->reserved_size = size;
2389 }
2390
2391 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2392 {
2393         WARN_ON(ringbuf->reserved_in_use);
2394
2395         ringbuf->reserved_size   = 0;
2396         ringbuf->reserved_in_use = false;
2397 }
2398
2399 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2400 {
2401         WARN_ON(ringbuf->reserved_in_use);
2402
2403         ringbuf->reserved_in_use = true;
2404         ringbuf->reserved_tail   = ringbuf->tail;
2405 }
2406
2407 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2408 {
2409         WARN_ON(!ringbuf->reserved_in_use);
2410         if (ringbuf->tail > ringbuf->reserved_tail) {
2411                 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2412                      "request reserved size too small: %d vs %d!\n",
2413                      ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2414         } else {
2415                 /*
2416                  * The ring was wrapped while the reserved space was in use.
2417                  * That means that some unknown amount of the ring tail was
2418                  * no-op filled and skipped. Thus simply adding the ring size
2419                  * to the tail and doing the above space check will not work.
2420                  * Rather than attempt to track how much tail was skipped,
2421                  * it is much simpler to say that also skipping the sanity
2422                  * check every once in a while is not a big issue.
2423                  */
2424         }
2425
2426         ringbuf->reserved_size   = 0;
2427         ringbuf->reserved_in_use = false;
2428 }
2429
2430 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2431 {
2432         struct intel_ringbuffer *ringbuf = ring->buffer;
2433         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2434         int remain_actual = ringbuf->size - ringbuf->tail;
2435         int ret, total_bytes, wait_bytes = 0;
2436         bool need_wrap = false;
2437
2438         if (ringbuf->reserved_in_use)
2439                 total_bytes = bytes;
2440         else
2441                 total_bytes = bytes + ringbuf->reserved_size;
2442
2443         if (unlikely(bytes > remain_usable)) {
2444                 /*
2445                  * Not enough space for the basic request. So need to flush
2446                  * out the remainder and then wait for base + reserved.
2447                  */
2448                 wait_bytes = remain_actual + total_bytes;
2449                 need_wrap = true;
2450         } else {
2451                 if (unlikely(total_bytes > remain_usable)) {
2452                         /*
2453                          * The base request will fit but the reserved space
2454                          * falls off the end. So only need to to wait for the
2455                          * reserved size after flushing out the remainder.
2456                          */
2457                         wait_bytes = remain_actual + ringbuf->reserved_size;
2458                         need_wrap = true;
2459                 } else if (total_bytes > ringbuf->space) {
2460                         /* No wrapping required, just waiting. */
2461                         wait_bytes = total_bytes;
2462                 }
2463         }
2464
2465         if (wait_bytes) {
2466                 ret = ring_wait_for_space(ring, wait_bytes);
2467                 if (unlikely(ret))
2468                         return ret;
2469
2470                 if (need_wrap)
2471                         __wrap_ring_buffer(ringbuf);
2472         }
2473
2474         return 0;
2475 }
2476
2477 int intel_ring_begin(struct drm_i915_gem_request *req,
2478                      int num_dwords)
2479 {
2480         struct intel_engine_cs *ring;
2481         struct drm_i915_private *dev_priv;
2482         int ret;
2483
2484         WARN_ON(req == NULL);
2485         ring = req->ring;
2486         dev_priv = ring->dev->dev_private;
2487
2488         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2489                                    dev_priv->mm.interruptible);
2490         if (ret)
2491                 return ret;
2492
2493         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2494         if (ret)
2495                 return ret;
2496
2497         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2498         return 0;
2499 }
2500
2501 /* Align the ring tail to a cacheline boundary */
2502 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2503 {
2504         struct intel_engine_cs *ring = req->ring;
2505         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2506         int ret;
2507
2508         if (num_dwords == 0)
2509                 return 0;
2510
2511         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2512         ret = intel_ring_begin(req, num_dwords);
2513         if (ret)
2514                 return ret;
2515
2516         while (num_dwords--)
2517                 intel_ring_emit(ring, MI_NOOP);
2518
2519         intel_ring_advance(ring);
2520
2521         return 0;
2522 }
2523
2524 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2525 {
2526         struct drm_device *dev = ring->dev;
2527         struct drm_i915_private *dev_priv = dev->dev_private;
2528
2529         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2530                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2531                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2532                 if (HAS_VEBOX(dev))
2533                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2534         }
2535
2536         ring->set_seqno(ring, seqno);
2537         ring->hangcheck.seqno = seqno;
2538 }
2539
2540 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2541                                      u32 value)
2542 {
2543         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2544
2545        /* Every tail move must follow the sequence below */
2546
2547         /* Disable notification that the ring is IDLE. The GT
2548          * will then assume that it is busy and bring it out of rc6.
2549          */
2550         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2551                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2552
2553         /* Clear the context id. Here be magic! */
2554         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2555
2556         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2557         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2558                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2559                      50))
2560                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2561
2562         /* Now that the ring is fully powered up, update the tail */
2563         I915_WRITE_TAIL(ring, value);
2564         POSTING_READ(RING_TAIL(ring->mmio_base));
2565
2566         /* Let the ring send IDLE messages to the GT again,
2567          * and so let it sleep to conserve power when idle.
2568          */
2569         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2570                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2571 }
2572
2573 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2574                                u32 invalidate, u32 flush)
2575 {
2576         struct intel_engine_cs *ring = req->ring;
2577         uint32_t cmd;
2578         int ret;
2579
2580         ret = intel_ring_begin(req, 4);
2581         if (ret)
2582                 return ret;
2583
2584         cmd = MI_FLUSH_DW;
2585         if (INTEL_INFO(ring->dev)->gen >= 8)
2586                 cmd += 1;
2587
2588         /* We always require a command barrier so that subsequent
2589          * commands, such as breadcrumb interrupts, are strictly ordered
2590          * wrt the contents of the write cache being flushed to memory
2591          * (and thus being coherent from the CPU).
2592          */
2593         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2594
2595         /*
2596          * Bspec vol 1c.5 - video engine command streamer:
2597          * "If ENABLED, all TLBs will be invalidated once the flush
2598          * operation is complete. This bit is only valid when the
2599          * Post-Sync Operation field is a value of 1h or 3h."
2600          */
2601         if (invalidate & I915_GEM_GPU_DOMAINS)
2602                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2603
2604         intel_ring_emit(ring, cmd);
2605         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2606         if (INTEL_INFO(ring->dev)->gen >= 8) {
2607                 intel_ring_emit(ring, 0); /* upper addr */
2608                 intel_ring_emit(ring, 0); /* value */
2609         } else  {
2610                 intel_ring_emit(ring, 0);
2611                 intel_ring_emit(ring, MI_NOOP);
2612         }
2613         intel_ring_advance(ring);
2614         return 0;
2615 }
2616
2617 static int
2618 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2619                               u64 offset, u32 len,
2620                               unsigned dispatch_flags)
2621 {
2622         struct intel_engine_cs *ring = req->ring;
2623         bool ppgtt = USES_PPGTT(ring->dev) &&
2624                         !(dispatch_flags & I915_DISPATCH_SECURE);
2625         int ret;
2626
2627         ret = intel_ring_begin(req, 4);
2628         if (ret)
2629                 return ret;
2630
2631         /* FIXME(BDW): Address space and security selectors. */
2632         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2633                         (dispatch_flags & I915_DISPATCH_RS ?
2634                          MI_BATCH_RESOURCE_STREAMER : 0));
2635         intel_ring_emit(ring, lower_32_bits(offset));
2636         intel_ring_emit(ring, upper_32_bits(offset));
2637         intel_ring_emit(ring, MI_NOOP);
2638         intel_ring_advance(ring);
2639
2640         return 0;
2641 }
2642
2643 static int
2644 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2645                              u64 offset, u32 len,
2646                              unsigned dispatch_flags)
2647 {
2648         struct intel_engine_cs *ring = req->ring;
2649         int ret;
2650
2651         ret = intel_ring_begin(req, 2);
2652         if (ret)
2653                 return ret;
2654
2655         intel_ring_emit(ring,
2656                         MI_BATCH_BUFFER_START |
2657                         (dispatch_flags & I915_DISPATCH_SECURE ?
2658                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2659                         (dispatch_flags & I915_DISPATCH_RS ?
2660                          MI_BATCH_RESOURCE_STREAMER : 0));
2661         /* bit0-7 is the length on GEN6+ */
2662         intel_ring_emit(ring, offset);
2663         intel_ring_advance(ring);
2664
2665         return 0;
2666 }
2667
2668 static int
2669 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2670                               u64 offset, u32 len,
2671                               unsigned dispatch_flags)
2672 {
2673         struct intel_engine_cs *ring = req->ring;
2674         int ret;
2675
2676         ret = intel_ring_begin(req, 2);
2677         if (ret)
2678                 return ret;
2679
2680         intel_ring_emit(ring,
2681                         MI_BATCH_BUFFER_START |
2682                         (dispatch_flags & I915_DISPATCH_SECURE ?
2683                          0 : MI_BATCH_NON_SECURE_I965));
2684         /* bit0-7 is the length on GEN6+ */
2685         intel_ring_emit(ring, offset);
2686         intel_ring_advance(ring);
2687
2688         return 0;
2689 }
2690
2691 /* Blitter support (SandyBridge+) */
2692
2693 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2694                            u32 invalidate, u32 flush)
2695 {
2696         struct intel_engine_cs *ring = req->ring;
2697         struct drm_device *dev = ring->dev;
2698         uint32_t cmd;
2699         int ret;
2700
2701         ret = intel_ring_begin(req, 4);
2702         if (ret)
2703                 return ret;
2704
2705         cmd = MI_FLUSH_DW;
2706         if (INTEL_INFO(dev)->gen >= 8)
2707                 cmd += 1;
2708
2709         /* We always require a command barrier so that subsequent
2710          * commands, such as breadcrumb interrupts, are strictly ordered
2711          * wrt the contents of the write cache being flushed to memory
2712          * (and thus being coherent from the CPU).
2713          */
2714         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2715
2716         /*
2717          * Bspec vol 1c.3 - blitter engine command streamer:
2718          * "If ENABLED, all TLBs will be invalidated once the flush
2719          * operation is complete. This bit is only valid when the
2720          * Post-Sync Operation field is a value of 1h or 3h."
2721          */
2722         if (invalidate & I915_GEM_DOMAIN_RENDER)
2723                 cmd |= MI_INVALIDATE_TLB;
2724         intel_ring_emit(ring, cmd);
2725         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2726         if (INTEL_INFO(dev)->gen >= 8) {
2727                 intel_ring_emit(ring, 0); /* upper addr */
2728                 intel_ring_emit(ring, 0); /* value */
2729         } else  {
2730                 intel_ring_emit(ring, 0);
2731                 intel_ring_emit(ring, MI_NOOP);
2732         }
2733         intel_ring_advance(ring);
2734
2735         return 0;
2736 }
2737
2738 int intel_init_render_ring_buffer(struct drm_device *dev)
2739 {
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2742         struct drm_i915_gem_object *obj;
2743         int ret;
2744
2745         ring->name = "render ring";
2746         ring->id = RCS;
2747         ring->exec_id = I915_EXEC_RENDER;
2748         ring->mmio_base = RENDER_RING_BASE;
2749
2750         if (INTEL_INFO(dev)->gen >= 8) {
2751                 if (i915_semaphore_is_enabled(dev)) {
2752                         obj = i915_gem_alloc_object(dev, 4096);
2753                         if (obj == NULL) {
2754                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2755                                 i915.semaphores = 0;
2756                         } else {
2757                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2758                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2759                                 if (ret != 0) {
2760                                         drm_gem_object_unreference(&obj->base);
2761                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2762                                         i915.semaphores = 0;
2763                                 } else
2764                                         dev_priv->semaphore_obj = obj;
2765                         }
2766                 }
2767
2768                 ring->init_context = intel_rcs_ctx_init;
2769                 ring->add_request = gen6_add_request;
2770                 ring->flush = gen8_render_ring_flush;
2771                 ring->irq_get = gen8_ring_get_irq;
2772                 ring->irq_put = gen8_ring_put_irq;
2773                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2774                 ring->get_seqno = gen6_ring_get_seqno;
2775                 ring->set_seqno = ring_set_seqno;
2776                 if (i915_semaphore_is_enabled(dev)) {
2777                         WARN_ON(!dev_priv->semaphore_obj);
2778                         ring->semaphore.sync_to = gen8_ring_sync;
2779                         ring->semaphore.signal = gen8_rcs_signal;
2780                         GEN8_RING_SEMAPHORE_INIT;
2781                 }
2782         } else if (INTEL_INFO(dev)->gen >= 6) {
2783                 ring->init_context = intel_rcs_ctx_init;
2784                 ring->add_request = gen6_add_request;
2785                 ring->flush = gen7_render_ring_flush;
2786                 if (INTEL_INFO(dev)->gen == 6)
2787                         ring->flush = gen6_render_ring_flush;
2788                 ring->irq_get = gen6_ring_get_irq;
2789                 ring->irq_put = gen6_ring_put_irq;
2790                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2791                 ring->get_seqno = gen6_ring_get_seqno;
2792                 ring->set_seqno = ring_set_seqno;
2793                 if (i915_semaphore_is_enabled(dev)) {
2794                         ring->semaphore.sync_to = gen6_ring_sync;
2795                         ring->semaphore.signal = gen6_signal;
2796                         /*
2797                          * The current semaphore is only applied on pre-gen8
2798                          * platform.  And there is no VCS2 ring on the pre-gen8
2799                          * platform. So the semaphore between RCS and VCS2 is
2800                          * initialized as INVALID.  Gen8 will initialize the
2801                          * sema between VCS2 and RCS later.
2802                          */
2803                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2804                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2805                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2806                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2807                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2808                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2809                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2810                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2811                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2812                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2813                 }
2814         } else if (IS_GEN5(dev)) {
2815                 ring->add_request = pc_render_add_request;
2816                 ring->flush = gen4_render_ring_flush;
2817                 ring->get_seqno = pc_render_get_seqno;
2818                 ring->set_seqno = pc_render_set_seqno;
2819                 ring->irq_get = gen5_ring_get_irq;
2820                 ring->irq_put = gen5_ring_put_irq;
2821                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2822                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2823         } else {
2824                 ring->add_request = i9xx_add_request;
2825                 if (INTEL_INFO(dev)->gen < 4)
2826                         ring->flush = gen2_render_ring_flush;
2827                 else
2828                         ring->flush = gen4_render_ring_flush;
2829                 ring->get_seqno = ring_get_seqno;
2830                 ring->set_seqno = ring_set_seqno;
2831                 if (IS_GEN2(dev)) {
2832                         ring->irq_get = i8xx_ring_get_irq;
2833                         ring->irq_put = i8xx_ring_put_irq;
2834                 } else {
2835                         ring->irq_get = i9xx_ring_get_irq;
2836                         ring->irq_put = i9xx_ring_put_irq;
2837                 }
2838                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2839         }
2840         ring->write_tail = ring_write_tail;
2841
2842         if (IS_HASWELL(dev))
2843                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2844         else if (IS_GEN8(dev))
2845                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2846         else if (INTEL_INFO(dev)->gen >= 6)
2847                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2848         else if (INTEL_INFO(dev)->gen >= 4)
2849                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2850         else if (IS_I830(dev) || IS_845G(dev))
2851                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2852         else
2853                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2854         ring->init_hw = init_render_ring;
2855         ring->cleanup = render_ring_cleanup;
2856
2857         /* Workaround batchbuffer to combat CS tlb bug. */
2858         if (HAS_BROKEN_CS_TLB(dev)) {
2859                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2860                 if (obj == NULL) {
2861                         DRM_ERROR("Failed to allocate batch bo\n");
2862                         return -ENOMEM;
2863                 }
2864
2865                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2866                 if (ret != 0) {
2867                         drm_gem_object_unreference(&obj->base);
2868                         DRM_ERROR("Failed to ping batch bo\n");
2869                         return ret;
2870                 }
2871
2872                 ring->scratch.obj = obj;
2873                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2874         }
2875
2876         ret = intel_init_ring_buffer(dev, ring);
2877         if (ret)
2878                 return ret;
2879
2880         if (INTEL_INFO(dev)->gen >= 5) {
2881                 ret = intel_init_pipe_control(ring);
2882                 if (ret)
2883                         return ret;
2884         }
2885
2886         return 0;
2887 }
2888
2889 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2890 {
2891         struct drm_i915_private *dev_priv = dev->dev_private;
2892         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2893
2894         ring->name = "bsd ring";
2895         ring->id = VCS;
2896         ring->exec_id = I915_EXEC_BSD;
2897
2898         ring->write_tail = ring_write_tail;
2899         if (INTEL_INFO(dev)->gen >= 6) {
2900                 ring->mmio_base = GEN6_BSD_RING_BASE;
2901                 /* gen6 bsd needs a special wa for tail updates */
2902                 if (IS_GEN6(dev))
2903                         ring->write_tail = gen6_bsd_ring_write_tail;
2904                 ring->flush = gen6_bsd_ring_flush;
2905                 ring->add_request = gen6_add_request;
2906                 ring->get_seqno = gen6_ring_get_seqno;
2907                 ring->set_seqno = ring_set_seqno;
2908                 if (INTEL_INFO(dev)->gen >= 8) {
2909                         ring->irq_enable_mask =
2910                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2911                         ring->irq_get = gen8_ring_get_irq;
2912                         ring->irq_put = gen8_ring_put_irq;
2913                         ring->dispatch_execbuffer =
2914                                 gen8_ring_dispatch_execbuffer;
2915                         if (i915_semaphore_is_enabled(dev)) {
2916                                 ring->semaphore.sync_to = gen8_ring_sync;
2917                                 ring->semaphore.signal = gen8_xcs_signal;
2918                                 GEN8_RING_SEMAPHORE_INIT;
2919                         }
2920                 } else {
2921                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2922                         ring->irq_get = gen6_ring_get_irq;
2923                         ring->irq_put = gen6_ring_put_irq;
2924                         ring->dispatch_execbuffer =
2925                                 gen6_ring_dispatch_execbuffer;
2926                         if (i915_semaphore_is_enabled(dev)) {
2927                                 ring->semaphore.sync_to = gen6_ring_sync;
2928                                 ring->semaphore.signal = gen6_signal;
2929                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2930                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2931                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2932                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2933                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2934                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2935                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2936                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2937                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2938                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2939                         }
2940                 }
2941         } else {
2942                 ring->mmio_base = BSD_RING_BASE;
2943                 ring->flush = bsd_ring_flush;
2944                 ring->add_request = i9xx_add_request;
2945                 ring->get_seqno = ring_get_seqno;
2946                 ring->set_seqno = ring_set_seqno;
2947                 if (IS_GEN5(dev)) {
2948                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2949                         ring->irq_get = gen5_ring_get_irq;
2950                         ring->irq_put = gen5_ring_put_irq;
2951                 } else {
2952                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2953                         ring->irq_get = i9xx_ring_get_irq;
2954                         ring->irq_put = i9xx_ring_put_irq;
2955                 }
2956                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2957         }
2958         ring->init_hw = init_ring_common;
2959
2960         return intel_init_ring_buffer(dev, ring);
2961 }
2962
2963 /**
2964  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2965  */
2966 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2967 {
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2970
2971         ring->name = "bsd2 ring";
2972         ring->id = VCS2;
2973         ring->exec_id = I915_EXEC_BSD;
2974
2975         ring->write_tail = ring_write_tail;
2976         ring->mmio_base = GEN8_BSD2_RING_BASE;
2977         ring->flush = gen6_bsd_ring_flush;
2978         ring->add_request = gen6_add_request;
2979         ring->get_seqno = gen6_ring_get_seqno;
2980         ring->set_seqno = ring_set_seqno;
2981         ring->irq_enable_mask =
2982                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2983         ring->irq_get = gen8_ring_get_irq;
2984         ring->irq_put = gen8_ring_put_irq;
2985         ring->dispatch_execbuffer =
2986                         gen8_ring_dispatch_execbuffer;
2987         if (i915_semaphore_is_enabled(dev)) {
2988                 ring->semaphore.sync_to = gen8_ring_sync;
2989                 ring->semaphore.signal = gen8_xcs_signal;
2990                 GEN8_RING_SEMAPHORE_INIT;
2991         }
2992         ring->init_hw = init_ring_common;
2993
2994         return intel_init_ring_buffer(dev, ring);
2995 }
2996
2997 int intel_init_blt_ring_buffer(struct drm_device *dev)
2998 {
2999         struct drm_i915_private *dev_priv = dev->dev_private;
3000         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
3001
3002         ring->name = "blitter ring";
3003         ring->id = BCS;
3004         ring->exec_id = I915_EXEC_BLT;
3005
3006         ring->mmio_base = BLT_RING_BASE;
3007         ring->write_tail = ring_write_tail;
3008         ring->flush = gen6_ring_flush;
3009         ring->add_request = gen6_add_request;
3010         ring->get_seqno = gen6_ring_get_seqno;
3011         ring->set_seqno = ring_set_seqno;
3012         if (INTEL_INFO(dev)->gen >= 8) {
3013                 ring->irq_enable_mask =
3014                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3015                 ring->irq_get = gen8_ring_get_irq;
3016                 ring->irq_put = gen8_ring_put_irq;
3017                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3018                 if (i915_semaphore_is_enabled(dev)) {
3019                         ring->semaphore.sync_to = gen8_ring_sync;
3020                         ring->semaphore.signal = gen8_xcs_signal;
3021                         GEN8_RING_SEMAPHORE_INIT;
3022                 }
3023         } else {
3024                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3025                 ring->irq_get = gen6_ring_get_irq;
3026                 ring->irq_put = gen6_ring_put_irq;
3027                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3028                 if (i915_semaphore_is_enabled(dev)) {
3029                         ring->semaphore.signal = gen6_signal;
3030                         ring->semaphore.sync_to = gen6_ring_sync;
3031                         /*
3032                          * The current semaphore is only applied on pre-gen8
3033                          * platform.  And there is no VCS2 ring on the pre-gen8
3034                          * platform. So the semaphore between BCS and VCS2 is
3035                          * initialized as INVALID.  Gen8 will initialize the
3036                          * sema between BCS and VCS2 later.
3037                          */
3038                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3039                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3040                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3041                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3042                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3043                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3044                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3045                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3046                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3047                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3048                 }
3049         }
3050         ring->init_hw = init_ring_common;
3051
3052         return intel_init_ring_buffer(dev, ring);
3053 }
3054
3055 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3056 {
3057         struct drm_i915_private *dev_priv = dev->dev_private;
3058         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
3059
3060         ring->name = "video enhancement ring";
3061         ring->id = VECS;
3062         ring->exec_id = I915_EXEC_VEBOX;
3063
3064         ring->mmio_base = VEBOX_RING_BASE;
3065         ring->write_tail = ring_write_tail;
3066         ring->flush = gen6_ring_flush;
3067         ring->add_request = gen6_add_request;
3068         ring->get_seqno = gen6_ring_get_seqno;
3069         ring->set_seqno = ring_set_seqno;
3070
3071         if (INTEL_INFO(dev)->gen >= 8) {
3072                 ring->irq_enable_mask =
3073                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3074                 ring->irq_get = gen8_ring_get_irq;
3075                 ring->irq_put = gen8_ring_put_irq;
3076                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3077                 if (i915_semaphore_is_enabled(dev)) {
3078                         ring->semaphore.sync_to = gen8_ring_sync;
3079                         ring->semaphore.signal = gen8_xcs_signal;
3080                         GEN8_RING_SEMAPHORE_INIT;
3081                 }
3082         } else {
3083                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3084                 ring->irq_get = hsw_vebox_get_irq;
3085                 ring->irq_put = hsw_vebox_put_irq;
3086                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3087                 if (i915_semaphore_is_enabled(dev)) {
3088                         ring->semaphore.sync_to = gen6_ring_sync;
3089                         ring->semaphore.signal = gen6_signal;
3090                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3091                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3092                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3093                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3094                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3095                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3096                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3097                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3098                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3099                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3100                 }
3101         }
3102         ring->init_hw = init_ring_common;
3103
3104         return intel_init_ring_buffer(dev, ring);
3105 }
3106
3107 int
3108 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3109 {
3110         struct intel_engine_cs *ring = req->ring;
3111         int ret;
3112
3113         if (!ring->gpu_caches_dirty)
3114                 return 0;
3115
3116         ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
3117         if (ret)
3118                 return ret;
3119
3120         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3121
3122         ring->gpu_caches_dirty = false;
3123         return 0;
3124 }
3125
3126 int
3127 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3128 {
3129         struct intel_engine_cs *ring = req->ring;
3130         uint32_t flush_domains;
3131         int ret;
3132
3133         flush_domains = 0;
3134         if (ring->gpu_caches_dirty)
3135                 flush_domains = I915_GEM_GPU_DOMAINS;
3136
3137         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3138         if (ret)
3139                 return ret;
3140
3141         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3142
3143         ring->gpu_caches_dirty = false;
3144         return 0;
3145 }
3146
3147 void
3148 intel_stop_ring_buffer(struct intel_engine_cs *ring)
3149 {
3150         int ret;
3151
3152         if (!intel_ring_initialized(ring))
3153                 return;
3154
3155         ret = intel_ring_idle(ring);
3156         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3157                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3158                           ring->name, ret);
3159
3160         stop_ring(ring);
3161 }