drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 int __intel_ring_space(int head, int tail, int size)
  38 {
  39         int space = head - tail;
  40         if (space <= 0)
  41                 space += size;
  42         return space - I915_RING_FREE_SPACE;
  43 }
  44
  45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  46 {
  47         if (ringbuf->last_retired_head != -1) {
  48                 ringbuf->head = ringbuf->last_retired_head;
  49                 ringbuf->last_retired_head = -1;
  50         }
  51
  52         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  53                                             ringbuf->tail, ringbuf->size);
  54 }
  55
  56 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  57 {
  58         intel_ring_update_space(ringbuf);
  59         return ringbuf->space;
  60 }
  61
  62 bool intel_ring_stopped(struct intel_engine_cs *engine)
  63 {
  64         struct drm_i915_private *dev_priv = engine->dev->dev_private;
  65         return dev_priv->gpu_error.stop_rings & intel_ring_flag(engine);
  66 }
  67
  68 static void __intel_ring_advance(struct intel_engine_cs *engine)
  69 {
  70         struct intel_ringbuffer *ringbuf = engine->buffer;
  71         ringbuf->tail &= ringbuf->size - 1;
  72         if (intel_ring_stopped(engine))
  73                 return;
  74         engine->write_tail(engine, ringbuf->tail);
  75 }
  76
  77 static int
  78 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  79                        u32      invalidate_domains,
  80                        u32      flush_domains)
  81 {
  82         struct intel_engine_cs *engine = req->engine;
  83         u32 cmd;
  84         int ret;
  85
  86         cmd = MI_FLUSH;
  87         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  88                 cmd |= MI_NO_WRITE_FLUSH;
  89
  90         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  91                 cmd |= MI_READ_FLUSH;
  92
  93         ret = intel_ring_begin(req, 2);
  94         if (ret)
  95                 return ret;
  96
  97         intel_ring_emit(engine, cmd);
  98         intel_ring_emit(engine, MI_NOOP);
  99         intel_ring_advance(engine);
 100
 101         return 0;
 102 }
 103
 104 static int
 105 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 106                        u32      invalidate_domains,
 107                        u32      flush_domains)
 108 {
 109         struct intel_engine_cs *engine = req->engine;
 110         struct drm_device *dev = engine->dev;
 111         u32 cmd;
 112         int ret;
 113
 114         /*
 115          * read/write caches:
 116          *
 117          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 118          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 119          * also flushed at 2d versus 3d pipeline switches.
 120          *
 121          * read-only caches:
 122          *
 123          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 124          * MI_READ_FLUSH is set, and is always flushed on 965.
 125          *
 126          * I915_GEM_DOMAIN_COMMAND may not exist?
 127          *
 128          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 129          * invalidated when MI_EXE_FLUSH is set.
 130          *
 131          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 132          * invalidated with every MI_FLUSH.
 133          *
 134          * TLBs:
 135          *
 136          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 137          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 138          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 139          * are flushed at any MI_FLUSH.
 140          */
 141
 142         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 143         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 144                 cmd &= ~MI_NO_WRITE_FLUSH;
 145         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 146                 cmd |= MI_EXE_FLUSH;
 147
 148         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 149             (IS_G4X(dev) || IS_GEN5(dev)))
 150                 cmd |= MI_INVALIDATE_ISP;
 151
 152         ret = intel_ring_begin(req, 2);
 153         if (ret)
 154                 return ret;
 155
 156         intel_ring_emit(engine, cmd);
 157         intel_ring_emit(engine, MI_NOOP);
 158         intel_ring_advance(engine);
 159
 160         return 0;
 161 }
 162
 163 /**
 164  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 165  * implementing two workarounds on gen6.  From section 1.4.7.1
 166  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 167  *
 168  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 169  * produced by non-pipelined state commands), software needs to first
 170  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 171  * 0.
 172  *
 173  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 174  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 175  *
 176  * And the workaround for these two requires this workaround first:
 177  *
 178  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 179  * BEFORE the pipe-control with a post-sync op and no write-cache
 180  * flushes.
 181  *
 182  * And this last workaround is tricky because of the requirements on
 183  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 184  * volume 2 part 1:
 185  *
 186  *     "1 of the following must also be set:
 187  *      - Render Target Cache Flush Enable ([12] of DW1)
 188  *      - Depth Cache Flush Enable ([0] of DW1)
 189  *      - Stall at Pixel Scoreboard ([1] of DW1)
 190  *      - Depth Stall ([13] of DW1)
 191  *      - Post-Sync Operation ([13] of DW1)
 192  *      - Notify Enable ([8] of DW1)"
 193  *
 194  * The cache flushes require the workaround flush that triggered this
 195  * one, so we can't use it.  Depth stall would trigger the same.
 196  * Post-sync nonzero is what triggered this second workaround, so we
 197  * can't use that one either.  Notify enable is IRQs, which aren't
 198  * really our business.  That leaves only stall at scoreboard.
 199  */
 200 static int
 201 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 202 {
 203         struct intel_engine_cs *engine = req->engine;
 204         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 205         int ret;
 206
 207         ret = intel_ring_begin(req, 6);
 208         if (ret)
 209                 return ret;
 210
 211         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 212         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 213                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 214         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 215         intel_ring_emit(engine, 0); /* low dword */
 216         intel_ring_emit(engine, 0); /* high dword */
 217         intel_ring_emit(engine, MI_NOOP);
 218         intel_ring_advance(engine);
 219
 220         ret = intel_ring_begin(req, 6);
 221         if (ret)
 222                 return ret;
 223
 224         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 225         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 226         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 227         intel_ring_emit(engine, 0);
 228         intel_ring_emit(engine, 0);
 229         intel_ring_emit(engine, MI_NOOP);
 230         intel_ring_advance(engine);
 231
 232         return 0;
 233 }
 234
 235 static int
 236 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 237                        u32 invalidate_domains, u32 flush_domains)
 238 {
 239         struct intel_engine_cs *engine = req->engine;
 240         u32 flags = 0;
 241         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 242         int ret;
 243
 244         /* Force SNB workarounds for PIPE_CONTROL flushes */
 245         ret = intel_emit_post_sync_nonzero_flush(req);
 246         if (ret)
 247                 return ret;
 248
 249         /* Just flush everything.  Experiments have shown that reducing the
 250          * number of bits based on the write domains has little performance
 251          * impact.
 252          */
 253         if (flush_domains) {
 254                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 255                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 256                 /*
 257                  * Ensure that any following seqno writes only happen
 258                  * when the render cache is indeed flushed.
 259                  */
 260                 flags |= PIPE_CONTROL_CS_STALL;
 261         }
 262         if (invalidate_domains) {
 263                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 264                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 265                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 266                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 267                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 268                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 269                 /*
 270                  * TLB invalidate requires a post-sync write.
 271                  */
 272                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 273         }
 274
 275         ret = intel_ring_begin(req, 4);
 276         if (ret)
 277                 return ret;
 278
 279         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 280         intel_ring_emit(engine, flags);
 281         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 282         intel_ring_emit(engine, 0);
 283         intel_ring_advance(engine);
 284
 285         return 0;
 286 }
 287
 288 static int
 289 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 290 {
 291         struct intel_engine_cs *engine = req->engine;
 292         int ret;
 293
 294         ret = intel_ring_begin(req, 4);
 295         if (ret)
 296                 return ret;
 297
 298         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 299         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 300                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 301         intel_ring_emit(engine, 0);
 302         intel_ring_emit(engine, 0);
 303         intel_ring_advance(engine);
 304
 305         return 0;
 306 }
 307
 308 static int
 309 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 310                        u32 invalidate_domains, u32 flush_domains)
 311 {
 312         struct intel_engine_cs *engine = req->engine;
 313         u32 flags = 0;
 314         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 315         int ret;
 316
 317         /*
 318          * Ensure that any following seqno writes only happen when the render
 319          * cache is indeed flushed.
 320          *
 321          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 322          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 323          * don't try to be clever and just set it unconditionally.
 324          */
 325         flags |= PIPE_CONTROL_CS_STALL;
 326
 327         /* Just flush everything.  Experiments have shown that reducing the
 328          * number of bits based on the write domains has little performance
 329          * impact.
 330          */
 331         if (flush_domains) {
 332                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 333                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 334                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 335                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 336         }
 337         if (invalidate_domains) {
 338                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 339                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 340                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 341                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 342                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 343                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 344                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 345                 /*
 346                  * TLB invalidate requires a post-sync write.
 347                  */
 348                 flags |= PIPE_CONTROL_QW_WRITE;
 349                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 350
 351                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 352
 353                 /* Workaround: we must issue a pipe_control with CS-stall bit
 354                  * set before a pipe_control command that has the state cache
 355                  * invalidate bit set. */
 356                 gen7_render_ring_cs_stall_wa(req);
 357         }
 358
 359         ret = intel_ring_begin(req, 4);
 360         if (ret)
 361                 return ret;
 362
 363         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 364         intel_ring_emit(engine, flags);
 365         intel_ring_emit(engine, scratch_addr);
 366         intel_ring_emit(engine, 0);
 367         intel_ring_advance(engine);
 368
 369         return 0;
 370 }
 371
 372 static int
 373 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 374                        u32 flags, u32 scratch_addr)
 375 {
 376         struct intel_engine_cs *engine = req->engine;
 377         int ret;
 378
 379         ret = intel_ring_begin(req, 6);
 380         if (ret)
 381                 return ret;
 382
 383         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 384         intel_ring_emit(engine, flags);
 385         intel_ring_emit(engine, scratch_addr);
 386         intel_ring_emit(engine, 0);
 387         intel_ring_emit(engine, 0);
 388         intel_ring_emit(engine, 0);
 389         intel_ring_advance(engine);
 390
 391         return 0;
 392 }
 393
 394 static int
 395 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 396                        u32 invalidate_domains, u32 flush_domains)
 397 {
 398         u32 flags = 0;
 399         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 400         int ret;
 401
 402         flags |= PIPE_CONTROL_CS_STALL;
 403
 404         if (flush_domains) {
 405                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 406                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 407                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 408                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 409         }
 410         if (invalidate_domains) {
 411                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 412                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 413                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 414                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 415                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 416                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 417                 flags |= PIPE_CONTROL_QW_WRITE;
 418                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 419
 420                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 421                 ret = gen8_emit_pipe_control(req,
 422                                              PIPE_CONTROL_CS_STALL |
 423                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 424                                              0);
 425                 if (ret)
 426                         return ret;
 427         }
 428
 429         return gen8_emit_pipe_control(req, flags, scratch_addr);
 430 }
 431
 432 static void ring_write_tail(struct intel_engine_cs *engine,
 433                             u32 value)
 434 {
 435         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 436         I915_WRITE_TAIL(engine, value);
 437 }
 438
 439 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 440 {
 441         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 442         u64 acthd;
 443
 444         if (INTEL_INFO(engine->dev)->gen >= 8)
 445                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 446                                          RING_ACTHD_UDW(engine->mmio_base));
 447         else if (INTEL_INFO(engine->dev)->gen >= 4)
 448                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 449         else
 450                 acthd = I915_READ(ACTHD);
 451
 452         return acthd;
 453 }
 454
 455 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 456 {
 457         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 458         u32 addr;
 459
 460         addr = dev_priv->status_page_dmah->busaddr;
 461         if (INTEL_INFO(engine->dev)->gen >= 4)
 462                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 463         I915_WRITE(HWS_PGA, addr);
 464 }
 465
 466 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 467 {
 468         struct drm_device *dev = engine->dev;
 469         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 470         i915_reg_t mmio;
 471
 472         /* The ring status page addresses are no longer next to the rest of
 473          * the ring registers as of gen7.
 474          */
 475         if (IS_GEN7(dev)) {
 476                 switch (engine->id) {
 477                 case RCS:
 478                         mmio = RENDER_HWS_PGA_GEN7;
 479                         break;
 480                 case BCS:
 481                         mmio = BLT_HWS_PGA_GEN7;
 482                         break;
 483                 /*
 484                  * VCS2 actually doesn't exist on Gen7. Only shut up
 485                  * gcc switch check warning
 486                  */
 487                 case VCS2:
 488                 case VCS:
 489                         mmio = BSD_HWS_PGA_GEN7;
 490                         break;
 491                 case VECS:
 492                         mmio = VEBOX_HWS_PGA_GEN7;
 493                         break;
 494                 }
 495         } else if (IS_GEN6(engine->dev)) {
 496                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 497         } else {
 498                 /* XXX: gen8 returns to sanity */
 499                 mmio = RING_HWS_PGA(engine->mmio_base);
 500         }
 501
 502         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 503         POSTING_READ(mmio);
 504
 505         /*
 506          * Flush the TLB for this page
 507          *
 508          * FIXME: These two bits have disappeared on gen8, so a question
 509          * arises: do we still need this and if so how should we go about
 510          * invalidating the TLB?
 511          */
 512         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 513                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 514
 515                 /* ring should be idle before issuing a sync flush*/
 516                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 517
 518                 I915_WRITE(reg,
 519                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 520                                               INSTPM_SYNC_FLUSH));
 521                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 522                              1000))
 523                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 524                                   engine->name);
 525         }
 526 }
 527
 528 static bool stop_ring(struct intel_engine_cs *engine)
 529 {
 530         struct drm_i915_private *dev_priv = to_i915(engine->dev);
 531
 532         if (!IS_GEN2(engine->dev)) {
 533                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 534                 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
 535                         DRM_ERROR("%s : timed out trying to stop ring\n",
 536                                   engine->name);
 537                         /* Sometimes we observe that the idle flag is not
 538                          * set even though the ring is empty. So double
 539                          * check before giving up.
 540                          */
 541                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 542                                 return false;
 543                 }
 544         }
 545
 546         I915_WRITE_CTL(engine, 0);
 547         I915_WRITE_HEAD(engine, 0);
 548         engine->write_tail(engine, 0);
 549
 550         if (!IS_GEN2(engine->dev)) {
 551                 (void)I915_READ_CTL(engine);
 552                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 553         }
 554
 555         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 556 }
 557
 558 static int init_ring_common(struct intel_engine_cs *engine)
 559 {
 560         struct drm_device *dev = engine->dev;
 561         struct drm_i915_private *dev_priv = dev->dev_private;
 562         struct intel_ringbuffer *ringbuf = engine->buffer;
 563         struct drm_i915_gem_object *obj = ringbuf->obj;
 564         int ret = 0;
 565
 566         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 567
 568         if (!stop_ring(engine)) {
 569                 /* G45 ring initialization often fails to reset head to zero */
 570                 DRM_DEBUG_KMS("%s head not reset to zero "
 571                               "ctl %08x head %08x tail %08x start %08x\n",
 572                               engine->name,
 573                               I915_READ_CTL(engine),
 574                               I915_READ_HEAD(engine),
 575                               I915_READ_TAIL(engine),
 576                               I915_READ_START(engine));
 577
 578                 if (!stop_ring(engine)) {
 579                         DRM_ERROR("failed to set %s head to zero "
 580                                   "ctl %08x head %08x tail %08x start %08x\n",
 581                                   engine->name,
 582                                   I915_READ_CTL(engine),
 583                                   I915_READ_HEAD(engine),
 584                                   I915_READ_TAIL(engine),
 585                                   I915_READ_START(engine));
 586                         ret = -EIO;
 587                         goto out;
 588                 }
 589         }
 590
 591         if (I915_NEED_GFX_HWS(dev))
 592                 intel_ring_setup_status_page(engine);
 593         else
 594                 ring_setup_phys_status_page(engine);
 595
 596         /* Enforce ordering by reading HEAD register back */
 597         I915_READ_HEAD(engine);
 598
 599         /* Initialize the ring. This must happen _after_ we've cleared the ring
 600          * registers with the above sequence (the readback of the HEAD registers
 601          * also enforces ordering), otherwise the hw might lose the new ring
 602          * register values. */
 603         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 604
 605         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 606         if (I915_READ_HEAD(engine))
 607                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 608                           engine->name, I915_READ_HEAD(engine));
 609         I915_WRITE_HEAD(engine, 0);
 610         (void)I915_READ_HEAD(engine);
 611
 612         I915_WRITE_CTL(engine,
 613                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 614                         | RING_VALID);
 615
 616         /* If the head is still not zero, the ring is dead */
 617         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 618                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 619                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 620                 DRM_ERROR("%s initialization failed "
 621                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 622                           engine->name,
 623                           I915_READ_CTL(engine),
 624                           I915_READ_CTL(engine) & RING_VALID,
 625                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 626                           I915_READ_START(engine),
 627                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 628                 ret = -EIO;
 629                 goto out;
 630         }
 631
 632         ringbuf->last_retired_head = -1;
 633         ringbuf->head = I915_READ_HEAD(engine);
 634         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 635         intel_ring_update_space(ringbuf);
 636
 637         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 638
 639 out:
 640         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 641
 642         return ret;
 643 }
 644
 645 void
 646 intel_fini_pipe_control(struct intel_engine_cs *engine)
 647 {
 648         struct drm_device *dev = engine->dev;
 649
 650         if (engine->scratch.obj == NULL)
 651                 return;
 652
 653         if (INTEL_INFO(dev)->gen >= 5) {
 654                 kunmap(sg_page(engine->scratch.obj->pages->sgl));
 655                 i915_gem_object_ggtt_unpin(engine->scratch.obj);
 656         }
 657
 658         drm_gem_object_unreference(&engine->scratch.obj->base);
 659         engine->scratch.obj = NULL;
 660 }
 661
 662 int
 663 intel_init_pipe_control(struct intel_engine_cs *engine)
 664 {
 665         int ret;
 666
 667         WARN_ON(engine->scratch.obj);
 668
 669         engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
 670         if (engine->scratch.obj == NULL) {
 671                 DRM_ERROR("Failed to allocate seqno page\n");
 672                 ret = -ENOMEM;
 673                 goto err;
 674         }
 675
 676         ret = i915_gem_object_set_cache_level(engine->scratch.obj,
 677                                               I915_CACHE_LLC);
 678         if (ret)
 679                 goto err_unref;
 680
 681         ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
 682         if (ret)
 683                 goto err_unref;
 684
 685         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
 686         engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
 687         if (engine->scratch.cpu_page == NULL) {
 688                 ret = -ENOMEM;
 689                 goto err_unpin;
 690         }
 691
 692         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 693                          engine->name, engine->scratch.gtt_offset);
 694         return 0;
 695
 696 err_unpin:
 697         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 698 err_unref:
 699         drm_gem_object_unreference(&engine->scratch.obj->base);
 700 err:
 701         return ret;
 702 }
 703
 704 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 705 {
 706         int ret, i;
 707         struct intel_engine_cs *engine = req->engine;
 708         struct drm_device *dev = engine->dev;
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710         struct i915_workarounds *w = &dev_priv->workarounds;
 711
 712         if (w->count == 0)
 713                 return 0;
 714
 715         engine->gpu_caches_dirty = true;
 716         ret = intel_ring_flush_all_caches(req);
 717         if (ret)
 718                 return ret;
 719
 720         ret = intel_ring_begin(req, (w->count * 2 + 2));
 721         if (ret)
 722                 return ret;
 723
 724         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 725         for (i = 0; i < w->count; i++) {
 726                 intel_ring_emit_reg(engine, w->reg[i].addr);
 727                 intel_ring_emit(engine, w->reg[i].value);
 728         }
 729         intel_ring_emit(engine, MI_NOOP);
 730
 731         intel_ring_advance(engine);
 732
 733         engine->gpu_caches_dirty = true;
 734         ret = intel_ring_flush_all_caches(req);
 735         if (ret)
 736                 return ret;
 737
 738         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 739
 740         return 0;
 741 }
 742
 743 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 744 {
 745         int ret;
 746
 747         ret = intel_ring_workarounds_emit(req);
 748         if (ret != 0)
 749                 return ret;
 750
 751         ret = i915_gem_render_state_init(req);
 752         if (ret)
 753                 return ret;
 754
 755         return 0;
 756 }
 757
 758 static int wa_add(struct drm_i915_private *dev_priv,
 759                   i915_reg_t addr,
 760                   const u32 mask, const u32 val)
 761 {
 762         const u32 idx = dev_priv->workarounds.count;
 763
 764         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 765                 return -ENOSPC;
 766
 767         dev_priv->workarounds.reg[idx].addr = addr;
 768         dev_priv->workarounds.reg[idx].value = val;
 769         dev_priv->workarounds.reg[idx].mask = mask;
 770
 771         dev_priv->workarounds.count++;
 772
 773         return 0;
 774 }
 775
 776 #define WA_REG(addr, mask, val) do { \
 777                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 778                 if (r) \
 779                         return r; \
 780         } while (0)
 781
 782 #define WA_SET_BIT_MASKED(addr, mask) \
 783         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 784
 785 #define WA_CLR_BIT_MASKED(addr, mask) \
 786         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 787
 788 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 789         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 790
 791 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 792 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 793
 794 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 795
 796 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 797                                  i915_reg_t reg)
 798 {
 799         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 800         struct i915_workarounds *wa = &dev_priv->workarounds;
 801         const uint32_t index = wa->hw_whitelist_count[engine->id];
 802
 803         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 804                 return -EINVAL;
 805
 806         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 807                  i915_mmio_reg_offset(reg));
 808         wa->hw_whitelist_count[engine->id]++;
 809
 810         return 0;
 811 }
 812
 813 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 814 {
 815         struct drm_device *dev = engine->dev;
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817
 818         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 819
 820         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 821         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 822
 823         /* WaDisablePartialInstShootdown:bdw,chv */
 824         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 825                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 826
 827         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 828          * workaround for for a possible hang in the unlikely event a TLB
 829          * invalidation occurs during a PSD flush.
 830          */
 831         /* WaForceEnableNonCoherent:bdw,chv */
 832         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 833         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 834                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 835                           HDC_FORCE_NON_COHERENT);
 836
 837         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 838          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 839          *  polygons in the same 8x4 pixel/sample area to be processed without
 840          *  stalling waiting for the earlier ones to write to Hierarchical Z
 841          *  buffer."
 842          *
 843          * This optimization is off by default for BDW and CHV; turn it on.
 844          */
 845         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 846
 847         /* Wa4x4STCOptimizationDisable:bdw,chv */
 848         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 849
 850         /*
 851          * BSpec recommends 8x4 when MSAA is used,
 852          * however in practice 16x4 seems fastest.
 853          *
 854          * Note that PS/WM thread counts depend on the WIZ hashing
 855          * disable bit, which we don't touch here, but it's good
 856          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 857          */
 858         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 859                             GEN6_WIZ_HASHING_MASK,
 860                             GEN6_WIZ_HASHING_16x4);
 861
 862         return 0;
 863 }
 864
 865 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 866 {
 867         int ret;
 868         struct drm_device *dev = engine->dev;
 869         struct drm_i915_private *dev_priv = dev->dev_private;
 870
 871         ret = gen8_init_workarounds(engine);
 872         if (ret)
 873                 return ret;
 874
 875         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 876         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 877
 878         /* WaDisableDopClockGating:bdw */
 879         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 880                           DOP_CLOCK_GATING_DISABLE);
 881
 882         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 883                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 884
 885         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 886                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 887                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 888                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 889                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 890
 891         return 0;
 892 }
 893
 894 static int chv_init_workarounds(struct intel_engine_cs *engine)
 895 {
 896         int ret;
 897         struct drm_device *dev = engine->dev;
 898         struct drm_i915_private *dev_priv = dev->dev_private;
 899
 900         ret = gen8_init_workarounds(engine);
 901         if (ret)
 902                 return ret;
 903
 904         /* WaDisableThreadStallDopClockGating:chv */
 905         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 906
 907         /* Improve HiZ throughput on CHV. */
 908         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 909
 910         return 0;
 911 }
 912
 913 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 914 {
 915         struct drm_device *dev = engine->dev;
 916         struct drm_i915_private *dev_priv = dev->dev_private;
 917         uint32_t tmp;
 918         int ret;
 919
 920         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 921         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 922                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 923
 924         /* WaDisableKillLogic:bxt,skl */
 925         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 926                    ECOCHK_DIS_TLB);
 927
 928         /* WaDisablePartialInstShootdown:skl,bxt */
 929         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 930                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 931
 932         /* Syncing dependencies between camera and graphics:skl,bxt */
 933         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 934                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 935
 936         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 937         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 938             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 939                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 940                                   GEN9_DG_MIRROR_FIX_ENABLE);
 941
 942         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 943         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 944             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 945                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 946                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 947                 /*
 948                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 949                  * but we do that in per ctx batchbuffer as there is an issue
 950                  * with this register not getting restored on ctx restore
 951                  */
 952         }
 953
 954         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 955         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
 956                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 957                                   GEN9_ENABLE_YV12_BUGFIX);
 958
 959         /* Wa4x4STCOptimizationDisable:skl,bxt */
 960         /* WaDisablePartialResolveInVc:skl,bxt */
 961         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 962                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 963
 964         /* WaCcsTlbPrefetchDisable:skl,bxt */
 965         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 966                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 967
 968         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 969         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 970             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 971                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 972                                   PIXEL_MASK_CAMMING_DISABLE);
 973
 974         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 975         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 976         if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
 977             IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
 978                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 979         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 980
 981         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 982         if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 983                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 984                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 985
 986         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 987         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 988
 989         /* WaOCLCoherentLineFlush:skl,bxt */
 990         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 991                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
 992
 993         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
 994         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
 995         if (ret)
 996                 return ret;
 997
 998         /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
 999         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1000         if (ret)
1001                 return ret;
1002
1003         return 0;
1004 }
1005
1006 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1007 {
1008         struct drm_device *dev = engine->dev;
1009         struct drm_i915_private *dev_priv = dev->dev_private;
1010         u8 vals[3] = { 0, 0, 0 };
1011         unsigned int i;
1012
1013         for (i = 0; i < 3; i++) {
1014                 u8 ss;
1015
1016                 /*
1017                  * Only consider slices where one, and only one, subslice has 7
1018                  * EUs
1019                  */
1020                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1021                         continue;
1022
1023                 /*
1024                  * subslice_7eu[i] != 0 (because of the check above) and
1025                  * ss_max == 4 (maximum number of subslices possible per slice)
1026                  *
1027                  * ->    0 <= ss <= 3;
1028                  */
1029                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1030                 vals[i] = 3 - ss;
1031         }
1032
1033         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1034                 return 0;
1035
1036         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1037         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1038                             GEN9_IZ_HASHING_MASK(2) |
1039                             GEN9_IZ_HASHING_MASK(1) |
1040                             GEN9_IZ_HASHING_MASK(0),
1041                             GEN9_IZ_HASHING(2, vals[2]) |
1042                             GEN9_IZ_HASHING(1, vals[1]) |
1043                             GEN9_IZ_HASHING(0, vals[0]));
1044
1045         return 0;
1046 }
1047
1048 static int skl_init_workarounds(struct intel_engine_cs *engine)
1049 {
1050         int ret;
1051         struct drm_device *dev = engine->dev;
1052         struct drm_i915_private *dev_priv = dev->dev_private;
1053
1054         ret = gen9_init_workarounds(engine);
1055         if (ret)
1056                 return ret;
1057
1058         /*
1059          * Actual WA is to disable percontext preemption granularity control
1060          * until D0 which is the default case so this is equivalent to
1061          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1062          */
1063         if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1064                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1065                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1066         }
1067
1068         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1069                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1070                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1071                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1072         }
1073
1074         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1075          * involving this register should also be added to WA batch as required.
1076          */
1077         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1078                 /* WaDisableLSQCROPERFforOCL:skl */
1079                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1080                            GEN8_LQSC_RO_PERF_DIS);
1081
1082         /* WaEnableGapsTsvCreditFix:skl */
1083         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1084                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1085                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1086         }
1087
1088         /* WaDisablePowerCompilerClockGating:skl */
1089         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1090                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1091                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1092
1093         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
1094                 /*
1095                  *Use Force Non-Coherent whenever executing a 3D context. This
1096                  * is a workaround for a possible hang in the unlikely event
1097                  * a TLB invalidation occurs during a PSD flush.
1098                  */
1099                 /* WaForceEnableNonCoherent:skl */
1100                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1101                                   HDC_FORCE_NON_COHERENT);
1102
1103                 /* WaDisableHDCInvalidation:skl */
1104                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1105                            BDW_DISABLE_HDC_INVALIDATION);
1106         }
1107
1108         /* WaBarrierPerformanceFixDisable:skl */
1109         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1110                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1111                                   HDC_FENCE_DEST_SLM_DISABLE |
1112                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1113
1114         /* WaDisableSbeCacheDispatchPortSharing:skl */
1115         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1116                 WA_SET_BIT_MASKED(
1117                         GEN7_HALF_SLICE_CHICKEN1,
1118                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1119
1120         /* WaDisableLSQCROPERFforOCL:skl */
1121         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1122         if (ret)
1123                 return ret;
1124
1125         return skl_tune_iz_hashing(engine);
1126 }
1127
1128 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1129 {
1130         int ret;
1131         struct drm_device *dev = engine->dev;
1132         struct drm_i915_private *dev_priv = dev->dev_private;
1133
1134         ret = gen9_init_workarounds(engine);
1135         if (ret)
1136                 return ret;
1137
1138         /* WaStoreMultiplePTEenable:bxt */
1139         /* This is a requirement according to Hardware specification */
1140         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1141                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1142
1143         /* WaSetClckGatingDisableMedia:bxt */
1144         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1145                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1146                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1147         }
1148
1149         /* WaDisableThreadStallDopClockGating:bxt */
1150         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1151                           STALL_DOP_GATING_DISABLE);
1152
1153         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1154         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1155                 WA_SET_BIT_MASKED(
1156                         GEN7_HALF_SLICE_CHICKEN1,
1157                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1158         }
1159
1160         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1161         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1162         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1163         /* WaDisableLSQCROPERFforOCL:bxt */
1164         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1165                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1166                 if (ret)
1167                         return ret;
1168
1169                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1170                 if (ret)
1171                         return ret;
1172         }
1173
1174         return 0;
1175 }
1176
1177 int init_workarounds_ring(struct intel_engine_cs *engine)
1178 {
1179         struct drm_device *dev = engine->dev;
1180         struct drm_i915_private *dev_priv = dev->dev_private;
1181
1182         WARN_ON(engine->id != RCS);
1183
1184         dev_priv->workarounds.count = 0;
1185         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1186
1187         if (IS_BROADWELL(dev))
1188                 return bdw_init_workarounds(engine);
1189
1190         if (IS_CHERRYVIEW(dev))
1191                 return chv_init_workarounds(engine);
1192
1193         if (IS_SKYLAKE(dev))
1194                 return skl_init_workarounds(engine);
1195
1196         if (IS_BROXTON(dev))
1197                 return bxt_init_workarounds(engine);
1198
1199         return 0;
1200 }
1201
1202 static int init_render_ring(struct intel_engine_cs *engine)
1203 {
1204         struct drm_device *dev = engine->dev;
1205         struct drm_i915_private *dev_priv = dev->dev_private;
1206         int ret = init_ring_common(engine);
1207         if (ret)
1208                 return ret;
1209
1210         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1211         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1212                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1213
1214         /* We need to disable the AsyncFlip performance optimisations in order
1215          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1216          * programmed to '1' on all products.
1217          *
1218          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1219          */
1220         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1221                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1222
1223         /* Required for the hardware to program scanline values for waiting */
1224         /* WaEnableFlushTlbInvalidationMode:snb */
1225         if (INTEL_INFO(dev)->gen == 6)
1226                 I915_WRITE(GFX_MODE,
1227                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1228
1229         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1230         if (IS_GEN7(dev))
1231                 I915_WRITE(GFX_MODE_GEN7,
1232                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1233                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1234
1235         if (IS_GEN6(dev)) {
1236                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1237                  * "If this bit is set, STCunit will have LRA as replacement
1238                  *  policy. [...] This bit must be reset.  LRA replacement
1239                  *  policy is not supported."
1240                  */
1241                 I915_WRITE(CACHE_MODE_0,
1242                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1243         }
1244
1245         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1246                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1247
1248         if (HAS_L3_DPF(dev))
1249                 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1250
1251         return init_workarounds_ring(engine);
1252 }
1253
1254 static void render_ring_cleanup(struct intel_engine_cs *engine)
1255 {
1256         struct drm_device *dev = engine->dev;
1257         struct drm_i915_private *dev_priv = dev->dev_private;
1258
1259         if (dev_priv->semaphore_obj) {
1260                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1261                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1262                 dev_priv->semaphore_obj = NULL;
1263         }
1264
1265         intel_fini_pipe_control(engine);
1266 }
1267
1268 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1269                            unsigned int num_dwords)
1270 {
1271 #define MBOX_UPDATE_DWORDS 8
1272         struct intel_engine_cs *signaller = signaller_req->engine;
1273         struct drm_device *dev = signaller->dev;
1274         struct drm_i915_private *dev_priv = dev->dev_private;
1275         struct intel_engine_cs *waiter;
1276         int i, ret, num_rings;
1277
1278         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1279         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1280 #undef MBOX_UPDATE_DWORDS
1281
1282         ret = intel_ring_begin(signaller_req, num_dwords);
1283         if (ret)
1284                 return ret;
1285
1286         for_each_ring(waiter, dev_priv, i) {
1287                 u32 seqno;
1288                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1289                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1290                         continue;
1291
1292                 seqno = i915_gem_request_get_seqno(signaller_req);
1293                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1294                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1295                                            PIPE_CONTROL_QW_WRITE |
1296                                            PIPE_CONTROL_FLUSH_ENABLE);
1297                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1298                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1299                 intel_ring_emit(signaller, seqno);
1300                 intel_ring_emit(signaller, 0);
1301                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1302                                            MI_SEMAPHORE_TARGET(waiter->id));
1303                 intel_ring_emit(signaller, 0);
1304         }
1305
1306         return 0;
1307 }
1308
1309 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1310                            unsigned int num_dwords)
1311 {
1312 #define MBOX_UPDATE_DWORDS 6
1313         struct intel_engine_cs *signaller = signaller_req->engine;
1314         struct drm_device *dev = signaller->dev;
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         struct intel_engine_cs *waiter;
1317         int i, ret, num_rings;
1318
1319         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1320         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1321 #undef MBOX_UPDATE_DWORDS
1322
1323         ret = intel_ring_begin(signaller_req, num_dwords);
1324         if (ret)
1325                 return ret;
1326
1327         for_each_ring(waiter, dev_priv, i) {
1328                 u32 seqno;
1329                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1330                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1331                         continue;
1332
1333                 seqno = i915_gem_request_get_seqno(signaller_req);
1334                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1335                                            MI_FLUSH_DW_OP_STOREDW);
1336                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1337                                            MI_FLUSH_DW_USE_GTT);
1338                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1339                 intel_ring_emit(signaller, seqno);
1340                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1341                                            MI_SEMAPHORE_TARGET(waiter->id));
1342                 intel_ring_emit(signaller, 0);
1343         }
1344
1345         return 0;
1346 }
1347
1348 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1349                        unsigned int num_dwords)
1350 {
1351         struct intel_engine_cs *signaller = signaller_req->engine;
1352         struct drm_device *dev = signaller->dev;
1353         struct drm_i915_private *dev_priv = dev->dev_private;
1354         struct intel_engine_cs *useless;
1355         int i, ret, num_rings;
1356
1357 #define MBOX_UPDATE_DWORDS 3
1358         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1359         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1360 #undef MBOX_UPDATE_DWORDS
1361
1362         ret = intel_ring_begin(signaller_req, num_dwords);
1363         if (ret)
1364                 return ret;
1365
1366         for_each_ring(useless, dev_priv, i) {
1367                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
1368
1369                 if (i915_mmio_reg_valid(mbox_reg)) {
1370                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1371
1372                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1373                         intel_ring_emit_reg(signaller, mbox_reg);
1374                         intel_ring_emit(signaller, seqno);
1375                 }
1376         }
1377
1378         /* If num_dwords was rounded, make sure the tail pointer is correct */
1379         if (num_rings % 2 == 0)
1380                 intel_ring_emit(signaller, MI_NOOP);
1381
1382         return 0;
1383 }
1384
1385 /**
1386  * gen6_add_request - Update the semaphore mailbox registers
1387  *
1388  * @request - request to write to the ring
1389  *
1390  * Update the mailbox registers in the *other* rings with the current seqno.
1391  * This acts like a signal in the canonical semaphore.
1392  */
1393 static int
1394 gen6_add_request(struct drm_i915_gem_request *req)
1395 {
1396         struct intel_engine_cs *engine = req->engine;
1397         int ret;
1398
1399         if (engine->semaphore.signal)
1400                 ret = engine->semaphore.signal(req, 4);
1401         else
1402                 ret = intel_ring_begin(req, 4);
1403
1404         if (ret)
1405                 return ret;
1406
1407         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1408         intel_ring_emit(engine,
1409                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1410         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1411         intel_ring_emit(engine, MI_USER_INTERRUPT);
1412         __intel_ring_advance(engine);
1413
1414         return 0;
1415 }
1416
1417 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1418                                               u32 seqno)
1419 {
1420         struct drm_i915_private *dev_priv = dev->dev_private;
1421         return dev_priv->last_seqno < seqno;
1422 }
1423
1424 /**
1425  * intel_ring_sync - sync the waiter to the signaller on seqno
1426  *
1427  * @waiter - ring that is waiting
1428  * @signaller - ring which has, or will signal
1429  * @seqno - seqno which the waiter will block on
1430  */
1431
1432 static int
1433 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1434                struct intel_engine_cs *signaller,
1435                u32 seqno)
1436 {
1437         struct intel_engine_cs *waiter = waiter_req->engine;
1438         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1439         int ret;
1440
1441         ret = intel_ring_begin(waiter_req, 4);
1442         if (ret)
1443                 return ret;
1444
1445         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1446                                 MI_SEMAPHORE_GLOBAL_GTT |
1447                                 MI_SEMAPHORE_POLL |
1448                                 MI_SEMAPHORE_SAD_GTE_SDD);
1449         intel_ring_emit(waiter, seqno);
1450         intel_ring_emit(waiter,
1451                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1452         intel_ring_emit(waiter,
1453                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1454         intel_ring_advance(waiter);
1455         return 0;
1456 }
1457
1458 static int
1459 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1460                struct intel_engine_cs *signaller,
1461                u32 seqno)
1462 {
1463         struct intel_engine_cs *waiter = waiter_req->engine;
1464         u32 dw1 = MI_SEMAPHORE_MBOX |
1465                   MI_SEMAPHORE_COMPARE |
1466                   MI_SEMAPHORE_REGISTER;
1467         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1468         int ret;
1469
1470         /* Throughout all of the GEM code, seqno passed implies our current
1471          * seqno is >= the last seqno executed. However for hardware the
1472          * comparison is strictly greater than.
1473          */
1474         seqno -= 1;
1475
1476         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1477
1478         ret = intel_ring_begin(waiter_req, 4);
1479         if (ret)
1480                 return ret;
1481
1482         /* If seqno wrap happened, omit the wait with no-ops */
1483         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1484                 intel_ring_emit(waiter, dw1 | wait_mbox);
1485                 intel_ring_emit(waiter, seqno);
1486                 intel_ring_emit(waiter, 0);
1487                 intel_ring_emit(waiter, MI_NOOP);
1488         } else {
1489                 intel_ring_emit(waiter, MI_NOOP);
1490                 intel_ring_emit(waiter, MI_NOOP);
1491                 intel_ring_emit(waiter, MI_NOOP);
1492                 intel_ring_emit(waiter, MI_NOOP);
1493         }
1494         intel_ring_advance(waiter);
1495
1496         return 0;
1497 }
1498
1499 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1500 do {                                                                    \
1501         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1502                  PIPE_CONTROL_DEPTH_STALL);                             \
1503         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1504         intel_ring_emit(ring__, 0);                                                     \
1505         intel_ring_emit(ring__, 0);                                                     \
1506 } while (0)
1507
1508 static int
1509 pc_render_add_request(struct drm_i915_gem_request *req)
1510 {
1511         struct intel_engine_cs *engine = req->engine;
1512         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1513         int ret;
1514
1515         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1516          * incoherent with writes to memory, i.e. completely fubar,
1517          * so we need to use PIPE_NOTIFY instead.
1518          *
1519          * However, we also need to workaround the qword write
1520          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1521          * memory before requesting an interrupt.
1522          */
1523         ret = intel_ring_begin(req, 32);
1524         if (ret)
1525                 return ret;
1526
1527         intel_ring_emit(engine,
1528                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1529                         PIPE_CONTROL_WRITE_FLUSH |
1530                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1531         intel_ring_emit(engine,
1532                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1533         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1534         intel_ring_emit(engine, 0);
1535         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1536         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1537         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1538         scratch_addr += 2 * CACHELINE_BYTES;
1539         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1540         scratch_addr += 2 * CACHELINE_BYTES;
1541         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1542         scratch_addr += 2 * CACHELINE_BYTES;
1543         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1544         scratch_addr += 2 * CACHELINE_BYTES;
1545         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1546
1547         intel_ring_emit(engine,
1548                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1549                         PIPE_CONTROL_WRITE_FLUSH |
1550                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1551                         PIPE_CONTROL_NOTIFY);
1552         intel_ring_emit(engine,
1553                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1554         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1555         intel_ring_emit(engine, 0);
1556         __intel_ring_advance(engine);
1557
1558         return 0;
1559 }
1560
1561 static u32
1562 gen6_ring_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
1563 {
1564         /* Workaround to force correct ordering between irq and seqno writes on
1565          * ivb (and maybe also on snb) by reading from a CS register (like
1566          * ACTHD) before reading the status page. */
1567         if (!lazy_coherency) {
1568                 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1569                 POSTING_READ(RING_ACTHD(engine->mmio_base));
1570         }
1571
1572         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1573 }
1574
1575 static u32
1576 ring_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
1577 {
1578         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1579 }
1580
1581 static void
1582 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1583 {
1584         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1585 }
1586
1587 static u32
1588 pc_render_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
1589 {
1590         return engine->scratch.cpu_page[0];
1591 }
1592
1593 static void
1594 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1595 {
1596         engine->scratch.cpu_page[0] = seqno;
1597 }
1598
1599 static bool
1600 gen5_ring_get_irq(struct intel_engine_cs *engine)
1601 {
1602         struct drm_device *dev = engine->dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         unsigned long flags;
1605
1606         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1607                 return false;
1608
1609         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1610         if (engine->irq_refcount++ == 0)
1611                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1612         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1613
1614         return true;
1615 }
1616
1617 static void
1618 gen5_ring_put_irq(struct intel_engine_cs *engine)
1619 {
1620         struct drm_device *dev = engine->dev;
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622         unsigned long flags;
1623
1624         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1625         if (--engine->irq_refcount == 0)
1626                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1627         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1628 }
1629
1630 static bool
1631 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1632 {
1633         struct drm_device *dev = engine->dev;
1634         struct drm_i915_private *dev_priv = dev->dev_private;
1635         unsigned long flags;
1636
1637         if (!intel_irqs_enabled(dev_priv))
1638                 return false;
1639
1640         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1641         if (engine->irq_refcount++ == 0) {
1642                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1643                 I915_WRITE(IMR, dev_priv->irq_mask);
1644                 POSTING_READ(IMR);
1645         }
1646         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1647
1648         return true;
1649 }
1650
1651 static void
1652 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1653 {
1654         struct drm_device *dev = engine->dev;
1655         struct drm_i915_private *dev_priv = dev->dev_private;
1656         unsigned long flags;
1657
1658         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1659         if (--engine->irq_refcount == 0) {
1660                 dev_priv->irq_mask |= engine->irq_enable_mask;
1661                 I915_WRITE(IMR, dev_priv->irq_mask);
1662                 POSTING_READ(IMR);
1663         }
1664         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1665 }
1666
1667 static bool
1668 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1669 {
1670         struct drm_device *dev = engine->dev;
1671         struct drm_i915_private *dev_priv = dev->dev_private;
1672         unsigned long flags;
1673
1674         if (!intel_irqs_enabled(dev_priv))
1675                 return false;
1676
1677         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1678         if (engine->irq_refcount++ == 0) {
1679                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1680                 I915_WRITE16(IMR, dev_priv->irq_mask);
1681                 POSTING_READ16(IMR);
1682         }
1683         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1684
1685         return true;
1686 }
1687
1688 static void
1689 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1690 {
1691         struct drm_device *dev = engine->dev;
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         unsigned long flags;
1694
1695         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1696         if (--engine->irq_refcount == 0) {
1697                 dev_priv->irq_mask |= engine->irq_enable_mask;
1698                 I915_WRITE16(IMR, dev_priv->irq_mask);
1699                 POSTING_READ16(IMR);
1700         }
1701         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1702 }
1703
1704 static int
1705 bsd_ring_flush(struct drm_i915_gem_request *req,
1706                u32     invalidate_domains,
1707                u32     flush_domains)
1708 {
1709         struct intel_engine_cs *engine = req->engine;
1710         int ret;
1711
1712         ret = intel_ring_begin(req, 2);
1713         if (ret)
1714                 return ret;
1715
1716         intel_ring_emit(engine, MI_FLUSH);
1717         intel_ring_emit(engine, MI_NOOP);
1718         intel_ring_advance(engine);
1719         return 0;
1720 }
1721
1722 static int
1723 i9xx_add_request(struct drm_i915_gem_request *req)
1724 {
1725         struct intel_engine_cs *engine = req->engine;
1726         int ret;
1727
1728         ret = intel_ring_begin(req, 4);
1729         if (ret)
1730                 return ret;
1731
1732         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1733         intel_ring_emit(engine,
1734                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1735         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1736         intel_ring_emit(engine, MI_USER_INTERRUPT);
1737         __intel_ring_advance(engine);
1738
1739         return 0;
1740 }
1741
1742 static bool
1743 gen6_ring_get_irq(struct intel_engine_cs *engine)
1744 {
1745         struct drm_device *dev = engine->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747         unsigned long flags;
1748
1749         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1750                 return false;
1751
1752         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1753         if (engine->irq_refcount++ == 0) {
1754                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1755                         I915_WRITE_IMR(engine,
1756                                        ~(engine->irq_enable_mask |
1757                                          GT_PARITY_ERROR(dev)));
1758                 else
1759                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1760                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1761         }
1762         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1763
1764         return true;
1765 }
1766
1767 static void
1768 gen6_ring_put_irq(struct intel_engine_cs *engine)
1769 {
1770         struct drm_device *dev = engine->dev;
1771         struct drm_i915_private *dev_priv = dev->dev_private;
1772         unsigned long flags;
1773
1774         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1775         if (--engine->irq_refcount == 0) {
1776                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1777                         I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1778                 else
1779                         I915_WRITE_IMR(engine, ~0);
1780                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1781         }
1782         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1783 }
1784
1785 static bool
1786 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1787 {
1788         struct drm_device *dev = engine->dev;
1789         struct drm_i915_private *dev_priv = dev->dev_private;
1790         unsigned long flags;
1791
1792         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1793                 return false;
1794
1795         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1796         if (engine->irq_refcount++ == 0) {
1797                 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1798                 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1799         }
1800         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1801
1802         return true;
1803 }
1804
1805 static void
1806 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1807 {
1808         struct drm_device *dev = engine->dev;
1809         struct drm_i915_private *dev_priv = dev->dev_private;
1810         unsigned long flags;
1811
1812         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1813         if (--engine->irq_refcount == 0) {
1814                 I915_WRITE_IMR(engine, ~0);
1815                 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1816         }
1817         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1818 }
1819
1820 static bool
1821 gen8_ring_get_irq(struct intel_engine_cs *engine)
1822 {
1823         struct drm_device *dev = engine->dev;
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         unsigned long flags;
1826
1827         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1828                 return false;
1829
1830         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1831         if (engine->irq_refcount++ == 0) {
1832                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1833                         I915_WRITE_IMR(engine,
1834                                        ~(engine->irq_enable_mask |
1835                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1836                 } else {
1837                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1838                 }
1839                 POSTING_READ(RING_IMR(engine->mmio_base));
1840         }
1841         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1842
1843         return true;
1844 }
1845
1846 static void
1847 gen8_ring_put_irq(struct intel_engine_cs *engine)
1848 {
1849         struct drm_device *dev = engine->dev;
1850         struct drm_i915_private *dev_priv = dev->dev_private;
1851         unsigned long flags;
1852
1853         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1854         if (--engine->irq_refcount == 0) {
1855                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1856                         I915_WRITE_IMR(engine,
1857                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1858                 } else {
1859                         I915_WRITE_IMR(engine, ~0);
1860                 }
1861                 POSTING_READ(RING_IMR(engine->mmio_base));
1862         }
1863         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1864 }
1865
1866 static int
1867 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1868                          u64 offset, u32 length,
1869                          unsigned dispatch_flags)
1870 {
1871         struct intel_engine_cs *engine = req->engine;
1872         int ret;
1873
1874         ret = intel_ring_begin(req, 2);
1875         if (ret)
1876                 return ret;
1877
1878         intel_ring_emit(engine,
1879                         MI_BATCH_BUFFER_START |
1880                         MI_BATCH_GTT |
1881                         (dispatch_flags & I915_DISPATCH_SECURE ?
1882                          0 : MI_BATCH_NON_SECURE_I965));
1883         intel_ring_emit(engine, offset);
1884         intel_ring_advance(engine);
1885
1886         return 0;
1887 }
1888
1889 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1890 #define I830_BATCH_LIMIT (256*1024)
1891 #define I830_TLB_ENTRIES (2)
1892 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1893 static int
1894 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1895                          u64 offset, u32 len,
1896                          unsigned dispatch_flags)
1897 {
1898         struct intel_engine_cs *engine = req->engine;
1899         u32 cs_offset = engine->scratch.gtt_offset;
1900         int ret;
1901
1902         ret = intel_ring_begin(req, 6);
1903         if (ret)
1904                 return ret;
1905
1906         /* Evict the invalid PTE TLBs */
1907         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1908         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1909         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1910         intel_ring_emit(engine, cs_offset);
1911         intel_ring_emit(engine, 0xdeadbeef);
1912         intel_ring_emit(engine, MI_NOOP);
1913         intel_ring_advance(engine);
1914
1915         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1916                 if (len > I830_BATCH_LIMIT)
1917                         return -ENOSPC;
1918
1919                 ret = intel_ring_begin(req, 6 + 2);
1920                 if (ret)
1921                         return ret;
1922
1923                 /* Blit the batch (which has now all relocs applied) to the
1924                  * stable batch scratch bo area (so that the CS never
1925                  * stumbles over its tlb invalidation bug) ...
1926                  */
1927                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1928                 intel_ring_emit(engine,
1929                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1930                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1931                 intel_ring_emit(engine, cs_offset);
1932                 intel_ring_emit(engine, 4096);
1933                 intel_ring_emit(engine, offset);
1934
1935                 intel_ring_emit(engine, MI_FLUSH);
1936                 intel_ring_emit(engine, MI_NOOP);
1937                 intel_ring_advance(engine);
1938
1939                 /* ... and execute it. */
1940                 offset = cs_offset;
1941         }
1942
1943         ret = intel_ring_begin(req, 2);
1944         if (ret)
1945                 return ret;
1946
1947         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1948         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1949                                           0 : MI_BATCH_NON_SECURE));
1950         intel_ring_advance(engine);
1951
1952         return 0;
1953 }
1954
1955 static int
1956 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1957                          u64 offset, u32 len,
1958                          unsigned dispatch_flags)
1959 {
1960         struct intel_engine_cs *engine = req->engine;
1961         int ret;
1962
1963         ret = intel_ring_begin(req, 2);
1964         if (ret)
1965                 return ret;
1966
1967         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1968         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1969                                           0 : MI_BATCH_NON_SECURE));
1970         intel_ring_advance(engine);
1971
1972         return 0;
1973 }
1974
1975 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1976 {
1977         struct drm_i915_private *dev_priv = to_i915(engine->dev);
1978
1979         if (!dev_priv->status_page_dmah)
1980                 return;
1981
1982         drm_pci_free(engine->dev, dev_priv->status_page_dmah);
1983         engine->status_page.page_addr = NULL;
1984 }
1985
1986 static void cleanup_status_page(struct intel_engine_cs *engine)
1987 {
1988         struct drm_i915_gem_object *obj;
1989
1990         obj = engine->status_page.obj;
1991         if (obj == NULL)
1992                 return;
1993
1994         kunmap(sg_page(obj->pages->sgl));
1995         i915_gem_object_ggtt_unpin(obj);
1996         drm_gem_object_unreference(&obj->base);
1997         engine->status_page.obj = NULL;
1998 }
1999
2000 static int init_status_page(struct intel_engine_cs *engine)
2001 {
2002         struct drm_i915_gem_object *obj = engine->status_page.obj;
2003
2004         if (obj == NULL) {
2005                 unsigned flags;
2006                 int ret;
2007
2008                 obj = i915_gem_alloc_object(engine->dev, 4096);
2009                 if (obj == NULL) {
2010                         DRM_ERROR("Failed to allocate status page\n");
2011                         return -ENOMEM;
2012                 }
2013
2014                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2015                 if (ret)
2016                         goto err_unref;
2017
2018                 flags = 0;
2019                 if (!HAS_LLC(engine->dev))
2020                         /* On g33, we cannot place HWS above 256MiB, so
2021                          * restrict its pinning to the low mappable arena.
2022                          * Though this restriction is not documented for
2023                          * gen4, gen5, or byt, they also behave similarly
2024                          * and hang if the HWS is placed at the top of the
2025                          * GTT. To generalise, it appears that all !llc
2026                          * platforms have issues with us placing the HWS
2027                          * above the mappable region (even though we never
2028                          * actualy map it).
2029                          */
2030                         flags |= PIN_MAPPABLE;
2031                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2032                 if (ret) {
2033 err_unref:
2034                         drm_gem_object_unreference(&obj->base);
2035                         return ret;
2036                 }
2037
2038                 engine->status_page.obj = obj;
2039         }
2040
2041         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2042         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2043         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2044
2045         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2046                         engine->name, engine->status_page.gfx_addr);
2047
2048         return 0;
2049 }
2050
2051 static int init_phys_status_page(struct intel_engine_cs *engine)
2052 {
2053         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2054
2055         if (!dev_priv->status_page_dmah) {
2056                 dev_priv->status_page_dmah =
2057                         drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2058                 if (!dev_priv->status_page_dmah)
2059                         return -ENOMEM;
2060         }
2061
2062         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2063         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2064
2065         return 0;
2066 }
2067
2068 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2069 {
2070         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2071                 vunmap(ringbuf->virtual_start);
2072         else
2073                 iounmap(ringbuf->virtual_start);
2074         ringbuf->virtual_start = NULL;
2075         ringbuf->vma = NULL;
2076         i915_gem_object_ggtt_unpin(ringbuf->obj);
2077 }
2078
2079 static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2080 {
2081         struct sg_page_iter sg_iter;
2082         struct page **pages;
2083         void *addr;
2084         int i;
2085
2086         pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2087         if (pages == NULL)
2088                 return NULL;
2089
2090         i = 0;
2091         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2092                 pages[i++] = sg_page_iter_page(&sg_iter);
2093
2094         addr = vmap(pages, i, 0, PAGE_KERNEL);
2095         drm_free_large(pages);
2096
2097         return addr;
2098 }
2099
2100 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2101                                      struct intel_ringbuffer *ringbuf)
2102 {
2103         struct drm_i915_private *dev_priv = to_i915(dev);
2104         struct drm_i915_gem_object *obj = ringbuf->obj;
2105         int ret;
2106
2107         if (HAS_LLC(dev_priv) && !obj->stolen) {
2108                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2109                 if (ret)
2110                         return ret;
2111
2112                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2113                 if (ret) {
2114                         i915_gem_object_ggtt_unpin(obj);
2115                         return ret;
2116                 }
2117
2118                 ringbuf->virtual_start = vmap_obj(obj);
2119                 if (ringbuf->virtual_start == NULL) {
2120                         i915_gem_object_ggtt_unpin(obj);
2121                         return -ENOMEM;
2122                 }
2123         } else {
2124                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2125                 if (ret)
2126                         return ret;
2127
2128                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2129                 if (ret) {
2130                         i915_gem_object_ggtt_unpin(obj);
2131                         return ret;
2132                 }
2133
2134                 /* Access through the GTT requires the device to be awake. */
2135                 assert_rpm_wakelock_held(dev_priv);
2136
2137                 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2138                                                     i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2139                 if (ringbuf->virtual_start == NULL) {
2140                         i915_gem_object_ggtt_unpin(obj);
2141                         return -EINVAL;
2142                 }
2143         }
2144
2145         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2146
2147         return 0;
2148 }
2149
2150 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2151 {
2152         drm_gem_object_unreference(&ringbuf->obj->base);
2153         ringbuf->obj = NULL;
2154 }
2155
2156 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2157                                       struct intel_ringbuffer *ringbuf)
2158 {
2159         struct drm_i915_gem_object *obj;
2160
2161         obj = NULL;
2162         if (!HAS_LLC(dev))
2163                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2164         if (obj == NULL)
2165                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2166         if (obj == NULL)
2167                 return -ENOMEM;
2168
2169         /* mark ring buffers as read-only from GPU side by default */
2170         obj->gt_ro = 1;
2171
2172         ringbuf->obj = obj;
2173
2174         return 0;
2175 }
2176
2177 struct intel_ringbuffer *
2178 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2179 {
2180         struct intel_ringbuffer *ring;
2181         int ret;
2182
2183         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2184         if (ring == NULL) {
2185                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2186                                  engine->name);
2187                 return ERR_PTR(-ENOMEM);
2188         }
2189
2190         ring->engine = engine;
2191         list_add(&ring->link, &engine->buffers);
2192
2193         ring->size = size;
2194         /* Workaround an erratum on the i830 which causes a hang if
2195          * the TAIL pointer points to within the last 2 cachelines
2196          * of the buffer.
2197          */
2198         ring->effective_size = size;
2199         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2200                 ring->effective_size -= 2 * CACHELINE_BYTES;
2201
2202         ring->last_retired_head = -1;
2203         intel_ring_update_space(ring);
2204
2205         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2206         if (ret) {
2207                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2208                                  engine->name, ret);
2209                 list_del(&ring->link);
2210                 kfree(ring);
2211                 return ERR_PTR(ret);
2212         }
2213
2214         return ring;
2215 }
2216
2217 void
2218 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2219 {
2220         intel_destroy_ringbuffer_obj(ring);
2221         list_del(&ring->link);
2222         kfree(ring);
2223 }
2224
2225 static int intel_init_ring_buffer(struct drm_device *dev,
2226                                   struct intel_engine_cs *engine)
2227 {
2228         struct intel_ringbuffer *ringbuf;
2229         int ret;
2230
2231         WARN_ON(engine->buffer);
2232
2233         engine->dev = dev;
2234         INIT_LIST_HEAD(&engine->active_list);
2235         INIT_LIST_HEAD(&engine->request_list);
2236         INIT_LIST_HEAD(&engine->execlist_queue);
2237         INIT_LIST_HEAD(&engine->buffers);
2238         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2239         memset(engine->semaphore.sync_seqno, 0,
2240                sizeof(engine->semaphore.sync_seqno));
2241
2242         init_waitqueue_head(&engine->irq_queue);
2243
2244         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2245         if (IS_ERR(ringbuf)) {
2246                 ret = PTR_ERR(ringbuf);
2247                 goto error;
2248         }
2249         engine->buffer = ringbuf;
2250
2251         if (I915_NEED_GFX_HWS(dev)) {
2252                 ret = init_status_page(engine);
2253                 if (ret)
2254                         goto error;
2255         } else {
2256                 WARN_ON(engine->id != RCS);
2257                 ret = init_phys_status_page(engine);
2258                 if (ret)
2259                         goto error;
2260         }
2261
2262         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2263         if (ret) {
2264                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2265                                 engine->name, ret);
2266                 intel_destroy_ringbuffer_obj(ringbuf);
2267                 goto error;
2268         }
2269
2270         ret = i915_cmd_parser_init_ring(engine);
2271         if (ret)
2272                 goto error;
2273
2274         return 0;
2275
2276 error:
2277         intel_cleanup_ring_buffer(engine);
2278         return ret;
2279 }
2280
2281 void intel_cleanup_ring_buffer(struct intel_engine_cs *engine)
2282 {
2283         struct drm_i915_private *dev_priv;
2284
2285         if (!intel_ring_initialized(engine))
2286                 return;
2287
2288         dev_priv = to_i915(engine->dev);
2289
2290         if (engine->buffer) {
2291                 intel_stop_ring_buffer(engine);
2292                 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2293
2294                 intel_unpin_ringbuffer_obj(engine->buffer);
2295                 intel_ringbuffer_free(engine->buffer);
2296                 engine->buffer = NULL;
2297         }
2298
2299         if (engine->cleanup)
2300                 engine->cleanup(engine);
2301
2302         if (I915_NEED_GFX_HWS(engine->dev)) {
2303                 cleanup_status_page(engine);
2304         } else {
2305                 WARN_ON(engine->id != RCS);
2306                 cleanup_phys_status_page(engine);
2307         }
2308
2309         i915_cmd_parser_fini_ring(engine);
2310         i915_gem_batch_pool_fini(&engine->batch_pool);
2311         engine->dev = NULL;
2312 }
2313
2314 static int ring_wait_for_space(struct intel_engine_cs *engine, int n)
2315 {
2316         struct intel_ringbuffer *ringbuf = engine->buffer;
2317         struct drm_i915_gem_request *request;
2318         unsigned space;
2319         int ret;
2320
2321         if (intel_ring_space(ringbuf) >= n)
2322                 return 0;
2323
2324         /* The whole point of reserving space is to not wait! */
2325         WARN_ON(ringbuf->reserved_in_use);
2326
2327         list_for_each_entry(request, &engine->request_list, list) {
2328                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2329                                            ringbuf->size);
2330                 if (space >= n)
2331                         break;
2332         }
2333
2334         if (WARN_ON(&request->list == &engine->request_list))
2335                 return -ENOSPC;
2336
2337         ret = i915_wait_request(request);
2338         if (ret)
2339                 return ret;
2340
2341         ringbuf->space = space;
2342         return 0;
2343 }
2344
2345 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2346 {
2347         uint32_t __iomem *virt;
2348         int rem = ringbuf->size - ringbuf->tail;
2349
2350         virt = ringbuf->virtual_start + ringbuf->tail;
2351         rem /= 4;
2352         while (rem--)
2353                 iowrite32(MI_NOOP, virt++);
2354
2355         ringbuf->tail = 0;
2356         intel_ring_update_space(ringbuf);
2357 }
2358
2359 int intel_ring_idle(struct intel_engine_cs *engine)
2360 {
2361         struct drm_i915_gem_request *req;
2362
2363         /* Wait upon the last request to be completed */
2364         if (list_empty(&engine->request_list))
2365                 return 0;
2366
2367         req = list_entry(engine->request_list.prev,
2368                          struct drm_i915_gem_request,
2369                          list);
2370
2371         /* Make sure we do not trigger any retires */
2372         return __i915_wait_request(req,
2373                                    atomic_read(&to_i915(engine->dev)->gpu_error.reset_counter),
2374                                    to_i915(engine->dev)->mm.interruptible,
2375                                    NULL, NULL);
2376 }
2377
2378 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2379 {
2380         request->ringbuf = request->engine->buffer;
2381         return 0;
2382 }
2383
2384 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2385 {
2386         /*
2387          * The first call merely notes the reserve request and is common for
2388          * all back ends. The subsequent localised _begin() call actually
2389          * ensures that the reservation is available. Without the begin, if
2390          * the request creator immediately submitted the request without
2391          * adding any commands to it then there might not actually be
2392          * sufficient room for the submission commands.
2393          */
2394         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2395
2396         return intel_ring_begin(request, 0);
2397 }
2398
2399 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2400 {
2401         WARN_ON(ringbuf->reserved_size);
2402         WARN_ON(ringbuf->reserved_in_use);
2403
2404         ringbuf->reserved_size = size;
2405 }
2406
2407 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2408 {
2409         WARN_ON(ringbuf->reserved_in_use);
2410
2411         ringbuf->reserved_size   = 0;
2412         ringbuf->reserved_in_use = false;
2413 }
2414
2415 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2416 {
2417         WARN_ON(ringbuf->reserved_in_use);
2418
2419         ringbuf->reserved_in_use = true;
2420         ringbuf->reserved_tail   = ringbuf->tail;
2421 }
2422
2423 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2424 {
2425         WARN_ON(!ringbuf->reserved_in_use);
2426         if (ringbuf->tail > ringbuf->reserved_tail) {
2427                 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2428                      "request reserved size too small: %d vs %d!\n",
2429                      ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2430         } else {
2431                 /*
2432                  * The ring was wrapped while the reserved space was in use.
2433                  * That means that some unknown amount of the ring tail was
2434                  * no-op filled and skipped. Thus simply adding the ring size
2435                  * to the tail and doing the above space check will not work.
2436                  * Rather than attempt to track how much tail was skipped,
2437                  * it is much simpler to say that also skipping the sanity
2438                  * check every once in a while is not a big issue.
2439                  */
2440         }
2441
2442         ringbuf->reserved_size   = 0;
2443         ringbuf->reserved_in_use = false;
2444 }
2445
2446 static int __intel_ring_prepare(struct intel_engine_cs *engine, int bytes)
2447 {
2448         struct intel_ringbuffer *ringbuf = engine->buffer;
2449         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2450         int remain_actual = ringbuf->size - ringbuf->tail;
2451         int ret, total_bytes, wait_bytes = 0;
2452         bool need_wrap = false;
2453
2454         if (ringbuf->reserved_in_use)
2455                 total_bytes = bytes;
2456         else
2457                 total_bytes = bytes + ringbuf->reserved_size;
2458
2459         if (unlikely(bytes > remain_usable)) {
2460                 /*
2461                  * Not enough space for the basic request. So need to flush
2462                  * out the remainder and then wait for base + reserved.
2463                  */
2464                 wait_bytes = remain_actual + total_bytes;
2465                 need_wrap = true;
2466         } else {
2467                 if (unlikely(total_bytes > remain_usable)) {
2468                         /*
2469                          * The base request will fit but the reserved space
2470                          * falls off the end. So only need to to wait for the
2471                          * reserved size after flushing out the remainder.
2472                          */
2473                         wait_bytes = remain_actual + ringbuf->reserved_size;
2474                         need_wrap = true;
2475                 } else if (total_bytes > ringbuf->space) {
2476                         /* No wrapping required, just waiting. */
2477                         wait_bytes = total_bytes;
2478                 }
2479         }
2480
2481         if (wait_bytes) {
2482                 ret = ring_wait_for_space(engine, wait_bytes);
2483                 if (unlikely(ret))
2484                         return ret;
2485
2486                 if (need_wrap)
2487                         __wrap_ring_buffer(ringbuf);
2488         }
2489
2490         return 0;
2491 }
2492
2493 int intel_ring_begin(struct drm_i915_gem_request *req,
2494                      int num_dwords)
2495 {
2496         struct intel_engine_cs *engine;
2497         struct drm_i915_private *dev_priv;
2498         int ret;
2499
2500         WARN_ON(req == NULL);
2501         engine = req->engine;
2502         dev_priv = engine->dev->dev_private;
2503
2504         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2505                                    dev_priv->mm.interruptible);
2506         if (ret)
2507                 return ret;
2508
2509         ret = __intel_ring_prepare(engine, num_dwords * sizeof(uint32_t));
2510         if (ret)
2511                 return ret;
2512
2513         engine->buffer->space -= num_dwords * sizeof(uint32_t);
2514         return 0;
2515 }
2516
2517 /* Align the ring tail to a cacheline boundary */
2518 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2519 {
2520         struct intel_engine_cs *engine = req->engine;
2521         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2522         int ret;
2523
2524         if (num_dwords == 0)
2525                 return 0;
2526
2527         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2528         ret = intel_ring_begin(req, num_dwords);
2529         if (ret)
2530                 return ret;
2531
2532         while (num_dwords--)
2533                 intel_ring_emit(engine, MI_NOOP);
2534
2535         intel_ring_advance(engine);
2536
2537         return 0;
2538 }
2539
2540 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2541 {
2542         struct drm_device *dev = engine->dev;
2543         struct drm_i915_private *dev_priv = dev->dev_private;
2544
2545         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2546                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2547                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2548                 if (HAS_VEBOX(dev))
2549                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2550         }
2551
2552         engine->set_seqno(engine, seqno);
2553         engine->hangcheck.seqno = seqno;
2554 }
2555
2556 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2557                                      u32 value)
2558 {
2559         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2560
2561        /* Every tail move must follow the sequence below */
2562
2563         /* Disable notification that the ring is IDLE. The GT
2564          * will then assume that it is busy and bring it out of rc6.
2565          */
2566         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2567                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2568
2569         /* Clear the context id. Here be magic! */
2570         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2571
2572         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2573         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2574                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2575                      50))
2576                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2577
2578         /* Now that the ring is fully powered up, update the tail */
2579         I915_WRITE_TAIL(engine, value);
2580         POSTING_READ(RING_TAIL(engine->mmio_base));
2581
2582         /* Let the ring send IDLE messages to the GT again,
2583          * and so let it sleep to conserve power when idle.
2584          */
2585         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2586                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2587 }
2588
2589 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2590                                u32 invalidate, u32 flush)
2591 {
2592         struct intel_engine_cs *engine = req->engine;
2593         uint32_t cmd;
2594         int ret;
2595
2596         ret = intel_ring_begin(req, 4);
2597         if (ret)
2598                 return ret;
2599
2600         cmd = MI_FLUSH_DW;
2601         if (INTEL_INFO(engine->dev)->gen >= 8)
2602                 cmd += 1;
2603
2604         /* We always require a command barrier so that subsequent
2605          * commands, such as breadcrumb interrupts, are strictly ordered
2606          * wrt the contents of the write cache being flushed to memory
2607          * (and thus being coherent from the CPU).
2608          */
2609         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2610
2611         /*
2612          * Bspec vol 1c.5 - video engine command streamer:
2613          * "If ENABLED, all TLBs will be invalidated once the flush
2614          * operation is complete. This bit is only valid when the
2615          * Post-Sync Operation field is a value of 1h or 3h."
2616          */
2617         if (invalidate & I915_GEM_GPU_DOMAINS)
2618                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2619
2620         intel_ring_emit(engine, cmd);
2621         intel_ring_emit(engine,
2622                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2623         if (INTEL_INFO(engine->dev)->gen >= 8) {
2624                 intel_ring_emit(engine, 0); /* upper addr */
2625                 intel_ring_emit(engine, 0); /* value */
2626         } else  {
2627                 intel_ring_emit(engine, 0);
2628                 intel_ring_emit(engine, MI_NOOP);
2629         }
2630         intel_ring_advance(engine);
2631         return 0;
2632 }
2633
2634 static int
2635 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2636                               u64 offset, u32 len,
2637                               unsigned dispatch_flags)
2638 {
2639         struct intel_engine_cs *engine = req->engine;
2640         bool ppgtt = USES_PPGTT(engine->dev) &&
2641                         !(dispatch_flags & I915_DISPATCH_SECURE);
2642         int ret;
2643
2644         ret = intel_ring_begin(req, 4);
2645         if (ret)
2646                 return ret;
2647
2648         /* FIXME(BDW): Address space and security selectors. */
2649         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2650                         (dispatch_flags & I915_DISPATCH_RS ?
2651                          MI_BATCH_RESOURCE_STREAMER : 0));
2652         intel_ring_emit(engine, lower_32_bits(offset));
2653         intel_ring_emit(engine, upper_32_bits(offset));
2654         intel_ring_emit(engine, MI_NOOP);
2655         intel_ring_advance(engine);
2656
2657         return 0;
2658 }
2659
2660 static int
2661 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2662                              u64 offset, u32 len,
2663                              unsigned dispatch_flags)
2664 {
2665         struct intel_engine_cs *engine = req->engine;
2666         int ret;
2667
2668         ret = intel_ring_begin(req, 2);
2669         if (ret)
2670                 return ret;
2671
2672         intel_ring_emit(engine,
2673                         MI_BATCH_BUFFER_START |
2674                         (dispatch_flags & I915_DISPATCH_SECURE ?
2675                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2676                         (dispatch_flags & I915_DISPATCH_RS ?
2677                          MI_BATCH_RESOURCE_STREAMER : 0));
2678         /* bit0-7 is the length on GEN6+ */
2679         intel_ring_emit(engine, offset);
2680         intel_ring_advance(engine);
2681
2682         return 0;
2683 }
2684
2685 static int
2686 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2687                               u64 offset, u32 len,
2688                               unsigned dispatch_flags)
2689 {
2690         struct intel_engine_cs *engine = req->engine;
2691         int ret;
2692
2693         ret = intel_ring_begin(req, 2);
2694         if (ret)
2695                 return ret;
2696
2697         intel_ring_emit(engine,
2698                         MI_BATCH_BUFFER_START |
2699                         (dispatch_flags & I915_DISPATCH_SECURE ?
2700                          0 : MI_BATCH_NON_SECURE_I965));
2701         /* bit0-7 is the length on GEN6+ */
2702         intel_ring_emit(engine, offset);
2703         intel_ring_advance(engine);
2704
2705         return 0;
2706 }
2707
2708 /* Blitter support (SandyBridge+) */
2709
2710 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2711                            u32 invalidate, u32 flush)
2712 {
2713         struct intel_engine_cs *engine = req->engine;
2714         struct drm_device *dev = engine->dev;
2715         uint32_t cmd;
2716         int ret;
2717
2718         ret = intel_ring_begin(req, 4);
2719         if (ret)
2720                 return ret;
2721
2722         cmd = MI_FLUSH_DW;
2723         if (INTEL_INFO(dev)->gen >= 8)
2724                 cmd += 1;
2725
2726         /* We always require a command barrier so that subsequent
2727          * commands, such as breadcrumb interrupts, are strictly ordered
2728          * wrt the contents of the write cache being flushed to memory
2729          * (and thus being coherent from the CPU).
2730          */
2731         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2732
2733         /*
2734          * Bspec vol 1c.3 - blitter engine command streamer:
2735          * "If ENABLED, all TLBs will be invalidated once the flush
2736          * operation is complete. This bit is only valid when the
2737          * Post-Sync Operation field is a value of 1h or 3h."
2738          */
2739         if (invalidate & I915_GEM_DOMAIN_RENDER)
2740                 cmd |= MI_INVALIDATE_TLB;
2741         intel_ring_emit(engine, cmd);
2742         intel_ring_emit(engine,
2743                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2744         if (INTEL_INFO(dev)->gen >= 8) {
2745                 intel_ring_emit(engine, 0); /* upper addr */
2746                 intel_ring_emit(engine, 0); /* value */
2747         } else  {
2748                 intel_ring_emit(engine, 0);
2749                 intel_ring_emit(engine, MI_NOOP);
2750         }
2751         intel_ring_advance(engine);
2752
2753         return 0;
2754 }
2755
2756 int intel_init_render_ring_buffer(struct drm_device *dev)
2757 {
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2760         struct drm_i915_gem_object *obj;
2761         int ret;
2762
2763         engine->name = "render ring";
2764         engine->id = RCS;
2765         engine->exec_id = I915_EXEC_RENDER;
2766         engine->mmio_base = RENDER_RING_BASE;
2767
2768         if (INTEL_INFO(dev)->gen >= 8) {
2769                 if (i915_semaphore_is_enabled(dev)) {
2770                         obj = i915_gem_alloc_object(dev, 4096);
2771                         if (obj == NULL) {
2772                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2773                                 i915.semaphores = 0;
2774                         } else {
2775                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2776                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2777                                 if (ret != 0) {
2778                                         drm_gem_object_unreference(&obj->base);
2779                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2780                                         i915.semaphores = 0;
2781                                 } else
2782                                         dev_priv->semaphore_obj = obj;
2783                         }
2784                 }
2785
2786                 engine->init_context = intel_rcs_ctx_init;
2787                 engine->add_request = gen6_add_request;
2788                 engine->flush = gen8_render_ring_flush;
2789                 engine->irq_get = gen8_ring_get_irq;
2790                 engine->irq_put = gen8_ring_put_irq;
2791                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2792                 engine->get_seqno = gen6_ring_get_seqno;
2793                 engine->set_seqno = ring_set_seqno;
2794                 if (i915_semaphore_is_enabled(dev)) {
2795                         WARN_ON(!dev_priv->semaphore_obj);
2796                         engine->semaphore.sync_to = gen8_ring_sync;
2797                         engine->semaphore.signal = gen8_rcs_signal;
2798                         GEN8_RING_SEMAPHORE_INIT(engine);
2799                 }
2800         } else if (INTEL_INFO(dev)->gen >= 6) {
2801                 engine->init_context = intel_rcs_ctx_init;
2802                 engine->add_request = gen6_add_request;
2803                 engine->flush = gen7_render_ring_flush;
2804                 if (INTEL_INFO(dev)->gen == 6)
2805                         engine->flush = gen6_render_ring_flush;
2806                 engine->irq_get = gen6_ring_get_irq;
2807                 engine->irq_put = gen6_ring_put_irq;
2808                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2809                 engine->get_seqno = gen6_ring_get_seqno;
2810                 engine->set_seqno = ring_set_seqno;
2811                 if (i915_semaphore_is_enabled(dev)) {
2812                         engine->semaphore.sync_to = gen6_ring_sync;
2813                         engine->semaphore.signal = gen6_signal;
2814                         /*
2815                          * The current semaphore is only applied on pre-gen8
2816                          * platform.  And there is no VCS2 ring on the pre-gen8
2817                          * platform. So the semaphore between RCS and VCS2 is
2818                          * initialized as INVALID.  Gen8 will initialize the
2819                          * sema between VCS2 and RCS later.
2820                          */
2821                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2822                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2823                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2824                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2825                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2826                         engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2827                         engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2828                         engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2829                         engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2830                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2831                 }
2832         } else if (IS_GEN5(dev)) {
2833                 engine->add_request = pc_render_add_request;
2834                 engine->flush = gen4_render_ring_flush;
2835                 engine->get_seqno = pc_render_get_seqno;
2836                 engine->set_seqno = pc_render_set_seqno;
2837                 engine->irq_get = gen5_ring_get_irq;
2838                 engine->irq_put = gen5_ring_put_irq;
2839                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2840                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2841         } else {
2842                 engine->add_request = i9xx_add_request;
2843                 if (INTEL_INFO(dev)->gen < 4)
2844                         engine->flush = gen2_render_ring_flush;
2845                 else
2846                         engine->flush = gen4_render_ring_flush;
2847                 engine->get_seqno = ring_get_seqno;
2848                 engine->set_seqno = ring_set_seqno;
2849                 if (IS_GEN2(dev)) {
2850                         engine->irq_get = i8xx_ring_get_irq;
2851                         engine->irq_put = i8xx_ring_put_irq;
2852                 } else {
2853                         engine->irq_get = i9xx_ring_get_irq;
2854                         engine->irq_put = i9xx_ring_put_irq;
2855                 }
2856                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2857         }
2858         engine->write_tail = ring_write_tail;
2859
2860         if (IS_HASWELL(dev))
2861                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2862         else if (IS_GEN8(dev))
2863                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2864         else if (INTEL_INFO(dev)->gen >= 6)
2865                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2866         else if (INTEL_INFO(dev)->gen >= 4)
2867                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2868         else if (IS_I830(dev) || IS_845G(dev))
2869                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2870         else
2871                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2872         engine->init_hw = init_render_ring;
2873         engine->cleanup = render_ring_cleanup;
2874
2875         /* Workaround batchbuffer to combat CS tlb bug. */
2876         if (HAS_BROKEN_CS_TLB(dev)) {
2877                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2878                 if (obj == NULL) {
2879                         DRM_ERROR("Failed to allocate batch bo\n");
2880                         return -ENOMEM;
2881                 }
2882
2883                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2884                 if (ret != 0) {
2885                         drm_gem_object_unreference(&obj->base);
2886                         DRM_ERROR("Failed to ping batch bo\n");
2887                         return ret;
2888                 }
2889
2890                 engine->scratch.obj = obj;
2891                 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2892         }
2893
2894         ret = intel_init_ring_buffer(dev, engine);
2895         if (ret)
2896                 return ret;
2897
2898         if (INTEL_INFO(dev)->gen >= 5) {
2899                 ret = intel_init_pipe_control(engine);
2900                 if (ret)
2901                         return ret;
2902         }
2903
2904         return 0;
2905 }
2906
2907 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2908 {
2909         struct drm_i915_private *dev_priv = dev->dev_private;
2910         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2911
2912         engine->name = "bsd ring";
2913         engine->id = VCS;
2914         engine->exec_id = I915_EXEC_BSD;
2915
2916         engine->write_tail = ring_write_tail;
2917         if (INTEL_INFO(dev)->gen >= 6) {
2918                 engine->mmio_base = GEN6_BSD_RING_BASE;
2919                 /* gen6 bsd needs a special wa for tail updates */
2920                 if (IS_GEN6(dev))
2921                         engine->write_tail = gen6_bsd_ring_write_tail;
2922                 engine->flush = gen6_bsd_ring_flush;
2923                 engine->add_request = gen6_add_request;
2924                 engine->get_seqno = gen6_ring_get_seqno;
2925                 engine->set_seqno = ring_set_seqno;
2926                 if (INTEL_INFO(dev)->gen >= 8) {
2927                         engine->irq_enable_mask =
2928                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2929                         engine->irq_get = gen8_ring_get_irq;
2930                         engine->irq_put = gen8_ring_put_irq;
2931                         engine->dispatch_execbuffer =
2932                                 gen8_ring_dispatch_execbuffer;
2933                         if (i915_semaphore_is_enabled(dev)) {
2934                                 engine->semaphore.sync_to = gen8_ring_sync;
2935                                 engine->semaphore.signal = gen8_xcs_signal;
2936                                 GEN8_RING_SEMAPHORE_INIT(engine);
2937                         }
2938                 } else {
2939                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2940                         engine->irq_get = gen6_ring_get_irq;
2941                         engine->irq_put = gen6_ring_put_irq;
2942                         engine->dispatch_execbuffer =
2943                                 gen6_ring_dispatch_execbuffer;
2944                         if (i915_semaphore_is_enabled(dev)) {
2945                                 engine->semaphore.sync_to = gen6_ring_sync;
2946                                 engine->semaphore.signal = gen6_signal;
2947                                 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2948                                 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2949                                 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2950                                 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2951                                 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2952                                 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2953                                 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2954                                 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2955                                 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2956                                 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2957                         }
2958                 }
2959         } else {
2960                 engine->mmio_base = BSD_RING_BASE;
2961                 engine->flush = bsd_ring_flush;
2962                 engine->add_request = i9xx_add_request;
2963                 engine->get_seqno = ring_get_seqno;
2964                 engine->set_seqno = ring_set_seqno;
2965                 if (IS_GEN5(dev)) {
2966                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2967                         engine->irq_get = gen5_ring_get_irq;
2968                         engine->irq_put = gen5_ring_put_irq;
2969                 } else {
2970                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2971                         engine->irq_get = i9xx_ring_get_irq;
2972                         engine->irq_put = i9xx_ring_put_irq;
2973                 }
2974                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2975         }
2976         engine->init_hw = init_ring_common;
2977
2978         return intel_init_ring_buffer(dev, engine);
2979 }
2980
2981 /**
2982  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2983  */
2984 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2985 {
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2988
2989         engine->name = "bsd2 ring";
2990         engine->id = VCS2;
2991         engine->exec_id = I915_EXEC_BSD;
2992
2993         engine->write_tail = ring_write_tail;
2994         engine->mmio_base = GEN8_BSD2_RING_BASE;
2995         engine->flush = gen6_bsd_ring_flush;
2996         engine->add_request = gen6_add_request;
2997         engine->get_seqno = gen6_ring_get_seqno;
2998         engine->set_seqno = ring_set_seqno;
2999         engine->irq_enable_mask =
3000                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3001         engine->irq_get = gen8_ring_get_irq;
3002         engine->irq_put = gen8_ring_put_irq;
3003         engine->dispatch_execbuffer =
3004                         gen8_ring_dispatch_execbuffer;
3005         if (i915_semaphore_is_enabled(dev)) {
3006                 engine->semaphore.sync_to = gen8_ring_sync;
3007                 engine->semaphore.signal = gen8_xcs_signal;
3008                 GEN8_RING_SEMAPHORE_INIT(engine);
3009         }
3010         engine->init_hw = init_ring_common;
3011
3012         return intel_init_ring_buffer(dev, engine);
3013 }
3014
3015 int intel_init_blt_ring_buffer(struct drm_device *dev)
3016 {
3017         struct drm_i915_private *dev_priv = dev->dev_private;
3018         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3019
3020         engine->name = "blitter ring";
3021         engine->id = BCS;
3022         engine->exec_id = I915_EXEC_BLT;
3023
3024         engine->mmio_base = BLT_RING_BASE;
3025         engine->write_tail = ring_write_tail;
3026         engine->flush = gen6_ring_flush;
3027         engine->add_request = gen6_add_request;
3028         engine->get_seqno = gen6_ring_get_seqno;
3029         engine->set_seqno = ring_set_seqno;
3030         if (INTEL_INFO(dev)->gen >= 8) {
3031                 engine->irq_enable_mask =
3032                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3033                 engine->irq_get = gen8_ring_get_irq;
3034                 engine->irq_put = gen8_ring_put_irq;
3035                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3036                 if (i915_semaphore_is_enabled(dev)) {
3037                         engine->semaphore.sync_to = gen8_ring_sync;
3038                         engine->semaphore.signal = gen8_xcs_signal;
3039                         GEN8_RING_SEMAPHORE_INIT(engine);
3040                 }
3041         } else {
3042                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3043                 engine->irq_get = gen6_ring_get_irq;
3044                 engine->irq_put = gen6_ring_put_irq;
3045                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3046                 if (i915_semaphore_is_enabled(dev)) {
3047                         engine->semaphore.signal = gen6_signal;
3048                         engine->semaphore.sync_to = gen6_ring_sync;
3049                         /*
3050                          * The current semaphore is only applied on pre-gen8
3051                          * platform.  And there is no VCS2 ring on the pre-gen8
3052                          * platform. So the semaphore between BCS and VCS2 is
3053                          * initialized as INVALID.  Gen8 will initialize the
3054                          * sema between BCS and VCS2 later.
3055                          */
3056                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3057                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3058                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3059                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3060                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3061                         engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3062                         engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3063                         engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3064                         engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3065                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3066                 }
3067         }
3068         engine->init_hw = init_ring_common;
3069
3070         return intel_init_ring_buffer(dev, engine);
3071 }
3072
3073 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3074 {
3075         struct drm_i915_private *dev_priv = dev->dev_private;
3076         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3077
3078         engine->name = "video enhancement ring";
3079         engine->id = VECS;
3080         engine->exec_id = I915_EXEC_VEBOX;
3081
3082         engine->mmio_base = VEBOX_RING_BASE;
3083         engine->write_tail = ring_write_tail;
3084         engine->flush = gen6_ring_flush;
3085         engine->add_request = gen6_add_request;
3086         engine->get_seqno = gen6_ring_get_seqno;
3087         engine->set_seqno = ring_set_seqno;
3088
3089         if (INTEL_INFO(dev)->gen >= 8) {
3090                 engine->irq_enable_mask =
3091                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3092                 engine->irq_get = gen8_ring_get_irq;
3093                 engine->irq_put = gen8_ring_put_irq;
3094                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3095                 if (i915_semaphore_is_enabled(dev)) {
3096                         engine->semaphore.sync_to = gen8_ring_sync;
3097                         engine->semaphore.signal = gen8_xcs_signal;
3098                         GEN8_RING_SEMAPHORE_INIT(engine);
3099                 }
3100         } else {
3101                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3102                 engine->irq_get = hsw_vebox_get_irq;
3103                 engine->irq_put = hsw_vebox_put_irq;
3104                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3105                 if (i915_semaphore_is_enabled(dev)) {
3106                         engine->semaphore.sync_to = gen6_ring_sync;
3107                         engine->semaphore.signal = gen6_signal;
3108                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3109                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3110                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3111                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3112                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3113                         engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3114                         engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3115                         engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3116                         engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3117                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3118                 }
3119         }
3120         engine->init_hw = init_ring_common;
3121
3122         return intel_init_ring_buffer(dev, engine);
3123 }
3124
3125 int
3126 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3127 {
3128         struct intel_engine_cs *engine = req->engine;
3129         int ret;
3130
3131         if (!engine->gpu_caches_dirty)
3132                 return 0;
3133
3134         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3135         if (ret)
3136                 return ret;
3137
3138         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3139
3140         engine->gpu_caches_dirty = false;
3141         return 0;
3142 }
3143
3144 int
3145 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3146 {
3147         struct intel_engine_cs *engine = req->engine;
3148         uint32_t flush_domains;
3149         int ret;
3150
3151         flush_domains = 0;
3152         if (engine->gpu_caches_dirty)
3153                 flush_domains = I915_GEM_GPU_DOMAINS;
3154
3155         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3156         if (ret)
3157                 return ret;
3158
3159         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3160
3161         engine->gpu_caches_dirty = false;
3162         return 0;
3163 }
3164
3165 void
3166 intel_stop_ring_buffer(struct intel_engine_cs *engine)
3167 {
3168         int ret;
3169
3170         if (!intel_ring_initialized(engine))
3171                 return;
3172
3173         ret = intel_ring_idle(engine);
3174         if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error))
3175                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3176                           engine->name, ret);
3177
3178         stop_ring(engine);
3179 }