drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 static u32 i915_gem_get_seqno(struct drm_device *dev)
  38 {
  39         drm_i915_private_t *dev_priv = dev->dev_private;
  40         u32 seqno;
  41
  42         seqno = dev_priv->next_seqno;
  43
  44         /* reserve 0 for non-seqno */
  45         if (++dev_priv->next_seqno == 0)
  46                 dev_priv->next_seqno = 1;
  47
  48         return seqno;
  49 }
  50
  51 static void
  52 render_ring_flush(struct drm_device *dev,
  53                   struct intel_ring_buffer *ring,
  54                   u32   invalidate_domains,
  55                   u32   flush_domains)
  56 {
  57         drm_i915_private_t *dev_priv = dev->dev_private;
  58         u32 cmd;
  59
  60 #if WATCH_EXEC
  61         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
  62                   invalidate_domains, flush_domains);
  63 #endif
  64
  65         trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
  66                                      invalidate_domains, flush_domains);
  67
  68         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
  69                 /*
  70                  * read/write caches:
  71                  *
  72                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  73                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  74                  * also flushed at 2d versus 3d pipeline switches.
  75                  *
  76                  * read-only caches:
  77                  *
  78                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  79                  * MI_READ_FLUSH is set, and is always flushed on 965.
  80                  *
  81                  * I915_GEM_DOMAIN_COMMAND may not exist?
  82                  *
  83                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  84                  * invalidated when MI_EXE_FLUSH is set.
  85                  *
  86                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  87                  * invalidated with every MI_FLUSH.
  88                  *
  89                  * TLBs:
  90                  *
  91                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  92                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  93                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  94                  * are flushed at any MI_FLUSH.
  95                  */
  96
  97                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  98                 if ((invalidate_domains|flush_domains) &
  99                     I915_GEM_DOMAIN_RENDER)
 100                         cmd &= ~MI_NO_WRITE_FLUSH;
 101                 if (INTEL_INFO(dev)->gen < 4) {
 102                         /*
 103                          * On the 965, the sampler cache always gets flushed
 104                          * and this bit is reserved.
 105                          */
 106                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 107                                 cmd |= MI_READ_FLUSH;
 108                 }
 109                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 110                         cmd |= MI_EXE_FLUSH;
 111
 112 #if WATCH_EXEC
 113                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 114 #endif
 115                 intel_ring_begin(dev, ring, 2);
 116                 intel_ring_emit(dev, ring, cmd);
 117                 intel_ring_emit(dev, ring, MI_NOOP);
 118                 intel_ring_advance(dev, ring);
 119         }
 120 }
 121
 122 static void ring_write_tail(struct drm_device *dev,
 123                             struct intel_ring_buffer *ring,
 124                             u32 value)
 125 {
 126         drm_i915_private_t *dev_priv = dev->dev_private;
 127         I915_WRITE_TAIL(ring, value);
 128 }
 129
 130 u32 intel_ring_get_active_head(struct drm_device *dev,
 131                                struct intel_ring_buffer *ring)
 132 {
 133         drm_i915_private_t *dev_priv = dev->dev_private;
 134         u32 acthd_reg = INTEL_INFO(dev)->gen >= 4 ?
 135                         RING_ACTHD(ring->mmio_base) : ACTHD;
 136
 137         return I915_READ(acthd_reg);
 138 }
 139
 140 static int init_ring_common(struct drm_device *dev,
 141                             struct intel_ring_buffer *ring)
 142 {
 143         u32 head;
 144         drm_i915_private_t *dev_priv = dev->dev_private;
 145         struct drm_i915_gem_object *obj_priv;
 146         obj_priv = to_intel_bo(ring->gem_object);
 147
 148         /* Stop the ring if it's running. */
 149         I915_WRITE_CTL(ring, 0);
 150         I915_WRITE_HEAD(ring, 0);
 151         ring->write_tail(dev, ring, 0);
 152
 153         /* Initialize the ring. */
 154         I915_WRITE_START(ring, obj_priv->gtt_offset);
 155         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 156
 157         /* G45 ring initialization fails to reset head to zero */
 158         if (head != 0) {
 159                 DRM_DEBUG_KMS("%s head not reset to zero "
 160                               "ctl %08x head %08x tail %08x start %08x\n",
 161                               ring->name,
 162                               I915_READ_CTL(ring),
 163                               I915_READ_HEAD(ring),
 164                               I915_READ_TAIL(ring),
 165                               I915_READ_START(ring));
 166
 167                 I915_WRITE_HEAD(ring, 0);
 168
 169                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 170                         DRM_ERROR("failed to set %s head to zero "
 171                                   "ctl %08x head %08x tail %08x start %08x\n",
 172                                   ring->name,
 173                                   I915_READ_CTL(ring),
 174                                   I915_READ_HEAD(ring),
 175                                   I915_READ_TAIL(ring),
 176                                   I915_READ_START(ring));
 177                 }
 178         }
 179
 180         I915_WRITE_CTL(ring,
 181                         ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES)
 182                         | RING_REPORT_64K | RING_VALID);
 183
 184         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 185         /* If the head is still not zero, the ring is dead */
 186         if (head != 0) {
 187                 DRM_ERROR("%s initialization failed "
 188                                 "ctl %08x head %08x tail %08x start %08x\n",
 189                                 ring->name,
 190                                 I915_READ_CTL(ring),
 191                                 I915_READ_HEAD(ring),
 192                                 I915_READ_TAIL(ring),
 193                                 I915_READ_START(ring));
 194                 return -EIO;
 195         }
 196
 197         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 198                 i915_kernel_lost_context(dev);
 199         else {
 200                 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 201                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 202                 ring->space = ring->head - (ring->tail + 8);
 203                 if (ring->space < 0)
 204                         ring->space += ring->size;
 205         }
 206         return 0;
 207 }
 208
 209 static int init_render_ring(struct drm_device *dev,
 210                             struct intel_ring_buffer *ring)
 211 {
 212         drm_i915_private_t *dev_priv = dev->dev_private;
 213         int ret = init_ring_common(dev, ring);
 214         int mode;
 215
 216         if (INTEL_INFO(dev)->gen > 3) {
 217                 mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 218                 if (IS_GEN6(dev))
 219                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 220                 I915_WRITE(MI_MODE, mode);
 221         }
 222         return ret;
 223 }
 224
 225 #define PIPE_CONTROL_FLUSH(addr)                                        \
 226 do {                                                                    \
 227         OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |          \
 228                  PIPE_CONTROL_DEPTH_STALL | 2);                         \
 229         OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT);                       \
 230         OUT_RING(0);                                                    \
 231         OUT_RING(0);                                                    \
 232 } while (0)
 233
 234 /**
 235  * Creates a new sequence number, emitting a write of it to the status page
 236  * plus an interrupt, which will trigger i915_user_interrupt_handler.
 237  *
 238  * Must be called with struct_lock held.
 239  *
 240  * Returned sequence numbers are nonzero on success.
 241  */
 242 static u32
 243 render_ring_add_request(struct drm_device *dev,
 244                         struct intel_ring_buffer *ring,
 245                         u32 flush_domains)
 246 {
 247         drm_i915_private_t *dev_priv = dev->dev_private;
 248         u32 seqno;
 249
 250         seqno = i915_gem_get_seqno(dev);
 251
 252         if (IS_GEN6(dev)) {
 253                 BEGIN_LP_RING(6);
 254                 OUT_RING(GFX_OP_PIPE_CONTROL | 3);
 255                 OUT_RING(PIPE_CONTROL_QW_WRITE |
 256                          PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH |
 257                          PIPE_CONTROL_NOTIFY);
 258                 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 259                 OUT_RING(seqno);
 260                 OUT_RING(0);
 261                 OUT_RING(0);
 262                 ADVANCE_LP_RING();
 263         } else if (HAS_PIPE_CONTROL(dev)) {
 264                 u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
 265
 266                 /*
 267                  * Workaround qword write incoherence by flushing the
 268                  * PIPE_NOTIFY buffers out to memory before requesting
 269                  * an interrupt.
 270                  */
 271                 BEGIN_LP_RING(32);
 272                 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 273                          PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
 274                 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 275                 OUT_RING(seqno);
 276                 OUT_RING(0);
 277                 PIPE_CONTROL_FLUSH(scratch_addr);
 278                 scratch_addr += 128; /* write to separate cachelines */
 279                 PIPE_CONTROL_FLUSH(scratch_addr);
 280                 scratch_addr += 128;
 281                 PIPE_CONTROL_FLUSH(scratch_addr);
 282                 scratch_addr += 128;
 283                 PIPE_CONTROL_FLUSH(scratch_addr);
 284                 scratch_addr += 128;
 285                 PIPE_CONTROL_FLUSH(scratch_addr);
 286                 scratch_addr += 128;
 287                 PIPE_CONTROL_FLUSH(scratch_addr);
 288                 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 289                          PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 290                          PIPE_CONTROL_NOTIFY);
 291                 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 292                 OUT_RING(seqno);
 293                 OUT_RING(0);
 294                 ADVANCE_LP_RING();
 295         } else {
 296                 BEGIN_LP_RING(4);
 297                 OUT_RING(MI_STORE_DWORD_INDEX);
 298                 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 299                 OUT_RING(seqno);
 300
 301                 OUT_RING(MI_USER_INTERRUPT);
 302                 ADVANCE_LP_RING();
 303         }
 304         return seqno;
 305 }
 306
 307 static u32
 308 render_ring_get_seqno(struct drm_device *dev,
 309                       struct intel_ring_buffer *ring)
 310 {
 311         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 312         if (HAS_PIPE_CONTROL(dev))
 313                 return ((volatile u32 *)(dev_priv->seqno_page))[0];
 314         else
 315                 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 316 }
 317
 318 static void
 319 render_ring_get_user_irq(struct drm_device *dev,
 320                          struct intel_ring_buffer *ring)
 321 {
 322         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 323         unsigned long irqflags;
 324
 325         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 326         if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) {
 327                 if (HAS_PCH_SPLIT(dev))
 328                         ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
 329                 else
 330                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 331         }
 332         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 333 }
 334
 335 static void
 336 render_ring_put_user_irq(struct drm_device *dev,
 337                          struct intel_ring_buffer *ring)
 338 {
 339         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 340         unsigned long irqflags;
 341
 342         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 343         BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0);
 344         if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) {
 345                 if (HAS_PCH_SPLIT(dev))
 346                         ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
 347                 else
 348                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 349         }
 350         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 351 }
 352
 353 void intel_ring_setup_status_page(struct drm_device *dev,
 354                                   struct intel_ring_buffer *ring)
 355 {
 356         drm_i915_private_t *dev_priv = dev->dev_private;
 357         if (IS_GEN6(dev)) {
 358                 I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base),
 359                            ring->status_page.gfx_addr);
 360                 I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base)); /* posting read */
 361         } else {
 362                 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
 363                            ring->status_page.gfx_addr);
 364                 I915_READ(RING_HWS_PGA(ring->mmio_base)); /* posting read */
 365         }
 366
 367 }
 368
 369 static void
 370 bsd_ring_flush(struct drm_device *dev,
 371                 struct intel_ring_buffer *ring,
 372                 u32     invalidate_domains,
 373                 u32     flush_domains)
 374 {
 375         intel_ring_begin(dev, ring, 2);
 376         intel_ring_emit(dev, ring, MI_FLUSH);
 377         intel_ring_emit(dev, ring, MI_NOOP);
 378         intel_ring_advance(dev, ring);
 379 }
 380
 381 static int init_bsd_ring(struct drm_device *dev,
 382                          struct intel_ring_buffer *ring)
 383 {
 384         return init_ring_common(dev, ring);
 385 }
 386
 387 static u32
 388 ring_add_request(struct drm_device *dev,
 389                  struct intel_ring_buffer *ring,
 390                  u32 flush_domains)
 391 {
 392         u32 seqno;
 393
 394         seqno = i915_gem_get_seqno(dev);
 395
 396         intel_ring_begin(dev, ring, 4);
 397         intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX);
 398         intel_ring_emit(dev, ring,
 399                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 400         intel_ring_emit(dev, ring, seqno);
 401         intel_ring_emit(dev, ring, MI_USER_INTERRUPT);
 402         intel_ring_advance(dev, ring);
 403
 404         DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
 405
 406         return seqno;
 407 }
 408
 409 static void
 410 bsd_ring_get_user_irq(struct drm_device *dev,
 411                       struct intel_ring_buffer *ring)
 412 {
 413         /* do nothing */
 414 }
 415 static void
 416 bsd_ring_put_user_irq(struct drm_device *dev,
 417                       struct intel_ring_buffer *ring)
 418 {
 419         /* do nothing */
 420 }
 421
 422 static u32
 423 ring_status_page_get_seqno(struct drm_device *dev,
 424                            struct intel_ring_buffer *ring)
 425 {
 426         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 427 }
 428
 429 static int
 430 ring_dispatch_gem_execbuffer(struct drm_device *dev,
 431                              struct intel_ring_buffer *ring,
 432                              struct drm_i915_gem_execbuffer2 *exec,
 433                              struct drm_clip_rect *cliprects,
 434                              uint64_t exec_offset)
 435 {
 436         uint32_t exec_start;
 437         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
 438         intel_ring_begin(dev, ring, 2);
 439         intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START |
 440                         (2 << 6) | MI_BATCH_NON_SECURE_I965);
 441         intel_ring_emit(dev, ring, exec_start);
 442         intel_ring_advance(dev, ring);
 443         return 0;
 444 }
 445
 446 static int
 447 render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
 448                                     struct intel_ring_buffer *ring,
 449                                     struct drm_i915_gem_execbuffer2 *exec,
 450                                     struct drm_clip_rect *cliprects,
 451                                     uint64_t exec_offset)
 452 {
 453         drm_i915_private_t *dev_priv = dev->dev_private;
 454         int nbox = exec->num_cliprects;
 455         int i = 0, count;
 456         uint32_t exec_start, exec_len;
 457         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
 458         exec_len = (uint32_t) exec->batch_len;
 459
 460         trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
 461
 462         count = nbox ? nbox : 1;
 463
 464         for (i = 0; i < count; i++) {
 465                 if (i < nbox) {
 466                         int ret = i915_emit_box(dev, cliprects, i,
 467                                                 exec->DR1, exec->DR4);
 468                         if (ret)
 469                                 return ret;
 470                 }
 471
 472                 if (IS_I830(dev) || IS_845G(dev)) {
 473                         intel_ring_begin(dev, ring, 4);
 474                         intel_ring_emit(dev, ring, MI_BATCH_BUFFER);
 475                         intel_ring_emit(dev, ring,
 476                                         exec_start | MI_BATCH_NON_SECURE);
 477                         intel_ring_emit(dev, ring, exec_start + exec_len - 4);
 478                         intel_ring_emit(dev, ring, 0);
 479                 } else {
 480                         intel_ring_begin(dev, ring, 2);
 481                         if (INTEL_INFO(dev)->gen >= 4) {
 482                                 intel_ring_emit(dev, ring,
 483                                                 MI_BATCH_BUFFER_START | (2 << 6)
 484                                                 | MI_BATCH_NON_SECURE_I965);
 485                                 intel_ring_emit(dev, ring, exec_start);
 486                         } else {
 487                                 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START
 488                                                 | (2 << 6));
 489                                 intel_ring_emit(dev, ring, exec_start |
 490                                                 MI_BATCH_NON_SECURE);
 491                         }
 492                 }
 493                 intel_ring_advance(dev, ring);
 494         }
 495
 496         if (IS_G4X(dev) || IS_GEN5(dev)) {
 497                 intel_ring_begin(dev, ring, 2);
 498                 intel_ring_emit(dev, ring, MI_FLUSH |
 499                                 MI_NO_WRITE_FLUSH |
 500                                 MI_INVALIDATE_ISP );
 501                 intel_ring_emit(dev, ring, MI_NOOP);
 502                 intel_ring_advance(dev, ring);
 503         }
 504         /* XXX breadcrumb */
 505
 506         return 0;
 507 }
 508
 509 static void cleanup_status_page(struct drm_device *dev,
 510                                 struct intel_ring_buffer *ring)
 511 {
 512         drm_i915_private_t *dev_priv = dev->dev_private;
 513         struct drm_gem_object *obj;
 514         struct drm_i915_gem_object *obj_priv;
 515
 516         obj = ring->status_page.obj;
 517         if (obj == NULL)
 518                 return;
 519         obj_priv = to_intel_bo(obj);
 520
 521         kunmap(obj_priv->pages[0]);
 522         i915_gem_object_unpin(obj);
 523         drm_gem_object_unreference(obj);
 524         ring->status_page.obj = NULL;
 525
 526         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 527 }
 528
 529 static int init_status_page(struct drm_device *dev,
 530                             struct intel_ring_buffer *ring)
 531 {
 532         drm_i915_private_t *dev_priv = dev->dev_private;
 533         struct drm_gem_object *obj;
 534         struct drm_i915_gem_object *obj_priv;
 535         int ret;
 536
 537         obj = i915_gem_alloc_object(dev, 4096);
 538         if (obj == NULL) {
 539                 DRM_ERROR("Failed to allocate status page\n");
 540                 ret = -ENOMEM;
 541                 goto err;
 542         }
 543         obj_priv = to_intel_bo(obj);
 544         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
 545
 546         ret = i915_gem_object_pin(obj, 4096);
 547         if (ret != 0) {
 548                 goto err_unref;
 549         }
 550
 551         ring->status_page.gfx_addr = obj_priv->gtt_offset;
 552         ring->status_page.page_addr = kmap(obj_priv->pages[0]);
 553         if (ring->status_page.page_addr == NULL) {
 554                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 555                 goto err_unpin;
 556         }
 557         ring->status_page.obj = obj;
 558         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 559
 560         intel_ring_setup_status_page(dev, ring);
 561         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 562                         ring->name, ring->status_page.gfx_addr);
 563
 564         return 0;
 565
 566 err_unpin:
 567         i915_gem_object_unpin(obj);
 568 err_unref:
 569         drm_gem_object_unreference(obj);
 570 err:
 571         return ret;
 572 }
 573
 574 int intel_init_ring_buffer(struct drm_device *dev,
 575                            struct intel_ring_buffer *ring)
 576 {
 577         struct drm_i915_private *dev_priv = dev->dev_private;
 578         struct drm_i915_gem_object *obj_priv;
 579         struct drm_gem_object *obj;
 580         int ret;
 581
 582         ring->dev = dev;
 583         INIT_LIST_HEAD(&ring->active_list);
 584         INIT_LIST_HEAD(&ring->request_list);
 585         INIT_LIST_HEAD(&ring->gpu_write_list);
 586
 587         if (I915_NEED_GFX_HWS(dev)) {
 588                 ret = init_status_page(dev, ring);
 589                 if (ret)
 590                         return ret;
 591         }
 592
 593         obj = i915_gem_alloc_object(dev, ring->size);
 594         if (obj == NULL) {
 595                 DRM_ERROR("Failed to allocate ringbuffer\n");
 596                 ret = -ENOMEM;
 597                 goto err_hws;
 598         }
 599
 600         ring->gem_object = obj;
 601
 602         ret = i915_gem_object_pin(obj, PAGE_SIZE);
 603         if (ret)
 604                 goto err_unref;
 605
 606         obj_priv = to_intel_bo(obj);
 607         ring->map.size = ring->size;
 608         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
 609         ring->map.type = 0;
 610         ring->map.flags = 0;
 611         ring->map.mtrr = 0;
 612
 613         drm_core_ioremap_wc(&ring->map, dev);
 614         if (ring->map.handle == NULL) {
 615                 DRM_ERROR("Failed to map ringbuffer.\n");
 616                 ret = -EINVAL;
 617                 goto err_unpin;
 618         }
 619
 620         ring->virtual_start = ring->map.handle;
 621         ret = ring->init(dev, ring);
 622         if (ret)
 623                 goto err_unmap;
 624
 625         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 626                 i915_kernel_lost_context(dev);
 627         else {
 628                 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 629                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 630                 ring->space = ring->head - (ring->tail + 8);
 631                 if (ring->space < 0)
 632                         ring->space += ring->size;
 633         }
 634         return ret;
 635
 636 err_unmap:
 637         drm_core_ioremapfree(&ring->map, dev);
 638 err_unpin:
 639         i915_gem_object_unpin(obj);
 640 err_unref:
 641         drm_gem_object_unreference(obj);
 642         ring->gem_object = NULL;
 643 err_hws:
 644         cleanup_status_page(dev, ring);
 645         return ret;
 646 }
 647
 648 void intel_cleanup_ring_buffer(struct drm_device *dev,
 649                                struct intel_ring_buffer *ring)
 650 {
 651         if (ring->gem_object == NULL)
 652                 return;
 653
 654         drm_core_ioremapfree(&ring->map, dev);
 655
 656         i915_gem_object_unpin(ring->gem_object);
 657         drm_gem_object_unreference(ring->gem_object);
 658         ring->gem_object = NULL;
 659
 660         if (ring->cleanup)
 661                 ring->cleanup(ring);
 662
 663         cleanup_status_page(dev, ring);
 664 }
 665
 666 static int intel_wrap_ring_buffer(struct drm_device *dev,
 667                                   struct intel_ring_buffer *ring)
 668 {
 669         unsigned int *virt;
 670         int rem;
 671         rem = ring->size - ring->tail;
 672
 673         if (ring->space < rem) {
 674                 int ret = intel_wait_ring_buffer(dev, ring, rem);
 675                 if (ret)
 676                         return ret;
 677         }
 678
 679         virt = (unsigned int *)(ring->virtual_start + ring->tail);
 680         rem /= 8;
 681         while (rem--) {
 682                 *virt++ = MI_NOOP;
 683                 *virt++ = MI_NOOP;
 684         }
 685
 686         ring->tail = 0;
 687         ring->space = ring->head - 8;
 688
 689         return 0;
 690 }
 691
 692 int intel_wait_ring_buffer(struct drm_device *dev,
 693                            struct intel_ring_buffer *ring, int n)
 694 {
 695         unsigned long end;
 696         drm_i915_private_t *dev_priv = dev->dev_private;
 697         u32 head;
 698
 699         head = intel_read_status_page(ring, 4);
 700         if (head) {
 701                 ring->head = head & HEAD_ADDR;
 702                 ring->space = ring->head - (ring->tail + 8);
 703                 if (ring->space < 0)
 704                         ring->space += ring->size;
 705                 if (ring->space >= n)
 706                         return 0;
 707         }
 708
 709         trace_i915_ring_wait_begin (dev);
 710         end = jiffies + 3 * HZ;
 711         do {
 712                 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 713                 ring->space = ring->head - (ring->tail + 8);
 714                 if (ring->space < 0)
 715                         ring->space += ring->size;
 716                 if (ring->space >= n) {
 717                         trace_i915_ring_wait_end (dev);
 718                         return 0;
 719                 }
 720
 721                 if (dev->primary->master) {
 722                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 723                         if (master_priv->sarea_priv)
 724                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 725                 }
 726
 727                 msleep(1);
 728         } while (!time_after(jiffies, end));
 729         trace_i915_ring_wait_end (dev);
 730         return -EBUSY;
 731 }
 732
 733 void intel_ring_begin(struct drm_device *dev,
 734                       struct intel_ring_buffer *ring,
 735                       int num_dwords)
 736 {
 737         int n = 4*num_dwords;
 738         if (unlikely(ring->tail + n > ring->size))
 739                 intel_wrap_ring_buffer(dev, ring);
 740         if (unlikely(ring->space < n))
 741                 intel_wait_ring_buffer(dev, ring, n);
 742
 743         ring->space -= n;
 744 }
 745
 746 void intel_ring_advance(struct drm_device *dev,
 747                         struct intel_ring_buffer *ring)
 748 {
 749         ring->tail &= ring->size - 1;
 750         ring->write_tail(dev, ring, ring->tail);
 751 }
 752
 753 static const struct intel_ring_buffer render_ring = {
 754         .name                   = "render ring",
 755         .id                     = RING_RENDER,
 756         .mmio_base              = RENDER_RING_BASE,
 757         .size                   = 32 * PAGE_SIZE,
 758         .init                   = init_render_ring,
 759         .write_tail             = ring_write_tail,
 760         .flush                  = render_ring_flush,
 761         .add_request            = render_ring_add_request,
 762         .get_seqno              = render_ring_get_seqno,
 763         .user_irq_get           = render_ring_get_user_irq,
 764         .user_irq_put           = render_ring_put_user_irq,
 765         .dispatch_gem_execbuffer = render_ring_dispatch_gem_execbuffer,
 766 };
 767
 768 /* ring buffer for bit-stream decoder */
 769
 770 static const struct intel_ring_buffer bsd_ring = {
 771         .name                   = "bsd ring",
 772         .id                     = RING_BSD,
 773         .mmio_base              = BSD_RING_BASE,
 774         .size                   = 32 * PAGE_SIZE,
 775         .init                   = init_bsd_ring,
 776         .write_tail             = ring_write_tail,
 777         .flush                  = bsd_ring_flush,
 778         .add_request            = ring_add_request,
 779         .get_seqno              = ring_status_page_get_seqno,
 780         .user_irq_get           = bsd_ring_get_user_irq,
 781         .user_irq_put           = bsd_ring_put_user_irq,
 782         .dispatch_gem_execbuffer = ring_dispatch_gem_execbuffer,
 783 };
 784
 785
 786 static void gen6_bsd_ring_write_tail(struct drm_device *dev,
 787                                      struct intel_ring_buffer *ring,
 788                                      u32 value)
 789 {
 790        drm_i915_private_t *dev_priv = dev->dev_private;
 791
 792        /* Every tail move must follow the sequence below */
 793        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
 794                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
 795                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
 796        I915_WRITE(GEN6_BSD_RNCID, 0x0);
 797
 798        if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
 799                                GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
 800                        50))
 801                DRM_ERROR("timed out waiting for IDLE Indicator\n");
 802
 803        I915_WRITE_TAIL(ring, value);
 804        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
 805                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
 806                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
 807 }
 808
 809 static void gen6_ring_flush(struct drm_device *dev,
 810                             struct intel_ring_buffer *ring,
 811                             u32 invalidate_domains,
 812                             u32 flush_domains)
 813 {
 814        intel_ring_begin(dev, ring, 4);
 815        intel_ring_emit(dev, ring, MI_FLUSH_DW);
 816        intel_ring_emit(dev, ring, 0);
 817        intel_ring_emit(dev, ring, 0);
 818        intel_ring_emit(dev, ring, 0);
 819        intel_ring_advance(dev, ring);
 820 }
 821
 822 static int
 823 gen6_ring_dispatch_gem_execbuffer(struct drm_device *dev,
 824                                   struct intel_ring_buffer *ring,
 825                                   struct drm_i915_gem_execbuffer2 *exec,
 826                                   struct drm_clip_rect *cliprects,
 827                                   uint64_t exec_offset)
 828 {
 829        uint32_t exec_start;
 830
 831        exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
 832
 833        intel_ring_begin(dev, ring, 2);
 834        intel_ring_emit(dev, ring,
 835                        MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
 836        /* bit0-7 is the length on GEN6+ */
 837        intel_ring_emit(dev, ring, exec_start);
 838        intel_ring_advance(dev, ring);
 839
 840        return 0;
 841 }
 842
 843 /* ring buffer for Video Codec for Gen6+ */
 844 static const struct intel_ring_buffer gen6_bsd_ring = {
 845        .name                    = "gen6 bsd ring",
 846        .id                      = RING_BSD,
 847        .mmio_base               = GEN6_BSD_RING_BASE,
 848        .size                    = 32 * PAGE_SIZE,
 849        .init                    = init_bsd_ring,
 850        .write_tail              = gen6_bsd_ring_write_tail,
 851        .flush                   = gen6_ring_flush,
 852        .add_request             = ring_add_request,
 853        .get_seqno               = ring_status_page_get_seqno,
 854        .user_irq_get            = bsd_ring_get_user_irq,
 855        .user_irq_put            = bsd_ring_put_user_irq,
 856        .dispatch_gem_execbuffer = gen6_ring_dispatch_gem_execbuffer,
 857 };
 858
 859 /* Blitter support (SandyBridge+) */
 860
 861 static void
 862 blt_ring_get_user_irq(struct drm_device *dev,
 863                       struct intel_ring_buffer *ring)
 864 {
 865         /* do nothing */
 866 }
 867 static void
 868 blt_ring_put_user_irq(struct drm_device *dev,
 869                       struct intel_ring_buffer *ring)
 870 {
 871         /* do nothing */
 872 }
 873
 874
 875 /* Workaround for some stepping of SNB,
 876  * each time when BLT engine ring tail moved,
 877  * the first command in the ring to be parsed
 878  * should be MI_BATCH_BUFFER_START
 879  */
 880 #define NEED_BLT_WORKAROUND(dev) \
 881         (IS_GEN6(dev) && (dev->pdev->revision < 8))
 882
 883 static inline struct drm_i915_gem_object *
 884 to_blt_workaround(struct intel_ring_buffer *ring)
 885 {
 886         return ring->private;
 887 }
 888
 889 static int blt_ring_init(struct drm_device *dev,
 890                          struct intel_ring_buffer *ring)
 891 {
 892         if (NEED_BLT_WORKAROUND(dev)) {
 893                 struct drm_i915_gem_object *obj;
 894                 u32 __iomem *ptr;
 895                 int ret;
 896
 897                 obj = to_intel_bo(i915_gem_alloc_object(dev, 4096));
 898                 if (obj == NULL)
 899                         return -ENOMEM;
 900
 901                 ret = i915_gem_object_pin(&obj->base, 4096);
 902                 if (ret) {
 903                         drm_gem_object_unreference(&obj->base);
 904                         return ret;
 905                 }
 906
 907                 ptr = kmap(obj->pages[0]);
 908                 iowrite32(MI_BATCH_BUFFER_END, ptr);
 909                 iowrite32(MI_NOOP, ptr+1);
 910                 kunmap(obj->pages[0]);
 911
 912                 ret = i915_gem_object_set_to_gtt_domain(&obj->base, false);
 913                 if (ret) {
 914                         i915_gem_object_unpin(&obj->base);
 915                         drm_gem_object_unreference(&obj->base);
 916                         return ret;
 917                 }
 918
 919                 ring->private = obj;
 920         }
 921
 922         return init_ring_common(dev, ring);
 923 }
 924
 925 static void blt_ring_begin(struct drm_device *dev,
 926                            struct intel_ring_buffer *ring,
 927                           int num_dwords)
 928 {
 929         if (ring->private) {
 930                 intel_ring_begin(dev, ring, num_dwords+2);
 931                 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START);
 932                 intel_ring_emit(dev, ring, to_blt_workaround(ring)->gtt_offset);
 933         } else
 934                 intel_ring_begin(dev, ring, 4);
 935 }
 936
 937 static void blt_ring_flush(struct drm_device *dev,
 938                            struct intel_ring_buffer *ring,
 939                            u32 invalidate_domains,
 940                            u32 flush_domains)
 941 {
 942         blt_ring_begin(dev, ring, 4);
 943         intel_ring_emit(dev, ring, MI_FLUSH_DW);
 944         intel_ring_emit(dev, ring, 0);
 945         intel_ring_emit(dev, ring, 0);
 946         intel_ring_emit(dev, ring, 0);
 947         intel_ring_advance(dev, ring);
 948 }
 949
 950 static u32
 951 blt_ring_add_request(struct drm_device *dev,
 952                      struct intel_ring_buffer *ring,
 953                      u32 flush_domains)
 954 {
 955         u32 seqno = i915_gem_get_seqno(dev);
 956
 957         blt_ring_begin(dev, ring, 4);
 958         intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX);
 959         intel_ring_emit(dev, ring,
 960                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 961         intel_ring_emit(dev, ring, seqno);
 962         intel_ring_emit(dev, ring, MI_USER_INTERRUPT);
 963         intel_ring_advance(dev, ring);
 964
 965         DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
 966         return seqno;
 967 }
 968
 969 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
 970 {
 971         if (!ring->private)
 972                 return;
 973
 974         i915_gem_object_unpin(ring->private);
 975         drm_gem_object_unreference(ring->private);
 976         ring->private = NULL;
 977 }
 978
 979 static const struct intel_ring_buffer gen6_blt_ring = {
 980        .name                    = "blt ring",
 981        .id                      = RING_BLT,
 982        .mmio_base               = BLT_RING_BASE,
 983        .size                    = 32 * PAGE_SIZE,
 984        .init                    = blt_ring_init,
 985        .write_tail              = ring_write_tail,
 986        .flush                   = blt_ring_flush,
 987        .add_request             = blt_ring_add_request,
 988        .get_seqno               = ring_status_page_get_seqno,
 989        .user_irq_get            = blt_ring_get_user_irq,
 990        .user_irq_put            = blt_ring_put_user_irq,
 991        .dispatch_gem_execbuffer = gen6_ring_dispatch_gem_execbuffer,
 992        .cleanup                 = blt_ring_cleanup,
 993 };
 994
 995 int intel_init_render_ring_buffer(struct drm_device *dev)
 996 {
 997         drm_i915_private_t *dev_priv = dev->dev_private;
 998
 999         dev_priv->render_ring = render_ring;
1000
1001         if (!I915_NEED_GFX_HWS(dev)) {
1002                 dev_priv->render_ring.status_page.page_addr
1003                         = dev_priv->status_page_dmah->vaddr;
1004                 memset(dev_priv->render_ring.status_page.page_addr,
1005                                 0, PAGE_SIZE);
1006         }
1007
1008         return intel_init_ring_buffer(dev, &dev_priv->render_ring);
1009 }
1010
1011 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1012 {
1013         drm_i915_private_t *dev_priv = dev->dev_private;
1014
1015         if (IS_GEN6(dev))
1016                 dev_priv->bsd_ring = gen6_bsd_ring;
1017         else
1018                 dev_priv->bsd_ring = bsd_ring;
1019
1020         return intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
1021 }
1022
1023 int intel_init_blt_ring_buffer(struct drm_device *dev)
1024 {
1025         drm_i915_private_t *dev_priv = dev->dev_private;
1026
1027         dev_priv->blt_ring = gen6_blt_ring;
1028
1029         return intel_init_ring_buffer(dev, &dev_priv->blt_ring);
1030 }