drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
  37  * but keeps the logic simple. Indeed, the whole purpose of this macro is just
  38  * to give some inclination as to some of the magic values used in the various
  39  * workarounds!
  40  */
  41 #define CACHELINE_BYTES 64
  42
  43 static inline int ring_space(struct intel_ring_buffer *ring)
  44 {
  45         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  46         if (space < 0)
  47                 space += ring->size;
  48         return space;
  49 }
  50
  51 static bool intel_ring_stopped(struct intel_ring_buffer *ring)
  52 {
  53         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  54         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  55 }
  56
  57 void __intel_ring_advance(struct intel_ring_buffer *ring)
  58 {
  59         ring->tail &= ring->size - 1;
  60         if (intel_ring_stopped(ring))
  61                 return;
  62         ring->write_tail(ring, ring->tail);
  63 }
  64
  65 static int
  66 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  67                        u32      invalidate_domains,
  68                        u32      flush_domains)
  69 {
  70         u32 cmd;
  71         int ret;
  72
  73         cmd = MI_FLUSH;
  74         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  75                 cmd |= MI_NO_WRITE_FLUSH;
  76
  77         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  78                 cmd |= MI_READ_FLUSH;
  79
  80         ret = intel_ring_begin(ring, 2);
  81         if (ret)
  82                 return ret;
  83
  84         intel_ring_emit(ring, cmd);
  85         intel_ring_emit(ring, MI_NOOP);
  86         intel_ring_advance(ring);
  87
  88         return 0;
  89 }
  90
  91 static int
  92 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  93                        u32      invalidate_domains,
  94                        u32      flush_domains)
  95 {
  96         struct drm_device *dev = ring->dev;
  97         u32 cmd;
  98         int ret;
  99
 100         /*
 101          * read/write caches:
 102          *
 103          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 104          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 105          * also flushed at 2d versus 3d pipeline switches.
 106          *
 107          * read-only caches:
 108          *
 109          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 110          * MI_READ_FLUSH is set, and is always flushed on 965.
 111          *
 112          * I915_GEM_DOMAIN_COMMAND may not exist?
 113          *
 114          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 115          * invalidated when MI_EXE_FLUSH is set.
 116          *
 117          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 118          * invalidated with every MI_FLUSH.
 119          *
 120          * TLBs:
 121          *
 122          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 123          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 124          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 125          * are flushed at any MI_FLUSH.
 126          */
 127
 128         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 129         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 130                 cmd &= ~MI_NO_WRITE_FLUSH;
 131         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 132                 cmd |= MI_EXE_FLUSH;
 133
 134         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 135             (IS_G4X(dev) || IS_GEN5(dev)))
 136                 cmd |= MI_INVALIDATE_ISP;
 137
 138         ret = intel_ring_begin(ring, 2);
 139         if (ret)
 140                 return ret;
 141
 142         intel_ring_emit(ring, cmd);
 143         intel_ring_emit(ring, MI_NOOP);
 144         intel_ring_advance(ring);
 145
 146         return 0;
 147 }
 148
 149 /**
 150  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 151  * implementing two workarounds on gen6.  From section 1.4.7.1
 152  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 153  *
 154  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 155  * produced by non-pipelined state commands), software needs to first
 156  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 157  * 0.
 158  *
 159  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 160  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 161  *
 162  * And the workaround for these two requires this workaround first:
 163  *
 164  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 165  * BEFORE the pipe-control with a post-sync op and no write-cache
 166  * flushes.
 167  *
 168  * And this last workaround is tricky because of the requirements on
 169  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 170  * volume 2 part 1:
 171  *
 172  *     "1 of the following must also be set:
 173  *      - Render Target Cache Flush Enable ([12] of DW1)
 174  *      - Depth Cache Flush Enable ([0] of DW1)
 175  *      - Stall at Pixel Scoreboard ([1] of DW1)
 176  *      - Depth Stall ([13] of DW1)
 177  *      - Post-Sync Operation ([13] of DW1)
 178  *      - Notify Enable ([8] of DW1)"
 179  *
 180  * The cache flushes require the workaround flush that triggered this
 181  * one, so we can't use it.  Depth stall would trigger the same.
 182  * Post-sync nonzero is what triggered this second workaround, so we
 183  * can't use that one either.  Notify enable is IRQs, which aren't
 184  * really our business.  That leaves only stall at scoreboard.
 185  */
 186 static int
 187 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 188 {
 189         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 190         int ret;
 191
 192
 193         ret = intel_ring_begin(ring, 6);
 194         if (ret)
 195                 return ret;
 196
 197         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 198         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 199                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 200         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 201         intel_ring_emit(ring, 0); /* low dword */
 202         intel_ring_emit(ring, 0); /* high dword */
 203         intel_ring_emit(ring, MI_NOOP);
 204         intel_ring_advance(ring);
 205
 206         ret = intel_ring_begin(ring, 6);
 207         if (ret)
 208                 return ret;
 209
 210         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 211         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 212         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 213         intel_ring_emit(ring, 0);
 214         intel_ring_emit(ring, 0);
 215         intel_ring_emit(ring, MI_NOOP);
 216         intel_ring_advance(ring);
 217
 218         return 0;
 219 }
 220
 221 static int
 222 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 223                          u32 invalidate_domains, u32 flush_domains)
 224 {
 225         u32 flags = 0;
 226         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 227         int ret;
 228
 229         /* Force SNB workarounds for PIPE_CONTROL flushes */
 230         ret = intel_emit_post_sync_nonzero_flush(ring);
 231         if (ret)
 232                 return ret;
 233
 234         /* Just flush everything.  Experiments have shown that reducing the
 235          * number of bits based on the write domains has little performance
 236          * impact.
 237          */
 238         if (flush_domains) {
 239                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 240                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 241                 /*
 242                  * Ensure that any following seqno writes only happen
 243                  * when the render cache is indeed flushed.
 244                  */
 245                 flags |= PIPE_CONTROL_CS_STALL;
 246         }
 247         if (invalidate_domains) {
 248                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 249                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 250                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 251                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 252                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 253                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 254                 /*
 255                  * TLB invalidate requires a post-sync write.
 256                  */
 257                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 258         }
 259
 260         ret = intel_ring_begin(ring, 4);
 261         if (ret)
 262                 return ret;
 263
 264         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 265         intel_ring_emit(ring, flags);
 266         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 267         intel_ring_emit(ring, 0);
 268         intel_ring_advance(ring);
 269
 270         return 0;
 271 }
 272
 273 static int
 274 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 275 {
 276         int ret;
 277
 278         ret = intel_ring_begin(ring, 4);
 279         if (ret)
 280                 return ret;
 281
 282         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 283         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 284                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 285         intel_ring_emit(ring, 0);
 286         intel_ring_emit(ring, 0);
 287         intel_ring_advance(ring);
 288
 289         return 0;
 290 }
 291
 292 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 293 {
 294         int ret;
 295
 296         if (!ring->fbc_dirty)
 297                 return 0;
 298
 299         ret = intel_ring_begin(ring, 6);
 300         if (ret)
 301                 return ret;
 302         /* WaFbcNukeOn3DBlt:ivb/hsw */
 303         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 304         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 305         intel_ring_emit(ring, value);
 306         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 307         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 308         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 309         intel_ring_advance(ring);
 310
 311         ring->fbc_dirty = false;
 312         return 0;
 313 }
 314
 315 static int
 316 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 317                        u32 invalidate_domains, u32 flush_domains)
 318 {
 319         u32 flags = 0;
 320         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 321         int ret;
 322
 323         /*
 324          * Ensure that any following seqno writes only happen when the render
 325          * cache is indeed flushed.
 326          *
 327          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 328          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 329          * don't try to be clever and just set it unconditionally.
 330          */
 331         flags |= PIPE_CONTROL_CS_STALL;
 332
 333         /* Just flush everything.  Experiments have shown that reducing the
 334          * number of bits based on the write domains has little performance
 335          * impact.
 336          */
 337         if (flush_domains) {
 338                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 339                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 340         }
 341         if (invalidate_domains) {
 342                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 343                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 344                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 345                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 346                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 347                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 348                 /*
 349                  * TLB invalidate requires a post-sync write.
 350                  */
 351                 flags |= PIPE_CONTROL_QW_WRITE;
 352                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 353
 354                 /* Workaround: we must issue a pipe_control with CS-stall bit
 355                  * set before a pipe_control command that has the state cache
 356                  * invalidate bit set. */
 357                 gen7_render_ring_cs_stall_wa(ring);
 358         }
 359
 360         ret = intel_ring_begin(ring, 4);
 361         if (ret)
 362                 return ret;
 363
 364         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 365         intel_ring_emit(ring, flags);
 366         intel_ring_emit(ring, scratch_addr);
 367         intel_ring_emit(ring, 0);
 368         intel_ring_advance(ring);
 369
 370         if (!invalidate_domains && flush_domains)
 371                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 372
 373         return 0;
 374 }
 375
 376 static int
 377 gen8_render_ring_flush(struct intel_ring_buffer *ring,
 378                        u32 invalidate_domains, u32 flush_domains)
 379 {
 380         u32 flags = 0;
 381         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 382         int ret;
 383
 384         flags |= PIPE_CONTROL_CS_STALL;
 385
 386         if (flush_domains) {
 387                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 388                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 389         }
 390         if (invalidate_domains) {
 391                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 392                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 393                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 394                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 395                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 396                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 397                 flags |= PIPE_CONTROL_QW_WRITE;
 398                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 399         }
 400
 401         ret = intel_ring_begin(ring, 6);
 402         if (ret)
 403                 return ret;
 404
 405         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 406         intel_ring_emit(ring, flags);
 407         intel_ring_emit(ring, scratch_addr);
 408         intel_ring_emit(ring, 0);
 409         intel_ring_emit(ring, 0);
 410         intel_ring_emit(ring, 0);
 411         intel_ring_advance(ring);
 412
 413         return 0;
 414
 415 }
 416
 417 static void ring_write_tail(struct intel_ring_buffer *ring,
 418                             u32 value)
 419 {
 420         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 421         I915_WRITE_TAIL(ring, value);
 422 }
 423
 424 u64 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 425 {
 426         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 427         u64 acthd;
 428
 429         if (INTEL_INFO(ring->dev)->gen >= 8)
 430                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 431                                          RING_ACTHD_UDW(ring->mmio_base));
 432         else if (INTEL_INFO(ring->dev)->gen >= 4)
 433                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 434         else
 435                 acthd = I915_READ(ACTHD);
 436
 437         return acthd;
 438 }
 439
 440 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
 441 {
 442         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 443         u32 addr;
 444
 445         addr = dev_priv->status_page_dmah->busaddr;
 446         if (INTEL_INFO(ring->dev)->gen >= 4)
 447                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 448         I915_WRITE(HWS_PGA, addr);
 449 }
 450
 451 static bool stop_ring(struct intel_ring_buffer *ring)
 452 {
 453         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 454
 455         if (!IS_GEN2(ring->dev)) {
 456                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 457                 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 458                         DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 459                         return false;
 460                 }
 461         }
 462
 463         I915_WRITE_CTL(ring, 0);
 464         I915_WRITE_HEAD(ring, 0);
 465         ring->write_tail(ring, 0);
 466
 467         if (!IS_GEN2(ring->dev)) {
 468                 (void)I915_READ_CTL(ring);
 469                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 470         }
 471
 472         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 473 }
 474
 475 static int init_ring_common(struct intel_ring_buffer *ring)
 476 {
 477         struct drm_device *dev = ring->dev;
 478         struct drm_i915_private *dev_priv = dev->dev_private;
 479         struct drm_i915_gem_object *obj = ring->obj;
 480         int ret = 0;
 481
 482         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 483
 484         if (!stop_ring(ring)) {
 485                 /* G45 ring initialization often fails to reset head to zero */
 486                 DRM_DEBUG_KMS("%s head not reset to zero "
 487                               "ctl %08x head %08x tail %08x start %08x\n",
 488                               ring->name,
 489                               I915_READ_CTL(ring),
 490                               I915_READ_HEAD(ring),
 491                               I915_READ_TAIL(ring),
 492                               I915_READ_START(ring));
 493
 494                 if (!stop_ring(ring)) {
 495                         DRM_ERROR("failed to set %s head to zero "
 496                                   "ctl %08x head %08x tail %08x start %08x\n",
 497                                   ring->name,
 498                                   I915_READ_CTL(ring),
 499                                   I915_READ_HEAD(ring),
 500                                   I915_READ_TAIL(ring),
 501                                   I915_READ_START(ring));
 502                         ret = -EIO;
 503                         goto out;
 504                 }
 505         }
 506
 507         if (I915_NEED_GFX_HWS(dev))
 508                 intel_ring_setup_status_page(ring);
 509         else
 510                 ring_setup_phys_status_page(ring);
 511
 512         /* Initialize the ring. This must happen _after_ we've cleared the ring
 513          * registers with the above sequence (the readback of the HEAD registers
 514          * also enforces ordering), otherwise the hw might lose the new ring
 515          * register values. */
 516         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 517         I915_WRITE_CTL(ring,
 518                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 519                         | RING_VALID);
 520
 521         /* If the head is still not zero, the ring is dead */
 522         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 523                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 524                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 525                 DRM_ERROR("%s initialization failed "
 526                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 527                           ring->name,
 528                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 529                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 530                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 531                 ret = -EIO;
 532                 goto out;
 533         }
 534
 535         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 536                 i915_kernel_lost_context(ring->dev);
 537         else {
 538                 ring->head = I915_READ_HEAD(ring);
 539                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 540                 ring->space = ring_space(ring);
 541                 ring->last_retired_head = -1;
 542         }
 543
 544         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 545
 546 out:
 547         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 548
 549         return ret;
 550 }
 551
 552 static int
 553 init_pipe_control(struct intel_ring_buffer *ring)
 554 {
 555         int ret;
 556
 557         if (ring->scratch.obj)
 558                 return 0;
 559
 560         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 561         if (ring->scratch.obj == NULL) {
 562                 DRM_ERROR("Failed to allocate seqno page\n");
 563                 ret = -ENOMEM;
 564                 goto err;
 565         }
 566
 567         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 568         if (ret)
 569                 goto err_unref;
 570
 571         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 572         if (ret)
 573                 goto err_unref;
 574
 575         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 576         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 577         if (ring->scratch.cpu_page == NULL) {
 578                 ret = -ENOMEM;
 579                 goto err_unpin;
 580         }
 581
 582         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 583                          ring->name, ring->scratch.gtt_offset);
 584         return 0;
 585
 586 err_unpin:
 587         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 588 err_unref:
 589         drm_gem_object_unreference(&ring->scratch.obj->base);
 590 err:
 591         return ret;
 592 }
 593
 594 static int init_render_ring(struct intel_ring_buffer *ring)
 595 {
 596         struct drm_device *dev = ring->dev;
 597         struct drm_i915_private *dev_priv = dev->dev_private;
 598         int ret = init_ring_common(ring);
 599
 600         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 601         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
 602                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 603
 604         /* We need to disable the AsyncFlip performance optimisations in order
 605          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 606          * programmed to '1' on all products.
 607          *
 608          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
 609          */
 610         if (INTEL_INFO(dev)->gen >= 6)
 611                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 612
 613         /* Required for the hardware to program scanline values for waiting */
 614         /* WaEnableFlushTlbInvalidationMode:snb */
 615         if (INTEL_INFO(dev)->gen == 6)
 616                 I915_WRITE(GFX_MODE,
 617                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 618
 619         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 620         if (IS_GEN7(dev))
 621                 I915_WRITE(GFX_MODE_GEN7,
 622                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 623                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 624
 625         if (INTEL_INFO(dev)->gen >= 5) {
 626                 ret = init_pipe_control(ring);
 627                 if (ret)
 628                         return ret;
 629         }
 630
 631         if (IS_GEN6(dev)) {
 632                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 633                  * "If this bit is set, STCunit will have LRA as replacement
 634                  *  policy. [...] This bit must be reset.  LRA replacement
 635                  *  policy is not supported."
 636                  */
 637                 I915_WRITE(CACHE_MODE_0,
 638                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 639         }
 640
 641         if (INTEL_INFO(dev)->gen >= 6)
 642                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 643
 644         if (HAS_L3_DPF(dev))
 645                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 646
 647         return ret;
 648 }
 649
 650 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 651 {
 652         struct drm_device *dev = ring->dev;
 653
 654         if (ring->scratch.obj == NULL)
 655                 return;
 656
 657         if (INTEL_INFO(dev)->gen >= 5) {
 658                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 659                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 660         }
 661
 662         drm_gem_object_unreference(&ring->scratch.obj->base);
 663         ring->scratch.obj = NULL;
 664 }
 665
 666 static void
 667 update_mboxes(struct intel_ring_buffer *ring,
 668               u32 mmio_offset)
 669 {
 670 /* NB: In order to be able to do semaphore MBOX updates for varying number
 671  * of rings, it's easiest if we round up each individual update to a
 672  * multiple of 2 (since ring updates must always be a multiple of 2)
 673  * even though the actual update only requires 3 dwords.
 674  */
 675 #define MBOX_UPDATE_DWORDS 4
 676         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 677         intel_ring_emit(ring, mmio_offset);
 678         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 679         intel_ring_emit(ring, MI_NOOP);
 680 }
 681
 682 /**
 683  * gen6_add_request - Update the semaphore mailbox registers
 684  *
 685  * @ring - ring that is adding a request
 686  * @seqno - return seqno stuck into the ring
 687  *
 688  * Update the mailbox registers in the *other* rings with the current seqno.
 689  * This acts like a signal in the canonical semaphore.
 690  */
 691 static int
 692 gen6_add_request(struct intel_ring_buffer *ring)
 693 {
 694         struct drm_device *dev = ring->dev;
 695         struct drm_i915_private *dev_priv = dev->dev_private;
 696         struct intel_ring_buffer *useless;
 697         int i, ret, num_dwords = 4;
 698
 699         if (i915_semaphore_is_enabled(dev))
 700                 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
 701 #undef MBOX_UPDATE_DWORDS
 702
 703         ret = intel_ring_begin(ring, num_dwords);
 704         if (ret)
 705                 return ret;
 706
 707         if (i915_semaphore_is_enabled(dev)) {
 708                 for_each_ring(useless, dev_priv, i) {
 709                         u32 mbox_reg = ring->signal_mbox[i];
 710                         if (mbox_reg != GEN6_NOSYNC)
 711                                 update_mboxes(ring, mbox_reg);
 712                 }
 713         }
 714
 715         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 716         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 717         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 718         intel_ring_emit(ring, MI_USER_INTERRUPT);
 719         __intel_ring_advance(ring);
 720
 721         return 0;
 722 }
 723
 724 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 725                                               u32 seqno)
 726 {
 727         struct drm_i915_private *dev_priv = dev->dev_private;
 728         return dev_priv->last_seqno < seqno;
 729 }
 730
 731 /**
 732  * intel_ring_sync - sync the waiter to the signaller on seqno
 733  *
 734  * @waiter - ring that is waiting
 735  * @signaller - ring which has, or will signal
 736  * @seqno - seqno which the waiter will block on
 737  */
 738 static int
 739 gen6_ring_sync(struct intel_ring_buffer *waiter,
 740                struct intel_ring_buffer *signaller,
 741                u32 seqno)
 742 {
 743         int ret;
 744         u32 dw1 = MI_SEMAPHORE_MBOX |
 745                   MI_SEMAPHORE_COMPARE |
 746                   MI_SEMAPHORE_REGISTER;
 747
 748         /* Throughout all of the GEM code, seqno passed implies our current
 749          * seqno is >= the last seqno executed. However for hardware the
 750          * comparison is strictly greater than.
 751          */
 752         seqno -= 1;
 753
 754         WARN_ON(signaller->semaphore_register[waiter->id] ==
 755                 MI_SEMAPHORE_SYNC_INVALID);
 756
 757         ret = intel_ring_begin(waiter, 4);
 758         if (ret)
 759                 return ret;
 760
 761         /* If seqno wrap happened, omit the wait with no-ops */
 762         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 763                 intel_ring_emit(waiter,
 764                                 dw1 |
 765                                 signaller->semaphore_register[waiter->id]);
 766                 intel_ring_emit(waiter, seqno);
 767                 intel_ring_emit(waiter, 0);
 768                 intel_ring_emit(waiter, MI_NOOP);
 769         } else {
 770                 intel_ring_emit(waiter, MI_NOOP);
 771                 intel_ring_emit(waiter, MI_NOOP);
 772                 intel_ring_emit(waiter, MI_NOOP);
 773                 intel_ring_emit(waiter, MI_NOOP);
 774         }
 775         intel_ring_advance(waiter);
 776
 777         return 0;
 778 }
 779
 780 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 781 do {                                                                    \
 782         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 783                  PIPE_CONTROL_DEPTH_STALL);                             \
 784         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 785         intel_ring_emit(ring__, 0);                                                     \
 786         intel_ring_emit(ring__, 0);                                                     \
 787 } while (0)
 788
 789 static int
 790 pc_render_add_request(struct intel_ring_buffer *ring)
 791 {
 792         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 793         int ret;
 794
 795         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 796          * incoherent with writes to memory, i.e. completely fubar,
 797          * so we need to use PIPE_NOTIFY instead.
 798          *
 799          * However, we also need to workaround the qword write
 800          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 801          * memory before requesting an interrupt.
 802          */
 803         ret = intel_ring_begin(ring, 32);
 804         if (ret)
 805                 return ret;
 806
 807         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 808                         PIPE_CONTROL_WRITE_FLUSH |
 809                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 810         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 811         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 812         intel_ring_emit(ring, 0);
 813         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 814         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
 815         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 816         scratch_addr += 2 * CACHELINE_BYTES;
 817         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 818         scratch_addr += 2 * CACHELINE_BYTES;
 819         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 820         scratch_addr += 2 * CACHELINE_BYTES;
 821         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 822         scratch_addr += 2 * CACHELINE_BYTES;
 823         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 824
 825         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 826                         PIPE_CONTROL_WRITE_FLUSH |
 827                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 828                         PIPE_CONTROL_NOTIFY);
 829         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 830         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 831         intel_ring_emit(ring, 0);
 832         __intel_ring_advance(ring);
 833
 834         return 0;
 835 }
 836
 837 static u32
 838 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 839 {
 840         /* Workaround to force correct ordering between irq and seqno writes on
 841          * ivb (and maybe also on snb) by reading from a CS register (like
 842          * ACTHD) before reading the status page. */
 843         if (!lazy_coherency) {
 844                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
 845                 POSTING_READ(RING_ACTHD(ring->mmio_base));
 846         }
 847
 848         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 849 }
 850
 851 static u32
 852 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 853 {
 854         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 855 }
 856
 857 static void
 858 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 859 {
 860         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 861 }
 862
 863 static u32
 864 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 865 {
 866         return ring->scratch.cpu_page[0];
 867 }
 868
 869 static void
 870 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 871 {
 872         ring->scratch.cpu_page[0] = seqno;
 873 }
 874
 875 static bool
 876 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 877 {
 878         struct drm_device *dev = ring->dev;
 879         struct drm_i915_private *dev_priv = dev->dev_private;
 880         unsigned long flags;
 881
 882         if (!dev->irq_enabled)
 883                 return false;
 884
 885         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 886         if (ring->irq_refcount++ == 0)
 887                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
 888         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 889
 890         return true;
 891 }
 892
 893 static void
 894 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 895 {
 896         struct drm_device *dev = ring->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898         unsigned long flags;
 899
 900         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 901         if (--ring->irq_refcount == 0)
 902                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
 903         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 904 }
 905
 906 static bool
 907 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 908 {
 909         struct drm_device *dev = ring->dev;
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911         unsigned long flags;
 912
 913         if (!dev->irq_enabled)
 914                 return false;
 915
 916         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 917         if (ring->irq_refcount++ == 0) {
 918                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 919                 I915_WRITE(IMR, dev_priv->irq_mask);
 920                 POSTING_READ(IMR);
 921         }
 922         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 923
 924         return true;
 925 }
 926
 927 static void
 928 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 929 {
 930         struct drm_device *dev = ring->dev;
 931         struct drm_i915_private *dev_priv = dev->dev_private;
 932         unsigned long flags;
 933
 934         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 935         if (--ring->irq_refcount == 0) {
 936                 dev_priv->irq_mask |= ring->irq_enable_mask;
 937                 I915_WRITE(IMR, dev_priv->irq_mask);
 938                 POSTING_READ(IMR);
 939         }
 940         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 941 }
 942
 943 static bool
 944 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 945 {
 946         struct drm_device *dev = ring->dev;
 947         struct drm_i915_private *dev_priv = dev->dev_private;
 948         unsigned long flags;
 949
 950         if (!dev->irq_enabled)
 951                 return false;
 952
 953         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 954         if (ring->irq_refcount++ == 0) {
 955                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 956                 I915_WRITE16(IMR, dev_priv->irq_mask);
 957                 POSTING_READ16(IMR);
 958         }
 959         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 960
 961         return true;
 962 }
 963
 964 static void
 965 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 966 {
 967         struct drm_device *dev = ring->dev;
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969         unsigned long flags;
 970
 971         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 972         if (--ring->irq_refcount == 0) {
 973                 dev_priv->irq_mask |= ring->irq_enable_mask;
 974                 I915_WRITE16(IMR, dev_priv->irq_mask);
 975                 POSTING_READ16(IMR);
 976         }
 977         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 978 }
 979
 980 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 981 {
 982         struct drm_device *dev = ring->dev;
 983         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 984         u32 mmio = 0;
 985
 986         /* The ring status page addresses are no longer next to the rest of
 987          * the ring registers as of gen7.
 988          */
 989         if (IS_GEN7(dev)) {
 990                 switch (ring->id) {
 991                 case RCS:
 992                         mmio = RENDER_HWS_PGA_GEN7;
 993                         break;
 994                 case BCS:
 995                         mmio = BLT_HWS_PGA_GEN7;
 996                         break;
 997                 /*
 998                  * VCS2 actually doesn't exist on Gen7. Only shut up
 999                  * gcc switch check warning
1000                  */
1001                 case VCS2:
1002                 case VCS:
1003                         mmio = BSD_HWS_PGA_GEN7;
1004                         break;
1005                 case VECS:
1006                         mmio = VEBOX_HWS_PGA_GEN7;
1007                         break;
1008                 }
1009         } else if (IS_GEN6(ring->dev)) {
1010                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1011         } else {
1012                 /* XXX: gen8 returns to sanity */
1013                 mmio = RING_HWS_PGA(ring->mmio_base);
1014         }
1015
1016         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1017         POSTING_READ(mmio);
1018
1019         /*
1020          * Flush the TLB for this page
1021          *
1022          * FIXME: These two bits have disappeared on gen8, so a question
1023          * arises: do we still need this and if so how should we go about
1024          * invalidating the TLB?
1025          */
1026         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1027                 u32 reg = RING_INSTPM(ring->mmio_base);
1028
1029                 /* ring should be idle before issuing a sync flush*/
1030                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1031
1032                 I915_WRITE(reg,
1033                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1034                                               INSTPM_SYNC_FLUSH));
1035                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1036                              1000))
1037                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1038                                   ring->name);
1039         }
1040 }
1041
1042 static int
1043 bsd_ring_flush(struct intel_ring_buffer *ring,
1044                u32     invalidate_domains,
1045                u32     flush_domains)
1046 {
1047         int ret;
1048
1049         ret = intel_ring_begin(ring, 2);
1050         if (ret)
1051                 return ret;
1052
1053         intel_ring_emit(ring, MI_FLUSH);
1054         intel_ring_emit(ring, MI_NOOP);
1055         intel_ring_advance(ring);
1056         return 0;
1057 }
1058
1059 static int
1060 i9xx_add_request(struct intel_ring_buffer *ring)
1061 {
1062         int ret;
1063
1064         ret = intel_ring_begin(ring, 4);
1065         if (ret)
1066                 return ret;
1067
1068         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1069         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1070         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1071         intel_ring_emit(ring, MI_USER_INTERRUPT);
1072         __intel_ring_advance(ring);
1073
1074         return 0;
1075 }
1076
1077 static bool
1078 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1079 {
1080         struct drm_device *dev = ring->dev;
1081         struct drm_i915_private *dev_priv = dev->dev_private;
1082         unsigned long flags;
1083
1084         if (!dev->irq_enabled)
1085                return false;
1086
1087         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1088         if (ring->irq_refcount++ == 0) {
1089                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1090                         I915_WRITE_IMR(ring,
1091                                        ~(ring->irq_enable_mask |
1092                                          GT_PARITY_ERROR(dev)));
1093                 else
1094                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1095                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1096         }
1097         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1098
1099         return true;
1100 }
1101
1102 static void
1103 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1104 {
1105         struct drm_device *dev = ring->dev;
1106         struct drm_i915_private *dev_priv = dev->dev_private;
1107         unsigned long flags;
1108
1109         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1110         if (--ring->irq_refcount == 0) {
1111                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1112                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1113                 else
1114                         I915_WRITE_IMR(ring, ~0);
1115                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1116         }
1117         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1118 }
1119
1120 static bool
1121 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1122 {
1123         struct drm_device *dev = ring->dev;
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125         unsigned long flags;
1126
1127         if (!dev->irq_enabled)
1128                 return false;
1129
1130         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1131         if (ring->irq_refcount++ == 0) {
1132                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1133                 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1134         }
1135         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1136
1137         return true;
1138 }
1139
1140 static void
1141 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1142 {
1143         struct drm_device *dev = ring->dev;
1144         struct drm_i915_private *dev_priv = dev->dev_private;
1145         unsigned long flags;
1146
1147         if (!dev->irq_enabled)
1148                 return;
1149
1150         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1151         if (--ring->irq_refcount == 0) {
1152                 I915_WRITE_IMR(ring, ~0);
1153                 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1154         }
1155         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1156 }
1157
1158 static bool
1159 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1160 {
1161         struct drm_device *dev = ring->dev;
1162         struct drm_i915_private *dev_priv = dev->dev_private;
1163         unsigned long flags;
1164
1165         if (!dev->irq_enabled)
1166                 return false;
1167
1168         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1169         if (ring->irq_refcount++ == 0) {
1170                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1171                         I915_WRITE_IMR(ring,
1172                                        ~(ring->irq_enable_mask |
1173                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1174                 } else {
1175                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1176                 }
1177                 POSTING_READ(RING_IMR(ring->mmio_base));
1178         }
1179         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1180
1181         return true;
1182 }
1183
1184 static void
1185 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1186 {
1187         struct drm_device *dev = ring->dev;
1188         struct drm_i915_private *dev_priv = dev->dev_private;
1189         unsigned long flags;
1190
1191         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1192         if (--ring->irq_refcount == 0) {
1193                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1194                         I915_WRITE_IMR(ring,
1195                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1196                 } else {
1197                         I915_WRITE_IMR(ring, ~0);
1198                 }
1199                 POSTING_READ(RING_IMR(ring->mmio_base));
1200         }
1201         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1202 }
1203
1204 static int
1205 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1206                          u32 offset, u32 length,
1207                          unsigned flags)
1208 {
1209         int ret;
1210
1211         ret = intel_ring_begin(ring, 2);
1212         if (ret)
1213                 return ret;
1214
1215         intel_ring_emit(ring,
1216                         MI_BATCH_BUFFER_START |
1217                         MI_BATCH_GTT |
1218                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1219         intel_ring_emit(ring, offset);
1220         intel_ring_advance(ring);
1221
1222         return 0;
1223 }
1224
1225 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1226 #define I830_BATCH_LIMIT (256*1024)
1227 static int
1228 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1229                                 u32 offset, u32 len,
1230                                 unsigned flags)
1231 {
1232         int ret;
1233
1234         if (flags & I915_DISPATCH_PINNED) {
1235                 ret = intel_ring_begin(ring, 4);
1236                 if (ret)
1237                         return ret;
1238
1239                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1240                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1241                 intel_ring_emit(ring, offset + len - 8);
1242                 intel_ring_emit(ring, MI_NOOP);
1243                 intel_ring_advance(ring);
1244         } else {
1245                 u32 cs_offset = ring->scratch.gtt_offset;
1246
1247                 if (len > I830_BATCH_LIMIT)
1248                         return -ENOSPC;
1249
1250                 ret = intel_ring_begin(ring, 9+3);
1251                 if (ret)
1252                         return ret;
1253                 /* Blit the batch (which has now all relocs applied) to the stable batch
1254                  * scratch bo area (so that the CS never stumbles over its tlb
1255                  * invalidation bug) ... */
1256                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1257                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1258                                 XY_SRC_COPY_BLT_WRITE_RGB);
1259                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1260                 intel_ring_emit(ring, 0);
1261                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1262                 intel_ring_emit(ring, cs_offset);
1263                 intel_ring_emit(ring, 0);
1264                 intel_ring_emit(ring, 4096);
1265                 intel_ring_emit(ring, offset);
1266                 intel_ring_emit(ring, MI_FLUSH);
1267
1268                 /* ... and execute it. */
1269                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1270                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1271                 intel_ring_emit(ring, cs_offset + len - 8);
1272                 intel_ring_advance(ring);
1273         }
1274
1275         return 0;
1276 }
1277
1278 static int
1279 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1280                          u32 offset, u32 len,
1281                          unsigned flags)
1282 {
1283         int ret;
1284
1285         ret = intel_ring_begin(ring, 2);
1286         if (ret)
1287                 return ret;
1288
1289         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1290         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1291         intel_ring_advance(ring);
1292
1293         return 0;
1294 }
1295
1296 static void cleanup_status_page(struct intel_ring_buffer *ring)
1297 {
1298         struct drm_i915_gem_object *obj;
1299
1300         obj = ring->status_page.obj;
1301         if (obj == NULL)
1302                 return;
1303
1304         kunmap(sg_page(obj->pages->sgl));
1305         i915_gem_object_ggtt_unpin(obj);
1306         drm_gem_object_unreference(&obj->base);
1307         ring->status_page.obj = NULL;
1308 }
1309
1310 static int init_status_page(struct intel_ring_buffer *ring)
1311 {
1312         struct drm_i915_gem_object *obj;
1313
1314         if ((obj = ring->status_page.obj) == NULL) {
1315                 int ret;
1316
1317                 obj = i915_gem_alloc_object(ring->dev, 4096);
1318                 if (obj == NULL) {
1319                         DRM_ERROR("Failed to allocate status page\n");
1320                         return -ENOMEM;
1321                 }
1322
1323                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1324                 if (ret)
1325                         goto err_unref;
1326
1327                 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1328                 if (ret) {
1329 err_unref:
1330                         drm_gem_object_unreference(&obj->base);
1331                         return ret;
1332                 }
1333
1334                 ring->status_page.obj = obj;
1335         }
1336
1337         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1338         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1339         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1340
1341         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1342                         ring->name, ring->status_page.gfx_addr);
1343
1344         return 0;
1345 }
1346
1347 static int init_phys_status_page(struct intel_ring_buffer *ring)
1348 {
1349         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1350
1351         if (!dev_priv->status_page_dmah) {
1352                 dev_priv->status_page_dmah =
1353                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1354                 if (!dev_priv->status_page_dmah)
1355                         return -ENOMEM;
1356         }
1357
1358         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1359         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1360
1361         return 0;
1362 }
1363
1364 static int allocate_ring_buffer(struct intel_ring_buffer *ring)
1365 {
1366         struct drm_device *dev = ring->dev;
1367         struct drm_i915_private *dev_priv = to_i915(dev);
1368         struct drm_i915_gem_object *obj;
1369         int ret;
1370
1371         if (ring->obj)
1372                 return 0;
1373
1374         obj = NULL;
1375         if (!HAS_LLC(dev))
1376                 obj = i915_gem_object_create_stolen(dev, ring->size);
1377         if (obj == NULL)
1378                 obj = i915_gem_alloc_object(dev, ring->size);
1379         if (obj == NULL)
1380                 return -ENOMEM;
1381
1382         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1383         if (ret)
1384                 goto err_unref;
1385
1386         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1387         if (ret)
1388                 goto err_unpin;
1389
1390         ring->virtual_start =
1391                 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1392                            ring->size);
1393         if (ring->virtual_start == NULL) {
1394                 ret = -EINVAL;
1395                 goto err_unpin;
1396         }
1397
1398         ring->obj = obj;
1399         return 0;
1400
1401 err_unpin:
1402         i915_gem_object_ggtt_unpin(obj);
1403 err_unref:
1404         drm_gem_object_unreference(&obj->base);
1405         return ret;
1406 }
1407
1408 static int intel_init_ring_buffer(struct drm_device *dev,
1409                                   struct intel_ring_buffer *ring)
1410 {
1411         int ret;
1412
1413         ring->dev = dev;
1414         INIT_LIST_HEAD(&ring->active_list);
1415         INIT_LIST_HEAD(&ring->request_list);
1416         ring->size = 32 * PAGE_SIZE;
1417         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1418
1419         init_waitqueue_head(&ring->irq_queue);
1420
1421         if (I915_NEED_GFX_HWS(dev)) {
1422                 ret = init_status_page(ring);
1423                 if (ret)
1424                         return ret;
1425         } else {
1426                 BUG_ON(ring->id != RCS);
1427                 ret = init_phys_status_page(ring);
1428                 if (ret)
1429                         return ret;
1430         }
1431
1432         ret = allocate_ring_buffer(ring);
1433         if (ret) {
1434                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1435                 return ret;
1436         }
1437
1438         /* Workaround an erratum on the i830 which causes a hang if
1439          * the TAIL pointer points to within the last 2 cachelines
1440          * of the buffer.
1441          */
1442         ring->effective_size = ring->size;
1443         if (IS_I830(dev) || IS_845G(dev))
1444                 ring->effective_size -= 2 * CACHELINE_BYTES;
1445
1446         i915_cmd_parser_init_ring(ring);
1447
1448         return ring->init(ring);
1449 }
1450
1451 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1452 {
1453         struct drm_i915_private *dev_priv = to_i915(ring->dev);
1454
1455         if (ring->obj == NULL)
1456                 return;
1457
1458         intel_stop_ring_buffer(ring);
1459         WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1460
1461         iounmap(ring->virtual_start);
1462
1463         i915_gem_object_ggtt_unpin(ring->obj);
1464         drm_gem_object_unreference(&ring->obj->base);
1465         ring->obj = NULL;
1466         ring->preallocated_lazy_request = NULL;
1467         ring->outstanding_lazy_seqno = 0;
1468
1469         if (ring->cleanup)
1470                 ring->cleanup(ring);
1471
1472         cleanup_status_page(ring);
1473 }
1474
1475 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1476 {
1477         struct drm_i915_gem_request *request;
1478         u32 seqno = 0, tail;
1479         int ret;
1480
1481         if (ring->last_retired_head != -1) {
1482                 ring->head = ring->last_retired_head;
1483                 ring->last_retired_head = -1;
1484
1485                 ring->space = ring_space(ring);
1486                 if (ring->space >= n)
1487                         return 0;
1488         }
1489
1490         list_for_each_entry(request, &ring->request_list, list) {
1491                 int space;
1492
1493                 if (request->tail == -1)
1494                         continue;
1495
1496                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1497                 if (space < 0)
1498                         space += ring->size;
1499                 if (space >= n) {
1500                         seqno = request->seqno;
1501                         tail = request->tail;
1502                         break;
1503                 }
1504
1505                 /* Consume this request in case we need more space than
1506                  * is available and so need to prevent a race between
1507                  * updating last_retired_head and direct reads of
1508                  * I915_RING_HEAD. It also provides a nice sanity check.
1509                  */
1510                 request->tail = -1;
1511         }
1512
1513         if (seqno == 0)
1514                 return -ENOSPC;
1515
1516         ret = i915_wait_seqno(ring, seqno);
1517         if (ret)
1518                 return ret;
1519
1520         ring->head = tail;
1521         ring->space = ring_space(ring);
1522         if (WARN_ON(ring->space < n))
1523                 return -ENOSPC;
1524
1525         return 0;
1526 }
1527
1528 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1529 {
1530         struct drm_device *dev = ring->dev;
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         unsigned long end;
1533         int ret;
1534
1535         ret = intel_ring_wait_request(ring, n);
1536         if (ret != -ENOSPC)
1537                 return ret;
1538
1539         /* force the tail write in case we have been skipping them */
1540         __intel_ring_advance(ring);
1541
1542         trace_i915_ring_wait_begin(ring);
1543         /* With GEM the hangcheck timer should kick us out of the loop,
1544          * leaving it early runs the risk of corrupting GEM state (due
1545          * to running on almost untested codepaths). But on resume
1546          * timers don't work yet, so prevent a complete hang in that
1547          * case by choosing an insanely large timeout. */
1548         end = jiffies + 60 * HZ;
1549
1550         do {
1551                 ring->head = I915_READ_HEAD(ring);
1552                 ring->space = ring_space(ring);
1553                 if (ring->space >= n) {
1554                         trace_i915_ring_wait_end(ring);
1555                         return 0;
1556                 }
1557
1558                 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1559                     dev->primary->master) {
1560                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1561                         if (master_priv->sarea_priv)
1562                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1563                 }
1564
1565                 msleep(1);
1566
1567                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1568                                            dev_priv->mm.interruptible);
1569                 if (ret)
1570                         return ret;
1571         } while (!time_after(jiffies, end));
1572         trace_i915_ring_wait_end(ring);
1573         return -EBUSY;
1574 }
1575
1576 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1577 {
1578         uint32_t __iomem *virt;
1579         int rem = ring->size - ring->tail;
1580
1581         if (ring->space < rem) {
1582                 int ret = ring_wait_for_space(ring, rem);
1583                 if (ret)
1584                         return ret;
1585         }
1586
1587         virt = ring->virtual_start + ring->tail;
1588         rem /= 4;
1589         while (rem--)
1590                 iowrite32(MI_NOOP, virt++);
1591
1592         ring->tail = 0;
1593         ring->space = ring_space(ring);
1594
1595         return 0;
1596 }
1597
1598 int intel_ring_idle(struct intel_ring_buffer *ring)
1599 {
1600         u32 seqno;
1601         int ret;
1602
1603         /* We need to add any requests required to flush the objects and ring */
1604         if (ring->outstanding_lazy_seqno) {
1605                 ret = i915_add_request(ring, NULL);
1606                 if (ret)
1607                         return ret;
1608         }
1609
1610         /* Wait upon the last request to be completed */
1611         if (list_empty(&ring->request_list))
1612                 return 0;
1613
1614         seqno = list_entry(ring->request_list.prev,
1615                            struct drm_i915_gem_request,
1616                            list)->seqno;
1617
1618         return i915_wait_seqno(ring, seqno);
1619 }
1620
1621 static int
1622 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1623 {
1624         if (ring->outstanding_lazy_seqno)
1625                 return 0;
1626
1627         if (ring->preallocated_lazy_request == NULL) {
1628                 struct drm_i915_gem_request *request;
1629
1630                 request = kmalloc(sizeof(*request), GFP_KERNEL);
1631                 if (request == NULL)
1632                         return -ENOMEM;
1633
1634                 ring->preallocated_lazy_request = request;
1635         }
1636
1637         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1638 }
1639
1640 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1641                                 int bytes)
1642 {
1643         int ret;
1644
1645         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1646                 ret = intel_wrap_ring_buffer(ring);
1647                 if (unlikely(ret))
1648                         return ret;
1649         }
1650
1651         if (unlikely(ring->space < bytes)) {
1652                 ret = ring_wait_for_space(ring, bytes);
1653                 if (unlikely(ret))
1654                         return ret;
1655         }
1656
1657         return 0;
1658 }
1659
1660 int intel_ring_begin(struct intel_ring_buffer *ring,
1661                      int num_dwords)
1662 {
1663         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1664         int ret;
1665
1666         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1667                                    dev_priv->mm.interruptible);
1668         if (ret)
1669                 return ret;
1670
1671         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1672         if (ret)
1673                 return ret;
1674
1675         /* Preallocate the olr before touching the ring */
1676         ret = intel_ring_alloc_seqno(ring);
1677         if (ret)
1678                 return ret;
1679
1680         ring->space -= num_dwords * sizeof(uint32_t);
1681         return 0;
1682 }
1683
1684 /* Align the ring tail to a cacheline boundary */
1685 int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1686 {
1687         int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
1688         int ret;
1689
1690         if (num_dwords == 0)
1691                 return 0;
1692
1693         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
1694         ret = intel_ring_begin(ring, num_dwords);
1695         if (ret)
1696                 return ret;
1697
1698         while (num_dwords--)
1699                 intel_ring_emit(ring, MI_NOOP);
1700
1701         intel_ring_advance(ring);
1702
1703         return 0;
1704 }
1705
1706 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1707 {
1708         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1709
1710         BUG_ON(ring->outstanding_lazy_seqno);
1711
1712         if (INTEL_INFO(ring->dev)->gen >= 6) {
1713                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1714                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1715                 if (HAS_VEBOX(ring->dev))
1716                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1717         }
1718
1719         ring->set_seqno(ring, seqno);
1720         ring->hangcheck.seqno = seqno;
1721 }
1722
1723 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1724                                      u32 value)
1725 {
1726         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1727
1728        /* Every tail move must follow the sequence below */
1729
1730         /* Disable notification that the ring is IDLE. The GT
1731          * will then assume that it is busy and bring it out of rc6.
1732          */
1733         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1734                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1735
1736         /* Clear the context id. Here be magic! */
1737         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1738
1739         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1740         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1741                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1742                      50))
1743                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1744
1745         /* Now that the ring is fully powered up, update the tail */
1746         I915_WRITE_TAIL(ring, value);
1747         POSTING_READ(RING_TAIL(ring->mmio_base));
1748
1749         /* Let the ring send IDLE messages to the GT again,
1750          * and so let it sleep to conserve power when idle.
1751          */
1752         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1753                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1754 }
1755
1756 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1757                                u32 invalidate, u32 flush)
1758 {
1759         uint32_t cmd;
1760         int ret;
1761
1762         ret = intel_ring_begin(ring, 4);
1763         if (ret)
1764                 return ret;
1765
1766         cmd = MI_FLUSH_DW;
1767         if (INTEL_INFO(ring->dev)->gen >= 8)
1768                 cmd += 1;
1769         /*
1770          * Bspec vol 1c.5 - video engine command streamer:
1771          * "If ENABLED, all TLBs will be invalidated once the flush
1772          * operation is complete. This bit is only valid when the
1773          * Post-Sync Operation field is a value of 1h or 3h."
1774          */
1775         if (invalidate & I915_GEM_GPU_DOMAINS)
1776                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1777                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1778         intel_ring_emit(ring, cmd);
1779         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1780         if (INTEL_INFO(ring->dev)->gen >= 8) {
1781                 intel_ring_emit(ring, 0); /* upper addr */
1782                 intel_ring_emit(ring, 0); /* value */
1783         } else  {
1784                 intel_ring_emit(ring, 0);
1785                 intel_ring_emit(ring, MI_NOOP);
1786         }
1787         intel_ring_advance(ring);
1788         return 0;
1789 }
1790
1791 static int
1792 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1793                               u32 offset, u32 len,
1794                               unsigned flags)
1795 {
1796         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1797         bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1798                 !(flags & I915_DISPATCH_SECURE);
1799         int ret;
1800
1801         ret = intel_ring_begin(ring, 4);
1802         if (ret)
1803                 return ret;
1804
1805         /* FIXME(BDW): Address space and security selectors. */
1806         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1807         intel_ring_emit(ring, offset);
1808         intel_ring_emit(ring, 0);
1809         intel_ring_emit(ring, MI_NOOP);
1810         intel_ring_advance(ring);
1811
1812         return 0;
1813 }
1814
1815 static int
1816 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1817                               u32 offset, u32 len,
1818                               unsigned flags)
1819 {
1820         int ret;
1821
1822         ret = intel_ring_begin(ring, 2);
1823         if (ret)
1824                 return ret;
1825
1826         intel_ring_emit(ring,
1827                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1828                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1829         /* bit0-7 is the length on GEN6+ */
1830         intel_ring_emit(ring, offset);
1831         intel_ring_advance(ring);
1832
1833         return 0;
1834 }
1835
1836 static int
1837 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1838                               u32 offset, u32 len,
1839                               unsigned flags)
1840 {
1841         int ret;
1842
1843         ret = intel_ring_begin(ring, 2);
1844         if (ret)
1845                 return ret;
1846
1847         intel_ring_emit(ring,
1848                         MI_BATCH_BUFFER_START |
1849                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1850         /* bit0-7 is the length on GEN6+ */
1851         intel_ring_emit(ring, offset);
1852         intel_ring_advance(ring);
1853
1854         return 0;
1855 }
1856
1857 /* Blitter support (SandyBridge+) */
1858
1859 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1860                            u32 invalidate, u32 flush)
1861 {
1862         struct drm_device *dev = ring->dev;
1863         uint32_t cmd;
1864         int ret;
1865
1866         ret = intel_ring_begin(ring, 4);
1867         if (ret)
1868                 return ret;
1869
1870         cmd = MI_FLUSH_DW;
1871         if (INTEL_INFO(ring->dev)->gen >= 8)
1872                 cmd += 1;
1873         /*
1874          * Bspec vol 1c.3 - blitter engine command streamer:
1875          * "If ENABLED, all TLBs will be invalidated once the flush
1876          * operation is complete. This bit is only valid when the
1877          * Post-Sync Operation field is a value of 1h or 3h."
1878          */
1879         if (invalidate & I915_GEM_DOMAIN_RENDER)
1880                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1881                         MI_FLUSH_DW_OP_STOREDW;
1882         intel_ring_emit(ring, cmd);
1883         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1884         if (INTEL_INFO(ring->dev)->gen >= 8) {
1885                 intel_ring_emit(ring, 0); /* upper addr */
1886                 intel_ring_emit(ring, 0); /* value */
1887         } else  {
1888                 intel_ring_emit(ring, 0);
1889                 intel_ring_emit(ring, MI_NOOP);
1890         }
1891         intel_ring_advance(ring);
1892
1893         if (IS_GEN7(dev) && !invalidate && flush)
1894                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1895
1896         return 0;
1897 }
1898
1899 int intel_init_render_ring_buffer(struct drm_device *dev)
1900 {
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1903
1904         ring->name = "render ring";
1905         ring->id = RCS;
1906         ring->mmio_base = RENDER_RING_BASE;
1907
1908         if (INTEL_INFO(dev)->gen >= 6) {
1909                 ring->add_request = gen6_add_request;
1910                 ring->flush = gen7_render_ring_flush;
1911                 if (INTEL_INFO(dev)->gen == 6)
1912                         ring->flush = gen6_render_ring_flush;
1913                 if (INTEL_INFO(dev)->gen >= 8) {
1914                         ring->flush = gen8_render_ring_flush;
1915                         ring->irq_get = gen8_ring_get_irq;
1916                         ring->irq_put = gen8_ring_put_irq;
1917                 } else {
1918                         ring->irq_get = gen6_ring_get_irq;
1919                         ring->irq_put = gen6_ring_put_irq;
1920                 }
1921                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1922                 ring->get_seqno = gen6_ring_get_seqno;
1923                 ring->set_seqno = ring_set_seqno;
1924                 ring->sync_to = gen6_ring_sync;
1925                 /*
1926                  * The current semaphore is only applied on pre-gen8 platform.
1927                  * And there is no VCS2 ring on the pre-gen8 platform. So the
1928                  * semaphore between RCS and VCS2 is initialized as INVALID.
1929                  * Gen8 will initialize the sema between VCS2 and RCS later.
1930                  */
1931                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1932                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1933                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1934                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1935                 ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
1936                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1937                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1938                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1939                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1940                 ring->signal_mbox[VCS2] = GEN6_NOSYNC;
1941         } else if (IS_GEN5(dev)) {
1942                 ring->add_request = pc_render_add_request;
1943                 ring->flush = gen4_render_ring_flush;
1944                 ring->get_seqno = pc_render_get_seqno;
1945                 ring->set_seqno = pc_render_set_seqno;
1946                 ring->irq_get = gen5_ring_get_irq;
1947                 ring->irq_put = gen5_ring_put_irq;
1948                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1949                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1950         } else {
1951                 ring->add_request = i9xx_add_request;
1952                 if (INTEL_INFO(dev)->gen < 4)
1953                         ring->flush = gen2_render_ring_flush;
1954                 else
1955                         ring->flush = gen4_render_ring_flush;
1956                 ring->get_seqno = ring_get_seqno;
1957                 ring->set_seqno = ring_set_seqno;
1958                 if (IS_GEN2(dev)) {
1959                         ring->irq_get = i8xx_ring_get_irq;
1960                         ring->irq_put = i8xx_ring_put_irq;
1961                 } else {
1962                         ring->irq_get = i9xx_ring_get_irq;
1963                         ring->irq_put = i9xx_ring_put_irq;
1964                 }
1965                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1966         }
1967         ring->write_tail = ring_write_tail;
1968         if (IS_HASWELL(dev))
1969                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1970         else if (IS_GEN8(dev))
1971                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1972         else if (INTEL_INFO(dev)->gen >= 6)
1973                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1974         else if (INTEL_INFO(dev)->gen >= 4)
1975                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1976         else if (IS_I830(dev) || IS_845G(dev))
1977                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1978         else
1979                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1980         ring->init = init_render_ring;
1981         ring->cleanup = render_ring_cleanup;
1982
1983         /* Workaround batchbuffer to combat CS tlb bug. */
1984         if (HAS_BROKEN_CS_TLB(dev)) {
1985                 struct drm_i915_gem_object *obj;
1986                 int ret;
1987
1988                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1989                 if (obj == NULL) {
1990                         DRM_ERROR("Failed to allocate batch bo\n");
1991                         return -ENOMEM;
1992                 }
1993
1994                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
1995                 if (ret != 0) {
1996                         drm_gem_object_unreference(&obj->base);
1997                         DRM_ERROR("Failed to ping batch bo\n");
1998                         return ret;
1999                 }
2000
2001                 ring->scratch.obj = obj;
2002                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2003         }
2004
2005         return intel_init_ring_buffer(dev, ring);
2006 }
2007
2008 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2009 {
2010         struct drm_i915_private *dev_priv = dev->dev_private;
2011         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2012         int ret;
2013
2014         ring->name = "render ring";
2015         ring->id = RCS;
2016         ring->mmio_base = RENDER_RING_BASE;
2017
2018         if (INTEL_INFO(dev)->gen >= 6) {
2019                 /* non-kms not supported on gen6+ */
2020                 return -ENODEV;
2021         }
2022
2023         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2024          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2025          * the special gen5 functions. */
2026         ring->add_request = i9xx_add_request;
2027         if (INTEL_INFO(dev)->gen < 4)
2028                 ring->flush = gen2_render_ring_flush;
2029         else
2030                 ring->flush = gen4_render_ring_flush;
2031         ring->get_seqno = ring_get_seqno;
2032         ring->set_seqno = ring_set_seqno;
2033         if (IS_GEN2(dev)) {
2034                 ring->irq_get = i8xx_ring_get_irq;
2035                 ring->irq_put = i8xx_ring_put_irq;
2036         } else {
2037                 ring->irq_get = i9xx_ring_get_irq;
2038                 ring->irq_put = i9xx_ring_put_irq;
2039         }
2040         ring->irq_enable_mask = I915_USER_INTERRUPT;
2041         ring->write_tail = ring_write_tail;
2042         if (INTEL_INFO(dev)->gen >= 4)
2043                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2044         else if (IS_I830(dev) || IS_845G(dev))
2045                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2046         else
2047                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2048         ring->init = init_render_ring;
2049         ring->cleanup = render_ring_cleanup;
2050
2051         ring->dev = dev;
2052         INIT_LIST_HEAD(&ring->active_list);
2053         INIT_LIST_HEAD(&ring->request_list);
2054
2055         ring->size = size;
2056         ring->effective_size = ring->size;
2057         if (IS_I830(ring->dev) || IS_845G(ring->dev))
2058                 ring->effective_size -= 2 * CACHELINE_BYTES;
2059
2060         ring->virtual_start = ioremap_wc(start, size);
2061         if (ring->virtual_start == NULL) {
2062                 DRM_ERROR("can not ioremap virtual address for"
2063                           " ring buffer\n");
2064                 return -ENOMEM;
2065         }
2066
2067         if (!I915_NEED_GFX_HWS(dev)) {
2068                 ret = init_phys_status_page(ring);
2069                 if (ret)
2070                         return ret;
2071         }
2072
2073         return 0;
2074 }
2075
2076 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2077 {
2078         struct drm_i915_private *dev_priv = dev->dev_private;
2079         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2080
2081         ring->name = "bsd ring";
2082         ring->id = VCS;
2083
2084         ring->write_tail = ring_write_tail;
2085         if (INTEL_INFO(dev)->gen >= 6) {
2086                 ring->mmio_base = GEN6_BSD_RING_BASE;
2087                 /* gen6 bsd needs a special wa for tail updates */
2088                 if (IS_GEN6(dev))
2089                         ring->write_tail = gen6_bsd_ring_write_tail;
2090                 ring->flush = gen6_bsd_ring_flush;
2091                 ring->add_request = gen6_add_request;
2092                 ring->get_seqno = gen6_ring_get_seqno;
2093                 ring->set_seqno = ring_set_seqno;
2094                 if (INTEL_INFO(dev)->gen >= 8) {
2095                         ring->irq_enable_mask =
2096                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2097                         ring->irq_get = gen8_ring_get_irq;
2098                         ring->irq_put = gen8_ring_put_irq;
2099                         ring->dispatch_execbuffer =
2100                                 gen8_ring_dispatch_execbuffer;
2101                 } else {
2102                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2103                         ring->irq_get = gen6_ring_get_irq;
2104                         ring->irq_put = gen6_ring_put_irq;
2105                         ring->dispatch_execbuffer =
2106                                 gen6_ring_dispatch_execbuffer;
2107                 }
2108                 ring->sync_to = gen6_ring_sync;
2109                 /*
2110                  * The current semaphore is only applied on pre-gen8 platform.
2111                  * And there is no VCS2 ring on the pre-gen8 platform. So the
2112                  * semaphore between VCS and VCS2 is initialized as INVALID.
2113                  * Gen8 will initialize the sema between VCS2 and VCS later.
2114                  */
2115                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
2116                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2117                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
2118                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
2119                 ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2120                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
2121                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2122                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
2123                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
2124                 ring->signal_mbox[VCS2] = GEN6_NOSYNC;
2125         } else {
2126                 ring->mmio_base = BSD_RING_BASE;
2127                 ring->flush = bsd_ring_flush;
2128                 ring->add_request = i9xx_add_request;
2129                 ring->get_seqno = ring_get_seqno;
2130                 ring->set_seqno = ring_set_seqno;
2131                 if (IS_GEN5(dev)) {
2132                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2133                         ring->irq_get = gen5_ring_get_irq;
2134                         ring->irq_put = gen5_ring_put_irq;
2135                 } else {
2136                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2137                         ring->irq_get = i9xx_ring_get_irq;
2138                         ring->irq_put = i9xx_ring_put_irq;
2139                 }
2140                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2141         }
2142         ring->init = init_ring_common;
2143
2144         return intel_init_ring_buffer(dev, ring);
2145 }
2146
2147 /**
2148  * Initialize the second BSD ring for Broadwell GT3.
2149  * It is noted that this only exists on Broadwell GT3.
2150  */
2151 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2152 {
2153         struct drm_i915_private *dev_priv = dev->dev_private;
2154         struct intel_ring_buffer *ring = &dev_priv->ring[VCS2];
2155
2156         if ((INTEL_INFO(dev)->gen != 8)) {
2157                 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2158                 return -EINVAL;
2159         }
2160
2161         ring->name = "bds2_ring";
2162         ring->id = VCS2;
2163
2164         ring->write_tail = ring_write_tail;
2165         ring->mmio_base = GEN8_BSD2_RING_BASE;
2166         ring->flush = gen6_bsd_ring_flush;
2167         ring->add_request = gen6_add_request;
2168         ring->get_seqno = gen6_ring_get_seqno;
2169         ring->set_seqno = ring_set_seqno;
2170         ring->irq_enable_mask =
2171                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2172         ring->irq_get = gen8_ring_get_irq;
2173         ring->irq_put = gen8_ring_put_irq;
2174         ring->dispatch_execbuffer =
2175                         gen8_ring_dispatch_execbuffer;
2176         ring->sync_to = gen6_ring_sync;
2177         /*
2178          * The current semaphore is only applied on the pre-gen8. And there
2179          * is no bsd2 ring on the pre-gen8. So now the semaphore_register
2180          * between VCS2 and other ring is initialized as invalid.
2181          * Gen8 will initialize the sema between VCS2 and other ring later.
2182          */
2183         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2184         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2185         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2186         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2187         ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2188         ring->signal_mbox[RCS] = GEN6_NOSYNC;
2189         ring->signal_mbox[VCS] = GEN6_NOSYNC;
2190         ring->signal_mbox[BCS] = GEN6_NOSYNC;
2191         ring->signal_mbox[VECS] = GEN6_NOSYNC;
2192         ring->signal_mbox[VCS2] = GEN6_NOSYNC;
2193
2194         ring->init = init_ring_common;
2195
2196         return intel_init_ring_buffer(dev, ring);
2197 }
2198
2199 int intel_init_blt_ring_buffer(struct drm_device *dev)
2200 {
2201         struct drm_i915_private *dev_priv = dev->dev_private;
2202         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2203
2204         ring->name = "blitter ring";
2205         ring->id = BCS;
2206
2207         ring->mmio_base = BLT_RING_BASE;
2208         ring->write_tail = ring_write_tail;
2209         ring->flush = gen6_ring_flush;
2210         ring->add_request = gen6_add_request;
2211         ring->get_seqno = gen6_ring_get_seqno;
2212         ring->set_seqno = ring_set_seqno;
2213         if (INTEL_INFO(dev)->gen >= 8) {
2214                 ring->irq_enable_mask =
2215                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2216                 ring->irq_get = gen8_ring_get_irq;
2217                 ring->irq_put = gen8_ring_put_irq;
2218                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2219         } else {
2220                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2221                 ring->irq_get = gen6_ring_get_irq;
2222                 ring->irq_put = gen6_ring_put_irq;
2223                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2224         }
2225         ring->sync_to = gen6_ring_sync;
2226         /*
2227          * The current semaphore is only applied on pre-gen8 platform. And
2228          * there is no VCS2 ring on the pre-gen8 platform. So the semaphore
2229          * between BCS and VCS2 is initialized as INVALID.
2230          * Gen8 will initialize the sema between BCS and VCS2 later.
2231          */
2232         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2233         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2234         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2235         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
2236         ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2237         ring->signal_mbox[RCS] = GEN6_RBSYNC;
2238         ring->signal_mbox[VCS] = GEN6_VBSYNC;
2239         ring->signal_mbox[BCS] = GEN6_NOSYNC;
2240         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
2241         ring->signal_mbox[VCS2] = GEN6_NOSYNC;
2242         ring->init = init_ring_common;
2243
2244         return intel_init_ring_buffer(dev, ring);
2245 }
2246
2247 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2248 {
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2251
2252         ring->name = "video enhancement ring";
2253         ring->id = VECS;
2254
2255         ring->mmio_base = VEBOX_RING_BASE;
2256         ring->write_tail = ring_write_tail;
2257         ring->flush = gen6_ring_flush;
2258         ring->add_request = gen6_add_request;
2259         ring->get_seqno = gen6_ring_get_seqno;
2260         ring->set_seqno = ring_set_seqno;
2261
2262         if (INTEL_INFO(dev)->gen >= 8) {
2263                 ring->irq_enable_mask =
2264                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2265                 ring->irq_get = gen8_ring_get_irq;
2266                 ring->irq_put = gen8_ring_put_irq;
2267                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2268         } else {
2269                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2270                 ring->irq_get = hsw_vebox_get_irq;
2271                 ring->irq_put = hsw_vebox_put_irq;
2272                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2273         }
2274         ring->sync_to = gen6_ring_sync;
2275         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2276         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2277         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2278         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2279         ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2280         ring->signal_mbox[RCS] = GEN6_RVESYNC;
2281         ring->signal_mbox[VCS] = GEN6_VVESYNC;
2282         ring->signal_mbox[BCS] = GEN6_BVESYNC;
2283         ring->signal_mbox[VECS] = GEN6_NOSYNC;
2284         ring->signal_mbox[VCS2] = GEN6_NOSYNC;
2285         ring->init = init_ring_common;
2286
2287         return intel_init_ring_buffer(dev, ring);
2288 }
2289
2290 int
2291 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2292 {
2293         int ret;
2294
2295         if (!ring->gpu_caches_dirty)
2296                 return 0;
2297
2298         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2299         if (ret)
2300                 return ret;
2301
2302         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2303
2304         ring->gpu_caches_dirty = false;
2305         return 0;
2306 }
2307
2308 int
2309 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2310 {
2311         uint32_t flush_domains;
2312         int ret;
2313
2314         flush_domains = 0;
2315         if (ring->gpu_caches_dirty)
2316                 flush_domains = I915_GEM_GPU_DOMAINS;
2317
2318         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2319         if (ret)
2320                 return ret;
2321
2322         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2323
2324         ring->gpu_caches_dirty = false;
2325         return 0;
2326 }
2327
2328 void
2329 intel_stop_ring_buffer(struct intel_ring_buffer *ring)
2330 {
2331         int ret;
2332
2333         if (!intel_ring_initialized(ring))
2334                 return;
2335
2336         ret = intel_ring_idle(ring);
2337         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2338                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2339                           ring->name, ret);
2340
2341         stop_ring(ring);
2342 }