drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /*
  38  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  39  * over cache flushing.
  40  */
  41 struct pipe_control {
  42         struct drm_i915_gem_object *obj;
  43         volatile u32 *cpu_page;
  44         u32 gtt_offset;
  45 };
  46
  47 static inline int ring_space(struct intel_ring_buffer *ring)
  48 {
  49         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  50         if (space < 0)
  51                 space += ring->size;
  52         return space;
  53 }
  54
  55 static int
  56 render_ring_flush(struct intel_ring_buffer *ring,
  57                   u32   invalidate_domains,
  58                   u32   flush_domains)
  59 {
  60         struct drm_device *dev = ring->dev;
  61         u32 cmd;
  62         int ret;
  63
  64         /*
  65          * read/write caches:
  66          *
  67          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  68          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  69          * also flushed at 2d versus 3d pipeline switches.
  70          *
  71          * read-only caches:
  72          *
  73          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  74          * MI_READ_FLUSH is set, and is always flushed on 965.
  75          *
  76          * I915_GEM_DOMAIN_COMMAND may not exist?
  77          *
  78          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  79          * invalidated when MI_EXE_FLUSH is set.
  80          *
  81          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  82          * invalidated with every MI_FLUSH.
  83          *
  84          * TLBs:
  85          *
  86          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  87          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  88          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  89          * are flushed at any MI_FLUSH.
  90          */
  91
  92         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  93         if ((invalidate_domains|flush_domains) &
  94             I915_GEM_DOMAIN_RENDER)
  95                 cmd &= ~MI_NO_WRITE_FLUSH;
  96         if (INTEL_INFO(dev)->gen < 4) {
  97                 /*
  98                  * On the 965, the sampler cache always gets flushed
  99                  * and this bit is reserved.
 100                  */
 101                 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 102                         cmd |= MI_READ_FLUSH;
 103         }
 104         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 105                 cmd |= MI_EXE_FLUSH;
 106
 107         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 108             (IS_G4X(dev) || IS_GEN5(dev)))
 109                 cmd |= MI_INVALIDATE_ISP;
 110
 111         ret = intel_ring_begin(ring, 2);
 112         if (ret)
 113                 return ret;
 114
 115         intel_ring_emit(ring, cmd);
 116         intel_ring_emit(ring, MI_NOOP);
 117         intel_ring_advance(ring);
 118
 119         return 0;
 120 }
 121
 122 /**
 123  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 124  * implementing two workarounds on gen6.  From section 1.4.7.1
 125  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 126  *
 127  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 128  * produced by non-pipelined state commands), software needs to first
 129  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 130  * 0.
 131  *
 132  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 133  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 134  *
 135  * And the workaround for these two requires this workaround first:
 136  *
 137  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 138  * BEFORE the pipe-control with a post-sync op and no write-cache
 139  * flushes.
 140  *
 141  * And this last workaround is tricky because of the requirements on
 142  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 143  * volume 2 part 1:
 144  *
 145  *     "1 of the following must also be set:
 146  *      - Render Target Cache Flush Enable ([12] of DW1)
 147  *      - Depth Cache Flush Enable ([0] of DW1)
 148  *      - Stall at Pixel Scoreboard ([1] of DW1)
 149  *      - Depth Stall ([13] of DW1)
 150  *      - Post-Sync Operation ([13] of DW1)
 151  *      - Notify Enable ([8] of DW1)"
 152  *
 153  * The cache flushes require the workaround flush that triggered this
 154  * one, so we can't use it.  Depth stall would trigger the same.
 155  * Post-sync nonzero is what triggered this second workaround, so we
 156  * can't use that one either.  Notify enable is IRQs, which aren't
 157  * really our business.  That leaves only stall at scoreboard.
 158  */
 159 static int
 160 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 161 {
 162         struct pipe_control *pc = ring->private;
 163         u32 scratch_addr = pc->gtt_offset + 128;
 164         int ret;
 165
 166
 167         ret = intel_ring_begin(ring, 6);
 168         if (ret)
 169                 return ret;
 170
 171         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 172         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 173                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 174         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 175         intel_ring_emit(ring, 0); /* low dword */
 176         intel_ring_emit(ring, 0); /* high dword */
 177         intel_ring_emit(ring, MI_NOOP);
 178         intel_ring_advance(ring);
 179
 180         ret = intel_ring_begin(ring, 6);
 181         if (ret)
 182                 return ret;
 183
 184         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 185         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 186         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 187         intel_ring_emit(ring, 0);
 188         intel_ring_emit(ring, 0);
 189         intel_ring_emit(ring, MI_NOOP);
 190         intel_ring_advance(ring);
 191
 192         return 0;
 193 }
 194
 195 static int
 196 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 197                          u32 invalidate_domains, u32 flush_domains)
 198 {
 199         u32 flags = 0;
 200         struct pipe_control *pc = ring->private;
 201         u32 scratch_addr = pc->gtt_offset + 128;
 202         int ret;
 203
 204         /* Force SNB workarounds for PIPE_CONTROL flushes */
 205         intel_emit_post_sync_nonzero_flush(ring);
 206
 207         /* Just flush everything.  Experiments have shown that reducing the
 208          * number of bits based on the write domains has little performance
 209          * impact.
 210          */
 211         flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 212         flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 213         flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 214         flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 215         flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 216         flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 217         flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 218
 219         ret = intel_ring_begin(ring, 6);
 220         if (ret)
 221                 return ret;
 222
 223         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 224         intel_ring_emit(ring, flags);
 225         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 226         intel_ring_emit(ring, 0); /* lower dword */
 227         intel_ring_emit(ring, 0); /* uppwer dword */
 228         intel_ring_emit(ring, MI_NOOP);
 229         intel_ring_advance(ring);
 230
 231         return 0;
 232 }
 233
 234 static void ring_write_tail(struct intel_ring_buffer *ring,
 235                             u32 value)
 236 {
 237         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 238         I915_WRITE_TAIL(ring, value);
 239 }
 240
 241 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 242 {
 243         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 244         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 245                         RING_ACTHD(ring->mmio_base) : ACTHD;
 246
 247         return I915_READ(acthd_reg);
 248 }
 249
 250 static int init_ring_common(struct intel_ring_buffer *ring)
 251 {
 252         struct drm_device *dev = ring->dev;
 253         drm_i915_private_t *dev_priv = dev->dev_private;
 254         struct drm_i915_gem_object *obj = ring->obj;
 255         int ret = 0;
 256         u32 head;
 257
 258         if (HAS_FORCE_WAKE(dev))
 259                 gen6_gt_force_wake_get(dev_priv);
 260
 261         /* Stop the ring if it's running. */
 262         I915_WRITE_CTL(ring, 0);
 263         I915_WRITE_HEAD(ring, 0);
 264         ring->write_tail(ring, 0);
 265
 266         /* Initialize the ring. */
 267         I915_WRITE_START(ring, obj->gtt_offset);
 268         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 269
 270         /* G45 ring initialization fails to reset head to zero */
 271         if (head != 0) {
 272                 DRM_DEBUG_KMS("%s head not reset to zero "
 273                               "ctl %08x head %08x tail %08x start %08x\n",
 274                               ring->name,
 275                               I915_READ_CTL(ring),
 276                               I915_READ_HEAD(ring),
 277                               I915_READ_TAIL(ring),
 278                               I915_READ_START(ring));
 279
 280                 I915_WRITE_HEAD(ring, 0);
 281
 282                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 283                         DRM_ERROR("failed to set %s head to zero "
 284                                   "ctl %08x head %08x tail %08x start %08x\n",
 285                                   ring->name,
 286                                   I915_READ_CTL(ring),
 287                                   I915_READ_HEAD(ring),
 288                                   I915_READ_TAIL(ring),
 289                                   I915_READ_START(ring));
 290                 }
 291         }
 292
 293         I915_WRITE_CTL(ring,
 294                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 295                         | RING_VALID);
 296
 297         /* If the head is still not zero, the ring is dead */
 298         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 299             I915_READ_START(ring) != obj->gtt_offset ||
 300             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 301                 DRM_ERROR("%s initialization failed "
 302                                 "ctl %08x head %08x tail %08x start %08x\n",
 303                                 ring->name,
 304                                 I915_READ_CTL(ring),
 305                                 I915_READ_HEAD(ring),
 306                                 I915_READ_TAIL(ring),
 307                                 I915_READ_START(ring));
 308                 ret = -EIO;
 309                 goto out;
 310         }
 311
 312         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 313                 i915_kernel_lost_context(ring->dev);
 314         else {
 315                 ring->head = I915_READ_HEAD(ring);
 316                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 317                 ring->space = ring_space(ring);
 318         }
 319
 320 out:
 321         if (HAS_FORCE_WAKE(dev))
 322                 gen6_gt_force_wake_put(dev_priv);
 323
 324         return ret;
 325 }
 326
 327 static int
 328 init_pipe_control(struct intel_ring_buffer *ring)
 329 {
 330         struct pipe_control *pc;
 331         struct drm_i915_gem_object *obj;
 332         int ret;
 333
 334         if (ring->private)
 335                 return 0;
 336
 337         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 338         if (!pc)
 339                 return -ENOMEM;
 340
 341         obj = i915_gem_alloc_object(ring->dev, 4096);
 342         if (obj == NULL) {
 343                 DRM_ERROR("Failed to allocate seqno page\n");
 344                 ret = -ENOMEM;
 345                 goto err;
 346         }
 347
 348         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 349
 350         ret = i915_gem_object_pin(obj, 4096, true);
 351         if (ret)
 352                 goto err_unref;
 353
 354         pc->gtt_offset = obj->gtt_offset;
 355         pc->cpu_page =  kmap(obj->pages[0]);
 356         if (pc->cpu_page == NULL)
 357                 goto err_unpin;
 358
 359         pc->obj = obj;
 360         ring->private = pc;
 361         return 0;
 362
 363 err_unpin:
 364         i915_gem_object_unpin(obj);
 365 err_unref:
 366         drm_gem_object_unreference(&obj->base);
 367 err:
 368         kfree(pc);
 369         return ret;
 370 }
 371
 372 static void
 373 cleanup_pipe_control(struct intel_ring_buffer *ring)
 374 {
 375         struct pipe_control *pc = ring->private;
 376         struct drm_i915_gem_object *obj;
 377
 378         if (!ring->private)
 379                 return;
 380
 381         obj = pc->obj;
 382         kunmap(obj->pages[0]);
 383         i915_gem_object_unpin(obj);
 384         drm_gem_object_unreference(&obj->base);
 385
 386         kfree(pc);
 387         ring->private = NULL;
 388 }
 389
 390 static int init_render_ring(struct intel_ring_buffer *ring)
 391 {
 392         struct drm_device *dev = ring->dev;
 393         struct drm_i915_private *dev_priv = dev->dev_private;
 394         int ret = init_ring_common(ring);
 395
 396         if (INTEL_INFO(dev)->gen > 3) {
 397                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 398                 if (IS_GEN6(dev) || IS_GEN7(dev))
 399                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 400                 I915_WRITE(MI_MODE, mode);
 401                 if (IS_GEN7(dev))
 402                         I915_WRITE(GFX_MODE_GEN7,
 403                                    GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 404                                    GFX_MODE_ENABLE(GFX_REPLAY_MODE));
 405         }
 406
 407         if (INTEL_INFO(dev)->gen >= 5) {
 408                 ret = init_pipe_control(ring);
 409                 if (ret)
 410                         return ret;
 411         }
 412
 413
 414         if (IS_GEN6(dev)) {
 415                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 416                  * "If this bit is set, STCunit will have LRA as replacement
 417                  *  policy. [...] This bit must be reset.  LRA replacement
 418                  *  policy is not supported."
 419                  */
 420                 I915_WRITE(CACHE_MODE_0,
 421                            CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
 422         }
 423
 424         if (INTEL_INFO(dev)->gen >= 6) {
 425                 I915_WRITE(INSTPM,
 426                            INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
 427         }
 428
 429         return ret;
 430 }
 431
 432 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 433 {
 434         if (!ring->private)
 435                 return;
 436
 437         cleanup_pipe_control(ring);
 438 }
 439
 440 static void
 441 update_mboxes(struct intel_ring_buffer *ring,
 442             u32 seqno,
 443             u32 mmio_offset)
 444 {
 445         intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
 446                               MI_SEMAPHORE_GLOBAL_GTT |
 447                               MI_SEMAPHORE_REGISTER |
 448                               MI_SEMAPHORE_UPDATE);
 449         intel_ring_emit(ring, seqno);
 450         intel_ring_emit(ring, mmio_offset);
 451 }
 452
 453 /**
 454  * gen6_add_request - Update the semaphore mailbox registers
 455  *
 456  * @ring - ring that is adding a request
 457  * @seqno - return seqno stuck into the ring
 458  *
 459  * Update the mailbox registers in the *other* rings with the current seqno.
 460  * This acts like a signal in the canonical semaphore.
 461  */
 462 static int
 463 gen6_add_request(struct intel_ring_buffer *ring,
 464                  u32 *seqno)
 465 {
 466         u32 mbox1_reg;
 467         u32 mbox2_reg;
 468         int ret;
 469
 470         ret = intel_ring_begin(ring, 10);
 471         if (ret)
 472                 return ret;
 473
 474         mbox1_reg = ring->signal_mbox[0];
 475         mbox2_reg = ring->signal_mbox[1];
 476
 477         *seqno = i915_gem_next_request_seqno(ring);
 478
 479         update_mboxes(ring, *seqno, mbox1_reg);
 480         update_mboxes(ring, *seqno, mbox2_reg);
 481         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 482         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 483         intel_ring_emit(ring, *seqno);
 484         intel_ring_emit(ring, MI_USER_INTERRUPT);
 485         intel_ring_advance(ring);
 486
 487         return 0;
 488 }
 489
 490 /**
 491  * intel_ring_sync - sync the waiter to the signaller on seqno
 492  *
 493  * @waiter - ring that is waiting
 494  * @signaller - ring which has, or will signal
 495  * @seqno - seqno which the waiter will block on
 496  */
 497 static int
 498 intel_ring_sync(struct intel_ring_buffer *waiter,
 499                 struct intel_ring_buffer *signaller,
 500                 int ring,
 501                 u32 seqno)
 502 {
 503         int ret;
 504         u32 dw1 = MI_SEMAPHORE_MBOX |
 505                   MI_SEMAPHORE_COMPARE |
 506                   MI_SEMAPHORE_REGISTER;
 507
 508         ret = intel_ring_begin(waiter, 4);
 509         if (ret)
 510                 return ret;
 511
 512         intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
 513         intel_ring_emit(waiter, seqno);
 514         intel_ring_emit(waiter, 0);
 515         intel_ring_emit(waiter, MI_NOOP);
 516         intel_ring_advance(waiter);
 517
 518         return 0;
 519 }
 520
 521 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
 522 int
 523 render_ring_sync_to(struct intel_ring_buffer *waiter,
 524                     struct intel_ring_buffer *signaller,
 525                     u32 seqno)
 526 {
 527         WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
 528         return intel_ring_sync(waiter,
 529                                signaller,
 530                                RCS,
 531                                seqno);
 532 }
 533
 534 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
 535 int
 536 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
 537                       struct intel_ring_buffer *signaller,
 538                       u32 seqno)
 539 {
 540         WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
 541         return intel_ring_sync(waiter,
 542                                signaller,
 543                                VCS,
 544                                seqno);
 545 }
 546
 547 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
 548 int
 549 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
 550                       struct intel_ring_buffer *signaller,
 551                       u32 seqno)
 552 {
 553         WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
 554         return intel_ring_sync(waiter,
 555                                signaller,
 556                                BCS,
 557                                seqno);
 558 }
 559
 560
 561
 562 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 563 do {                                                                    \
 564         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 565                  PIPE_CONTROL_DEPTH_STALL);                             \
 566         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 567         intel_ring_emit(ring__, 0);                                                     \
 568         intel_ring_emit(ring__, 0);                                                     \
 569 } while (0)
 570
 571 static int
 572 pc_render_add_request(struct intel_ring_buffer *ring,
 573                       u32 *result)
 574 {
 575         u32 seqno = i915_gem_next_request_seqno(ring);
 576         struct pipe_control *pc = ring->private;
 577         u32 scratch_addr = pc->gtt_offset + 128;
 578         int ret;
 579
 580         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 581          * incoherent with writes to memory, i.e. completely fubar,
 582          * so we need to use PIPE_NOTIFY instead.
 583          *
 584          * However, we also need to workaround the qword write
 585          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 586          * memory before requesting an interrupt.
 587          */
 588         ret = intel_ring_begin(ring, 32);
 589         if (ret)
 590                 return ret;
 591
 592         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 593                         PIPE_CONTROL_WRITE_FLUSH |
 594                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 595         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 596         intel_ring_emit(ring, seqno);
 597         intel_ring_emit(ring, 0);
 598         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 599         scratch_addr += 128; /* write to separate cachelines */
 600         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 601         scratch_addr += 128;
 602         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 603         scratch_addr += 128;
 604         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 605         scratch_addr += 128;
 606         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 607         scratch_addr += 128;
 608         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 609         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 610                         PIPE_CONTROL_WRITE_FLUSH |
 611                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 612                         PIPE_CONTROL_NOTIFY);
 613         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 614         intel_ring_emit(ring, seqno);
 615         intel_ring_emit(ring, 0);
 616         intel_ring_advance(ring);
 617
 618         *result = seqno;
 619         return 0;
 620 }
 621
 622 static int
 623 render_ring_add_request(struct intel_ring_buffer *ring,
 624                         u32 *result)
 625 {
 626         u32 seqno = i915_gem_next_request_seqno(ring);
 627         int ret;
 628
 629         ret = intel_ring_begin(ring, 4);
 630         if (ret)
 631                 return ret;
 632
 633         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 634         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 635         intel_ring_emit(ring, seqno);
 636         intel_ring_emit(ring, MI_USER_INTERRUPT);
 637         intel_ring_advance(ring);
 638
 639         *result = seqno;
 640         return 0;
 641 }
 642
 643 static u32
 644 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
 645 {
 646         struct drm_device *dev = ring->dev;
 647
 648         /* Workaround to force correct ordering between irq and seqno writes on
 649          * ivb (and maybe also on snb) by reading from a CS register (like
 650          * ACTHD) before reading the status page. */
 651         if (IS_GEN7(dev))
 652                 intel_ring_get_active_head(ring);
 653         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 654 }
 655
 656 static u32
 657 ring_get_seqno(struct intel_ring_buffer *ring)
 658 {
 659         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 660 }
 661
 662 static u32
 663 pc_render_get_seqno(struct intel_ring_buffer *ring)
 664 {
 665         struct pipe_control *pc = ring->private;
 666         return pc->cpu_page[0];
 667 }
 668
 669 static void
 670 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 671 {
 672         dev_priv->gt_irq_mask &= ~mask;
 673         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 674         POSTING_READ(GTIMR);
 675 }
 676
 677 static void
 678 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 679 {
 680         dev_priv->gt_irq_mask |= mask;
 681         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 682         POSTING_READ(GTIMR);
 683 }
 684
 685 static void
 686 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 687 {
 688         dev_priv->irq_mask &= ~mask;
 689         I915_WRITE(IMR, dev_priv->irq_mask);
 690         POSTING_READ(IMR);
 691 }
 692
 693 static void
 694 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 695 {
 696         dev_priv->irq_mask |= mask;
 697         I915_WRITE(IMR, dev_priv->irq_mask);
 698         POSTING_READ(IMR);
 699 }
 700
 701 static bool
 702 render_ring_get_irq(struct intel_ring_buffer *ring)
 703 {
 704         struct drm_device *dev = ring->dev;
 705         drm_i915_private_t *dev_priv = dev->dev_private;
 706
 707         if (!dev->irq_enabled)
 708                 return false;
 709
 710         spin_lock(&ring->irq_lock);
 711         if (ring->irq_refcount++ == 0) {
 712                 if (HAS_PCH_SPLIT(dev))
 713                         ironlake_enable_irq(dev_priv,
 714                                             GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 715                 else
 716                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 717         }
 718         spin_unlock(&ring->irq_lock);
 719
 720         return true;
 721 }
 722
 723 static void
 724 render_ring_put_irq(struct intel_ring_buffer *ring)
 725 {
 726         struct drm_device *dev = ring->dev;
 727         drm_i915_private_t *dev_priv = dev->dev_private;
 728
 729         spin_lock(&ring->irq_lock);
 730         if (--ring->irq_refcount == 0) {
 731                 if (HAS_PCH_SPLIT(dev))
 732                         ironlake_disable_irq(dev_priv,
 733                                              GT_USER_INTERRUPT |
 734                                              GT_PIPE_NOTIFY);
 735                 else
 736                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 737         }
 738         spin_unlock(&ring->irq_lock);
 739 }
 740
 741 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 742 {
 743         struct drm_device *dev = ring->dev;
 744         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 745         u32 mmio = 0;
 746
 747         /* The ring status page addresses are no longer next to the rest of
 748          * the ring registers as of gen7.
 749          */
 750         if (IS_GEN7(dev)) {
 751                 switch (ring->id) {
 752                 case RING_RENDER:
 753                         mmio = RENDER_HWS_PGA_GEN7;
 754                         break;
 755                 case RING_BLT:
 756                         mmio = BLT_HWS_PGA_GEN7;
 757                         break;
 758                 case RING_BSD:
 759                         mmio = BSD_HWS_PGA_GEN7;
 760                         break;
 761                 }
 762         } else if (IS_GEN6(ring->dev)) {
 763                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 764         } else {
 765                 mmio = RING_HWS_PGA(ring->mmio_base);
 766         }
 767
 768         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 769         POSTING_READ(mmio);
 770 }
 771
 772 static int
 773 bsd_ring_flush(struct intel_ring_buffer *ring,
 774                u32     invalidate_domains,
 775                u32     flush_domains)
 776 {
 777         int ret;
 778
 779         ret = intel_ring_begin(ring, 2);
 780         if (ret)
 781                 return ret;
 782
 783         intel_ring_emit(ring, MI_FLUSH);
 784         intel_ring_emit(ring, MI_NOOP);
 785         intel_ring_advance(ring);
 786         return 0;
 787 }
 788
 789 static int
 790 ring_add_request(struct intel_ring_buffer *ring,
 791                  u32 *result)
 792 {
 793         u32 seqno;
 794         int ret;
 795
 796         ret = intel_ring_begin(ring, 4);
 797         if (ret)
 798                 return ret;
 799
 800         seqno = i915_gem_next_request_seqno(ring);
 801
 802         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 803         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 804         intel_ring_emit(ring, seqno);
 805         intel_ring_emit(ring, MI_USER_INTERRUPT);
 806         intel_ring_advance(ring);
 807
 808         *result = seqno;
 809         return 0;
 810 }
 811
 812 static bool
 813 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 814 {
 815         struct drm_device *dev = ring->dev;
 816         drm_i915_private_t *dev_priv = dev->dev_private;
 817
 818         if (!dev->irq_enabled)
 819                return false;
 820
 821         /* It looks like we need to prevent the gt from suspending while waiting
 822          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 823          * blt/bsd rings on ivb. */
 824         if (IS_GEN7(dev))
 825                 gen6_gt_force_wake_get(dev_priv);
 826
 827         spin_lock(&ring->irq_lock);
 828         if (ring->irq_refcount++ == 0) {
 829                 ring->irq_mask &= ~rflag;
 830                 I915_WRITE_IMR(ring, ring->irq_mask);
 831                 ironlake_enable_irq(dev_priv, gflag);
 832         }
 833         spin_unlock(&ring->irq_lock);
 834
 835         return true;
 836 }
 837
 838 static void
 839 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 840 {
 841         struct drm_device *dev = ring->dev;
 842         drm_i915_private_t *dev_priv = dev->dev_private;
 843
 844         spin_lock(&ring->irq_lock);
 845         if (--ring->irq_refcount == 0) {
 846                 ring->irq_mask |= rflag;
 847                 I915_WRITE_IMR(ring, ring->irq_mask);
 848                 ironlake_disable_irq(dev_priv, gflag);
 849         }
 850         spin_unlock(&ring->irq_lock);
 851
 852         if (IS_GEN7(dev))
 853                 gen6_gt_force_wake_put(dev_priv);
 854 }
 855
 856 static bool
 857 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 858 {
 859         struct drm_device *dev = ring->dev;
 860         drm_i915_private_t *dev_priv = dev->dev_private;
 861
 862         if (!dev->irq_enabled)
 863                 return false;
 864
 865         spin_lock(&ring->irq_lock);
 866         if (ring->irq_refcount++ == 0) {
 867                 if (IS_G4X(dev))
 868                         i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 869                 else
 870                         ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 871         }
 872         spin_unlock(&ring->irq_lock);
 873
 874         return true;
 875 }
 876 static void
 877 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 878 {
 879         struct drm_device *dev = ring->dev;
 880         drm_i915_private_t *dev_priv = dev->dev_private;
 881
 882         spin_lock(&ring->irq_lock);
 883         if (--ring->irq_refcount == 0) {
 884                 if (IS_G4X(dev))
 885                         i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 886                 else
 887                         ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 888         }
 889         spin_unlock(&ring->irq_lock);
 890 }
 891
 892 static int
 893 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 894 {
 895         int ret;
 896
 897         ret = intel_ring_begin(ring, 2);
 898         if (ret)
 899                 return ret;
 900
 901         intel_ring_emit(ring,
 902                         MI_BATCH_BUFFER_START | (2 << 6) |
 903                         MI_BATCH_NON_SECURE_I965);
 904         intel_ring_emit(ring, offset);
 905         intel_ring_advance(ring);
 906
 907         return 0;
 908 }
 909
 910 static int
 911 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 912                                 u32 offset, u32 len)
 913 {
 914         struct drm_device *dev = ring->dev;
 915         int ret;
 916
 917         if (IS_I830(dev) || IS_845G(dev)) {
 918                 ret = intel_ring_begin(ring, 4);
 919                 if (ret)
 920                         return ret;
 921
 922                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 923                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 924                 intel_ring_emit(ring, offset + len - 8);
 925                 intel_ring_emit(ring, 0);
 926         } else {
 927                 ret = intel_ring_begin(ring, 2);
 928                 if (ret)
 929                         return ret;
 930
 931                 if (INTEL_INFO(dev)->gen >= 4) {
 932                         intel_ring_emit(ring,
 933                                         MI_BATCH_BUFFER_START | (2 << 6) |
 934                                         MI_BATCH_NON_SECURE_I965);
 935                         intel_ring_emit(ring, offset);
 936                 } else {
 937                         intel_ring_emit(ring,
 938                                         MI_BATCH_BUFFER_START | (2 << 6));
 939                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 940                 }
 941         }
 942         intel_ring_advance(ring);
 943
 944         return 0;
 945 }
 946
 947 static void cleanup_status_page(struct intel_ring_buffer *ring)
 948 {
 949         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 950         struct drm_i915_gem_object *obj;
 951
 952         obj = ring->status_page.obj;
 953         if (obj == NULL)
 954                 return;
 955
 956         kunmap(obj->pages[0]);
 957         i915_gem_object_unpin(obj);
 958         drm_gem_object_unreference(&obj->base);
 959         ring->status_page.obj = NULL;
 960
 961         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 962 }
 963
 964 static int init_status_page(struct intel_ring_buffer *ring)
 965 {
 966         struct drm_device *dev = ring->dev;
 967         drm_i915_private_t *dev_priv = dev->dev_private;
 968         struct drm_i915_gem_object *obj;
 969         int ret;
 970
 971         obj = i915_gem_alloc_object(dev, 4096);
 972         if (obj == NULL) {
 973                 DRM_ERROR("Failed to allocate status page\n");
 974                 ret = -ENOMEM;
 975                 goto err;
 976         }
 977
 978         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 979
 980         ret = i915_gem_object_pin(obj, 4096, true);
 981         if (ret != 0) {
 982                 goto err_unref;
 983         }
 984
 985         ring->status_page.gfx_addr = obj->gtt_offset;
 986         ring->status_page.page_addr = kmap(obj->pages[0]);
 987         if (ring->status_page.page_addr == NULL) {
 988                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 989                 goto err_unpin;
 990         }
 991         ring->status_page.obj = obj;
 992         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 993
 994         intel_ring_setup_status_page(ring);
 995         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 996                         ring->name, ring->status_page.gfx_addr);
 997
 998         return 0;
 999
1000 err_unpin:
1001         i915_gem_object_unpin(obj);
1002 err_unref:
1003         drm_gem_object_unreference(&obj->base);
1004 err:
1005         return ret;
1006 }
1007
1008 int intel_init_ring_buffer(struct drm_device *dev,
1009                            struct intel_ring_buffer *ring)
1010 {
1011         struct drm_i915_gem_object *obj;
1012         int ret;
1013
1014         ring->dev = dev;
1015         INIT_LIST_HEAD(&ring->active_list);
1016         INIT_LIST_HEAD(&ring->request_list);
1017         INIT_LIST_HEAD(&ring->gpu_write_list);
1018
1019         init_waitqueue_head(&ring->irq_queue);
1020         spin_lock_init(&ring->irq_lock);
1021         ring->irq_mask = ~0;
1022
1023         if (I915_NEED_GFX_HWS(dev)) {
1024                 ret = init_status_page(ring);
1025                 if (ret)
1026                         return ret;
1027         }
1028
1029         obj = i915_gem_alloc_object(dev, ring->size);
1030         if (obj == NULL) {
1031                 DRM_ERROR("Failed to allocate ringbuffer\n");
1032                 ret = -ENOMEM;
1033                 goto err_hws;
1034         }
1035
1036         ring->obj = obj;
1037
1038         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1039         if (ret)
1040                 goto err_unref;
1041
1042         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1043         if (ret)
1044                 goto err_unpin;
1045
1046         ring->map.size = ring->size;
1047         ring->map.offset = dev->agp->base + obj->gtt_offset;
1048         ring->map.type = 0;
1049         ring->map.flags = 0;
1050         ring->map.mtrr = 0;
1051
1052         drm_core_ioremap_wc(&ring->map, dev);
1053         if (ring->map.handle == NULL) {
1054                 DRM_ERROR("Failed to map ringbuffer.\n");
1055                 ret = -EINVAL;
1056                 goto err_unpin;
1057         }
1058
1059         ring->virtual_start = ring->map.handle;
1060         ret = ring->init(ring);
1061         if (ret)
1062                 goto err_unmap;
1063
1064         /* Workaround an erratum on the i830 which causes a hang if
1065          * the TAIL pointer points to within the last 2 cachelines
1066          * of the buffer.
1067          */
1068         ring->effective_size = ring->size;
1069         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1070                 ring->effective_size -= 128;
1071
1072         return 0;
1073
1074 err_unmap:
1075         drm_core_ioremapfree(&ring->map, dev);
1076 err_unpin:
1077         i915_gem_object_unpin(obj);
1078 err_unref:
1079         drm_gem_object_unreference(&obj->base);
1080         ring->obj = NULL;
1081 err_hws:
1082         cleanup_status_page(ring);
1083         return ret;
1084 }
1085
1086 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1087 {
1088         struct drm_i915_private *dev_priv;
1089         int ret;
1090
1091         if (ring->obj == NULL)
1092                 return;
1093
1094         /* Disable the ring buffer. The ring must be idle at this point */
1095         dev_priv = ring->dev->dev_private;
1096         ret = intel_wait_ring_idle(ring);
1097         if (ret)
1098                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1099                           ring->name, ret);
1100
1101         I915_WRITE_CTL(ring, 0);
1102
1103         drm_core_ioremapfree(&ring->map, ring->dev);
1104
1105         i915_gem_object_unpin(ring->obj);
1106         drm_gem_object_unreference(&ring->obj->base);
1107         ring->obj = NULL;
1108
1109         if (ring->cleanup)
1110                 ring->cleanup(ring);
1111
1112         cleanup_status_page(ring);
1113 }
1114
1115 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1116 {
1117         unsigned int *virt;
1118         int rem = ring->size - ring->tail;
1119
1120         if (ring->space < rem) {
1121                 int ret = intel_wait_ring_buffer(ring, rem);
1122                 if (ret)
1123                         return ret;
1124         }
1125
1126         virt = (unsigned int *)(ring->virtual_start + ring->tail);
1127         rem /= 8;
1128         while (rem--) {
1129                 *virt++ = MI_NOOP;
1130                 *virt++ = MI_NOOP;
1131         }
1132
1133         ring->tail = 0;
1134         ring->space = ring_space(ring);
1135
1136         return 0;
1137 }
1138
1139 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1140 {
1141         struct drm_device *dev = ring->dev;
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143         unsigned long end;
1144
1145         trace_i915_ring_wait_begin(ring);
1146         end = jiffies + 3 * HZ;
1147         do {
1148                 ring->head = I915_READ_HEAD(ring);
1149                 ring->space = ring_space(ring);
1150                 if (ring->space >= n) {
1151                         trace_i915_ring_wait_end(ring);
1152                         return 0;
1153                 }
1154
1155                 if (dev->primary->master) {
1156                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1157                         if (master_priv->sarea_priv)
1158                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1159                 }
1160
1161                 msleep(1);
1162                 if (atomic_read(&dev_priv->mm.wedged))
1163                         return -EAGAIN;
1164         } while (!time_after(jiffies, end));
1165         trace_i915_ring_wait_end(ring);
1166         return -EBUSY;
1167 }
1168
1169 int intel_ring_begin(struct intel_ring_buffer *ring,
1170                      int num_dwords)
1171 {
1172         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1173         int n = 4*num_dwords;
1174         int ret;
1175
1176         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1177                 return -EIO;
1178
1179         if (unlikely(ring->tail + n > ring->effective_size)) {
1180                 ret = intel_wrap_ring_buffer(ring);
1181                 if (unlikely(ret))
1182                         return ret;
1183         }
1184
1185         if (unlikely(ring->space < n)) {
1186                 ret = intel_wait_ring_buffer(ring, n);
1187                 if (unlikely(ret))
1188                         return ret;
1189         }
1190
1191         ring->space -= n;
1192         return 0;
1193 }
1194
1195 void intel_ring_advance(struct intel_ring_buffer *ring)
1196 {
1197         ring->tail &= ring->size - 1;
1198         ring->write_tail(ring, ring->tail);
1199 }
1200
1201 static const struct intel_ring_buffer render_ring = {
1202         .name                   = "render ring",
1203         .id                     = RING_RENDER,
1204         .mmio_base              = RENDER_RING_BASE,
1205         .size                   = 32 * PAGE_SIZE,
1206         .init                   = init_render_ring,
1207         .write_tail             = ring_write_tail,
1208         .flush                  = render_ring_flush,
1209         .add_request            = render_ring_add_request,
1210         .get_seqno              = ring_get_seqno,
1211         .irq_get                = render_ring_get_irq,
1212         .irq_put                = render_ring_put_irq,
1213         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1214         .cleanup                = render_ring_cleanup,
1215         .sync_to                = render_ring_sync_to,
1216         .semaphore_register     = {MI_SEMAPHORE_SYNC_INVALID,
1217                                    MI_SEMAPHORE_SYNC_RV,
1218                                    MI_SEMAPHORE_SYNC_RB},
1219         .signal_mbox            = {GEN6_VRSYNC, GEN6_BRSYNC},
1220 };
1221
1222 /* ring buffer for bit-stream decoder */
1223
1224 static const struct intel_ring_buffer bsd_ring = {
1225         .name                   = "bsd ring",
1226         .id                     = RING_BSD,
1227         .mmio_base              = BSD_RING_BASE,
1228         .size                   = 32 * PAGE_SIZE,
1229         .init                   = init_ring_common,
1230         .write_tail             = ring_write_tail,
1231         .flush                  = bsd_ring_flush,
1232         .add_request            = ring_add_request,
1233         .get_seqno              = ring_get_seqno,
1234         .irq_get                = bsd_ring_get_irq,
1235         .irq_put                = bsd_ring_put_irq,
1236         .dispatch_execbuffer    = ring_dispatch_execbuffer,
1237 };
1238
1239
1240 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1241                                      u32 value)
1242 {
1243         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1244
1245        /* Every tail move must follow the sequence below */
1246         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1247                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1248                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1249         I915_WRITE(GEN6_BSD_RNCID, 0x0);
1250
1251         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1252                 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1253                 50))
1254         DRM_ERROR("timed out waiting for IDLE Indicator\n");
1255
1256         I915_WRITE_TAIL(ring, value);
1257         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1258                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1259                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1260 }
1261
1262 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1263                            u32 invalidate, u32 flush)
1264 {
1265         uint32_t cmd;
1266         int ret;
1267
1268         ret = intel_ring_begin(ring, 4);
1269         if (ret)
1270                 return ret;
1271
1272         cmd = MI_FLUSH_DW;
1273         if (invalidate & I915_GEM_GPU_DOMAINS)
1274                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1275         intel_ring_emit(ring, cmd);
1276         intel_ring_emit(ring, 0);
1277         intel_ring_emit(ring, 0);
1278         intel_ring_emit(ring, MI_NOOP);
1279         intel_ring_advance(ring);
1280         return 0;
1281 }
1282
1283 static int
1284 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1285                               u32 offset, u32 len)
1286 {
1287         int ret;
1288
1289         ret = intel_ring_begin(ring, 2);
1290         if (ret)
1291                 return ret;
1292
1293         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1294         /* bit0-7 is the length on GEN6+ */
1295         intel_ring_emit(ring, offset);
1296         intel_ring_advance(ring);
1297
1298         return 0;
1299 }
1300
1301 static bool
1302 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1303 {
1304         return gen6_ring_get_irq(ring,
1305                                  GT_USER_INTERRUPT,
1306                                  GEN6_RENDER_USER_INTERRUPT);
1307 }
1308
1309 static void
1310 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1311 {
1312         return gen6_ring_put_irq(ring,
1313                                  GT_USER_INTERRUPT,
1314                                  GEN6_RENDER_USER_INTERRUPT);
1315 }
1316
1317 static bool
1318 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1319 {
1320         return gen6_ring_get_irq(ring,
1321                                  GT_GEN6_BSD_USER_INTERRUPT,
1322                                  GEN6_BSD_USER_INTERRUPT);
1323 }
1324
1325 static void
1326 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1327 {
1328         return gen6_ring_put_irq(ring,
1329                                  GT_GEN6_BSD_USER_INTERRUPT,
1330                                  GEN6_BSD_USER_INTERRUPT);
1331 }
1332
1333 /* ring buffer for Video Codec for Gen6+ */
1334 static const struct intel_ring_buffer gen6_bsd_ring = {
1335         .name                   = "gen6 bsd ring",
1336         .id                     = RING_BSD,
1337         .mmio_base              = GEN6_BSD_RING_BASE,
1338         .size                   = 32 * PAGE_SIZE,
1339         .init                   = init_ring_common,
1340         .write_tail             = gen6_bsd_ring_write_tail,
1341         .flush                  = gen6_ring_flush,
1342         .add_request            = gen6_add_request,
1343         .get_seqno              = gen6_ring_get_seqno,
1344         .irq_get                = gen6_bsd_ring_get_irq,
1345         .irq_put                = gen6_bsd_ring_put_irq,
1346         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1347         .sync_to                = gen6_bsd_ring_sync_to,
1348         .semaphore_register     = {MI_SEMAPHORE_SYNC_VR,
1349                                    MI_SEMAPHORE_SYNC_INVALID,
1350                                    MI_SEMAPHORE_SYNC_VB},
1351         .signal_mbox            = {GEN6_RVSYNC, GEN6_BVSYNC},
1352 };
1353
1354 /* Blitter support (SandyBridge+) */
1355
1356 static bool
1357 blt_ring_get_irq(struct intel_ring_buffer *ring)
1358 {
1359         return gen6_ring_get_irq(ring,
1360                                  GT_BLT_USER_INTERRUPT,
1361                                  GEN6_BLITTER_USER_INTERRUPT);
1362 }
1363
1364 static void
1365 blt_ring_put_irq(struct intel_ring_buffer *ring)
1366 {
1367         gen6_ring_put_irq(ring,
1368                           GT_BLT_USER_INTERRUPT,
1369                           GEN6_BLITTER_USER_INTERRUPT);
1370 }
1371
1372
1373 /* Workaround for some stepping of SNB,
1374  * each time when BLT engine ring tail moved,
1375  * the first command in the ring to be parsed
1376  * should be MI_BATCH_BUFFER_START
1377  */
1378 #define NEED_BLT_WORKAROUND(dev) \
1379         (IS_GEN6(dev) && (dev->pdev->revision < 8))
1380
1381 static inline struct drm_i915_gem_object *
1382 to_blt_workaround(struct intel_ring_buffer *ring)
1383 {
1384         return ring->private;
1385 }
1386
1387 static int blt_ring_init(struct intel_ring_buffer *ring)
1388 {
1389         if (NEED_BLT_WORKAROUND(ring->dev)) {
1390                 struct drm_i915_gem_object *obj;
1391                 u32 *ptr;
1392                 int ret;
1393
1394                 obj = i915_gem_alloc_object(ring->dev, 4096);
1395                 if (obj == NULL)
1396                         return -ENOMEM;
1397
1398                 ret = i915_gem_object_pin(obj, 4096, true);
1399                 if (ret) {
1400                         drm_gem_object_unreference(&obj->base);
1401                         return ret;
1402                 }
1403
1404                 ptr = kmap(obj->pages[0]);
1405                 *ptr++ = MI_BATCH_BUFFER_END;
1406                 *ptr++ = MI_NOOP;
1407                 kunmap(obj->pages[0]);
1408
1409                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1410                 if (ret) {
1411                         i915_gem_object_unpin(obj);
1412                         drm_gem_object_unreference(&obj->base);
1413                         return ret;
1414                 }
1415
1416                 ring->private = obj;
1417         }
1418
1419         return init_ring_common(ring);
1420 }
1421
1422 static int blt_ring_begin(struct intel_ring_buffer *ring,
1423                           int num_dwords)
1424 {
1425         if (ring->private) {
1426                 int ret = intel_ring_begin(ring, num_dwords+2);
1427                 if (ret)
1428                         return ret;
1429
1430                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1431                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1432
1433                 return 0;
1434         } else
1435                 return intel_ring_begin(ring, 4);
1436 }
1437
1438 static int blt_ring_flush(struct intel_ring_buffer *ring,
1439                           u32 invalidate, u32 flush)
1440 {
1441         uint32_t cmd;
1442         int ret;
1443
1444         ret = blt_ring_begin(ring, 4);
1445         if (ret)
1446                 return ret;
1447
1448         cmd = MI_FLUSH_DW;
1449         if (invalidate & I915_GEM_DOMAIN_RENDER)
1450                 cmd |= MI_INVALIDATE_TLB;
1451         intel_ring_emit(ring, cmd);
1452         intel_ring_emit(ring, 0);
1453         intel_ring_emit(ring, 0);
1454         intel_ring_emit(ring, MI_NOOP);
1455         intel_ring_advance(ring);
1456         return 0;
1457 }
1458
1459 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1460 {
1461         if (!ring->private)
1462                 return;
1463
1464         i915_gem_object_unpin(ring->private);
1465         drm_gem_object_unreference(ring->private);
1466         ring->private = NULL;
1467 }
1468
1469 static const struct intel_ring_buffer gen6_blt_ring = {
1470         .name                   = "blt ring",
1471         .id                     = RING_BLT,
1472         .mmio_base              = BLT_RING_BASE,
1473         .size                   = 32 * PAGE_SIZE,
1474         .init                   = blt_ring_init,
1475         .write_tail             = ring_write_tail,
1476         .flush                  = blt_ring_flush,
1477         .add_request            = gen6_add_request,
1478         .get_seqno              = gen6_ring_get_seqno,
1479         .irq_get                = blt_ring_get_irq,
1480         .irq_put                = blt_ring_put_irq,
1481         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1482         .cleanup                = blt_ring_cleanup,
1483         .sync_to                = gen6_blt_ring_sync_to,
1484         .semaphore_register     = {MI_SEMAPHORE_SYNC_BR,
1485                                    MI_SEMAPHORE_SYNC_BV,
1486                                    MI_SEMAPHORE_SYNC_INVALID},
1487         .signal_mbox            = {GEN6_RBSYNC, GEN6_VBSYNC},
1488 };
1489
1490 int intel_init_render_ring_buffer(struct drm_device *dev)
1491 {
1492         drm_i915_private_t *dev_priv = dev->dev_private;
1493         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1494
1495         *ring = render_ring;
1496         if (INTEL_INFO(dev)->gen >= 6) {
1497                 ring->add_request = gen6_add_request;
1498                 ring->flush = gen6_render_ring_flush;
1499                 ring->irq_get = gen6_render_ring_get_irq;
1500                 ring->irq_put = gen6_render_ring_put_irq;
1501                 ring->get_seqno = gen6_ring_get_seqno;
1502         } else if (IS_GEN5(dev)) {
1503                 ring->add_request = pc_render_add_request;
1504                 ring->get_seqno = pc_render_get_seqno;
1505         }
1506
1507         if (!I915_NEED_GFX_HWS(dev)) {
1508                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1509                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1510         }
1511
1512         return intel_init_ring_buffer(dev, ring);
1513 }
1514
1515 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1516 {
1517         drm_i915_private_t *dev_priv = dev->dev_private;
1518         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1519
1520         *ring = render_ring;
1521         if (INTEL_INFO(dev)->gen >= 6) {
1522                 ring->add_request = gen6_add_request;
1523                 ring->irq_get = gen6_render_ring_get_irq;
1524                 ring->irq_put = gen6_render_ring_put_irq;
1525         } else if (IS_GEN5(dev)) {
1526                 ring->add_request = pc_render_add_request;
1527                 ring->get_seqno = pc_render_get_seqno;
1528         }
1529
1530         if (!I915_NEED_GFX_HWS(dev))
1531                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1532
1533         ring->dev = dev;
1534         INIT_LIST_HEAD(&ring->active_list);
1535         INIT_LIST_HEAD(&ring->request_list);
1536         INIT_LIST_HEAD(&ring->gpu_write_list);
1537
1538         ring->size = size;
1539         ring->effective_size = ring->size;
1540         if (IS_I830(ring->dev))
1541                 ring->effective_size -= 128;
1542
1543         ring->map.offset = start;
1544         ring->map.size = size;
1545         ring->map.type = 0;
1546         ring->map.flags = 0;
1547         ring->map.mtrr = 0;
1548
1549         drm_core_ioremap_wc(&ring->map, dev);
1550         if (ring->map.handle == NULL) {
1551                 DRM_ERROR("can not ioremap virtual address for"
1552                           " ring buffer\n");
1553                 return -ENOMEM;
1554         }
1555
1556         ring->virtual_start = (void __force __iomem *)ring->map.handle;
1557         return 0;
1558 }
1559
1560 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1561 {
1562         drm_i915_private_t *dev_priv = dev->dev_private;
1563         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1564
1565         if (IS_GEN6(dev) || IS_GEN7(dev))
1566                 *ring = gen6_bsd_ring;
1567         else
1568                 *ring = bsd_ring;
1569
1570         return intel_init_ring_buffer(dev, ring);
1571 }
1572
1573 int intel_init_blt_ring_buffer(struct drm_device *dev)
1574 {
1575         drm_i915_private_t *dev_priv = dev->dev_private;
1576         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1577
1578         *ring = gen6_blt_ring;
1579
1580         return intel_init_ring_buffer(dev, ring);
1581 }