2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
41 struct drm_i915_gem_object *obj;
42 volatile u32 *cpu_page;
46 static inline int ring_space(struct intel_ring_buffer *ring)
48 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
69 ret = intel_ring_begin(ring, 2);
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
85 struct drm_device *dev = ring->dev;
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
101 * I915_GEM_DOMAIN_COMMAND may not exist?
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
127 ret = intel_ring_begin(ring, 2);
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 * And the workaround for these two requires this workaround first:
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 struct pipe_control *pc = ring->private;
179 u32 scratch_addr = pc->gtt_offset + 128;
183 ret = intel_ring_begin(ring, 6);
187 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
189 PIPE_CONTROL_STALL_AT_SCOREBOARD);
190 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
191 intel_ring_emit(ring, 0); /* low dword */
192 intel_ring_emit(ring, 0); /* high dword */
193 intel_ring_emit(ring, MI_NOOP);
194 intel_ring_advance(ring);
196 ret = intel_ring_begin(ring, 6);
200 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
202 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, MI_NOOP);
206 intel_ring_advance(ring);
212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
213 u32 invalidate_domains, u32 flush_domains)
216 struct pipe_control *pc = ring->private;
217 u32 scratch_addr = pc->gtt_offset + 128;
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret = intel_emit_post_sync_nonzero_flush(ring);
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
236 flags |= PIPE_CONTROL_CS_STALL;
238 if (invalidate_domains) {
239 flags |= PIPE_CONTROL_TLB_INVALIDATE;
240 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
246 * TLB invalidate requires a post-sync write.
248 flags |= PIPE_CONTROL_QW_WRITE;
251 ret = intel_ring_begin(ring, 4);
255 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring, flags);
257 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
258 intel_ring_emit(ring, 0);
259 intel_ring_advance(ring);
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
269 ret = intel_ring_begin(ring, 4);
273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
275 PIPE_CONTROL_STALL_AT_SCOREBOARD);
276 intel_ring_emit(ring, 0);
277 intel_ring_emit(ring, 0);
278 intel_ring_advance(ring);
284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
285 u32 invalidate_domains, u32 flush_domains)
288 struct pipe_control *pc = ring->private;
289 u32 scratch_addr = pc->gtt_offset + 128;
293 * Ensure that any following seqno writes only happen when the render
294 * cache is indeed flushed.
296 * Workaround: 4th PIPE_CONTROL command (except the ones with only
297 * read-cache invalidate bits set) must have the CS_STALL bit set. We
298 * don't try to be clever and just set it unconditionally.
300 flags |= PIPE_CONTROL_CS_STALL;
302 /* Just flush everything. Experiments have shown that reducing the
303 * number of bits based on the write domains has little performance
307 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
308 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
310 if (invalidate_domains) {
311 flags |= PIPE_CONTROL_TLB_INVALIDATE;
312 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
313 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
314 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
315 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
316 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
318 * TLB invalidate requires a post-sync write.
320 flags |= PIPE_CONTROL_QW_WRITE;
322 /* Workaround: we must issue a pipe_control with CS-stall bit
323 * set before a pipe_control command that has the state cache
324 * invalidate bit set. */
325 gen7_render_ring_cs_stall_wa(ring);
328 ret = intel_ring_begin(ring, 4);
332 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
333 intel_ring_emit(ring, flags);
334 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
335 intel_ring_emit(ring, 0);
336 intel_ring_advance(ring);
341 static void ring_write_tail(struct intel_ring_buffer *ring,
344 drm_i915_private_t *dev_priv = ring->dev->dev_private;
345 I915_WRITE_TAIL(ring, value);
348 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
350 drm_i915_private_t *dev_priv = ring->dev->dev_private;
351 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
352 RING_ACTHD(ring->mmio_base) : ACTHD;
354 return I915_READ(acthd_reg);
357 static int init_ring_common(struct intel_ring_buffer *ring)
359 struct drm_device *dev = ring->dev;
360 drm_i915_private_t *dev_priv = dev->dev_private;
361 struct drm_i915_gem_object *obj = ring->obj;
365 if (HAS_FORCE_WAKE(dev))
366 gen6_gt_force_wake_get(dev_priv);
368 /* Stop the ring if it's running. */
369 I915_WRITE_CTL(ring, 0);
370 I915_WRITE_HEAD(ring, 0);
371 ring->write_tail(ring, 0);
373 head = I915_READ_HEAD(ring) & HEAD_ADDR;
375 /* G45 ring initialization fails to reset head to zero */
377 DRM_DEBUG_KMS("%s head not reset to zero "
378 "ctl %08x head %08x tail %08x start %08x\n",
381 I915_READ_HEAD(ring),
382 I915_READ_TAIL(ring),
383 I915_READ_START(ring));
385 I915_WRITE_HEAD(ring, 0);
387 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
388 DRM_ERROR("failed to set %s head to zero "
389 "ctl %08x head %08x tail %08x start %08x\n",
392 I915_READ_HEAD(ring),
393 I915_READ_TAIL(ring),
394 I915_READ_START(ring));
398 /* Initialize the ring. This must happen _after_ we've cleared the ring
399 * registers with the above sequence (the readback of the HEAD registers
400 * also enforces ordering), otherwise the hw might lose the new ring
401 * register values. */
402 I915_WRITE_START(ring, obj->gtt_offset);
404 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
407 /* If the head is still not zero, the ring is dead */
408 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
409 I915_READ_START(ring) == obj->gtt_offset &&
410 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
411 DRM_ERROR("%s initialization failed "
412 "ctl %08x head %08x tail %08x start %08x\n",
415 I915_READ_HEAD(ring),
416 I915_READ_TAIL(ring),
417 I915_READ_START(ring));
422 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
423 i915_kernel_lost_context(ring->dev);
425 ring->head = I915_READ_HEAD(ring);
426 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
427 ring->space = ring_space(ring);
428 ring->last_retired_head = -1;
432 if (HAS_FORCE_WAKE(dev))
433 gen6_gt_force_wake_put(dev_priv);
439 init_pipe_control(struct intel_ring_buffer *ring)
441 struct pipe_control *pc;
442 struct drm_i915_gem_object *obj;
448 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
452 obj = i915_gem_alloc_object(ring->dev, 4096);
454 DRM_ERROR("Failed to allocate seqno page\n");
459 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
461 ret = i915_gem_object_pin(obj, 4096, true, false);
465 pc->gtt_offset = obj->gtt_offset;
466 pc->cpu_page = kmap(sg_page(obj->pages->sgl));
467 if (pc->cpu_page == NULL)
475 i915_gem_object_unpin(obj);
477 drm_gem_object_unreference(&obj->base);
484 cleanup_pipe_control(struct intel_ring_buffer *ring)
486 struct pipe_control *pc = ring->private;
487 struct drm_i915_gem_object *obj;
494 kunmap(sg_page(obj->pages->sgl));
495 i915_gem_object_unpin(obj);
496 drm_gem_object_unreference(&obj->base);
499 ring->private = NULL;
502 static int init_render_ring(struct intel_ring_buffer *ring)
504 struct drm_device *dev = ring->dev;
505 struct drm_i915_private *dev_priv = dev->dev_private;
506 int ret = init_ring_common(ring);
508 if (INTEL_INFO(dev)->gen > 3) {
509 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
511 I915_WRITE(GFX_MODE_GEN7,
512 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
513 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
516 if (INTEL_INFO(dev)->gen >= 5) {
517 ret = init_pipe_control(ring);
523 /* From the Sandybridge PRM, volume 1 part 3, page 24:
524 * "If this bit is set, STCunit will have LRA as replacement
525 * policy. [...] This bit must be reset. LRA replacement
526 * policy is not supported."
528 I915_WRITE(CACHE_MODE_0,
529 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
531 /* This is not explicitly set for GEN6, so read the register.
532 * see intel_ring_mi_set_context() for why we care.
533 * TODO: consider explicitly setting the bit for GEN5
535 ring->itlb_before_ctx_switch =
536 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
539 if (INTEL_INFO(dev)->gen >= 6)
540 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
542 if (HAS_L3_GPU_CACHE(dev))
543 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
548 static void render_ring_cleanup(struct intel_ring_buffer *ring)
553 cleanup_pipe_control(ring);
557 update_mboxes(struct intel_ring_buffer *ring,
561 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
562 MI_SEMAPHORE_GLOBAL_GTT |
563 MI_SEMAPHORE_REGISTER |
564 MI_SEMAPHORE_UPDATE);
565 intel_ring_emit(ring, seqno);
566 intel_ring_emit(ring, mmio_offset);
570 * gen6_add_request - Update the semaphore mailbox registers
572 * @ring - ring that is adding a request
573 * @seqno - return seqno stuck into the ring
575 * Update the mailbox registers in the *other* rings with the current seqno.
576 * This acts like a signal in the canonical semaphore.
579 gen6_add_request(struct intel_ring_buffer *ring,
586 ret = intel_ring_begin(ring, 10);
590 mbox1_reg = ring->signal_mbox[0];
591 mbox2_reg = ring->signal_mbox[1];
593 *seqno = i915_gem_next_request_seqno(ring);
595 update_mboxes(ring, *seqno, mbox1_reg);
596 update_mboxes(ring, *seqno, mbox2_reg);
597 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
598 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
599 intel_ring_emit(ring, *seqno);
600 intel_ring_emit(ring, MI_USER_INTERRUPT);
601 intel_ring_advance(ring);
607 * intel_ring_sync - sync the waiter to the signaller on seqno
609 * @waiter - ring that is waiting
610 * @signaller - ring which has, or will signal
611 * @seqno - seqno which the waiter will block on
614 gen6_ring_sync(struct intel_ring_buffer *waiter,
615 struct intel_ring_buffer *signaller,
619 u32 dw1 = MI_SEMAPHORE_MBOX |
620 MI_SEMAPHORE_COMPARE |
621 MI_SEMAPHORE_REGISTER;
623 /* Throughout all of the GEM code, seqno passed implies our current
624 * seqno is >= the last seqno executed. However for hardware the
625 * comparison is strictly greater than.
629 WARN_ON(signaller->semaphore_register[waiter->id] ==
630 MI_SEMAPHORE_SYNC_INVALID);
632 ret = intel_ring_begin(waiter, 4);
636 intel_ring_emit(waiter,
637 dw1 | signaller->semaphore_register[waiter->id]);
638 intel_ring_emit(waiter, seqno);
639 intel_ring_emit(waiter, 0);
640 intel_ring_emit(waiter, MI_NOOP);
641 intel_ring_advance(waiter);
646 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
648 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
649 PIPE_CONTROL_DEPTH_STALL); \
650 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
651 intel_ring_emit(ring__, 0); \
652 intel_ring_emit(ring__, 0); \
656 pc_render_add_request(struct intel_ring_buffer *ring,
659 u32 seqno = i915_gem_next_request_seqno(ring);
660 struct pipe_control *pc = ring->private;
661 u32 scratch_addr = pc->gtt_offset + 128;
664 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
665 * incoherent with writes to memory, i.e. completely fubar,
666 * so we need to use PIPE_NOTIFY instead.
668 * However, we also need to workaround the qword write
669 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
670 * memory before requesting an interrupt.
672 ret = intel_ring_begin(ring, 32);
676 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
677 PIPE_CONTROL_WRITE_FLUSH |
678 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
679 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
680 intel_ring_emit(ring, seqno);
681 intel_ring_emit(ring, 0);
682 PIPE_CONTROL_FLUSH(ring, scratch_addr);
683 scratch_addr += 128; /* write to separate cachelines */
684 PIPE_CONTROL_FLUSH(ring, scratch_addr);
686 PIPE_CONTROL_FLUSH(ring, scratch_addr);
688 PIPE_CONTROL_FLUSH(ring, scratch_addr);
690 PIPE_CONTROL_FLUSH(ring, scratch_addr);
692 PIPE_CONTROL_FLUSH(ring, scratch_addr);
694 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
695 PIPE_CONTROL_WRITE_FLUSH |
696 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
697 PIPE_CONTROL_NOTIFY);
698 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
699 intel_ring_emit(ring, seqno);
700 intel_ring_emit(ring, 0);
701 intel_ring_advance(ring);
708 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
710 /* Workaround to force correct ordering between irq and seqno writes on
711 * ivb (and maybe also on snb) by reading from a CS register (like
712 * ACTHD) before reading the status page. */
714 intel_ring_get_active_head(ring);
715 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
719 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
721 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
725 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
727 struct pipe_control *pc = ring->private;
728 return pc->cpu_page[0];
732 gen5_ring_get_irq(struct intel_ring_buffer *ring)
734 struct drm_device *dev = ring->dev;
735 drm_i915_private_t *dev_priv = dev->dev_private;
738 if (!dev->irq_enabled)
741 spin_lock_irqsave(&dev_priv->irq_lock, flags);
742 if (ring->irq_refcount++ == 0) {
743 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
744 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
747 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
753 gen5_ring_put_irq(struct intel_ring_buffer *ring)
755 struct drm_device *dev = ring->dev;
756 drm_i915_private_t *dev_priv = dev->dev_private;
759 spin_lock_irqsave(&dev_priv->irq_lock, flags);
760 if (--ring->irq_refcount == 0) {
761 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
762 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
765 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
769 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
771 struct drm_device *dev = ring->dev;
772 drm_i915_private_t *dev_priv = dev->dev_private;
775 if (!dev->irq_enabled)
778 spin_lock_irqsave(&dev_priv->irq_lock, flags);
779 if (ring->irq_refcount++ == 0) {
780 dev_priv->irq_mask &= ~ring->irq_enable_mask;
781 I915_WRITE(IMR, dev_priv->irq_mask);
784 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
790 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
792 struct drm_device *dev = ring->dev;
793 drm_i915_private_t *dev_priv = dev->dev_private;
796 spin_lock_irqsave(&dev_priv->irq_lock, flags);
797 if (--ring->irq_refcount == 0) {
798 dev_priv->irq_mask |= ring->irq_enable_mask;
799 I915_WRITE(IMR, dev_priv->irq_mask);
802 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
806 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
808 struct drm_device *dev = ring->dev;
809 drm_i915_private_t *dev_priv = dev->dev_private;
812 if (!dev->irq_enabled)
815 spin_lock_irqsave(&dev_priv->irq_lock, flags);
816 if (ring->irq_refcount++ == 0) {
817 dev_priv->irq_mask &= ~ring->irq_enable_mask;
818 I915_WRITE16(IMR, dev_priv->irq_mask);
821 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
827 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
829 struct drm_device *dev = ring->dev;
830 drm_i915_private_t *dev_priv = dev->dev_private;
833 spin_lock_irqsave(&dev_priv->irq_lock, flags);
834 if (--ring->irq_refcount == 0) {
835 dev_priv->irq_mask |= ring->irq_enable_mask;
836 I915_WRITE16(IMR, dev_priv->irq_mask);
839 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
842 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
844 struct drm_device *dev = ring->dev;
845 drm_i915_private_t *dev_priv = ring->dev->dev_private;
848 /* The ring status page addresses are no longer next to the rest of
849 * the ring registers as of gen7.
854 mmio = RENDER_HWS_PGA_GEN7;
857 mmio = BLT_HWS_PGA_GEN7;
860 mmio = BSD_HWS_PGA_GEN7;
863 } else if (IS_GEN6(ring->dev)) {
864 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
866 mmio = RING_HWS_PGA(ring->mmio_base);
869 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
874 bsd_ring_flush(struct intel_ring_buffer *ring,
875 u32 invalidate_domains,
880 ret = intel_ring_begin(ring, 2);
884 intel_ring_emit(ring, MI_FLUSH);
885 intel_ring_emit(ring, MI_NOOP);
886 intel_ring_advance(ring);
891 i9xx_add_request(struct intel_ring_buffer *ring,
897 ret = intel_ring_begin(ring, 4);
901 seqno = i915_gem_next_request_seqno(ring);
903 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
904 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
905 intel_ring_emit(ring, seqno);
906 intel_ring_emit(ring, MI_USER_INTERRUPT);
907 intel_ring_advance(ring);
914 gen6_ring_get_irq(struct intel_ring_buffer *ring)
916 struct drm_device *dev = ring->dev;
917 drm_i915_private_t *dev_priv = dev->dev_private;
920 if (!dev->irq_enabled)
923 /* It looks like we need to prevent the gt from suspending while waiting
924 * for an notifiy irq, otherwise irqs seem to get lost on at least the
925 * blt/bsd rings on ivb. */
926 gen6_gt_force_wake_get(dev_priv);
928 spin_lock_irqsave(&dev_priv->irq_lock, flags);
929 if (ring->irq_refcount++ == 0) {
930 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
931 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
932 GEN6_RENDER_L3_PARITY_ERROR));
934 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
935 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
936 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
939 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
945 gen6_ring_put_irq(struct intel_ring_buffer *ring)
947 struct drm_device *dev = ring->dev;
948 drm_i915_private_t *dev_priv = dev->dev_private;
951 spin_lock_irqsave(&dev_priv->irq_lock, flags);
952 if (--ring->irq_refcount == 0) {
953 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
954 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
956 I915_WRITE_IMR(ring, ~0);
957 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
958 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
961 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
963 gen6_gt_force_wake_put(dev_priv);
967 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
971 ret = intel_ring_begin(ring, 2);
975 intel_ring_emit(ring,
976 MI_BATCH_BUFFER_START |
978 MI_BATCH_NON_SECURE_I965);
979 intel_ring_emit(ring, offset);
980 intel_ring_advance(ring);
986 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
991 ret = intel_ring_begin(ring, 4);
995 intel_ring_emit(ring, MI_BATCH_BUFFER);
996 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
997 intel_ring_emit(ring, offset + len - 8);
998 intel_ring_emit(ring, 0);
999 intel_ring_advance(ring);
1005 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1006 u32 offset, u32 len)
1010 ret = intel_ring_begin(ring, 2);
1014 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1015 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
1016 intel_ring_advance(ring);
1021 static void cleanup_status_page(struct intel_ring_buffer *ring)
1023 struct drm_i915_gem_object *obj;
1025 obj = ring->status_page.obj;
1029 kunmap(sg_page(obj->pages->sgl));
1030 i915_gem_object_unpin(obj);
1031 drm_gem_object_unreference(&obj->base);
1032 ring->status_page.obj = NULL;
1035 static int init_status_page(struct intel_ring_buffer *ring)
1037 struct drm_device *dev = ring->dev;
1038 struct drm_i915_gem_object *obj;
1041 obj = i915_gem_alloc_object(dev, 4096);
1043 DRM_ERROR("Failed to allocate status page\n");
1048 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1050 ret = i915_gem_object_pin(obj, 4096, true, false);
1055 ring->status_page.gfx_addr = obj->gtt_offset;
1056 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1057 if (ring->status_page.page_addr == NULL) {
1061 ring->status_page.obj = obj;
1062 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1064 intel_ring_setup_status_page(ring);
1065 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1066 ring->name, ring->status_page.gfx_addr);
1071 i915_gem_object_unpin(obj);
1073 drm_gem_object_unreference(&obj->base);
1078 static int intel_init_ring_buffer(struct drm_device *dev,
1079 struct intel_ring_buffer *ring)
1081 struct drm_i915_gem_object *obj;
1082 struct drm_i915_private *dev_priv = dev->dev_private;
1086 INIT_LIST_HEAD(&ring->active_list);
1087 INIT_LIST_HEAD(&ring->request_list);
1088 ring->size = 32 * PAGE_SIZE;
1090 init_waitqueue_head(&ring->irq_queue);
1092 if (I915_NEED_GFX_HWS(dev)) {
1093 ret = init_status_page(ring);
1098 obj = i915_gem_alloc_object(dev, ring->size);
1100 DRM_ERROR("Failed to allocate ringbuffer\n");
1107 ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1111 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1115 ring->virtual_start =
1116 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1118 if (ring->virtual_start == NULL) {
1119 DRM_ERROR("Failed to map ringbuffer.\n");
1124 ret = ring->init(ring);
1128 /* Workaround an erratum on the i830 which causes a hang if
1129 * the TAIL pointer points to within the last 2 cachelines
1132 ring->effective_size = ring->size;
1133 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1134 ring->effective_size -= 128;
1139 iounmap(ring->virtual_start);
1141 i915_gem_object_unpin(obj);
1143 drm_gem_object_unreference(&obj->base);
1146 cleanup_status_page(ring);
1150 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1152 struct drm_i915_private *dev_priv;
1155 if (ring->obj == NULL)
1158 /* Disable the ring buffer. The ring must be idle at this point */
1159 dev_priv = ring->dev->dev_private;
1160 ret = intel_wait_ring_idle(ring);
1162 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1165 I915_WRITE_CTL(ring, 0);
1167 iounmap(ring->virtual_start);
1169 i915_gem_object_unpin(ring->obj);
1170 drm_gem_object_unreference(&ring->obj->base);
1174 ring->cleanup(ring);
1176 cleanup_status_page(ring);
1179 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1181 uint32_t __iomem *virt;
1182 int rem = ring->size - ring->tail;
1184 if (ring->space < rem) {
1185 int ret = intel_wait_ring_buffer(ring, rem);
1190 virt = ring->virtual_start + ring->tail;
1193 iowrite32(MI_NOOP, virt++);
1196 ring->space = ring_space(ring);
1201 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1205 ret = i915_wait_seqno(ring, seqno);
1207 i915_gem_retire_requests_ring(ring);
1212 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1214 struct drm_i915_gem_request *request;
1218 i915_gem_retire_requests_ring(ring);
1220 if (ring->last_retired_head != -1) {
1221 ring->head = ring->last_retired_head;
1222 ring->last_retired_head = -1;
1223 ring->space = ring_space(ring);
1224 if (ring->space >= n)
1228 list_for_each_entry(request, &ring->request_list, list) {
1231 if (request->tail == -1)
1234 space = request->tail - (ring->tail + 8);
1236 space += ring->size;
1238 seqno = request->seqno;
1242 /* Consume this request in case we need more space than
1243 * is available and so need to prevent a race between
1244 * updating last_retired_head and direct reads of
1245 * I915_RING_HEAD. It also provides a nice sanity check.
1253 ret = intel_ring_wait_seqno(ring, seqno);
1257 if (WARN_ON(ring->last_retired_head == -1))
1260 ring->head = ring->last_retired_head;
1261 ring->last_retired_head = -1;
1262 ring->space = ring_space(ring);
1263 if (WARN_ON(ring->space < n))
1269 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1271 struct drm_device *dev = ring->dev;
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1276 ret = intel_ring_wait_request(ring, n);
1280 trace_i915_ring_wait_begin(ring);
1281 /* With GEM the hangcheck timer should kick us out of the loop,
1282 * leaving it early runs the risk of corrupting GEM state (due
1283 * to running on almost untested codepaths). But on resume
1284 * timers don't work yet, so prevent a complete hang in that
1285 * case by choosing an insanely large timeout. */
1286 end = jiffies + 60 * HZ;
1289 ring->head = I915_READ_HEAD(ring);
1290 ring->space = ring_space(ring);
1291 if (ring->space >= n) {
1292 trace_i915_ring_wait_end(ring);
1296 if (dev->primary->master) {
1297 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1298 if (master_priv->sarea_priv)
1299 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1304 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1307 } while (!time_after(jiffies, end));
1308 trace_i915_ring_wait_end(ring);
1312 int intel_ring_begin(struct intel_ring_buffer *ring,
1315 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1316 int n = 4*num_dwords;
1319 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1323 if (unlikely(ring->tail + n > ring->effective_size)) {
1324 ret = intel_wrap_ring_buffer(ring);
1329 if (unlikely(ring->space < n)) {
1330 ret = intel_wait_ring_buffer(ring, n);
1339 void intel_ring_advance(struct intel_ring_buffer *ring)
1341 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1343 ring->tail &= ring->size - 1;
1344 if (dev_priv->stop_rings & intel_ring_flag(ring))
1346 ring->write_tail(ring, ring->tail);
1350 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1353 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1355 /* Every tail move must follow the sequence below */
1357 /* Disable notification that the ring is IDLE. The GT
1358 * will then assume that it is busy and bring it out of rc6.
1360 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1361 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1363 /* Clear the context id. Here be magic! */
1364 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1366 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1367 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1368 GEN6_BSD_SLEEP_INDICATOR) == 0,
1370 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1372 /* Now that the ring is fully powered up, update the tail */
1373 I915_WRITE_TAIL(ring, value);
1374 POSTING_READ(RING_TAIL(ring->mmio_base));
1376 /* Let the ring send IDLE messages to the GT again,
1377 * and so let it sleep to conserve power when idle.
1379 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1380 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1383 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1384 u32 invalidate, u32 flush)
1389 ret = intel_ring_begin(ring, 4);
1394 if (invalidate & I915_GEM_GPU_DOMAINS)
1395 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1396 intel_ring_emit(ring, cmd);
1397 intel_ring_emit(ring, 0);
1398 intel_ring_emit(ring, 0);
1399 intel_ring_emit(ring, MI_NOOP);
1400 intel_ring_advance(ring);
1405 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1406 u32 offset, u32 len)
1410 ret = intel_ring_begin(ring, 2);
1414 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1415 /* bit0-7 is the length on GEN6+ */
1416 intel_ring_emit(ring, offset);
1417 intel_ring_advance(ring);
1422 /* Blitter support (SandyBridge+) */
1424 static int blt_ring_flush(struct intel_ring_buffer *ring,
1425 u32 invalidate, u32 flush)
1430 ret = intel_ring_begin(ring, 4);
1435 if (invalidate & I915_GEM_DOMAIN_RENDER)
1436 cmd |= MI_INVALIDATE_TLB;
1437 intel_ring_emit(ring, cmd);
1438 intel_ring_emit(ring, 0);
1439 intel_ring_emit(ring, 0);
1440 intel_ring_emit(ring, MI_NOOP);
1441 intel_ring_advance(ring);
1445 int intel_init_render_ring_buffer(struct drm_device *dev)
1447 drm_i915_private_t *dev_priv = dev->dev_private;
1448 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1450 ring->name = "render ring";
1452 ring->mmio_base = RENDER_RING_BASE;
1454 if (INTEL_INFO(dev)->gen >= 6) {
1455 ring->add_request = gen6_add_request;
1456 ring->flush = gen7_render_ring_flush;
1457 if (INTEL_INFO(dev)->gen == 6)
1458 ring->flush = gen6_render_ring_flush;
1459 ring->irq_get = gen6_ring_get_irq;
1460 ring->irq_put = gen6_ring_put_irq;
1461 ring->irq_enable_mask = GT_USER_INTERRUPT;
1462 ring->get_seqno = gen6_ring_get_seqno;
1463 ring->sync_to = gen6_ring_sync;
1464 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1465 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1466 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1467 ring->signal_mbox[0] = GEN6_VRSYNC;
1468 ring->signal_mbox[1] = GEN6_BRSYNC;
1469 } else if (IS_GEN5(dev)) {
1470 ring->add_request = pc_render_add_request;
1471 ring->flush = gen4_render_ring_flush;
1472 ring->get_seqno = pc_render_get_seqno;
1473 ring->irq_get = gen5_ring_get_irq;
1474 ring->irq_put = gen5_ring_put_irq;
1475 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1477 ring->add_request = i9xx_add_request;
1478 if (INTEL_INFO(dev)->gen < 4)
1479 ring->flush = gen2_render_ring_flush;
1481 ring->flush = gen4_render_ring_flush;
1482 ring->get_seqno = ring_get_seqno;
1484 ring->irq_get = i8xx_ring_get_irq;
1485 ring->irq_put = i8xx_ring_put_irq;
1487 ring->irq_get = i9xx_ring_get_irq;
1488 ring->irq_put = i9xx_ring_put_irq;
1490 ring->irq_enable_mask = I915_USER_INTERRUPT;
1492 ring->write_tail = ring_write_tail;
1493 if (INTEL_INFO(dev)->gen >= 6)
1494 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1495 else if (INTEL_INFO(dev)->gen >= 4)
1496 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1497 else if (IS_I830(dev) || IS_845G(dev))
1498 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1500 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1501 ring->init = init_render_ring;
1502 ring->cleanup = render_ring_cleanup;
1505 if (!I915_NEED_GFX_HWS(dev)) {
1506 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1507 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1510 return intel_init_ring_buffer(dev, ring);
1513 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1515 drm_i915_private_t *dev_priv = dev->dev_private;
1516 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1518 ring->name = "render ring";
1520 ring->mmio_base = RENDER_RING_BASE;
1522 if (INTEL_INFO(dev)->gen >= 6) {
1523 /* non-kms not supported on gen6+ */
1527 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1528 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1529 * the special gen5 functions. */
1530 ring->add_request = i9xx_add_request;
1531 if (INTEL_INFO(dev)->gen < 4)
1532 ring->flush = gen2_render_ring_flush;
1534 ring->flush = gen4_render_ring_flush;
1535 ring->get_seqno = ring_get_seqno;
1537 ring->irq_get = i8xx_ring_get_irq;
1538 ring->irq_put = i8xx_ring_put_irq;
1540 ring->irq_get = i9xx_ring_get_irq;
1541 ring->irq_put = i9xx_ring_put_irq;
1543 ring->irq_enable_mask = I915_USER_INTERRUPT;
1544 ring->write_tail = ring_write_tail;
1545 if (INTEL_INFO(dev)->gen >= 4)
1546 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1547 else if (IS_I830(dev) || IS_845G(dev))
1548 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1550 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1551 ring->init = init_render_ring;
1552 ring->cleanup = render_ring_cleanup;
1554 if (!I915_NEED_GFX_HWS(dev))
1555 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1558 INIT_LIST_HEAD(&ring->active_list);
1559 INIT_LIST_HEAD(&ring->request_list);
1562 ring->effective_size = ring->size;
1563 if (IS_I830(ring->dev))
1564 ring->effective_size -= 128;
1566 ring->virtual_start = ioremap_wc(start, size);
1567 if (ring->virtual_start == NULL) {
1568 DRM_ERROR("can not ioremap virtual address for"
1576 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1578 drm_i915_private_t *dev_priv = dev->dev_private;
1579 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1581 ring->name = "bsd ring";
1584 ring->write_tail = ring_write_tail;
1585 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1586 ring->mmio_base = GEN6_BSD_RING_BASE;
1587 /* gen6 bsd needs a special wa for tail updates */
1589 ring->write_tail = gen6_bsd_ring_write_tail;
1590 ring->flush = gen6_ring_flush;
1591 ring->add_request = gen6_add_request;
1592 ring->get_seqno = gen6_ring_get_seqno;
1593 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1594 ring->irq_get = gen6_ring_get_irq;
1595 ring->irq_put = gen6_ring_put_irq;
1596 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1597 ring->sync_to = gen6_ring_sync;
1598 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1599 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1600 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1601 ring->signal_mbox[0] = GEN6_RVSYNC;
1602 ring->signal_mbox[1] = GEN6_BVSYNC;
1604 ring->mmio_base = BSD_RING_BASE;
1605 ring->flush = bsd_ring_flush;
1606 ring->add_request = i9xx_add_request;
1607 ring->get_seqno = ring_get_seqno;
1609 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1610 ring->irq_get = gen5_ring_get_irq;
1611 ring->irq_put = gen5_ring_put_irq;
1613 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1614 ring->irq_get = i9xx_ring_get_irq;
1615 ring->irq_put = i9xx_ring_put_irq;
1617 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1619 ring->init = init_ring_common;
1622 return intel_init_ring_buffer(dev, ring);
1625 int intel_init_blt_ring_buffer(struct drm_device *dev)
1627 drm_i915_private_t *dev_priv = dev->dev_private;
1628 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1630 ring->name = "blitter ring";
1633 ring->mmio_base = BLT_RING_BASE;
1634 ring->write_tail = ring_write_tail;
1635 ring->flush = blt_ring_flush;
1636 ring->add_request = gen6_add_request;
1637 ring->get_seqno = gen6_ring_get_seqno;
1638 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1639 ring->irq_get = gen6_ring_get_irq;
1640 ring->irq_put = gen6_ring_put_irq;
1641 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1642 ring->sync_to = gen6_ring_sync;
1643 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1644 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1645 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1646 ring->signal_mbox[0] = GEN6_RBSYNC;
1647 ring->signal_mbox[1] = GEN6_VBSYNC;
1648 ring->init = init_ring_common;
1650 return intel_init_ring_buffer(dev, ring);
1654 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1658 if (!ring->gpu_caches_dirty)
1661 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1665 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1667 ring->gpu_caches_dirty = false;
1672 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1674 uint32_t flush_domains;
1678 if (ring->gpu_caches_dirty)
1679 flush_domains = I915_GEM_GPU_DOMAINS;
1681 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1685 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1687 ring->gpu_caches_dirty = false;