drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 284 {
 285         int ret;
 286
 287         if (!ring->fbc_dirty)
 288                 return 0;
 289
 290         ret = intel_ring_begin(ring, 4);
 291         if (ret)
 292                 return ret;
 293         intel_ring_emit(ring, MI_NOOP);
 294         /* WaFbcNukeOn3DBlt:ivb/hsw */
 295         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 296         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 297         intel_ring_emit(ring, value);
 298         intel_ring_advance(ring);
 299
 300         ring->fbc_dirty = false;
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 306                        u32 invalidate_domains, u32 flush_domains)
 307 {
 308         u32 flags = 0;
 309         struct pipe_control *pc = ring->private;
 310         u32 scratch_addr = pc->gtt_offset + 128;
 311         int ret;
 312
 313         /*
 314          * Ensure that any following seqno writes only happen when the render
 315          * cache is indeed flushed.
 316          *
 317          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 318          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 319          * don't try to be clever and just set it unconditionally.
 320          */
 321         flags |= PIPE_CONTROL_CS_STALL;
 322
 323         /* Just flush everything.  Experiments have shown that reducing the
 324          * number of bits based on the write domains has little performance
 325          * impact.
 326          */
 327         if (flush_domains) {
 328                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 329                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 330         }
 331         if (invalidate_domains) {
 332                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 333                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 337                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 338                 /*
 339                  * TLB invalidate requires a post-sync write.
 340                  */
 341                 flags |= PIPE_CONTROL_QW_WRITE;
 342                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 343
 344                 /* Workaround: we must issue a pipe_control with CS-stall bit
 345                  * set before a pipe_control command that has the state cache
 346                  * invalidate bit set. */
 347                 gen7_render_ring_cs_stall_wa(ring);
 348         }
 349
 350         ret = intel_ring_begin(ring, 4);
 351         if (ret)
 352                 return ret;
 353
 354         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 355         intel_ring_emit(ring, flags);
 356         intel_ring_emit(ring, scratch_addr);
 357         intel_ring_emit(ring, 0);
 358         intel_ring_advance(ring);
 359
 360         if (flush_domains)
 361                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 362
 363         return 0;
 364 }
 365
 366 static void ring_write_tail(struct intel_ring_buffer *ring,
 367                             u32 value)
 368 {
 369         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 370         I915_WRITE_TAIL(ring, value);
 371 }
 372
 373 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 374 {
 375         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 376         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 377                         RING_ACTHD(ring->mmio_base) : ACTHD;
 378
 379         return I915_READ(acthd_reg);
 380 }
 381
 382 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
 383 {
 384         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 385         u32 addr;
 386
 387         addr = dev_priv->status_page_dmah->busaddr;
 388         if (INTEL_INFO(ring->dev)->gen >= 4)
 389                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 390         I915_WRITE(HWS_PGA, addr);
 391 }
 392
 393 static int init_ring_common(struct intel_ring_buffer *ring)
 394 {
 395         struct drm_device *dev = ring->dev;
 396         drm_i915_private_t *dev_priv = dev->dev_private;
 397         struct drm_i915_gem_object *obj = ring->obj;
 398         int ret = 0;
 399         u32 head;
 400
 401         if (HAS_FORCE_WAKE(dev))
 402                 gen6_gt_force_wake_get(dev_priv);
 403
 404         if (I915_NEED_GFX_HWS(dev))
 405                 intel_ring_setup_status_page(ring);
 406         else
 407                 ring_setup_phys_status_page(ring);
 408
 409         /* Stop the ring if it's running. */
 410         I915_WRITE_CTL(ring, 0);
 411         I915_WRITE_HEAD(ring, 0);
 412         ring->write_tail(ring, 0);
 413
 414         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 415
 416         /* G45 ring initialization fails to reset head to zero */
 417         if (head != 0) {
 418                 DRM_DEBUG_KMS("%s head not reset to zero "
 419                               "ctl %08x head %08x tail %08x start %08x\n",
 420                               ring->name,
 421                               I915_READ_CTL(ring),
 422                               I915_READ_HEAD(ring),
 423                               I915_READ_TAIL(ring),
 424                               I915_READ_START(ring));
 425
 426                 I915_WRITE_HEAD(ring, 0);
 427
 428                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 429                         DRM_ERROR("failed to set %s head to zero "
 430                                   "ctl %08x head %08x tail %08x start %08x\n",
 431                                   ring->name,
 432                                   I915_READ_CTL(ring),
 433                                   I915_READ_HEAD(ring),
 434                                   I915_READ_TAIL(ring),
 435                                   I915_READ_START(ring));
 436                 }
 437         }
 438
 439         /* Initialize the ring. This must happen _after_ we've cleared the ring
 440          * registers with the above sequence (the readback of the HEAD registers
 441          * also enforces ordering), otherwise the hw might lose the new ring
 442          * register values. */
 443         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 444         I915_WRITE_CTL(ring,
 445                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 446                         | RING_VALID);
 447
 448         /* If the head is still not zero, the ring is dead */
 449         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 450                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 451                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 452                 DRM_ERROR("%s initialization failed "
 453                                 "ctl %08x head %08x tail %08x start %08x\n",
 454                                 ring->name,
 455                                 I915_READ_CTL(ring),
 456                                 I915_READ_HEAD(ring),
 457                                 I915_READ_TAIL(ring),
 458                                 I915_READ_START(ring));
 459                 ret = -EIO;
 460                 goto out;
 461         }
 462
 463         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 464                 i915_kernel_lost_context(ring->dev);
 465         else {
 466                 ring->head = I915_READ_HEAD(ring);
 467                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 468                 ring->space = ring_space(ring);
 469                 ring->last_retired_head = -1;
 470         }
 471
 472         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 473
 474 out:
 475         if (HAS_FORCE_WAKE(dev))
 476                 gen6_gt_force_wake_put(dev_priv);
 477
 478         return ret;
 479 }
 480
 481 static int
 482 init_pipe_control(struct intel_ring_buffer *ring)
 483 {
 484         struct pipe_control *pc;
 485         struct drm_i915_gem_object *obj;
 486         int ret;
 487
 488         if (ring->private)
 489                 return 0;
 490
 491         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 492         if (!pc)
 493                 return -ENOMEM;
 494
 495         obj = i915_gem_alloc_object(ring->dev, 4096);
 496         if (obj == NULL) {
 497                 DRM_ERROR("Failed to allocate seqno page\n");
 498                 ret = -ENOMEM;
 499                 goto err;
 500         }
 501
 502         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 503
 504         ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false);
 505         if (ret)
 506                 goto err_unref;
 507
 508         pc->gtt_offset = i915_gem_obj_ggtt_offset(obj);
 509         pc->cpu_page = kmap(sg_page(obj->pages->sgl));
 510         if (pc->cpu_page == NULL) {
 511                 ret = -ENOMEM;
 512                 goto err_unpin;
 513         }
 514
 515         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 516                          ring->name, pc->gtt_offset);
 517
 518         pc->obj = obj;
 519         ring->private = pc;
 520         return 0;
 521
 522 err_unpin:
 523         i915_gem_object_unpin(obj);
 524 err_unref:
 525         drm_gem_object_unreference(&obj->base);
 526 err:
 527         kfree(pc);
 528         return ret;
 529 }
 530
 531 static void
 532 cleanup_pipe_control(struct intel_ring_buffer *ring)
 533 {
 534         struct pipe_control *pc = ring->private;
 535         struct drm_i915_gem_object *obj;
 536
 537         obj = pc->obj;
 538
 539         kunmap(sg_page(obj->pages->sgl));
 540         i915_gem_object_unpin(obj);
 541         drm_gem_object_unreference(&obj->base);
 542
 543         kfree(pc);
 544 }
 545
 546 static int init_render_ring(struct intel_ring_buffer *ring)
 547 {
 548         struct drm_device *dev = ring->dev;
 549         struct drm_i915_private *dev_priv = dev->dev_private;
 550         int ret = init_ring_common(ring);
 551
 552         if (INTEL_INFO(dev)->gen > 3)
 553                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 554
 555         /* We need to disable the AsyncFlip performance optimisations in order
 556          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 557          * programmed to '1' on all products.
 558          *
 559          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 560          */
 561         if (INTEL_INFO(dev)->gen >= 6)
 562                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 563
 564         /* Required for the hardware to program scanline values for waiting */
 565         if (INTEL_INFO(dev)->gen == 6)
 566                 I915_WRITE(GFX_MODE,
 567                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 568
 569         if (IS_GEN7(dev))
 570                 I915_WRITE(GFX_MODE_GEN7,
 571                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 572                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 573
 574         if (INTEL_INFO(dev)->gen >= 5) {
 575                 ret = init_pipe_control(ring);
 576                 if (ret)
 577                         return ret;
 578         }
 579
 580         if (IS_GEN6(dev)) {
 581                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 582                  * "If this bit is set, STCunit will have LRA as replacement
 583                  *  policy. [...] This bit must be reset.  LRA replacement
 584                  *  policy is not supported."
 585                  */
 586                 I915_WRITE(CACHE_MODE_0,
 587                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 588
 589                 /* This is not explicitly set for GEN6, so read the register.
 590                  * see intel_ring_mi_set_context() for why we care.
 591                  * TODO: consider explicitly setting the bit for GEN5
 592                  */
 593                 ring->itlb_before_ctx_switch =
 594                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 595         }
 596
 597         if (INTEL_INFO(dev)->gen >= 6)
 598                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 599
 600         if (HAS_L3_GPU_CACHE(dev))
 601                 I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
 602
 603         return ret;
 604 }
 605
 606 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 607 {
 608         struct drm_device *dev = ring->dev;
 609
 610         if (!ring->private)
 611                 return;
 612
 613         if (HAS_BROKEN_CS_TLB(dev))
 614                 drm_gem_object_unreference(to_gem_object(ring->private));
 615
 616         if (INTEL_INFO(dev)->gen >= 5)
 617                 cleanup_pipe_control(ring);
 618
 619         ring->private = NULL;
 620 }
 621
 622 static void
 623 update_mboxes(struct intel_ring_buffer *ring,
 624               u32 mmio_offset)
 625 {
 626 /* NB: In order to be able to do semaphore MBOX updates for varying number
 627  * of rings, it's easiest if we round up each individual update to a
 628  * multiple of 2 (since ring updates must always be a multiple of 2)
 629  * even though the actual update only requires 3 dwords.
 630  */
 631 #define MBOX_UPDATE_DWORDS 4
 632         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 633         intel_ring_emit(ring, mmio_offset);
 634         intel_ring_emit(ring, ring->outstanding_lazy_request);
 635         intel_ring_emit(ring, MI_NOOP);
 636 }
 637
 638 /**
 639  * gen6_add_request - Update the semaphore mailbox registers
 640  *
 641  * @ring - ring that is adding a request
 642  * @seqno - return seqno stuck into the ring
 643  *
 644  * Update the mailbox registers in the *other* rings with the current seqno.
 645  * This acts like a signal in the canonical semaphore.
 646  */
 647 static int
 648 gen6_add_request(struct intel_ring_buffer *ring)
 649 {
 650         struct drm_device *dev = ring->dev;
 651         struct drm_i915_private *dev_priv = dev->dev_private;
 652         struct intel_ring_buffer *useless;
 653         int i, ret;
 654
 655         ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
 656                                       MBOX_UPDATE_DWORDS) +
 657                                       4);
 658         if (ret)
 659                 return ret;
 660 #undef MBOX_UPDATE_DWORDS
 661
 662         for_each_ring(useless, dev_priv, i) {
 663                 u32 mbox_reg = ring->signal_mbox[i];
 664                 if (mbox_reg != GEN6_NOSYNC)
 665                         update_mboxes(ring, mbox_reg);
 666         }
 667
 668         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 669         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 670         intel_ring_emit(ring, ring->outstanding_lazy_request);
 671         intel_ring_emit(ring, MI_USER_INTERRUPT);
 672         intel_ring_advance(ring);
 673
 674         return 0;
 675 }
 676
 677 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 678                                               u32 seqno)
 679 {
 680         struct drm_i915_private *dev_priv = dev->dev_private;
 681         return dev_priv->last_seqno < seqno;
 682 }
 683
 684 /**
 685  * intel_ring_sync - sync the waiter to the signaller on seqno
 686  *
 687  * @waiter - ring that is waiting
 688  * @signaller - ring which has, or will signal
 689  * @seqno - seqno which the waiter will block on
 690  */
 691 static int
 692 gen6_ring_sync(struct intel_ring_buffer *waiter,
 693                struct intel_ring_buffer *signaller,
 694                u32 seqno)
 695 {
 696         int ret;
 697         u32 dw1 = MI_SEMAPHORE_MBOX |
 698                   MI_SEMAPHORE_COMPARE |
 699                   MI_SEMAPHORE_REGISTER;
 700
 701         /* Throughout all of the GEM code, seqno passed implies our current
 702          * seqno is >= the last seqno executed. However for hardware the
 703          * comparison is strictly greater than.
 704          */
 705         seqno -= 1;
 706
 707         WARN_ON(signaller->semaphore_register[waiter->id] ==
 708                 MI_SEMAPHORE_SYNC_INVALID);
 709
 710         ret = intel_ring_begin(waiter, 4);
 711         if (ret)
 712                 return ret;
 713
 714         /* If seqno wrap happened, omit the wait with no-ops */
 715         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 716                 intel_ring_emit(waiter,
 717                                 dw1 |
 718                                 signaller->semaphore_register[waiter->id]);
 719                 intel_ring_emit(waiter, seqno);
 720                 intel_ring_emit(waiter, 0);
 721                 intel_ring_emit(waiter, MI_NOOP);
 722         } else {
 723                 intel_ring_emit(waiter, MI_NOOP);
 724                 intel_ring_emit(waiter, MI_NOOP);
 725                 intel_ring_emit(waiter, MI_NOOP);
 726                 intel_ring_emit(waiter, MI_NOOP);
 727         }
 728         intel_ring_advance(waiter);
 729
 730         return 0;
 731 }
 732
 733 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 734 do {                                                                    \
 735         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 736                  PIPE_CONTROL_DEPTH_STALL);                             \
 737         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 738         intel_ring_emit(ring__, 0);                                                     \
 739         intel_ring_emit(ring__, 0);                                                     \
 740 } while (0)
 741
 742 static int
 743 pc_render_add_request(struct intel_ring_buffer *ring)
 744 {
 745         struct pipe_control *pc = ring->private;
 746         u32 scratch_addr = pc->gtt_offset + 128;
 747         int ret;
 748
 749         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 750          * incoherent with writes to memory, i.e. completely fubar,
 751          * so we need to use PIPE_NOTIFY instead.
 752          *
 753          * However, we also need to workaround the qword write
 754          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 755          * memory before requesting an interrupt.
 756          */
 757         ret = intel_ring_begin(ring, 32);
 758         if (ret)
 759                 return ret;
 760
 761         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 762                         PIPE_CONTROL_WRITE_FLUSH |
 763                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 764         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 765         intel_ring_emit(ring, ring->outstanding_lazy_request);
 766         intel_ring_emit(ring, 0);
 767         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 768         scratch_addr += 128; /* write to separate cachelines */
 769         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 770         scratch_addr += 128;
 771         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 772         scratch_addr += 128;
 773         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 774         scratch_addr += 128;
 775         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 776         scratch_addr += 128;
 777         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 778
 779         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 780                         PIPE_CONTROL_WRITE_FLUSH |
 781                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 782                         PIPE_CONTROL_NOTIFY);
 783         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 784         intel_ring_emit(ring, ring->outstanding_lazy_request);
 785         intel_ring_emit(ring, 0);
 786         intel_ring_advance(ring);
 787
 788         return 0;
 789 }
 790
 791 static u32
 792 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 793 {
 794         /* Workaround to force correct ordering between irq and seqno writes on
 795          * ivb (and maybe also on snb) by reading from a CS register (like
 796          * ACTHD) before reading the status page. */
 797         if (!lazy_coherency)
 798                 intel_ring_get_active_head(ring);
 799         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 800 }
 801
 802 static u32
 803 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 804 {
 805         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 806 }
 807
 808 static void
 809 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 810 {
 811         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 812 }
 813
 814 static u32
 815 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 816 {
 817         struct pipe_control *pc = ring->private;
 818         return pc->cpu_page[0];
 819 }
 820
 821 static void
 822 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 823 {
 824         struct pipe_control *pc = ring->private;
 825         pc->cpu_page[0] = seqno;
 826 }
 827
 828 static bool
 829 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 830 {
 831         struct drm_device *dev = ring->dev;
 832         drm_i915_private_t *dev_priv = dev->dev_private;
 833         unsigned long flags;
 834
 835         if (!dev->irq_enabled)
 836                 return false;
 837
 838         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 839         if (ring->irq_refcount++ == 0)
 840                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
 841         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 842
 843         return true;
 844 }
 845
 846 static void
 847 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 848 {
 849         struct drm_device *dev = ring->dev;
 850         drm_i915_private_t *dev_priv = dev->dev_private;
 851         unsigned long flags;
 852
 853         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 854         if (--ring->irq_refcount == 0)
 855                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
 856         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 857 }
 858
 859 static bool
 860 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 861 {
 862         struct drm_device *dev = ring->dev;
 863         drm_i915_private_t *dev_priv = dev->dev_private;
 864         unsigned long flags;
 865
 866         if (!dev->irq_enabled)
 867                 return false;
 868
 869         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 870         if (ring->irq_refcount++ == 0) {
 871                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 872                 I915_WRITE(IMR, dev_priv->irq_mask);
 873                 POSTING_READ(IMR);
 874         }
 875         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 876
 877         return true;
 878 }
 879
 880 static void
 881 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 882 {
 883         struct drm_device *dev = ring->dev;
 884         drm_i915_private_t *dev_priv = dev->dev_private;
 885         unsigned long flags;
 886
 887         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 888         if (--ring->irq_refcount == 0) {
 889                 dev_priv->irq_mask |= ring->irq_enable_mask;
 890                 I915_WRITE(IMR, dev_priv->irq_mask);
 891                 POSTING_READ(IMR);
 892         }
 893         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 894 }
 895
 896 static bool
 897 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 898 {
 899         struct drm_device *dev = ring->dev;
 900         drm_i915_private_t *dev_priv = dev->dev_private;
 901         unsigned long flags;
 902
 903         if (!dev->irq_enabled)
 904                 return false;
 905
 906         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 907         if (ring->irq_refcount++ == 0) {
 908                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 909                 I915_WRITE16(IMR, dev_priv->irq_mask);
 910                 POSTING_READ16(IMR);
 911         }
 912         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 913
 914         return true;
 915 }
 916
 917 static void
 918 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 919 {
 920         struct drm_device *dev = ring->dev;
 921         drm_i915_private_t *dev_priv = dev->dev_private;
 922         unsigned long flags;
 923
 924         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 925         if (--ring->irq_refcount == 0) {
 926                 dev_priv->irq_mask |= ring->irq_enable_mask;
 927                 I915_WRITE16(IMR, dev_priv->irq_mask);
 928                 POSTING_READ16(IMR);
 929         }
 930         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 931 }
 932
 933 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 934 {
 935         struct drm_device *dev = ring->dev;
 936         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 937         u32 mmio = 0;
 938
 939         /* The ring status page addresses are no longer next to the rest of
 940          * the ring registers as of gen7.
 941          */
 942         if (IS_GEN7(dev)) {
 943                 switch (ring->id) {
 944                 case RCS:
 945                         mmio = RENDER_HWS_PGA_GEN7;
 946                         break;
 947                 case BCS:
 948                         mmio = BLT_HWS_PGA_GEN7;
 949                         break;
 950                 case VCS:
 951                         mmio = BSD_HWS_PGA_GEN7;
 952                         break;
 953                 case VECS:
 954                         mmio = VEBOX_HWS_PGA_GEN7;
 955                         break;
 956                 }
 957         } else if (IS_GEN6(ring->dev)) {
 958                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 959         } else {
 960                 mmio = RING_HWS_PGA(ring->mmio_base);
 961         }
 962
 963         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 964         POSTING_READ(mmio);
 965
 966         /* Flush the TLB for this page */
 967         if (INTEL_INFO(dev)->gen >= 6) {
 968                 u32 reg = RING_INSTPM(ring->mmio_base);
 969                 I915_WRITE(reg,
 970                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 971                                               INSTPM_SYNC_FLUSH));
 972                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 973                              1000))
 974                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 975                                   ring->name);
 976         }
 977 }
 978
 979 static int
 980 bsd_ring_flush(struct intel_ring_buffer *ring,
 981                u32     invalidate_domains,
 982                u32     flush_domains)
 983 {
 984         int ret;
 985
 986         ret = intel_ring_begin(ring, 2);
 987         if (ret)
 988                 return ret;
 989
 990         intel_ring_emit(ring, MI_FLUSH);
 991         intel_ring_emit(ring, MI_NOOP);
 992         intel_ring_advance(ring);
 993         return 0;
 994 }
 995
 996 static int
 997 i9xx_add_request(struct intel_ring_buffer *ring)
 998 {
 999         int ret;
1000
1001         ret = intel_ring_begin(ring, 4);
1002         if (ret)
1003                 return ret;
1004
1005         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1006         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1007         intel_ring_emit(ring, ring->outstanding_lazy_request);
1008         intel_ring_emit(ring, MI_USER_INTERRUPT);
1009         intel_ring_advance(ring);
1010
1011         return 0;
1012 }
1013
1014 static bool
1015 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1016 {
1017         struct drm_device *dev = ring->dev;
1018         drm_i915_private_t *dev_priv = dev->dev_private;
1019         unsigned long flags;
1020
1021         if (!dev->irq_enabled)
1022                return false;
1023
1024         /* It looks like we need to prevent the gt from suspending while waiting
1025          * for an notifiy irq, otherwise irqs seem to get lost on at least the
1026          * blt/bsd rings on ivb. */
1027         gen6_gt_force_wake_get(dev_priv);
1028
1029         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1030         if (ring->irq_refcount++ == 0) {
1031                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1032                         I915_WRITE_IMR(ring,
1033                                        ~(ring->irq_enable_mask |
1034                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1035                 else
1036                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1037                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1038         }
1039         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1040
1041         return true;
1042 }
1043
1044 static void
1045 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1046 {
1047         struct drm_device *dev = ring->dev;
1048         drm_i915_private_t *dev_priv = dev->dev_private;
1049         unsigned long flags;
1050
1051         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1052         if (--ring->irq_refcount == 0) {
1053                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1054                         I915_WRITE_IMR(ring,
1055                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1056                 else
1057                         I915_WRITE_IMR(ring, ~0);
1058                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1059         }
1060         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1061
1062         gen6_gt_force_wake_put(dev_priv);
1063 }
1064
1065 static bool
1066 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1067 {
1068         struct drm_device *dev = ring->dev;
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070         unsigned long flags;
1071
1072         if (!dev->irq_enabled)
1073                 return false;
1074
1075         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1076         if (ring->irq_refcount++ == 0) {
1077                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1078                 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1079         }
1080         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1081
1082         return true;
1083 }
1084
1085 static void
1086 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1087 {
1088         struct drm_device *dev = ring->dev;
1089         struct drm_i915_private *dev_priv = dev->dev_private;
1090         unsigned long flags;
1091
1092         if (!dev->irq_enabled)
1093                 return;
1094
1095         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1096         if (--ring->irq_refcount == 0) {
1097                 I915_WRITE_IMR(ring, ~0);
1098                 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1099         }
1100         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1101 }
1102
1103 static int
1104 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1105                          u32 offset, u32 length,
1106                          unsigned flags)
1107 {
1108         int ret;
1109
1110         ret = intel_ring_begin(ring, 2);
1111         if (ret)
1112                 return ret;
1113
1114         intel_ring_emit(ring,
1115                         MI_BATCH_BUFFER_START |
1116                         MI_BATCH_GTT |
1117                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1118         intel_ring_emit(ring, offset);
1119         intel_ring_advance(ring);
1120
1121         return 0;
1122 }
1123
1124 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1125 #define I830_BATCH_LIMIT (256*1024)
1126 static int
1127 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1128                                 u32 offset, u32 len,
1129                                 unsigned flags)
1130 {
1131         int ret;
1132
1133         if (flags & I915_DISPATCH_PINNED) {
1134                 ret = intel_ring_begin(ring, 4);
1135                 if (ret)
1136                         return ret;
1137
1138                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1139                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1140                 intel_ring_emit(ring, offset + len - 8);
1141                 intel_ring_emit(ring, MI_NOOP);
1142                 intel_ring_advance(ring);
1143         } else {
1144                 struct drm_i915_gem_object *obj = ring->private;
1145                 u32 cs_offset = i915_gem_obj_ggtt_offset(obj);
1146
1147                 if (len > I830_BATCH_LIMIT)
1148                         return -ENOSPC;
1149
1150                 ret = intel_ring_begin(ring, 9+3);
1151                 if (ret)
1152                         return ret;
1153                 /* Blit the batch (which has now all relocs applied) to the stable batch
1154                  * scratch bo area (so that the CS never stumbles over its tlb
1155                  * invalidation bug) ... */
1156                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1157                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1158                                 XY_SRC_COPY_BLT_WRITE_RGB);
1159                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1160                 intel_ring_emit(ring, 0);
1161                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1162                 intel_ring_emit(ring, cs_offset);
1163                 intel_ring_emit(ring, 0);
1164                 intel_ring_emit(ring, 4096);
1165                 intel_ring_emit(ring, offset);
1166                 intel_ring_emit(ring, MI_FLUSH);
1167
1168                 /* ... and execute it. */
1169                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1170                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1171                 intel_ring_emit(ring, cs_offset + len - 8);
1172                 intel_ring_advance(ring);
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int
1179 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1180                          u32 offset, u32 len,
1181                          unsigned flags)
1182 {
1183         int ret;
1184
1185         ret = intel_ring_begin(ring, 2);
1186         if (ret)
1187                 return ret;
1188
1189         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1190         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1191         intel_ring_advance(ring);
1192
1193         return 0;
1194 }
1195
1196 static void cleanup_status_page(struct intel_ring_buffer *ring)
1197 {
1198         struct drm_i915_gem_object *obj;
1199
1200         obj = ring->status_page.obj;
1201         if (obj == NULL)
1202                 return;
1203
1204         kunmap(sg_page(obj->pages->sgl));
1205         i915_gem_object_unpin(obj);
1206         drm_gem_object_unreference(&obj->base);
1207         ring->status_page.obj = NULL;
1208 }
1209
1210 static int init_status_page(struct intel_ring_buffer *ring)
1211 {
1212         struct drm_device *dev = ring->dev;
1213         struct drm_i915_gem_object *obj;
1214         int ret;
1215
1216         obj = i915_gem_alloc_object(dev, 4096);
1217         if (obj == NULL) {
1218                 DRM_ERROR("Failed to allocate status page\n");
1219                 ret = -ENOMEM;
1220                 goto err;
1221         }
1222
1223         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1224
1225         ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false);
1226         if (ret != 0) {
1227                 goto err_unref;
1228         }
1229
1230         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1231         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1232         if (ring->status_page.page_addr == NULL) {
1233                 ret = -ENOMEM;
1234                 goto err_unpin;
1235         }
1236         ring->status_page.obj = obj;
1237         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1238
1239         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1240                         ring->name, ring->status_page.gfx_addr);
1241
1242         return 0;
1243
1244 err_unpin:
1245         i915_gem_object_unpin(obj);
1246 err_unref:
1247         drm_gem_object_unreference(&obj->base);
1248 err:
1249         return ret;
1250 }
1251
1252 static int init_phys_status_page(struct intel_ring_buffer *ring)
1253 {
1254         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1255
1256         if (!dev_priv->status_page_dmah) {
1257                 dev_priv->status_page_dmah =
1258                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1259                 if (!dev_priv->status_page_dmah)
1260                         return -ENOMEM;
1261         }
1262
1263         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1264         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1265
1266         return 0;
1267 }
1268
1269 static int intel_init_ring_buffer(struct drm_device *dev,
1270                                   struct intel_ring_buffer *ring)
1271 {
1272         struct drm_i915_gem_object *obj;
1273         struct drm_i915_private *dev_priv = dev->dev_private;
1274         int ret;
1275
1276         ring->dev = dev;
1277         INIT_LIST_HEAD(&ring->active_list);
1278         INIT_LIST_HEAD(&ring->request_list);
1279         ring->size = 32 * PAGE_SIZE;
1280         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1281
1282         init_waitqueue_head(&ring->irq_queue);
1283
1284         if (I915_NEED_GFX_HWS(dev)) {
1285                 ret = init_status_page(ring);
1286                 if (ret)
1287                         return ret;
1288         } else {
1289                 BUG_ON(ring->id != RCS);
1290                 ret = init_phys_status_page(ring);
1291                 if (ret)
1292                         return ret;
1293         }
1294
1295         obj = NULL;
1296         if (!HAS_LLC(dev))
1297                 obj = i915_gem_object_create_stolen(dev, ring->size);
1298         if (obj == NULL)
1299                 obj = i915_gem_alloc_object(dev, ring->size);
1300         if (obj == NULL) {
1301                 DRM_ERROR("Failed to allocate ringbuffer\n");
1302                 ret = -ENOMEM;
1303                 goto err_hws;
1304         }
1305
1306         ring->obj = obj;
1307
1308         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false);
1309         if (ret)
1310                 goto err_unref;
1311
1312         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1313         if (ret)
1314                 goto err_unpin;
1315
1316         ring->virtual_start =
1317                 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1318                            ring->size);
1319         if (ring->virtual_start == NULL) {
1320                 DRM_ERROR("Failed to map ringbuffer.\n");
1321                 ret = -EINVAL;
1322                 goto err_unpin;
1323         }
1324
1325         ret = ring->init(ring);
1326         if (ret)
1327                 goto err_unmap;
1328
1329         /* Workaround an erratum on the i830 which causes a hang if
1330          * the TAIL pointer points to within the last 2 cachelines
1331          * of the buffer.
1332          */
1333         ring->effective_size = ring->size;
1334         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1335                 ring->effective_size -= 128;
1336
1337         return 0;
1338
1339 err_unmap:
1340         iounmap(ring->virtual_start);
1341 err_unpin:
1342         i915_gem_object_unpin(obj);
1343 err_unref:
1344         drm_gem_object_unreference(&obj->base);
1345         ring->obj = NULL;
1346 err_hws:
1347         cleanup_status_page(ring);
1348         return ret;
1349 }
1350
1351 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1352 {
1353         struct drm_i915_private *dev_priv;
1354         int ret;
1355
1356         if (ring->obj == NULL)
1357                 return;
1358
1359         /* Disable the ring buffer. The ring must be idle at this point */
1360         dev_priv = ring->dev->dev_private;
1361         ret = intel_ring_idle(ring);
1362         if (ret)
1363                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1364                           ring->name, ret);
1365
1366         I915_WRITE_CTL(ring, 0);
1367
1368         iounmap(ring->virtual_start);
1369
1370         i915_gem_object_unpin(ring->obj);
1371         drm_gem_object_unreference(&ring->obj->base);
1372         ring->obj = NULL;
1373
1374         if (ring->cleanup)
1375                 ring->cleanup(ring);
1376
1377         cleanup_status_page(ring);
1378 }
1379
1380 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1381 {
1382         int ret;
1383
1384         ret = i915_wait_seqno(ring, seqno);
1385         if (!ret)
1386                 i915_gem_retire_requests_ring(ring);
1387
1388         return ret;
1389 }
1390
1391 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1392 {
1393         struct drm_i915_gem_request *request;
1394         u32 seqno = 0;
1395         int ret;
1396
1397         i915_gem_retire_requests_ring(ring);
1398
1399         if (ring->last_retired_head != -1) {
1400                 ring->head = ring->last_retired_head;
1401                 ring->last_retired_head = -1;
1402                 ring->space = ring_space(ring);
1403                 if (ring->space >= n)
1404                         return 0;
1405         }
1406
1407         list_for_each_entry(request, &ring->request_list, list) {
1408                 int space;
1409
1410                 if (request->tail == -1)
1411                         continue;
1412
1413                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1414                 if (space < 0)
1415                         space += ring->size;
1416                 if (space >= n) {
1417                         seqno = request->seqno;
1418                         break;
1419                 }
1420
1421                 /* Consume this request in case we need more space than
1422                  * is available and so need to prevent a race between
1423                  * updating last_retired_head and direct reads of
1424                  * I915_RING_HEAD. It also provides a nice sanity check.
1425                  */
1426                 request->tail = -1;
1427         }
1428
1429         if (seqno == 0)
1430                 return -ENOSPC;
1431
1432         ret = intel_ring_wait_seqno(ring, seqno);
1433         if (ret)
1434                 return ret;
1435
1436         if (WARN_ON(ring->last_retired_head == -1))
1437                 return -ENOSPC;
1438
1439         ring->head = ring->last_retired_head;
1440         ring->last_retired_head = -1;
1441         ring->space = ring_space(ring);
1442         if (WARN_ON(ring->space < n))
1443                 return -ENOSPC;
1444
1445         return 0;
1446 }
1447
1448 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1449 {
1450         struct drm_device *dev = ring->dev;
1451         struct drm_i915_private *dev_priv = dev->dev_private;
1452         unsigned long end;
1453         int ret;
1454
1455         ret = intel_ring_wait_request(ring, n);
1456         if (ret != -ENOSPC)
1457                 return ret;
1458
1459         trace_i915_ring_wait_begin(ring);
1460         /* With GEM the hangcheck timer should kick us out of the loop,
1461          * leaving it early runs the risk of corrupting GEM state (due
1462          * to running on almost untested codepaths). But on resume
1463          * timers don't work yet, so prevent a complete hang in that
1464          * case by choosing an insanely large timeout. */
1465         end = jiffies + 60 * HZ;
1466
1467         do {
1468                 ring->head = I915_READ_HEAD(ring);
1469                 ring->space = ring_space(ring);
1470                 if (ring->space >= n) {
1471                         trace_i915_ring_wait_end(ring);
1472                         return 0;
1473                 }
1474
1475                 if (dev->primary->master) {
1476                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1477                         if (master_priv->sarea_priv)
1478                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1479                 }
1480
1481                 msleep(1);
1482
1483                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1484                                            dev_priv->mm.interruptible);
1485                 if (ret)
1486                         return ret;
1487         } while (!time_after(jiffies, end));
1488         trace_i915_ring_wait_end(ring);
1489         return -EBUSY;
1490 }
1491
1492 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1493 {
1494         uint32_t __iomem *virt;
1495         int rem = ring->size - ring->tail;
1496
1497         if (ring->space < rem) {
1498                 int ret = ring_wait_for_space(ring, rem);
1499                 if (ret)
1500                         return ret;
1501         }
1502
1503         virt = ring->virtual_start + ring->tail;
1504         rem /= 4;
1505         while (rem--)
1506                 iowrite32(MI_NOOP, virt++);
1507
1508         ring->tail = 0;
1509         ring->space = ring_space(ring);
1510
1511         return 0;
1512 }
1513
1514 int intel_ring_idle(struct intel_ring_buffer *ring)
1515 {
1516         u32 seqno;
1517         int ret;
1518
1519         /* We need to add any requests required to flush the objects and ring */
1520         if (ring->outstanding_lazy_request) {
1521                 ret = i915_add_request(ring, NULL);
1522                 if (ret)
1523                         return ret;
1524         }
1525
1526         /* Wait upon the last request to be completed */
1527         if (list_empty(&ring->request_list))
1528                 return 0;
1529
1530         seqno = list_entry(ring->request_list.prev,
1531                            struct drm_i915_gem_request,
1532                            list)->seqno;
1533
1534         return i915_wait_seqno(ring, seqno);
1535 }
1536
1537 static int
1538 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1539 {
1540         if (ring->outstanding_lazy_request)
1541                 return 0;
1542
1543         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1544 }
1545
1546 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1547                               int bytes)
1548 {
1549         int ret;
1550
1551         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1552                 ret = intel_wrap_ring_buffer(ring);
1553                 if (unlikely(ret))
1554                         return ret;
1555         }
1556
1557         if (unlikely(ring->space < bytes)) {
1558                 ret = ring_wait_for_space(ring, bytes);
1559                 if (unlikely(ret))
1560                         return ret;
1561         }
1562
1563         ring->space -= bytes;
1564         return 0;
1565 }
1566
1567 int intel_ring_begin(struct intel_ring_buffer *ring,
1568                      int num_dwords)
1569 {
1570         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1571         int ret;
1572
1573         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1574                                    dev_priv->mm.interruptible);
1575         if (ret)
1576                 return ret;
1577
1578         /* Preallocate the olr before touching the ring */
1579         ret = intel_ring_alloc_seqno(ring);
1580         if (ret)
1581                 return ret;
1582
1583         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1584 }
1585
1586 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1587 {
1588         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1589
1590         BUG_ON(ring->outstanding_lazy_request);
1591
1592         if (INTEL_INFO(ring->dev)->gen >= 6) {
1593                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1594                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1595                 if (HAS_VEBOX(ring->dev))
1596                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1597         }
1598
1599         ring->set_seqno(ring, seqno);
1600         ring->hangcheck.seqno = seqno;
1601 }
1602
1603 void intel_ring_advance(struct intel_ring_buffer *ring)
1604 {
1605         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1606
1607         ring->tail &= ring->size - 1;
1608         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1609                 return;
1610         ring->write_tail(ring, ring->tail);
1611 }
1612
1613
1614 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1615                                      u32 value)
1616 {
1617         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1618
1619        /* Every tail move must follow the sequence below */
1620
1621         /* Disable notification that the ring is IDLE. The GT
1622          * will then assume that it is busy and bring it out of rc6.
1623          */
1624         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1625                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1626
1627         /* Clear the context id. Here be magic! */
1628         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1629
1630         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1631         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1632                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1633                      50))
1634                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1635
1636         /* Now that the ring is fully powered up, update the tail */
1637         I915_WRITE_TAIL(ring, value);
1638         POSTING_READ(RING_TAIL(ring->mmio_base));
1639
1640         /* Let the ring send IDLE messages to the GT again,
1641          * and so let it sleep to conserve power when idle.
1642          */
1643         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1644                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1645 }
1646
1647 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1648                                u32 invalidate, u32 flush)
1649 {
1650         uint32_t cmd;
1651         int ret;
1652
1653         ret = intel_ring_begin(ring, 4);
1654         if (ret)
1655                 return ret;
1656
1657         cmd = MI_FLUSH_DW;
1658         /*
1659          * Bspec vol 1c.5 - video engine command streamer:
1660          * "If ENABLED, all TLBs will be invalidated once the flush
1661          * operation is complete. This bit is only valid when the
1662          * Post-Sync Operation field is a value of 1h or 3h."
1663          */
1664         if (invalidate & I915_GEM_GPU_DOMAINS)
1665                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1666                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1667         intel_ring_emit(ring, cmd);
1668         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1669         intel_ring_emit(ring, 0);
1670         intel_ring_emit(ring, MI_NOOP);
1671         intel_ring_advance(ring);
1672         return 0;
1673 }
1674
1675 static int
1676 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1677                               u32 offset, u32 len,
1678                               unsigned flags)
1679 {
1680         int ret;
1681
1682         ret = intel_ring_begin(ring, 2);
1683         if (ret)
1684                 return ret;
1685
1686         intel_ring_emit(ring,
1687                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1688                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1689         /* bit0-7 is the length on GEN6+ */
1690         intel_ring_emit(ring, offset);
1691         intel_ring_advance(ring);
1692
1693         return 0;
1694 }
1695
1696 static int
1697 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1698                               u32 offset, u32 len,
1699                               unsigned flags)
1700 {
1701         int ret;
1702
1703         ret = intel_ring_begin(ring, 2);
1704         if (ret)
1705                 return ret;
1706
1707         intel_ring_emit(ring,
1708                         MI_BATCH_BUFFER_START |
1709                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1710         /* bit0-7 is the length on GEN6+ */
1711         intel_ring_emit(ring, offset);
1712         intel_ring_advance(ring);
1713
1714         return 0;
1715 }
1716
1717 /* Blitter support (SandyBridge+) */
1718
1719 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1720                            u32 invalidate, u32 flush)
1721 {
1722         struct drm_device *dev = ring->dev;
1723         uint32_t cmd;
1724         int ret;
1725
1726         ret = intel_ring_begin(ring, 4);
1727         if (ret)
1728                 return ret;
1729
1730         cmd = MI_FLUSH_DW;
1731         /*
1732          * Bspec vol 1c.3 - blitter engine command streamer:
1733          * "If ENABLED, all TLBs will be invalidated once the flush
1734          * operation is complete. This bit is only valid when the
1735          * Post-Sync Operation field is a value of 1h or 3h."
1736          */
1737         if (invalidate & I915_GEM_DOMAIN_RENDER)
1738                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1739                         MI_FLUSH_DW_OP_STOREDW;
1740         intel_ring_emit(ring, cmd);
1741         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1742         intel_ring_emit(ring, 0);
1743         intel_ring_emit(ring, MI_NOOP);
1744         intel_ring_advance(ring);
1745
1746         if (IS_GEN7(dev) && flush)
1747                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1748
1749         return 0;
1750 }
1751
1752 int intel_init_render_ring_buffer(struct drm_device *dev)
1753 {
1754         drm_i915_private_t *dev_priv = dev->dev_private;
1755         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1756
1757         ring->name = "render ring";
1758         ring->id = RCS;
1759         ring->mmio_base = RENDER_RING_BASE;
1760
1761         if (INTEL_INFO(dev)->gen >= 6) {
1762                 ring->add_request = gen6_add_request;
1763                 ring->flush = gen7_render_ring_flush;
1764                 if (INTEL_INFO(dev)->gen == 6)
1765                         ring->flush = gen6_render_ring_flush;
1766                 ring->irq_get = gen6_ring_get_irq;
1767                 ring->irq_put = gen6_ring_put_irq;
1768                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1769                 ring->get_seqno = gen6_ring_get_seqno;
1770                 ring->set_seqno = ring_set_seqno;
1771                 ring->sync_to = gen6_ring_sync;
1772                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1773                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1774                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1775                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1776                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1777                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1778                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1779                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1780         } else if (IS_GEN5(dev)) {
1781                 ring->add_request = pc_render_add_request;
1782                 ring->flush = gen4_render_ring_flush;
1783                 ring->get_seqno = pc_render_get_seqno;
1784                 ring->set_seqno = pc_render_set_seqno;
1785                 ring->irq_get = gen5_ring_get_irq;
1786                 ring->irq_put = gen5_ring_put_irq;
1787                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1788                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1789         } else {
1790                 ring->add_request = i9xx_add_request;
1791                 if (INTEL_INFO(dev)->gen < 4)
1792                         ring->flush = gen2_render_ring_flush;
1793                 else
1794                         ring->flush = gen4_render_ring_flush;
1795                 ring->get_seqno = ring_get_seqno;
1796                 ring->set_seqno = ring_set_seqno;
1797                 if (IS_GEN2(dev)) {
1798                         ring->irq_get = i8xx_ring_get_irq;
1799                         ring->irq_put = i8xx_ring_put_irq;
1800                 } else {
1801                         ring->irq_get = i9xx_ring_get_irq;
1802                         ring->irq_put = i9xx_ring_put_irq;
1803                 }
1804                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1805         }
1806         ring->write_tail = ring_write_tail;
1807         if (IS_HASWELL(dev))
1808                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1809         else if (INTEL_INFO(dev)->gen >= 6)
1810                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1811         else if (INTEL_INFO(dev)->gen >= 4)
1812                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1813         else if (IS_I830(dev) || IS_845G(dev))
1814                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1815         else
1816                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1817         ring->init = init_render_ring;
1818         ring->cleanup = render_ring_cleanup;
1819
1820         /* Workaround batchbuffer to combat CS tlb bug. */
1821         if (HAS_BROKEN_CS_TLB(dev)) {
1822                 struct drm_i915_gem_object *obj;
1823                 int ret;
1824
1825                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1826                 if (obj == NULL) {
1827                         DRM_ERROR("Failed to allocate batch bo\n");
1828                         return -ENOMEM;
1829                 }
1830
1831                 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1832                 if (ret != 0) {
1833                         drm_gem_object_unreference(&obj->base);
1834                         DRM_ERROR("Failed to ping batch bo\n");
1835                         return ret;
1836                 }
1837
1838                 ring->private = obj;
1839         }
1840
1841         return intel_init_ring_buffer(dev, ring);
1842 }
1843
1844 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1845 {
1846         drm_i915_private_t *dev_priv = dev->dev_private;
1847         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1848         int ret;
1849
1850         ring->name = "render ring";
1851         ring->id = RCS;
1852         ring->mmio_base = RENDER_RING_BASE;
1853
1854         if (INTEL_INFO(dev)->gen >= 6) {
1855                 /* non-kms not supported on gen6+ */
1856                 return -ENODEV;
1857         }
1858
1859         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1860          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1861          * the special gen5 functions. */
1862         ring->add_request = i9xx_add_request;
1863         if (INTEL_INFO(dev)->gen < 4)
1864                 ring->flush = gen2_render_ring_flush;
1865         else
1866                 ring->flush = gen4_render_ring_flush;
1867         ring->get_seqno = ring_get_seqno;
1868         ring->set_seqno = ring_set_seqno;
1869         if (IS_GEN2(dev)) {
1870                 ring->irq_get = i8xx_ring_get_irq;
1871                 ring->irq_put = i8xx_ring_put_irq;
1872         } else {
1873                 ring->irq_get = i9xx_ring_get_irq;
1874                 ring->irq_put = i9xx_ring_put_irq;
1875         }
1876         ring->irq_enable_mask = I915_USER_INTERRUPT;
1877         ring->write_tail = ring_write_tail;
1878         if (INTEL_INFO(dev)->gen >= 4)
1879                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1880         else if (IS_I830(dev) || IS_845G(dev))
1881                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1882         else
1883                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1884         ring->init = init_render_ring;
1885         ring->cleanup = render_ring_cleanup;
1886
1887         ring->dev = dev;
1888         INIT_LIST_HEAD(&ring->active_list);
1889         INIT_LIST_HEAD(&ring->request_list);
1890
1891         ring->size = size;
1892         ring->effective_size = ring->size;
1893         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1894                 ring->effective_size -= 128;
1895
1896         ring->virtual_start = ioremap_wc(start, size);
1897         if (ring->virtual_start == NULL) {
1898                 DRM_ERROR("can not ioremap virtual address for"
1899                           " ring buffer\n");
1900                 return -ENOMEM;
1901         }
1902
1903         if (!I915_NEED_GFX_HWS(dev)) {
1904                 ret = init_phys_status_page(ring);
1905                 if (ret)
1906                         return ret;
1907         }
1908
1909         return 0;
1910 }
1911
1912 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1913 {
1914         drm_i915_private_t *dev_priv = dev->dev_private;
1915         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1916
1917         ring->name = "bsd ring";
1918         ring->id = VCS;
1919
1920         ring->write_tail = ring_write_tail;
1921         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1922                 ring->mmio_base = GEN6_BSD_RING_BASE;
1923                 /* gen6 bsd needs a special wa for tail updates */
1924                 if (IS_GEN6(dev))
1925                         ring->write_tail = gen6_bsd_ring_write_tail;
1926                 ring->flush = gen6_bsd_ring_flush;
1927                 ring->add_request = gen6_add_request;
1928                 ring->get_seqno = gen6_ring_get_seqno;
1929                 ring->set_seqno = ring_set_seqno;
1930                 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1931                 ring->irq_get = gen6_ring_get_irq;
1932                 ring->irq_put = gen6_ring_put_irq;
1933                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1934                 ring->sync_to = gen6_ring_sync;
1935                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
1936                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
1937                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
1938                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
1939                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
1940                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
1941                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
1942                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
1943         } else {
1944                 ring->mmio_base = BSD_RING_BASE;
1945                 ring->flush = bsd_ring_flush;
1946                 ring->add_request = i9xx_add_request;
1947                 ring->get_seqno = ring_get_seqno;
1948                 ring->set_seqno = ring_set_seqno;
1949                 if (IS_GEN5(dev)) {
1950                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1951                         ring->irq_get = gen5_ring_get_irq;
1952                         ring->irq_put = gen5_ring_put_irq;
1953                 } else {
1954                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1955                         ring->irq_get = i9xx_ring_get_irq;
1956                         ring->irq_put = i9xx_ring_put_irq;
1957                 }
1958                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1959         }
1960         ring->init = init_ring_common;
1961
1962         return intel_init_ring_buffer(dev, ring);
1963 }
1964
1965 int intel_init_blt_ring_buffer(struct drm_device *dev)
1966 {
1967         drm_i915_private_t *dev_priv = dev->dev_private;
1968         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1969
1970         ring->name = "blitter ring";
1971         ring->id = BCS;
1972
1973         ring->mmio_base = BLT_RING_BASE;
1974         ring->write_tail = ring_write_tail;
1975         ring->flush = gen6_ring_flush;
1976         ring->add_request = gen6_add_request;
1977         ring->get_seqno = gen6_ring_get_seqno;
1978         ring->set_seqno = ring_set_seqno;
1979         ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1980         ring->irq_get = gen6_ring_get_irq;
1981         ring->irq_put = gen6_ring_put_irq;
1982         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1983         ring->sync_to = gen6_ring_sync;
1984         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
1985         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
1986         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
1987         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
1988         ring->signal_mbox[RCS] = GEN6_RBSYNC;
1989         ring->signal_mbox[VCS] = GEN6_VBSYNC;
1990         ring->signal_mbox[BCS] = GEN6_NOSYNC;
1991         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
1992         ring->init = init_ring_common;
1993
1994         return intel_init_ring_buffer(dev, ring);
1995 }
1996
1997 int intel_init_vebox_ring_buffer(struct drm_device *dev)
1998 {
1999         drm_i915_private_t *dev_priv = dev->dev_private;
2000         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2001
2002         ring->name = "video enhancement ring";
2003         ring->id = VECS;
2004
2005         ring->mmio_base = VEBOX_RING_BASE;
2006         ring->write_tail = ring_write_tail;
2007         ring->flush = gen6_ring_flush;
2008         ring->add_request = gen6_add_request;
2009         ring->get_seqno = gen6_ring_get_seqno;
2010         ring->set_seqno = ring_set_seqno;
2011         ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2012         ring->irq_get = hsw_vebox_get_irq;
2013         ring->irq_put = hsw_vebox_put_irq;
2014         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2015         ring->sync_to = gen6_ring_sync;
2016         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2017         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2018         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2019         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2020         ring->signal_mbox[RCS] = GEN6_RVESYNC;
2021         ring->signal_mbox[VCS] = GEN6_VVESYNC;
2022         ring->signal_mbox[BCS] = GEN6_BVESYNC;
2023         ring->signal_mbox[VECS] = GEN6_NOSYNC;
2024         ring->init = init_ring_common;
2025
2026         return intel_init_ring_buffer(dev, ring);
2027 }
2028
2029 int
2030 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2031 {
2032         int ret;
2033
2034         if (!ring->gpu_caches_dirty)
2035                 return 0;
2036
2037         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2038         if (ret)
2039                 return ret;
2040
2041         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2042
2043         ring->gpu_caches_dirty = false;
2044         return 0;
2045 }
2046
2047 int
2048 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2049 {
2050         uint32_t flush_domains;
2051         int ret;
2052
2053         flush_domains = 0;
2054         if (ring->gpu_caches_dirty)
2055                 flush_domains = I915_GEM_GPU_DOMAINS;
2056
2057         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2058         if (ret)
2059                 return ret;
2060
2061         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2062
2063         ring->gpu_caches_dirty = false;
2064         return 0;
2065 }