drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 284 {
 285         int ret;
 286
 287         if (!ring->fbc_dirty)
 288                 return 0;
 289
 290         ret = intel_ring_begin(ring, 4);
 291         if (ret)
 292                 return ret;
 293         intel_ring_emit(ring, MI_NOOP);
 294         /* WaFbcNukeOn3DBlt:ivb/hsw */
 295         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 296         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 297         intel_ring_emit(ring, value);
 298         intel_ring_advance(ring);
 299
 300         ring->fbc_dirty = false;
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 306                        u32 invalidate_domains, u32 flush_domains)
 307 {
 308         u32 flags = 0;
 309         struct pipe_control *pc = ring->private;
 310         u32 scratch_addr = pc->gtt_offset + 128;
 311         int ret;
 312
 313         /*
 314          * Ensure that any following seqno writes only happen when the render
 315          * cache is indeed flushed.
 316          *
 317          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 318          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 319          * don't try to be clever and just set it unconditionally.
 320          */
 321         flags |= PIPE_CONTROL_CS_STALL;
 322
 323         /* Just flush everything.  Experiments have shown that reducing the
 324          * number of bits based on the write domains has little performance
 325          * impact.
 326          */
 327         if (flush_domains) {
 328                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 329                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 330         }
 331         if (invalidate_domains) {
 332                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 333                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 337                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 338                 /*
 339                  * TLB invalidate requires a post-sync write.
 340                  */
 341                 flags |= PIPE_CONTROL_QW_WRITE;
 342                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 343
 344                 /* Workaround: we must issue a pipe_control with CS-stall bit
 345                  * set before a pipe_control command that has the state cache
 346                  * invalidate bit set. */
 347                 gen7_render_ring_cs_stall_wa(ring);
 348         }
 349
 350         ret = intel_ring_begin(ring, 4);
 351         if (ret)
 352                 return ret;
 353
 354         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 355         intel_ring_emit(ring, flags);
 356         intel_ring_emit(ring, scratch_addr);
 357         intel_ring_emit(ring, 0);
 358         intel_ring_advance(ring);
 359
 360         if (flush_domains)
 361                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 362
 363         return 0;
 364 }
 365
 366 static void ring_write_tail(struct intel_ring_buffer *ring,
 367                             u32 value)
 368 {
 369         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 370         I915_WRITE_TAIL(ring, value);
 371 }
 372
 373 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 374 {
 375         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 376         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 377                         RING_ACTHD(ring->mmio_base) : ACTHD;
 378
 379         return I915_READ(acthd_reg);
 380 }
 381
 382 static int init_ring_common(struct intel_ring_buffer *ring)
 383 {
 384         struct drm_device *dev = ring->dev;
 385         drm_i915_private_t *dev_priv = dev->dev_private;
 386         struct drm_i915_gem_object *obj = ring->obj;
 387         int ret = 0;
 388         u32 head;
 389
 390         if (HAS_FORCE_WAKE(dev))
 391                 gen6_gt_force_wake_get(dev_priv);
 392
 393         /* Stop the ring if it's running. */
 394         I915_WRITE_CTL(ring, 0);
 395         I915_WRITE_HEAD(ring, 0);
 396         ring->write_tail(ring, 0);
 397
 398         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 399
 400         /* G45 ring initialization fails to reset head to zero */
 401         if (head != 0) {
 402                 DRM_DEBUG_KMS("%s head not reset to zero "
 403                               "ctl %08x head %08x tail %08x start %08x\n",
 404                               ring->name,
 405                               I915_READ_CTL(ring),
 406                               I915_READ_HEAD(ring),
 407                               I915_READ_TAIL(ring),
 408                               I915_READ_START(ring));
 409
 410                 I915_WRITE_HEAD(ring, 0);
 411
 412                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 413                         DRM_ERROR("failed to set %s head to zero "
 414                                   "ctl %08x head %08x tail %08x start %08x\n",
 415                                   ring->name,
 416                                   I915_READ_CTL(ring),
 417                                   I915_READ_HEAD(ring),
 418                                   I915_READ_TAIL(ring),
 419                                   I915_READ_START(ring));
 420                 }
 421         }
 422
 423         /* Initialize the ring. This must happen _after_ we've cleared the ring
 424          * registers with the above sequence (the readback of the HEAD registers
 425          * also enforces ordering), otherwise the hw might lose the new ring
 426          * register values. */
 427         I915_WRITE_START(ring, obj->gtt_offset);
 428         I915_WRITE_CTL(ring,
 429                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 430                         | RING_VALID);
 431
 432         /* If the head is still not zero, the ring is dead */
 433         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 434                      I915_READ_START(ring) == obj->gtt_offset &&
 435                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 436                 DRM_ERROR("%s initialization failed "
 437                                 "ctl %08x head %08x tail %08x start %08x\n",
 438                                 ring->name,
 439                                 I915_READ_CTL(ring),
 440                                 I915_READ_HEAD(ring),
 441                                 I915_READ_TAIL(ring),
 442                                 I915_READ_START(ring));
 443                 ret = -EIO;
 444                 goto out;
 445         }
 446
 447         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 448                 i915_kernel_lost_context(ring->dev);
 449         else {
 450                 ring->head = I915_READ_HEAD(ring);
 451                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 452                 ring->space = ring_space(ring);
 453                 ring->last_retired_head = -1;
 454         }
 455
 456         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 457
 458 out:
 459         if (HAS_FORCE_WAKE(dev))
 460                 gen6_gt_force_wake_put(dev_priv);
 461
 462         return ret;
 463 }
 464
 465 static int
 466 init_pipe_control(struct intel_ring_buffer *ring)
 467 {
 468         struct pipe_control *pc;
 469         struct drm_i915_gem_object *obj;
 470         int ret;
 471
 472         if (ring->private)
 473                 return 0;
 474
 475         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 476         if (!pc)
 477                 return -ENOMEM;
 478
 479         obj = i915_gem_alloc_object(ring->dev, 4096);
 480         if (obj == NULL) {
 481                 DRM_ERROR("Failed to allocate seqno page\n");
 482                 ret = -ENOMEM;
 483                 goto err;
 484         }
 485
 486         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 487
 488         ret = i915_gem_object_pin(obj, 4096, true, false);
 489         if (ret)
 490                 goto err_unref;
 491
 492         pc->gtt_offset = obj->gtt_offset;
 493         pc->cpu_page = kmap(sg_page(obj->pages->sgl));
 494         if (pc->cpu_page == NULL) {
 495                 ret = -ENOMEM;
 496                 goto err_unpin;
 497         }
 498
 499         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 500                          ring->name, pc->gtt_offset);
 501
 502         pc->obj = obj;
 503         ring->private = pc;
 504         return 0;
 505
 506 err_unpin:
 507         i915_gem_object_unpin(obj);
 508 err_unref:
 509         drm_gem_object_unreference(&obj->base);
 510 err:
 511         kfree(pc);
 512         return ret;
 513 }
 514
 515 static void
 516 cleanup_pipe_control(struct intel_ring_buffer *ring)
 517 {
 518         struct pipe_control *pc = ring->private;
 519         struct drm_i915_gem_object *obj;
 520
 521         if (!ring->private)
 522                 return;
 523
 524         obj = pc->obj;
 525
 526         kunmap(sg_page(obj->pages->sgl));
 527         i915_gem_object_unpin(obj);
 528         drm_gem_object_unreference(&obj->base);
 529
 530         kfree(pc);
 531         ring->private = NULL;
 532 }
 533
 534 static int init_render_ring(struct intel_ring_buffer *ring)
 535 {
 536         struct drm_device *dev = ring->dev;
 537         struct drm_i915_private *dev_priv = dev->dev_private;
 538         int ret = init_ring_common(ring);
 539
 540         if (INTEL_INFO(dev)->gen > 3)
 541                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 542
 543         /* We need to disable the AsyncFlip performance optimisations in order
 544          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 545          * programmed to '1' on all products.
 546          *
 547          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 548          */
 549         if (INTEL_INFO(dev)->gen >= 6)
 550                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 551
 552         /* Required for the hardware to program scanline values for waiting */
 553         if (INTEL_INFO(dev)->gen == 6)
 554                 I915_WRITE(GFX_MODE,
 555                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 556
 557         if (IS_GEN7(dev))
 558                 I915_WRITE(GFX_MODE_GEN7,
 559                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 560                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 561
 562         if (INTEL_INFO(dev)->gen >= 5) {
 563                 ret = init_pipe_control(ring);
 564                 if (ret)
 565                         return ret;
 566         }
 567
 568         if (IS_GEN6(dev)) {
 569                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 570                  * "If this bit is set, STCunit will have LRA as replacement
 571                  *  policy. [...] This bit must be reset.  LRA replacement
 572                  *  policy is not supported."
 573                  */
 574                 I915_WRITE(CACHE_MODE_0,
 575                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 576
 577                 /* This is not explicitly set for GEN6, so read the register.
 578                  * see intel_ring_mi_set_context() for why we care.
 579                  * TODO: consider explicitly setting the bit for GEN5
 580                  */
 581                 ring->itlb_before_ctx_switch =
 582                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 583         }
 584
 585         if (INTEL_INFO(dev)->gen >= 6)
 586                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 587
 588         if (HAS_L3_GPU_CACHE(dev))
 589                 I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
 590
 591         return ret;
 592 }
 593
 594 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 595 {
 596         struct drm_device *dev = ring->dev;
 597
 598         if (!ring->private)
 599                 return;
 600
 601         if (HAS_BROKEN_CS_TLB(dev))
 602                 drm_gem_object_unreference(to_gem_object(ring->private));
 603
 604         cleanup_pipe_control(ring);
 605 }
 606
 607 static void
 608 update_mboxes(struct intel_ring_buffer *ring,
 609               u32 mmio_offset)
 610 {
 611 /* NB: In order to be able to do semaphore MBOX updates for varying number
 612  * of rings, it's easiest if we round up each individual update to a
 613  * multiple of 2 (since ring updates must always be a multiple of 2)
 614  * even though the actual update only requires 3 dwords.
 615  */
 616 #define MBOX_UPDATE_DWORDS 4
 617         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 618         intel_ring_emit(ring, mmio_offset);
 619         intel_ring_emit(ring, ring->outstanding_lazy_request);
 620         intel_ring_emit(ring, MI_NOOP);
 621 }
 622
 623 /**
 624  * gen6_add_request - Update the semaphore mailbox registers
 625  *
 626  * @ring - ring that is adding a request
 627  * @seqno - return seqno stuck into the ring
 628  *
 629  * Update the mailbox registers in the *other* rings with the current seqno.
 630  * This acts like a signal in the canonical semaphore.
 631  */
 632 static int
 633 gen6_add_request(struct intel_ring_buffer *ring)
 634 {
 635         struct drm_device *dev = ring->dev;
 636         struct drm_i915_private *dev_priv = dev->dev_private;
 637         struct intel_ring_buffer *useless;
 638         int i, ret;
 639
 640         ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
 641                                       MBOX_UPDATE_DWORDS) +
 642                                       4);
 643         if (ret)
 644                 return ret;
 645 #undef MBOX_UPDATE_DWORDS
 646
 647         for_each_ring(useless, dev_priv, i) {
 648                 u32 mbox_reg = ring->signal_mbox[i];
 649                 if (mbox_reg != GEN6_NOSYNC)
 650                         update_mboxes(ring, mbox_reg);
 651         }
 652
 653         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 654         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 655         intel_ring_emit(ring, ring->outstanding_lazy_request);
 656         intel_ring_emit(ring, MI_USER_INTERRUPT);
 657         intel_ring_advance(ring);
 658
 659         return 0;
 660 }
 661
 662 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 663                                               u32 seqno)
 664 {
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         return dev_priv->last_seqno < seqno;
 667 }
 668
 669 /**
 670  * intel_ring_sync - sync the waiter to the signaller on seqno
 671  *
 672  * @waiter - ring that is waiting
 673  * @signaller - ring which has, or will signal
 674  * @seqno - seqno which the waiter will block on
 675  */
 676 static int
 677 gen6_ring_sync(struct intel_ring_buffer *waiter,
 678                struct intel_ring_buffer *signaller,
 679                u32 seqno)
 680 {
 681         int ret;
 682         u32 dw1 = MI_SEMAPHORE_MBOX |
 683                   MI_SEMAPHORE_COMPARE |
 684                   MI_SEMAPHORE_REGISTER;
 685
 686         /* Throughout all of the GEM code, seqno passed implies our current
 687          * seqno is >= the last seqno executed. However for hardware the
 688          * comparison is strictly greater than.
 689          */
 690         seqno -= 1;
 691
 692         WARN_ON(signaller->semaphore_register[waiter->id] ==
 693                 MI_SEMAPHORE_SYNC_INVALID);
 694
 695         ret = intel_ring_begin(waiter, 4);
 696         if (ret)
 697                 return ret;
 698
 699         /* If seqno wrap happened, omit the wait with no-ops */
 700         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 701                 intel_ring_emit(waiter,
 702                                 dw1 |
 703                                 signaller->semaphore_register[waiter->id]);
 704                 intel_ring_emit(waiter, seqno);
 705                 intel_ring_emit(waiter, 0);
 706                 intel_ring_emit(waiter, MI_NOOP);
 707         } else {
 708                 intel_ring_emit(waiter, MI_NOOP);
 709                 intel_ring_emit(waiter, MI_NOOP);
 710                 intel_ring_emit(waiter, MI_NOOP);
 711                 intel_ring_emit(waiter, MI_NOOP);
 712         }
 713         intel_ring_advance(waiter);
 714
 715         return 0;
 716 }
 717
 718 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 719 do {                                                                    \
 720         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 721                  PIPE_CONTROL_DEPTH_STALL);                             \
 722         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 723         intel_ring_emit(ring__, 0);                                                     \
 724         intel_ring_emit(ring__, 0);                                                     \
 725 } while (0)
 726
 727 static int
 728 pc_render_add_request(struct intel_ring_buffer *ring)
 729 {
 730         struct pipe_control *pc = ring->private;
 731         u32 scratch_addr = pc->gtt_offset + 128;
 732         int ret;
 733
 734         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 735          * incoherent with writes to memory, i.e. completely fubar,
 736          * so we need to use PIPE_NOTIFY instead.
 737          *
 738          * However, we also need to workaround the qword write
 739          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 740          * memory before requesting an interrupt.
 741          */
 742         ret = intel_ring_begin(ring, 32);
 743         if (ret)
 744                 return ret;
 745
 746         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 747                         PIPE_CONTROL_WRITE_FLUSH |
 748                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 749         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 750         intel_ring_emit(ring, ring->outstanding_lazy_request);
 751         intel_ring_emit(ring, 0);
 752         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 753         scratch_addr += 128; /* write to separate cachelines */
 754         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 755         scratch_addr += 128;
 756         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 757         scratch_addr += 128;
 758         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 759         scratch_addr += 128;
 760         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 761         scratch_addr += 128;
 762         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 763
 764         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 765                         PIPE_CONTROL_WRITE_FLUSH |
 766                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 767                         PIPE_CONTROL_NOTIFY);
 768         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 769         intel_ring_emit(ring, ring->outstanding_lazy_request);
 770         intel_ring_emit(ring, 0);
 771         intel_ring_advance(ring);
 772
 773         return 0;
 774 }
 775
 776 static u32
 777 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 778 {
 779         /* Workaround to force correct ordering between irq and seqno writes on
 780          * ivb (and maybe also on snb) by reading from a CS register (like
 781          * ACTHD) before reading the status page. */
 782         if (!lazy_coherency)
 783                 intel_ring_get_active_head(ring);
 784         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 785 }
 786
 787 static u32
 788 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 789 {
 790         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 791 }
 792
 793 static void
 794 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 795 {
 796         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 797 }
 798
 799 static u32
 800 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 801 {
 802         struct pipe_control *pc = ring->private;
 803         return pc->cpu_page[0];
 804 }
 805
 806 static void
 807 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 808 {
 809         struct pipe_control *pc = ring->private;
 810         pc->cpu_page[0] = seqno;
 811 }
 812
 813 static bool
 814 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 815 {
 816         struct drm_device *dev = ring->dev;
 817         drm_i915_private_t *dev_priv = dev->dev_private;
 818         unsigned long flags;
 819
 820         if (!dev->irq_enabled)
 821                 return false;
 822
 823         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 824         if (ring->irq_refcount.gt++ == 0) {
 825                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 826                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 827                 POSTING_READ(GTIMR);
 828         }
 829         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 830
 831         return true;
 832 }
 833
 834 static void
 835 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 836 {
 837         struct drm_device *dev = ring->dev;
 838         drm_i915_private_t *dev_priv = dev->dev_private;
 839         unsigned long flags;
 840
 841         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 842         if (--ring->irq_refcount.gt == 0) {
 843                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 844                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 845                 POSTING_READ(GTIMR);
 846         }
 847         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 848 }
 849
 850 static bool
 851 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 852 {
 853         struct drm_device *dev = ring->dev;
 854         drm_i915_private_t *dev_priv = dev->dev_private;
 855         unsigned long flags;
 856
 857         if (!dev->irq_enabled)
 858                 return false;
 859
 860         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 861         if (ring->irq_refcount.gt++ == 0) {
 862                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 863                 I915_WRITE(IMR, dev_priv->irq_mask);
 864                 POSTING_READ(IMR);
 865         }
 866         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 867
 868         return true;
 869 }
 870
 871 static void
 872 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 873 {
 874         struct drm_device *dev = ring->dev;
 875         drm_i915_private_t *dev_priv = dev->dev_private;
 876         unsigned long flags;
 877
 878         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 879         if (--ring->irq_refcount.gt == 0) {
 880                 dev_priv->irq_mask |= ring->irq_enable_mask;
 881                 I915_WRITE(IMR, dev_priv->irq_mask);
 882                 POSTING_READ(IMR);
 883         }
 884         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 885 }
 886
 887 static bool
 888 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 889 {
 890         struct drm_device *dev = ring->dev;
 891         drm_i915_private_t *dev_priv = dev->dev_private;
 892         unsigned long flags;
 893
 894         if (!dev->irq_enabled)
 895                 return false;
 896
 897         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 898         if (ring->irq_refcount.gt++ == 0) {
 899                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 900                 I915_WRITE16(IMR, dev_priv->irq_mask);
 901                 POSTING_READ16(IMR);
 902         }
 903         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 904
 905         return true;
 906 }
 907
 908 static void
 909 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 910 {
 911         struct drm_device *dev = ring->dev;
 912         drm_i915_private_t *dev_priv = dev->dev_private;
 913         unsigned long flags;
 914
 915         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 916         if (--ring->irq_refcount.gt == 0) {
 917                 dev_priv->irq_mask |= ring->irq_enable_mask;
 918                 I915_WRITE16(IMR, dev_priv->irq_mask);
 919                 POSTING_READ16(IMR);
 920         }
 921         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 922 }
 923
 924 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 925 {
 926         struct drm_device *dev = ring->dev;
 927         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 928         u32 mmio = 0;
 929
 930         /* The ring status page addresses are no longer next to the rest of
 931          * the ring registers as of gen7.
 932          */
 933         if (IS_GEN7(dev)) {
 934                 switch (ring->id) {
 935                 case RCS:
 936                         mmio = RENDER_HWS_PGA_GEN7;
 937                         break;
 938                 case BCS:
 939                         mmio = BLT_HWS_PGA_GEN7;
 940                         break;
 941                 case VCS:
 942                         mmio = BSD_HWS_PGA_GEN7;
 943                         break;
 944                 case VECS:
 945                         mmio = VEBOX_HWS_PGA_GEN7;
 946                         break;
 947                 }
 948         } else if (IS_GEN6(ring->dev)) {
 949                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 950         } else {
 951                 mmio = RING_HWS_PGA(ring->mmio_base);
 952         }
 953
 954         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 955         POSTING_READ(mmio);
 956 }
 957
 958 static int
 959 bsd_ring_flush(struct intel_ring_buffer *ring,
 960                u32     invalidate_domains,
 961                u32     flush_domains)
 962 {
 963         int ret;
 964
 965         ret = intel_ring_begin(ring, 2);
 966         if (ret)
 967                 return ret;
 968
 969         intel_ring_emit(ring, MI_FLUSH);
 970         intel_ring_emit(ring, MI_NOOP);
 971         intel_ring_advance(ring);
 972         return 0;
 973 }
 974
 975 static int
 976 i9xx_add_request(struct intel_ring_buffer *ring)
 977 {
 978         int ret;
 979
 980         ret = intel_ring_begin(ring, 4);
 981         if (ret)
 982                 return ret;
 983
 984         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 985         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 986         intel_ring_emit(ring, ring->outstanding_lazy_request);
 987         intel_ring_emit(ring, MI_USER_INTERRUPT);
 988         intel_ring_advance(ring);
 989
 990         return 0;
 991 }
 992
 993 static bool
 994 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 995 {
 996         struct drm_device *dev = ring->dev;
 997         drm_i915_private_t *dev_priv = dev->dev_private;
 998         unsigned long flags;
 999
1000         if (!dev->irq_enabled)
1001                return false;
1002
1003         /* It looks like we need to prevent the gt from suspending while waiting
1004          * for an notifiy irq, otherwise irqs seem to get lost on at least the
1005          * blt/bsd rings on ivb. */
1006         gen6_gt_force_wake_get(dev_priv);
1007
1008         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1009         if (ring->irq_refcount.gt++ == 0) {
1010                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1011                         I915_WRITE_IMR(ring,
1012                                        ~(ring->irq_enable_mask |
1013                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1014                 else
1015                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1016                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
1017                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1018                 POSTING_READ(GTIMR);
1019         }
1020         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1021
1022         return true;
1023 }
1024
1025 static void
1026 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1027 {
1028         struct drm_device *dev = ring->dev;
1029         drm_i915_private_t *dev_priv = dev->dev_private;
1030         unsigned long flags;
1031
1032         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1033         if (--ring->irq_refcount.gt == 0) {
1034                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1035                         I915_WRITE_IMR(ring,
1036                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1037                 else
1038                         I915_WRITE_IMR(ring, ~0);
1039                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
1040                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1041                 POSTING_READ(GTIMR);
1042         }
1043         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1044
1045         gen6_gt_force_wake_put(dev_priv);
1046 }
1047
1048 static bool
1049 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1050 {
1051         struct drm_device *dev = ring->dev;
1052         struct drm_i915_private *dev_priv = dev->dev_private;
1053         unsigned long flags;
1054
1055         if (!dev->irq_enabled)
1056                 return false;
1057
1058         spin_lock_irqsave(&dev_priv->rps.lock, flags);
1059         if (ring->irq_refcount.pm++ == 0) {
1060                 u32 pm_imr = I915_READ(GEN6_PMIMR);
1061                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1062                 I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
1063                 POSTING_READ(GEN6_PMIMR);
1064         }
1065         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
1066
1067         return true;
1068 }
1069
1070 static void
1071 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1072 {
1073         struct drm_device *dev = ring->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         unsigned long flags;
1076
1077         if (!dev->irq_enabled)
1078                 return;
1079
1080         spin_lock_irqsave(&dev_priv->rps.lock, flags);
1081         if (--ring->irq_refcount.pm == 0) {
1082                 u32 pm_imr = I915_READ(GEN6_PMIMR);
1083                 I915_WRITE_IMR(ring, ~0);
1084                 I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
1085                 POSTING_READ(GEN6_PMIMR);
1086         }
1087         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
1088 }
1089
1090 static int
1091 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1092                          u32 offset, u32 length,
1093                          unsigned flags)
1094 {
1095         int ret;
1096
1097         ret = intel_ring_begin(ring, 2);
1098         if (ret)
1099                 return ret;
1100
1101         intel_ring_emit(ring,
1102                         MI_BATCH_BUFFER_START |
1103                         MI_BATCH_GTT |
1104                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1105         intel_ring_emit(ring, offset);
1106         intel_ring_advance(ring);
1107
1108         return 0;
1109 }
1110
1111 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1112 #define I830_BATCH_LIMIT (256*1024)
1113 static int
1114 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1115                                 u32 offset, u32 len,
1116                                 unsigned flags)
1117 {
1118         int ret;
1119
1120         if (flags & I915_DISPATCH_PINNED) {
1121                 ret = intel_ring_begin(ring, 4);
1122                 if (ret)
1123                         return ret;
1124
1125                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1126                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1127                 intel_ring_emit(ring, offset + len - 8);
1128                 intel_ring_emit(ring, MI_NOOP);
1129                 intel_ring_advance(ring);
1130         } else {
1131                 struct drm_i915_gem_object *obj = ring->private;
1132                 u32 cs_offset = obj->gtt_offset;
1133
1134                 if (len > I830_BATCH_LIMIT)
1135                         return -ENOSPC;
1136
1137                 ret = intel_ring_begin(ring, 9+3);
1138                 if (ret)
1139                         return ret;
1140                 /* Blit the batch (which has now all relocs applied) to the stable batch
1141                  * scratch bo area (so that the CS never stumbles over its tlb
1142                  * invalidation bug) ... */
1143                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1144                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1145                                 XY_SRC_COPY_BLT_WRITE_RGB);
1146                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1147                 intel_ring_emit(ring, 0);
1148                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1149                 intel_ring_emit(ring, cs_offset);
1150                 intel_ring_emit(ring, 0);
1151                 intel_ring_emit(ring, 4096);
1152                 intel_ring_emit(ring, offset);
1153                 intel_ring_emit(ring, MI_FLUSH);
1154
1155                 /* ... and execute it. */
1156                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1157                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1158                 intel_ring_emit(ring, cs_offset + len - 8);
1159                 intel_ring_advance(ring);
1160         }
1161
1162         return 0;
1163 }
1164
1165 static int
1166 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1167                          u32 offset, u32 len,
1168                          unsigned flags)
1169 {
1170         int ret;
1171
1172         ret = intel_ring_begin(ring, 2);
1173         if (ret)
1174                 return ret;
1175
1176         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1177         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1178         intel_ring_advance(ring);
1179
1180         return 0;
1181 }
1182
1183 static void cleanup_status_page(struct intel_ring_buffer *ring)
1184 {
1185         struct drm_i915_gem_object *obj;
1186
1187         obj = ring->status_page.obj;
1188         if (obj == NULL)
1189                 return;
1190
1191         kunmap(sg_page(obj->pages->sgl));
1192         i915_gem_object_unpin(obj);
1193         drm_gem_object_unreference(&obj->base);
1194         ring->status_page.obj = NULL;
1195 }
1196
1197 static int init_status_page(struct intel_ring_buffer *ring)
1198 {
1199         struct drm_device *dev = ring->dev;
1200         struct drm_i915_gem_object *obj;
1201         int ret;
1202
1203         obj = i915_gem_alloc_object(dev, 4096);
1204         if (obj == NULL) {
1205                 DRM_ERROR("Failed to allocate status page\n");
1206                 ret = -ENOMEM;
1207                 goto err;
1208         }
1209
1210         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1211
1212         ret = i915_gem_object_pin(obj, 4096, true, false);
1213         if (ret != 0) {
1214                 goto err_unref;
1215         }
1216
1217         ring->status_page.gfx_addr = obj->gtt_offset;
1218         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1219         if (ring->status_page.page_addr == NULL) {
1220                 ret = -ENOMEM;
1221                 goto err_unpin;
1222         }
1223         ring->status_page.obj = obj;
1224         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1225
1226         intel_ring_setup_status_page(ring);
1227         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1228                         ring->name, ring->status_page.gfx_addr);
1229
1230         return 0;
1231
1232 err_unpin:
1233         i915_gem_object_unpin(obj);
1234 err_unref:
1235         drm_gem_object_unreference(&obj->base);
1236 err:
1237         return ret;
1238 }
1239
1240 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1241 {
1242         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1243         u32 addr;
1244
1245         if (!dev_priv->status_page_dmah) {
1246                 dev_priv->status_page_dmah =
1247                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1248                 if (!dev_priv->status_page_dmah)
1249                         return -ENOMEM;
1250         }
1251
1252         addr = dev_priv->status_page_dmah->busaddr;
1253         if (INTEL_INFO(ring->dev)->gen >= 4)
1254                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1255         I915_WRITE(HWS_PGA, addr);
1256
1257         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1258         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1259
1260         return 0;
1261 }
1262
1263 static int intel_init_ring_buffer(struct drm_device *dev,
1264                                   struct intel_ring_buffer *ring)
1265 {
1266         struct drm_i915_gem_object *obj;
1267         struct drm_i915_private *dev_priv = dev->dev_private;
1268         int ret;
1269
1270         ring->dev = dev;
1271         INIT_LIST_HEAD(&ring->active_list);
1272         INIT_LIST_HEAD(&ring->request_list);
1273         ring->size = 32 * PAGE_SIZE;
1274         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1275
1276         init_waitqueue_head(&ring->irq_queue);
1277
1278         if (I915_NEED_GFX_HWS(dev)) {
1279                 ret = init_status_page(ring);
1280                 if (ret)
1281                         return ret;
1282         } else {
1283                 BUG_ON(ring->id != RCS);
1284                 ret = init_phys_hws_pga(ring);
1285                 if (ret)
1286                         return ret;
1287         }
1288
1289         obj = NULL;
1290         if (!HAS_LLC(dev))
1291                 obj = i915_gem_object_create_stolen(dev, ring->size);
1292         if (obj == NULL)
1293                 obj = i915_gem_alloc_object(dev, ring->size);
1294         if (obj == NULL) {
1295                 DRM_ERROR("Failed to allocate ringbuffer\n");
1296                 ret = -ENOMEM;
1297                 goto err_hws;
1298         }
1299
1300         ring->obj = obj;
1301
1302         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1303         if (ret)
1304                 goto err_unref;
1305
1306         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1307         if (ret)
1308                 goto err_unpin;
1309
1310         ring->virtual_start =
1311                 ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
1312                            ring->size);
1313         if (ring->virtual_start == NULL) {
1314                 DRM_ERROR("Failed to map ringbuffer.\n");
1315                 ret = -EINVAL;
1316                 goto err_unpin;
1317         }
1318
1319         ret = ring->init(ring);
1320         if (ret)
1321                 goto err_unmap;
1322
1323         /* Workaround an erratum on the i830 which causes a hang if
1324          * the TAIL pointer points to within the last 2 cachelines
1325          * of the buffer.
1326          */
1327         ring->effective_size = ring->size;
1328         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1329                 ring->effective_size -= 128;
1330
1331         return 0;
1332
1333 err_unmap:
1334         iounmap(ring->virtual_start);
1335 err_unpin:
1336         i915_gem_object_unpin(obj);
1337 err_unref:
1338         drm_gem_object_unreference(&obj->base);
1339         ring->obj = NULL;
1340 err_hws:
1341         cleanup_status_page(ring);
1342         return ret;
1343 }
1344
1345 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1346 {
1347         struct drm_i915_private *dev_priv;
1348         int ret;
1349
1350         if (ring->obj == NULL)
1351                 return;
1352
1353         /* Disable the ring buffer. The ring must be idle at this point */
1354         dev_priv = ring->dev->dev_private;
1355         ret = intel_ring_idle(ring);
1356         if (ret)
1357                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1358                           ring->name, ret);
1359
1360         I915_WRITE_CTL(ring, 0);
1361
1362         iounmap(ring->virtual_start);
1363
1364         i915_gem_object_unpin(ring->obj);
1365         drm_gem_object_unreference(&ring->obj->base);
1366         ring->obj = NULL;
1367
1368         if (ring->cleanup)
1369                 ring->cleanup(ring);
1370
1371         cleanup_status_page(ring);
1372 }
1373
1374 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1375 {
1376         int ret;
1377
1378         ret = i915_wait_seqno(ring, seqno);
1379         if (!ret)
1380                 i915_gem_retire_requests_ring(ring);
1381
1382         return ret;
1383 }
1384
1385 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1386 {
1387         struct drm_i915_gem_request *request;
1388         u32 seqno = 0;
1389         int ret;
1390
1391         i915_gem_retire_requests_ring(ring);
1392
1393         if (ring->last_retired_head != -1) {
1394                 ring->head = ring->last_retired_head;
1395                 ring->last_retired_head = -1;
1396                 ring->space = ring_space(ring);
1397                 if (ring->space >= n)
1398                         return 0;
1399         }
1400
1401         list_for_each_entry(request, &ring->request_list, list) {
1402                 int space;
1403
1404                 if (request->tail == -1)
1405                         continue;
1406
1407                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1408                 if (space < 0)
1409                         space += ring->size;
1410                 if (space >= n) {
1411                         seqno = request->seqno;
1412                         break;
1413                 }
1414
1415                 /* Consume this request in case we need more space than
1416                  * is available and so need to prevent a race between
1417                  * updating last_retired_head and direct reads of
1418                  * I915_RING_HEAD. It also provides a nice sanity check.
1419                  */
1420                 request->tail = -1;
1421         }
1422
1423         if (seqno == 0)
1424                 return -ENOSPC;
1425
1426         ret = intel_ring_wait_seqno(ring, seqno);
1427         if (ret)
1428                 return ret;
1429
1430         if (WARN_ON(ring->last_retired_head == -1))
1431                 return -ENOSPC;
1432
1433         ring->head = ring->last_retired_head;
1434         ring->last_retired_head = -1;
1435         ring->space = ring_space(ring);
1436         if (WARN_ON(ring->space < n))
1437                 return -ENOSPC;
1438
1439         return 0;
1440 }
1441
1442 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1443 {
1444         struct drm_device *dev = ring->dev;
1445         struct drm_i915_private *dev_priv = dev->dev_private;
1446         unsigned long end;
1447         int ret;
1448
1449         ret = intel_ring_wait_request(ring, n);
1450         if (ret != -ENOSPC)
1451                 return ret;
1452
1453         trace_i915_ring_wait_begin(ring);
1454         /* With GEM the hangcheck timer should kick us out of the loop,
1455          * leaving it early runs the risk of corrupting GEM state (due
1456          * to running on almost untested codepaths). But on resume
1457          * timers don't work yet, so prevent a complete hang in that
1458          * case by choosing an insanely large timeout. */
1459         end = jiffies + 60 * HZ;
1460
1461         do {
1462                 ring->head = I915_READ_HEAD(ring);
1463                 ring->space = ring_space(ring);
1464                 if (ring->space >= n) {
1465                         trace_i915_ring_wait_end(ring);
1466                         return 0;
1467                 }
1468
1469                 if (dev->primary->master) {
1470                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1471                         if (master_priv->sarea_priv)
1472                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1473                 }
1474
1475                 msleep(1);
1476
1477                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1478                                            dev_priv->mm.interruptible);
1479                 if (ret)
1480                         return ret;
1481         } while (!time_after(jiffies, end));
1482         trace_i915_ring_wait_end(ring);
1483         return -EBUSY;
1484 }
1485
1486 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1487 {
1488         uint32_t __iomem *virt;
1489         int rem = ring->size - ring->tail;
1490
1491         if (ring->space < rem) {
1492                 int ret = ring_wait_for_space(ring, rem);
1493                 if (ret)
1494                         return ret;
1495         }
1496
1497         virt = ring->virtual_start + ring->tail;
1498         rem /= 4;
1499         while (rem--)
1500                 iowrite32(MI_NOOP, virt++);
1501
1502         ring->tail = 0;
1503         ring->space = ring_space(ring);
1504
1505         return 0;
1506 }
1507
1508 int intel_ring_idle(struct intel_ring_buffer *ring)
1509 {
1510         u32 seqno;
1511         int ret;
1512
1513         /* We need to add any requests required to flush the objects and ring */
1514         if (ring->outstanding_lazy_request) {
1515                 ret = i915_add_request(ring, NULL);
1516                 if (ret)
1517                         return ret;
1518         }
1519
1520         /* Wait upon the last request to be completed */
1521         if (list_empty(&ring->request_list))
1522                 return 0;
1523
1524         seqno = list_entry(ring->request_list.prev,
1525                            struct drm_i915_gem_request,
1526                            list)->seqno;
1527
1528         return i915_wait_seqno(ring, seqno);
1529 }
1530
1531 static int
1532 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1533 {
1534         if (ring->outstanding_lazy_request)
1535                 return 0;
1536
1537         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1538 }
1539
1540 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1541                               int bytes)
1542 {
1543         int ret;
1544
1545         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1546                 ret = intel_wrap_ring_buffer(ring);
1547                 if (unlikely(ret))
1548                         return ret;
1549         }
1550
1551         if (unlikely(ring->space < bytes)) {
1552                 ret = ring_wait_for_space(ring, bytes);
1553                 if (unlikely(ret))
1554                         return ret;
1555         }
1556
1557         ring->space -= bytes;
1558         return 0;
1559 }
1560
1561 int intel_ring_begin(struct intel_ring_buffer *ring,
1562                      int num_dwords)
1563 {
1564         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1565         int ret;
1566
1567         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1568                                    dev_priv->mm.interruptible);
1569         if (ret)
1570                 return ret;
1571
1572         /* Preallocate the olr before touching the ring */
1573         ret = intel_ring_alloc_seqno(ring);
1574         if (ret)
1575                 return ret;
1576
1577         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1578 }
1579
1580 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1581 {
1582         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1583
1584         BUG_ON(ring->outstanding_lazy_request);
1585
1586         if (INTEL_INFO(ring->dev)->gen >= 6) {
1587                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1588                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1589         }
1590
1591         ring->set_seqno(ring, seqno);
1592         ring->hangcheck.seqno = seqno;
1593 }
1594
1595 void intel_ring_advance(struct intel_ring_buffer *ring)
1596 {
1597         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1598
1599         ring->tail &= ring->size - 1;
1600         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1601                 return;
1602         ring->write_tail(ring, ring->tail);
1603 }
1604
1605
1606 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1607                                      u32 value)
1608 {
1609         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1610
1611        /* Every tail move must follow the sequence below */
1612
1613         /* Disable notification that the ring is IDLE. The GT
1614          * will then assume that it is busy and bring it out of rc6.
1615          */
1616         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1617                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1618
1619         /* Clear the context id. Here be magic! */
1620         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1621
1622         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1623         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1624                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1625                      50))
1626                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1627
1628         /* Now that the ring is fully powered up, update the tail */
1629         I915_WRITE_TAIL(ring, value);
1630         POSTING_READ(RING_TAIL(ring->mmio_base));
1631
1632         /* Let the ring send IDLE messages to the GT again,
1633          * and so let it sleep to conserve power when idle.
1634          */
1635         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1636                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1637 }
1638
1639 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1640                                u32 invalidate, u32 flush)
1641 {
1642         uint32_t cmd;
1643         int ret;
1644
1645         ret = intel_ring_begin(ring, 4);
1646         if (ret)
1647                 return ret;
1648
1649         cmd = MI_FLUSH_DW;
1650         /*
1651          * Bspec vol 1c.5 - video engine command streamer:
1652          * "If ENABLED, all TLBs will be invalidated once the flush
1653          * operation is complete. This bit is only valid when the
1654          * Post-Sync Operation field is a value of 1h or 3h."
1655          */
1656         if (invalidate & I915_GEM_GPU_DOMAINS)
1657                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1658                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1659         intel_ring_emit(ring, cmd);
1660         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1661         intel_ring_emit(ring, 0);
1662         intel_ring_emit(ring, MI_NOOP);
1663         intel_ring_advance(ring);
1664         return 0;
1665 }
1666
1667 static int
1668 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1669                               u32 offset, u32 len,
1670                               unsigned flags)
1671 {
1672         int ret;
1673
1674         ret = intel_ring_begin(ring, 2);
1675         if (ret)
1676                 return ret;
1677
1678         intel_ring_emit(ring,
1679                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1680                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1681         /* bit0-7 is the length on GEN6+ */
1682         intel_ring_emit(ring, offset);
1683         intel_ring_advance(ring);
1684
1685         return 0;
1686 }
1687
1688 static int
1689 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1690                               u32 offset, u32 len,
1691                               unsigned flags)
1692 {
1693         int ret;
1694
1695         ret = intel_ring_begin(ring, 2);
1696         if (ret)
1697                 return ret;
1698
1699         intel_ring_emit(ring,
1700                         MI_BATCH_BUFFER_START |
1701                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1702         /* bit0-7 is the length on GEN6+ */
1703         intel_ring_emit(ring, offset);
1704         intel_ring_advance(ring);
1705
1706         return 0;
1707 }
1708
1709 /* Blitter support (SandyBridge+) */
1710
1711 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1712                            u32 invalidate, u32 flush)
1713 {
1714         struct drm_device *dev = ring->dev;
1715         uint32_t cmd;
1716         int ret;
1717
1718         ret = intel_ring_begin(ring, 4);
1719         if (ret)
1720                 return ret;
1721
1722         cmd = MI_FLUSH_DW;
1723         /*
1724          * Bspec vol 1c.3 - blitter engine command streamer:
1725          * "If ENABLED, all TLBs will be invalidated once the flush
1726          * operation is complete. This bit is only valid when the
1727          * Post-Sync Operation field is a value of 1h or 3h."
1728          */
1729         if (invalidate & I915_GEM_DOMAIN_RENDER)
1730                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1731                         MI_FLUSH_DW_OP_STOREDW;
1732         intel_ring_emit(ring, cmd);
1733         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1734         intel_ring_emit(ring, 0);
1735         intel_ring_emit(ring, MI_NOOP);
1736         intel_ring_advance(ring);
1737
1738         if (IS_GEN7(dev) && flush)
1739                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1740
1741         return 0;
1742 }
1743
1744 int intel_init_render_ring_buffer(struct drm_device *dev)
1745 {
1746         drm_i915_private_t *dev_priv = dev->dev_private;
1747         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1748
1749         ring->name = "render ring";
1750         ring->id = RCS;
1751         ring->mmio_base = RENDER_RING_BASE;
1752
1753         if (INTEL_INFO(dev)->gen >= 6) {
1754                 ring->add_request = gen6_add_request;
1755                 ring->flush = gen7_render_ring_flush;
1756                 if (INTEL_INFO(dev)->gen == 6)
1757                         ring->flush = gen6_render_ring_flush;
1758                 ring->irq_get = gen6_ring_get_irq;
1759                 ring->irq_put = gen6_ring_put_irq;
1760                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1761                 ring->get_seqno = gen6_ring_get_seqno;
1762                 ring->set_seqno = ring_set_seqno;
1763                 ring->sync_to = gen6_ring_sync;
1764                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1765                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1766                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1767                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1768                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1769                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1770                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1771                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1772         } else if (IS_GEN5(dev)) {
1773                 ring->add_request = pc_render_add_request;
1774                 ring->flush = gen4_render_ring_flush;
1775                 ring->get_seqno = pc_render_get_seqno;
1776                 ring->set_seqno = pc_render_set_seqno;
1777                 ring->irq_get = gen5_ring_get_irq;
1778                 ring->irq_put = gen5_ring_put_irq;
1779                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1780                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1781         } else {
1782                 ring->add_request = i9xx_add_request;
1783                 if (INTEL_INFO(dev)->gen < 4)
1784                         ring->flush = gen2_render_ring_flush;
1785                 else
1786                         ring->flush = gen4_render_ring_flush;
1787                 ring->get_seqno = ring_get_seqno;
1788                 ring->set_seqno = ring_set_seqno;
1789                 if (IS_GEN2(dev)) {
1790                         ring->irq_get = i8xx_ring_get_irq;
1791                         ring->irq_put = i8xx_ring_put_irq;
1792                 } else {
1793                         ring->irq_get = i9xx_ring_get_irq;
1794                         ring->irq_put = i9xx_ring_put_irq;
1795                 }
1796                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1797         }
1798         ring->write_tail = ring_write_tail;
1799         if (IS_HASWELL(dev))
1800                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1801         else if (INTEL_INFO(dev)->gen >= 6)
1802                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1803         else if (INTEL_INFO(dev)->gen >= 4)
1804                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1805         else if (IS_I830(dev) || IS_845G(dev))
1806                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1807         else
1808                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1809         ring->init = init_render_ring;
1810         ring->cleanup = render_ring_cleanup;
1811
1812         /* Workaround batchbuffer to combat CS tlb bug. */
1813         if (HAS_BROKEN_CS_TLB(dev)) {
1814                 struct drm_i915_gem_object *obj;
1815                 int ret;
1816
1817                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1818                 if (obj == NULL) {
1819                         DRM_ERROR("Failed to allocate batch bo\n");
1820                         return -ENOMEM;
1821                 }
1822
1823                 ret = i915_gem_object_pin(obj, 0, true, false);
1824                 if (ret != 0) {
1825                         drm_gem_object_unreference(&obj->base);
1826                         DRM_ERROR("Failed to ping batch bo\n");
1827                         return ret;
1828                 }
1829
1830                 ring->private = obj;
1831         }
1832
1833         return intel_init_ring_buffer(dev, ring);
1834 }
1835
1836 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1837 {
1838         drm_i915_private_t *dev_priv = dev->dev_private;
1839         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1840         int ret;
1841
1842         ring->name = "render ring";
1843         ring->id = RCS;
1844         ring->mmio_base = RENDER_RING_BASE;
1845
1846         if (INTEL_INFO(dev)->gen >= 6) {
1847                 /* non-kms not supported on gen6+ */
1848                 return -ENODEV;
1849         }
1850
1851         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1852          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1853          * the special gen5 functions. */
1854         ring->add_request = i9xx_add_request;
1855         if (INTEL_INFO(dev)->gen < 4)
1856                 ring->flush = gen2_render_ring_flush;
1857         else
1858                 ring->flush = gen4_render_ring_flush;
1859         ring->get_seqno = ring_get_seqno;
1860         ring->set_seqno = ring_set_seqno;
1861         if (IS_GEN2(dev)) {
1862                 ring->irq_get = i8xx_ring_get_irq;
1863                 ring->irq_put = i8xx_ring_put_irq;
1864         } else {
1865                 ring->irq_get = i9xx_ring_get_irq;
1866                 ring->irq_put = i9xx_ring_put_irq;
1867         }
1868         ring->irq_enable_mask = I915_USER_INTERRUPT;
1869         ring->write_tail = ring_write_tail;
1870         if (INTEL_INFO(dev)->gen >= 4)
1871                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1872         else if (IS_I830(dev) || IS_845G(dev))
1873                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1874         else
1875                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1876         ring->init = init_render_ring;
1877         ring->cleanup = render_ring_cleanup;
1878
1879         ring->dev = dev;
1880         INIT_LIST_HEAD(&ring->active_list);
1881         INIT_LIST_HEAD(&ring->request_list);
1882
1883         ring->size = size;
1884         ring->effective_size = ring->size;
1885         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1886                 ring->effective_size -= 128;
1887
1888         ring->virtual_start = ioremap_wc(start, size);
1889         if (ring->virtual_start == NULL) {
1890                 DRM_ERROR("can not ioremap virtual address for"
1891                           " ring buffer\n");
1892                 return -ENOMEM;
1893         }
1894
1895         if (!I915_NEED_GFX_HWS(dev)) {
1896                 ret = init_phys_hws_pga(ring);
1897                 if (ret)
1898                         return ret;
1899         }
1900
1901         return 0;
1902 }
1903
1904 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1905 {
1906         drm_i915_private_t *dev_priv = dev->dev_private;
1907         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1908
1909         ring->name = "bsd ring";
1910         ring->id = VCS;
1911
1912         ring->write_tail = ring_write_tail;
1913         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1914                 ring->mmio_base = GEN6_BSD_RING_BASE;
1915                 /* gen6 bsd needs a special wa for tail updates */
1916                 if (IS_GEN6(dev))
1917                         ring->write_tail = gen6_bsd_ring_write_tail;
1918                 ring->flush = gen6_bsd_ring_flush;
1919                 ring->add_request = gen6_add_request;
1920                 ring->get_seqno = gen6_ring_get_seqno;
1921                 ring->set_seqno = ring_set_seqno;
1922                 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1923                 ring->irq_get = gen6_ring_get_irq;
1924                 ring->irq_put = gen6_ring_put_irq;
1925                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1926                 ring->sync_to = gen6_ring_sync;
1927                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
1928                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
1929                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
1930                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
1931                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
1932                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
1933                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
1934                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
1935         } else {
1936                 ring->mmio_base = BSD_RING_BASE;
1937                 ring->flush = bsd_ring_flush;
1938                 ring->add_request = i9xx_add_request;
1939                 ring->get_seqno = ring_get_seqno;
1940                 ring->set_seqno = ring_set_seqno;
1941                 if (IS_GEN5(dev)) {
1942                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1943                         ring->irq_get = gen5_ring_get_irq;
1944                         ring->irq_put = gen5_ring_put_irq;
1945                 } else {
1946                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1947                         ring->irq_get = i9xx_ring_get_irq;
1948                         ring->irq_put = i9xx_ring_put_irq;
1949                 }
1950                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1951         }
1952         ring->init = init_ring_common;
1953
1954         return intel_init_ring_buffer(dev, ring);
1955 }
1956
1957 int intel_init_blt_ring_buffer(struct drm_device *dev)
1958 {
1959         drm_i915_private_t *dev_priv = dev->dev_private;
1960         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1961
1962         ring->name = "blitter ring";
1963         ring->id = BCS;
1964
1965         ring->mmio_base = BLT_RING_BASE;
1966         ring->write_tail = ring_write_tail;
1967         ring->flush = gen6_ring_flush;
1968         ring->add_request = gen6_add_request;
1969         ring->get_seqno = gen6_ring_get_seqno;
1970         ring->set_seqno = ring_set_seqno;
1971         ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1972         ring->irq_get = gen6_ring_get_irq;
1973         ring->irq_put = gen6_ring_put_irq;
1974         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1975         ring->sync_to = gen6_ring_sync;
1976         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
1977         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
1978         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
1979         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
1980         ring->signal_mbox[RCS] = GEN6_RBSYNC;
1981         ring->signal_mbox[VCS] = GEN6_VBSYNC;
1982         ring->signal_mbox[BCS] = GEN6_NOSYNC;
1983         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
1984         ring->init = init_ring_common;
1985
1986         return intel_init_ring_buffer(dev, ring);
1987 }
1988
1989 int intel_init_vebox_ring_buffer(struct drm_device *dev)
1990 {
1991         drm_i915_private_t *dev_priv = dev->dev_private;
1992         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
1993
1994         ring->name = "video enhancement ring";
1995         ring->id = VECS;
1996
1997         ring->mmio_base = VEBOX_RING_BASE;
1998         ring->write_tail = ring_write_tail;
1999         ring->flush = gen6_ring_flush;
2000         ring->add_request = gen6_add_request;
2001         ring->get_seqno = gen6_ring_get_seqno;
2002         ring->set_seqno = ring_set_seqno;
2003         ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT |
2004                 PM_VEBOX_CS_ERROR_INTERRUPT;
2005         ring->irq_get = hsw_vebox_get_irq;
2006         ring->irq_put = hsw_vebox_put_irq;
2007         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2008         ring->sync_to = gen6_ring_sync;
2009         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2010         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2011         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2012         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2013         ring->signal_mbox[RCS] = GEN6_RVESYNC;
2014         ring->signal_mbox[VCS] = GEN6_VVESYNC;
2015         ring->signal_mbox[BCS] = GEN6_BVESYNC;
2016         ring->signal_mbox[VECS] = GEN6_NOSYNC;
2017         ring->init = init_ring_common;
2018
2019         return intel_init_ring_buffer(dev, ring);
2020 }
2021
2022 int
2023 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2024 {
2025         int ret;
2026
2027         if (!ring->gpu_caches_dirty)
2028                 return 0;
2029
2030         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2031         if (ret)
2032                 return ret;
2033
2034         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2035
2036         ring->gpu_caches_dirty = false;
2037         return 0;
2038 }
2039
2040 int
2041 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2042 {
2043         uint32_t flush_domains;
2044         int ret;
2045
2046         flush_domains = 0;
2047         if (ring->gpu_caches_dirty)
2048                 flush_domains = I915_GEM_GPU_DOMAINS;
2049
2050         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2051         if (ret)
2052                 return ret;
2053
2054         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2055
2056         ring->gpu_caches_dirty = false;
2057         return 0;
2058 }