2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
36 static inline int ring_space(struct intel_ring_buffer *ring)
38 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
44 void __intel_ring_advance(struct intel_ring_buffer *ring)
46 struct drm_i915_private *dev_priv = ring->dev->dev_private;
48 ring->tail &= ring->size - 1;
49 if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
51 ring->write_tail(ring, ring->tail);
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
69 ret = intel_ring_begin(ring, 2);
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
85 struct drm_device *dev = ring->dev;
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
101 * I915_GEM_DOMAIN_COMMAND may not exist?
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
127 ret = intel_ring_begin(ring, 2);
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 * And the workaround for these two requires this workaround first:
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 u32 scratch_addr = ring->scratch.gtt_offset + 128;
182 ret = intel_ring_begin(ring, 6);
186 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
188 PIPE_CONTROL_STALL_AT_SCOREBOARD);
189 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
190 intel_ring_emit(ring, 0); /* low dword */
191 intel_ring_emit(ring, 0); /* high dword */
192 intel_ring_emit(ring, MI_NOOP);
193 intel_ring_advance(ring);
195 ret = intel_ring_begin(ring, 6);
199 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
201 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
202 intel_ring_emit(ring, 0);
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, MI_NOOP);
205 intel_ring_advance(ring);
211 gen6_render_ring_flush(struct intel_ring_buffer *ring,
212 u32 invalidate_domains, u32 flush_domains)
215 u32 scratch_addr = ring->scratch.gtt_offset + 128;
218 /* Force SNB workarounds for PIPE_CONTROL flushes */
219 ret = intel_emit_post_sync_nonzero_flush(ring);
223 /* Just flush everything. Experiments have shown that reducing the
224 * number of bits based on the write domains has little performance
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
231 * Ensure that any following seqno writes only happen
232 * when the render cache is indeed flushed.
234 flags |= PIPE_CONTROL_CS_STALL;
236 if (invalidate_domains) {
237 flags |= PIPE_CONTROL_TLB_INVALIDATE;
238 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
239 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
244 * TLB invalidate requires a post-sync write.
246 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
249 ret = intel_ring_begin(ring, 4);
253 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
254 intel_ring_emit(ring, flags);
255 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
256 intel_ring_emit(ring, 0);
257 intel_ring_advance(ring);
263 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
267 ret = intel_ring_begin(ring, 4);
271 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
272 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
273 PIPE_CONTROL_STALL_AT_SCOREBOARD);
274 intel_ring_emit(ring, 0);
275 intel_ring_emit(ring, 0);
276 intel_ring_advance(ring);
281 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
285 if (!ring->fbc_dirty)
288 ret = intel_ring_begin(ring, 6);
291 /* WaFbcNukeOn3DBlt:ivb/hsw */
292 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
293 intel_ring_emit(ring, MSG_FBC_REND_STATE);
294 intel_ring_emit(ring, value);
295 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
296 intel_ring_emit(ring, MSG_FBC_REND_STATE);
297 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
298 intel_ring_advance(ring);
300 ring->fbc_dirty = false;
305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
306 u32 invalidate_domains, u32 flush_domains)
309 u32 scratch_addr = ring->scratch.gtt_offset + 128;
313 * Ensure that any following seqno writes only happen when the render
314 * cache is indeed flushed.
316 * Workaround: 4th PIPE_CONTROL command (except the ones with only
317 * read-cache invalidate bits set) must have the CS_STALL bit set. We
318 * don't try to be clever and just set it unconditionally.
320 flags |= PIPE_CONTROL_CS_STALL;
322 /* Just flush everything. Experiments have shown that reducing the
323 * number of bits based on the write domains has little performance
327 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
328 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
330 if (invalidate_domains) {
331 flags |= PIPE_CONTROL_TLB_INVALIDATE;
332 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
333 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
334 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
335 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
336 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
338 * TLB invalidate requires a post-sync write.
340 flags |= PIPE_CONTROL_QW_WRITE;
341 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
343 /* Workaround: we must issue a pipe_control with CS-stall bit
344 * set before a pipe_control command that has the state cache
345 * invalidate bit set. */
346 gen7_render_ring_cs_stall_wa(ring);
349 ret = intel_ring_begin(ring, 4);
353 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
354 intel_ring_emit(ring, flags);
355 intel_ring_emit(ring, scratch_addr);
356 intel_ring_emit(ring, 0);
357 intel_ring_advance(ring);
359 if (!invalidate_domains && flush_domains)
360 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
366 gen8_render_ring_flush(struct intel_ring_buffer *ring,
367 u32 invalidate_domains, u32 flush_domains)
370 u32 scratch_addr = ring->scratch.gtt_offset + 128;
373 flags |= PIPE_CONTROL_CS_STALL;
376 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
377 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
379 if (invalidate_domains) {
380 flags |= PIPE_CONTROL_TLB_INVALIDATE;
381 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
382 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
383 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
384 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
385 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
386 flags |= PIPE_CONTROL_QW_WRITE;
387 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
390 ret = intel_ring_begin(ring, 6);
394 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
395 intel_ring_emit(ring, flags);
396 intel_ring_emit(ring, scratch_addr);
397 intel_ring_emit(ring, 0);
398 intel_ring_emit(ring, 0);
399 intel_ring_emit(ring, 0);
400 intel_ring_advance(ring);
406 static void ring_write_tail(struct intel_ring_buffer *ring,
409 struct drm_i915_private *dev_priv = ring->dev->dev_private;
410 I915_WRITE_TAIL(ring, value);
413 u64 intel_ring_get_active_head(struct intel_ring_buffer *ring)
415 struct drm_i915_private *dev_priv = ring->dev->dev_private;
418 if (INTEL_INFO(ring->dev)->gen >= 8)
419 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
420 RING_ACTHD_UDW(ring->mmio_base));
421 else if (INTEL_INFO(ring->dev)->gen >= 4)
422 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
424 acthd = I915_READ(ACTHD);
429 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
431 struct drm_i915_private *dev_priv = ring->dev->dev_private;
434 addr = dev_priv->status_page_dmah->busaddr;
435 if (INTEL_INFO(ring->dev)->gen >= 4)
436 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
437 I915_WRITE(HWS_PGA, addr);
440 static bool stop_ring(struct intel_ring_buffer *ring)
442 struct drm_i915_private *dev_priv = to_i915(ring->dev);
444 if (!IS_GEN2(ring->dev)) {
445 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
446 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
447 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
452 I915_WRITE_CTL(ring, 0);
453 I915_WRITE_HEAD(ring, 0);
454 ring->write_tail(ring, 0);
456 if (!IS_GEN2(ring->dev)) {
457 (void)I915_READ_CTL(ring);
458 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
461 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
464 static int init_ring_common(struct intel_ring_buffer *ring)
466 struct drm_device *dev = ring->dev;
467 struct drm_i915_private *dev_priv = dev->dev_private;
468 struct drm_i915_gem_object *obj = ring->obj;
471 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
473 if (!stop_ring(ring)) {
474 /* G45 ring initialization often fails to reset head to zero */
475 DRM_DEBUG_KMS("%s head not reset to zero "
476 "ctl %08x head %08x tail %08x start %08x\n",
479 I915_READ_HEAD(ring),
480 I915_READ_TAIL(ring),
481 I915_READ_START(ring));
483 if (!stop_ring(ring)) {
484 DRM_ERROR("failed to set %s head to zero "
485 "ctl %08x head %08x tail %08x start %08x\n",
488 I915_READ_HEAD(ring),
489 I915_READ_TAIL(ring),
490 I915_READ_START(ring));
496 if (I915_NEED_GFX_HWS(dev))
497 intel_ring_setup_status_page(ring);
499 ring_setup_phys_status_page(ring);
501 /* Initialize the ring. This must happen _after_ we've cleared the ring
502 * registers with the above sequence (the readback of the HEAD registers
503 * also enforces ordering), otherwise the hw might lose the new ring
504 * register values. */
505 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
507 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
510 /* If the head is still not zero, the ring is dead */
511 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
512 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
513 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
514 DRM_ERROR("%s initialization failed "
515 "ctl %08x head %08x tail %08x start %08x\n",
518 I915_READ_HEAD(ring),
519 I915_READ_TAIL(ring),
520 I915_READ_START(ring));
525 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
526 i915_kernel_lost_context(ring->dev);
528 ring->head = I915_READ_HEAD(ring);
529 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
530 ring->space = ring_space(ring);
531 ring->last_retired_head = -1;
534 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
537 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
543 init_pipe_control(struct intel_ring_buffer *ring)
547 if (ring->scratch.obj)
550 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
551 if (ring->scratch.obj == NULL) {
552 DRM_ERROR("Failed to allocate seqno page\n");
557 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
561 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
565 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
566 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
567 if (ring->scratch.cpu_page == NULL) {
572 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
573 ring->name, ring->scratch.gtt_offset);
577 i915_gem_object_ggtt_unpin(ring->scratch.obj);
579 drm_gem_object_unreference(&ring->scratch.obj->base);
584 static int init_render_ring(struct intel_ring_buffer *ring)
586 struct drm_device *dev = ring->dev;
587 struct drm_i915_private *dev_priv = dev->dev_private;
588 int ret = init_ring_common(ring);
590 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
591 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
592 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
594 /* We need to disable the AsyncFlip performance optimisations in order
595 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
596 * programmed to '1' on all products.
598 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
600 if (INTEL_INFO(dev)->gen >= 6)
601 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
603 /* Required for the hardware to program scanline values for waiting */
604 if (INTEL_INFO(dev)->gen == 6)
606 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
609 I915_WRITE(GFX_MODE_GEN7,
610 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
611 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
613 if (INTEL_INFO(dev)->gen >= 5) {
614 ret = init_pipe_control(ring);
620 /* From the Sandybridge PRM, volume 1 part 3, page 24:
621 * "If this bit is set, STCunit will have LRA as replacement
622 * policy. [...] This bit must be reset. LRA replacement
623 * policy is not supported."
625 I915_WRITE(CACHE_MODE_0,
626 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
628 /* This is not explicitly set for GEN6, so read the register.
629 * see intel_ring_mi_set_context() for why we care.
630 * TODO: consider explicitly setting the bit for GEN5
632 ring->itlb_before_ctx_switch =
633 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
636 if (INTEL_INFO(dev)->gen >= 6)
637 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
640 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
645 static void render_ring_cleanup(struct intel_ring_buffer *ring)
647 struct drm_device *dev = ring->dev;
649 if (ring->scratch.obj == NULL)
652 if (INTEL_INFO(dev)->gen >= 5) {
653 kunmap(sg_page(ring->scratch.obj->pages->sgl));
654 i915_gem_object_ggtt_unpin(ring->scratch.obj);
657 drm_gem_object_unreference(&ring->scratch.obj->base);
658 ring->scratch.obj = NULL;
662 update_mboxes(struct intel_ring_buffer *ring,
665 /* NB: In order to be able to do semaphore MBOX updates for varying number
666 * of rings, it's easiest if we round up each individual update to a
667 * multiple of 2 (since ring updates must always be a multiple of 2)
668 * even though the actual update only requires 3 dwords.
670 #define MBOX_UPDATE_DWORDS 4
671 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
672 intel_ring_emit(ring, mmio_offset);
673 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
674 intel_ring_emit(ring, MI_NOOP);
678 * gen6_add_request - Update the semaphore mailbox registers
680 * @ring - ring that is adding a request
681 * @seqno - return seqno stuck into the ring
683 * Update the mailbox registers in the *other* rings with the current seqno.
684 * This acts like a signal in the canonical semaphore.
687 gen6_add_request(struct intel_ring_buffer *ring)
689 struct drm_device *dev = ring->dev;
690 struct drm_i915_private *dev_priv = dev->dev_private;
691 struct intel_ring_buffer *useless;
692 int i, ret, num_dwords = 4;
694 if (i915_semaphore_is_enabled(dev))
695 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
696 #undef MBOX_UPDATE_DWORDS
698 ret = intel_ring_begin(ring, num_dwords);
702 if (i915_semaphore_is_enabled(dev)) {
703 for_each_ring(useless, dev_priv, i) {
704 u32 mbox_reg = ring->signal_mbox[i];
705 if (mbox_reg != GEN6_NOSYNC)
706 update_mboxes(ring, mbox_reg);
710 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
711 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
712 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
713 intel_ring_emit(ring, MI_USER_INTERRUPT);
714 __intel_ring_advance(ring);
719 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
722 struct drm_i915_private *dev_priv = dev->dev_private;
723 return dev_priv->last_seqno < seqno;
727 * intel_ring_sync - sync the waiter to the signaller on seqno
729 * @waiter - ring that is waiting
730 * @signaller - ring which has, or will signal
731 * @seqno - seqno which the waiter will block on
734 gen6_ring_sync(struct intel_ring_buffer *waiter,
735 struct intel_ring_buffer *signaller,
739 u32 dw1 = MI_SEMAPHORE_MBOX |
740 MI_SEMAPHORE_COMPARE |
741 MI_SEMAPHORE_REGISTER;
743 /* Throughout all of the GEM code, seqno passed implies our current
744 * seqno is >= the last seqno executed. However for hardware the
745 * comparison is strictly greater than.
749 WARN_ON(signaller->semaphore_register[waiter->id] ==
750 MI_SEMAPHORE_SYNC_INVALID);
752 ret = intel_ring_begin(waiter, 4);
756 /* If seqno wrap happened, omit the wait with no-ops */
757 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
758 intel_ring_emit(waiter,
760 signaller->semaphore_register[waiter->id]);
761 intel_ring_emit(waiter, seqno);
762 intel_ring_emit(waiter, 0);
763 intel_ring_emit(waiter, MI_NOOP);
765 intel_ring_emit(waiter, MI_NOOP);
766 intel_ring_emit(waiter, MI_NOOP);
767 intel_ring_emit(waiter, MI_NOOP);
768 intel_ring_emit(waiter, MI_NOOP);
770 intel_ring_advance(waiter);
775 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
777 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
778 PIPE_CONTROL_DEPTH_STALL); \
779 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
780 intel_ring_emit(ring__, 0); \
781 intel_ring_emit(ring__, 0); \
785 pc_render_add_request(struct intel_ring_buffer *ring)
787 u32 scratch_addr = ring->scratch.gtt_offset + 128;
790 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
791 * incoherent with writes to memory, i.e. completely fubar,
792 * so we need to use PIPE_NOTIFY instead.
794 * However, we also need to workaround the qword write
795 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
796 * memory before requesting an interrupt.
798 ret = intel_ring_begin(ring, 32);
802 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
803 PIPE_CONTROL_WRITE_FLUSH |
804 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
805 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
806 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
807 intel_ring_emit(ring, 0);
808 PIPE_CONTROL_FLUSH(ring, scratch_addr);
809 scratch_addr += 128; /* write to separate cachelines */
810 PIPE_CONTROL_FLUSH(ring, scratch_addr);
812 PIPE_CONTROL_FLUSH(ring, scratch_addr);
814 PIPE_CONTROL_FLUSH(ring, scratch_addr);
816 PIPE_CONTROL_FLUSH(ring, scratch_addr);
818 PIPE_CONTROL_FLUSH(ring, scratch_addr);
820 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
821 PIPE_CONTROL_WRITE_FLUSH |
822 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
823 PIPE_CONTROL_NOTIFY);
824 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
825 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
826 intel_ring_emit(ring, 0);
827 __intel_ring_advance(ring);
833 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
835 /* Workaround to force correct ordering between irq and seqno writes on
836 * ivb (and maybe also on snb) by reading from a CS register (like
837 * ACTHD) before reading the status page. */
838 if (!lazy_coherency) {
839 struct drm_i915_private *dev_priv = ring->dev->dev_private;
840 POSTING_READ(RING_ACTHD(ring->mmio_base));
843 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
847 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
849 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
853 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
855 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
859 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
861 return ring->scratch.cpu_page[0];
865 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
867 ring->scratch.cpu_page[0] = seqno;
871 gen5_ring_get_irq(struct intel_ring_buffer *ring)
873 struct drm_device *dev = ring->dev;
874 struct drm_i915_private *dev_priv = dev->dev_private;
877 if (!dev->irq_enabled)
880 spin_lock_irqsave(&dev_priv->irq_lock, flags);
881 if (ring->irq_refcount++ == 0)
882 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
883 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
889 gen5_ring_put_irq(struct intel_ring_buffer *ring)
891 struct drm_device *dev = ring->dev;
892 struct drm_i915_private *dev_priv = dev->dev_private;
895 spin_lock_irqsave(&dev_priv->irq_lock, flags);
896 if (--ring->irq_refcount == 0)
897 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
898 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
902 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
904 struct drm_device *dev = ring->dev;
905 struct drm_i915_private *dev_priv = dev->dev_private;
908 if (!dev->irq_enabled)
911 spin_lock_irqsave(&dev_priv->irq_lock, flags);
912 if (ring->irq_refcount++ == 0) {
913 dev_priv->irq_mask &= ~ring->irq_enable_mask;
914 I915_WRITE(IMR, dev_priv->irq_mask);
917 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
923 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
925 struct drm_device *dev = ring->dev;
926 struct drm_i915_private *dev_priv = dev->dev_private;
929 spin_lock_irqsave(&dev_priv->irq_lock, flags);
930 if (--ring->irq_refcount == 0) {
931 dev_priv->irq_mask |= ring->irq_enable_mask;
932 I915_WRITE(IMR, dev_priv->irq_mask);
935 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
939 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
941 struct drm_device *dev = ring->dev;
942 struct drm_i915_private *dev_priv = dev->dev_private;
945 if (!dev->irq_enabled)
948 spin_lock_irqsave(&dev_priv->irq_lock, flags);
949 if (ring->irq_refcount++ == 0) {
950 dev_priv->irq_mask &= ~ring->irq_enable_mask;
951 I915_WRITE16(IMR, dev_priv->irq_mask);
954 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
960 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
962 struct drm_device *dev = ring->dev;
963 struct drm_i915_private *dev_priv = dev->dev_private;
966 spin_lock_irqsave(&dev_priv->irq_lock, flags);
967 if (--ring->irq_refcount == 0) {
968 dev_priv->irq_mask |= ring->irq_enable_mask;
969 I915_WRITE16(IMR, dev_priv->irq_mask);
972 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
975 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
977 struct drm_device *dev = ring->dev;
978 struct drm_i915_private *dev_priv = ring->dev->dev_private;
981 /* The ring status page addresses are no longer next to the rest of
982 * the ring registers as of gen7.
987 mmio = RENDER_HWS_PGA_GEN7;
990 mmio = BLT_HWS_PGA_GEN7;
993 mmio = BSD_HWS_PGA_GEN7;
996 mmio = VEBOX_HWS_PGA_GEN7;
999 } else if (IS_GEN6(ring->dev)) {
1000 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1002 /* XXX: gen8 returns to sanity */
1003 mmio = RING_HWS_PGA(ring->mmio_base);
1006 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1010 * Flush the TLB for this page
1012 * FIXME: These two bits have disappeared on gen8, so a question
1013 * arises: do we still need this and if so how should we go about
1014 * invalidating the TLB?
1016 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1017 u32 reg = RING_INSTPM(ring->mmio_base);
1019 /* ring should be idle before issuing a sync flush*/
1020 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1023 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1024 INSTPM_SYNC_FLUSH));
1025 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1027 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1033 bsd_ring_flush(struct intel_ring_buffer *ring,
1034 u32 invalidate_domains,
1039 ret = intel_ring_begin(ring, 2);
1043 intel_ring_emit(ring, MI_FLUSH);
1044 intel_ring_emit(ring, MI_NOOP);
1045 intel_ring_advance(ring);
1050 i9xx_add_request(struct intel_ring_buffer *ring)
1054 ret = intel_ring_begin(ring, 4);
1058 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1059 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1060 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1061 intel_ring_emit(ring, MI_USER_INTERRUPT);
1062 __intel_ring_advance(ring);
1068 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1070 struct drm_device *dev = ring->dev;
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 unsigned long flags;
1074 if (!dev->irq_enabled)
1077 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1078 if (ring->irq_refcount++ == 0) {
1079 if (HAS_L3_DPF(dev) && ring->id == RCS)
1080 I915_WRITE_IMR(ring,
1081 ~(ring->irq_enable_mask |
1082 GT_PARITY_ERROR(dev)));
1084 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1085 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1087 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1093 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1095 struct drm_device *dev = ring->dev;
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 unsigned long flags;
1099 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1100 if (--ring->irq_refcount == 0) {
1101 if (HAS_L3_DPF(dev) && ring->id == RCS)
1102 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1104 I915_WRITE_IMR(ring, ~0);
1105 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1107 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1111 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1113 struct drm_device *dev = ring->dev;
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 unsigned long flags;
1117 if (!dev->irq_enabled)
1120 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1121 if (ring->irq_refcount++ == 0) {
1122 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1123 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1125 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1131 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1133 struct drm_device *dev = ring->dev;
1134 struct drm_i915_private *dev_priv = dev->dev_private;
1135 unsigned long flags;
1137 if (!dev->irq_enabled)
1140 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1141 if (--ring->irq_refcount == 0) {
1142 I915_WRITE_IMR(ring, ~0);
1143 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1145 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1149 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1151 struct drm_device *dev = ring->dev;
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1153 unsigned long flags;
1155 if (!dev->irq_enabled)
1158 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1159 if (ring->irq_refcount++ == 0) {
1160 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1161 I915_WRITE_IMR(ring,
1162 ~(ring->irq_enable_mask |
1163 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1165 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1167 POSTING_READ(RING_IMR(ring->mmio_base));
1169 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1175 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1177 struct drm_device *dev = ring->dev;
1178 struct drm_i915_private *dev_priv = dev->dev_private;
1179 unsigned long flags;
1181 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1182 if (--ring->irq_refcount == 0) {
1183 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1184 I915_WRITE_IMR(ring,
1185 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1187 I915_WRITE_IMR(ring, ~0);
1189 POSTING_READ(RING_IMR(ring->mmio_base));
1191 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1195 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1196 u32 offset, u32 length,
1201 ret = intel_ring_begin(ring, 2);
1205 intel_ring_emit(ring,
1206 MI_BATCH_BUFFER_START |
1208 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1209 intel_ring_emit(ring, offset);
1210 intel_ring_advance(ring);
1215 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1216 #define I830_BATCH_LIMIT (256*1024)
1218 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1219 u32 offset, u32 len,
1224 if (flags & I915_DISPATCH_PINNED) {
1225 ret = intel_ring_begin(ring, 4);
1229 intel_ring_emit(ring, MI_BATCH_BUFFER);
1230 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1231 intel_ring_emit(ring, offset + len - 8);
1232 intel_ring_emit(ring, MI_NOOP);
1233 intel_ring_advance(ring);
1235 u32 cs_offset = ring->scratch.gtt_offset;
1237 if (len > I830_BATCH_LIMIT)
1240 ret = intel_ring_begin(ring, 9+3);
1243 /* Blit the batch (which has now all relocs applied) to the stable batch
1244 * scratch bo area (so that the CS never stumbles over its tlb
1245 * invalidation bug) ... */
1246 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1247 XY_SRC_COPY_BLT_WRITE_ALPHA |
1248 XY_SRC_COPY_BLT_WRITE_RGB);
1249 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1250 intel_ring_emit(ring, 0);
1251 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1252 intel_ring_emit(ring, cs_offset);
1253 intel_ring_emit(ring, 0);
1254 intel_ring_emit(ring, 4096);
1255 intel_ring_emit(ring, offset);
1256 intel_ring_emit(ring, MI_FLUSH);
1258 /* ... and execute it. */
1259 intel_ring_emit(ring, MI_BATCH_BUFFER);
1260 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1261 intel_ring_emit(ring, cs_offset + len - 8);
1262 intel_ring_advance(ring);
1269 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1270 u32 offset, u32 len,
1275 ret = intel_ring_begin(ring, 2);
1279 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1280 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1281 intel_ring_advance(ring);
1286 static void cleanup_status_page(struct intel_ring_buffer *ring)
1288 struct drm_i915_gem_object *obj;
1290 obj = ring->status_page.obj;
1294 kunmap(sg_page(obj->pages->sgl));
1295 i915_gem_object_ggtt_unpin(obj);
1296 drm_gem_object_unreference(&obj->base);
1297 ring->status_page.obj = NULL;
1300 static int init_status_page(struct intel_ring_buffer *ring)
1302 struct drm_device *dev = ring->dev;
1303 struct drm_i915_gem_object *obj;
1306 obj = i915_gem_alloc_object(dev, 4096);
1308 DRM_ERROR("Failed to allocate status page\n");
1313 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1317 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1321 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1322 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1323 if (ring->status_page.page_addr == NULL) {
1327 ring->status_page.obj = obj;
1328 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1330 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1331 ring->name, ring->status_page.gfx_addr);
1336 i915_gem_object_ggtt_unpin(obj);
1338 drm_gem_object_unreference(&obj->base);
1343 static int init_phys_status_page(struct intel_ring_buffer *ring)
1345 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1347 if (!dev_priv->status_page_dmah) {
1348 dev_priv->status_page_dmah =
1349 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1350 if (!dev_priv->status_page_dmah)
1354 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1355 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1360 static int intel_init_ring_buffer(struct drm_device *dev,
1361 struct intel_ring_buffer *ring)
1363 struct drm_i915_gem_object *obj;
1364 struct drm_i915_private *dev_priv = dev->dev_private;
1368 INIT_LIST_HEAD(&ring->active_list);
1369 INIT_LIST_HEAD(&ring->request_list);
1370 ring->size = 32 * PAGE_SIZE;
1371 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1373 init_waitqueue_head(&ring->irq_queue);
1375 if (I915_NEED_GFX_HWS(dev)) {
1376 ret = init_status_page(ring);
1380 BUG_ON(ring->id != RCS);
1381 ret = init_phys_status_page(ring);
1388 obj = i915_gem_object_create_stolen(dev, ring->size);
1390 obj = i915_gem_alloc_object(dev, ring->size);
1392 DRM_ERROR("Failed to allocate ringbuffer\n");
1399 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1403 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1407 ring->virtual_start =
1408 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1410 if (ring->virtual_start == NULL) {
1411 DRM_ERROR("Failed to map ringbuffer.\n");
1416 ret = ring->init(ring);
1420 /* Workaround an erratum on the i830 which causes a hang if
1421 * the TAIL pointer points to within the last 2 cachelines
1424 ring->effective_size = ring->size;
1425 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1426 ring->effective_size -= 128;
1428 i915_cmd_parser_init_ring(ring);
1433 iounmap(ring->virtual_start);
1435 i915_gem_object_ggtt_unpin(obj);
1437 drm_gem_object_unreference(&obj->base);
1440 cleanup_status_page(ring);
1444 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1446 struct drm_i915_private *dev_priv;
1449 if (ring->obj == NULL)
1452 /* Disable the ring buffer. The ring must be idle at this point */
1453 dev_priv = ring->dev->dev_private;
1454 ret = intel_ring_idle(ring);
1455 if (ret && !i915_reset_in_progress(&dev_priv->gpu_error))
1456 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1459 I915_WRITE_CTL(ring, 0);
1461 iounmap(ring->virtual_start);
1463 i915_gem_object_ggtt_unpin(ring->obj);
1464 drm_gem_object_unreference(&ring->obj->base);
1466 ring->preallocated_lazy_request = NULL;
1467 ring->outstanding_lazy_seqno = 0;
1470 ring->cleanup(ring);
1472 cleanup_status_page(ring);
1475 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1477 struct drm_i915_gem_request *request;
1478 u32 seqno = 0, tail;
1481 if (ring->last_retired_head != -1) {
1482 ring->head = ring->last_retired_head;
1483 ring->last_retired_head = -1;
1485 ring->space = ring_space(ring);
1486 if (ring->space >= n)
1490 list_for_each_entry(request, &ring->request_list, list) {
1493 if (request->tail == -1)
1496 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1498 space += ring->size;
1500 seqno = request->seqno;
1501 tail = request->tail;
1505 /* Consume this request in case we need more space than
1506 * is available and so need to prevent a race between
1507 * updating last_retired_head and direct reads of
1508 * I915_RING_HEAD. It also provides a nice sanity check.
1516 ret = i915_wait_seqno(ring, seqno);
1521 ring->space = ring_space(ring);
1522 if (WARN_ON(ring->space < n))
1528 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1530 struct drm_device *dev = ring->dev;
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1535 ret = intel_ring_wait_request(ring, n);
1539 /* force the tail write in case we have been skipping them */
1540 __intel_ring_advance(ring);
1542 trace_i915_ring_wait_begin(ring);
1543 /* With GEM the hangcheck timer should kick us out of the loop,
1544 * leaving it early runs the risk of corrupting GEM state (due
1545 * to running on almost untested codepaths). But on resume
1546 * timers don't work yet, so prevent a complete hang in that
1547 * case by choosing an insanely large timeout. */
1548 end = jiffies + 60 * HZ;
1551 ring->head = I915_READ_HEAD(ring);
1552 ring->space = ring_space(ring);
1553 if (ring->space >= n) {
1554 trace_i915_ring_wait_end(ring);
1558 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1559 dev->primary->master) {
1560 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1561 if (master_priv->sarea_priv)
1562 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1567 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1568 dev_priv->mm.interruptible);
1571 } while (!time_after(jiffies, end));
1572 trace_i915_ring_wait_end(ring);
1576 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1578 uint32_t __iomem *virt;
1579 int rem = ring->size - ring->tail;
1581 if (ring->space < rem) {
1582 int ret = ring_wait_for_space(ring, rem);
1587 virt = ring->virtual_start + ring->tail;
1590 iowrite32(MI_NOOP, virt++);
1593 ring->space = ring_space(ring);
1598 int intel_ring_idle(struct intel_ring_buffer *ring)
1603 /* We need to add any requests required to flush the objects and ring */
1604 if (ring->outstanding_lazy_seqno) {
1605 ret = i915_add_request(ring, NULL);
1610 /* Wait upon the last request to be completed */
1611 if (list_empty(&ring->request_list))
1614 seqno = list_entry(ring->request_list.prev,
1615 struct drm_i915_gem_request,
1618 return i915_wait_seqno(ring, seqno);
1622 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1624 if (ring->outstanding_lazy_seqno)
1627 if (ring->preallocated_lazy_request == NULL) {
1628 struct drm_i915_gem_request *request;
1630 request = kmalloc(sizeof(*request), GFP_KERNEL);
1631 if (request == NULL)
1634 ring->preallocated_lazy_request = request;
1637 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1640 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1645 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1646 ret = intel_wrap_ring_buffer(ring);
1651 if (unlikely(ring->space < bytes)) {
1652 ret = ring_wait_for_space(ring, bytes);
1660 int intel_ring_begin(struct intel_ring_buffer *ring,
1663 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1666 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1667 dev_priv->mm.interruptible);
1671 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1675 /* Preallocate the olr before touching the ring */
1676 ret = intel_ring_alloc_seqno(ring);
1680 ring->space -= num_dwords * sizeof(uint32_t);
1684 /* Align the ring tail to a cacheline boundary */
1685 int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1687 int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t);
1690 if (num_dwords == 0)
1693 ret = intel_ring_begin(ring, num_dwords);
1697 while (num_dwords--)
1698 intel_ring_emit(ring, MI_NOOP);
1700 intel_ring_advance(ring);
1705 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1707 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1709 BUG_ON(ring->outstanding_lazy_seqno);
1711 if (INTEL_INFO(ring->dev)->gen >= 6) {
1712 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1713 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1714 if (HAS_VEBOX(ring->dev))
1715 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1718 ring->set_seqno(ring, seqno);
1719 ring->hangcheck.seqno = seqno;
1722 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1725 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1727 /* Every tail move must follow the sequence below */
1729 /* Disable notification that the ring is IDLE. The GT
1730 * will then assume that it is busy and bring it out of rc6.
1732 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1733 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1735 /* Clear the context id. Here be magic! */
1736 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1738 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1739 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1740 GEN6_BSD_SLEEP_INDICATOR) == 0,
1742 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1744 /* Now that the ring is fully powered up, update the tail */
1745 I915_WRITE_TAIL(ring, value);
1746 POSTING_READ(RING_TAIL(ring->mmio_base));
1748 /* Let the ring send IDLE messages to the GT again,
1749 * and so let it sleep to conserve power when idle.
1751 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1752 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1755 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1756 u32 invalidate, u32 flush)
1761 ret = intel_ring_begin(ring, 4);
1766 if (INTEL_INFO(ring->dev)->gen >= 8)
1769 * Bspec vol 1c.5 - video engine command streamer:
1770 * "If ENABLED, all TLBs will be invalidated once the flush
1771 * operation is complete. This bit is only valid when the
1772 * Post-Sync Operation field is a value of 1h or 3h."
1774 if (invalidate & I915_GEM_GPU_DOMAINS)
1775 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1776 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1777 intel_ring_emit(ring, cmd);
1778 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1779 if (INTEL_INFO(ring->dev)->gen >= 8) {
1780 intel_ring_emit(ring, 0); /* upper addr */
1781 intel_ring_emit(ring, 0); /* value */
1783 intel_ring_emit(ring, 0);
1784 intel_ring_emit(ring, MI_NOOP);
1786 intel_ring_advance(ring);
1791 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1792 u32 offset, u32 len,
1795 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1796 bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1797 !(flags & I915_DISPATCH_SECURE);
1800 ret = intel_ring_begin(ring, 4);
1804 /* FIXME(BDW): Address space and security selectors. */
1805 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1806 intel_ring_emit(ring, offset);
1807 intel_ring_emit(ring, 0);
1808 intel_ring_emit(ring, MI_NOOP);
1809 intel_ring_advance(ring);
1815 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1816 u32 offset, u32 len,
1821 ret = intel_ring_begin(ring, 2);
1825 intel_ring_emit(ring,
1826 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1827 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1828 /* bit0-7 is the length on GEN6+ */
1829 intel_ring_emit(ring, offset);
1830 intel_ring_advance(ring);
1836 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1837 u32 offset, u32 len,
1842 ret = intel_ring_begin(ring, 2);
1846 intel_ring_emit(ring,
1847 MI_BATCH_BUFFER_START |
1848 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1849 /* bit0-7 is the length on GEN6+ */
1850 intel_ring_emit(ring, offset);
1851 intel_ring_advance(ring);
1856 /* Blitter support (SandyBridge+) */
1858 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1859 u32 invalidate, u32 flush)
1861 struct drm_device *dev = ring->dev;
1865 ret = intel_ring_begin(ring, 4);
1870 if (INTEL_INFO(ring->dev)->gen >= 8)
1873 * Bspec vol 1c.3 - blitter engine command streamer:
1874 * "If ENABLED, all TLBs will be invalidated once the flush
1875 * operation is complete. This bit is only valid when the
1876 * Post-Sync Operation field is a value of 1h or 3h."
1878 if (invalidate & I915_GEM_DOMAIN_RENDER)
1879 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1880 MI_FLUSH_DW_OP_STOREDW;
1881 intel_ring_emit(ring, cmd);
1882 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1883 if (INTEL_INFO(ring->dev)->gen >= 8) {
1884 intel_ring_emit(ring, 0); /* upper addr */
1885 intel_ring_emit(ring, 0); /* value */
1887 intel_ring_emit(ring, 0);
1888 intel_ring_emit(ring, MI_NOOP);
1890 intel_ring_advance(ring);
1892 if (IS_GEN7(dev) && !invalidate && flush)
1893 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1898 int intel_init_render_ring_buffer(struct drm_device *dev)
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1903 ring->name = "render ring";
1905 ring->mmio_base = RENDER_RING_BASE;
1907 if (INTEL_INFO(dev)->gen >= 6) {
1908 ring->add_request = gen6_add_request;
1909 ring->flush = gen7_render_ring_flush;
1910 if (INTEL_INFO(dev)->gen == 6)
1911 ring->flush = gen6_render_ring_flush;
1912 if (INTEL_INFO(dev)->gen >= 8) {
1913 ring->flush = gen8_render_ring_flush;
1914 ring->irq_get = gen8_ring_get_irq;
1915 ring->irq_put = gen8_ring_put_irq;
1917 ring->irq_get = gen6_ring_get_irq;
1918 ring->irq_put = gen6_ring_put_irq;
1920 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1921 ring->get_seqno = gen6_ring_get_seqno;
1922 ring->set_seqno = ring_set_seqno;
1923 ring->sync_to = gen6_ring_sync;
1924 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1925 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1926 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1927 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1928 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1929 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1930 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1931 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1932 } else if (IS_GEN5(dev)) {
1933 ring->add_request = pc_render_add_request;
1934 ring->flush = gen4_render_ring_flush;
1935 ring->get_seqno = pc_render_get_seqno;
1936 ring->set_seqno = pc_render_set_seqno;
1937 ring->irq_get = gen5_ring_get_irq;
1938 ring->irq_put = gen5_ring_put_irq;
1939 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1940 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1942 ring->add_request = i9xx_add_request;
1943 if (INTEL_INFO(dev)->gen < 4)
1944 ring->flush = gen2_render_ring_flush;
1946 ring->flush = gen4_render_ring_flush;
1947 ring->get_seqno = ring_get_seqno;
1948 ring->set_seqno = ring_set_seqno;
1950 ring->irq_get = i8xx_ring_get_irq;
1951 ring->irq_put = i8xx_ring_put_irq;
1953 ring->irq_get = i9xx_ring_get_irq;
1954 ring->irq_put = i9xx_ring_put_irq;
1956 ring->irq_enable_mask = I915_USER_INTERRUPT;
1958 ring->write_tail = ring_write_tail;
1959 if (IS_HASWELL(dev))
1960 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1961 else if (IS_GEN8(dev))
1962 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1963 else if (INTEL_INFO(dev)->gen >= 6)
1964 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1965 else if (INTEL_INFO(dev)->gen >= 4)
1966 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1967 else if (IS_I830(dev) || IS_845G(dev))
1968 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1970 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1971 ring->init = init_render_ring;
1972 ring->cleanup = render_ring_cleanup;
1974 /* Workaround batchbuffer to combat CS tlb bug. */
1975 if (HAS_BROKEN_CS_TLB(dev)) {
1976 struct drm_i915_gem_object *obj;
1979 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1981 DRM_ERROR("Failed to allocate batch bo\n");
1985 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
1987 drm_gem_object_unreference(&obj->base);
1988 DRM_ERROR("Failed to ping batch bo\n");
1992 ring->scratch.obj = obj;
1993 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
1996 return intel_init_ring_buffer(dev, ring);
1999 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2005 ring->name = "render ring";
2007 ring->mmio_base = RENDER_RING_BASE;
2009 if (INTEL_INFO(dev)->gen >= 6) {
2010 /* non-kms not supported on gen6+ */
2014 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2015 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2016 * the special gen5 functions. */
2017 ring->add_request = i9xx_add_request;
2018 if (INTEL_INFO(dev)->gen < 4)
2019 ring->flush = gen2_render_ring_flush;
2021 ring->flush = gen4_render_ring_flush;
2022 ring->get_seqno = ring_get_seqno;
2023 ring->set_seqno = ring_set_seqno;
2025 ring->irq_get = i8xx_ring_get_irq;
2026 ring->irq_put = i8xx_ring_put_irq;
2028 ring->irq_get = i9xx_ring_get_irq;
2029 ring->irq_put = i9xx_ring_put_irq;
2031 ring->irq_enable_mask = I915_USER_INTERRUPT;
2032 ring->write_tail = ring_write_tail;
2033 if (INTEL_INFO(dev)->gen >= 4)
2034 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2035 else if (IS_I830(dev) || IS_845G(dev))
2036 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2038 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2039 ring->init = init_render_ring;
2040 ring->cleanup = render_ring_cleanup;
2043 INIT_LIST_HEAD(&ring->active_list);
2044 INIT_LIST_HEAD(&ring->request_list);
2047 ring->effective_size = ring->size;
2048 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2049 ring->effective_size -= 128;
2051 ring->virtual_start = ioremap_wc(start, size);
2052 if (ring->virtual_start == NULL) {
2053 DRM_ERROR("can not ioremap virtual address for"
2058 if (!I915_NEED_GFX_HWS(dev)) {
2059 ret = init_phys_status_page(ring);
2067 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2072 ring->name = "bsd ring";
2075 ring->write_tail = ring_write_tail;
2076 if (INTEL_INFO(dev)->gen >= 6) {
2077 ring->mmio_base = GEN6_BSD_RING_BASE;
2078 /* gen6 bsd needs a special wa for tail updates */
2080 ring->write_tail = gen6_bsd_ring_write_tail;
2081 ring->flush = gen6_bsd_ring_flush;
2082 ring->add_request = gen6_add_request;
2083 ring->get_seqno = gen6_ring_get_seqno;
2084 ring->set_seqno = ring_set_seqno;
2085 if (INTEL_INFO(dev)->gen >= 8) {
2086 ring->irq_enable_mask =
2087 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2088 ring->irq_get = gen8_ring_get_irq;
2089 ring->irq_put = gen8_ring_put_irq;
2090 ring->dispatch_execbuffer =
2091 gen8_ring_dispatch_execbuffer;
2093 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2094 ring->irq_get = gen6_ring_get_irq;
2095 ring->irq_put = gen6_ring_put_irq;
2096 ring->dispatch_execbuffer =
2097 gen6_ring_dispatch_execbuffer;
2099 ring->sync_to = gen6_ring_sync;
2100 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
2101 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2102 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
2103 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
2104 ring->signal_mbox[RCS] = GEN6_RVSYNC;
2105 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2106 ring->signal_mbox[BCS] = GEN6_BVSYNC;
2107 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
2109 ring->mmio_base = BSD_RING_BASE;
2110 ring->flush = bsd_ring_flush;
2111 ring->add_request = i9xx_add_request;
2112 ring->get_seqno = ring_get_seqno;
2113 ring->set_seqno = ring_set_seqno;
2115 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2116 ring->irq_get = gen5_ring_get_irq;
2117 ring->irq_put = gen5_ring_put_irq;
2119 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2120 ring->irq_get = i9xx_ring_get_irq;
2121 ring->irq_put = i9xx_ring_put_irq;
2123 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2125 ring->init = init_ring_common;
2127 return intel_init_ring_buffer(dev, ring);
2130 int intel_init_blt_ring_buffer(struct drm_device *dev)
2132 struct drm_i915_private *dev_priv = dev->dev_private;
2133 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2135 ring->name = "blitter ring";
2138 ring->mmio_base = BLT_RING_BASE;
2139 ring->write_tail = ring_write_tail;
2140 ring->flush = gen6_ring_flush;
2141 ring->add_request = gen6_add_request;
2142 ring->get_seqno = gen6_ring_get_seqno;
2143 ring->set_seqno = ring_set_seqno;
2144 if (INTEL_INFO(dev)->gen >= 8) {
2145 ring->irq_enable_mask =
2146 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2147 ring->irq_get = gen8_ring_get_irq;
2148 ring->irq_put = gen8_ring_put_irq;
2149 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2151 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2152 ring->irq_get = gen6_ring_get_irq;
2153 ring->irq_put = gen6_ring_put_irq;
2154 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2156 ring->sync_to = gen6_ring_sync;
2157 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2158 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2159 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2160 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
2161 ring->signal_mbox[RCS] = GEN6_RBSYNC;
2162 ring->signal_mbox[VCS] = GEN6_VBSYNC;
2163 ring->signal_mbox[BCS] = GEN6_NOSYNC;
2164 ring->signal_mbox[VECS] = GEN6_VEBSYNC;
2165 ring->init = init_ring_common;
2167 return intel_init_ring_buffer(dev, ring);
2170 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2175 ring->name = "video enhancement ring";
2178 ring->mmio_base = VEBOX_RING_BASE;
2179 ring->write_tail = ring_write_tail;
2180 ring->flush = gen6_ring_flush;
2181 ring->add_request = gen6_add_request;
2182 ring->get_seqno = gen6_ring_get_seqno;
2183 ring->set_seqno = ring_set_seqno;
2185 if (INTEL_INFO(dev)->gen >= 8) {
2186 ring->irq_enable_mask =
2187 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2188 ring->irq_get = gen8_ring_get_irq;
2189 ring->irq_put = gen8_ring_put_irq;
2190 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2192 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2193 ring->irq_get = hsw_vebox_get_irq;
2194 ring->irq_put = hsw_vebox_put_irq;
2195 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2197 ring->sync_to = gen6_ring_sync;
2198 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2199 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2200 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2201 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2202 ring->signal_mbox[RCS] = GEN6_RVESYNC;
2203 ring->signal_mbox[VCS] = GEN6_VVESYNC;
2204 ring->signal_mbox[BCS] = GEN6_BVESYNC;
2205 ring->signal_mbox[VECS] = GEN6_NOSYNC;
2206 ring->init = init_ring_common;
2208 return intel_init_ring_buffer(dev, ring);
2212 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2216 if (!ring->gpu_caches_dirty)
2219 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2223 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2225 ring->gpu_caches_dirty = false;
2230 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2232 uint32_t flush_domains;
2236 if (ring->gpu_caches_dirty)
2237 flush_domains = I915_GEM_GPU_DOMAINS;
2239 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2243 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2245 ring->gpu_caches_dirty = false;