drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 bool
  38 intel_ring_initialized(struct intel_engine_cs *ring)
  39 {
  40         struct drm_device *dev = ring->dev;
  41
  42         if (!dev)
  43                 return false;
  44
  45         if (i915.enable_execlists) {
  46                 struct intel_context *dctx = ring->default_context;
  47                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  48
  49                 return ringbuf->obj;
  50         } else
  51                 return ring->buffer && ring->buffer->obj;
  52 }
  53
  54 int __intel_ring_space(int head, int tail, int size)
  55 {
  56         int space = head - tail;
  57         if (space <= 0)
  58                 space += size;
  59         return space - I915_RING_FREE_SPACE;
  60 }
  61
  62 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  63 {
  64         if (ringbuf->last_retired_head != -1) {
  65                 ringbuf->head = ringbuf->last_retired_head;
  66                 ringbuf->last_retired_head = -1;
  67         }
  68
  69         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  70                                             ringbuf->tail, ringbuf->size);
  71 }
  72
  73 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  74 {
  75         intel_ring_update_space(ringbuf);
  76         return ringbuf->space;
  77 }
  78
  79 bool intel_ring_stopped(struct intel_engine_cs *ring)
  80 {
  81         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  82         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  83 }
  84
  85 static void __intel_ring_advance(struct intel_engine_cs *ring)
  86 {
  87         struct intel_ringbuffer *ringbuf = ring->buffer;
  88         ringbuf->tail &= ringbuf->size - 1;
  89         if (intel_ring_stopped(ring))
  90                 return;
  91         ring->write_tail(ring, ringbuf->tail);
  92 }
  93
  94 static int
  95 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  96                        u32      invalidate_domains,
  97                        u32      flush_domains)
  98 {
  99         struct intel_engine_cs *ring = req->ring;
 100         u32 cmd;
 101         int ret;
 102
 103         cmd = MI_FLUSH;
 104         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 105                 cmd |= MI_NO_WRITE_FLUSH;
 106
 107         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 108                 cmd |= MI_READ_FLUSH;
 109
 110         ret = intel_ring_begin(req, 2);
 111         if (ret)
 112                 return ret;
 113
 114         intel_ring_emit(ring, cmd);
 115         intel_ring_emit(ring, MI_NOOP);
 116         intel_ring_advance(ring);
 117
 118         return 0;
 119 }
 120
 121 static int
 122 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 123                        u32      invalidate_domains,
 124                        u32      flush_domains)
 125 {
 126         struct intel_engine_cs *ring = req->ring;
 127         struct drm_device *dev = ring->dev;
 128         u32 cmd;
 129         int ret;
 130
 131         /*
 132          * read/write caches:
 133          *
 134          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 135          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 136          * also flushed at 2d versus 3d pipeline switches.
 137          *
 138          * read-only caches:
 139          *
 140          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 141          * MI_READ_FLUSH is set, and is always flushed on 965.
 142          *
 143          * I915_GEM_DOMAIN_COMMAND may not exist?
 144          *
 145          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 146          * invalidated when MI_EXE_FLUSH is set.
 147          *
 148          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 149          * invalidated with every MI_FLUSH.
 150          *
 151          * TLBs:
 152          *
 153          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 154          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 155          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 156          * are flushed at any MI_FLUSH.
 157          */
 158
 159         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 160         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 161                 cmd &= ~MI_NO_WRITE_FLUSH;
 162         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 163                 cmd |= MI_EXE_FLUSH;
 164
 165         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 166             (IS_G4X(dev) || IS_GEN5(dev)))
 167                 cmd |= MI_INVALIDATE_ISP;
 168
 169         ret = intel_ring_begin(req, 2);
 170         if (ret)
 171                 return ret;
 172
 173         intel_ring_emit(ring, cmd);
 174         intel_ring_emit(ring, MI_NOOP);
 175         intel_ring_advance(ring);
 176
 177         return 0;
 178 }
 179
 180 /**
 181  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 182  * implementing two workarounds on gen6.  From section 1.4.7.1
 183  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 184  *
 185  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 186  * produced by non-pipelined state commands), software needs to first
 187  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 188  * 0.
 189  *
 190  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 191  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 192  *
 193  * And the workaround for these two requires this workaround first:
 194  *
 195  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 196  * BEFORE the pipe-control with a post-sync op and no write-cache
 197  * flushes.
 198  *
 199  * And this last workaround is tricky because of the requirements on
 200  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 201  * volume 2 part 1:
 202  *
 203  *     "1 of the following must also be set:
 204  *      - Render Target Cache Flush Enable ([12] of DW1)
 205  *      - Depth Cache Flush Enable ([0] of DW1)
 206  *      - Stall at Pixel Scoreboard ([1] of DW1)
 207  *      - Depth Stall ([13] of DW1)
 208  *      - Post-Sync Operation ([13] of DW1)
 209  *      - Notify Enable ([8] of DW1)"
 210  *
 211  * The cache flushes require the workaround flush that triggered this
 212  * one, so we can't use it.  Depth stall would trigger the same.
 213  * Post-sync nonzero is what triggered this second workaround, so we
 214  * can't use that one either.  Notify enable is IRQs, which aren't
 215  * really our business.  That leaves only stall at scoreboard.
 216  */
 217 static int
 218 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 219 {
 220         struct intel_engine_cs *ring = req->ring;
 221         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 222         int ret;
 223
 224         ret = intel_ring_begin(req, 6);
 225         if (ret)
 226                 return ret;
 227
 228         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 229         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 230                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 231         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 232         intel_ring_emit(ring, 0); /* low dword */
 233         intel_ring_emit(ring, 0); /* high dword */
 234         intel_ring_emit(ring, MI_NOOP);
 235         intel_ring_advance(ring);
 236
 237         ret = intel_ring_begin(req, 6);
 238         if (ret)
 239                 return ret;
 240
 241         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 242         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 243         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 244         intel_ring_emit(ring, 0);
 245         intel_ring_emit(ring, 0);
 246         intel_ring_emit(ring, MI_NOOP);
 247         intel_ring_advance(ring);
 248
 249         return 0;
 250 }
 251
 252 static int
 253 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 254                        u32 invalidate_domains, u32 flush_domains)
 255 {
 256         struct intel_engine_cs *ring = req->ring;
 257         u32 flags = 0;
 258         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 259         int ret;
 260
 261         /* Force SNB workarounds for PIPE_CONTROL flushes */
 262         ret = intel_emit_post_sync_nonzero_flush(req);
 263         if (ret)
 264                 return ret;
 265
 266         /* Just flush everything.  Experiments have shown that reducing the
 267          * number of bits based on the write domains has little performance
 268          * impact.
 269          */
 270         if (flush_domains) {
 271                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 272                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 273                 /*
 274                  * Ensure that any following seqno writes only happen
 275                  * when the render cache is indeed flushed.
 276                  */
 277                 flags |= PIPE_CONTROL_CS_STALL;
 278         }
 279         if (invalidate_domains) {
 280                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 281                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 282                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 283                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 284                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 285                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 286                 /*
 287                  * TLB invalidate requires a post-sync write.
 288                  */
 289                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 290         }
 291
 292         ret = intel_ring_begin(req, 4);
 293         if (ret)
 294                 return ret;
 295
 296         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 297         intel_ring_emit(ring, flags);
 298         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 299         intel_ring_emit(ring, 0);
 300         intel_ring_advance(ring);
 301
 302         return 0;
 303 }
 304
 305 static int
 306 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 307 {
 308         struct intel_engine_cs *ring = req->ring;
 309         int ret;
 310
 311         ret = intel_ring_begin(req, 4);
 312         if (ret)
 313                 return ret;
 314
 315         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 316         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 317                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 318         intel_ring_emit(ring, 0);
 319         intel_ring_emit(ring, 0);
 320         intel_ring_advance(ring);
 321
 322         return 0;
 323 }
 324
 325 static int
 326 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 327                        u32 invalidate_domains, u32 flush_domains)
 328 {
 329         struct intel_engine_cs *ring = req->ring;
 330         u32 flags = 0;
 331         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 332         int ret;
 333
 334         /*
 335          * Ensure that any following seqno writes only happen when the render
 336          * cache is indeed flushed.
 337          *
 338          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 339          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 340          * don't try to be clever and just set it unconditionally.
 341          */
 342         flags |= PIPE_CONTROL_CS_STALL;
 343
 344         /* Just flush everything.  Experiments have shown that reducing the
 345          * number of bits based on the write domains has little performance
 346          * impact.
 347          */
 348         if (flush_domains) {
 349                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 350                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 351                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 352         }
 353         if (invalidate_domains) {
 354                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 355                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 356                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 357                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 358                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 359                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 360                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 361                 /*
 362                  * TLB invalidate requires a post-sync write.
 363                  */
 364                 flags |= PIPE_CONTROL_QW_WRITE;
 365                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 366
 367                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 368
 369                 /* Workaround: we must issue a pipe_control with CS-stall bit
 370                  * set before a pipe_control command that has the state cache
 371                  * invalidate bit set. */
 372                 gen7_render_ring_cs_stall_wa(req);
 373         }
 374
 375         ret = intel_ring_begin(req, 4);
 376         if (ret)
 377                 return ret;
 378
 379         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 380         intel_ring_emit(ring, flags);
 381         intel_ring_emit(ring, scratch_addr);
 382         intel_ring_emit(ring, 0);
 383         intel_ring_advance(ring);
 384
 385         return 0;
 386 }
 387
 388 static int
 389 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 390                        u32 flags, u32 scratch_addr)
 391 {
 392         struct intel_engine_cs *ring = req->ring;
 393         int ret;
 394
 395         ret = intel_ring_begin(req, 6);
 396         if (ret)
 397                 return ret;
 398
 399         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 400         intel_ring_emit(ring, flags);
 401         intel_ring_emit(ring, scratch_addr);
 402         intel_ring_emit(ring, 0);
 403         intel_ring_emit(ring, 0);
 404         intel_ring_emit(ring, 0);
 405         intel_ring_advance(ring);
 406
 407         return 0;
 408 }
 409
 410 static int
 411 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 412                        u32 invalidate_domains, u32 flush_domains)
 413 {
 414         u32 flags = 0;
 415         u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 416         int ret;
 417
 418         flags |= PIPE_CONTROL_CS_STALL;
 419
 420         if (flush_domains) {
 421                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 422                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 423                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 424         }
 425         if (invalidate_domains) {
 426                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 427                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 428                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 429                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 430                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 431                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 432                 flags |= PIPE_CONTROL_QW_WRITE;
 433                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 434
 435                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 436                 ret = gen8_emit_pipe_control(req,
 437                                              PIPE_CONTROL_CS_STALL |
 438                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 439                                              0);
 440                 if (ret)
 441                         return ret;
 442         }
 443
 444         return gen8_emit_pipe_control(req, flags, scratch_addr);
 445 }
 446
 447 static void ring_write_tail(struct intel_engine_cs *ring,
 448                             u32 value)
 449 {
 450         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 451         I915_WRITE_TAIL(ring, value);
 452 }
 453
 454 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 455 {
 456         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 457         u64 acthd;
 458
 459         if (INTEL_INFO(ring->dev)->gen >= 8)
 460                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 461                                          RING_ACTHD_UDW(ring->mmio_base));
 462         else if (INTEL_INFO(ring->dev)->gen >= 4)
 463                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 464         else
 465                 acthd = I915_READ(ACTHD);
 466
 467         return acthd;
 468 }
 469
 470 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 471 {
 472         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 473         u32 addr;
 474
 475         addr = dev_priv->status_page_dmah->busaddr;
 476         if (INTEL_INFO(ring->dev)->gen >= 4)
 477                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 478         I915_WRITE(HWS_PGA, addr);
 479 }
 480
 481 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 482 {
 483         struct drm_device *dev = ring->dev;
 484         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 485         i915_reg_t mmio;
 486
 487         /* The ring status page addresses are no longer next to the rest of
 488          * the ring registers as of gen7.
 489          */
 490         if (IS_GEN7(dev)) {
 491                 switch (ring->id) {
 492                 case RCS:
 493                         mmio = RENDER_HWS_PGA_GEN7;
 494                         break;
 495                 case BCS:
 496                         mmio = BLT_HWS_PGA_GEN7;
 497                         break;
 498                 /*
 499                  * VCS2 actually doesn't exist on Gen7. Only shut up
 500                  * gcc switch check warning
 501                  */
 502                 case VCS2:
 503                 case VCS:
 504                         mmio = BSD_HWS_PGA_GEN7;
 505                         break;
 506                 case VECS:
 507                         mmio = VEBOX_HWS_PGA_GEN7;
 508                         break;
 509                 }
 510         } else if (IS_GEN6(ring->dev)) {
 511                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 512         } else {
 513                 /* XXX: gen8 returns to sanity */
 514                 mmio = RING_HWS_PGA(ring->mmio_base);
 515         }
 516
 517         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 518         POSTING_READ(mmio);
 519
 520         /*
 521          * Flush the TLB for this page
 522          *
 523          * FIXME: These two bits have disappeared on gen8, so a question
 524          * arises: do we still need this and if so how should we go about
 525          * invalidating the TLB?
 526          */
 527         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 528                 i915_reg_t reg = RING_INSTPM(ring->mmio_base);
 529
 530                 /* ring should be idle before issuing a sync flush*/
 531                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 532
 533                 I915_WRITE(reg,
 534                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 535                                               INSTPM_SYNC_FLUSH));
 536                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 537                              1000))
 538                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 539                                   ring->name);
 540         }
 541 }
 542
 543 static bool stop_ring(struct intel_engine_cs *ring)
 544 {
 545         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 546
 547         if (!IS_GEN2(ring->dev)) {
 548                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 549                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 550                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 551                         /* Sometimes we observe that the idle flag is not
 552                          * set even though the ring is empty. So double
 553                          * check before giving up.
 554                          */
 555                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 556                                 return false;
 557                 }
 558         }
 559
 560         I915_WRITE_CTL(ring, 0);
 561         I915_WRITE_HEAD(ring, 0);
 562         ring->write_tail(ring, 0);
 563
 564         if (!IS_GEN2(ring->dev)) {
 565                 (void)I915_READ_CTL(ring);
 566                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 567         }
 568
 569         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 570 }
 571
 572 static int init_ring_common(struct intel_engine_cs *ring)
 573 {
 574         struct drm_device *dev = ring->dev;
 575         struct drm_i915_private *dev_priv = dev->dev_private;
 576         struct intel_ringbuffer *ringbuf = ring->buffer;
 577         struct drm_i915_gem_object *obj = ringbuf->obj;
 578         int ret = 0;
 579
 580         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 581
 582         if (!stop_ring(ring)) {
 583                 /* G45 ring initialization often fails to reset head to zero */
 584                 DRM_DEBUG_KMS("%s head not reset to zero "
 585                               "ctl %08x head %08x tail %08x start %08x\n",
 586                               ring->name,
 587                               I915_READ_CTL(ring),
 588                               I915_READ_HEAD(ring),
 589                               I915_READ_TAIL(ring),
 590                               I915_READ_START(ring));
 591
 592                 if (!stop_ring(ring)) {
 593                         DRM_ERROR("failed to set %s head to zero "
 594                                   "ctl %08x head %08x tail %08x start %08x\n",
 595                                   ring->name,
 596                                   I915_READ_CTL(ring),
 597                                   I915_READ_HEAD(ring),
 598                                   I915_READ_TAIL(ring),
 599                                   I915_READ_START(ring));
 600                         ret = -EIO;
 601                         goto out;
 602                 }
 603         }
 604
 605         if (I915_NEED_GFX_HWS(dev))
 606                 intel_ring_setup_status_page(ring);
 607         else
 608                 ring_setup_phys_status_page(ring);
 609
 610         /* Enforce ordering by reading HEAD register back */
 611         I915_READ_HEAD(ring);
 612
 613         /* Initialize the ring. This must happen _after_ we've cleared the ring
 614          * registers with the above sequence (the readback of the HEAD registers
 615          * also enforces ordering), otherwise the hw might lose the new ring
 616          * register values. */
 617         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 618
 619         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 620         if (I915_READ_HEAD(ring))
 621                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 622                           ring->name, I915_READ_HEAD(ring));
 623         I915_WRITE_HEAD(ring, 0);
 624         (void)I915_READ_HEAD(ring);
 625
 626         I915_WRITE_CTL(ring,
 627                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 628                         | RING_VALID);
 629
 630         /* If the head is still not zero, the ring is dead */
 631         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 632                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 633                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 634                 DRM_ERROR("%s initialization failed "
 635                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 636                           ring->name,
 637                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 638                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 639                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 640                 ret = -EIO;
 641                 goto out;
 642         }
 643
 644         ringbuf->last_retired_head = -1;
 645         ringbuf->head = I915_READ_HEAD(ring);
 646         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 647         intel_ring_update_space(ringbuf);
 648
 649         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 650
 651 out:
 652         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 653
 654         return ret;
 655 }
 656
 657 void
 658 intel_fini_pipe_control(struct intel_engine_cs *ring)
 659 {
 660         struct drm_device *dev = ring->dev;
 661
 662         if (ring->scratch.obj == NULL)
 663                 return;
 664
 665         if (INTEL_INFO(dev)->gen >= 5) {
 666                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 667                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 668         }
 669
 670         drm_gem_object_unreference(&ring->scratch.obj->base);
 671         ring->scratch.obj = NULL;
 672 }
 673
 674 int
 675 intel_init_pipe_control(struct intel_engine_cs *ring)
 676 {
 677         int ret;
 678
 679         WARN_ON(ring->scratch.obj);
 680
 681         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 682         if (ring->scratch.obj == NULL) {
 683                 DRM_ERROR("Failed to allocate seqno page\n");
 684                 ret = -ENOMEM;
 685                 goto err;
 686         }
 687
 688         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 689         if (ret)
 690                 goto err_unref;
 691
 692         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 693         if (ret)
 694                 goto err_unref;
 695
 696         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 697         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 698         if (ring->scratch.cpu_page == NULL) {
 699                 ret = -ENOMEM;
 700                 goto err_unpin;
 701         }
 702
 703         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 704                          ring->name, ring->scratch.gtt_offset);
 705         return 0;
 706
 707 err_unpin:
 708         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 709 err_unref:
 710         drm_gem_object_unreference(&ring->scratch.obj->base);
 711 err:
 712         return ret;
 713 }
 714
 715 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 716 {
 717         int ret, i;
 718         struct intel_engine_cs *ring = req->ring;
 719         struct drm_device *dev = ring->dev;
 720         struct drm_i915_private *dev_priv = dev->dev_private;
 721         struct i915_workarounds *w = &dev_priv->workarounds;
 722
 723         if (w->count == 0)
 724                 return 0;
 725
 726         ring->gpu_caches_dirty = true;
 727         ret = intel_ring_flush_all_caches(req);
 728         if (ret)
 729                 return ret;
 730
 731         ret = intel_ring_begin(req, (w->count * 2 + 2));
 732         if (ret)
 733                 return ret;
 734
 735         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 736         for (i = 0; i < w->count; i++) {
 737                 intel_ring_emit_reg(ring, w->reg[i].addr);
 738                 intel_ring_emit(ring, w->reg[i].value);
 739         }
 740         intel_ring_emit(ring, MI_NOOP);
 741
 742         intel_ring_advance(ring);
 743
 744         ring->gpu_caches_dirty = true;
 745         ret = intel_ring_flush_all_caches(req);
 746         if (ret)
 747                 return ret;
 748
 749         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 750
 751         return 0;
 752 }
 753
 754 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 755 {
 756         int ret;
 757
 758         ret = intel_ring_workarounds_emit(req);
 759         if (ret != 0)
 760                 return ret;
 761
 762         ret = i915_gem_render_state_init(req);
 763         if (ret)
 764                 DRM_ERROR("init render state: %d\n", ret);
 765
 766         return ret;
 767 }
 768
 769 static int wa_add(struct drm_i915_private *dev_priv,
 770                   i915_reg_t addr,
 771                   const u32 mask, const u32 val)
 772 {
 773         const u32 idx = dev_priv->workarounds.count;
 774
 775         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 776                 return -ENOSPC;
 777
 778         dev_priv->workarounds.reg[idx].addr = addr;
 779         dev_priv->workarounds.reg[idx].value = val;
 780         dev_priv->workarounds.reg[idx].mask = mask;
 781
 782         dev_priv->workarounds.count++;
 783
 784         return 0;
 785 }
 786
 787 #define WA_REG(addr, mask, val) do { \
 788                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 789                 if (r) \
 790                         return r; \
 791         } while (0)
 792
 793 #define WA_SET_BIT_MASKED(addr, mask) \
 794         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 795
 796 #define WA_CLR_BIT_MASKED(addr, mask) \
 797         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 798
 799 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 800         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 801
 802 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 803 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 804
 805 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 806
 807 static int gen8_init_workarounds(struct intel_engine_cs *ring)
 808 {
 809         struct drm_device *dev = ring->dev;
 810         struct drm_i915_private *dev_priv = dev->dev_private;
 811
 812         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 813
 814         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 815         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 816
 817         /* WaDisablePartialInstShootdown:bdw,chv */
 818         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 819                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 820
 821         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 822          * workaround for for a possible hang in the unlikely event a TLB
 823          * invalidation occurs during a PSD flush.
 824          */
 825         /* WaForceEnableNonCoherent:bdw,chv */
 826         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 827         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 828                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 829                           HDC_FORCE_NON_COHERENT);
 830
 831         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 832          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 833          *  polygons in the same 8x4 pixel/sample area to be processed without
 834          *  stalling waiting for the earlier ones to write to Hierarchical Z
 835          *  buffer."
 836          *
 837          * This optimization is off by default for BDW and CHV; turn it on.
 838          */
 839         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 840
 841         /* Wa4x4STCOptimizationDisable:bdw,chv */
 842         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 843
 844         /*
 845          * BSpec recommends 8x4 when MSAA is used,
 846          * however in practice 16x4 seems fastest.
 847          *
 848          * Note that PS/WM thread counts depend on the WIZ hashing
 849          * disable bit, which we don't touch here, but it's good
 850          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 851          */
 852         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 853                             GEN6_WIZ_HASHING_MASK,
 854                             GEN6_WIZ_HASHING_16x4);
 855
 856         return 0;
 857 }
 858
 859 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 860 {
 861         int ret;
 862         struct drm_device *dev = ring->dev;
 863         struct drm_i915_private *dev_priv = dev->dev_private;
 864
 865         ret = gen8_init_workarounds(ring);
 866         if (ret)
 867                 return ret;
 868
 869         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 870         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 871
 872         /* WaDisableDopClockGating:bdw */
 873         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 874                           DOP_CLOCK_GATING_DISABLE);
 875
 876         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 877                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 878
 879         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 880                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 881                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 882                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 883                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 884
 885         return 0;
 886 }
 887
 888 static int chv_init_workarounds(struct intel_engine_cs *ring)
 889 {
 890         int ret;
 891         struct drm_device *dev = ring->dev;
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893
 894         ret = gen8_init_workarounds(ring);
 895         if (ret)
 896                 return ret;
 897
 898         /* WaDisableThreadStallDopClockGating:chv */
 899         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 900
 901         /* Improve HiZ throughput on CHV. */
 902         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 903
 904         return 0;
 905 }
 906
 907 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 908 {
 909         struct drm_device *dev = ring->dev;
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911         uint32_t tmp;
 912
 913         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 914         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 915                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 916
 917         /* WaDisableKillLogic:bxt,skl */
 918         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 919                    ECOCHK_DIS_TLB);
 920
 921         /* WaDisablePartialInstShootdown:skl,bxt */
 922         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 923                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 924
 925         /* Syncing dependencies between camera and graphics:skl,bxt */
 926         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 927                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 928
 929         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 930         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 931             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 932                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 933                                   GEN9_DG_MIRROR_FIX_ENABLE);
 934
 935         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 936         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 937             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 938                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 939                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 940                 /*
 941                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 942                  * but we do that in per ctx batchbuffer as there is an issue
 943                  * with this register not getting restored on ctx restore
 944                  */
 945         }
 946
 947         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 948         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
 949                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 950                                   GEN9_ENABLE_YV12_BUGFIX);
 951
 952         /* Wa4x4STCOptimizationDisable:skl,bxt */
 953         /* WaDisablePartialResolveInVc:skl,bxt */
 954         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 955                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 956
 957         /* WaCcsTlbPrefetchDisable:skl,bxt */
 958         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 959                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 960
 961         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 962         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 963             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 964                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 965                                   PIXEL_MASK_CAMMING_DISABLE);
 966
 967         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 968         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 969         if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
 970             IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
 971                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 972         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 973
 974         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 975         if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 976                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 977                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 978
 979         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 980         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 981
 982         return 0;
 983 }
 984
 985 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 986 {
 987         struct drm_device *dev = ring->dev;
 988         struct drm_i915_private *dev_priv = dev->dev_private;
 989         u8 vals[3] = { 0, 0, 0 };
 990         unsigned int i;
 991
 992         for (i = 0; i < 3; i++) {
 993                 u8 ss;
 994
 995                 /*
 996                  * Only consider slices where one, and only one, subslice has 7
 997                  * EUs
 998                  */
 999                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1000                         continue;
1001
1002                 /*
1003                  * subslice_7eu[i] != 0 (because of the check above) and
1004                  * ss_max == 4 (maximum number of subslices possible per slice)
1005                  *
1006                  * ->    0 <= ss <= 3;
1007                  */
1008                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1009                 vals[i] = 3 - ss;
1010         }
1011
1012         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1013                 return 0;
1014
1015         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1016         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1017                             GEN9_IZ_HASHING_MASK(2) |
1018                             GEN9_IZ_HASHING_MASK(1) |
1019                             GEN9_IZ_HASHING_MASK(0),
1020                             GEN9_IZ_HASHING(2, vals[2]) |
1021                             GEN9_IZ_HASHING(1, vals[1]) |
1022                             GEN9_IZ_HASHING(0, vals[0]));
1023
1024         return 0;
1025 }
1026
1027 static int skl_init_workarounds(struct intel_engine_cs *ring)
1028 {
1029         int ret;
1030         struct drm_device *dev = ring->dev;
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032
1033         ret = gen9_init_workarounds(ring);
1034         if (ret)
1035                 return ret;
1036
1037         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1038                 /* WaDisableHDCInvalidation:skl */
1039                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1040                            BDW_DISABLE_HDC_INVALIDATION);
1041
1042                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1043                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1044                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1045         }
1046
1047         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1048          * involving this register should also be added to WA batch as required.
1049          */
1050         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1051                 /* WaDisableLSQCROPERFforOCL:skl */
1052                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1053                            GEN8_LQSC_RO_PERF_DIS);
1054
1055         /* WaEnableGapsTsvCreditFix:skl */
1056         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1057                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1058                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1059         }
1060
1061         /* WaDisablePowerCompilerClockGating:skl */
1062         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1063                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1064                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1065
1066         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1067                 /*
1068                  *Use Force Non-Coherent whenever executing a 3D context. This
1069                  * is a workaround for a possible hang in the unlikely event
1070                  * a TLB invalidation occurs during a PSD flush.
1071                  */
1072                 /* WaForceEnableNonCoherent:skl */
1073                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1074                                   HDC_FORCE_NON_COHERENT);
1075         }
1076
1077         /* WaBarrierPerformanceFixDisable:skl */
1078         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1079                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1080                                   HDC_FENCE_DEST_SLM_DISABLE |
1081                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1082
1083         /* WaDisableSbeCacheDispatchPortSharing:skl */
1084         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1085                 WA_SET_BIT_MASKED(
1086                         GEN7_HALF_SLICE_CHICKEN1,
1087                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1088
1089         return skl_tune_iz_hashing(ring);
1090 }
1091
1092 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1093 {
1094         int ret;
1095         struct drm_device *dev = ring->dev;
1096         struct drm_i915_private *dev_priv = dev->dev_private;
1097
1098         ret = gen9_init_workarounds(ring);
1099         if (ret)
1100                 return ret;
1101
1102         /* WaStoreMultiplePTEenable:bxt */
1103         /* This is a requirement according to Hardware specification */
1104         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1105                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1106
1107         /* WaSetClckGatingDisableMedia:bxt */
1108         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1109                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1110                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1111         }
1112
1113         /* WaDisableThreadStallDopClockGating:bxt */
1114         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1115                           STALL_DOP_GATING_DISABLE);
1116
1117         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1118         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1119                 WA_SET_BIT_MASKED(
1120                         GEN7_HALF_SLICE_CHICKEN1,
1121                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1122         }
1123
1124         return 0;
1125 }
1126
1127 int init_workarounds_ring(struct intel_engine_cs *ring)
1128 {
1129         struct drm_device *dev = ring->dev;
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         WARN_ON(ring->id != RCS);
1133
1134         dev_priv->workarounds.count = 0;
1135
1136         if (IS_BROADWELL(dev))
1137                 return bdw_init_workarounds(ring);
1138
1139         if (IS_CHERRYVIEW(dev))
1140                 return chv_init_workarounds(ring);
1141
1142         if (IS_SKYLAKE(dev))
1143                 return skl_init_workarounds(ring);
1144
1145         if (IS_BROXTON(dev))
1146                 return bxt_init_workarounds(ring);
1147
1148         return 0;
1149 }
1150
1151 static int init_render_ring(struct intel_engine_cs *ring)
1152 {
1153         struct drm_device *dev = ring->dev;
1154         struct drm_i915_private *dev_priv = dev->dev_private;
1155         int ret = init_ring_common(ring);
1156         if (ret)
1157                 return ret;
1158
1159         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1160         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1161                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1162
1163         /* We need to disable the AsyncFlip performance optimisations in order
1164          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1165          * programmed to '1' on all products.
1166          *
1167          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1168          */
1169         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1170                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1171
1172         /* Required for the hardware to program scanline values for waiting */
1173         /* WaEnableFlushTlbInvalidationMode:snb */
1174         if (INTEL_INFO(dev)->gen == 6)
1175                 I915_WRITE(GFX_MODE,
1176                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1177
1178         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1179         if (IS_GEN7(dev))
1180                 I915_WRITE(GFX_MODE_GEN7,
1181                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1182                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1183
1184         if (IS_GEN6(dev)) {
1185                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1186                  * "If this bit is set, STCunit will have LRA as replacement
1187                  *  policy. [...] This bit must be reset.  LRA replacement
1188                  *  policy is not supported."
1189                  */
1190                 I915_WRITE(CACHE_MODE_0,
1191                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1192         }
1193
1194         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1195                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1196
1197         if (HAS_L3_DPF(dev))
1198                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1199
1200         return init_workarounds_ring(ring);
1201 }
1202
1203 static void render_ring_cleanup(struct intel_engine_cs *ring)
1204 {
1205         struct drm_device *dev = ring->dev;
1206         struct drm_i915_private *dev_priv = dev->dev_private;
1207
1208         if (dev_priv->semaphore_obj) {
1209                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1210                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1211                 dev_priv->semaphore_obj = NULL;
1212         }
1213
1214         intel_fini_pipe_control(ring);
1215 }
1216
1217 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1218                            unsigned int num_dwords)
1219 {
1220 #define MBOX_UPDATE_DWORDS 8
1221         struct intel_engine_cs *signaller = signaller_req->ring;
1222         struct drm_device *dev = signaller->dev;
1223         struct drm_i915_private *dev_priv = dev->dev_private;
1224         struct intel_engine_cs *waiter;
1225         int i, ret, num_rings;
1226
1227         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1228         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1229 #undef MBOX_UPDATE_DWORDS
1230
1231         ret = intel_ring_begin(signaller_req, num_dwords);
1232         if (ret)
1233                 return ret;
1234
1235         for_each_ring(waiter, dev_priv, i) {
1236                 u32 seqno;
1237                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1238                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1239                         continue;
1240
1241                 seqno = i915_gem_request_get_seqno(signaller_req);
1242                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1243                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1244                                            PIPE_CONTROL_QW_WRITE |
1245                                            PIPE_CONTROL_FLUSH_ENABLE);
1246                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1247                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1248                 intel_ring_emit(signaller, seqno);
1249                 intel_ring_emit(signaller, 0);
1250                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1251                                            MI_SEMAPHORE_TARGET(waiter->id));
1252                 intel_ring_emit(signaller, 0);
1253         }
1254
1255         return 0;
1256 }
1257
1258 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1259                            unsigned int num_dwords)
1260 {
1261 #define MBOX_UPDATE_DWORDS 6
1262         struct intel_engine_cs *signaller = signaller_req->ring;
1263         struct drm_device *dev = signaller->dev;
1264         struct drm_i915_private *dev_priv = dev->dev_private;
1265         struct intel_engine_cs *waiter;
1266         int i, ret, num_rings;
1267
1268         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1269         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1270 #undef MBOX_UPDATE_DWORDS
1271
1272         ret = intel_ring_begin(signaller_req, num_dwords);
1273         if (ret)
1274                 return ret;
1275
1276         for_each_ring(waiter, dev_priv, i) {
1277                 u32 seqno;
1278                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1279                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1280                         continue;
1281
1282                 seqno = i915_gem_request_get_seqno(signaller_req);
1283                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1284                                            MI_FLUSH_DW_OP_STOREDW);
1285                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1286                                            MI_FLUSH_DW_USE_GTT);
1287                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1288                 intel_ring_emit(signaller, seqno);
1289                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1290                                            MI_SEMAPHORE_TARGET(waiter->id));
1291                 intel_ring_emit(signaller, 0);
1292         }
1293
1294         return 0;
1295 }
1296
1297 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1298                        unsigned int num_dwords)
1299 {
1300         struct intel_engine_cs *signaller = signaller_req->ring;
1301         struct drm_device *dev = signaller->dev;
1302         struct drm_i915_private *dev_priv = dev->dev_private;
1303         struct intel_engine_cs *useless;
1304         int i, ret, num_rings;
1305
1306 #define MBOX_UPDATE_DWORDS 3
1307         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1308         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1309 #undef MBOX_UPDATE_DWORDS
1310
1311         ret = intel_ring_begin(signaller_req, num_dwords);
1312         if (ret)
1313                 return ret;
1314
1315         for_each_ring(useless, dev_priv, i) {
1316                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
1317
1318                 if (i915_mmio_reg_valid(mbox_reg)) {
1319                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1320
1321                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1322                         intel_ring_emit_reg(signaller, mbox_reg);
1323                         intel_ring_emit(signaller, seqno);
1324                 }
1325         }
1326
1327         /* If num_dwords was rounded, make sure the tail pointer is correct */
1328         if (num_rings % 2 == 0)
1329                 intel_ring_emit(signaller, MI_NOOP);
1330
1331         return 0;
1332 }
1333
1334 /**
1335  * gen6_add_request - Update the semaphore mailbox registers
1336  *
1337  * @request - request to write to the ring
1338  *
1339  * Update the mailbox registers in the *other* rings with the current seqno.
1340  * This acts like a signal in the canonical semaphore.
1341  */
1342 static int
1343 gen6_add_request(struct drm_i915_gem_request *req)
1344 {
1345         struct intel_engine_cs *ring = req->ring;
1346         int ret;
1347
1348         if (ring->semaphore.signal)
1349                 ret = ring->semaphore.signal(req, 4);
1350         else
1351                 ret = intel_ring_begin(req, 4);
1352
1353         if (ret)
1354                 return ret;
1355
1356         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1357         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1358         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1359         intel_ring_emit(ring, MI_USER_INTERRUPT);
1360         __intel_ring_advance(ring);
1361
1362         return 0;
1363 }
1364
1365 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1366                                               u32 seqno)
1367 {
1368         struct drm_i915_private *dev_priv = dev->dev_private;
1369         return dev_priv->last_seqno < seqno;
1370 }
1371
1372 /**
1373  * intel_ring_sync - sync the waiter to the signaller on seqno
1374  *
1375  * @waiter - ring that is waiting
1376  * @signaller - ring which has, or will signal
1377  * @seqno - seqno which the waiter will block on
1378  */
1379
1380 static int
1381 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1382                struct intel_engine_cs *signaller,
1383                u32 seqno)
1384 {
1385         struct intel_engine_cs *waiter = waiter_req->ring;
1386         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1387         int ret;
1388
1389         ret = intel_ring_begin(waiter_req, 4);
1390         if (ret)
1391                 return ret;
1392
1393         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1394                                 MI_SEMAPHORE_GLOBAL_GTT |
1395                                 MI_SEMAPHORE_POLL |
1396                                 MI_SEMAPHORE_SAD_GTE_SDD);
1397         intel_ring_emit(waiter, seqno);
1398         intel_ring_emit(waiter,
1399                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1400         intel_ring_emit(waiter,
1401                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1402         intel_ring_advance(waiter);
1403         return 0;
1404 }
1405
1406 static int
1407 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1408                struct intel_engine_cs *signaller,
1409                u32 seqno)
1410 {
1411         struct intel_engine_cs *waiter = waiter_req->ring;
1412         u32 dw1 = MI_SEMAPHORE_MBOX |
1413                   MI_SEMAPHORE_COMPARE |
1414                   MI_SEMAPHORE_REGISTER;
1415         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1416         int ret;
1417
1418         /* Throughout all of the GEM code, seqno passed implies our current
1419          * seqno is >= the last seqno executed. However for hardware the
1420          * comparison is strictly greater than.
1421          */
1422         seqno -= 1;
1423
1424         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1425
1426         ret = intel_ring_begin(waiter_req, 4);
1427         if (ret)
1428                 return ret;
1429
1430         /* If seqno wrap happened, omit the wait with no-ops */
1431         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1432                 intel_ring_emit(waiter, dw1 | wait_mbox);
1433                 intel_ring_emit(waiter, seqno);
1434                 intel_ring_emit(waiter, 0);
1435                 intel_ring_emit(waiter, MI_NOOP);
1436         } else {
1437                 intel_ring_emit(waiter, MI_NOOP);
1438                 intel_ring_emit(waiter, MI_NOOP);
1439                 intel_ring_emit(waiter, MI_NOOP);
1440                 intel_ring_emit(waiter, MI_NOOP);
1441         }
1442         intel_ring_advance(waiter);
1443
1444         return 0;
1445 }
1446
1447 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1448 do {                                                                    \
1449         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1450                  PIPE_CONTROL_DEPTH_STALL);                             \
1451         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1452         intel_ring_emit(ring__, 0);                                                     \
1453         intel_ring_emit(ring__, 0);                                                     \
1454 } while (0)
1455
1456 static int
1457 pc_render_add_request(struct drm_i915_gem_request *req)
1458 {
1459         struct intel_engine_cs *ring = req->ring;
1460         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1461         int ret;
1462
1463         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1464          * incoherent with writes to memory, i.e. completely fubar,
1465          * so we need to use PIPE_NOTIFY instead.
1466          *
1467          * However, we also need to workaround the qword write
1468          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1469          * memory before requesting an interrupt.
1470          */
1471         ret = intel_ring_begin(req, 32);
1472         if (ret)
1473                 return ret;
1474
1475         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1476                         PIPE_CONTROL_WRITE_FLUSH |
1477                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1478         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1479         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1480         intel_ring_emit(ring, 0);
1481         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1482         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1483         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1484         scratch_addr += 2 * CACHELINE_BYTES;
1485         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1486         scratch_addr += 2 * CACHELINE_BYTES;
1487         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1488         scratch_addr += 2 * CACHELINE_BYTES;
1489         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1490         scratch_addr += 2 * CACHELINE_BYTES;
1491         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1492
1493         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1494                         PIPE_CONTROL_WRITE_FLUSH |
1495                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1496                         PIPE_CONTROL_NOTIFY);
1497         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1498         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1499         intel_ring_emit(ring, 0);
1500         __intel_ring_advance(ring);
1501
1502         return 0;
1503 }
1504
1505 static u32
1506 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1507 {
1508         /* Workaround to force correct ordering between irq and seqno writes on
1509          * ivb (and maybe also on snb) by reading from a CS register (like
1510          * ACTHD) before reading the status page. */
1511         if (!lazy_coherency) {
1512                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1513                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1514         }
1515
1516         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1517 }
1518
1519 static u32
1520 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1521 {
1522         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1523 }
1524
1525 static void
1526 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1527 {
1528         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1529 }
1530
1531 static u32
1532 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1533 {
1534         return ring->scratch.cpu_page[0];
1535 }
1536
1537 static void
1538 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1539 {
1540         ring->scratch.cpu_page[0] = seqno;
1541 }
1542
1543 static bool
1544 gen5_ring_get_irq(struct intel_engine_cs *ring)
1545 {
1546         struct drm_device *dev = ring->dev;
1547         struct drm_i915_private *dev_priv = dev->dev_private;
1548         unsigned long flags;
1549
1550         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1551                 return false;
1552
1553         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1554         if (ring->irq_refcount++ == 0)
1555                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1556         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1557
1558         return true;
1559 }
1560
1561 static void
1562 gen5_ring_put_irq(struct intel_engine_cs *ring)
1563 {
1564         struct drm_device *dev = ring->dev;
1565         struct drm_i915_private *dev_priv = dev->dev_private;
1566         unsigned long flags;
1567
1568         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1569         if (--ring->irq_refcount == 0)
1570                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1571         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1572 }
1573
1574 static bool
1575 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1576 {
1577         struct drm_device *dev = ring->dev;
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579         unsigned long flags;
1580
1581         if (!intel_irqs_enabled(dev_priv))
1582                 return false;
1583
1584         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1585         if (ring->irq_refcount++ == 0) {
1586                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1587                 I915_WRITE(IMR, dev_priv->irq_mask);
1588                 POSTING_READ(IMR);
1589         }
1590         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1591
1592         return true;
1593 }
1594
1595 static void
1596 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1597 {
1598         struct drm_device *dev = ring->dev;
1599         struct drm_i915_private *dev_priv = dev->dev_private;
1600         unsigned long flags;
1601
1602         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1603         if (--ring->irq_refcount == 0) {
1604                 dev_priv->irq_mask |= ring->irq_enable_mask;
1605                 I915_WRITE(IMR, dev_priv->irq_mask);
1606                 POSTING_READ(IMR);
1607         }
1608         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1609 }
1610
1611 static bool
1612 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1613 {
1614         struct drm_device *dev = ring->dev;
1615         struct drm_i915_private *dev_priv = dev->dev_private;
1616         unsigned long flags;
1617
1618         if (!intel_irqs_enabled(dev_priv))
1619                 return false;
1620
1621         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1622         if (ring->irq_refcount++ == 0) {
1623                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1624                 I915_WRITE16(IMR, dev_priv->irq_mask);
1625                 POSTING_READ16(IMR);
1626         }
1627         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1628
1629         return true;
1630 }
1631
1632 static void
1633 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1634 {
1635         struct drm_device *dev = ring->dev;
1636         struct drm_i915_private *dev_priv = dev->dev_private;
1637         unsigned long flags;
1638
1639         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1640         if (--ring->irq_refcount == 0) {
1641                 dev_priv->irq_mask |= ring->irq_enable_mask;
1642                 I915_WRITE16(IMR, dev_priv->irq_mask);
1643                 POSTING_READ16(IMR);
1644         }
1645         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1646 }
1647
1648 static int
1649 bsd_ring_flush(struct drm_i915_gem_request *req,
1650                u32     invalidate_domains,
1651                u32     flush_domains)
1652 {
1653         struct intel_engine_cs *ring = req->ring;
1654         int ret;
1655
1656         ret = intel_ring_begin(req, 2);
1657         if (ret)
1658                 return ret;
1659
1660         intel_ring_emit(ring, MI_FLUSH);
1661         intel_ring_emit(ring, MI_NOOP);
1662         intel_ring_advance(ring);
1663         return 0;
1664 }
1665
1666 static int
1667 i9xx_add_request(struct drm_i915_gem_request *req)
1668 {
1669         struct intel_engine_cs *ring = req->ring;
1670         int ret;
1671
1672         ret = intel_ring_begin(req, 4);
1673         if (ret)
1674                 return ret;
1675
1676         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1677         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1678         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1679         intel_ring_emit(ring, MI_USER_INTERRUPT);
1680         __intel_ring_advance(ring);
1681
1682         return 0;
1683 }
1684
1685 static bool
1686 gen6_ring_get_irq(struct intel_engine_cs *ring)
1687 {
1688         struct drm_device *dev = ring->dev;
1689         struct drm_i915_private *dev_priv = dev->dev_private;
1690         unsigned long flags;
1691
1692         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1693                 return false;
1694
1695         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1696         if (ring->irq_refcount++ == 0) {
1697                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1698                         I915_WRITE_IMR(ring,
1699                                        ~(ring->irq_enable_mask |
1700                                          GT_PARITY_ERROR(dev)));
1701                 else
1702                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1703                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1704         }
1705         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1706
1707         return true;
1708 }
1709
1710 static void
1711 gen6_ring_put_irq(struct intel_engine_cs *ring)
1712 {
1713         struct drm_device *dev = ring->dev;
1714         struct drm_i915_private *dev_priv = dev->dev_private;
1715         unsigned long flags;
1716
1717         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1718         if (--ring->irq_refcount == 0) {
1719                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1720                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1721                 else
1722                         I915_WRITE_IMR(ring, ~0);
1723                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1724         }
1725         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1726 }
1727
1728 static bool
1729 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1730 {
1731         struct drm_device *dev = ring->dev;
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         unsigned long flags;
1734
1735         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1736                 return false;
1737
1738         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1739         if (ring->irq_refcount++ == 0) {
1740                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1741                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1742         }
1743         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1744
1745         return true;
1746 }
1747
1748 static void
1749 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1750 {
1751         struct drm_device *dev = ring->dev;
1752         struct drm_i915_private *dev_priv = dev->dev_private;
1753         unsigned long flags;
1754
1755         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1756         if (--ring->irq_refcount == 0) {
1757                 I915_WRITE_IMR(ring, ~0);
1758                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1759         }
1760         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1761 }
1762
1763 static bool
1764 gen8_ring_get_irq(struct intel_engine_cs *ring)
1765 {
1766         struct drm_device *dev = ring->dev;
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         unsigned long flags;
1769
1770         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1771                 return false;
1772
1773         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1774         if (ring->irq_refcount++ == 0) {
1775                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1776                         I915_WRITE_IMR(ring,
1777                                        ~(ring->irq_enable_mask |
1778                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1779                 } else {
1780                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1781                 }
1782                 POSTING_READ(RING_IMR(ring->mmio_base));
1783         }
1784         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1785
1786         return true;
1787 }
1788
1789 static void
1790 gen8_ring_put_irq(struct intel_engine_cs *ring)
1791 {
1792         struct drm_device *dev = ring->dev;
1793         struct drm_i915_private *dev_priv = dev->dev_private;
1794         unsigned long flags;
1795
1796         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1797         if (--ring->irq_refcount == 0) {
1798                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1799                         I915_WRITE_IMR(ring,
1800                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1801                 } else {
1802                         I915_WRITE_IMR(ring, ~0);
1803                 }
1804                 POSTING_READ(RING_IMR(ring->mmio_base));
1805         }
1806         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1807 }
1808
1809 static int
1810 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1811                          u64 offset, u32 length,
1812                          unsigned dispatch_flags)
1813 {
1814         struct intel_engine_cs *ring = req->ring;
1815         int ret;
1816
1817         ret = intel_ring_begin(req, 2);
1818         if (ret)
1819                 return ret;
1820
1821         intel_ring_emit(ring,
1822                         MI_BATCH_BUFFER_START |
1823                         MI_BATCH_GTT |
1824                         (dispatch_flags & I915_DISPATCH_SECURE ?
1825                          0 : MI_BATCH_NON_SECURE_I965));
1826         intel_ring_emit(ring, offset);
1827         intel_ring_advance(ring);
1828
1829         return 0;
1830 }
1831
1832 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1833 #define I830_BATCH_LIMIT (256*1024)
1834 #define I830_TLB_ENTRIES (2)
1835 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1836 static int
1837 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1838                          u64 offset, u32 len,
1839                          unsigned dispatch_flags)
1840 {
1841         struct intel_engine_cs *ring = req->ring;
1842         u32 cs_offset = ring->scratch.gtt_offset;
1843         int ret;
1844
1845         ret = intel_ring_begin(req, 6);
1846         if (ret)
1847                 return ret;
1848
1849         /* Evict the invalid PTE TLBs */
1850         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1851         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1852         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1853         intel_ring_emit(ring, cs_offset);
1854         intel_ring_emit(ring, 0xdeadbeef);
1855         intel_ring_emit(ring, MI_NOOP);
1856         intel_ring_advance(ring);
1857
1858         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1859                 if (len > I830_BATCH_LIMIT)
1860                         return -ENOSPC;
1861
1862                 ret = intel_ring_begin(req, 6 + 2);
1863                 if (ret)
1864                         return ret;
1865
1866                 /* Blit the batch (which has now all relocs applied) to the
1867                  * stable batch scratch bo area (so that the CS never
1868                  * stumbles over its tlb invalidation bug) ...
1869                  */
1870                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1871                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1872                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1873                 intel_ring_emit(ring, cs_offset);
1874                 intel_ring_emit(ring, 4096);
1875                 intel_ring_emit(ring, offset);
1876
1877                 intel_ring_emit(ring, MI_FLUSH);
1878                 intel_ring_emit(ring, MI_NOOP);
1879                 intel_ring_advance(ring);
1880
1881                 /* ... and execute it. */
1882                 offset = cs_offset;
1883         }
1884
1885         ret = intel_ring_begin(req, 4);
1886         if (ret)
1887                 return ret;
1888
1889         intel_ring_emit(ring, MI_BATCH_BUFFER);
1890         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1891                                         0 : MI_BATCH_NON_SECURE));
1892         intel_ring_emit(ring, offset + len - 8);
1893         intel_ring_emit(ring, MI_NOOP);
1894         intel_ring_advance(ring);
1895
1896         return 0;
1897 }
1898
1899 static int
1900 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1901                          u64 offset, u32 len,
1902                          unsigned dispatch_flags)
1903 {
1904         struct intel_engine_cs *ring = req->ring;
1905         int ret;
1906
1907         ret = intel_ring_begin(req, 2);
1908         if (ret)
1909                 return ret;
1910
1911         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1912         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1913                                         0 : MI_BATCH_NON_SECURE));
1914         intel_ring_advance(ring);
1915
1916         return 0;
1917 }
1918
1919 static void cleanup_status_page(struct intel_engine_cs *ring)
1920 {
1921         struct drm_i915_gem_object *obj;
1922
1923         obj = ring->status_page.obj;
1924         if (obj == NULL)
1925                 return;
1926
1927         kunmap(sg_page(obj->pages->sgl));
1928         i915_gem_object_ggtt_unpin(obj);
1929         drm_gem_object_unreference(&obj->base);
1930         ring->status_page.obj = NULL;
1931 }
1932
1933 static int init_status_page(struct intel_engine_cs *ring)
1934 {
1935         struct drm_i915_gem_object *obj;
1936
1937         if ((obj = ring->status_page.obj) == NULL) {
1938                 unsigned flags;
1939                 int ret;
1940
1941                 obj = i915_gem_alloc_object(ring->dev, 4096);
1942                 if (obj == NULL) {
1943                         DRM_ERROR("Failed to allocate status page\n");
1944                         return -ENOMEM;
1945                 }
1946
1947                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1948                 if (ret)
1949                         goto err_unref;
1950
1951                 flags = 0;
1952                 if (!HAS_LLC(ring->dev))
1953                         /* On g33, we cannot place HWS above 256MiB, so
1954                          * restrict its pinning to the low mappable arena.
1955                          * Though this restriction is not documented for
1956                          * gen4, gen5, or byt, they also behave similarly
1957                          * and hang if the HWS is placed at the top of the
1958                          * GTT. To generalise, it appears that all !llc
1959                          * platforms have issues with us placing the HWS
1960                          * above the mappable region (even though we never
1961                          * actualy map it).
1962                          */
1963                         flags |= PIN_MAPPABLE;
1964                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1965                 if (ret) {
1966 err_unref:
1967                         drm_gem_object_unreference(&obj->base);
1968                         return ret;
1969                 }
1970
1971                 ring->status_page.obj = obj;
1972         }
1973
1974         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1975         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1976         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1977
1978         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1979                         ring->name, ring->status_page.gfx_addr);
1980
1981         return 0;
1982 }
1983
1984 static int init_phys_status_page(struct intel_engine_cs *ring)
1985 {
1986         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1987
1988         if (!dev_priv->status_page_dmah) {
1989                 dev_priv->status_page_dmah =
1990                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1991                 if (!dev_priv->status_page_dmah)
1992                         return -ENOMEM;
1993         }
1994
1995         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1996         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1997
1998         return 0;
1999 }
2000
2001 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2002 {
2003         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2004                 vunmap(ringbuf->virtual_start);
2005         else
2006                 iounmap(ringbuf->virtual_start);
2007         ringbuf->virtual_start = NULL;
2008         i915_gem_object_ggtt_unpin(ringbuf->obj);
2009 }
2010
2011 static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2012 {
2013         struct sg_page_iter sg_iter;
2014         struct page **pages;
2015         void *addr;
2016         int i;
2017
2018         pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2019         if (pages == NULL)
2020                 return NULL;
2021
2022         i = 0;
2023         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2024                 pages[i++] = sg_page_iter_page(&sg_iter);
2025
2026         addr = vmap(pages, i, 0, PAGE_KERNEL);
2027         drm_free_large(pages);
2028
2029         return addr;
2030 }
2031
2032 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2033                                      struct intel_ringbuffer *ringbuf)
2034 {
2035         struct drm_i915_private *dev_priv = to_i915(dev);
2036         struct drm_i915_gem_object *obj = ringbuf->obj;
2037         int ret;
2038
2039         if (HAS_LLC(dev_priv) && !obj->stolen) {
2040                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2041                 if (ret)
2042                         return ret;
2043
2044                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2045                 if (ret) {
2046                         i915_gem_object_ggtt_unpin(obj);
2047                         return ret;
2048                 }
2049
2050                 ringbuf->virtual_start = vmap_obj(obj);
2051                 if (ringbuf->virtual_start == NULL) {
2052                         i915_gem_object_ggtt_unpin(obj);
2053                         return -ENOMEM;
2054                 }
2055         } else {
2056                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2057                 if (ret)
2058                         return ret;
2059
2060                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2061                 if (ret) {
2062                         i915_gem_object_ggtt_unpin(obj);
2063                         return ret;
2064                 }
2065
2066                 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2067                                                     i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2068                 if (ringbuf->virtual_start == NULL) {
2069                         i915_gem_object_ggtt_unpin(obj);
2070                         return -EINVAL;
2071                 }
2072         }
2073
2074         return 0;
2075 }
2076
2077 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2078 {
2079         drm_gem_object_unreference(&ringbuf->obj->base);
2080         ringbuf->obj = NULL;
2081 }
2082
2083 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2084                                       struct intel_ringbuffer *ringbuf)
2085 {
2086         struct drm_i915_gem_object *obj;
2087
2088         obj = NULL;
2089         if (!HAS_LLC(dev))
2090                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2091         if (obj == NULL)
2092                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2093         if (obj == NULL)
2094                 return -ENOMEM;
2095
2096         /* mark ring buffers as read-only from GPU side by default */
2097         obj->gt_ro = 1;
2098
2099         ringbuf->obj = obj;
2100
2101         return 0;
2102 }
2103
2104 struct intel_ringbuffer *
2105 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2106 {
2107         struct intel_ringbuffer *ring;
2108         int ret;
2109
2110         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2111         if (ring == NULL) {
2112                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2113                                  engine->name);
2114                 return ERR_PTR(-ENOMEM);
2115         }
2116
2117         ring->ring = engine;
2118         list_add(&ring->link, &engine->buffers);
2119
2120         ring->size = size;
2121         /* Workaround an erratum on the i830 which causes a hang if
2122          * the TAIL pointer points to within the last 2 cachelines
2123          * of the buffer.
2124          */
2125         ring->effective_size = size;
2126         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2127                 ring->effective_size -= 2 * CACHELINE_BYTES;
2128
2129         ring->last_retired_head = -1;
2130         intel_ring_update_space(ring);
2131
2132         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2133         if (ret) {
2134                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2135                                  engine->name, ret);
2136                 list_del(&ring->link);
2137                 kfree(ring);
2138                 return ERR_PTR(ret);
2139         }
2140
2141         return ring;
2142 }
2143
2144 void
2145 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2146 {
2147         intel_destroy_ringbuffer_obj(ring);
2148         list_del(&ring->link);
2149         kfree(ring);
2150 }
2151
2152 static int intel_init_ring_buffer(struct drm_device *dev,
2153                                   struct intel_engine_cs *ring)
2154 {
2155         struct intel_ringbuffer *ringbuf;
2156         int ret;
2157
2158         WARN_ON(ring->buffer);
2159
2160         ring->dev = dev;
2161         INIT_LIST_HEAD(&ring->active_list);
2162         INIT_LIST_HEAD(&ring->request_list);
2163         INIT_LIST_HEAD(&ring->execlist_queue);
2164         INIT_LIST_HEAD(&ring->buffers);
2165         i915_gem_batch_pool_init(dev, &ring->batch_pool);
2166         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2167
2168         init_waitqueue_head(&ring->irq_queue);
2169
2170         ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2171         if (IS_ERR(ringbuf))
2172                 return PTR_ERR(ringbuf);
2173         ring->buffer = ringbuf;
2174
2175         if (I915_NEED_GFX_HWS(dev)) {
2176                 ret = init_status_page(ring);
2177                 if (ret)
2178                         goto error;
2179         } else {
2180                 BUG_ON(ring->id != RCS);
2181                 ret = init_phys_status_page(ring);
2182                 if (ret)
2183                         goto error;
2184         }
2185
2186         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2187         if (ret) {
2188                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2189                                 ring->name, ret);
2190                 intel_destroy_ringbuffer_obj(ringbuf);
2191                 goto error;
2192         }
2193
2194         ret = i915_cmd_parser_init_ring(ring);
2195         if (ret)
2196                 goto error;
2197
2198         return 0;
2199
2200 error:
2201         intel_ringbuffer_free(ringbuf);
2202         ring->buffer = NULL;
2203         return ret;
2204 }
2205
2206 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2207 {
2208         struct drm_i915_private *dev_priv;
2209
2210         if (!intel_ring_initialized(ring))
2211                 return;
2212
2213         dev_priv = to_i915(ring->dev);
2214
2215         intel_stop_ring_buffer(ring);
2216         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2217
2218         intel_unpin_ringbuffer_obj(ring->buffer);
2219         intel_ringbuffer_free(ring->buffer);
2220         ring->buffer = NULL;
2221
2222         if (ring->cleanup)
2223                 ring->cleanup(ring);
2224
2225         cleanup_status_page(ring);
2226
2227         i915_cmd_parser_fini_ring(ring);
2228         i915_gem_batch_pool_fini(&ring->batch_pool);
2229 }
2230
2231 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2232 {
2233         struct intel_ringbuffer *ringbuf = ring->buffer;
2234         struct drm_i915_gem_request *request;
2235         unsigned space;
2236         int ret;
2237
2238         if (intel_ring_space(ringbuf) >= n)
2239                 return 0;
2240
2241         /* The whole point of reserving space is to not wait! */
2242         WARN_ON(ringbuf->reserved_in_use);
2243
2244         list_for_each_entry(request, &ring->request_list, list) {
2245                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2246                                            ringbuf->size);
2247                 if (space >= n)
2248                         break;
2249         }
2250
2251         if (WARN_ON(&request->list == &ring->request_list))
2252                 return -ENOSPC;
2253
2254         ret = i915_wait_request(request);
2255         if (ret)
2256                 return ret;
2257
2258         ringbuf->space = space;
2259         return 0;
2260 }
2261
2262 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2263 {
2264         uint32_t __iomem *virt;
2265         int rem = ringbuf->size - ringbuf->tail;
2266
2267         virt = ringbuf->virtual_start + ringbuf->tail;
2268         rem /= 4;
2269         while (rem--)
2270                 iowrite32(MI_NOOP, virt++);
2271
2272         ringbuf->tail = 0;
2273         intel_ring_update_space(ringbuf);
2274 }
2275
2276 int intel_ring_idle(struct intel_engine_cs *ring)
2277 {
2278         struct drm_i915_gem_request *req;
2279
2280         /* Wait upon the last request to be completed */
2281         if (list_empty(&ring->request_list))
2282                 return 0;
2283
2284         req = list_entry(ring->request_list.prev,
2285                         struct drm_i915_gem_request,
2286                         list);
2287
2288         /* Make sure we do not trigger any retires */
2289         return __i915_wait_request(req,
2290                                    atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2291                                    to_i915(ring->dev)->mm.interruptible,
2292                                    NULL, NULL);
2293 }
2294
2295 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2296 {
2297         request->ringbuf = request->ring->buffer;
2298         return 0;
2299 }
2300
2301 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2302 {
2303         /*
2304          * The first call merely notes the reserve request and is common for
2305          * all back ends. The subsequent localised _begin() call actually
2306          * ensures that the reservation is available. Without the begin, if
2307          * the request creator immediately submitted the request without
2308          * adding any commands to it then there might not actually be
2309          * sufficient room for the submission commands.
2310          */
2311         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2312
2313         return intel_ring_begin(request, 0);
2314 }
2315
2316 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2317 {
2318         WARN_ON(ringbuf->reserved_size);
2319         WARN_ON(ringbuf->reserved_in_use);
2320
2321         ringbuf->reserved_size = size;
2322 }
2323
2324 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2325 {
2326         WARN_ON(ringbuf->reserved_in_use);
2327
2328         ringbuf->reserved_size   = 0;
2329         ringbuf->reserved_in_use = false;
2330 }
2331
2332 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2333 {
2334         WARN_ON(ringbuf->reserved_in_use);
2335
2336         ringbuf->reserved_in_use = true;
2337         ringbuf->reserved_tail   = ringbuf->tail;
2338 }
2339
2340 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2341 {
2342         WARN_ON(!ringbuf->reserved_in_use);
2343         if (ringbuf->tail > ringbuf->reserved_tail) {
2344                 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2345                      "request reserved size too small: %d vs %d!\n",
2346                      ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2347         } else {
2348                 /*
2349                  * The ring was wrapped while the reserved space was in use.
2350                  * That means that some unknown amount of the ring tail was
2351                  * no-op filled and skipped. Thus simply adding the ring size
2352                  * to the tail and doing the above space check will not work.
2353                  * Rather than attempt to track how much tail was skipped,
2354                  * it is much simpler to say that also skipping the sanity
2355                  * check every once in a while is not a big issue.
2356                  */
2357         }
2358
2359         ringbuf->reserved_size   = 0;
2360         ringbuf->reserved_in_use = false;
2361 }
2362
2363 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2364 {
2365         struct intel_ringbuffer *ringbuf = ring->buffer;
2366         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2367         int remain_actual = ringbuf->size - ringbuf->tail;
2368         int ret, total_bytes, wait_bytes = 0;
2369         bool need_wrap = false;
2370
2371         if (ringbuf->reserved_in_use)
2372                 total_bytes = bytes;
2373         else
2374                 total_bytes = bytes + ringbuf->reserved_size;
2375
2376         if (unlikely(bytes > remain_usable)) {
2377                 /*
2378                  * Not enough space for the basic request. So need to flush
2379                  * out the remainder and then wait for base + reserved.
2380                  */
2381                 wait_bytes = remain_actual + total_bytes;
2382                 need_wrap = true;
2383         } else {
2384                 if (unlikely(total_bytes > remain_usable)) {
2385                         /*
2386                          * The base request will fit but the reserved space
2387                          * falls off the end. So only need to to wait for the
2388                          * reserved size after flushing out the remainder.
2389                          */
2390                         wait_bytes = remain_actual + ringbuf->reserved_size;
2391                         need_wrap = true;
2392                 } else if (total_bytes > ringbuf->space) {
2393                         /* No wrapping required, just waiting. */
2394                         wait_bytes = total_bytes;
2395                 }
2396         }
2397
2398         if (wait_bytes) {
2399                 ret = ring_wait_for_space(ring, wait_bytes);
2400                 if (unlikely(ret))
2401                         return ret;
2402
2403                 if (need_wrap)
2404                         __wrap_ring_buffer(ringbuf);
2405         }
2406
2407         return 0;
2408 }
2409
2410 int intel_ring_begin(struct drm_i915_gem_request *req,
2411                      int num_dwords)
2412 {
2413         struct intel_engine_cs *ring;
2414         struct drm_i915_private *dev_priv;
2415         int ret;
2416
2417         WARN_ON(req == NULL);
2418         ring = req->ring;
2419         dev_priv = ring->dev->dev_private;
2420
2421         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2422                                    dev_priv->mm.interruptible);
2423         if (ret)
2424                 return ret;
2425
2426         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2427         if (ret)
2428                 return ret;
2429
2430         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2431         return 0;
2432 }
2433
2434 /* Align the ring tail to a cacheline boundary */
2435 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2436 {
2437         struct intel_engine_cs *ring = req->ring;
2438         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2439         int ret;
2440
2441         if (num_dwords == 0)
2442                 return 0;
2443
2444         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2445         ret = intel_ring_begin(req, num_dwords);
2446         if (ret)
2447                 return ret;
2448
2449         while (num_dwords--)
2450                 intel_ring_emit(ring, MI_NOOP);
2451
2452         intel_ring_advance(ring);
2453
2454         return 0;
2455 }
2456
2457 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2458 {
2459         struct drm_device *dev = ring->dev;
2460         struct drm_i915_private *dev_priv = dev->dev_private;
2461
2462         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2463                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2464                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2465                 if (HAS_VEBOX(dev))
2466                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2467         }
2468
2469         ring->set_seqno(ring, seqno);
2470         ring->hangcheck.seqno = seqno;
2471 }
2472
2473 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2474                                      u32 value)
2475 {
2476         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2477
2478        /* Every tail move must follow the sequence below */
2479
2480         /* Disable notification that the ring is IDLE. The GT
2481          * will then assume that it is busy and bring it out of rc6.
2482          */
2483         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2484                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2485
2486         /* Clear the context id. Here be magic! */
2487         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2488
2489         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2490         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2491                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2492                      50))
2493                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2494
2495         /* Now that the ring is fully powered up, update the tail */
2496         I915_WRITE_TAIL(ring, value);
2497         POSTING_READ(RING_TAIL(ring->mmio_base));
2498
2499         /* Let the ring send IDLE messages to the GT again,
2500          * and so let it sleep to conserve power when idle.
2501          */
2502         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2503                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2504 }
2505
2506 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2507                                u32 invalidate, u32 flush)
2508 {
2509         struct intel_engine_cs *ring = req->ring;
2510         uint32_t cmd;
2511         int ret;
2512
2513         ret = intel_ring_begin(req, 4);
2514         if (ret)
2515                 return ret;
2516
2517         cmd = MI_FLUSH_DW;
2518         if (INTEL_INFO(ring->dev)->gen >= 8)
2519                 cmd += 1;
2520
2521         /* We always require a command barrier so that subsequent
2522          * commands, such as breadcrumb interrupts, are strictly ordered
2523          * wrt the contents of the write cache being flushed to memory
2524          * (and thus being coherent from the CPU).
2525          */
2526         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2527
2528         /*
2529          * Bspec vol 1c.5 - video engine command streamer:
2530          * "If ENABLED, all TLBs will be invalidated once the flush
2531          * operation is complete. This bit is only valid when the
2532          * Post-Sync Operation field is a value of 1h or 3h."
2533          */
2534         if (invalidate & I915_GEM_GPU_DOMAINS)
2535                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2536
2537         intel_ring_emit(ring, cmd);
2538         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2539         if (INTEL_INFO(ring->dev)->gen >= 8) {
2540                 intel_ring_emit(ring, 0); /* upper addr */
2541                 intel_ring_emit(ring, 0); /* value */
2542         } else  {
2543                 intel_ring_emit(ring, 0);
2544                 intel_ring_emit(ring, MI_NOOP);
2545         }
2546         intel_ring_advance(ring);
2547         return 0;
2548 }
2549
2550 static int
2551 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2552                               u64 offset, u32 len,
2553                               unsigned dispatch_flags)
2554 {
2555         struct intel_engine_cs *ring = req->ring;
2556         bool ppgtt = USES_PPGTT(ring->dev) &&
2557                         !(dispatch_flags & I915_DISPATCH_SECURE);
2558         int ret;
2559
2560         ret = intel_ring_begin(req, 4);
2561         if (ret)
2562                 return ret;
2563
2564         /* FIXME(BDW): Address space and security selectors. */
2565         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2566                         (dispatch_flags & I915_DISPATCH_RS ?
2567                          MI_BATCH_RESOURCE_STREAMER : 0));
2568         intel_ring_emit(ring, lower_32_bits(offset));
2569         intel_ring_emit(ring, upper_32_bits(offset));
2570         intel_ring_emit(ring, MI_NOOP);
2571         intel_ring_advance(ring);
2572
2573         return 0;
2574 }
2575
2576 static int
2577 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2578                              u64 offset, u32 len,
2579                              unsigned dispatch_flags)
2580 {
2581         struct intel_engine_cs *ring = req->ring;
2582         int ret;
2583
2584         ret = intel_ring_begin(req, 2);
2585         if (ret)
2586                 return ret;
2587
2588         intel_ring_emit(ring,
2589                         MI_BATCH_BUFFER_START |
2590                         (dispatch_flags & I915_DISPATCH_SECURE ?
2591                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2592                         (dispatch_flags & I915_DISPATCH_RS ?
2593                          MI_BATCH_RESOURCE_STREAMER : 0));
2594         /* bit0-7 is the length on GEN6+ */
2595         intel_ring_emit(ring, offset);
2596         intel_ring_advance(ring);
2597
2598         return 0;
2599 }
2600
2601 static int
2602 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2603                               u64 offset, u32 len,
2604                               unsigned dispatch_flags)
2605 {
2606         struct intel_engine_cs *ring = req->ring;
2607         int ret;
2608
2609         ret = intel_ring_begin(req, 2);
2610         if (ret)
2611                 return ret;
2612
2613         intel_ring_emit(ring,
2614                         MI_BATCH_BUFFER_START |
2615                         (dispatch_flags & I915_DISPATCH_SECURE ?
2616                          0 : MI_BATCH_NON_SECURE_I965));
2617         /* bit0-7 is the length on GEN6+ */
2618         intel_ring_emit(ring, offset);
2619         intel_ring_advance(ring);
2620
2621         return 0;
2622 }
2623
2624 /* Blitter support (SandyBridge+) */
2625
2626 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2627                            u32 invalidate, u32 flush)
2628 {
2629         struct intel_engine_cs *ring = req->ring;
2630         struct drm_device *dev = ring->dev;
2631         uint32_t cmd;
2632         int ret;
2633
2634         ret = intel_ring_begin(req, 4);
2635         if (ret)
2636                 return ret;
2637
2638         cmd = MI_FLUSH_DW;
2639         if (INTEL_INFO(dev)->gen >= 8)
2640                 cmd += 1;
2641
2642         /* We always require a command barrier so that subsequent
2643          * commands, such as breadcrumb interrupts, are strictly ordered
2644          * wrt the contents of the write cache being flushed to memory
2645          * (and thus being coherent from the CPU).
2646          */
2647         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2648
2649         /*
2650          * Bspec vol 1c.3 - blitter engine command streamer:
2651          * "If ENABLED, all TLBs will be invalidated once the flush
2652          * operation is complete. This bit is only valid when the
2653          * Post-Sync Operation field is a value of 1h or 3h."
2654          */
2655         if (invalidate & I915_GEM_DOMAIN_RENDER)
2656                 cmd |= MI_INVALIDATE_TLB;
2657         intel_ring_emit(ring, cmd);
2658         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2659         if (INTEL_INFO(dev)->gen >= 8) {
2660                 intel_ring_emit(ring, 0); /* upper addr */
2661                 intel_ring_emit(ring, 0); /* value */
2662         } else  {
2663                 intel_ring_emit(ring, 0);
2664                 intel_ring_emit(ring, MI_NOOP);
2665         }
2666         intel_ring_advance(ring);
2667
2668         return 0;
2669 }
2670
2671 int intel_init_render_ring_buffer(struct drm_device *dev)
2672 {
2673         struct drm_i915_private *dev_priv = dev->dev_private;
2674         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2675         struct drm_i915_gem_object *obj;
2676         int ret;
2677
2678         ring->name = "render ring";
2679         ring->id = RCS;
2680         ring->mmio_base = RENDER_RING_BASE;
2681
2682         if (INTEL_INFO(dev)->gen >= 8) {
2683                 if (i915_semaphore_is_enabled(dev)) {
2684                         obj = i915_gem_alloc_object(dev, 4096);
2685                         if (obj == NULL) {
2686                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2687                                 i915.semaphores = 0;
2688                         } else {
2689                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2690                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2691                                 if (ret != 0) {
2692                                         drm_gem_object_unreference(&obj->base);
2693                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2694                                         i915.semaphores = 0;
2695                                 } else
2696                                         dev_priv->semaphore_obj = obj;
2697                         }
2698                 }
2699
2700                 ring->init_context = intel_rcs_ctx_init;
2701                 ring->add_request = gen6_add_request;
2702                 ring->flush = gen8_render_ring_flush;
2703                 ring->irq_get = gen8_ring_get_irq;
2704                 ring->irq_put = gen8_ring_put_irq;
2705                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2706                 ring->get_seqno = gen6_ring_get_seqno;
2707                 ring->set_seqno = ring_set_seqno;
2708                 if (i915_semaphore_is_enabled(dev)) {
2709                         WARN_ON(!dev_priv->semaphore_obj);
2710                         ring->semaphore.sync_to = gen8_ring_sync;
2711                         ring->semaphore.signal = gen8_rcs_signal;
2712                         GEN8_RING_SEMAPHORE_INIT;
2713                 }
2714         } else if (INTEL_INFO(dev)->gen >= 6) {
2715                 ring->init_context = intel_rcs_ctx_init;
2716                 ring->add_request = gen6_add_request;
2717                 ring->flush = gen7_render_ring_flush;
2718                 if (INTEL_INFO(dev)->gen == 6)
2719                         ring->flush = gen6_render_ring_flush;
2720                 ring->irq_get = gen6_ring_get_irq;
2721                 ring->irq_put = gen6_ring_put_irq;
2722                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2723                 ring->get_seqno = gen6_ring_get_seqno;
2724                 ring->set_seqno = ring_set_seqno;
2725                 if (i915_semaphore_is_enabled(dev)) {
2726                         ring->semaphore.sync_to = gen6_ring_sync;
2727                         ring->semaphore.signal = gen6_signal;
2728                         /*
2729                          * The current semaphore is only applied on pre-gen8
2730                          * platform.  And there is no VCS2 ring on the pre-gen8
2731                          * platform. So the semaphore between RCS and VCS2 is
2732                          * initialized as INVALID.  Gen8 will initialize the
2733                          * sema between VCS2 and RCS later.
2734                          */
2735                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2736                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2737                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2738                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2739                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2740                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2741                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2742                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2743                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2744                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2745                 }
2746         } else if (IS_GEN5(dev)) {
2747                 ring->add_request = pc_render_add_request;
2748                 ring->flush = gen4_render_ring_flush;
2749                 ring->get_seqno = pc_render_get_seqno;
2750                 ring->set_seqno = pc_render_set_seqno;
2751                 ring->irq_get = gen5_ring_get_irq;
2752                 ring->irq_put = gen5_ring_put_irq;
2753                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2754                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2755         } else {
2756                 ring->add_request = i9xx_add_request;
2757                 if (INTEL_INFO(dev)->gen < 4)
2758                         ring->flush = gen2_render_ring_flush;
2759                 else
2760                         ring->flush = gen4_render_ring_flush;
2761                 ring->get_seqno = ring_get_seqno;
2762                 ring->set_seqno = ring_set_seqno;
2763                 if (IS_GEN2(dev)) {
2764                         ring->irq_get = i8xx_ring_get_irq;
2765                         ring->irq_put = i8xx_ring_put_irq;
2766                 } else {
2767                         ring->irq_get = i9xx_ring_get_irq;
2768                         ring->irq_put = i9xx_ring_put_irq;
2769                 }
2770                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2771         }
2772         ring->write_tail = ring_write_tail;
2773
2774         if (IS_HASWELL(dev))
2775                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2776         else if (IS_GEN8(dev))
2777                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2778         else if (INTEL_INFO(dev)->gen >= 6)
2779                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2780         else if (INTEL_INFO(dev)->gen >= 4)
2781                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2782         else if (IS_I830(dev) || IS_845G(dev))
2783                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2784         else
2785                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2786         ring->init_hw = init_render_ring;
2787         ring->cleanup = render_ring_cleanup;
2788
2789         /* Workaround batchbuffer to combat CS tlb bug. */
2790         if (HAS_BROKEN_CS_TLB(dev)) {
2791                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2792                 if (obj == NULL) {
2793                         DRM_ERROR("Failed to allocate batch bo\n");
2794                         return -ENOMEM;
2795                 }
2796
2797                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2798                 if (ret != 0) {
2799                         drm_gem_object_unreference(&obj->base);
2800                         DRM_ERROR("Failed to ping batch bo\n");
2801                         return ret;
2802                 }
2803
2804                 ring->scratch.obj = obj;
2805                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2806         }
2807
2808         ret = intel_init_ring_buffer(dev, ring);
2809         if (ret)
2810                 return ret;
2811
2812         if (INTEL_INFO(dev)->gen >= 5) {
2813                 ret = intel_init_pipe_control(ring);
2814                 if (ret)
2815                         return ret;
2816         }
2817
2818         return 0;
2819 }
2820
2821 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2822 {
2823         struct drm_i915_private *dev_priv = dev->dev_private;
2824         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2825
2826         ring->name = "bsd ring";
2827         ring->id = VCS;
2828
2829         ring->write_tail = ring_write_tail;
2830         if (INTEL_INFO(dev)->gen >= 6) {
2831                 ring->mmio_base = GEN6_BSD_RING_BASE;
2832                 /* gen6 bsd needs a special wa for tail updates */
2833                 if (IS_GEN6(dev))
2834                         ring->write_tail = gen6_bsd_ring_write_tail;
2835                 ring->flush = gen6_bsd_ring_flush;
2836                 ring->add_request = gen6_add_request;
2837                 ring->get_seqno = gen6_ring_get_seqno;
2838                 ring->set_seqno = ring_set_seqno;
2839                 if (INTEL_INFO(dev)->gen >= 8) {
2840                         ring->irq_enable_mask =
2841                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2842                         ring->irq_get = gen8_ring_get_irq;
2843                         ring->irq_put = gen8_ring_put_irq;
2844                         ring->dispatch_execbuffer =
2845                                 gen8_ring_dispatch_execbuffer;
2846                         if (i915_semaphore_is_enabled(dev)) {
2847                                 ring->semaphore.sync_to = gen8_ring_sync;
2848                                 ring->semaphore.signal = gen8_xcs_signal;
2849                                 GEN8_RING_SEMAPHORE_INIT;
2850                         }
2851                 } else {
2852                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2853                         ring->irq_get = gen6_ring_get_irq;
2854                         ring->irq_put = gen6_ring_put_irq;
2855                         ring->dispatch_execbuffer =
2856                                 gen6_ring_dispatch_execbuffer;
2857                         if (i915_semaphore_is_enabled(dev)) {
2858                                 ring->semaphore.sync_to = gen6_ring_sync;
2859                                 ring->semaphore.signal = gen6_signal;
2860                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2861                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2862                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2863                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2864                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2865                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2866                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2867                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2868                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2869                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2870                         }
2871                 }
2872         } else {
2873                 ring->mmio_base = BSD_RING_BASE;
2874                 ring->flush = bsd_ring_flush;
2875                 ring->add_request = i9xx_add_request;
2876                 ring->get_seqno = ring_get_seqno;
2877                 ring->set_seqno = ring_set_seqno;
2878                 if (IS_GEN5(dev)) {
2879                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2880                         ring->irq_get = gen5_ring_get_irq;
2881                         ring->irq_put = gen5_ring_put_irq;
2882                 } else {
2883                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2884                         ring->irq_get = i9xx_ring_get_irq;
2885                         ring->irq_put = i9xx_ring_put_irq;
2886                 }
2887                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2888         }
2889         ring->init_hw = init_ring_common;
2890
2891         return intel_init_ring_buffer(dev, ring);
2892 }
2893
2894 /**
2895  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2896  */
2897 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2898 {
2899         struct drm_i915_private *dev_priv = dev->dev_private;
2900         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2901
2902         ring->name = "bsd2 ring";
2903         ring->id = VCS2;
2904
2905         ring->write_tail = ring_write_tail;
2906         ring->mmio_base = GEN8_BSD2_RING_BASE;
2907         ring->flush = gen6_bsd_ring_flush;
2908         ring->add_request = gen6_add_request;
2909         ring->get_seqno = gen6_ring_get_seqno;
2910         ring->set_seqno = ring_set_seqno;
2911         ring->irq_enable_mask =
2912                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2913         ring->irq_get = gen8_ring_get_irq;
2914         ring->irq_put = gen8_ring_put_irq;
2915         ring->dispatch_execbuffer =
2916                         gen8_ring_dispatch_execbuffer;
2917         if (i915_semaphore_is_enabled(dev)) {
2918                 ring->semaphore.sync_to = gen8_ring_sync;
2919                 ring->semaphore.signal = gen8_xcs_signal;
2920                 GEN8_RING_SEMAPHORE_INIT;
2921         }
2922         ring->init_hw = init_ring_common;
2923
2924         return intel_init_ring_buffer(dev, ring);
2925 }
2926
2927 int intel_init_blt_ring_buffer(struct drm_device *dev)
2928 {
2929         struct drm_i915_private *dev_priv = dev->dev_private;
2930         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2931
2932         ring->name = "blitter ring";
2933         ring->id = BCS;
2934
2935         ring->mmio_base = BLT_RING_BASE;
2936         ring->write_tail = ring_write_tail;
2937         ring->flush = gen6_ring_flush;
2938         ring->add_request = gen6_add_request;
2939         ring->get_seqno = gen6_ring_get_seqno;
2940         ring->set_seqno = ring_set_seqno;
2941         if (INTEL_INFO(dev)->gen >= 8) {
2942                 ring->irq_enable_mask =
2943                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2944                 ring->irq_get = gen8_ring_get_irq;
2945                 ring->irq_put = gen8_ring_put_irq;
2946                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2947                 if (i915_semaphore_is_enabled(dev)) {
2948                         ring->semaphore.sync_to = gen8_ring_sync;
2949                         ring->semaphore.signal = gen8_xcs_signal;
2950                         GEN8_RING_SEMAPHORE_INIT;
2951                 }
2952         } else {
2953                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2954                 ring->irq_get = gen6_ring_get_irq;
2955                 ring->irq_put = gen6_ring_put_irq;
2956                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2957                 if (i915_semaphore_is_enabled(dev)) {
2958                         ring->semaphore.signal = gen6_signal;
2959                         ring->semaphore.sync_to = gen6_ring_sync;
2960                         /*
2961                          * The current semaphore is only applied on pre-gen8
2962                          * platform.  And there is no VCS2 ring on the pre-gen8
2963                          * platform. So the semaphore between BCS and VCS2 is
2964                          * initialized as INVALID.  Gen8 will initialize the
2965                          * sema between BCS and VCS2 later.
2966                          */
2967                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2968                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2969                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2970                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2971                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2972                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2973                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2974                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2975                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2976                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2977                 }
2978         }
2979         ring->init_hw = init_ring_common;
2980
2981         return intel_init_ring_buffer(dev, ring);
2982 }
2983
2984 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2985 {
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2988
2989         ring->name = "video enhancement ring";
2990         ring->id = VECS;
2991
2992         ring->mmio_base = VEBOX_RING_BASE;
2993         ring->write_tail = ring_write_tail;
2994         ring->flush = gen6_ring_flush;
2995         ring->add_request = gen6_add_request;
2996         ring->get_seqno = gen6_ring_get_seqno;
2997         ring->set_seqno = ring_set_seqno;
2998
2999         if (INTEL_INFO(dev)->gen >= 8) {
3000                 ring->irq_enable_mask =
3001                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3002                 ring->irq_get = gen8_ring_get_irq;
3003                 ring->irq_put = gen8_ring_put_irq;
3004                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3005                 if (i915_semaphore_is_enabled(dev)) {
3006                         ring->semaphore.sync_to = gen8_ring_sync;
3007                         ring->semaphore.signal = gen8_xcs_signal;
3008                         GEN8_RING_SEMAPHORE_INIT;
3009                 }
3010         } else {
3011                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3012                 ring->irq_get = hsw_vebox_get_irq;
3013                 ring->irq_put = hsw_vebox_put_irq;
3014                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3015                 if (i915_semaphore_is_enabled(dev)) {
3016                         ring->semaphore.sync_to = gen6_ring_sync;
3017                         ring->semaphore.signal = gen6_signal;
3018                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3019                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3020                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3021                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3022                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3023                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3024                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3025                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3026                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3027                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3028                 }
3029         }
3030         ring->init_hw = init_ring_common;
3031
3032         return intel_init_ring_buffer(dev, ring);
3033 }
3034
3035 int
3036 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3037 {
3038         struct intel_engine_cs *ring = req->ring;
3039         int ret;
3040
3041         if (!ring->gpu_caches_dirty)
3042                 return 0;
3043
3044         ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
3045         if (ret)
3046                 return ret;
3047
3048         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3049
3050         ring->gpu_caches_dirty = false;
3051         return 0;
3052 }
3053
3054 int
3055 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3056 {
3057         struct intel_engine_cs *ring = req->ring;
3058         uint32_t flush_domains;
3059         int ret;
3060
3061         flush_domains = 0;
3062         if (ring->gpu_caches_dirty)
3063                 flush_domains = I915_GEM_GPU_DOMAINS;
3064
3065         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3066         if (ret)
3067                 return ret;
3068
3069         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3070
3071         ring->gpu_caches_dirty = false;
3072         return 0;
3073 }
3074
3075 void
3076 intel_stop_ring_buffer(struct intel_engine_cs *ring)
3077 {
3078         int ret;
3079
3080         if (!intel_ring_initialized(ring))
3081                 return;
3082
3083         ret = intel_ring_idle(ring);
3084         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3085                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3086                           ring->name, ret);
3087
3088         stop_ring(ring);
3089 }