drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 static inline int ring_space(struct intel_ring_buffer *ring)
  37 {
  38         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  39         if (space < 0)
  40                 space += ring->size;
  41         return space;
  42 }
  43
  44 void __intel_ring_advance(struct intel_ring_buffer *ring)
  45 {
  46         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  47
  48         ring->tail &= ring->size - 1;
  49         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
  50                 return;
  51         ring->write_tail(ring, ring->tail);
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 179         int ret;
 180
 181
 182         ret = intel_ring_begin(ring, 6);
 183         if (ret)
 184                 return ret;
 185
 186         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 187         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 188                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 189         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 190         intel_ring_emit(ring, 0); /* low dword */
 191         intel_ring_emit(ring, 0); /* high dword */
 192         intel_ring_emit(ring, MI_NOOP);
 193         intel_ring_advance(ring);
 194
 195         ret = intel_ring_begin(ring, 6);
 196         if (ret)
 197                 return ret;
 198
 199         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 200         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 201         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 202         intel_ring_emit(ring, 0);
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, MI_NOOP);
 205         intel_ring_advance(ring);
 206
 207         return 0;
 208 }
 209
 210 static int
 211 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 212                          u32 invalidate_domains, u32 flush_domains)
 213 {
 214         u32 flags = 0;
 215         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 216         int ret;
 217
 218         /* Force SNB workarounds for PIPE_CONTROL flushes */
 219         ret = intel_emit_post_sync_nonzero_flush(ring);
 220         if (ret)
 221                 return ret;
 222
 223         /* Just flush everything.  Experiments have shown that reducing the
 224          * number of bits based on the write domains has little performance
 225          * impact.
 226          */
 227         if (flush_domains) {
 228                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 229                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 230                 /*
 231                  * Ensure that any following seqno writes only happen
 232                  * when the render cache is indeed flushed.
 233                  */
 234                 flags |= PIPE_CONTROL_CS_STALL;
 235         }
 236         if (invalidate_domains) {
 237                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 238                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 239                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 240                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 243                 /*
 244                  * TLB invalidate requires a post-sync write.
 245                  */
 246                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 247         }
 248
 249         ret = intel_ring_begin(ring, 4);
 250         if (ret)
 251                 return ret;
 252
 253         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 254         intel_ring_emit(ring, flags);
 255         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 256         intel_ring_emit(ring, 0);
 257         intel_ring_advance(ring);
 258
 259         return 0;
 260 }
 261
 262 static int
 263 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 264 {
 265         int ret;
 266
 267         ret = intel_ring_begin(ring, 4);
 268         if (ret)
 269                 return ret;
 270
 271         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 272         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 273                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 274         intel_ring_emit(ring, 0);
 275         intel_ring_emit(ring, 0);
 276         intel_ring_advance(ring);
 277
 278         return 0;
 279 }
 280
 281 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 282 {
 283         int ret;
 284
 285         if (!ring->fbc_dirty)
 286                 return 0;
 287
 288         ret = intel_ring_begin(ring, 6);
 289         if (ret)
 290                 return ret;
 291         /* WaFbcNukeOn3DBlt:ivb/hsw */
 292         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 293         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 294         intel_ring_emit(ring, value);
 295         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 296         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 297         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 298         intel_ring_advance(ring);
 299
 300         ring->fbc_dirty = false;
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 306                        u32 invalidate_domains, u32 flush_domains)
 307 {
 308         u32 flags = 0;
 309         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 310         int ret;
 311
 312         /*
 313          * Ensure that any following seqno writes only happen when the render
 314          * cache is indeed flushed.
 315          *
 316          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 317          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 318          * don't try to be clever and just set it unconditionally.
 319          */
 320         flags |= PIPE_CONTROL_CS_STALL;
 321
 322         /* Just flush everything.  Experiments have shown that reducing the
 323          * number of bits based on the write domains has little performance
 324          * impact.
 325          */
 326         if (flush_domains) {
 327                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 328                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 329         }
 330         if (invalidate_domains) {
 331                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 332                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 333                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 337                 /*
 338                  * TLB invalidate requires a post-sync write.
 339                  */
 340                 flags |= PIPE_CONTROL_QW_WRITE;
 341                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 342
 343                 /* Workaround: we must issue a pipe_control with CS-stall bit
 344                  * set before a pipe_control command that has the state cache
 345                  * invalidate bit set. */
 346                 gen7_render_ring_cs_stall_wa(ring);
 347         }
 348
 349         ret = intel_ring_begin(ring, 4);
 350         if (ret)
 351                 return ret;
 352
 353         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 354         intel_ring_emit(ring, flags);
 355         intel_ring_emit(ring, scratch_addr);
 356         intel_ring_emit(ring, 0);
 357         intel_ring_advance(ring);
 358
 359         if (!invalidate_domains && flush_domains)
 360                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 361
 362         return 0;
 363 }
 364
 365 static int
 366 gen8_render_ring_flush(struct intel_ring_buffer *ring,
 367                        u32 invalidate_domains, u32 flush_domains)
 368 {
 369         u32 flags = 0;
 370         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 371         int ret;
 372
 373         flags |= PIPE_CONTROL_CS_STALL;
 374
 375         if (flush_domains) {
 376                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 377                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 378         }
 379         if (invalidate_domains) {
 380                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 381                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 382                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 383                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 384                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 385                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 386                 flags |= PIPE_CONTROL_QW_WRITE;
 387                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 388         }
 389
 390         ret = intel_ring_begin(ring, 6);
 391         if (ret)
 392                 return ret;
 393
 394         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 395         intel_ring_emit(ring, flags);
 396         intel_ring_emit(ring, scratch_addr);
 397         intel_ring_emit(ring, 0);
 398         intel_ring_emit(ring, 0);
 399         intel_ring_emit(ring, 0);
 400         intel_ring_advance(ring);
 401
 402         return 0;
 403
 404 }
 405
 406 static void ring_write_tail(struct intel_ring_buffer *ring,
 407                             u32 value)
 408 {
 409         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 410         I915_WRITE_TAIL(ring, value);
 411 }
 412
 413 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 414 {
 415         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 416         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 417                         RING_ACTHD(ring->mmio_base) : ACTHD;
 418
 419         return I915_READ(acthd_reg);
 420 }
 421
 422 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
 423 {
 424         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 425         u32 addr;
 426
 427         addr = dev_priv->status_page_dmah->busaddr;
 428         if (INTEL_INFO(ring->dev)->gen >= 4)
 429                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 430         I915_WRITE(HWS_PGA, addr);
 431 }
 432
 433 static int init_ring_common(struct intel_ring_buffer *ring)
 434 {
 435         struct drm_device *dev = ring->dev;
 436         drm_i915_private_t *dev_priv = dev->dev_private;
 437         struct drm_i915_gem_object *obj = ring->obj;
 438         int ret = 0;
 439         u32 head;
 440
 441         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 442
 443         if (I915_NEED_GFX_HWS(dev))
 444                 intel_ring_setup_status_page(ring);
 445         else
 446                 ring_setup_phys_status_page(ring);
 447
 448         /* Stop the ring if it's running. */
 449         I915_WRITE_CTL(ring, 0);
 450         I915_WRITE_HEAD(ring, 0);
 451         ring->write_tail(ring, 0);
 452
 453         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 454
 455         /* G45 ring initialization fails to reset head to zero */
 456         if (head != 0) {
 457                 DRM_DEBUG_KMS("%s head not reset to zero "
 458                               "ctl %08x head %08x tail %08x start %08x\n",
 459                               ring->name,
 460                               I915_READ_CTL(ring),
 461                               I915_READ_HEAD(ring),
 462                               I915_READ_TAIL(ring),
 463                               I915_READ_START(ring));
 464
 465                 I915_WRITE_HEAD(ring, 0);
 466
 467                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 468                         DRM_ERROR("failed to set %s head to zero "
 469                                   "ctl %08x head %08x tail %08x start %08x\n",
 470                                   ring->name,
 471                                   I915_READ_CTL(ring),
 472                                   I915_READ_HEAD(ring),
 473                                   I915_READ_TAIL(ring),
 474                                   I915_READ_START(ring));
 475                 }
 476         }
 477
 478         /* Initialize the ring. This must happen _after_ we've cleared the ring
 479          * registers with the above sequence (the readback of the HEAD registers
 480          * also enforces ordering), otherwise the hw might lose the new ring
 481          * register values. */
 482         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 483         I915_WRITE_CTL(ring,
 484                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 485                         | RING_VALID);
 486
 487         /* If the head is still not zero, the ring is dead */
 488         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 489                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 490                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 491                 DRM_ERROR("%s initialization failed "
 492                                 "ctl %08x head %08x tail %08x start %08x\n",
 493                                 ring->name,
 494                                 I915_READ_CTL(ring),
 495                                 I915_READ_HEAD(ring),
 496                                 I915_READ_TAIL(ring),
 497                                 I915_READ_START(ring));
 498                 ret = -EIO;
 499                 goto out;
 500         }
 501
 502         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 503                 i915_kernel_lost_context(ring->dev);
 504         else {
 505                 ring->head = I915_READ_HEAD(ring);
 506                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 507                 ring->space = ring_space(ring);
 508                 ring->last_retired_head = -1;
 509         }
 510
 511         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 512
 513 out:
 514         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 515
 516         return ret;
 517 }
 518
 519 static int
 520 init_pipe_control(struct intel_ring_buffer *ring)
 521 {
 522         int ret;
 523
 524         if (ring->scratch.obj)
 525                 return 0;
 526
 527         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 528         if (ring->scratch.obj == NULL) {
 529                 DRM_ERROR("Failed to allocate seqno page\n");
 530                 ret = -ENOMEM;
 531                 goto err;
 532         }
 533
 534         i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 535
 536         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false);
 537         if (ret)
 538                 goto err_unref;
 539
 540         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 541         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 542         if (ring->scratch.cpu_page == NULL) {
 543                 ret = -ENOMEM;
 544                 goto err_unpin;
 545         }
 546
 547         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 548                          ring->name, ring->scratch.gtt_offset);
 549         return 0;
 550
 551 err_unpin:
 552         i915_gem_object_unpin(ring->scratch.obj);
 553 err_unref:
 554         drm_gem_object_unreference(&ring->scratch.obj->base);
 555 err:
 556         return ret;
 557 }
 558
 559 static int init_render_ring(struct intel_ring_buffer *ring)
 560 {
 561         struct drm_device *dev = ring->dev;
 562         struct drm_i915_private *dev_priv = dev->dev_private;
 563         int ret = init_ring_common(ring);
 564
 565         if (INTEL_INFO(dev)->gen > 3)
 566                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 567
 568         /* We need to disable the AsyncFlip performance optimisations in order
 569          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 570          * programmed to '1' on all products.
 571          *
 572          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 573          */
 574         if (INTEL_INFO(dev)->gen >= 6)
 575                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 576
 577         /* Required for the hardware to program scanline values for waiting */
 578         if (INTEL_INFO(dev)->gen == 6)
 579                 I915_WRITE(GFX_MODE,
 580                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 581
 582         if (IS_GEN7(dev))
 583                 I915_WRITE(GFX_MODE_GEN7,
 584                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 585                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 586
 587         if (INTEL_INFO(dev)->gen >= 5) {
 588                 ret = init_pipe_control(ring);
 589                 if (ret)
 590                         return ret;
 591         }
 592
 593         if (IS_GEN6(dev)) {
 594                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 595                  * "If this bit is set, STCunit will have LRA as replacement
 596                  *  policy. [...] This bit must be reset.  LRA replacement
 597                  *  policy is not supported."
 598                  */
 599                 I915_WRITE(CACHE_MODE_0,
 600                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 601
 602                 /* This is not explicitly set for GEN6, so read the register.
 603                  * see intel_ring_mi_set_context() for why we care.
 604                  * TODO: consider explicitly setting the bit for GEN5
 605                  */
 606                 ring->itlb_before_ctx_switch =
 607                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 608         }
 609
 610         if (INTEL_INFO(dev)->gen >= 6)
 611                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 612
 613         if (HAS_L3_DPF(dev))
 614                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 615
 616         return ret;
 617 }
 618
 619 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 620 {
 621         struct drm_device *dev = ring->dev;
 622
 623         if (ring->scratch.obj == NULL)
 624                 return;
 625
 626         if (INTEL_INFO(dev)->gen >= 5) {
 627                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 628                 i915_gem_object_unpin(ring->scratch.obj);
 629         }
 630
 631         drm_gem_object_unreference(&ring->scratch.obj->base);
 632         ring->scratch.obj = NULL;
 633 }
 634
 635 static void
 636 update_mboxes(struct intel_ring_buffer *ring,
 637               u32 mmio_offset)
 638 {
 639 /* NB: In order to be able to do semaphore MBOX updates for varying number
 640  * of rings, it's easiest if we round up each individual update to a
 641  * multiple of 2 (since ring updates must always be a multiple of 2)
 642  * even though the actual update only requires 3 dwords.
 643  */
 644 #define MBOX_UPDATE_DWORDS 4
 645         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 646         intel_ring_emit(ring, mmio_offset);
 647         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 648         intel_ring_emit(ring, MI_NOOP);
 649 }
 650
 651 /**
 652  * gen6_add_request - Update the semaphore mailbox registers
 653  *
 654  * @ring - ring that is adding a request
 655  * @seqno - return seqno stuck into the ring
 656  *
 657  * Update the mailbox registers in the *other* rings with the current seqno.
 658  * This acts like a signal in the canonical semaphore.
 659  */
 660 static int
 661 gen6_add_request(struct intel_ring_buffer *ring)
 662 {
 663         struct drm_device *dev = ring->dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         struct intel_ring_buffer *useless;
 666         int i, ret;
 667
 668         ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
 669                                       MBOX_UPDATE_DWORDS) +
 670                                       4);
 671         if (ret)
 672                 return ret;
 673 #undef MBOX_UPDATE_DWORDS
 674
 675         for_each_ring(useless, dev_priv, i) {
 676                 u32 mbox_reg = ring->signal_mbox[i];
 677                 if (mbox_reg != GEN6_NOSYNC)
 678                         update_mboxes(ring, mbox_reg);
 679         }
 680
 681         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 682         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 683         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 684         intel_ring_emit(ring, MI_USER_INTERRUPT);
 685         __intel_ring_advance(ring);
 686
 687         return 0;
 688 }
 689
 690 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 691                                               u32 seqno)
 692 {
 693         struct drm_i915_private *dev_priv = dev->dev_private;
 694         return dev_priv->last_seqno < seqno;
 695 }
 696
 697 /**
 698  * intel_ring_sync - sync the waiter to the signaller on seqno
 699  *
 700  * @waiter - ring that is waiting
 701  * @signaller - ring which has, or will signal
 702  * @seqno - seqno which the waiter will block on
 703  */
 704 static int
 705 gen6_ring_sync(struct intel_ring_buffer *waiter,
 706                struct intel_ring_buffer *signaller,
 707                u32 seqno)
 708 {
 709         int ret;
 710         u32 dw1 = MI_SEMAPHORE_MBOX |
 711                   MI_SEMAPHORE_COMPARE |
 712                   MI_SEMAPHORE_REGISTER;
 713
 714         /* Throughout all of the GEM code, seqno passed implies our current
 715          * seqno is >= the last seqno executed. However for hardware the
 716          * comparison is strictly greater than.
 717          */
 718         seqno -= 1;
 719
 720         WARN_ON(signaller->semaphore_register[waiter->id] ==
 721                 MI_SEMAPHORE_SYNC_INVALID);
 722
 723         ret = intel_ring_begin(waiter, 4);
 724         if (ret)
 725                 return ret;
 726
 727         /* If seqno wrap happened, omit the wait with no-ops */
 728         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 729                 intel_ring_emit(waiter,
 730                                 dw1 |
 731                                 signaller->semaphore_register[waiter->id]);
 732                 intel_ring_emit(waiter, seqno);
 733                 intel_ring_emit(waiter, 0);
 734                 intel_ring_emit(waiter, MI_NOOP);
 735         } else {
 736                 intel_ring_emit(waiter, MI_NOOP);
 737                 intel_ring_emit(waiter, MI_NOOP);
 738                 intel_ring_emit(waiter, MI_NOOP);
 739                 intel_ring_emit(waiter, MI_NOOP);
 740         }
 741         intel_ring_advance(waiter);
 742
 743         return 0;
 744 }
 745
 746 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 747 do {                                                                    \
 748         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 749                  PIPE_CONTROL_DEPTH_STALL);                             \
 750         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 751         intel_ring_emit(ring__, 0);                                                     \
 752         intel_ring_emit(ring__, 0);                                                     \
 753 } while (0)
 754
 755 static int
 756 pc_render_add_request(struct intel_ring_buffer *ring)
 757 {
 758         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 759         int ret;
 760
 761         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 762          * incoherent with writes to memory, i.e. completely fubar,
 763          * so we need to use PIPE_NOTIFY instead.
 764          *
 765          * However, we also need to workaround the qword write
 766          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 767          * memory before requesting an interrupt.
 768          */
 769         ret = intel_ring_begin(ring, 32);
 770         if (ret)
 771                 return ret;
 772
 773         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 774                         PIPE_CONTROL_WRITE_FLUSH |
 775                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 776         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 777         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 778         intel_ring_emit(ring, 0);
 779         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 780         scratch_addr += 128; /* write to separate cachelines */
 781         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 782         scratch_addr += 128;
 783         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 784         scratch_addr += 128;
 785         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 786         scratch_addr += 128;
 787         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 788         scratch_addr += 128;
 789         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 790
 791         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 792                         PIPE_CONTROL_WRITE_FLUSH |
 793                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 794                         PIPE_CONTROL_NOTIFY);
 795         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 796         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 797         intel_ring_emit(ring, 0);
 798         __intel_ring_advance(ring);
 799
 800         return 0;
 801 }
 802
 803 static u32
 804 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 805 {
 806         /* Workaround to force correct ordering between irq and seqno writes on
 807          * ivb (and maybe also on snb) by reading from a CS register (like
 808          * ACTHD) before reading the status page. */
 809         if (!lazy_coherency)
 810                 intel_ring_get_active_head(ring);
 811         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 812 }
 813
 814 static u32
 815 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 816 {
 817         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 818 }
 819
 820 static void
 821 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 822 {
 823         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 824 }
 825
 826 static u32
 827 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 828 {
 829         return ring->scratch.cpu_page[0];
 830 }
 831
 832 static void
 833 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 834 {
 835         ring->scratch.cpu_page[0] = seqno;
 836 }
 837
 838 static bool
 839 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 840 {
 841         struct drm_device *dev = ring->dev;
 842         drm_i915_private_t *dev_priv = dev->dev_private;
 843         unsigned long flags;
 844
 845         if (!dev->irq_enabled)
 846                 return false;
 847
 848         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 849         if (ring->irq_refcount++ == 0)
 850                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
 851         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 852
 853         return true;
 854 }
 855
 856 static void
 857 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 858 {
 859         struct drm_device *dev = ring->dev;
 860         drm_i915_private_t *dev_priv = dev->dev_private;
 861         unsigned long flags;
 862
 863         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 864         if (--ring->irq_refcount == 0)
 865                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
 866         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 867 }
 868
 869 static bool
 870 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 871 {
 872         struct drm_device *dev = ring->dev;
 873         drm_i915_private_t *dev_priv = dev->dev_private;
 874         unsigned long flags;
 875
 876         if (!dev->irq_enabled)
 877                 return false;
 878
 879         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 880         if (ring->irq_refcount++ == 0) {
 881                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 882                 I915_WRITE(IMR, dev_priv->irq_mask);
 883                 POSTING_READ(IMR);
 884         }
 885         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 886
 887         return true;
 888 }
 889
 890 static void
 891 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 892 {
 893         struct drm_device *dev = ring->dev;
 894         drm_i915_private_t *dev_priv = dev->dev_private;
 895         unsigned long flags;
 896
 897         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 898         if (--ring->irq_refcount == 0) {
 899                 dev_priv->irq_mask |= ring->irq_enable_mask;
 900                 I915_WRITE(IMR, dev_priv->irq_mask);
 901                 POSTING_READ(IMR);
 902         }
 903         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 904 }
 905
 906 static bool
 907 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 908 {
 909         struct drm_device *dev = ring->dev;
 910         drm_i915_private_t *dev_priv = dev->dev_private;
 911         unsigned long flags;
 912
 913         if (!dev->irq_enabled)
 914                 return false;
 915
 916         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 917         if (ring->irq_refcount++ == 0) {
 918                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 919                 I915_WRITE16(IMR, dev_priv->irq_mask);
 920                 POSTING_READ16(IMR);
 921         }
 922         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 923
 924         return true;
 925 }
 926
 927 static void
 928 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 929 {
 930         struct drm_device *dev = ring->dev;
 931         drm_i915_private_t *dev_priv = dev->dev_private;
 932         unsigned long flags;
 933
 934         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 935         if (--ring->irq_refcount == 0) {
 936                 dev_priv->irq_mask |= ring->irq_enable_mask;
 937                 I915_WRITE16(IMR, dev_priv->irq_mask);
 938                 POSTING_READ16(IMR);
 939         }
 940         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 941 }
 942
 943 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 944 {
 945         struct drm_device *dev = ring->dev;
 946         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 947         u32 mmio = 0;
 948
 949         /* The ring status page addresses are no longer next to the rest of
 950          * the ring registers as of gen7.
 951          */
 952         if (IS_GEN7(dev)) {
 953                 switch (ring->id) {
 954                 case RCS:
 955                         mmio = RENDER_HWS_PGA_GEN7;
 956                         break;
 957                 case BCS:
 958                         mmio = BLT_HWS_PGA_GEN7;
 959                         break;
 960                 case VCS:
 961                         mmio = BSD_HWS_PGA_GEN7;
 962                         break;
 963                 case VECS:
 964                         mmio = VEBOX_HWS_PGA_GEN7;
 965                         break;
 966                 }
 967         } else if (IS_GEN6(ring->dev)) {
 968                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 969         } else {
 970                 /* XXX: gen8 returns to sanity */
 971                 mmio = RING_HWS_PGA(ring->mmio_base);
 972         }
 973
 974         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 975         POSTING_READ(mmio);
 976
 977         /* Flush the TLB for this page */
 978         if (INTEL_INFO(dev)->gen >= 6) {
 979                 u32 reg = RING_INSTPM(ring->mmio_base);
 980                 I915_WRITE(reg,
 981                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 982                                               INSTPM_SYNC_FLUSH));
 983                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 984                              1000))
 985                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 986                                   ring->name);
 987         }
 988 }
 989
 990 static int
 991 bsd_ring_flush(struct intel_ring_buffer *ring,
 992                u32     invalidate_domains,
 993                u32     flush_domains)
 994 {
 995         int ret;
 996
 997         ret = intel_ring_begin(ring, 2);
 998         if (ret)
 999                 return ret;
1000
1001         intel_ring_emit(ring, MI_FLUSH);
1002         intel_ring_emit(ring, MI_NOOP);
1003         intel_ring_advance(ring);
1004         return 0;
1005 }
1006
1007 static int
1008 i9xx_add_request(struct intel_ring_buffer *ring)
1009 {
1010         int ret;
1011
1012         ret = intel_ring_begin(ring, 4);
1013         if (ret)
1014                 return ret;
1015
1016         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1017         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1018         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1019         intel_ring_emit(ring, MI_USER_INTERRUPT);
1020         __intel_ring_advance(ring);
1021
1022         return 0;
1023 }
1024
1025 static bool
1026 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1027 {
1028         struct drm_device *dev = ring->dev;
1029         drm_i915_private_t *dev_priv = dev->dev_private;
1030         unsigned long flags;
1031
1032         if (!dev->irq_enabled)
1033                return false;
1034
1035         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1036         if (ring->irq_refcount++ == 0) {
1037                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1038                         I915_WRITE_IMR(ring,
1039                                        ~(ring->irq_enable_mask |
1040                                          GT_PARITY_ERROR(dev)));
1041                 else
1042                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1043                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1044         }
1045         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1046
1047         return true;
1048 }
1049
1050 static void
1051 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1052 {
1053         struct drm_device *dev = ring->dev;
1054         drm_i915_private_t *dev_priv = dev->dev_private;
1055         unsigned long flags;
1056
1057         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1058         if (--ring->irq_refcount == 0) {
1059                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1060                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1061                 else
1062                         I915_WRITE_IMR(ring, ~0);
1063                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1064         }
1065         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1066 }
1067
1068 static bool
1069 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1070 {
1071         struct drm_device *dev = ring->dev;
1072         struct drm_i915_private *dev_priv = dev->dev_private;
1073         unsigned long flags;
1074
1075         if (!dev->irq_enabled)
1076                 return false;
1077
1078         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1079         if (ring->irq_refcount++ == 0) {
1080                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1081                 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1082         }
1083         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1084
1085         return true;
1086 }
1087
1088 static void
1089 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1090 {
1091         struct drm_device *dev = ring->dev;
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093         unsigned long flags;
1094
1095         if (!dev->irq_enabled)
1096                 return;
1097
1098         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1099         if (--ring->irq_refcount == 0) {
1100                 I915_WRITE_IMR(ring, ~0);
1101                 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1102         }
1103         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1104 }
1105
1106 static bool
1107 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1108 {
1109         struct drm_device *dev = ring->dev;
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         unsigned long flags;
1112
1113         if (!dev->irq_enabled)
1114                 return false;
1115
1116         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1117         if (ring->irq_refcount++ == 0) {
1118                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1119                         I915_WRITE_IMR(ring,
1120                                        ~(ring->irq_enable_mask |
1121                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1122                 } else {
1123                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1124                 }
1125                 POSTING_READ(RING_IMR(ring->mmio_base));
1126         }
1127         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1128
1129         return true;
1130 }
1131
1132 static void
1133 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1134 {
1135         struct drm_device *dev = ring->dev;
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         unsigned long flags;
1138
1139         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1140         if (--ring->irq_refcount == 0) {
1141                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1142                         I915_WRITE_IMR(ring,
1143                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1144                 } else {
1145                         I915_WRITE_IMR(ring, ~0);
1146                 }
1147                 POSTING_READ(RING_IMR(ring->mmio_base));
1148         }
1149         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1150 }
1151
1152 static int
1153 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1154                          u32 offset, u32 length,
1155                          unsigned flags)
1156 {
1157         int ret;
1158
1159         ret = intel_ring_begin(ring, 2);
1160         if (ret)
1161                 return ret;
1162
1163         intel_ring_emit(ring,
1164                         MI_BATCH_BUFFER_START |
1165                         MI_BATCH_GTT |
1166                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1167         intel_ring_emit(ring, offset);
1168         intel_ring_advance(ring);
1169
1170         return 0;
1171 }
1172
1173 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1174 #define I830_BATCH_LIMIT (256*1024)
1175 static int
1176 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1177                                 u32 offset, u32 len,
1178                                 unsigned flags)
1179 {
1180         int ret;
1181
1182         if (flags & I915_DISPATCH_PINNED) {
1183                 ret = intel_ring_begin(ring, 4);
1184                 if (ret)
1185                         return ret;
1186
1187                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1188                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1189                 intel_ring_emit(ring, offset + len - 8);
1190                 intel_ring_emit(ring, MI_NOOP);
1191                 intel_ring_advance(ring);
1192         } else {
1193                 u32 cs_offset = ring->scratch.gtt_offset;
1194
1195                 if (len > I830_BATCH_LIMIT)
1196                         return -ENOSPC;
1197
1198                 ret = intel_ring_begin(ring, 9+3);
1199                 if (ret)
1200                         return ret;
1201                 /* Blit the batch (which has now all relocs applied) to the stable batch
1202                  * scratch bo area (so that the CS never stumbles over its tlb
1203                  * invalidation bug) ... */
1204                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1205                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1206                                 XY_SRC_COPY_BLT_WRITE_RGB);
1207                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1208                 intel_ring_emit(ring, 0);
1209                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1210                 intel_ring_emit(ring, cs_offset);
1211                 intel_ring_emit(ring, 0);
1212                 intel_ring_emit(ring, 4096);
1213                 intel_ring_emit(ring, offset);
1214                 intel_ring_emit(ring, MI_FLUSH);
1215
1216                 /* ... and execute it. */
1217                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1218                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1219                 intel_ring_emit(ring, cs_offset + len - 8);
1220                 intel_ring_advance(ring);
1221         }
1222
1223         return 0;
1224 }
1225
1226 static int
1227 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1228                          u32 offset, u32 len,
1229                          unsigned flags)
1230 {
1231         int ret;
1232
1233         ret = intel_ring_begin(ring, 2);
1234         if (ret)
1235                 return ret;
1236
1237         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1238         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1239         intel_ring_advance(ring);
1240
1241         return 0;
1242 }
1243
1244 static void cleanup_status_page(struct intel_ring_buffer *ring)
1245 {
1246         struct drm_i915_gem_object *obj;
1247
1248         obj = ring->status_page.obj;
1249         if (obj == NULL)
1250                 return;
1251
1252         kunmap(sg_page(obj->pages->sgl));
1253         i915_gem_object_unpin(obj);
1254         drm_gem_object_unreference(&obj->base);
1255         ring->status_page.obj = NULL;
1256 }
1257
1258 static int init_status_page(struct intel_ring_buffer *ring)
1259 {
1260         struct drm_device *dev = ring->dev;
1261         struct drm_i915_gem_object *obj;
1262         int ret;
1263
1264         obj = i915_gem_alloc_object(dev, 4096);
1265         if (obj == NULL) {
1266                 DRM_ERROR("Failed to allocate status page\n");
1267                 ret = -ENOMEM;
1268                 goto err;
1269         }
1270
1271         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1272
1273         ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false);
1274         if (ret != 0) {
1275                 goto err_unref;
1276         }
1277
1278         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1279         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1280         if (ring->status_page.page_addr == NULL) {
1281                 ret = -ENOMEM;
1282                 goto err_unpin;
1283         }
1284         ring->status_page.obj = obj;
1285         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1286
1287         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1288                         ring->name, ring->status_page.gfx_addr);
1289
1290         return 0;
1291
1292 err_unpin:
1293         i915_gem_object_unpin(obj);
1294 err_unref:
1295         drm_gem_object_unreference(&obj->base);
1296 err:
1297         return ret;
1298 }
1299
1300 static int init_phys_status_page(struct intel_ring_buffer *ring)
1301 {
1302         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1303
1304         if (!dev_priv->status_page_dmah) {
1305                 dev_priv->status_page_dmah =
1306                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1307                 if (!dev_priv->status_page_dmah)
1308                         return -ENOMEM;
1309         }
1310
1311         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1312         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1313
1314         return 0;
1315 }
1316
1317 static int intel_init_ring_buffer(struct drm_device *dev,
1318                                   struct intel_ring_buffer *ring)
1319 {
1320         struct drm_i915_gem_object *obj;
1321         struct drm_i915_private *dev_priv = dev->dev_private;
1322         int ret;
1323
1324         ring->dev = dev;
1325         INIT_LIST_HEAD(&ring->active_list);
1326         INIT_LIST_HEAD(&ring->request_list);
1327         ring->size = 32 * PAGE_SIZE;
1328         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1329
1330         init_waitqueue_head(&ring->irq_queue);
1331
1332         if (I915_NEED_GFX_HWS(dev)) {
1333                 ret = init_status_page(ring);
1334                 if (ret)
1335                         return ret;
1336         } else {
1337                 BUG_ON(ring->id != RCS);
1338                 ret = init_phys_status_page(ring);
1339                 if (ret)
1340                         return ret;
1341         }
1342
1343         obj = NULL;
1344         if (!HAS_LLC(dev))
1345                 obj = i915_gem_object_create_stolen(dev, ring->size);
1346         if (obj == NULL)
1347                 obj = i915_gem_alloc_object(dev, ring->size);
1348         if (obj == NULL) {
1349                 DRM_ERROR("Failed to allocate ringbuffer\n");
1350                 ret = -ENOMEM;
1351                 goto err_hws;
1352         }
1353
1354         ring->obj = obj;
1355
1356         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false);
1357         if (ret)
1358                 goto err_unref;
1359
1360         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1361         if (ret)
1362                 goto err_unpin;
1363
1364         ring->virtual_start =
1365                 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1366                            ring->size);
1367         if (ring->virtual_start == NULL) {
1368                 DRM_ERROR("Failed to map ringbuffer.\n");
1369                 ret = -EINVAL;
1370                 goto err_unpin;
1371         }
1372
1373         ret = ring->init(ring);
1374         if (ret)
1375                 goto err_unmap;
1376
1377         /* Workaround an erratum on the i830 which causes a hang if
1378          * the TAIL pointer points to within the last 2 cachelines
1379          * of the buffer.
1380          */
1381         ring->effective_size = ring->size;
1382         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1383                 ring->effective_size -= 128;
1384
1385         return 0;
1386
1387 err_unmap:
1388         iounmap(ring->virtual_start);
1389 err_unpin:
1390         i915_gem_object_unpin(obj);
1391 err_unref:
1392         drm_gem_object_unreference(&obj->base);
1393         ring->obj = NULL;
1394 err_hws:
1395         cleanup_status_page(ring);
1396         return ret;
1397 }
1398
1399 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1400 {
1401         struct drm_i915_private *dev_priv;
1402         int ret;
1403
1404         if (ring->obj == NULL)
1405                 return;
1406
1407         /* Disable the ring buffer. The ring must be idle at this point */
1408         dev_priv = ring->dev->dev_private;
1409         ret = intel_ring_idle(ring);
1410         if (ret && !i915_reset_in_progress(&dev_priv->gpu_error))
1411                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1412                           ring->name, ret);
1413
1414         I915_WRITE_CTL(ring, 0);
1415
1416         iounmap(ring->virtual_start);
1417
1418         i915_gem_object_unpin(ring->obj);
1419         drm_gem_object_unreference(&ring->obj->base);
1420         ring->obj = NULL;
1421         ring->preallocated_lazy_request = NULL;
1422         ring->outstanding_lazy_seqno = 0;
1423
1424         if (ring->cleanup)
1425                 ring->cleanup(ring);
1426
1427         cleanup_status_page(ring);
1428 }
1429
1430 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1431 {
1432         int ret;
1433
1434         ret = i915_wait_seqno(ring, seqno);
1435         if (!ret)
1436                 i915_gem_retire_requests_ring(ring);
1437
1438         return ret;
1439 }
1440
1441 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1442 {
1443         struct drm_i915_gem_request *request;
1444         u32 seqno = 0;
1445         int ret;
1446
1447         i915_gem_retire_requests_ring(ring);
1448
1449         if (ring->last_retired_head != -1) {
1450                 ring->head = ring->last_retired_head;
1451                 ring->last_retired_head = -1;
1452                 ring->space = ring_space(ring);
1453                 if (ring->space >= n)
1454                         return 0;
1455         }
1456
1457         list_for_each_entry(request, &ring->request_list, list) {
1458                 int space;
1459
1460                 if (request->tail == -1)
1461                         continue;
1462
1463                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1464                 if (space < 0)
1465                         space += ring->size;
1466                 if (space >= n) {
1467                         seqno = request->seqno;
1468                         break;
1469                 }
1470
1471                 /* Consume this request in case we need more space than
1472                  * is available and so need to prevent a race between
1473                  * updating last_retired_head and direct reads of
1474                  * I915_RING_HEAD. It also provides a nice sanity check.
1475                  */
1476                 request->tail = -1;
1477         }
1478
1479         if (seqno == 0)
1480                 return -ENOSPC;
1481
1482         ret = intel_ring_wait_seqno(ring, seqno);
1483         if (ret)
1484                 return ret;
1485
1486         if (WARN_ON(ring->last_retired_head == -1))
1487                 return -ENOSPC;
1488
1489         ring->head = ring->last_retired_head;
1490         ring->last_retired_head = -1;
1491         ring->space = ring_space(ring);
1492         if (WARN_ON(ring->space < n))
1493                 return -ENOSPC;
1494
1495         return 0;
1496 }
1497
1498 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1499 {
1500         struct drm_device *dev = ring->dev;
1501         struct drm_i915_private *dev_priv = dev->dev_private;
1502         unsigned long end;
1503         int ret;
1504
1505         ret = intel_ring_wait_request(ring, n);
1506         if (ret != -ENOSPC)
1507                 return ret;
1508
1509         /* force the tail write in case we have been skipping them */
1510         __intel_ring_advance(ring);
1511
1512         trace_i915_ring_wait_begin(ring);
1513         /* With GEM the hangcheck timer should kick us out of the loop,
1514          * leaving it early runs the risk of corrupting GEM state (due
1515          * to running on almost untested codepaths). But on resume
1516          * timers don't work yet, so prevent a complete hang in that
1517          * case by choosing an insanely large timeout. */
1518         end = jiffies + 60 * HZ;
1519
1520         do {
1521                 ring->head = I915_READ_HEAD(ring);
1522                 ring->space = ring_space(ring);
1523                 if (ring->space >= n) {
1524                         trace_i915_ring_wait_end(ring);
1525                         return 0;
1526                 }
1527
1528                 if (dev->primary->master) {
1529                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1530                         if (master_priv->sarea_priv)
1531                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1532                 }
1533
1534                 msleep(1);
1535
1536                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1537                                            dev_priv->mm.interruptible);
1538                 if (ret)
1539                         return ret;
1540         } while (!time_after(jiffies, end));
1541         trace_i915_ring_wait_end(ring);
1542         return -EBUSY;
1543 }
1544
1545 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1546 {
1547         uint32_t __iomem *virt;
1548         int rem = ring->size - ring->tail;
1549
1550         if (ring->space < rem) {
1551                 int ret = ring_wait_for_space(ring, rem);
1552                 if (ret)
1553                         return ret;
1554         }
1555
1556         virt = ring->virtual_start + ring->tail;
1557         rem /= 4;
1558         while (rem--)
1559                 iowrite32(MI_NOOP, virt++);
1560
1561         ring->tail = 0;
1562         ring->space = ring_space(ring);
1563
1564         return 0;
1565 }
1566
1567 int intel_ring_idle(struct intel_ring_buffer *ring)
1568 {
1569         u32 seqno;
1570         int ret;
1571
1572         /* We need to add any requests required to flush the objects and ring */
1573         if (ring->outstanding_lazy_seqno) {
1574                 ret = i915_add_request(ring, NULL);
1575                 if (ret)
1576                         return ret;
1577         }
1578
1579         /* Wait upon the last request to be completed */
1580         if (list_empty(&ring->request_list))
1581                 return 0;
1582
1583         seqno = list_entry(ring->request_list.prev,
1584                            struct drm_i915_gem_request,
1585                            list)->seqno;
1586
1587         return i915_wait_seqno(ring, seqno);
1588 }
1589
1590 static int
1591 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1592 {
1593         if (ring->outstanding_lazy_seqno)
1594                 return 0;
1595
1596         if (ring->preallocated_lazy_request == NULL) {
1597                 struct drm_i915_gem_request *request;
1598
1599                 request = kmalloc(sizeof(*request), GFP_KERNEL);
1600                 if (request == NULL)
1601                         return -ENOMEM;
1602
1603                 ring->preallocated_lazy_request = request;
1604         }
1605
1606         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1607 }
1608
1609 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1610                               int bytes)
1611 {
1612         int ret;
1613
1614         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1615                 ret = intel_wrap_ring_buffer(ring);
1616                 if (unlikely(ret))
1617                         return ret;
1618         }
1619
1620         if (unlikely(ring->space < bytes)) {
1621                 ret = ring_wait_for_space(ring, bytes);
1622                 if (unlikely(ret))
1623                         return ret;
1624         }
1625
1626         ring->space -= bytes;
1627         return 0;
1628 }
1629
1630 int intel_ring_begin(struct intel_ring_buffer *ring,
1631                      int num_dwords)
1632 {
1633         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1634         int ret;
1635
1636         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1637                                    dev_priv->mm.interruptible);
1638         if (ret)
1639                 return ret;
1640
1641         /* Preallocate the olr before touching the ring */
1642         ret = intel_ring_alloc_seqno(ring);
1643         if (ret)
1644                 return ret;
1645
1646         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1647 }
1648
1649 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1650 {
1651         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1652
1653         BUG_ON(ring->outstanding_lazy_seqno);
1654
1655         if (INTEL_INFO(ring->dev)->gen >= 6) {
1656                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1657                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1658                 if (HAS_VEBOX(ring->dev))
1659                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1660         }
1661
1662         ring->set_seqno(ring, seqno);
1663         ring->hangcheck.seqno = seqno;
1664 }
1665
1666 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1667                                      u32 value)
1668 {
1669         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1670
1671        /* Every tail move must follow the sequence below */
1672
1673         /* Disable notification that the ring is IDLE. The GT
1674          * will then assume that it is busy and bring it out of rc6.
1675          */
1676         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1677                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1678
1679         /* Clear the context id. Here be magic! */
1680         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1681
1682         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1683         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1684                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1685                      50))
1686                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1687
1688         /* Now that the ring is fully powered up, update the tail */
1689         I915_WRITE_TAIL(ring, value);
1690         POSTING_READ(RING_TAIL(ring->mmio_base));
1691
1692         /* Let the ring send IDLE messages to the GT again,
1693          * and so let it sleep to conserve power when idle.
1694          */
1695         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1696                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1697 }
1698
1699 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1700                                u32 invalidate, u32 flush)
1701 {
1702         uint32_t cmd;
1703         int ret;
1704
1705         ret = intel_ring_begin(ring, 4);
1706         if (ret)
1707                 return ret;
1708
1709         cmd = MI_FLUSH_DW;
1710         if (INTEL_INFO(ring->dev)->gen >= 8)
1711                 cmd += 1;
1712         /*
1713          * Bspec vol 1c.5 - video engine command streamer:
1714          * "If ENABLED, all TLBs will be invalidated once the flush
1715          * operation is complete. This bit is only valid when the
1716          * Post-Sync Operation field is a value of 1h or 3h."
1717          */
1718         if (invalidate & I915_GEM_GPU_DOMAINS)
1719                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1720                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1721         intel_ring_emit(ring, cmd);
1722         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1723         if (INTEL_INFO(ring->dev)->gen >= 8) {
1724                 intel_ring_emit(ring, 0); /* upper addr */
1725                 intel_ring_emit(ring, 0); /* value */
1726         } else  {
1727                 intel_ring_emit(ring, 0);
1728                 intel_ring_emit(ring, MI_NOOP);
1729         }
1730         intel_ring_advance(ring);
1731         return 0;
1732 }
1733
1734 static int
1735 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1736                               u32 offset, u32 len,
1737                               unsigned flags)
1738 {
1739         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1740         bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1741                 !(flags & I915_DISPATCH_SECURE);
1742         int ret;
1743
1744         ret = intel_ring_begin(ring, 4);
1745         if (ret)
1746                 return ret;
1747
1748         /* FIXME(BDW): Address space and security selectors. */
1749         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1750         intel_ring_emit(ring, offset);
1751         intel_ring_emit(ring, 0);
1752         intel_ring_emit(ring, MI_NOOP);
1753         intel_ring_advance(ring);
1754
1755         return 0;
1756 }
1757
1758 static int
1759 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1760                               u32 offset, u32 len,
1761                               unsigned flags)
1762 {
1763         int ret;
1764
1765         ret = intel_ring_begin(ring, 2);
1766         if (ret)
1767                 return ret;
1768
1769         intel_ring_emit(ring,
1770                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1771                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1772         /* bit0-7 is the length on GEN6+ */
1773         intel_ring_emit(ring, offset);
1774         intel_ring_advance(ring);
1775
1776         return 0;
1777 }
1778
1779 static int
1780 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1781                               u32 offset, u32 len,
1782                               unsigned flags)
1783 {
1784         int ret;
1785
1786         ret = intel_ring_begin(ring, 2);
1787         if (ret)
1788                 return ret;
1789
1790         intel_ring_emit(ring,
1791                         MI_BATCH_BUFFER_START |
1792                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1793         /* bit0-7 is the length on GEN6+ */
1794         intel_ring_emit(ring, offset);
1795         intel_ring_advance(ring);
1796
1797         return 0;
1798 }
1799
1800 /* Blitter support (SandyBridge+) */
1801
1802 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1803                            u32 invalidate, u32 flush)
1804 {
1805         struct drm_device *dev = ring->dev;
1806         uint32_t cmd;
1807         int ret;
1808
1809         ret = intel_ring_begin(ring, 4);
1810         if (ret)
1811                 return ret;
1812
1813         cmd = MI_FLUSH_DW;
1814         if (INTEL_INFO(ring->dev)->gen >= 8)
1815                 cmd += 1;
1816         /*
1817          * Bspec vol 1c.3 - blitter engine command streamer:
1818          * "If ENABLED, all TLBs will be invalidated once the flush
1819          * operation is complete. This bit is only valid when the
1820          * Post-Sync Operation field is a value of 1h or 3h."
1821          */
1822         if (invalidate & I915_GEM_DOMAIN_RENDER)
1823                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1824                         MI_FLUSH_DW_OP_STOREDW;
1825         intel_ring_emit(ring, cmd);
1826         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1827         if (INTEL_INFO(ring->dev)->gen >= 8) {
1828                 intel_ring_emit(ring, 0); /* upper addr */
1829                 intel_ring_emit(ring, 0); /* value */
1830         } else  {
1831                 intel_ring_emit(ring, 0);
1832                 intel_ring_emit(ring, MI_NOOP);
1833         }
1834         intel_ring_advance(ring);
1835
1836         if (IS_GEN7(dev) && !invalidate && flush)
1837                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1838
1839         return 0;
1840 }
1841
1842 int intel_init_render_ring_buffer(struct drm_device *dev)
1843 {
1844         drm_i915_private_t *dev_priv = dev->dev_private;
1845         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1846
1847         ring->name = "render ring";
1848         ring->id = RCS;
1849         ring->mmio_base = RENDER_RING_BASE;
1850
1851         if (INTEL_INFO(dev)->gen >= 6) {
1852                 ring->add_request = gen6_add_request;
1853                 ring->flush = gen7_render_ring_flush;
1854                 if (INTEL_INFO(dev)->gen == 6)
1855                         ring->flush = gen6_render_ring_flush;
1856                 if (INTEL_INFO(dev)->gen >= 8) {
1857                         ring->flush = gen8_render_ring_flush;
1858                         ring->irq_get = gen8_ring_get_irq;
1859                         ring->irq_put = gen8_ring_put_irq;
1860                 } else {
1861                         ring->irq_get = gen6_ring_get_irq;
1862                         ring->irq_put = gen6_ring_put_irq;
1863                 }
1864                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1865                 ring->get_seqno = gen6_ring_get_seqno;
1866                 ring->set_seqno = ring_set_seqno;
1867                 ring->sync_to = gen6_ring_sync;
1868                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1869                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1870                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1871                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1872                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1873                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1874                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1875                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1876         } else if (IS_GEN5(dev)) {
1877                 ring->add_request = pc_render_add_request;
1878                 ring->flush = gen4_render_ring_flush;
1879                 ring->get_seqno = pc_render_get_seqno;
1880                 ring->set_seqno = pc_render_set_seqno;
1881                 ring->irq_get = gen5_ring_get_irq;
1882                 ring->irq_put = gen5_ring_put_irq;
1883                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1884                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1885         } else {
1886                 ring->add_request = i9xx_add_request;
1887                 if (INTEL_INFO(dev)->gen < 4)
1888                         ring->flush = gen2_render_ring_flush;
1889                 else
1890                         ring->flush = gen4_render_ring_flush;
1891                 ring->get_seqno = ring_get_seqno;
1892                 ring->set_seqno = ring_set_seqno;
1893                 if (IS_GEN2(dev)) {
1894                         ring->irq_get = i8xx_ring_get_irq;
1895                         ring->irq_put = i8xx_ring_put_irq;
1896                 } else {
1897                         ring->irq_get = i9xx_ring_get_irq;
1898                         ring->irq_put = i9xx_ring_put_irq;
1899                 }
1900                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1901         }
1902         ring->write_tail = ring_write_tail;
1903         if (IS_HASWELL(dev))
1904                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1905         else if (IS_GEN8(dev))
1906                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1907         else if (INTEL_INFO(dev)->gen >= 6)
1908                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1909         else if (INTEL_INFO(dev)->gen >= 4)
1910                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1911         else if (IS_I830(dev) || IS_845G(dev))
1912                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1913         else
1914                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1915         ring->init = init_render_ring;
1916         ring->cleanup = render_ring_cleanup;
1917
1918         /* Workaround batchbuffer to combat CS tlb bug. */
1919         if (HAS_BROKEN_CS_TLB(dev)) {
1920                 struct drm_i915_gem_object *obj;
1921                 int ret;
1922
1923                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1924                 if (obj == NULL) {
1925                         DRM_ERROR("Failed to allocate batch bo\n");
1926                         return -ENOMEM;
1927                 }
1928
1929                 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1930                 if (ret != 0) {
1931                         drm_gem_object_unreference(&obj->base);
1932                         DRM_ERROR("Failed to ping batch bo\n");
1933                         return ret;
1934                 }
1935
1936                 ring->scratch.obj = obj;
1937                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
1938         }
1939
1940         return intel_init_ring_buffer(dev, ring);
1941 }
1942
1943 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1944 {
1945         drm_i915_private_t *dev_priv = dev->dev_private;
1946         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1947         int ret;
1948
1949         ring->name = "render ring";
1950         ring->id = RCS;
1951         ring->mmio_base = RENDER_RING_BASE;
1952
1953         if (INTEL_INFO(dev)->gen >= 6) {
1954                 /* non-kms not supported on gen6+ */
1955                 return -ENODEV;
1956         }
1957
1958         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1959          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1960          * the special gen5 functions. */
1961         ring->add_request = i9xx_add_request;
1962         if (INTEL_INFO(dev)->gen < 4)
1963                 ring->flush = gen2_render_ring_flush;
1964         else
1965                 ring->flush = gen4_render_ring_flush;
1966         ring->get_seqno = ring_get_seqno;
1967         ring->set_seqno = ring_set_seqno;
1968         if (IS_GEN2(dev)) {
1969                 ring->irq_get = i8xx_ring_get_irq;
1970                 ring->irq_put = i8xx_ring_put_irq;
1971         } else {
1972                 ring->irq_get = i9xx_ring_get_irq;
1973                 ring->irq_put = i9xx_ring_put_irq;
1974         }
1975         ring->irq_enable_mask = I915_USER_INTERRUPT;
1976         ring->write_tail = ring_write_tail;
1977         if (INTEL_INFO(dev)->gen >= 4)
1978                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1979         else if (IS_I830(dev) || IS_845G(dev))
1980                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1981         else
1982                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1983         ring->init = init_render_ring;
1984         ring->cleanup = render_ring_cleanup;
1985
1986         ring->dev = dev;
1987         INIT_LIST_HEAD(&ring->active_list);
1988         INIT_LIST_HEAD(&ring->request_list);
1989
1990         ring->size = size;
1991         ring->effective_size = ring->size;
1992         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1993                 ring->effective_size -= 128;
1994
1995         ring->virtual_start = ioremap_wc(start, size);
1996         if (ring->virtual_start == NULL) {
1997                 DRM_ERROR("can not ioremap virtual address for"
1998                           " ring buffer\n");
1999                 return -ENOMEM;
2000         }
2001
2002         if (!I915_NEED_GFX_HWS(dev)) {
2003                 ret = init_phys_status_page(ring);
2004                 if (ret)
2005                         return ret;
2006         }
2007
2008         return 0;
2009 }
2010
2011 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2012 {
2013         drm_i915_private_t *dev_priv = dev->dev_private;
2014         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2015
2016         ring->name = "bsd ring";
2017         ring->id = VCS;
2018
2019         ring->write_tail = ring_write_tail;
2020         if (INTEL_INFO(dev)->gen >= 6) {
2021                 ring->mmio_base = GEN6_BSD_RING_BASE;
2022                 /* gen6 bsd needs a special wa for tail updates */
2023                 if (IS_GEN6(dev))
2024                         ring->write_tail = gen6_bsd_ring_write_tail;
2025                 ring->flush = gen6_bsd_ring_flush;
2026                 ring->add_request = gen6_add_request;
2027                 ring->get_seqno = gen6_ring_get_seqno;
2028                 ring->set_seqno = ring_set_seqno;
2029                 if (INTEL_INFO(dev)->gen >= 8) {
2030                         ring->irq_enable_mask =
2031                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2032                         ring->irq_get = gen8_ring_get_irq;
2033                         ring->irq_put = gen8_ring_put_irq;
2034                         ring->dispatch_execbuffer =
2035                                 gen8_ring_dispatch_execbuffer;
2036                 } else {
2037                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2038                         ring->irq_get = gen6_ring_get_irq;
2039                         ring->irq_put = gen6_ring_put_irq;
2040                         ring->dispatch_execbuffer =
2041                                 gen6_ring_dispatch_execbuffer;
2042                 }
2043                 ring->sync_to = gen6_ring_sync;
2044                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
2045                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2046                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
2047                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
2048                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
2049                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2050                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
2051                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
2052         } else {
2053                 ring->mmio_base = BSD_RING_BASE;
2054                 ring->flush = bsd_ring_flush;
2055                 ring->add_request = i9xx_add_request;
2056                 ring->get_seqno = ring_get_seqno;
2057                 ring->set_seqno = ring_set_seqno;
2058                 if (IS_GEN5(dev)) {
2059                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2060                         ring->irq_get = gen5_ring_get_irq;
2061                         ring->irq_put = gen5_ring_put_irq;
2062                 } else {
2063                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2064                         ring->irq_get = i9xx_ring_get_irq;
2065                         ring->irq_put = i9xx_ring_put_irq;
2066                 }
2067                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2068         }
2069         ring->init = init_ring_common;
2070
2071         return intel_init_ring_buffer(dev, ring);
2072 }
2073
2074 int intel_init_blt_ring_buffer(struct drm_device *dev)
2075 {
2076         drm_i915_private_t *dev_priv = dev->dev_private;
2077         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2078
2079         ring->name = "blitter ring";
2080         ring->id = BCS;
2081
2082         ring->mmio_base = BLT_RING_BASE;
2083         ring->write_tail = ring_write_tail;
2084         ring->flush = gen6_ring_flush;
2085         ring->add_request = gen6_add_request;
2086         ring->get_seqno = gen6_ring_get_seqno;
2087         ring->set_seqno = ring_set_seqno;
2088         if (INTEL_INFO(dev)->gen >= 8) {
2089                 ring->irq_enable_mask =
2090                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2091                 ring->irq_get = gen8_ring_get_irq;
2092                 ring->irq_put = gen8_ring_put_irq;
2093                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2094         } else {
2095                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2096                 ring->irq_get = gen6_ring_get_irq;
2097                 ring->irq_put = gen6_ring_put_irq;
2098                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2099         }
2100         ring->sync_to = gen6_ring_sync;
2101         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2102         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2103         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2104         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
2105         ring->signal_mbox[RCS] = GEN6_RBSYNC;
2106         ring->signal_mbox[VCS] = GEN6_VBSYNC;
2107         ring->signal_mbox[BCS] = GEN6_NOSYNC;
2108         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
2109         ring->init = init_ring_common;
2110
2111         return intel_init_ring_buffer(dev, ring);
2112 }
2113
2114 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2115 {
2116         drm_i915_private_t *dev_priv = dev->dev_private;
2117         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2118
2119         ring->name = "video enhancement ring";
2120         ring->id = VECS;
2121
2122         ring->mmio_base = VEBOX_RING_BASE;
2123         ring->write_tail = ring_write_tail;
2124         ring->flush = gen6_ring_flush;
2125         ring->add_request = gen6_add_request;
2126         ring->get_seqno = gen6_ring_get_seqno;
2127         ring->set_seqno = ring_set_seqno;
2128
2129         if (INTEL_INFO(dev)->gen >= 8) {
2130                 ring->irq_enable_mask =
2131                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2132                 ring->irq_get = gen8_ring_get_irq;
2133                 ring->irq_put = gen8_ring_put_irq;
2134                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2135         } else {
2136                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2137                 ring->irq_get = hsw_vebox_get_irq;
2138                 ring->irq_put = hsw_vebox_put_irq;
2139                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2140         }
2141         ring->sync_to = gen6_ring_sync;
2142         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2143         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2144         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2145         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2146         ring->signal_mbox[RCS] = GEN6_RVESYNC;
2147         ring->signal_mbox[VCS] = GEN6_VVESYNC;
2148         ring->signal_mbox[BCS] = GEN6_BVESYNC;
2149         ring->signal_mbox[VECS] = GEN6_NOSYNC;
2150         ring->init = init_ring_common;
2151
2152         return intel_init_ring_buffer(dev, ring);
2153 }
2154
2155 int
2156 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2157 {
2158         int ret;
2159
2160         if (!ring->gpu_caches_dirty)
2161                 return 0;
2162
2163         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2164         if (ret)
2165                 return ret;
2166
2167         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2168
2169         ring->gpu_caches_dirty = false;
2170         return 0;
2171 }
2172
2173 int
2174 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2175 {
2176         uint32_t flush_domains;
2177         int ret;
2178
2179         flush_domains = 0;
2180         if (ring->gpu_caches_dirty)
2181                 flush_domains = I915_GEM_GPU_DOMAINS;
2182
2183         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2184         if (ret)
2185                 return ret;
2186
2187         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2188
2189         ring->gpu_caches_dirty = false;
2190         return 0;
2191 }