drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - tail;
  56         if (space <= 0)
  57                 space += size;
  58         return space - I915_RING_FREE_SPACE;
  59 }
  60
  61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         if (ringbuf->last_retired_head != -1) {
  64                 ringbuf->head = ringbuf->last_retired_head;
  65                 ringbuf->last_retired_head = -1;
  66         }
  67
  68         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  69                                             ringbuf->tail, ringbuf->size);
  70 }
  71
  72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  73 {
  74         intel_ring_update_space(ringbuf);
  75         return ringbuf->space;
  76 }
  77
  78 bool intel_ring_stopped(struct intel_engine_cs *ring)
  79 {
  80         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  81         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  82 }
  83
  84 static void __intel_ring_advance(struct intel_engine_cs *ring)
  85 {
  86         struct intel_ringbuffer *ringbuf = ring->buffer;
  87         ringbuf->tail &= ringbuf->size - 1;
  88         if (intel_ring_stopped(ring))
  89                 return;
  90         ring->write_tail(ring, ringbuf->tail);
  91 }
  92
  93 static int
  94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  95                        u32      invalidate_domains,
  96                        u32      flush_domains)
  97 {
  98         struct intel_engine_cs *ring = req->ring;
  99         u32 cmd;
 100         int ret;
 101
 102         cmd = MI_FLUSH;
 103         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
 104                 cmd |= MI_NO_WRITE_FLUSH;
 105
 106         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 107                 cmd |= MI_READ_FLUSH;
 108
 109         ret = intel_ring_begin(req, 2);
 110         if (ret)
 111                 return ret;
 112
 113         intel_ring_emit(ring, cmd);
 114         intel_ring_emit(ring, MI_NOOP);
 115         intel_ring_advance(ring);
 116
 117         return 0;
 118 }
 119
 120 static int
 121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 122                        u32      invalidate_domains,
 123                        u32      flush_domains)
 124 {
 125         struct intel_engine_cs *ring = req->ring;
 126         struct drm_device *dev = ring->dev;
 127         u32 cmd;
 128         int ret;
 129
 130         /*
 131          * read/write caches:
 132          *
 133          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 134          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 135          * also flushed at 2d versus 3d pipeline switches.
 136          *
 137          * read-only caches:
 138          *
 139          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 140          * MI_READ_FLUSH is set, and is always flushed on 965.
 141          *
 142          * I915_GEM_DOMAIN_COMMAND may not exist?
 143          *
 144          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 145          * invalidated when MI_EXE_FLUSH is set.
 146          *
 147          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 148          * invalidated with every MI_FLUSH.
 149          *
 150          * TLBs:
 151          *
 152          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 153          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 154          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 155          * are flushed at any MI_FLUSH.
 156          */
 157
 158         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 159         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 160                 cmd &= ~MI_NO_WRITE_FLUSH;
 161         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 162                 cmd |= MI_EXE_FLUSH;
 163
 164         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 165             (IS_G4X(dev) || IS_GEN5(dev)))
 166                 cmd |= MI_INVALIDATE_ISP;
 167
 168         ret = intel_ring_begin(req, 2);
 169         if (ret)
 170                 return ret;
 171
 172         intel_ring_emit(ring, cmd);
 173         intel_ring_emit(ring, MI_NOOP);
 174         intel_ring_advance(ring);
 175
 176         return 0;
 177 }
 178
 179 /**
 180  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 181  * implementing two workarounds on gen6.  From section 1.4.7.1
 182  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 183  *
 184  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 185  * produced by non-pipelined state commands), software needs to first
 186  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 187  * 0.
 188  *
 189  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 190  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 191  *
 192  * And the workaround for these two requires this workaround first:
 193  *
 194  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 195  * BEFORE the pipe-control with a post-sync op and no write-cache
 196  * flushes.
 197  *
 198  * And this last workaround is tricky because of the requirements on
 199  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 200  * volume 2 part 1:
 201  *
 202  *     "1 of the following must also be set:
 203  *      - Render Target Cache Flush Enable ([12] of DW1)
 204  *      - Depth Cache Flush Enable ([0] of DW1)
 205  *      - Stall at Pixel Scoreboard ([1] of DW1)
 206  *      - Depth Stall ([13] of DW1)
 207  *      - Post-Sync Operation ([13] of DW1)
 208  *      - Notify Enable ([8] of DW1)"
 209  *
 210  * The cache flushes require the workaround flush that triggered this
 211  * one, so we can't use it.  Depth stall would trigger the same.
 212  * Post-sync nonzero is what triggered this second workaround, so we
 213  * can't use that one either.  Notify enable is IRQs, which aren't
 214  * really our business.  That leaves only stall at scoreboard.
 215  */
 216 static int
 217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 218 {
 219         struct intel_engine_cs *ring = req->ring;
 220         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 221         int ret;
 222
 223         ret = intel_ring_begin(req, 6);
 224         if (ret)
 225                 return ret;
 226
 227         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 228         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 229                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 230         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 231         intel_ring_emit(ring, 0); /* low dword */
 232         intel_ring_emit(ring, 0); /* high dword */
 233         intel_ring_emit(ring, MI_NOOP);
 234         intel_ring_advance(ring);
 235
 236         ret = intel_ring_begin(req, 6);
 237         if (ret)
 238                 return ret;
 239
 240         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 241         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 242         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 243         intel_ring_emit(ring, 0);
 244         intel_ring_emit(ring, 0);
 245         intel_ring_emit(ring, MI_NOOP);
 246         intel_ring_advance(ring);
 247
 248         return 0;
 249 }
 250
 251 static int
 252 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 253                        u32 invalidate_domains, u32 flush_domains)
 254 {
 255         struct intel_engine_cs *ring = req->ring;
 256         u32 flags = 0;
 257         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 258         int ret;
 259
 260         /* Force SNB workarounds for PIPE_CONTROL flushes */
 261         ret = intel_emit_post_sync_nonzero_flush(req);
 262         if (ret)
 263                 return ret;
 264
 265         /* Just flush everything.  Experiments have shown that reducing the
 266          * number of bits based on the write domains has little performance
 267          * impact.
 268          */
 269         if (flush_domains) {
 270                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 271                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 272                 /*
 273                  * Ensure that any following seqno writes only happen
 274                  * when the render cache is indeed flushed.
 275                  */
 276                 flags |= PIPE_CONTROL_CS_STALL;
 277         }
 278         if (invalidate_domains) {
 279                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 280                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 281                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 282                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 283                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 284                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 285                 /*
 286                  * TLB invalidate requires a post-sync write.
 287                  */
 288                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 289         }
 290
 291         ret = intel_ring_begin(req, 4);
 292         if (ret)
 293                 return ret;
 294
 295         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 296         intel_ring_emit(ring, flags);
 297         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 298         intel_ring_emit(ring, 0);
 299         intel_ring_advance(ring);
 300
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 306 {
 307         struct intel_engine_cs *ring = req->ring;
 308         int ret;
 309
 310         ret = intel_ring_begin(req, 4);
 311         if (ret)
 312                 return ret;
 313
 314         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 315         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 316                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 317         intel_ring_emit(ring, 0);
 318         intel_ring_emit(ring, 0);
 319         intel_ring_advance(ring);
 320
 321         return 0;
 322 }
 323
 324 static int
 325 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 326                        u32 invalidate_domains, u32 flush_domains)
 327 {
 328         struct intel_engine_cs *ring = req->ring;
 329         u32 flags = 0;
 330         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 331         int ret;
 332
 333         /*
 334          * Ensure that any following seqno writes only happen when the render
 335          * cache is indeed flushed.
 336          *
 337          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 338          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 339          * don't try to be clever and just set it unconditionally.
 340          */
 341         flags |= PIPE_CONTROL_CS_STALL;
 342
 343         /* Just flush everything.  Experiments have shown that reducing the
 344          * number of bits based on the write domains has little performance
 345          * impact.
 346          */
 347         if (flush_domains) {
 348                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 349                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 350         }
 351         if (invalidate_domains) {
 352                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 353                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 354                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 355                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 356                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 357                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 358                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 359                 /*
 360                  * TLB invalidate requires a post-sync write.
 361                  */
 362                 flags |= PIPE_CONTROL_QW_WRITE;
 363                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 364
 365                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 366
 367                 /* Workaround: we must issue a pipe_control with CS-stall bit
 368                  * set before a pipe_control command that has the state cache
 369                  * invalidate bit set. */
 370                 gen7_render_ring_cs_stall_wa(req);
 371         }
 372
 373         ret = intel_ring_begin(req, 4);
 374         if (ret)
 375                 return ret;
 376
 377         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 378         intel_ring_emit(ring, flags);
 379         intel_ring_emit(ring, scratch_addr);
 380         intel_ring_emit(ring, 0);
 381         intel_ring_advance(ring);
 382
 383         return 0;
 384 }
 385
 386 static int
 387 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 388                        u32 flags, u32 scratch_addr)
 389 {
 390         struct intel_engine_cs *ring = req->ring;
 391         int ret;
 392
 393         ret = intel_ring_begin(req, 6);
 394         if (ret)
 395                 return ret;
 396
 397         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 398         intel_ring_emit(ring, flags);
 399         intel_ring_emit(ring, scratch_addr);
 400         intel_ring_emit(ring, 0);
 401         intel_ring_emit(ring, 0);
 402         intel_ring_emit(ring, 0);
 403         intel_ring_advance(ring);
 404
 405         return 0;
 406 }
 407
 408 static int
 409 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 410                        u32 invalidate_domains, u32 flush_domains)
 411 {
 412         u32 flags = 0;
 413         u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 414         int ret;
 415
 416         flags |= PIPE_CONTROL_CS_STALL;
 417
 418         if (flush_domains) {
 419                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 420                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 421         }
 422         if (invalidate_domains) {
 423                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 424                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 425                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 426                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 427                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 428                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 429                 flags |= PIPE_CONTROL_QW_WRITE;
 430                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 431
 432                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 433                 ret = gen8_emit_pipe_control(req,
 434                                              PIPE_CONTROL_CS_STALL |
 435                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 436                                              0);
 437                 if (ret)
 438                         return ret;
 439         }
 440
 441         return gen8_emit_pipe_control(req, flags, scratch_addr);
 442 }
 443
 444 static void ring_write_tail(struct intel_engine_cs *ring,
 445                             u32 value)
 446 {
 447         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 448         I915_WRITE_TAIL(ring, value);
 449 }
 450
 451 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 452 {
 453         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 454         u64 acthd;
 455
 456         if (INTEL_INFO(ring->dev)->gen >= 8)
 457                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 458                                          RING_ACTHD_UDW(ring->mmio_base));
 459         else if (INTEL_INFO(ring->dev)->gen >= 4)
 460                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 461         else
 462                 acthd = I915_READ(ACTHD);
 463
 464         return acthd;
 465 }
 466
 467 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 468 {
 469         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 470         u32 addr;
 471
 472         addr = dev_priv->status_page_dmah->busaddr;
 473         if (INTEL_INFO(ring->dev)->gen >= 4)
 474                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 475         I915_WRITE(HWS_PGA, addr);
 476 }
 477
 478 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
 479 {
 480         struct drm_device *dev = ring->dev;
 481         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 482         i915_reg_t mmio;
 483
 484         /* The ring status page addresses are no longer next to the rest of
 485          * the ring registers as of gen7.
 486          */
 487         if (IS_GEN7(dev)) {
 488                 switch (ring->id) {
 489                 case RCS:
 490                         mmio = RENDER_HWS_PGA_GEN7;
 491                         break;
 492                 case BCS:
 493                         mmio = BLT_HWS_PGA_GEN7;
 494                         break;
 495                 /*
 496                  * VCS2 actually doesn't exist on Gen7. Only shut up
 497                  * gcc switch check warning
 498                  */
 499                 case VCS2:
 500                 case VCS:
 501                         mmio = BSD_HWS_PGA_GEN7;
 502                         break;
 503                 case VECS:
 504                         mmio = VEBOX_HWS_PGA_GEN7;
 505                         break;
 506                 }
 507         } else if (IS_GEN6(ring->dev)) {
 508                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 509         } else {
 510                 /* XXX: gen8 returns to sanity */
 511                 mmio = RING_HWS_PGA(ring->mmio_base);
 512         }
 513
 514         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 515         POSTING_READ(mmio);
 516
 517         /*
 518          * Flush the TLB for this page
 519          *
 520          * FIXME: These two bits have disappeared on gen8, so a question
 521          * arises: do we still need this and if so how should we go about
 522          * invalidating the TLB?
 523          */
 524         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 525                 i915_reg_t reg = RING_INSTPM(ring->mmio_base);
 526
 527                 /* ring should be idle before issuing a sync flush*/
 528                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
 529
 530                 I915_WRITE(reg,
 531                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 532                                               INSTPM_SYNC_FLUSH));
 533                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 534                              1000))
 535                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 536                                   ring->name);
 537         }
 538 }
 539
 540 static bool stop_ring(struct intel_engine_cs *ring)
 541 {
 542         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 543
 544         if (!IS_GEN2(ring->dev)) {
 545                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 546                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 547                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 548                         /* Sometimes we observe that the idle flag is not
 549                          * set even though the ring is empty. So double
 550                          * check before giving up.
 551                          */
 552                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 553                                 return false;
 554                 }
 555         }
 556
 557         I915_WRITE_CTL(ring, 0);
 558         I915_WRITE_HEAD(ring, 0);
 559         ring->write_tail(ring, 0);
 560
 561         if (!IS_GEN2(ring->dev)) {
 562                 (void)I915_READ_CTL(ring);
 563                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 564         }
 565
 566         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 567 }
 568
 569 static int init_ring_common(struct intel_engine_cs *ring)
 570 {
 571         struct drm_device *dev = ring->dev;
 572         struct drm_i915_private *dev_priv = dev->dev_private;
 573         struct intel_ringbuffer *ringbuf = ring->buffer;
 574         struct drm_i915_gem_object *obj = ringbuf->obj;
 575         int ret = 0;
 576
 577         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 578
 579         if (!stop_ring(ring)) {
 580                 /* G45 ring initialization often fails to reset head to zero */
 581                 DRM_DEBUG_KMS("%s head not reset to zero "
 582                               "ctl %08x head %08x tail %08x start %08x\n",
 583                               ring->name,
 584                               I915_READ_CTL(ring),
 585                               I915_READ_HEAD(ring),
 586                               I915_READ_TAIL(ring),
 587                               I915_READ_START(ring));
 588
 589                 if (!stop_ring(ring)) {
 590                         DRM_ERROR("failed to set %s head to zero "
 591                                   "ctl %08x head %08x tail %08x start %08x\n",
 592                                   ring->name,
 593                                   I915_READ_CTL(ring),
 594                                   I915_READ_HEAD(ring),
 595                                   I915_READ_TAIL(ring),
 596                                   I915_READ_START(ring));
 597                         ret = -EIO;
 598                         goto out;
 599                 }
 600         }
 601
 602         if (I915_NEED_GFX_HWS(dev))
 603                 intel_ring_setup_status_page(ring);
 604         else
 605                 ring_setup_phys_status_page(ring);
 606
 607         /* Enforce ordering by reading HEAD register back */
 608         I915_READ_HEAD(ring);
 609
 610         /* Initialize the ring. This must happen _after_ we've cleared the ring
 611          * registers with the above sequence (the readback of the HEAD registers
 612          * also enforces ordering), otherwise the hw might lose the new ring
 613          * register values. */
 614         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 615
 616         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 617         if (I915_READ_HEAD(ring))
 618                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 619                           ring->name, I915_READ_HEAD(ring));
 620         I915_WRITE_HEAD(ring, 0);
 621         (void)I915_READ_HEAD(ring);
 622
 623         I915_WRITE_CTL(ring,
 624                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 625                         | RING_VALID);
 626
 627         /* If the head is still not zero, the ring is dead */
 628         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 629                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 630                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 631                 DRM_ERROR("%s initialization failed "
 632                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 633                           ring->name,
 634                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 635                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 636                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 637                 ret = -EIO;
 638                 goto out;
 639         }
 640
 641         ringbuf->last_retired_head = -1;
 642         ringbuf->head = I915_READ_HEAD(ring);
 643         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 644         intel_ring_update_space(ringbuf);
 645
 646         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 647
 648 out:
 649         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 650
 651         return ret;
 652 }
 653
 654 void
 655 intel_fini_pipe_control(struct intel_engine_cs *ring)
 656 {
 657         struct drm_device *dev = ring->dev;
 658
 659         if (ring->scratch.obj == NULL)
 660                 return;
 661
 662         if (INTEL_INFO(dev)->gen >= 5) {
 663                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 664                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 665         }
 666
 667         drm_gem_object_unreference(&ring->scratch.obj->base);
 668         ring->scratch.obj = NULL;
 669 }
 670
 671 int
 672 intel_init_pipe_control(struct intel_engine_cs *ring)
 673 {
 674         int ret;
 675
 676         WARN_ON(ring->scratch.obj);
 677
 678         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 679         if (ring->scratch.obj == NULL) {
 680                 DRM_ERROR("Failed to allocate seqno page\n");
 681                 ret = -ENOMEM;
 682                 goto err;
 683         }
 684
 685         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 686         if (ret)
 687                 goto err_unref;
 688
 689         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 690         if (ret)
 691                 goto err_unref;
 692
 693         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 694         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 695         if (ring->scratch.cpu_page == NULL) {
 696                 ret = -ENOMEM;
 697                 goto err_unpin;
 698         }
 699
 700         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 701                          ring->name, ring->scratch.gtt_offset);
 702         return 0;
 703
 704 err_unpin:
 705         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 706 err_unref:
 707         drm_gem_object_unreference(&ring->scratch.obj->base);
 708 err:
 709         return ret;
 710 }
 711
 712 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 713 {
 714         int ret, i;
 715         struct intel_engine_cs *ring = req->ring;
 716         struct drm_device *dev = ring->dev;
 717         struct drm_i915_private *dev_priv = dev->dev_private;
 718         struct i915_workarounds *w = &dev_priv->workarounds;
 719
 720         if (w->count == 0)
 721                 return 0;
 722
 723         ring->gpu_caches_dirty = true;
 724         ret = intel_ring_flush_all_caches(req);
 725         if (ret)
 726                 return ret;
 727
 728         ret = intel_ring_begin(req, (w->count * 2 + 2));
 729         if (ret)
 730                 return ret;
 731
 732         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 733         for (i = 0; i < w->count; i++) {
 734                 intel_ring_emit_reg(ring, w->reg[i].addr);
 735                 intel_ring_emit(ring, w->reg[i].value);
 736         }
 737         intel_ring_emit(ring, MI_NOOP);
 738
 739         intel_ring_advance(ring);
 740
 741         ring->gpu_caches_dirty = true;
 742         ret = intel_ring_flush_all_caches(req);
 743         if (ret)
 744                 return ret;
 745
 746         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 747
 748         return 0;
 749 }
 750
 751 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 752 {
 753         int ret;
 754
 755         ret = intel_ring_workarounds_emit(req);
 756         if (ret != 0)
 757                 return ret;
 758
 759         ret = i915_gem_render_state_init(req);
 760         if (ret)
 761                 DRM_ERROR("init render state: %d\n", ret);
 762
 763         return ret;
 764 }
 765
 766 static int wa_add(struct drm_i915_private *dev_priv,
 767                   i915_reg_t addr,
 768                   const u32 mask, const u32 val)
 769 {
 770         const u32 idx = dev_priv->workarounds.count;
 771
 772         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 773                 return -ENOSPC;
 774
 775         dev_priv->workarounds.reg[idx].addr = addr;
 776         dev_priv->workarounds.reg[idx].value = val;
 777         dev_priv->workarounds.reg[idx].mask = mask;
 778
 779         dev_priv->workarounds.count++;
 780
 781         return 0;
 782 }
 783
 784 #define WA_REG(addr, mask, val) do { \
 785                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 786                 if (r) \
 787                         return r; \
 788         } while (0)
 789
 790 #define WA_SET_BIT_MASKED(addr, mask) \
 791         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 792
 793 #define WA_CLR_BIT_MASKED(addr, mask) \
 794         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 795
 796 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 797         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 798
 799 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 800 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 801
 802 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 803
 804 static int gen8_init_workarounds(struct intel_engine_cs *ring)
 805 {
 806         struct drm_device *dev = ring->dev;
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808
 809         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 810
 811         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 812         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 813
 814         /* WaDisablePartialInstShootdown:bdw,chv */
 815         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 816                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 817
 818         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 819          * workaround for for a possible hang in the unlikely event a TLB
 820          * invalidation occurs during a PSD flush.
 821          */
 822         /* WaForceEnableNonCoherent:bdw,chv */
 823         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 824         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 825                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 826                           HDC_FORCE_NON_COHERENT);
 827
 828         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 829          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 830          *  polygons in the same 8x4 pixel/sample area to be processed without
 831          *  stalling waiting for the earlier ones to write to Hierarchical Z
 832          *  buffer."
 833          *
 834          * This optimization is off by default for BDW and CHV; turn it on.
 835          */
 836         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 837
 838         /* Wa4x4STCOptimizationDisable:bdw,chv */
 839         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 840
 841         /*
 842          * BSpec recommends 8x4 when MSAA is used,
 843          * however in practice 16x4 seems fastest.
 844          *
 845          * Note that PS/WM thread counts depend on the WIZ hashing
 846          * disable bit, which we don't touch here, but it's good
 847          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 848          */
 849         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 850                             GEN6_WIZ_HASHING_MASK,
 851                             GEN6_WIZ_HASHING_16x4);
 852
 853         return 0;
 854 }
 855
 856 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 857 {
 858         int ret;
 859         struct drm_device *dev = ring->dev;
 860         struct drm_i915_private *dev_priv = dev->dev_private;
 861
 862         ret = gen8_init_workarounds(ring);
 863         if (ret)
 864                 return ret;
 865
 866         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 867         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 868
 869         /* WaDisableDopClockGating:bdw */
 870         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 871                           DOP_CLOCK_GATING_DISABLE);
 872
 873         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 874                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 875
 876         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 877                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 878                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 879                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 880                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 881
 882         return 0;
 883 }
 884
 885 static int chv_init_workarounds(struct intel_engine_cs *ring)
 886 {
 887         int ret;
 888         struct drm_device *dev = ring->dev;
 889         struct drm_i915_private *dev_priv = dev->dev_private;
 890
 891         ret = gen8_init_workarounds(ring);
 892         if (ret)
 893                 return ret;
 894
 895         /* WaDisableThreadStallDopClockGating:chv */
 896         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 897
 898         /* Improve HiZ throughput on CHV. */
 899         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 900
 901         return 0;
 902 }
 903
 904 static int gen9_init_workarounds(struct intel_engine_cs *ring)
 905 {
 906         struct drm_device *dev = ring->dev;
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908         uint32_t tmp;
 909
 910         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 911         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 912                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 913
 914         /* WaDisableKillLogic:bxt,skl */
 915         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 916                    ECOCHK_DIS_TLB);
 917
 918         /* WaDisablePartialInstShootdown:skl,bxt */
 919         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 920                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 921
 922         /* Syncing dependencies between camera and graphics:skl,bxt */
 923         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 924                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 925
 926         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 927         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 928             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 929                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 930                                   GEN9_DG_MIRROR_FIX_ENABLE);
 931
 932         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 933         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 934             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 935                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 936                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 937                 /*
 938                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 939                  * but we do that in per ctx batchbuffer as there is an issue
 940                  * with this register not getting restored on ctx restore
 941                  */
 942         }
 943
 944         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 945         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
 946                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 947                                   GEN9_ENABLE_YV12_BUGFIX);
 948
 949         /* Wa4x4STCOptimizationDisable:skl,bxt */
 950         /* WaDisablePartialResolveInVc:skl,bxt */
 951         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 952                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 953
 954         /* WaCcsTlbPrefetchDisable:skl,bxt */
 955         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 956                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 957
 958         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 959         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 960             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 961                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 962                                   PIXEL_MASK_CAMMING_DISABLE);
 963
 964         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 965         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 966         if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
 967             IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
 968                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 969         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 970
 971         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 972         if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 973                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 974                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 975
 976         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 977         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 978
 979         return 0;
 980 }
 981
 982 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 983 {
 984         struct drm_device *dev = ring->dev;
 985         struct drm_i915_private *dev_priv = dev->dev_private;
 986         u8 vals[3] = { 0, 0, 0 };
 987         unsigned int i;
 988
 989         for (i = 0; i < 3; i++) {
 990                 u8 ss;
 991
 992                 /*
 993                  * Only consider slices where one, and only one, subslice has 7
 994                  * EUs
 995                  */
 996                 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
 997                         continue;
 998
 999                 /*
1000                  * subslice_7eu[i] != 0 (because of the check above) and
1001                  * ss_max == 4 (maximum number of subslices possible per slice)
1002                  *
1003                  * ->    0 <= ss <= 3;
1004                  */
1005                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1006                 vals[i] = 3 - ss;
1007         }
1008
1009         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1010                 return 0;
1011
1012         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1013         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1014                             GEN9_IZ_HASHING_MASK(2) |
1015                             GEN9_IZ_HASHING_MASK(1) |
1016                             GEN9_IZ_HASHING_MASK(0),
1017                             GEN9_IZ_HASHING(2, vals[2]) |
1018                             GEN9_IZ_HASHING(1, vals[1]) |
1019                             GEN9_IZ_HASHING(0, vals[0]));
1020
1021         return 0;
1022 }
1023
1024 static int skl_init_workarounds(struct intel_engine_cs *ring)
1025 {
1026         int ret;
1027         struct drm_device *dev = ring->dev;
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029
1030         ret = gen9_init_workarounds(ring);
1031         if (ret)
1032                 return ret;
1033
1034         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1035                 /* WaDisableHDCInvalidation:skl */
1036                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1037                            BDW_DISABLE_HDC_INVALIDATION);
1038
1039                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1040                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1041                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1042         }
1043
1044         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1045          * involving this register should also be added to WA batch as required.
1046          */
1047         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1048                 /* WaDisableLSQCROPERFforOCL:skl */
1049                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1050                            GEN8_LQSC_RO_PERF_DIS);
1051
1052         /* WaEnableGapsTsvCreditFix:skl */
1053         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1054                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1055                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1056         }
1057
1058         /* WaDisablePowerCompilerClockGating:skl */
1059         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1060                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1061                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1062
1063         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1064                 /*
1065                  *Use Force Non-Coherent whenever executing a 3D context. This
1066                  * is a workaround for a possible hang in the unlikely event
1067                  * a TLB invalidation occurs during a PSD flush.
1068                  */
1069                 /* WaForceEnableNonCoherent:skl */
1070                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1071                                   HDC_FORCE_NON_COHERENT);
1072         }
1073
1074         /* WaBarrierPerformanceFixDisable:skl */
1075         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1076                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1077                                   HDC_FENCE_DEST_SLM_DISABLE |
1078                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1079
1080         /* WaDisableSbeCacheDispatchPortSharing:skl */
1081         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1082                 WA_SET_BIT_MASKED(
1083                         GEN7_HALF_SLICE_CHICKEN1,
1084                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1085
1086         return skl_tune_iz_hashing(ring);
1087 }
1088
1089 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1090 {
1091         int ret;
1092         struct drm_device *dev = ring->dev;
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094
1095         ret = gen9_init_workarounds(ring);
1096         if (ret)
1097                 return ret;
1098
1099         /* WaStoreMultiplePTEenable:bxt */
1100         /* This is a requirement according to Hardware specification */
1101         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1102                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1103
1104         /* WaSetClckGatingDisableMedia:bxt */
1105         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1106                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1107                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1108         }
1109
1110         /* WaDisableThreadStallDopClockGating:bxt */
1111         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1112                           STALL_DOP_GATING_DISABLE);
1113
1114         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1115         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1116                 WA_SET_BIT_MASKED(
1117                         GEN7_HALF_SLICE_CHICKEN1,
1118                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1119         }
1120
1121         return 0;
1122 }
1123
1124 int init_workarounds_ring(struct intel_engine_cs *ring)
1125 {
1126         struct drm_device *dev = ring->dev;
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129         WARN_ON(ring->id != RCS);
1130
1131         dev_priv->workarounds.count = 0;
1132
1133         if (IS_BROADWELL(dev))
1134                 return bdw_init_workarounds(ring);
1135
1136         if (IS_CHERRYVIEW(dev))
1137                 return chv_init_workarounds(ring);
1138
1139         if (IS_SKYLAKE(dev))
1140                 return skl_init_workarounds(ring);
1141
1142         if (IS_BROXTON(dev))
1143                 return bxt_init_workarounds(ring);
1144
1145         return 0;
1146 }
1147
1148 static int init_render_ring(struct intel_engine_cs *ring)
1149 {
1150         struct drm_device *dev = ring->dev;
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         int ret = init_ring_common(ring);
1153         if (ret)
1154                 return ret;
1155
1156         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1157         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1158                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1159
1160         /* We need to disable the AsyncFlip performance optimisations in order
1161          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1162          * programmed to '1' on all products.
1163          *
1164          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1165          */
1166         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1167                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1168
1169         /* Required for the hardware to program scanline values for waiting */
1170         /* WaEnableFlushTlbInvalidationMode:snb */
1171         if (INTEL_INFO(dev)->gen == 6)
1172                 I915_WRITE(GFX_MODE,
1173                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1174
1175         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1176         if (IS_GEN7(dev))
1177                 I915_WRITE(GFX_MODE_GEN7,
1178                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1179                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1180
1181         if (IS_GEN6(dev)) {
1182                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1183                  * "If this bit is set, STCunit will have LRA as replacement
1184                  *  policy. [...] This bit must be reset.  LRA replacement
1185                  *  policy is not supported."
1186                  */
1187                 I915_WRITE(CACHE_MODE_0,
1188                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1189         }
1190
1191         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1192                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1193
1194         if (HAS_L3_DPF(dev))
1195                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1196
1197         return init_workarounds_ring(ring);
1198 }
1199
1200 static void render_ring_cleanup(struct intel_engine_cs *ring)
1201 {
1202         struct drm_device *dev = ring->dev;
1203         struct drm_i915_private *dev_priv = dev->dev_private;
1204
1205         if (dev_priv->semaphore_obj) {
1206                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1207                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1208                 dev_priv->semaphore_obj = NULL;
1209         }
1210
1211         intel_fini_pipe_control(ring);
1212 }
1213
1214 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1215                            unsigned int num_dwords)
1216 {
1217 #define MBOX_UPDATE_DWORDS 8
1218         struct intel_engine_cs *signaller = signaller_req->ring;
1219         struct drm_device *dev = signaller->dev;
1220         struct drm_i915_private *dev_priv = dev->dev_private;
1221         struct intel_engine_cs *waiter;
1222         int i, ret, num_rings;
1223
1224         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1225         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1226 #undef MBOX_UPDATE_DWORDS
1227
1228         ret = intel_ring_begin(signaller_req, num_dwords);
1229         if (ret)
1230                 return ret;
1231
1232         for_each_ring(waiter, dev_priv, i) {
1233                 u32 seqno;
1234                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1235                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1236                         continue;
1237
1238                 seqno = i915_gem_request_get_seqno(signaller_req);
1239                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1240                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1241                                            PIPE_CONTROL_QW_WRITE |
1242                                            PIPE_CONTROL_FLUSH_ENABLE);
1243                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1244                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1245                 intel_ring_emit(signaller, seqno);
1246                 intel_ring_emit(signaller, 0);
1247                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1248                                            MI_SEMAPHORE_TARGET(waiter->id));
1249                 intel_ring_emit(signaller, 0);
1250         }
1251
1252         return 0;
1253 }
1254
1255 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1256                            unsigned int num_dwords)
1257 {
1258 #define MBOX_UPDATE_DWORDS 6
1259         struct intel_engine_cs *signaller = signaller_req->ring;
1260         struct drm_device *dev = signaller->dev;
1261         struct drm_i915_private *dev_priv = dev->dev_private;
1262         struct intel_engine_cs *waiter;
1263         int i, ret, num_rings;
1264
1265         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1266         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1267 #undef MBOX_UPDATE_DWORDS
1268
1269         ret = intel_ring_begin(signaller_req, num_dwords);
1270         if (ret)
1271                 return ret;
1272
1273         for_each_ring(waiter, dev_priv, i) {
1274                 u32 seqno;
1275                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1276                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1277                         continue;
1278
1279                 seqno = i915_gem_request_get_seqno(signaller_req);
1280                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1281                                            MI_FLUSH_DW_OP_STOREDW);
1282                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1283                                            MI_FLUSH_DW_USE_GTT);
1284                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1285                 intel_ring_emit(signaller, seqno);
1286                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1287                                            MI_SEMAPHORE_TARGET(waiter->id));
1288                 intel_ring_emit(signaller, 0);
1289         }
1290
1291         return 0;
1292 }
1293
1294 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1295                        unsigned int num_dwords)
1296 {
1297         struct intel_engine_cs *signaller = signaller_req->ring;
1298         struct drm_device *dev = signaller->dev;
1299         struct drm_i915_private *dev_priv = dev->dev_private;
1300         struct intel_engine_cs *useless;
1301         int i, ret, num_rings;
1302
1303 #define MBOX_UPDATE_DWORDS 3
1304         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1305         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1306 #undef MBOX_UPDATE_DWORDS
1307
1308         ret = intel_ring_begin(signaller_req, num_dwords);
1309         if (ret)
1310                 return ret;
1311
1312         for_each_ring(useless, dev_priv, i) {
1313                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
1314
1315                 if (i915_mmio_reg_valid(mbox_reg)) {
1316                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1317
1318                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1319                         intel_ring_emit_reg(signaller, mbox_reg);
1320                         intel_ring_emit(signaller, seqno);
1321                 }
1322         }
1323
1324         /* If num_dwords was rounded, make sure the tail pointer is correct */
1325         if (num_rings % 2 == 0)
1326                 intel_ring_emit(signaller, MI_NOOP);
1327
1328         return 0;
1329 }
1330
1331 /**
1332  * gen6_add_request - Update the semaphore mailbox registers
1333  *
1334  * @request - request to write to the ring
1335  *
1336  * Update the mailbox registers in the *other* rings with the current seqno.
1337  * This acts like a signal in the canonical semaphore.
1338  */
1339 static int
1340 gen6_add_request(struct drm_i915_gem_request *req)
1341 {
1342         struct intel_engine_cs *ring = req->ring;
1343         int ret;
1344
1345         if (ring->semaphore.signal)
1346                 ret = ring->semaphore.signal(req, 4);
1347         else
1348                 ret = intel_ring_begin(req, 4);
1349
1350         if (ret)
1351                 return ret;
1352
1353         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1354         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1355         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1356         intel_ring_emit(ring, MI_USER_INTERRUPT);
1357         __intel_ring_advance(ring);
1358
1359         return 0;
1360 }
1361
1362 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1363                                               u32 seqno)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366         return dev_priv->last_seqno < seqno;
1367 }
1368
1369 /**
1370  * intel_ring_sync - sync the waiter to the signaller on seqno
1371  *
1372  * @waiter - ring that is waiting
1373  * @signaller - ring which has, or will signal
1374  * @seqno - seqno which the waiter will block on
1375  */
1376
1377 static int
1378 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1379                struct intel_engine_cs *signaller,
1380                u32 seqno)
1381 {
1382         struct intel_engine_cs *waiter = waiter_req->ring;
1383         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1384         int ret;
1385
1386         ret = intel_ring_begin(waiter_req, 4);
1387         if (ret)
1388                 return ret;
1389
1390         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1391                                 MI_SEMAPHORE_GLOBAL_GTT |
1392                                 MI_SEMAPHORE_POLL |
1393                                 MI_SEMAPHORE_SAD_GTE_SDD);
1394         intel_ring_emit(waiter, seqno);
1395         intel_ring_emit(waiter,
1396                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1397         intel_ring_emit(waiter,
1398                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1399         intel_ring_advance(waiter);
1400         return 0;
1401 }
1402
1403 static int
1404 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1405                struct intel_engine_cs *signaller,
1406                u32 seqno)
1407 {
1408         struct intel_engine_cs *waiter = waiter_req->ring;
1409         u32 dw1 = MI_SEMAPHORE_MBOX |
1410                   MI_SEMAPHORE_COMPARE |
1411                   MI_SEMAPHORE_REGISTER;
1412         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1413         int ret;
1414
1415         /* Throughout all of the GEM code, seqno passed implies our current
1416          * seqno is >= the last seqno executed. However for hardware the
1417          * comparison is strictly greater than.
1418          */
1419         seqno -= 1;
1420
1421         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1422
1423         ret = intel_ring_begin(waiter_req, 4);
1424         if (ret)
1425                 return ret;
1426
1427         /* If seqno wrap happened, omit the wait with no-ops */
1428         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1429                 intel_ring_emit(waiter, dw1 | wait_mbox);
1430                 intel_ring_emit(waiter, seqno);
1431                 intel_ring_emit(waiter, 0);
1432                 intel_ring_emit(waiter, MI_NOOP);
1433         } else {
1434                 intel_ring_emit(waiter, MI_NOOP);
1435                 intel_ring_emit(waiter, MI_NOOP);
1436                 intel_ring_emit(waiter, MI_NOOP);
1437                 intel_ring_emit(waiter, MI_NOOP);
1438         }
1439         intel_ring_advance(waiter);
1440
1441         return 0;
1442 }
1443
1444 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1445 do {                                                                    \
1446         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1447                  PIPE_CONTROL_DEPTH_STALL);                             \
1448         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1449         intel_ring_emit(ring__, 0);                                                     \
1450         intel_ring_emit(ring__, 0);                                                     \
1451 } while (0)
1452
1453 static int
1454 pc_render_add_request(struct drm_i915_gem_request *req)
1455 {
1456         struct intel_engine_cs *ring = req->ring;
1457         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1458         int ret;
1459
1460         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1461          * incoherent with writes to memory, i.e. completely fubar,
1462          * so we need to use PIPE_NOTIFY instead.
1463          *
1464          * However, we also need to workaround the qword write
1465          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1466          * memory before requesting an interrupt.
1467          */
1468         ret = intel_ring_begin(req, 32);
1469         if (ret)
1470                 return ret;
1471
1472         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1473                         PIPE_CONTROL_WRITE_FLUSH |
1474                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1475         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1476         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1477         intel_ring_emit(ring, 0);
1478         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1479         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1480         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1481         scratch_addr += 2 * CACHELINE_BYTES;
1482         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1483         scratch_addr += 2 * CACHELINE_BYTES;
1484         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1485         scratch_addr += 2 * CACHELINE_BYTES;
1486         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1487         scratch_addr += 2 * CACHELINE_BYTES;
1488         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1489
1490         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1491                         PIPE_CONTROL_WRITE_FLUSH |
1492                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1493                         PIPE_CONTROL_NOTIFY);
1494         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1495         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1496         intel_ring_emit(ring, 0);
1497         __intel_ring_advance(ring);
1498
1499         return 0;
1500 }
1501
1502 static u32
1503 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1504 {
1505         /* Workaround to force correct ordering between irq and seqno writes on
1506          * ivb (and maybe also on snb) by reading from a CS register (like
1507          * ACTHD) before reading the status page. */
1508         if (!lazy_coherency) {
1509                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1510                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1511         }
1512
1513         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1514 }
1515
1516 static u32
1517 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1518 {
1519         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1520 }
1521
1522 static void
1523 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1524 {
1525         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1526 }
1527
1528 static u32
1529 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1530 {
1531         return ring->scratch.cpu_page[0];
1532 }
1533
1534 static void
1535 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1536 {
1537         ring->scratch.cpu_page[0] = seqno;
1538 }
1539
1540 static bool
1541 gen5_ring_get_irq(struct intel_engine_cs *ring)
1542 {
1543         struct drm_device *dev = ring->dev;
1544         struct drm_i915_private *dev_priv = dev->dev_private;
1545         unsigned long flags;
1546
1547         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1548                 return false;
1549
1550         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1551         if (ring->irq_refcount++ == 0)
1552                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1553         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1554
1555         return true;
1556 }
1557
1558 static void
1559 gen5_ring_put_irq(struct intel_engine_cs *ring)
1560 {
1561         struct drm_device *dev = ring->dev;
1562         struct drm_i915_private *dev_priv = dev->dev_private;
1563         unsigned long flags;
1564
1565         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1566         if (--ring->irq_refcount == 0)
1567                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1568         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1569 }
1570
1571 static bool
1572 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1573 {
1574         struct drm_device *dev = ring->dev;
1575         struct drm_i915_private *dev_priv = dev->dev_private;
1576         unsigned long flags;
1577
1578         if (!intel_irqs_enabled(dev_priv))
1579                 return false;
1580
1581         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1582         if (ring->irq_refcount++ == 0) {
1583                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1584                 I915_WRITE(IMR, dev_priv->irq_mask);
1585                 POSTING_READ(IMR);
1586         }
1587         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1588
1589         return true;
1590 }
1591
1592 static void
1593 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1594 {
1595         struct drm_device *dev = ring->dev;
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597         unsigned long flags;
1598
1599         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1600         if (--ring->irq_refcount == 0) {
1601                 dev_priv->irq_mask |= ring->irq_enable_mask;
1602                 I915_WRITE(IMR, dev_priv->irq_mask);
1603                 POSTING_READ(IMR);
1604         }
1605         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1606 }
1607
1608 static bool
1609 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1610 {
1611         struct drm_device *dev = ring->dev;
1612         struct drm_i915_private *dev_priv = dev->dev_private;
1613         unsigned long flags;
1614
1615         if (!intel_irqs_enabled(dev_priv))
1616                 return false;
1617
1618         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1619         if (ring->irq_refcount++ == 0) {
1620                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1621                 I915_WRITE16(IMR, dev_priv->irq_mask);
1622                 POSTING_READ16(IMR);
1623         }
1624         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1625
1626         return true;
1627 }
1628
1629 static void
1630 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1631 {
1632         struct drm_device *dev = ring->dev;
1633         struct drm_i915_private *dev_priv = dev->dev_private;
1634         unsigned long flags;
1635
1636         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1637         if (--ring->irq_refcount == 0) {
1638                 dev_priv->irq_mask |= ring->irq_enable_mask;
1639                 I915_WRITE16(IMR, dev_priv->irq_mask);
1640                 POSTING_READ16(IMR);
1641         }
1642         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1643 }
1644
1645 static int
1646 bsd_ring_flush(struct drm_i915_gem_request *req,
1647                u32     invalidate_domains,
1648                u32     flush_domains)
1649 {
1650         struct intel_engine_cs *ring = req->ring;
1651         int ret;
1652
1653         ret = intel_ring_begin(req, 2);
1654         if (ret)
1655                 return ret;
1656
1657         intel_ring_emit(ring, MI_FLUSH);
1658         intel_ring_emit(ring, MI_NOOP);
1659         intel_ring_advance(ring);
1660         return 0;
1661 }
1662
1663 static int
1664 i9xx_add_request(struct drm_i915_gem_request *req)
1665 {
1666         struct intel_engine_cs *ring = req->ring;
1667         int ret;
1668
1669         ret = intel_ring_begin(req, 4);
1670         if (ret)
1671                 return ret;
1672
1673         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1674         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1675         intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1676         intel_ring_emit(ring, MI_USER_INTERRUPT);
1677         __intel_ring_advance(ring);
1678
1679         return 0;
1680 }
1681
1682 static bool
1683 gen6_ring_get_irq(struct intel_engine_cs *ring)
1684 {
1685         struct drm_device *dev = ring->dev;
1686         struct drm_i915_private *dev_priv = dev->dev_private;
1687         unsigned long flags;
1688
1689         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1690                 return false;
1691
1692         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1693         if (ring->irq_refcount++ == 0) {
1694                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1695                         I915_WRITE_IMR(ring,
1696                                        ~(ring->irq_enable_mask |
1697                                          GT_PARITY_ERROR(dev)));
1698                 else
1699                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1700                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1701         }
1702         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1703
1704         return true;
1705 }
1706
1707 static void
1708 gen6_ring_put_irq(struct intel_engine_cs *ring)
1709 {
1710         struct drm_device *dev = ring->dev;
1711         struct drm_i915_private *dev_priv = dev->dev_private;
1712         unsigned long flags;
1713
1714         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1715         if (--ring->irq_refcount == 0) {
1716                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1717                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1718                 else
1719                         I915_WRITE_IMR(ring, ~0);
1720                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1721         }
1722         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1723 }
1724
1725 static bool
1726 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1727 {
1728         struct drm_device *dev = ring->dev;
1729         struct drm_i915_private *dev_priv = dev->dev_private;
1730         unsigned long flags;
1731
1732         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1733                 return false;
1734
1735         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1736         if (ring->irq_refcount++ == 0) {
1737                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1738                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1739         }
1740         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1741
1742         return true;
1743 }
1744
1745 static void
1746 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1747 {
1748         struct drm_device *dev = ring->dev;
1749         struct drm_i915_private *dev_priv = dev->dev_private;
1750         unsigned long flags;
1751
1752         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1753         if (--ring->irq_refcount == 0) {
1754                 I915_WRITE_IMR(ring, ~0);
1755                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1756         }
1757         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1758 }
1759
1760 static bool
1761 gen8_ring_get_irq(struct intel_engine_cs *ring)
1762 {
1763         struct drm_device *dev = ring->dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765         unsigned long flags;
1766
1767         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1768                 return false;
1769
1770         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1771         if (ring->irq_refcount++ == 0) {
1772                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1773                         I915_WRITE_IMR(ring,
1774                                        ~(ring->irq_enable_mask |
1775                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1776                 } else {
1777                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1778                 }
1779                 POSTING_READ(RING_IMR(ring->mmio_base));
1780         }
1781         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1782
1783         return true;
1784 }
1785
1786 static void
1787 gen8_ring_put_irq(struct intel_engine_cs *ring)
1788 {
1789         struct drm_device *dev = ring->dev;
1790         struct drm_i915_private *dev_priv = dev->dev_private;
1791         unsigned long flags;
1792
1793         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1794         if (--ring->irq_refcount == 0) {
1795                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1796                         I915_WRITE_IMR(ring,
1797                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1798                 } else {
1799                         I915_WRITE_IMR(ring, ~0);
1800                 }
1801                 POSTING_READ(RING_IMR(ring->mmio_base));
1802         }
1803         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1804 }
1805
1806 static int
1807 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1808                          u64 offset, u32 length,
1809                          unsigned dispatch_flags)
1810 {
1811         struct intel_engine_cs *ring = req->ring;
1812         int ret;
1813
1814         ret = intel_ring_begin(req, 2);
1815         if (ret)
1816                 return ret;
1817
1818         intel_ring_emit(ring,
1819                         MI_BATCH_BUFFER_START |
1820                         MI_BATCH_GTT |
1821                         (dispatch_flags & I915_DISPATCH_SECURE ?
1822                          0 : MI_BATCH_NON_SECURE_I965));
1823         intel_ring_emit(ring, offset);
1824         intel_ring_advance(ring);
1825
1826         return 0;
1827 }
1828
1829 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1830 #define I830_BATCH_LIMIT (256*1024)
1831 #define I830_TLB_ENTRIES (2)
1832 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1833 static int
1834 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1835                          u64 offset, u32 len,
1836                          unsigned dispatch_flags)
1837 {
1838         struct intel_engine_cs *ring = req->ring;
1839         u32 cs_offset = ring->scratch.gtt_offset;
1840         int ret;
1841
1842         ret = intel_ring_begin(req, 6);
1843         if (ret)
1844                 return ret;
1845
1846         /* Evict the invalid PTE TLBs */
1847         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1848         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1849         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1850         intel_ring_emit(ring, cs_offset);
1851         intel_ring_emit(ring, 0xdeadbeef);
1852         intel_ring_emit(ring, MI_NOOP);
1853         intel_ring_advance(ring);
1854
1855         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1856                 if (len > I830_BATCH_LIMIT)
1857                         return -ENOSPC;
1858
1859                 ret = intel_ring_begin(req, 6 + 2);
1860                 if (ret)
1861                         return ret;
1862
1863                 /* Blit the batch (which has now all relocs applied) to the
1864                  * stable batch scratch bo area (so that the CS never
1865                  * stumbles over its tlb invalidation bug) ...
1866                  */
1867                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1868                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1869                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1870                 intel_ring_emit(ring, cs_offset);
1871                 intel_ring_emit(ring, 4096);
1872                 intel_ring_emit(ring, offset);
1873
1874                 intel_ring_emit(ring, MI_FLUSH);
1875                 intel_ring_emit(ring, MI_NOOP);
1876                 intel_ring_advance(ring);
1877
1878                 /* ... and execute it. */
1879                 offset = cs_offset;
1880         }
1881
1882         ret = intel_ring_begin(req, 4);
1883         if (ret)
1884                 return ret;
1885
1886         intel_ring_emit(ring, MI_BATCH_BUFFER);
1887         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1888                                         0 : MI_BATCH_NON_SECURE));
1889         intel_ring_emit(ring, offset + len - 8);
1890         intel_ring_emit(ring, MI_NOOP);
1891         intel_ring_advance(ring);
1892
1893         return 0;
1894 }
1895
1896 static int
1897 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1898                          u64 offset, u32 len,
1899                          unsigned dispatch_flags)
1900 {
1901         struct intel_engine_cs *ring = req->ring;
1902         int ret;
1903
1904         ret = intel_ring_begin(req, 2);
1905         if (ret)
1906                 return ret;
1907
1908         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1909         intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1910                                         0 : MI_BATCH_NON_SECURE));
1911         intel_ring_advance(ring);
1912
1913         return 0;
1914 }
1915
1916 static void cleanup_status_page(struct intel_engine_cs *ring)
1917 {
1918         struct drm_i915_gem_object *obj;
1919
1920         obj = ring->status_page.obj;
1921         if (obj == NULL)
1922                 return;
1923
1924         kunmap(sg_page(obj->pages->sgl));
1925         i915_gem_object_ggtt_unpin(obj);
1926         drm_gem_object_unreference(&obj->base);
1927         ring->status_page.obj = NULL;
1928 }
1929
1930 static int init_status_page(struct intel_engine_cs *ring)
1931 {
1932         struct drm_i915_gem_object *obj;
1933
1934         if ((obj = ring->status_page.obj) == NULL) {
1935                 unsigned flags;
1936                 int ret;
1937
1938                 obj = i915_gem_alloc_object(ring->dev, 4096);
1939                 if (obj == NULL) {
1940                         DRM_ERROR("Failed to allocate status page\n");
1941                         return -ENOMEM;
1942                 }
1943
1944                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1945                 if (ret)
1946                         goto err_unref;
1947
1948                 flags = 0;
1949                 if (!HAS_LLC(ring->dev))
1950                         /* On g33, we cannot place HWS above 256MiB, so
1951                          * restrict its pinning to the low mappable arena.
1952                          * Though this restriction is not documented for
1953                          * gen4, gen5, or byt, they also behave similarly
1954                          * and hang if the HWS is placed at the top of the
1955                          * GTT. To generalise, it appears that all !llc
1956                          * platforms have issues with us placing the HWS
1957                          * above the mappable region (even though we never
1958                          * actualy map it).
1959                          */
1960                         flags |= PIN_MAPPABLE;
1961                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1962                 if (ret) {
1963 err_unref:
1964                         drm_gem_object_unreference(&obj->base);
1965                         return ret;
1966                 }
1967
1968                 ring->status_page.obj = obj;
1969         }
1970
1971         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1972         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1973         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1974
1975         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1976                         ring->name, ring->status_page.gfx_addr);
1977
1978         return 0;
1979 }
1980
1981 static int init_phys_status_page(struct intel_engine_cs *ring)
1982 {
1983         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1984
1985         if (!dev_priv->status_page_dmah) {
1986                 dev_priv->status_page_dmah =
1987                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1988                 if (!dev_priv->status_page_dmah)
1989                         return -ENOMEM;
1990         }
1991
1992         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1993         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1994
1995         return 0;
1996 }
1997
1998 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1999 {
2000         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2001                 vunmap(ringbuf->virtual_start);
2002         else
2003                 iounmap(ringbuf->virtual_start);
2004         ringbuf->virtual_start = NULL;
2005         i915_gem_object_ggtt_unpin(ringbuf->obj);
2006 }
2007
2008 static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2009 {
2010         struct sg_page_iter sg_iter;
2011         struct page **pages;
2012         void *addr;
2013         int i;
2014
2015         pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2016         if (pages == NULL)
2017                 return NULL;
2018
2019         i = 0;
2020         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2021                 pages[i++] = sg_page_iter_page(&sg_iter);
2022
2023         addr = vmap(pages, i, 0, PAGE_KERNEL);
2024         drm_free_large(pages);
2025
2026         return addr;
2027 }
2028
2029 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2030                                      struct intel_ringbuffer *ringbuf)
2031 {
2032         struct drm_i915_private *dev_priv = to_i915(dev);
2033         struct drm_i915_gem_object *obj = ringbuf->obj;
2034         int ret;
2035
2036         if (HAS_LLC(dev_priv) && !obj->stolen) {
2037                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2038                 if (ret)
2039                         return ret;
2040
2041                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2042                 if (ret) {
2043                         i915_gem_object_ggtt_unpin(obj);
2044                         return ret;
2045                 }
2046
2047                 ringbuf->virtual_start = vmap_obj(obj);
2048                 if (ringbuf->virtual_start == NULL) {
2049                         i915_gem_object_ggtt_unpin(obj);
2050                         return -ENOMEM;
2051                 }
2052         } else {
2053                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2054                 if (ret)
2055                         return ret;
2056
2057                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2058                 if (ret) {
2059                         i915_gem_object_ggtt_unpin(obj);
2060                         return ret;
2061                 }
2062
2063                 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2064                                                     i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2065                 if (ringbuf->virtual_start == NULL) {
2066                         i915_gem_object_ggtt_unpin(obj);
2067                         return -EINVAL;
2068                 }
2069         }
2070
2071         return 0;
2072 }
2073
2074 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2075 {
2076         drm_gem_object_unreference(&ringbuf->obj->base);
2077         ringbuf->obj = NULL;
2078 }
2079
2080 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2081                                       struct intel_ringbuffer *ringbuf)
2082 {
2083         struct drm_i915_gem_object *obj;
2084
2085         obj = NULL;
2086         if (!HAS_LLC(dev))
2087                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2088         if (obj == NULL)
2089                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2090         if (obj == NULL)
2091                 return -ENOMEM;
2092
2093         /* mark ring buffers as read-only from GPU side by default */
2094         obj->gt_ro = 1;
2095
2096         ringbuf->obj = obj;
2097
2098         return 0;
2099 }
2100
2101 struct intel_ringbuffer *
2102 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2103 {
2104         struct intel_ringbuffer *ring;
2105         int ret;
2106
2107         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2108         if (ring == NULL) {
2109                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2110                                  engine->name);
2111                 return ERR_PTR(-ENOMEM);
2112         }
2113
2114         ring->ring = engine;
2115         list_add(&ring->link, &engine->buffers);
2116
2117         ring->size = size;
2118         /* Workaround an erratum on the i830 which causes a hang if
2119          * the TAIL pointer points to within the last 2 cachelines
2120          * of the buffer.
2121          */
2122         ring->effective_size = size;
2123         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2124                 ring->effective_size -= 2 * CACHELINE_BYTES;
2125
2126         ring->last_retired_head = -1;
2127         intel_ring_update_space(ring);
2128
2129         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2130         if (ret) {
2131                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2132                                  engine->name, ret);
2133                 list_del(&ring->link);
2134                 kfree(ring);
2135                 return ERR_PTR(ret);
2136         }
2137
2138         return ring;
2139 }
2140
2141 void
2142 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2143 {
2144         intel_destroy_ringbuffer_obj(ring);
2145         list_del(&ring->link);
2146         kfree(ring);
2147 }
2148
2149 static int intel_init_ring_buffer(struct drm_device *dev,
2150                                   struct intel_engine_cs *ring)
2151 {
2152         struct intel_ringbuffer *ringbuf;
2153         int ret;
2154
2155         WARN_ON(ring->buffer);
2156
2157         ring->dev = dev;
2158         INIT_LIST_HEAD(&ring->active_list);
2159         INIT_LIST_HEAD(&ring->request_list);
2160         INIT_LIST_HEAD(&ring->execlist_queue);
2161         INIT_LIST_HEAD(&ring->buffers);
2162         i915_gem_batch_pool_init(dev, &ring->batch_pool);
2163         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2164
2165         init_waitqueue_head(&ring->irq_queue);
2166
2167         ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2168         if (IS_ERR(ringbuf))
2169                 return PTR_ERR(ringbuf);
2170         ring->buffer = ringbuf;
2171
2172         if (I915_NEED_GFX_HWS(dev)) {
2173                 ret = init_status_page(ring);
2174                 if (ret)
2175                         goto error;
2176         } else {
2177                 BUG_ON(ring->id != RCS);
2178                 ret = init_phys_status_page(ring);
2179                 if (ret)
2180                         goto error;
2181         }
2182
2183         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2184         if (ret) {
2185                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2186                                 ring->name, ret);
2187                 intel_destroy_ringbuffer_obj(ringbuf);
2188                 goto error;
2189         }
2190
2191         ret = i915_cmd_parser_init_ring(ring);
2192         if (ret)
2193                 goto error;
2194
2195         return 0;
2196
2197 error:
2198         intel_ringbuffer_free(ringbuf);
2199         ring->buffer = NULL;
2200         return ret;
2201 }
2202
2203 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2204 {
2205         struct drm_i915_private *dev_priv;
2206
2207         if (!intel_ring_initialized(ring))
2208                 return;
2209
2210         dev_priv = to_i915(ring->dev);
2211
2212         intel_stop_ring_buffer(ring);
2213         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2214
2215         intel_unpin_ringbuffer_obj(ring->buffer);
2216         intel_ringbuffer_free(ring->buffer);
2217         ring->buffer = NULL;
2218
2219         if (ring->cleanup)
2220                 ring->cleanup(ring);
2221
2222         cleanup_status_page(ring);
2223
2224         i915_cmd_parser_fini_ring(ring);
2225         i915_gem_batch_pool_fini(&ring->batch_pool);
2226 }
2227
2228 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2229 {
2230         struct intel_ringbuffer *ringbuf = ring->buffer;
2231         struct drm_i915_gem_request *request;
2232         unsigned space;
2233         int ret;
2234
2235         if (intel_ring_space(ringbuf) >= n)
2236                 return 0;
2237
2238         /* The whole point of reserving space is to not wait! */
2239         WARN_ON(ringbuf->reserved_in_use);
2240
2241         list_for_each_entry(request, &ring->request_list, list) {
2242                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2243                                            ringbuf->size);
2244                 if (space >= n)
2245                         break;
2246         }
2247
2248         if (WARN_ON(&request->list == &ring->request_list))
2249                 return -ENOSPC;
2250
2251         ret = i915_wait_request(request);
2252         if (ret)
2253                 return ret;
2254
2255         ringbuf->space = space;
2256         return 0;
2257 }
2258
2259 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2260 {
2261         uint32_t __iomem *virt;
2262         int rem = ringbuf->size - ringbuf->tail;
2263
2264         virt = ringbuf->virtual_start + ringbuf->tail;
2265         rem /= 4;
2266         while (rem--)
2267                 iowrite32(MI_NOOP, virt++);
2268
2269         ringbuf->tail = 0;
2270         intel_ring_update_space(ringbuf);
2271 }
2272
2273 int intel_ring_idle(struct intel_engine_cs *ring)
2274 {
2275         struct drm_i915_gem_request *req;
2276
2277         /* Wait upon the last request to be completed */
2278         if (list_empty(&ring->request_list))
2279                 return 0;
2280
2281         req = list_entry(ring->request_list.prev,
2282                         struct drm_i915_gem_request,
2283                         list);
2284
2285         /* Make sure we do not trigger any retires */
2286         return __i915_wait_request(req,
2287                                    atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2288                                    to_i915(ring->dev)->mm.interruptible,
2289                                    NULL, NULL);
2290 }
2291
2292 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2293 {
2294         request->ringbuf = request->ring->buffer;
2295         return 0;
2296 }
2297
2298 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2299 {
2300         /*
2301          * The first call merely notes the reserve request and is common for
2302          * all back ends. The subsequent localised _begin() call actually
2303          * ensures that the reservation is available. Without the begin, if
2304          * the request creator immediately submitted the request without
2305          * adding any commands to it then there might not actually be
2306          * sufficient room for the submission commands.
2307          */
2308         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2309
2310         return intel_ring_begin(request, 0);
2311 }
2312
2313 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2314 {
2315         WARN_ON(ringbuf->reserved_size);
2316         WARN_ON(ringbuf->reserved_in_use);
2317
2318         ringbuf->reserved_size = size;
2319 }
2320
2321 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2322 {
2323         WARN_ON(ringbuf->reserved_in_use);
2324
2325         ringbuf->reserved_size   = 0;
2326         ringbuf->reserved_in_use = false;
2327 }
2328
2329 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2330 {
2331         WARN_ON(ringbuf->reserved_in_use);
2332
2333         ringbuf->reserved_in_use = true;
2334         ringbuf->reserved_tail   = ringbuf->tail;
2335 }
2336
2337 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2338 {
2339         WARN_ON(!ringbuf->reserved_in_use);
2340         if (ringbuf->tail > ringbuf->reserved_tail) {
2341                 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2342                      "request reserved size too small: %d vs %d!\n",
2343                      ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2344         } else {
2345                 /*
2346                  * The ring was wrapped while the reserved space was in use.
2347                  * That means that some unknown amount of the ring tail was
2348                  * no-op filled and skipped. Thus simply adding the ring size
2349                  * to the tail and doing the above space check will not work.
2350                  * Rather than attempt to track how much tail was skipped,
2351                  * it is much simpler to say that also skipping the sanity
2352                  * check every once in a while is not a big issue.
2353                  */
2354         }
2355
2356         ringbuf->reserved_size   = 0;
2357         ringbuf->reserved_in_use = false;
2358 }
2359
2360 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2361 {
2362         struct intel_ringbuffer *ringbuf = ring->buffer;
2363         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2364         int remain_actual = ringbuf->size - ringbuf->tail;
2365         int ret, total_bytes, wait_bytes = 0;
2366         bool need_wrap = false;
2367
2368         if (ringbuf->reserved_in_use)
2369                 total_bytes = bytes;
2370         else
2371                 total_bytes = bytes + ringbuf->reserved_size;
2372
2373         if (unlikely(bytes > remain_usable)) {
2374                 /*
2375                  * Not enough space for the basic request. So need to flush
2376                  * out the remainder and then wait for base + reserved.
2377                  */
2378                 wait_bytes = remain_actual + total_bytes;
2379                 need_wrap = true;
2380         } else {
2381                 if (unlikely(total_bytes > remain_usable)) {
2382                         /*
2383                          * The base request will fit but the reserved space
2384                          * falls off the end. So only need to to wait for the
2385                          * reserved size after flushing out the remainder.
2386                          */
2387                         wait_bytes = remain_actual + ringbuf->reserved_size;
2388                         need_wrap = true;
2389                 } else if (total_bytes > ringbuf->space) {
2390                         /* No wrapping required, just waiting. */
2391                         wait_bytes = total_bytes;
2392                 }
2393         }
2394
2395         if (wait_bytes) {
2396                 ret = ring_wait_for_space(ring, wait_bytes);
2397                 if (unlikely(ret))
2398                         return ret;
2399
2400                 if (need_wrap)
2401                         __wrap_ring_buffer(ringbuf);
2402         }
2403
2404         return 0;
2405 }
2406
2407 int intel_ring_begin(struct drm_i915_gem_request *req,
2408                      int num_dwords)
2409 {
2410         struct intel_engine_cs *ring;
2411         struct drm_i915_private *dev_priv;
2412         int ret;
2413
2414         WARN_ON(req == NULL);
2415         ring = req->ring;
2416         dev_priv = ring->dev->dev_private;
2417
2418         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2419                                    dev_priv->mm.interruptible);
2420         if (ret)
2421                 return ret;
2422
2423         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2424         if (ret)
2425                 return ret;
2426
2427         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2428         return 0;
2429 }
2430
2431 /* Align the ring tail to a cacheline boundary */
2432 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2433 {
2434         struct intel_engine_cs *ring = req->ring;
2435         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2436         int ret;
2437
2438         if (num_dwords == 0)
2439                 return 0;
2440
2441         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2442         ret = intel_ring_begin(req, num_dwords);
2443         if (ret)
2444                 return ret;
2445
2446         while (num_dwords--)
2447                 intel_ring_emit(ring, MI_NOOP);
2448
2449         intel_ring_advance(ring);
2450
2451         return 0;
2452 }
2453
2454 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2455 {
2456         struct drm_device *dev = ring->dev;
2457         struct drm_i915_private *dev_priv = dev->dev_private;
2458
2459         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2460                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2461                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2462                 if (HAS_VEBOX(dev))
2463                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2464         }
2465
2466         ring->set_seqno(ring, seqno);
2467         ring->hangcheck.seqno = seqno;
2468 }
2469
2470 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2471                                      u32 value)
2472 {
2473         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2474
2475        /* Every tail move must follow the sequence below */
2476
2477         /* Disable notification that the ring is IDLE. The GT
2478          * will then assume that it is busy and bring it out of rc6.
2479          */
2480         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2481                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2482
2483         /* Clear the context id. Here be magic! */
2484         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2485
2486         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2487         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2488                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2489                      50))
2490                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2491
2492         /* Now that the ring is fully powered up, update the tail */
2493         I915_WRITE_TAIL(ring, value);
2494         POSTING_READ(RING_TAIL(ring->mmio_base));
2495
2496         /* Let the ring send IDLE messages to the GT again,
2497          * and so let it sleep to conserve power when idle.
2498          */
2499         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2500                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2501 }
2502
2503 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2504                                u32 invalidate, u32 flush)
2505 {
2506         struct intel_engine_cs *ring = req->ring;
2507         uint32_t cmd;
2508         int ret;
2509
2510         ret = intel_ring_begin(req, 4);
2511         if (ret)
2512                 return ret;
2513
2514         cmd = MI_FLUSH_DW;
2515         if (INTEL_INFO(ring->dev)->gen >= 8)
2516                 cmd += 1;
2517
2518         /* We always require a command barrier so that subsequent
2519          * commands, such as breadcrumb interrupts, are strictly ordered
2520          * wrt the contents of the write cache being flushed to memory
2521          * (and thus being coherent from the CPU).
2522          */
2523         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2524
2525         /*
2526          * Bspec vol 1c.5 - video engine command streamer:
2527          * "If ENABLED, all TLBs will be invalidated once the flush
2528          * operation is complete. This bit is only valid when the
2529          * Post-Sync Operation field is a value of 1h or 3h."
2530          */
2531         if (invalidate & I915_GEM_GPU_DOMAINS)
2532                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2533
2534         intel_ring_emit(ring, cmd);
2535         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2536         if (INTEL_INFO(ring->dev)->gen >= 8) {
2537                 intel_ring_emit(ring, 0); /* upper addr */
2538                 intel_ring_emit(ring, 0); /* value */
2539         } else  {
2540                 intel_ring_emit(ring, 0);
2541                 intel_ring_emit(ring, MI_NOOP);
2542         }
2543         intel_ring_advance(ring);
2544         return 0;
2545 }
2546
2547 static int
2548 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2549                               u64 offset, u32 len,
2550                               unsigned dispatch_flags)
2551 {
2552         struct intel_engine_cs *ring = req->ring;
2553         bool ppgtt = USES_PPGTT(ring->dev) &&
2554                         !(dispatch_flags & I915_DISPATCH_SECURE);
2555         int ret;
2556
2557         ret = intel_ring_begin(req, 4);
2558         if (ret)
2559                 return ret;
2560
2561         /* FIXME(BDW): Address space and security selectors. */
2562         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2563                         (dispatch_flags & I915_DISPATCH_RS ?
2564                          MI_BATCH_RESOURCE_STREAMER : 0));
2565         intel_ring_emit(ring, lower_32_bits(offset));
2566         intel_ring_emit(ring, upper_32_bits(offset));
2567         intel_ring_emit(ring, MI_NOOP);
2568         intel_ring_advance(ring);
2569
2570         return 0;
2571 }
2572
2573 static int
2574 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2575                              u64 offset, u32 len,
2576                              unsigned dispatch_flags)
2577 {
2578         struct intel_engine_cs *ring = req->ring;
2579         int ret;
2580
2581         ret = intel_ring_begin(req, 2);
2582         if (ret)
2583                 return ret;
2584
2585         intel_ring_emit(ring,
2586                         MI_BATCH_BUFFER_START |
2587                         (dispatch_flags & I915_DISPATCH_SECURE ?
2588                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2589                         (dispatch_flags & I915_DISPATCH_RS ?
2590                          MI_BATCH_RESOURCE_STREAMER : 0));
2591         /* bit0-7 is the length on GEN6+ */
2592         intel_ring_emit(ring, offset);
2593         intel_ring_advance(ring);
2594
2595         return 0;
2596 }
2597
2598 static int
2599 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2600                               u64 offset, u32 len,
2601                               unsigned dispatch_flags)
2602 {
2603         struct intel_engine_cs *ring = req->ring;
2604         int ret;
2605
2606         ret = intel_ring_begin(req, 2);
2607         if (ret)
2608                 return ret;
2609
2610         intel_ring_emit(ring,
2611                         MI_BATCH_BUFFER_START |
2612                         (dispatch_flags & I915_DISPATCH_SECURE ?
2613                          0 : MI_BATCH_NON_SECURE_I965));
2614         /* bit0-7 is the length on GEN6+ */
2615         intel_ring_emit(ring, offset);
2616         intel_ring_advance(ring);
2617
2618         return 0;
2619 }
2620
2621 /* Blitter support (SandyBridge+) */
2622
2623 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2624                            u32 invalidate, u32 flush)
2625 {
2626         struct intel_engine_cs *ring = req->ring;
2627         struct drm_device *dev = ring->dev;
2628         uint32_t cmd;
2629         int ret;
2630
2631         ret = intel_ring_begin(req, 4);
2632         if (ret)
2633                 return ret;
2634
2635         cmd = MI_FLUSH_DW;
2636         if (INTEL_INFO(dev)->gen >= 8)
2637                 cmd += 1;
2638
2639         /* We always require a command barrier so that subsequent
2640          * commands, such as breadcrumb interrupts, are strictly ordered
2641          * wrt the contents of the write cache being flushed to memory
2642          * (and thus being coherent from the CPU).
2643          */
2644         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2645
2646         /*
2647          * Bspec vol 1c.3 - blitter engine command streamer:
2648          * "If ENABLED, all TLBs will be invalidated once the flush
2649          * operation is complete. This bit is only valid when the
2650          * Post-Sync Operation field is a value of 1h or 3h."
2651          */
2652         if (invalidate & I915_GEM_DOMAIN_RENDER)
2653                 cmd |= MI_INVALIDATE_TLB;
2654         intel_ring_emit(ring, cmd);
2655         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2656         if (INTEL_INFO(dev)->gen >= 8) {
2657                 intel_ring_emit(ring, 0); /* upper addr */
2658                 intel_ring_emit(ring, 0); /* value */
2659         } else  {
2660                 intel_ring_emit(ring, 0);
2661                 intel_ring_emit(ring, MI_NOOP);
2662         }
2663         intel_ring_advance(ring);
2664
2665         return 0;
2666 }
2667
2668 int intel_init_render_ring_buffer(struct drm_device *dev)
2669 {
2670         struct drm_i915_private *dev_priv = dev->dev_private;
2671         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2672         struct drm_i915_gem_object *obj;
2673         int ret;
2674
2675         ring->name = "render ring";
2676         ring->id = RCS;
2677         ring->mmio_base = RENDER_RING_BASE;
2678
2679         if (INTEL_INFO(dev)->gen >= 8) {
2680                 if (i915_semaphore_is_enabled(dev)) {
2681                         obj = i915_gem_alloc_object(dev, 4096);
2682                         if (obj == NULL) {
2683                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2684                                 i915.semaphores = 0;
2685                         } else {
2686                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2687                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2688                                 if (ret != 0) {
2689                                         drm_gem_object_unreference(&obj->base);
2690                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2691                                         i915.semaphores = 0;
2692                                 } else
2693                                         dev_priv->semaphore_obj = obj;
2694                         }
2695                 }
2696
2697                 ring->init_context = intel_rcs_ctx_init;
2698                 ring->add_request = gen6_add_request;
2699                 ring->flush = gen8_render_ring_flush;
2700                 ring->irq_get = gen8_ring_get_irq;
2701                 ring->irq_put = gen8_ring_put_irq;
2702                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2703                 ring->get_seqno = gen6_ring_get_seqno;
2704                 ring->set_seqno = ring_set_seqno;
2705                 if (i915_semaphore_is_enabled(dev)) {
2706                         WARN_ON(!dev_priv->semaphore_obj);
2707                         ring->semaphore.sync_to = gen8_ring_sync;
2708                         ring->semaphore.signal = gen8_rcs_signal;
2709                         GEN8_RING_SEMAPHORE_INIT;
2710                 }
2711         } else if (INTEL_INFO(dev)->gen >= 6) {
2712                 ring->init_context = intel_rcs_ctx_init;
2713                 ring->add_request = gen6_add_request;
2714                 ring->flush = gen7_render_ring_flush;
2715                 if (INTEL_INFO(dev)->gen == 6)
2716                         ring->flush = gen6_render_ring_flush;
2717                 ring->irq_get = gen6_ring_get_irq;
2718                 ring->irq_put = gen6_ring_put_irq;
2719                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2720                 ring->get_seqno = gen6_ring_get_seqno;
2721                 ring->set_seqno = ring_set_seqno;
2722                 if (i915_semaphore_is_enabled(dev)) {
2723                         ring->semaphore.sync_to = gen6_ring_sync;
2724                         ring->semaphore.signal = gen6_signal;
2725                         /*
2726                          * The current semaphore is only applied on pre-gen8
2727                          * platform.  And there is no VCS2 ring on the pre-gen8
2728                          * platform. So the semaphore between RCS and VCS2 is
2729                          * initialized as INVALID.  Gen8 will initialize the
2730                          * sema between VCS2 and RCS later.
2731                          */
2732                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2733                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2734                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2735                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2736                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2737                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2738                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2739                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2740                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2741                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2742                 }
2743         } else if (IS_GEN5(dev)) {
2744                 ring->add_request = pc_render_add_request;
2745                 ring->flush = gen4_render_ring_flush;
2746                 ring->get_seqno = pc_render_get_seqno;
2747                 ring->set_seqno = pc_render_set_seqno;
2748                 ring->irq_get = gen5_ring_get_irq;
2749                 ring->irq_put = gen5_ring_put_irq;
2750                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2751                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2752         } else {
2753                 ring->add_request = i9xx_add_request;
2754                 if (INTEL_INFO(dev)->gen < 4)
2755                         ring->flush = gen2_render_ring_flush;
2756                 else
2757                         ring->flush = gen4_render_ring_flush;
2758                 ring->get_seqno = ring_get_seqno;
2759                 ring->set_seqno = ring_set_seqno;
2760                 if (IS_GEN2(dev)) {
2761                         ring->irq_get = i8xx_ring_get_irq;
2762                         ring->irq_put = i8xx_ring_put_irq;
2763                 } else {
2764                         ring->irq_get = i9xx_ring_get_irq;
2765                         ring->irq_put = i9xx_ring_put_irq;
2766                 }
2767                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2768         }
2769         ring->write_tail = ring_write_tail;
2770
2771         if (IS_HASWELL(dev))
2772                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2773         else if (IS_GEN8(dev))
2774                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2775         else if (INTEL_INFO(dev)->gen >= 6)
2776                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2777         else if (INTEL_INFO(dev)->gen >= 4)
2778                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2779         else if (IS_I830(dev) || IS_845G(dev))
2780                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2781         else
2782                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2783         ring->init_hw = init_render_ring;
2784         ring->cleanup = render_ring_cleanup;
2785
2786         /* Workaround batchbuffer to combat CS tlb bug. */
2787         if (HAS_BROKEN_CS_TLB(dev)) {
2788                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2789                 if (obj == NULL) {
2790                         DRM_ERROR("Failed to allocate batch bo\n");
2791                         return -ENOMEM;
2792                 }
2793
2794                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2795                 if (ret != 0) {
2796                         drm_gem_object_unreference(&obj->base);
2797                         DRM_ERROR("Failed to ping batch bo\n");
2798                         return ret;
2799                 }
2800
2801                 ring->scratch.obj = obj;
2802                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2803         }
2804
2805         ret = intel_init_ring_buffer(dev, ring);
2806         if (ret)
2807                 return ret;
2808
2809         if (INTEL_INFO(dev)->gen >= 5) {
2810                 ret = intel_init_pipe_control(ring);
2811                 if (ret)
2812                         return ret;
2813         }
2814
2815         return 0;
2816 }
2817
2818 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2819 {
2820         struct drm_i915_private *dev_priv = dev->dev_private;
2821         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2822
2823         ring->name = "bsd ring";
2824         ring->id = VCS;
2825
2826         ring->write_tail = ring_write_tail;
2827         if (INTEL_INFO(dev)->gen >= 6) {
2828                 ring->mmio_base = GEN6_BSD_RING_BASE;
2829                 /* gen6 bsd needs a special wa for tail updates */
2830                 if (IS_GEN6(dev))
2831                         ring->write_tail = gen6_bsd_ring_write_tail;
2832                 ring->flush = gen6_bsd_ring_flush;
2833                 ring->add_request = gen6_add_request;
2834                 ring->get_seqno = gen6_ring_get_seqno;
2835                 ring->set_seqno = ring_set_seqno;
2836                 if (INTEL_INFO(dev)->gen >= 8) {
2837                         ring->irq_enable_mask =
2838                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2839                         ring->irq_get = gen8_ring_get_irq;
2840                         ring->irq_put = gen8_ring_put_irq;
2841                         ring->dispatch_execbuffer =
2842                                 gen8_ring_dispatch_execbuffer;
2843                         if (i915_semaphore_is_enabled(dev)) {
2844                                 ring->semaphore.sync_to = gen8_ring_sync;
2845                                 ring->semaphore.signal = gen8_xcs_signal;
2846                                 GEN8_RING_SEMAPHORE_INIT;
2847                         }
2848                 } else {
2849                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2850                         ring->irq_get = gen6_ring_get_irq;
2851                         ring->irq_put = gen6_ring_put_irq;
2852                         ring->dispatch_execbuffer =
2853                                 gen6_ring_dispatch_execbuffer;
2854                         if (i915_semaphore_is_enabled(dev)) {
2855                                 ring->semaphore.sync_to = gen6_ring_sync;
2856                                 ring->semaphore.signal = gen6_signal;
2857                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2858                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2859                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2860                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2861                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2862                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2863                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2864                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2865                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2866                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2867                         }
2868                 }
2869         } else {
2870                 ring->mmio_base = BSD_RING_BASE;
2871                 ring->flush = bsd_ring_flush;
2872                 ring->add_request = i9xx_add_request;
2873                 ring->get_seqno = ring_get_seqno;
2874                 ring->set_seqno = ring_set_seqno;
2875                 if (IS_GEN5(dev)) {
2876                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2877                         ring->irq_get = gen5_ring_get_irq;
2878                         ring->irq_put = gen5_ring_put_irq;
2879                 } else {
2880                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2881                         ring->irq_get = i9xx_ring_get_irq;
2882                         ring->irq_put = i9xx_ring_put_irq;
2883                 }
2884                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2885         }
2886         ring->init_hw = init_ring_common;
2887
2888         return intel_init_ring_buffer(dev, ring);
2889 }
2890
2891 /**
2892  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2893  */
2894 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2895 {
2896         struct drm_i915_private *dev_priv = dev->dev_private;
2897         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2898
2899         ring->name = "bsd2 ring";
2900         ring->id = VCS2;
2901
2902         ring->write_tail = ring_write_tail;
2903         ring->mmio_base = GEN8_BSD2_RING_BASE;
2904         ring->flush = gen6_bsd_ring_flush;
2905         ring->add_request = gen6_add_request;
2906         ring->get_seqno = gen6_ring_get_seqno;
2907         ring->set_seqno = ring_set_seqno;
2908         ring->irq_enable_mask =
2909                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2910         ring->irq_get = gen8_ring_get_irq;
2911         ring->irq_put = gen8_ring_put_irq;
2912         ring->dispatch_execbuffer =
2913                         gen8_ring_dispatch_execbuffer;
2914         if (i915_semaphore_is_enabled(dev)) {
2915                 ring->semaphore.sync_to = gen8_ring_sync;
2916                 ring->semaphore.signal = gen8_xcs_signal;
2917                 GEN8_RING_SEMAPHORE_INIT;
2918         }
2919         ring->init_hw = init_ring_common;
2920
2921         return intel_init_ring_buffer(dev, ring);
2922 }
2923
2924 int intel_init_blt_ring_buffer(struct drm_device *dev)
2925 {
2926         struct drm_i915_private *dev_priv = dev->dev_private;
2927         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2928
2929         ring->name = "blitter ring";
2930         ring->id = BCS;
2931
2932         ring->mmio_base = BLT_RING_BASE;
2933         ring->write_tail = ring_write_tail;
2934         ring->flush = gen6_ring_flush;
2935         ring->add_request = gen6_add_request;
2936         ring->get_seqno = gen6_ring_get_seqno;
2937         ring->set_seqno = ring_set_seqno;
2938         if (INTEL_INFO(dev)->gen >= 8) {
2939                 ring->irq_enable_mask =
2940                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2941                 ring->irq_get = gen8_ring_get_irq;
2942                 ring->irq_put = gen8_ring_put_irq;
2943                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2944                 if (i915_semaphore_is_enabled(dev)) {
2945                         ring->semaphore.sync_to = gen8_ring_sync;
2946                         ring->semaphore.signal = gen8_xcs_signal;
2947                         GEN8_RING_SEMAPHORE_INIT;
2948                 }
2949         } else {
2950                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2951                 ring->irq_get = gen6_ring_get_irq;
2952                 ring->irq_put = gen6_ring_put_irq;
2953                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2954                 if (i915_semaphore_is_enabled(dev)) {
2955                         ring->semaphore.signal = gen6_signal;
2956                         ring->semaphore.sync_to = gen6_ring_sync;
2957                         /*
2958                          * The current semaphore is only applied on pre-gen8
2959                          * platform.  And there is no VCS2 ring on the pre-gen8
2960                          * platform. So the semaphore between BCS and VCS2 is
2961                          * initialized as INVALID.  Gen8 will initialize the
2962                          * sema between BCS and VCS2 later.
2963                          */
2964                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2965                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2966                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2967                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2968                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2969                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2970                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2971                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2972                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2973                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2974                 }
2975         }
2976         ring->init_hw = init_ring_common;
2977
2978         return intel_init_ring_buffer(dev, ring);
2979 }
2980
2981 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2982 {
2983         struct drm_i915_private *dev_priv = dev->dev_private;
2984         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2985
2986         ring->name = "video enhancement ring";
2987         ring->id = VECS;
2988
2989         ring->mmio_base = VEBOX_RING_BASE;
2990         ring->write_tail = ring_write_tail;
2991         ring->flush = gen6_ring_flush;
2992         ring->add_request = gen6_add_request;
2993         ring->get_seqno = gen6_ring_get_seqno;
2994         ring->set_seqno = ring_set_seqno;
2995
2996         if (INTEL_INFO(dev)->gen >= 8) {
2997                 ring->irq_enable_mask =
2998                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2999                 ring->irq_get = gen8_ring_get_irq;
3000                 ring->irq_put = gen8_ring_put_irq;
3001                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3002                 if (i915_semaphore_is_enabled(dev)) {
3003                         ring->semaphore.sync_to = gen8_ring_sync;
3004                         ring->semaphore.signal = gen8_xcs_signal;
3005                         GEN8_RING_SEMAPHORE_INIT;
3006                 }
3007         } else {
3008                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3009                 ring->irq_get = hsw_vebox_get_irq;
3010                 ring->irq_put = hsw_vebox_put_irq;
3011                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3012                 if (i915_semaphore_is_enabled(dev)) {
3013                         ring->semaphore.sync_to = gen6_ring_sync;
3014                         ring->semaphore.signal = gen6_signal;
3015                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3016                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3017                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3018                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3019                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3020                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3021                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3022                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3023                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3024                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3025                 }
3026         }
3027         ring->init_hw = init_ring_common;
3028
3029         return intel_init_ring_buffer(dev, ring);
3030 }
3031
3032 int
3033 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3034 {
3035         struct intel_engine_cs *ring = req->ring;
3036         int ret;
3037
3038         if (!ring->gpu_caches_dirty)
3039                 return 0;
3040
3041         ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
3042         if (ret)
3043                 return ret;
3044
3045         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3046
3047         ring->gpu_caches_dirty = false;
3048         return 0;
3049 }
3050
3051 int
3052 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3053 {
3054         struct intel_engine_cs *ring = req->ring;
3055         uint32_t flush_domains;
3056         int ret;
3057
3058         flush_domains = 0;
3059         if (ring->gpu_caches_dirty)
3060                 flush_domains = I915_GEM_GPU_DOMAINS;
3061
3062         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3063         if (ret)
3064                 return ret;
3065
3066         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3067
3068         ring->gpu_caches_dirty = false;
3069         return 0;
3070 }
3071
3072 void
3073 intel_stop_ring_buffer(struct intel_engine_cs *ring)
3074 {
3075         int ret;
3076
3077         if (!intel_ring_initialized(ring))
3078                 return;
3079
3080         ret = intel_ring_idle(ring);
3081         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3082                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3083                           ring->name, ret);
3084
3085         stop_ring(ring);
3086 }