drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 static u32 i915_gem_get_seqno(struct drm_device *dev)
  38 {
  39         drm_i915_private_t *dev_priv = dev->dev_private;
  40         u32 seqno;
  41
  42         seqno = dev_priv->next_seqno;
  43
  44         /* reserve 0 for non-seqno */
  45         if (++dev_priv->next_seqno == 0)
  46                 dev_priv->next_seqno = 1;
  47
  48         return seqno;
  49 }
  50
  51 static void
  52 render_ring_flush(struct intel_ring_buffer *ring,
  53                   u32   invalidate_domains,
  54                   u32   flush_domains)
  55 {
  56         struct drm_device *dev = ring->dev;
  57         drm_i915_private_t *dev_priv = dev->dev_private;
  58         u32 cmd;
  59
  60 #if WATCH_EXEC
  61         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
  62                   invalidate_domains, flush_domains);
  63 #endif
  64
  65         trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
  66                                      invalidate_domains, flush_domains);
  67
  68         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
  69                 /*
  70                  * read/write caches:
  71                  *
  72                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  73                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  74                  * also flushed at 2d versus 3d pipeline switches.
  75                  *
  76                  * read-only caches:
  77                  *
  78                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  79                  * MI_READ_FLUSH is set, and is always flushed on 965.
  80                  *
  81                  * I915_GEM_DOMAIN_COMMAND may not exist?
  82                  *
  83                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  84                  * invalidated when MI_EXE_FLUSH is set.
  85                  *
  86                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  87                  * invalidated with every MI_FLUSH.
  88                  *
  89                  * TLBs:
  90                  *
  91                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  92                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  93                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  94                  * are flushed at any MI_FLUSH.
  95                  */
  96
  97                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  98                 if ((invalidate_domains|flush_domains) &
  99                     I915_GEM_DOMAIN_RENDER)
 100                         cmd &= ~MI_NO_WRITE_FLUSH;
 101                 if (INTEL_INFO(dev)->gen < 4) {
 102                         /*
 103                          * On the 965, the sampler cache always gets flushed
 104                          * and this bit is reserved.
 105                          */
 106                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 107                                 cmd |= MI_READ_FLUSH;
 108                 }
 109                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 110                         cmd |= MI_EXE_FLUSH;
 111
 112                 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 113                     (IS_G4X(dev) || IS_GEN5(dev)))
 114                         cmd |= MI_INVALIDATE_ISP;
 115
 116 #if WATCH_EXEC
 117                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 118 #endif
 119                 if (intel_ring_begin(ring, 2) == 0) {
 120                         intel_ring_emit(ring, cmd);
 121                         intel_ring_emit(ring, MI_NOOP);
 122                         intel_ring_advance(ring);
 123                 }
 124         }
 125 }
 126
 127 static void ring_write_tail(struct intel_ring_buffer *ring,
 128                             u32 value)
 129 {
 130         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 131         I915_WRITE_TAIL(ring, value);
 132 }
 133
 134 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 135 {
 136         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 137         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 138                         RING_ACTHD(ring->mmio_base) : ACTHD;
 139
 140         return I915_READ(acthd_reg);
 141 }
 142
 143 static int init_ring_common(struct intel_ring_buffer *ring)
 144 {
 145         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 146         struct drm_i915_gem_object *obj = ring->obj;
 147         u32 head;
 148
 149         /* Stop the ring if it's running. */
 150         I915_WRITE_CTL(ring, 0);
 151         I915_WRITE_HEAD(ring, 0);
 152         ring->write_tail(ring, 0);
 153
 154         /* Initialize the ring. */
 155         I915_WRITE_START(ring, obj->gtt_offset);
 156         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 157
 158         /* G45 ring initialization fails to reset head to zero */
 159         if (head != 0) {
 160                 DRM_DEBUG_KMS("%s head not reset to zero "
 161                               "ctl %08x head %08x tail %08x start %08x\n",
 162                               ring->name,
 163                               I915_READ_CTL(ring),
 164                               I915_READ_HEAD(ring),
 165                               I915_READ_TAIL(ring),
 166                               I915_READ_START(ring));
 167
 168                 I915_WRITE_HEAD(ring, 0);
 169
 170                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 171                         DRM_ERROR("failed to set %s head to zero "
 172                                   "ctl %08x head %08x tail %08x start %08x\n",
 173                                   ring->name,
 174                                   I915_READ_CTL(ring),
 175                                   I915_READ_HEAD(ring),
 176                                   I915_READ_TAIL(ring),
 177                                   I915_READ_START(ring));
 178                 }
 179         }
 180
 181         I915_WRITE_CTL(ring,
 182                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 183                         | RING_REPORT_64K | RING_VALID);
 184
 185         /* If the head is still not zero, the ring is dead */
 186         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 187             I915_READ_START(ring) != obj->gtt_offset ||
 188             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 189                 DRM_ERROR("%s initialization failed "
 190                                 "ctl %08x head %08x tail %08x start %08x\n",
 191                                 ring->name,
 192                                 I915_READ_CTL(ring),
 193                                 I915_READ_HEAD(ring),
 194                                 I915_READ_TAIL(ring),
 195                                 I915_READ_START(ring));
 196                 return -EIO;
 197         }
 198
 199         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 200                 i915_kernel_lost_context(ring->dev);
 201         else {
 202                 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 203                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 204                 ring->space = ring->head - (ring->tail + 8);
 205                 if (ring->space < 0)
 206                         ring->space += ring->size;
 207         }
 208
 209         return 0;
 210 }
 211
 212 /*
 213  * 965+ support PIPE_CONTROL commands, which provide finer grained control
 214  * over cache flushing.
 215  */
 216 struct pipe_control {
 217         struct drm_i915_gem_object *obj;
 218         volatile u32 *cpu_page;
 219         u32 gtt_offset;
 220 };
 221
 222 static int
 223 init_pipe_control(struct intel_ring_buffer *ring)
 224 {
 225         struct pipe_control *pc;
 226         struct drm_i915_gem_object *obj;
 227         int ret;
 228
 229         if (ring->private)
 230                 return 0;
 231
 232         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 233         if (!pc)
 234                 return -ENOMEM;
 235
 236         obj = i915_gem_alloc_object(ring->dev, 4096);
 237         if (obj == NULL) {
 238                 DRM_ERROR("Failed to allocate seqno page\n");
 239                 ret = -ENOMEM;
 240                 goto err;
 241         }
 242         obj->agp_type = AGP_USER_CACHED_MEMORY;
 243
 244         ret = i915_gem_object_pin(obj, 4096, true);
 245         if (ret)
 246                 goto err_unref;
 247
 248         pc->gtt_offset = obj->gtt_offset;
 249         pc->cpu_page =  kmap(obj->pages[0]);
 250         if (pc->cpu_page == NULL)
 251                 goto err_unpin;
 252
 253         pc->obj = obj;
 254         ring->private = pc;
 255         return 0;
 256
 257 err_unpin:
 258         i915_gem_object_unpin(obj);
 259 err_unref:
 260         drm_gem_object_unreference(&obj->base);
 261 err:
 262         kfree(pc);
 263         return ret;
 264 }
 265
 266 static void
 267 cleanup_pipe_control(struct intel_ring_buffer *ring)
 268 {
 269         struct pipe_control *pc = ring->private;
 270         struct drm_i915_gem_object *obj;
 271
 272         if (!ring->private)
 273                 return;
 274
 275         obj = pc->obj;
 276         kunmap(obj->pages[0]);
 277         i915_gem_object_unpin(obj);
 278         drm_gem_object_unreference(&obj->base);
 279
 280         kfree(pc);
 281         ring->private = NULL;
 282 }
 283
 284 static int init_render_ring(struct intel_ring_buffer *ring)
 285 {
 286         struct drm_device *dev = ring->dev;
 287         struct drm_i915_private *dev_priv = dev->dev_private;
 288         int ret = init_ring_common(ring);
 289
 290         if (INTEL_INFO(dev)->gen > 3) {
 291                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 292                 if (IS_GEN6(dev))
 293                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 294                 I915_WRITE(MI_MODE, mode);
 295         }
 296
 297         if (INTEL_INFO(dev)->gen >= 6) {
 298         } else if (IS_GEN5(dev)) {
 299                 ret = init_pipe_control(ring);
 300                 if (ret)
 301                         return ret;
 302         }
 303
 304         return ret;
 305 }
 306
 307 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 308 {
 309         if (!ring->private)
 310                 return;
 311
 312         cleanup_pipe_control(ring);
 313 }
 314
 315 static void
 316 update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
 317 {
 318         struct drm_device *dev = ring->dev;
 319         struct drm_i915_private *dev_priv = dev->dev_private;
 320         int id;
 321
 322         /*
 323          * cs -> 1 = vcs, 0 = bcs
 324          * vcs -> 1 = bcs, 0 = cs,
 325          * bcs -> 1 = cs, 0 = vcs.
 326          */
 327         id = ring - dev_priv->ring;
 328         id += 2 - i;
 329         id %= 3;
 330
 331         intel_ring_emit(ring,
 332                         MI_SEMAPHORE_MBOX |
 333                         MI_SEMAPHORE_REGISTER |
 334                         MI_SEMAPHORE_UPDATE);
 335         intel_ring_emit(ring, seqno);
 336         intel_ring_emit(ring,
 337                         RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
 338 }
 339
 340 static int
 341 gen6_add_request(struct intel_ring_buffer *ring,
 342                  u32 *result)
 343 {
 344         u32 seqno;
 345         int ret;
 346
 347         ret = intel_ring_begin(ring, 10);
 348         if (ret)
 349                 return ret;
 350
 351         seqno = i915_gem_get_seqno(ring->dev);
 352         update_semaphore(ring, 0, seqno);
 353         update_semaphore(ring, 1, seqno);
 354
 355         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 356         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 357         intel_ring_emit(ring, seqno);
 358         intel_ring_emit(ring, MI_USER_INTERRUPT);
 359         intel_ring_advance(ring);
 360
 361         *result = seqno;
 362         return 0;
 363 }
 364
 365 int
 366 intel_ring_sync(struct intel_ring_buffer *ring,
 367                 struct intel_ring_buffer *to,
 368                 u32 seqno)
 369 {
 370         int ret;
 371
 372         ret = intel_ring_begin(ring, 4);
 373         if (ret)
 374                 return ret;
 375
 376         intel_ring_emit(ring,
 377                         MI_SEMAPHORE_MBOX |
 378                         MI_SEMAPHORE_REGISTER |
 379                         intel_ring_sync_index(ring, to) << 17 |
 380                         MI_SEMAPHORE_COMPARE);
 381         intel_ring_emit(ring, seqno);
 382         intel_ring_emit(ring, 0);
 383         intel_ring_emit(ring, MI_NOOP);
 384         intel_ring_advance(ring);
 385
 386         return 0;
 387 }
 388
 389 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 390 do {                                                                    \
 391         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |           \
 392                  PIPE_CONTROL_DEPTH_STALL | 2);                         \
 393         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 394         intel_ring_emit(ring__, 0);                                                     \
 395         intel_ring_emit(ring__, 0);                                                     \
 396 } while (0)
 397
 398 static int
 399 pc_render_add_request(struct intel_ring_buffer *ring,
 400                       u32 *result)
 401 {
 402         struct drm_device *dev = ring->dev;
 403         u32 seqno = i915_gem_get_seqno(dev);
 404         struct pipe_control *pc = ring->private;
 405         u32 scratch_addr = pc->gtt_offset + 128;
 406         int ret;
 407
 408         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 409          * incoherent with writes to memory, i.e. completely fubar,
 410          * so we need to use PIPE_NOTIFY instead.
 411          *
 412          * However, we also need to workaround the qword write
 413          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 414          * memory before requesting an interrupt.
 415          */
 416         ret = intel_ring_begin(ring, 32);
 417         if (ret)
 418                 return ret;
 419
 420         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 421                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
 422         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 423         intel_ring_emit(ring, seqno);
 424         intel_ring_emit(ring, 0);
 425         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 426         scratch_addr += 128; /* write to separate cachelines */
 427         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 428         scratch_addr += 128;
 429         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 430         scratch_addr += 128;
 431         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 432         scratch_addr += 128;
 433         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 434         scratch_addr += 128;
 435         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 436         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 437                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 438                         PIPE_CONTROL_NOTIFY);
 439         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 440         intel_ring_emit(ring, seqno);
 441         intel_ring_emit(ring, 0);
 442         intel_ring_advance(ring);
 443
 444         *result = seqno;
 445         return 0;
 446 }
 447
 448 static int
 449 render_ring_add_request(struct intel_ring_buffer *ring,
 450                         u32 *result)
 451 {
 452         struct drm_device *dev = ring->dev;
 453         u32 seqno = i915_gem_get_seqno(dev);
 454         int ret;
 455
 456         ret = intel_ring_begin(ring, 4);
 457         if (ret)
 458                 return ret;
 459
 460         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 461         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 462         intel_ring_emit(ring, seqno);
 463         intel_ring_emit(ring, MI_USER_INTERRUPT);
 464         intel_ring_advance(ring);
 465
 466         *result = seqno;
 467         return 0;
 468 }
 469
 470 static u32
 471 ring_get_seqno(struct intel_ring_buffer *ring)
 472 {
 473         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 474 }
 475
 476 static u32
 477 pc_render_get_seqno(struct intel_ring_buffer *ring)
 478 {
 479         struct pipe_control *pc = ring->private;
 480         return pc->cpu_page[0];
 481 }
 482
 483 static bool
 484 render_ring_get_irq(struct intel_ring_buffer *ring)
 485 {
 486         struct drm_device *dev = ring->dev;
 487
 488         if (!dev->irq_enabled)
 489                 return false;
 490
 491         if (atomic_inc_return(&ring->irq_refcount) == 1) {
 492                 drm_i915_private_t *dev_priv = dev->dev_private;
 493                 unsigned long irqflags;
 494
 495                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 496                 if (HAS_PCH_SPLIT(dev))
 497                         ironlake_enable_graphics_irq(dev_priv,
 498                                                      GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 499                 else
 500                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 501                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 502         }
 503
 504         return true;
 505 }
 506
 507 static void
 508 render_ring_put_irq(struct intel_ring_buffer *ring)
 509 {
 510         struct drm_device *dev = ring->dev;
 511
 512         if (atomic_dec_and_test(&ring->irq_refcount)) {
 513                 drm_i915_private_t *dev_priv = dev->dev_private;
 514                 unsigned long irqflags;
 515
 516                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 517                 if (HAS_PCH_SPLIT(dev))
 518                         ironlake_disable_graphics_irq(dev_priv,
 519                                                       GT_USER_INTERRUPT |
 520                                                       GT_PIPE_NOTIFY);
 521                 else
 522                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 523                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 524         }
 525 }
 526
 527 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 528 {
 529         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 530         u32 mmio = IS_GEN6(ring->dev) ?
 531                 RING_HWS_PGA_GEN6(ring->mmio_base) :
 532                 RING_HWS_PGA(ring->mmio_base);
 533         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 534         POSTING_READ(mmio);
 535 }
 536
 537 static void
 538 bsd_ring_flush(struct intel_ring_buffer *ring,
 539                u32     invalidate_domains,
 540                u32     flush_domains)
 541 {
 542         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
 543                 return;
 544
 545         if (intel_ring_begin(ring, 2) == 0) {
 546                 intel_ring_emit(ring, MI_FLUSH);
 547                 intel_ring_emit(ring, MI_NOOP);
 548                 intel_ring_advance(ring);
 549         }
 550 }
 551
 552 static int
 553 ring_add_request(struct intel_ring_buffer *ring,
 554                  u32 *result)
 555 {
 556         u32 seqno;
 557         int ret;
 558
 559         ret = intel_ring_begin(ring, 4);
 560         if (ret)
 561                 return ret;
 562
 563         seqno = i915_gem_get_seqno(ring->dev);
 564
 565         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 566         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 567         intel_ring_emit(ring, seqno);
 568         intel_ring_emit(ring, MI_USER_INTERRUPT);
 569         intel_ring_advance(ring);
 570
 571         DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
 572         *result = seqno;
 573         return 0;
 574 }
 575
 576 static bool
 577 ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
 578 {
 579         struct drm_device *dev = ring->dev;
 580
 581         if (!dev->irq_enabled)
 582                return false;
 583
 584         if (atomic_inc_return(&ring->irq_refcount) == 1) {
 585                 drm_i915_private_t *dev_priv = dev->dev_private;
 586                 unsigned long irqflags;
 587
 588                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 589                 ironlake_enable_graphics_irq(dev_priv, flag);
 590                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 591         }
 592
 593         return true;
 594 }
 595
 596 static void
 597 ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
 598 {
 599         struct drm_device *dev = ring->dev;
 600
 601         if (atomic_dec_and_test(&ring->irq_refcount)) {
 602                 drm_i915_private_t *dev_priv = dev->dev_private;
 603                 unsigned long irqflags;
 604
 605                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 606                 ironlake_disable_graphics_irq(dev_priv, flag);
 607                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 608         }
 609 }
 610
 611 static bool
 612 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 613 {
 614         return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
 615 }
 616 static void
 617 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 618 {
 619         ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
 620 }
 621
 622 static int
 623 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 624 {
 625         int ret;
 626
 627         ret = intel_ring_begin(ring, 2);
 628         if (ret)
 629                 return ret;
 630
 631         intel_ring_emit(ring,
 632                         MI_BATCH_BUFFER_START | (2 << 6) |
 633                         MI_BATCH_NON_SECURE_I965);
 634         intel_ring_emit(ring, offset);
 635         intel_ring_advance(ring);
 636
 637         return 0;
 638 }
 639
 640 static int
 641 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 642                                 u32 offset, u32 len)
 643 {
 644         struct drm_device *dev = ring->dev;
 645         drm_i915_private_t *dev_priv = dev->dev_private;
 646         int ret;
 647
 648         trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
 649
 650         if (IS_I830(dev) || IS_845G(dev)) {
 651                 ret = intel_ring_begin(ring, 4);
 652                 if (ret)
 653                         return ret;
 654
 655                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 656                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 657                 intel_ring_emit(ring, offset + len - 8);
 658                 intel_ring_emit(ring, 0);
 659         } else {
 660                 ret = intel_ring_begin(ring, 2);
 661                 if (ret)
 662                         return ret;
 663
 664                 if (INTEL_INFO(dev)->gen >= 4) {
 665                         intel_ring_emit(ring,
 666                                         MI_BATCH_BUFFER_START | (2 << 6) |
 667                                         MI_BATCH_NON_SECURE_I965);
 668                         intel_ring_emit(ring, offset);
 669                 } else {
 670                         intel_ring_emit(ring,
 671                                         MI_BATCH_BUFFER_START | (2 << 6));
 672                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 673                 }
 674         }
 675         intel_ring_advance(ring);
 676
 677         return 0;
 678 }
 679
 680 static void cleanup_status_page(struct intel_ring_buffer *ring)
 681 {
 682         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 683         struct drm_i915_gem_object *obj;
 684
 685         obj = ring->status_page.obj;
 686         if (obj == NULL)
 687                 return;
 688
 689         kunmap(obj->pages[0]);
 690         i915_gem_object_unpin(obj);
 691         drm_gem_object_unreference(&obj->base);
 692         ring->status_page.obj = NULL;
 693
 694         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 695 }
 696
 697 static int init_status_page(struct intel_ring_buffer *ring)
 698 {
 699         struct drm_device *dev = ring->dev;
 700         drm_i915_private_t *dev_priv = dev->dev_private;
 701         struct drm_i915_gem_object *obj;
 702         int ret;
 703
 704         obj = i915_gem_alloc_object(dev, 4096);
 705         if (obj == NULL) {
 706                 DRM_ERROR("Failed to allocate status page\n");
 707                 ret = -ENOMEM;
 708                 goto err;
 709         }
 710         obj->agp_type = AGP_USER_CACHED_MEMORY;
 711
 712         ret = i915_gem_object_pin(obj, 4096, true);
 713         if (ret != 0) {
 714                 goto err_unref;
 715         }
 716
 717         ring->status_page.gfx_addr = obj->gtt_offset;
 718         ring->status_page.page_addr = kmap(obj->pages[0]);
 719         if (ring->status_page.page_addr == NULL) {
 720                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 721                 goto err_unpin;
 722         }
 723         ring->status_page.obj = obj;
 724         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 725
 726         intel_ring_setup_status_page(ring);
 727         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 728                         ring->name, ring->status_page.gfx_addr);
 729
 730         return 0;
 731
 732 err_unpin:
 733         i915_gem_object_unpin(obj);
 734 err_unref:
 735         drm_gem_object_unreference(&obj->base);
 736 err:
 737         return ret;
 738 }
 739
 740 int intel_init_ring_buffer(struct drm_device *dev,
 741                            struct intel_ring_buffer *ring)
 742 {
 743         struct drm_i915_gem_object *obj;
 744         int ret;
 745
 746         ring->dev = dev;
 747         INIT_LIST_HEAD(&ring->active_list);
 748         INIT_LIST_HEAD(&ring->request_list);
 749         INIT_LIST_HEAD(&ring->gpu_write_list);
 750
 751         if (I915_NEED_GFX_HWS(dev)) {
 752                 ret = init_status_page(ring);
 753                 if (ret)
 754                         return ret;
 755         }
 756
 757         obj = i915_gem_alloc_object(dev, ring->size);
 758         if (obj == NULL) {
 759                 DRM_ERROR("Failed to allocate ringbuffer\n");
 760                 ret = -ENOMEM;
 761                 goto err_hws;
 762         }
 763
 764         ring->obj = obj;
 765
 766         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
 767         if (ret)
 768                 goto err_unref;
 769
 770         ring->map.size = ring->size;
 771         ring->map.offset = dev->agp->base + obj->gtt_offset;
 772         ring->map.type = 0;
 773         ring->map.flags = 0;
 774         ring->map.mtrr = 0;
 775
 776         drm_core_ioremap_wc(&ring->map, dev);
 777         if (ring->map.handle == NULL) {
 778                 DRM_ERROR("Failed to map ringbuffer.\n");
 779                 ret = -EINVAL;
 780                 goto err_unpin;
 781         }
 782
 783         ring->virtual_start = ring->map.handle;
 784         ret = ring->init(ring);
 785         if (ret)
 786                 goto err_unmap;
 787
 788         return 0;
 789
 790 err_unmap:
 791         drm_core_ioremapfree(&ring->map, dev);
 792 err_unpin:
 793         i915_gem_object_unpin(obj);
 794 err_unref:
 795         drm_gem_object_unreference(&obj->base);
 796         ring->obj = NULL;
 797 err_hws:
 798         cleanup_status_page(ring);
 799         return ret;
 800 }
 801
 802 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
 803 {
 804         struct drm_i915_private *dev_priv;
 805         int ret;
 806
 807         if (ring->obj == NULL)
 808                 return;
 809
 810         /* Disable the ring buffer. The ring must be idle at this point */
 811         dev_priv = ring->dev->dev_private;
 812         ret = intel_wait_ring_buffer(ring, ring->size - 8);
 813         I915_WRITE_CTL(ring, 0);
 814
 815         drm_core_ioremapfree(&ring->map, ring->dev);
 816
 817         i915_gem_object_unpin(ring->obj);
 818         drm_gem_object_unreference(&ring->obj->base);
 819         ring->obj = NULL;
 820
 821         if (ring->cleanup)
 822                 ring->cleanup(ring);
 823
 824         cleanup_status_page(ring);
 825 }
 826
 827 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
 828 {
 829         unsigned int *virt;
 830         int rem;
 831         rem = ring->size - ring->tail;
 832
 833         if (ring->space < rem) {
 834                 int ret = intel_wait_ring_buffer(ring, rem);
 835                 if (ret)
 836                         return ret;
 837         }
 838
 839         virt = (unsigned int *)(ring->virtual_start + ring->tail);
 840         rem /= 8;
 841         while (rem--) {
 842                 *virt++ = MI_NOOP;
 843                 *virt++ = MI_NOOP;
 844         }
 845
 846         ring->tail = 0;
 847         ring->space = ring->head - 8;
 848
 849         return 0;
 850 }
 851
 852 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
 853 {
 854         struct drm_device *dev = ring->dev;
 855         struct drm_i915_private *dev_priv = dev->dev_private;
 856         unsigned long end;
 857         u32 head;
 858
 859         trace_i915_ring_wait_begin (dev);
 860         end = jiffies + 3 * HZ;
 861         do {
 862                 /* If the reported head position has wrapped or hasn't advanced,
 863                  * fallback to the slow and accurate path.
 864                  */
 865                 head = intel_read_status_page(ring, 4);
 866                 if (head < ring->actual_head)
 867                         head = I915_READ_HEAD(ring);
 868                 ring->actual_head = head;
 869                 ring->head = head & HEAD_ADDR;
 870                 ring->space = ring->head - (ring->tail + 8);
 871                 if (ring->space < 0)
 872                         ring->space += ring->size;
 873                 if (ring->space >= n) {
 874                         trace_i915_ring_wait_end(dev);
 875                         return 0;
 876                 }
 877
 878                 if (dev->primary->master) {
 879                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 880                         if (master_priv->sarea_priv)
 881                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 882                 }
 883
 884                 msleep(1);
 885                 if (atomic_read(&dev_priv->mm.wedged))
 886                         return -EAGAIN;
 887         } while (!time_after(jiffies, end));
 888         trace_i915_ring_wait_end (dev);
 889         return -EBUSY;
 890 }
 891
 892 int intel_ring_begin(struct intel_ring_buffer *ring,
 893                      int num_dwords)
 894 {
 895         int n = 4*num_dwords;
 896         int ret;
 897
 898         if (unlikely(ring->tail + n > ring->size)) {
 899                 ret = intel_wrap_ring_buffer(ring);
 900                 if (unlikely(ret))
 901                         return ret;
 902         }
 903
 904         if (unlikely(ring->space < n)) {
 905                 ret = intel_wait_ring_buffer(ring, n);
 906                 if (unlikely(ret))
 907                         return ret;
 908         }
 909
 910         ring->space -= n;
 911         return 0;
 912 }
 913
 914 void intel_ring_advance(struct intel_ring_buffer *ring)
 915 {
 916         ring->tail &= ring->size - 1;
 917         ring->write_tail(ring, ring->tail);
 918 }
 919
 920 static const struct intel_ring_buffer render_ring = {
 921         .name                   = "render ring",
 922         .id                     = RING_RENDER,
 923         .mmio_base              = RENDER_RING_BASE,
 924         .size                   = 32 * PAGE_SIZE,
 925         .init                   = init_render_ring,
 926         .write_tail             = ring_write_tail,
 927         .flush                  = render_ring_flush,
 928         .add_request            = render_ring_add_request,
 929         .get_seqno              = ring_get_seqno,
 930         .irq_get                = render_ring_get_irq,
 931         .irq_put                = render_ring_put_irq,
 932         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
 933        .cleanup                 = render_ring_cleanup,
 934 };
 935
 936 /* ring buffer for bit-stream decoder */
 937
 938 static const struct intel_ring_buffer bsd_ring = {
 939         .name                   = "bsd ring",
 940         .id                     = RING_BSD,
 941         .mmio_base              = BSD_RING_BASE,
 942         .size                   = 32 * PAGE_SIZE,
 943         .init                   = init_ring_common,
 944         .write_tail             = ring_write_tail,
 945         .flush                  = bsd_ring_flush,
 946         .add_request            = ring_add_request,
 947         .get_seqno              = ring_get_seqno,
 948         .irq_get                = bsd_ring_get_irq,
 949         .irq_put                = bsd_ring_put_irq,
 950         .dispatch_execbuffer    = ring_dispatch_execbuffer,
 951 };
 952
 953
 954 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
 955                                      u32 value)
 956 {
 957        drm_i915_private_t *dev_priv = ring->dev->dev_private;
 958
 959        /* Every tail move must follow the sequence below */
 960        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
 961                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
 962                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
 963        I915_WRITE(GEN6_BSD_RNCID, 0x0);
 964
 965        if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
 966                                GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
 967                        50))
 968                DRM_ERROR("timed out waiting for IDLE Indicator\n");
 969
 970        I915_WRITE_TAIL(ring, value);
 971        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
 972                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
 973                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
 974 }
 975
 976 static void gen6_ring_flush(struct intel_ring_buffer *ring,
 977                             u32 invalidate_domains,
 978                             u32 flush_domains)
 979 {
 980         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
 981                 return;
 982
 983         if (intel_ring_begin(ring, 4) == 0) {
 984                 intel_ring_emit(ring, MI_FLUSH_DW);
 985                 intel_ring_emit(ring, 0);
 986                 intel_ring_emit(ring, 0);
 987                 intel_ring_emit(ring, 0);
 988                 intel_ring_advance(ring);
 989         }
 990 }
 991
 992 static int
 993 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 994                               u32 offset, u32 len)
 995 {
 996        int ret;
 997
 998        ret = intel_ring_begin(ring, 2);
 999        if (ret)
1000                return ret;
1001
1002        intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1003        /* bit0-7 is the length on GEN6+ */
1004        intel_ring_emit(ring, offset);
1005        intel_ring_advance(ring);
1006
1007        return 0;
1008 }
1009
1010 static bool
1011 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1012 {
1013         return ring_get_irq(ring, GT_GEN6_BSD_USER_INTERRUPT);
1014 }
1015
1016 static void
1017 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1018 {
1019         ring_put_irq(ring, GT_GEN6_BSD_USER_INTERRUPT);
1020 }
1021
1022 /* ring buffer for Video Codec for Gen6+ */
1023 static const struct intel_ring_buffer gen6_bsd_ring = {
1024         .name                   = "gen6 bsd ring",
1025         .id                     = RING_BSD,
1026         .mmio_base              = GEN6_BSD_RING_BASE,
1027         .size                   = 32 * PAGE_SIZE,
1028         .init                   = init_ring_common,
1029         .write_tail             = gen6_bsd_ring_write_tail,
1030         .flush                  = gen6_ring_flush,
1031         .add_request            = gen6_add_request,
1032         .get_seqno              = ring_get_seqno,
1033         .irq_get                = gen6_bsd_ring_get_irq,
1034         .irq_put                = gen6_bsd_ring_put_irq,
1035         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1036 };
1037
1038 /* Blitter support (SandyBridge+) */
1039
1040 static bool
1041 blt_ring_get_irq(struct intel_ring_buffer *ring)
1042 {
1043         return ring_get_irq(ring, GT_BLT_USER_INTERRUPT);
1044 }
1045
1046 static void
1047 blt_ring_put_irq(struct intel_ring_buffer *ring)
1048 {
1049         ring_put_irq(ring, GT_BLT_USER_INTERRUPT);
1050 }
1051
1052
1053 /* Workaround for some stepping of SNB,
1054  * each time when BLT engine ring tail moved,
1055  * the first command in the ring to be parsed
1056  * should be MI_BATCH_BUFFER_START
1057  */
1058 #define NEED_BLT_WORKAROUND(dev) \
1059         (IS_GEN6(dev) && (dev->pdev->revision < 8))
1060
1061 static inline struct drm_i915_gem_object *
1062 to_blt_workaround(struct intel_ring_buffer *ring)
1063 {
1064         return ring->private;
1065 }
1066
1067 static int blt_ring_init(struct intel_ring_buffer *ring)
1068 {
1069         if (NEED_BLT_WORKAROUND(ring->dev)) {
1070                 struct drm_i915_gem_object *obj;
1071                 u32 *ptr;
1072                 int ret;
1073
1074                 obj = i915_gem_alloc_object(ring->dev, 4096);
1075                 if (obj == NULL)
1076                         return -ENOMEM;
1077
1078                 ret = i915_gem_object_pin(obj, 4096, true);
1079                 if (ret) {
1080                         drm_gem_object_unreference(&obj->base);
1081                         return ret;
1082                 }
1083
1084                 ptr = kmap(obj->pages[0]);
1085                 *ptr++ = MI_BATCH_BUFFER_END;
1086                 *ptr++ = MI_NOOP;
1087                 kunmap(obj->pages[0]);
1088
1089                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1090                 if (ret) {
1091                         i915_gem_object_unpin(obj);
1092                         drm_gem_object_unreference(&obj->base);
1093                         return ret;
1094                 }
1095
1096                 ring->private = obj;
1097         }
1098
1099         return init_ring_common(ring);
1100 }
1101
1102 static int blt_ring_begin(struct intel_ring_buffer *ring,
1103                           int num_dwords)
1104 {
1105         if (ring->private) {
1106                 int ret = intel_ring_begin(ring, num_dwords+2);
1107                 if (ret)
1108                         return ret;
1109
1110                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1111                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1112
1113                 return 0;
1114         } else
1115                 return intel_ring_begin(ring, 4);
1116 }
1117
1118 static void blt_ring_flush(struct intel_ring_buffer *ring,
1119                            u32 invalidate_domains,
1120                            u32 flush_domains)
1121 {
1122         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
1123                 return;
1124
1125         if (blt_ring_begin(ring, 4) == 0) {
1126                 intel_ring_emit(ring, MI_FLUSH_DW);
1127                 intel_ring_emit(ring, 0);
1128                 intel_ring_emit(ring, 0);
1129                 intel_ring_emit(ring, 0);
1130                 intel_ring_advance(ring);
1131         }
1132 }
1133
1134 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1135 {
1136         if (!ring->private)
1137                 return;
1138
1139         i915_gem_object_unpin(ring->private);
1140         drm_gem_object_unreference(ring->private);
1141         ring->private = NULL;
1142 }
1143
1144 static const struct intel_ring_buffer gen6_blt_ring = {
1145        .name                    = "blt ring",
1146        .id                      = RING_BLT,
1147        .mmio_base               = BLT_RING_BASE,
1148        .size                    = 32 * PAGE_SIZE,
1149        .init                    = blt_ring_init,
1150        .write_tail              = ring_write_tail,
1151        .flush                   = blt_ring_flush,
1152        .add_request             = gen6_add_request,
1153        .get_seqno               = ring_get_seqno,
1154        .irq_get                 = blt_ring_get_irq,
1155        .irq_put                 = blt_ring_put_irq,
1156        .dispatch_execbuffer     = gen6_ring_dispatch_execbuffer,
1157        .cleanup                 = blt_ring_cleanup,
1158 };
1159
1160 int intel_init_render_ring_buffer(struct drm_device *dev)
1161 {
1162         drm_i915_private_t *dev_priv = dev->dev_private;
1163         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1164
1165         *ring = render_ring;
1166         if (INTEL_INFO(dev)->gen >= 6) {
1167                 ring->add_request = gen6_add_request;
1168         } else if (IS_GEN5(dev)) {
1169                 ring->add_request = pc_render_add_request;
1170                 ring->get_seqno = pc_render_get_seqno;
1171         }
1172
1173         if (!I915_NEED_GFX_HWS(dev)) {
1174                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1175                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1176         }
1177
1178         return intel_init_ring_buffer(dev, ring);
1179 }
1180
1181 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1182 {
1183         drm_i915_private_t *dev_priv = dev->dev_private;
1184         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1185
1186         if (IS_GEN6(dev))
1187                 *ring = gen6_bsd_ring;
1188         else
1189                 *ring = bsd_ring;
1190
1191         return intel_init_ring_buffer(dev, ring);
1192 }
1193
1194 int intel_init_blt_ring_buffer(struct drm_device *dev)
1195 {
1196         drm_i915_private_t *dev_priv = dev->dev_private;
1197         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1198
1199         *ring = gen6_blt_ring;
1200
1201         return intel_init_ring_buffer(dev, ring);
1202 }