1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
4 #include <linux/hashtable.h>
5 #include "i915_gem_batch_pool.h"
6 #include "i915_gem_request.h"
7 #include "i915_gem_timeline.h"
8 #include "i915_selftest.h"
10 #define I915_CMD_HASH_ORDER 9
12 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
13 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
14 * to give some inclination as to some of the magic values used in the various
17 #define CACHELINE_BYTES 64
18 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
20 struct intel_hw_status_page {
26 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
27 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
29 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
30 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
32 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
33 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
35 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
36 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
38 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
39 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
41 #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
42 #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
44 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
45 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
47 #define gen8_semaphore_seqno_size sizeof(uint64_t)
48 #define GEN8_SEMAPHORE_OFFSET(__from, __to) \
49 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
50 #define GEN8_SIGNAL_OFFSET(__ring, to) \
51 (dev_priv->semaphore->node.start + \
52 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
53 #define GEN8_WAIT_OFFSET(__ring, from) \
54 (dev_priv->semaphore->node.start + \
55 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
57 enum intel_engine_hangcheck_action {
62 ENGINE_ACTIVE_SUBUNITS,
67 static inline const char *
68 hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
75 case ENGINE_ACTIVE_SEQNO:
76 return "active seqno";
77 case ENGINE_ACTIVE_HEAD:
79 case ENGINE_ACTIVE_SUBUNITS:
80 return "active subunits";
81 case ENGINE_WAIT_KICK:
90 #define I915_MAX_SLICES 3
91 #define I915_MAX_SUBSLICES 3
93 #define instdone_slice_mask(dev_priv__) \
94 (INTEL_GEN(dev_priv__) == 7 ? \
95 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
97 #define instdone_subslice_mask(dev_priv__) \
98 (INTEL_GEN(dev_priv__) == 7 ? \
99 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)
101 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
102 for ((slice__) = 0, (subslice__) = 0; \
103 (slice__) < I915_MAX_SLICES; \
104 (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
105 (slice__) += ((subslice__) == 0)) \
106 for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
107 (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
109 struct intel_instdone {
111 /* The following exist only in the RCS engine */
113 u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
114 u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
117 struct intel_engine_hangcheck {
120 enum intel_engine_hangcheck_action action;
121 unsigned long action_timestamp;
123 struct intel_instdone instdone;
128 struct i915_vma *vma;
131 struct list_head request_list;
142 struct i915_gem_context;
143 struct drm_i915_reg_table;
146 * we use a single page to load ctx workarounds so all of these
147 * values are referred in terms of dwords
149 * struct i915_wa_ctx_bb:
150 * offset: specifies batch starting position, also helpful in case
151 * if we want to have multiple batches at different offsets based on
152 * some criteria. It is not a requirement at the moment but provides
153 * an option for future use.
154 * size: size of the batch in DWORDS
156 struct i915_ctx_workarounds {
157 struct i915_wa_ctx_bb {
160 } indirect_ctx, per_ctx;
161 struct i915_vma *vma;
164 struct drm_i915_gem_request;
165 struct intel_render_state;
168 * Engine IDs definitions.
169 * Keep instances of the same type engine together.
171 enum intel_engine_id {
176 #define _VCS(n) (VCS + (n))
180 #define INTEL_ENGINE_CS_MAX_NAME 8
182 struct intel_engine_cs {
183 struct drm_i915_private *i915;
184 char name[INTEL_ENGINE_CS_MAX_NAME];
185 enum intel_engine_id id;
186 unsigned int uabi_id;
194 unsigned int irq_shift;
196 struct intel_ring *buffer;
197 struct intel_timeline *timeline;
199 struct intel_render_state *render_state;
202 unsigned long irq_posted;
203 #define ENGINE_IRQ_BREADCRUMB 0
204 #define ENGINE_IRQ_EXECLIST 1
206 /* Rather than have every client wait upon all user interrupts,
207 * with the herd waking after every interrupt and each doing the
208 * heavyweight seqno dance, we delegate the task (of being the
209 * bottom-half of the user interrupt) to the first client. After
210 * every interrupt, we wake up one client, who does the heavyweight
211 * coherent seqno read and either goes back to sleep (if incomplete),
212 * or wakes up all the completed clients in parallel, before then
213 * transferring the bottom-half status to the next client in the queue.
215 * Compared to walking the entire list of waiters in a single dedicated
216 * bottom-half, we reduce the latency of the first waiter by avoiding
217 * a context switch, but incur additional coherent seqno reads when
218 * following the chain of request breadcrumbs. Since it is most likely
219 * that we have a single client waiting on each seqno, then reducing
220 * the overhead of waking that client is much preferred.
222 struct intel_breadcrumbs {
223 spinlock_t irq_lock; /* protects irq_*; irqsafe */
224 struct intel_wait *irq_wait; /* oldest waiter by retirement */
226 spinlock_t rb_lock; /* protects the rb and wraps irq_lock */
227 struct rb_root waiters; /* sorted by retirement, priority */
228 struct rb_root signals; /* sorted by retirement */
229 struct task_struct *signaler; /* used for fence signalling */
230 struct drm_i915_gem_request __rcu *first_signal;
231 struct timer_list fake_irq; /* used after a missed interrupt */
232 struct timer_list hangcheck; /* detect missed interrupts */
234 unsigned int hangcheck_interrupts;
237 bool irq_enabled : 1;
238 I915_SELFTEST_DECLARE(bool mock : 1);
242 * A pool of objects to use as shadow copies of client batch buffers
243 * when the command parser is enabled. Prevents the client from
244 * modifying the batch contents after software parsing.
246 struct i915_gem_batch_pool batch_pool;
248 struct intel_hw_status_page status_page;
249 struct i915_ctx_workarounds wa_ctx;
250 struct i915_vma *scratch;
252 u32 irq_keep_mask; /* always keep these interrupts */
253 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
254 void (*irq_enable)(struct intel_engine_cs *engine);
255 void (*irq_disable)(struct intel_engine_cs *engine);
257 int (*init_hw)(struct intel_engine_cs *engine);
258 void (*reset_hw)(struct intel_engine_cs *engine,
259 struct drm_i915_gem_request *req);
261 void (*set_default_submission)(struct intel_engine_cs *engine);
263 struct intel_ring *(*context_pin)(struct intel_engine_cs *engine,
264 struct i915_gem_context *ctx);
265 void (*context_unpin)(struct intel_engine_cs *engine,
266 struct i915_gem_context *ctx);
267 int (*request_alloc)(struct drm_i915_gem_request *req);
268 int (*init_context)(struct drm_i915_gem_request *req);
270 int (*emit_flush)(struct drm_i915_gem_request *request,
272 #define EMIT_INVALIDATE BIT(0)
273 #define EMIT_FLUSH BIT(1)
274 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
275 int (*emit_bb_start)(struct drm_i915_gem_request *req,
276 u64 offset, u32 length,
277 unsigned int dispatch_flags);
278 #define I915_DISPATCH_SECURE BIT(0)
279 #define I915_DISPATCH_PINNED BIT(1)
280 #define I915_DISPATCH_RS BIT(2)
281 void (*emit_breadcrumb)(struct drm_i915_gem_request *req,
283 int emit_breadcrumb_sz;
285 /* Pass the request to the hardware queue (e.g. directly into
286 * the legacy ringbuffer or to the end of an execlist).
288 * This is called from an atomic context with irqs disabled; must
291 void (*submit_request)(struct drm_i915_gem_request *req);
293 /* Call when the priority on a request has changed and it and its
294 * dependencies may need rescheduling. Note the request itself may
295 * not be ready to run!
297 * Called under the struct_mutex.
299 void (*schedule)(struct drm_i915_gem_request *request,
302 /* Some chipsets are not quite as coherent as advertised and need
303 * an expensive kick to force a true read of the up-to-date seqno.
304 * However, the up-to-date seqno is not always required and the last
305 * seen value is good enough. Note that the seqno will always be
306 * monotonic, even if not coherent.
308 void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
309 void (*cleanup)(struct intel_engine_cs *engine);
311 /* GEN8 signal/wait table - never trust comments!
312 * signal to signal to signal to signal to signal to
313 * RCS VCS BCS VECS VCS2
314 * --------------------------------------------------------------------
315 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
316 * |-------------------------------------------------------------------
317 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
318 * |-------------------------------------------------------------------
319 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
320 * |-------------------------------------------------------------------
321 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
322 * |-------------------------------------------------------------------
323 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
324 * |-------------------------------------------------------------------
327 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
328 * ie. transpose of g(x, y)
330 * sync from sync from sync from sync from sync from
331 * RCS VCS BCS VECS VCS2
332 * --------------------------------------------------------------------
333 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
334 * |-------------------------------------------------------------------
335 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
336 * |-------------------------------------------------------------------
337 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
338 * |-------------------------------------------------------------------
339 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
340 * |-------------------------------------------------------------------
341 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
342 * |-------------------------------------------------------------------
345 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
346 * ie. transpose of f(x, y)
350 #define GEN6_SEMAPHORE_LAST VECS_HW
351 #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
352 #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
354 /* our mbox written by others */
355 u32 wait[GEN6_NUM_SEMAPHORES];
356 /* mboxes this ring signals to */
357 i915_reg_t signal[GEN6_NUM_SEMAPHORES];
359 u64 signal_ggtt[I915_NUM_ENGINES];
363 int (*sync_to)(struct drm_i915_gem_request *req,
364 struct drm_i915_gem_request *signal);
365 u32 *(*signal)(struct drm_i915_gem_request *req, u32 *cs);
369 struct tasklet_struct irq_tasklet;
370 struct execlist_port {
371 struct drm_i915_gem_request *request;
373 GEM_DEBUG_DECL(u32 context_id);
375 struct rb_root execlist_queue;
376 struct rb_node *execlist_first;
377 unsigned int fw_domains;
379 /* Contexts are pinned whilst they are active on the GPU. The last
380 * context executed remains active whilst the GPU is idle - the
381 * switch away and write to the context object only occurs on the
382 * next execution. Contexts are only unpinned on retirement of the
383 * following request ensuring that we can always write to the object
384 * on the context switch even after idling. Across suspend, we switch
385 * to the kernel context and trash it as the save may not happen
386 * before the hardware is powered down.
388 struct i915_gem_context *last_retired_context;
390 /* We track the current MI_SET_CONTEXT in order to eliminate
391 * redudant context switches. This presumes that requests are not
392 * reordered! Or when they are the tracking is updated along with
393 * the emission of individual requests into the legacy command
396 struct i915_gem_context *legacy_active_context;
398 /* status_notifier: list of callbacks for context-switch changes */
399 struct atomic_notifier_head context_status_notifier;
401 struct intel_engine_hangcheck hangcheck;
403 bool needs_cmd_parser;
406 * Table of commands the command parser needs to know about
409 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
412 * Table of registers allowed in commands that read/write registers.
414 const struct drm_i915_reg_table *reg_tables;
418 * Returns the bitmask for the length field of the specified command.
419 * Return 0 for an unrecognized/invalid command.
421 * If the command parser finds an entry for a command in the engine's
422 * cmd_tables, it gets the command's length based on the table entry.
423 * If not, it calls this function to determine the per-engine length
424 * field encoding for the command (i.e. different opcode ranges use
425 * certain bits to encode the command length in the header).
427 u32 (*get_cmd_length_mask)(u32 cmd_header);
430 static inline unsigned int
431 intel_engine_flag(const struct intel_engine_cs *engine)
433 return BIT(engine->id);
437 intel_read_status_page(struct intel_engine_cs *engine, int reg)
439 /* Ensure that the compiler doesn't optimize away the load. */
440 return READ_ONCE(engine->status_page.page_addr[reg]);
444 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
446 /* Writing into the status page should be done sparingly. Since
447 * we do when we are uncertain of the device state, we take a bit
448 * of extra paranoia to try and ensure that the HWS takes the value
449 * we give and that it doesn't end up trapped inside the CPU!
451 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
453 clflush(&engine->status_page.page_addr[reg]);
454 engine->status_page.page_addr[reg] = value;
455 clflush(&engine->status_page.page_addr[reg]);
458 WRITE_ONCE(engine->status_page.page_addr[reg], value);
463 * Reads a dword out of the status page, which is written to from the command
464 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
467 * The following dwords have a reserved meaning:
468 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
469 * 0x04: ring 0 head pointer
470 * 0x05: ring 1 head pointer (915-class)
471 * 0x06: ring 2 head pointer (915-class)
472 * 0x10-0x1b: Context status DWords (GM45)
473 * 0x1f: Last written status offset. (GM45)
474 * 0x20-0x2f: Reserved (Gen6+)
476 * The area from dword 0x30 to 0x3ff is available for driver usage.
478 #define I915_GEM_HWS_INDEX 0x30
479 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
480 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
481 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
484 intel_engine_create_ring(struct intel_engine_cs *engine, int size);
485 int intel_ring_pin(struct intel_ring *ring,
486 struct drm_i915_private *i915,
487 unsigned int offset_bias);
488 void intel_ring_reset(struct intel_ring *ring, u32 tail);
489 void intel_ring_update_space(struct intel_ring *ring);
490 void intel_ring_unpin(struct intel_ring *ring);
491 void intel_ring_free(struct intel_ring *ring);
493 void intel_engine_stop(struct intel_engine_cs *engine);
494 void intel_engine_cleanup(struct intel_engine_cs *engine);
496 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv);
498 int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
500 u32 __must_check *intel_ring_begin(struct drm_i915_gem_request *req, int n);
503 intel_ring_advance(struct drm_i915_gem_request *req, u32 *cs)
507 * This serves as a placeholder in the code so that the reader
508 * can compare against the preceding intel_ring_begin() and
509 * check that the number of dwords emitted matches the space
510 * reserved for the command packet (i.e. the value passed to
511 * intel_ring_begin()).
513 GEM_BUG_ON((req->ring->vaddr + req->ring->emit) != cs);
517 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
519 return pos & (ring->size - 1);
523 intel_ring_offset(const struct drm_i915_gem_request *req, void *addr)
525 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
526 u32 offset = addr - req->ring->vaddr;
527 GEM_BUG_ON(offset > req->ring->size);
528 return intel_ring_wrap(req->ring, offset);
532 assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
534 /* We could combine these into a single tail operation, but keeping
535 * them as seperate tests will help identify the cause should one
538 GEM_BUG_ON(!IS_ALIGNED(tail, 8));
539 GEM_BUG_ON(tail >= ring->size);
543 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6
544 * Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5
545 * Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5
546 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
547 * same cacheline, the Head Pointer must not be greater than the Tail
550 * We use ring->head as the last known location of the actual RING_HEAD,
551 * it may have advanced but in the worst case it is equally the same
552 * as ring->head and so we should never program RING_TAIL to advance
553 * into the same cacheline as ring->head.
555 #define cacheline(a) round_down(a, CACHELINE_BYTES)
556 GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) &&
561 static inline unsigned int
562 intel_ring_set_tail(struct intel_ring *ring, unsigned int tail)
564 /* Whilst writes to the tail are strictly order, there is no
565 * serialisation between readers and the writers. The tail may be
566 * read by i915_gem_request_retire() just as it is being updated
567 * by execlists, as although the breadcrumb is complete, the context
568 * switch hasn't been seen.
570 assert_ring_tail_valid(ring, tail);
575 void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);
577 void intel_engine_setup_common(struct intel_engine_cs *engine);
578 int intel_engine_init_common(struct intel_engine_cs *engine);
579 int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
580 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
582 int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
583 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
584 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
585 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
587 u64 intel_engine_get_active_head(struct intel_engine_cs *engine);
588 u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine);
590 static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
592 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
595 static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine)
597 /* We are only peeking at the tail of the submit queue (and not the
598 * queue itself) in order to gain a hint as to the current active
599 * state of the engine. Callers are not expected to be taking
600 * engine->timeline->lock, nor are they expected to be concerned
601 * wtih serialising this hint with anything, so document it as
602 * a hint and nothing more.
604 return READ_ONCE(engine->timeline->seqno);
607 int init_workarounds_ring(struct intel_engine_cs *engine);
608 int intel_ring_workarounds_emit(struct drm_i915_gem_request *req);
610 void intel_engine_get_instdone(struct intel_engine_cs *engine,
611 struct intel_instdone *instdone);
614 * Arbitrary size for largest possible 'add request' sequence. The code paths
615 * are complex and variable. Empirical measurement shows that the worst case
616 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
617 * we need to allocate double the largest single packet within that emission
618 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
620 #define MIN_SPACE_FOR_ADD_REQUEST 336
622 static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
624 return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
627 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
628 int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
630 static inline void intel_wait_init(struct intel_wait *wait,
631 struct drm_i915_gem_request *rq)
637 static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 seqno)
643 static inline bool intel_wait_has_seqno(const struct intel_wait *wait)
649 intel_wait_update_seqno(struct intel_wait *wait, u32 seqno)
652 return intel_wait_has_seqno(wait);
656 intel_wait_update_request(struct intel_wait *wait,
657 const struct drm_i915_gem_request *rq)
659 return intel_wait_update_seqno(wait, i915_gem_request_global_seqno(rq));
663 intel_wait_check_seqno(const struct intel_wait *wait, u32 seqno)
665 return wait->seqno == seqno;
669 intel_wait_check_request(const struct intel_wait *wait,
670 const struct drm_i915_gem_request *rq)
672 return intel_wait_check_seqno(wait, i915_gem_request_global_seqno(rq));
675 static inline bool intel_wait_complete(const struct intel_wait *wait)
677 return RB_EMPTY_NODE(&wait->node);
680 bool intel_engine_add_wait(struct intel_engine_cs *engine,
681 struct intel_wait *wait);
682 void intel_engine_remove_wait(struct intel_engine_cs *engine,
683 struct intel_wait *wait);
684 void intel_engine_enable_signaling(struct drm_i915_gem_request *request,
686 void intel_engine_cancel_signaling(struct drm_i915_gem_request *request);
688 static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
690 return READ_ONCE(engine->breadcrumbs.irq_wait);
693 unsigned int intel_engine_wakeup(struct intel_engine_cs *engine);
694 #define ENGINE_WAKEUP_WAITER BIT(0)
695 #define ENGINE_WAKEUP_ASLEEP BIT(1)
697 void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
698 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
700 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
701 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
702 bool intel_breadcrumbs_busy(struct intel_engine_cs *engine);
704 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
706 memset(batch, 0, 6 * sizeof(u32));
708 batch[0] = GFX_OP_PIPE_CONTROL(6);
715 bool intel_engine_is_idle(struct intel_engine_cs *engine);
716 bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
718 void intel_engines_reset_default_submission(struct drm_i915_private *i915);
720 #endif /* _INTEL_RINGBUFFER_H_ */