1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
4 #include <linux/hashtable.h>
5 #include "i915_gem_batch_pool.h"
7 #define I915_CMD_HASH_ORDER 9
9 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
10 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
11 * to give some inclination as to some of the magic values used in the various
14 #define CACHELINE_BYTES 64
15 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
18 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
19 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
20 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
22 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
23 * cacheline, the Head Pointer must not be greater than the Tail
26 #define I915_RING_FREE_SPACE 64
28 struct intel_hw_status_page {
30 unsigned int gfx_addr;
31 struct drm_i915_gem_object *obj;
34 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
35 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
37 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
38 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
40 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
41 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
43 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
44 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
46 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
47 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
49 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
50 #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
52 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
53 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
55 #define gen8_semaphore_seqno_size sizeof(uint64_t)
56 #define GEN8_SEMAPHORE_OFFSET(__from, __to) \
57 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
58 #define GEN8_SIGNAL_OFFSET(__ring, to) \
59 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
60 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
61 #define GEN8_WAIT_OFFSET(__ring, from) \
62 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
63 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
65 #define GEN8_RING_SEMAPHORE_INIT(e) do { \
66 if (!dev_priv->semaphore_obj) { \
69 (e)->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET((e), RCS); \
70 (e)->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET((e), VCS); \
71 (e)->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET((e), BCS); \
72 (e)->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET((e), VECS); \
73 (e)->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET((e), VCS2); \
74 (e)->semaphore.signal_ggtt[(e)->id] = MI_SEMAPHORE_SYNC_INVALID; \
77 enum intel_ring_hangcheck_action {
85 #define HANGCHECK_SCORE_RING_HUNG 31
87 struct intel_ring_hangcheck {
90 unsigned user_interrupts;
92 enum intel_ring_hangcheck_action action;
94 u32 instdone[I915_NUM_INSTDONE_REG];
97 struct intel_ringbuffer {
98 struct drm_i915_gem_object *obj;
99 void __iomem *virtual_start;
100 struct i915_vma *vma;
102 struct intel_engine_cs *engine;
103 struct list_head link;
111 /** We track the position of the requests in the ring buffer, and
112 * when each is retired we increment last_retired_head as the GPU
113 * must have finished processing the request and so we know we
114 * can advance the ringbuffer up to that position.
116 * last_retired_head is set to -1 after the value is consumed so
117 * we can detect new retirements.
119 u32 last_retired_head;
122 struct intel_context;
123 struct drm_i915_reg_table;
126 * we use a single page to load ctx workarounds so all of these
127 * values are referred in terms of dwords
129 * struct i915_wa_ctx_bb:
130 * offset: specifies batch starting position, also helpful in case
131 * if we want to have multiple batches at different offsets based on
132 * some criteria. It is not a requirement at the moment but provides
133 * an option for future use.
134 * size: size of the batch in DWORDS
136 struct i915_ctx_workarounds {
137 struct i915_wa_ctx_bb {
140 } indirect_ctx, per_ctx;
141 struct drm_i915_gem_object *obj;
144 struct intel_engine_cs {
146 enum intel_engine_id {
150 VCS2, /* Keep instances of the same type engine together. */
153 #define I915_NUM_ENGINES 5
154 #define _VCS(n) (VCS + (n))
155 unsigned int exec_id;
158 struct drm_device *dev;
159 struct intel_ringbuffer *buffer;
160 struct list_head buffers;
163 * A pool of objects to use as shadow copies of client batch buffers
164 * when the command parser is enabled. Prevents the client from
165 * modifying the batch contents after software parsing.
167 struct i915_gem_batch_pool batch_pool;
169 struct intel_hw_status_page status_page;
170 struct i915_ctx_workarounds wa_ctx;
172 unsigned irq_refcount; /* protected by dev_priv->irq_lock */
173 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
174 struct drm_i915_gem_request *trace_irq_req;
175 bool __must_check (*irq_get)(struct intel_engine_cs *ring);
176 void (*irq_put)(struct intel_engine_cs *ring);
178 int (*init_hw)(struct intel_engine_cs *ring);
180 int (*init_context)(struct drm_i915_gem_request *req);
182 void (*write_tail)(struct intel_engine_cs *ring,
184 int __must_check (*flush)(struct drm_i915_gem_request *req,
185 u32 invalidate_domains,
187 int (*add_request)(struct drm_i915_gem_request *req);
188 /* Some chipsets are not quite as coherent as advertised and need
189 * an expensive kick to force a true read of the up-to-date seqno.
190 * However, the up-to-date seqno is not always required and the last
191 * seen value is good enough. Note that the seqno will always be
192 * monotonic, even if not coherent.
194 void (*irq_seqno_barrier)(struct intel_engine_cs *ring);
195 u32 (*get_seqno)(struct intel_engine_cs *ring);
196 void (*set_seqno)(struct intel_engine_cs *ring,
198 int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
199 u64 offset, u32 length,
200 unsigned dispatch_flags);
201 #define I915_DISPATCH_SECURE 0x1
202 #define I915_DISPATCH_PINNED 0x2
203 #define I915_DISPATCH_RS 0x4
204 void (*cleanup)(struct intel_engine_cs *ring);
206 /* GEN8 signal/wait table - never trust comments!
207 * signal to signal to signal to signal to signal to
208 * RCS VCS BCS VECS VCS2
209 * --------------------------------------------------------------------
210 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
211 * |-------------------------------------------------------------------
212 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
213 * |-------------------------------------------------------------------
214 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
215 * |-------------------------------------------------------------------
216 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
217 * |-------------------------------------------------------------------
218 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
219 * |-------------------------------------------------------------------
222 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
223 * ie. transpose of g(x, y)
225 * sync from sync from sync from sync from sync from
226 * RCS VCS BCS VECS VCS2
227 * --------------------------------------------------------------------
228 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
229 * |-------------------------------------------------------------------
230 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
231 * |-------------------------------------------------------------------
232 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
233 * |-------------------------------------------------------------------
234 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
235 * |-------------------------------------------------------------------
236 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
237 * |-------------------------------------------------------------------
240 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
241 * ie. transpose of f(x, y)
244 u32 sync_seqno[I915_NUM_ENGINES-1];
248 /* our mbox written by others */
249 u32 wait[I915_NUM_ENGINES];
250 /* mboxes this ring signals to */
251 i915_reg_t signal[I915_NUM_ENGINES];
253 u64 signal_ggtt[I915_NUM_ENGINES];
257 int (*sync_to)(struct drm_i915_gem_request *to_req,
258 struct intel_engine_cs *from,
260 int (*signal)(struct drm_i915_gem_request *signaller_req,
261 /* num_dwords needed by caller */
262 unsigned int num_dwords);
266 struct tasklet_struct irq_tasklet;
267 spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */
268 struct list_head execlist_queue;
269 unsigned int fw_domains;
270 unsigned int next_context_status_buffer;
271 unsigned int idle_lite_restore_wa;
272 bool disable_lite_restore_wa;
273 u32 ctx_desc_template;
274 u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
275 int (*emit_request)(struct drm_i915_gem_request *request);
276 int (*emit_flush)(struct drm_i915_gem_request *request,
277 u32 invalidate_domains,
279 int (*emit_bb_start)(struct drm_i915_gem_request *req,
280 u64 offset, unsigned dispatch_flags);
283 * List of objects currently involved in rendering from the
286 * Includes buffers having the contents of their GPU caches
287 * flushed, not necessarily primitives. last_read_req
288 * represents when the rendering involved will be completed.
290 * A reference is held on the buffer while on this list.
292 struct list_head active_list;
295 * List of breadcrumbs associated with GPU requests currently
298 struct list_head request_list;
301 * Seqno of request most recently submitted to request_list.
302 * Used exclusively by hang checker to avoid grabbing lock while
303 * inspecting request list.
305 u32 last_submitted_seqno;
306 unsigned user_interrupts;
308 bool gpu_caches_dirty;
310 wait_queue_head_t irq_queue;
312 struct intel_context *last_context;
314 struct intel_ring_hangcheck hangcheck;
317 struct drm_i915_gem_object *obj;
319 volatile u32 *cpu_page;
322 bool needs_cmd_parser;
325 * Table of commands the command parser needs to know about
328 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
331 * Table of registers allowed in commands that read/write registers.
333 const struct drm_i915_reg_table *reg_tables;
337 * Returns the bitmask for the length field of the specified command.
338 * Return 0 for an unrecognized/invalid command.
340 * If the command parser finds an entry for a command in the ring's
341 * cmd_tables, it gets the command's length based on the table entry.
342 * If not, it calls this function to determine the per-ring length field
343 * encoding for the command (i.e. certain opcode ranges use certain bits
344 * to encode the command length in the header).
346 u32 (*get_cmd_length_mask)(u32 cmd_header);
350 intel_engine_initialized(struct intel_engine_cs *engine)
352 return engine->dev != NULL;
355 static inline unsigned
356 intel_engine_flag(struct intel_engine_cs *engine)
358 return 1 << engine->id;
362 intel_ring_sync_index(struct intel_engine_cs *engine,
363 struct intel_engine_cs *other)
368 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
369 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
370 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
371 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
372 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
375 idx = (other - engine) - 1;
377 idx += I915_NUM_ENGINES;
383 intel_flush_status_page(struct intel_engine_cs *engine, int reg)
386 clflush(&engine->status_page.page_addr[reg]);
391 intel_read_status_page(struct intel_engine_cs *engine, int reg)
393 /* Ensure that the compiler doesn't optimize away the load. */
394 return READ_ONCE(engine->status_page.page_addr[reg]);
398 intel_write_status_page(struct intel_engine_cs *engine,
401 engine->status_page.page_addr[reg] = value;
405 * Reads a dword out of the status page, which is written to from the command
406 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
409 * The following dwords have a reserved meaning:
410 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
411 * 0x04: ring 0 head pointer
412 * 0x05: ring 1 head pointer (915-class)
413 * 0x06: ring 2 head pointer (915-class)
414 * 0x10-0x1b: Context status DWords (GM45)
415 * 0x1f: Last written status offset. (GM45)
416 * 0x20-0x2f: Reserved (Gen6+)
418 * The area from dword 0x30 to 0x3ff is available for driver usage.
420 #define I915_GEM_HWS_INDEX 0x30
421 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
422 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
423 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
425 struct intel_ringbuffer *
426 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
427 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
428 struct intel_ringbuffer *ringbuf);
429 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
430 void intel_ringbuffer_free(struct intel_ringbuffer *ring);
432 void intel_stop_engine(struct intel_engine_cs *engine);
433 void intel_cleanup_engine(struct intel_engine_cs *engine);
435 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
437 int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
438 int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
439 static inline void intel_ring_emit(struct intel_engine_cs *engine,
442 struct intel_ringbuffer *ringbuf = engine->buffer;
443 iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
446 static inline void intel_ring_emit_reg(struct intel_engine_cs *engine,
449 intel_ring_emit(engine, i915_mmio_reg_offset(reg));
451 static inline void intel_ring_advance(struct intel_engine_cs *engine)
453 struct intel_ringbuffer *ringbuf = engine->buffer;
454 ringbuf->tail &= ringbuf->size - 1;
456 int __intel_ring_space(int head, int tail, int size);
457 void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
458 bool intel_engine_stopped(struct intel_engine_cs *engine);
460 int __must_check intel_engine_idle(struct intel_engine_cs *engine);
461 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno);
462 int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
463 int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);
465 void intel_fini_pipe_control(struct intel_engine_cs *engine);
466 int intel_init_pipe_control(struct intel_engine_cs *engine);
468 int intel_init_render_ring_buffer(struct drm_device *dev);
469 int intel_init_bsd_ring_buffer(struct drm_device *dev);
470 int intel_init_bsd2_ring_buffer(struct drm_device *dev);
471 int intel_init_blt_ring_buffer(struct drm_device *dev);
472 int intel_init_vebox_ring_buffer(struct drm_device *dev);
474 u64 intel_ring_get_active_head(struct intel_engine_cs *engine);
476 int init_workarounds_ring(struct intel_engine_cs *engine);
478 static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
480 return ringbuf->tail;
484 * Arbitrary size for largest possible 'add request' sequence. The code paths
485 * are complex and variable. Empirical measurement shows that the worst case
486 * is ILK at 136 words. Reserving too much is better than reserving too little
487 * as that allows for corner cases that might have been missed. So the figure
488 * has been rounded up to 160 words.
490 #define MIN_SPACE_FOR_ADD_REQUEST 160
492 #endif /* _INTEL_RINGBUFFER_H_ */