drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 struct  intel_hw_status_page {
   5         u32             *page_addr;
   6         unsigned int    gfx_addr;
   7         struct          drm_i915_gem_object *obj;
   8 };
   9
  10 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
  11 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
  12
  13 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
  14 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
  15
  16 #define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
  17 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
  18
  19 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
  20 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
  21
  22 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
  23 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
  24
  25 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
  26 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
  27 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
  28
  29 struct  intel_ring_buffer {
  30         const char      *name;
  31         enum intel_ring_id {
  32                 RCS = 0x0,
  33                 VCS,
  34                 BCS,
  35         } id;
  36 #define I915_NUM_RINGS 3
  37         u32             mmio_base;
  38         void            __iomem *virtual_start;
  39         struct          drm_device *dev;
  40         struct          drm_i915_gem_object *obj;
  41
  42         u32             head;
  43         u32             tail;
  44         int             space;
  45         int             size;
  46         int             effective_size;
  47         struct intel_hw_status_page status_page;
  48
  49         /** We track the position of the requests in the ring buffer, and
  50          * when each is retired we increment last_retired_head as the GPU
  51          * must have finished processing the request and so we know we
  52          * can advance the ringbuffer up to that position.
  53          *
  54          * last_retired_head is set to -1 after the value is consumed so
  55          * we can detect new retirements.
  56          */
  57         u32             last_retired_head;
  58
  59         u32             irq_refcount;           /* protected by dev_priv->irq_lock */
  60         u32             irq_enable_mask;        /* bitmask to enable ring interrupt */
  61         u32             trace_irq_seqno;
  62         u32             sync_seqno[I915_NUM_RINGS-1];
  63         bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  64         void            (*irq_put)(struct intel_ring_buffer *ring);
  65
  66         int             (*init)(struct intel_ring_buffer *ring);
  67
  68         void            (*write_tail)(struct intel_ring_buffer *ring,
  69                                       u32 value);
  70         int __must_check (*flush)(struct intel_ring_buffer *ring,
  71                                   u32   invalidate_domains,
  72                                   u32   flush_domains);
  73         int             (*add_request)(struct intel_ring_buffer *ring);
  74         /* Some chipsets are not quite as coherent as advertised and need
  75          * an expensive kick to force a true read of the up-to-date seqno.
  76          * However, the up-to-date seqno is not always required and the last
  77          * seen value is good enough. Note that the seqno will always be
  78          * monotonic, even if not coherent.
  79          */
  80         u32             (*get_seqno)(struct intel_ring_buffer *ring,
  81                                      bool lazy_coherency);
  82         int             (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
  83                                                u32 offset, u32 length,
  84                                                unsigned flags);
  85 #define I915_DISPATCH_SECURE 0x1
  86         void            (*cleanup)(struct intel_ring_buffer *ring);
  87         int             (*sync_to)(struct intel_ring_buffer *ring,
  88                                    struct intel_ring_buffer *to,
  89                                    u32 seqno);
  90
  91         u32             semaphore_register[3]; /*our mbox written by others */
  92         u32             signal_mbox[2]; /* mboxes this ring signals to */
  93         /**
  94          * List of objects currently involved in rendering from the
  95          * ringbuffer.
  96          *
  97          * Includes buffers having the contents of their GPU caches
  98          * flushed, not necessarily primitives.  last_rendering_seqno
  99          * represents when the rendering involved will be completed.
 100          *
 101          * A reference is held on the buffer while on this list.
 102          */
 103         struct list_head active_list;
 104
 105         /**
 106          * List of breadcrumbs associated with GPU requests currently
 107          * outstanding.
 108          */
 109         struct list_head request_list;
 110
 111         /**
 112          * Do we have some not yet emitted requests outstanding?
 113          */
 114         u32 outstanding_lazy_request;
 115         bool gpu_caches_dirty;
 116
 117         wait_queue_head_t irq_queue;
 118
 119         /**
 120          * Do an explicit TLB flush before MI_SET_CONTEXT
 121          */
 122         bool itlb_before_ctx_switch;
 123         struct i915_hw_context *default_context;
 124         struct drm_i915_gem_object *last_context_obj;
 125
 126         void *private;
 127 };
 128
 129 static inline bool
 130 intel_ring_initialized(struct intel_ring_buffer *ring)
 131 {
 132         return ring->obj != NULL;
 133 }
 134
 135 static inline unsigned
 136 intel_ring_flag(struct intel_ring_buffer *ring)
 137 {
 138         return 1 << ring->id;
 139 }
 140
 141 static inline u32
 142 intel_ring_sync_index(struct intel_ring_buffer *ring,
 143                       struct intel_ring_buffer *other)
 144 {
 145         int idx;
 146
 147         /*
 148          * cs -> 0 = vcs, 1 = bcs
 149          * vcs -> 0 = bcs, 1 = cs,
 150          * bcs -> 0 = cs, 1 = vcs.
 151          */
 152
 153         idx = (other - ring) - 1;
 154         if (idx < 0)
 155                 idx += I915_NUM_RINGS;
 156
 157         return idx;
 158 }
 159
 160 static inline u32
 161 intel_read_status_page(struct intel_ring_buffer *ring,
 162                        int reg)
 163 {
 164         /* Ensure that the compiler doesn't optimize away the load. */
 165         barrier();
 166         return ring->status_page.page_addr[reg];
 167 }
 168
 169 /**
 170  * Reads a dword out of the status page, which is written to from the command
 171  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 172  * MI_STORE_DATA_IMM.
 173  *
 174  * The following dwords have a reserved meaning:
 175  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 176  * 0x04: ring 0 head pointer
 177  * 0x05: ring 1 head pointer (915-class)
 178  * 0x06: ring 2 head pointer (915-class)
 179  * 0x10-0x1b: Context status DWords (GM45)
 180  * 0x1f: Last written status offset. (GM45)
 181  *
 182  * The area from dword 0x20 to 0x3ff is available for driver usage.
 183  */
 184 #define I915_GEM_HWS_INDEX              0x20
 185 #define I915_GEM_HWS_SCRATCH_INDEX      0x30
 186 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 187
 188 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 189
 190 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
 191 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
 192                                    u32 data)
 193 {
 194         iowrite32(data, ring->virtual_start + ring->tail);
 195         ring->tail += 4;
 196 }
 197 void intel_ring_advance(struct intel_ring_buffer *ring);
 198 int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
 199 int __must_check intel_ring_handle_seqno_wrap(struct intel_ring_buffer *ring);
 200 int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
 201 int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
 202
 203 int intel_init_render_ring_buffer(struct drm_device *dev);
 204 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 205 int intel_init_blt_ring_buffer(struct drm_device *dev);
 206
 207 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
 208 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 209
 210 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
 211 {
 212         return ring->tail;
 213 }
 214
 215 static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
 216 {
 217         BUG_ON(ring->outstanding_lazy_request == 0);
 218         return ring->outstanding_lazy_request;
 219 }
 220
 221 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
 222 {
 223         if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
 224                 ring->trace_irq_seqno = seqno;
 225 }
 226
 227 /* DRI warts */
 228 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 229
 230 #endif /* _INTEL_RINGBUFFER_H_ */