1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
4 #include <linux/hashtable.h>
5 #include "i915_gem_batch_pool.h"
6 #include "i915_gem_request.h"
8 #define I915_CMD_HASH_ORDER 9
10 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
11 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
12 * to give some inclination as to some of the magic values used in the various
15 #define CACHELINE_BYTES 64
16 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
19 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
20 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
21 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
23 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
24 * cacheline, the Head Pointer must not be greater than the Tail
27 #define I915_RING_FREE_SPACE 64
29 struct intel_hw_status_page {
35 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
36 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
38 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
39 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
41 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
42 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
44 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
45 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
47 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
48 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
50 #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
51 #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
53 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
54 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
56 #define gen8_semaphore_seqno_size sizeof(uint64_t)
57 #define GEN8_SEMAPHORE_OFFSET(__from, __to) \
58 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
59 #define GEN8_SIGNAL_OFFSET(__ring, to) \
60 (dev_priv->semaphore->node.start + \
61 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
62 #define GEN8_WAIT_OFFSET(__ring, from) \
63 (dev_priv->semaphore->node.start + \
64 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
66 enum intel_engine_hangcheck_action {
74 #define HANGCHECK_SCORE_RING_HUNG 31
76 struct intel_engine_hangcheck {
80 enum intel_engine_hangcheck_action action;
82 u32 instdone[I915_NUM_INSTDONE_REG];
89 struct intel_engine_cs *engine;
91 struct list_head request_list;
99 /** We track the position of the requests in the ring buffer, and
100 * when each is retired we increment last_retired_head as the GPU
101 * must have finished processing the request and so we know we
102 * can advance the ringbuffer up to that position.
104 * last_retired_head is set to -1 after the value is consumed so
105 * we can detect new retirements.
107 u32 last_retired_head;
110 struct i915_gem_context;
111 struct drm_i915_reg_table;
114 * we use a single page to load ctx workarounds so all of these
115 * values are referred in terms of dwords
117 * struct i915_wa_ctx_bb:
118 * offset: specifies batch starting position, also helpful in case
119 * if we want to have multiple batches at different offsets based on
120 * some criteria. It is not a requirement at the moment but provides
121 * an option for future use.
122 * size: size of the batch in DWORDS
124 struct i915_ctx_workarounds {
125 struct i915_wa_ctx_bb {
128 } indirect_ctx, per_ctx;
129 struct i915_vma *vma;
132 struct drm_i915_gem_request;
134 struct intel_engine_cs {
135 struct drm_i915_private *i915;
137 enum intel_engine_id {
141 VCS2, /* Keep instances of the same type engine together. */
144 #define I915_NUM_ENGINES 5
145 #define _VCS(n) (VCS + (n))
146 unsigned int exec_id;
147 enum intel_engine_hw_id {
154 enum intel_engine_hw_id guc_id; /* XXX same as hw_id? */
157 unsigned int irq_shift;
158 struct intel_ring *buffer;
160 /* Rather than have every client wait upon all user interrupts,
161 * with the herd waking after every interrupt and each doing the
162 * heavyweight seqno dance, we delegate the task (of being the
163 * bottom-half of the user interrupt) to the first client. After
164 * every interrupt, we wake up one client, who does the heavyweight
165 * coherent seqno read and either goes back to sleep (if incomplete),
166 * or wakes up all the completed clients in parallel, before then
167 * transferring the bottom-half status to the next client in the queue.
169 * Compared to walking the entire list of waiters in a single dedicated
170 * bottom-half, we reduce the latency of the first waiter by avoiding
171 * a context switch, but incur additional coherent seqno reads when
172 * following the chain of request breadcrumbs. Since it is most likely
173 * that we have a single client waiting on each seqno, then reducing
174 * the overhead of waking that client is much preferred.
176 struct intel_breadcrumbs {
177 struct task_struct __rcu *irq_seqno_bh; /* bh for interrupts */
180 spinlock_t lock; /* protects the lists of requests */
181 struct rb_root waiters; /* sorted by retirement, priority */
182 struct rb_root signals; /* sorted by retirement */
183 struct intel_wait *first_wait; /* oldest waiter by retirement */
184 struct task_struct *signaler; /* used for fence signalling */
185 struct drm_i915_gem_request *first_signal;
186 struct timer_list fake_irq; /* used after a missed interrupt */
187 struct timer_list hangcheck; /* detect missed interrupts */
189 unsigned long timeout;
191 bool irq_enabled : 1;
192 bool rpm_wakelock : 1;
196 * A pool of objects to use as shadow copies of client batch buffers
197 * when the command parser is enabled. Prevents the client from
198 * modifying the batch contents after software parsing.
200 struct i915_gem_batch_pool batch_pool;
202 struct intel_hw_status_page status_page;
203 struct i915_ctx_workarounds wa_ctx;
204 struct i915_vma *scratch;
206 u32 irq_keep_mask; /* always keep these interrupts */
207 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
208 void (*irq_enable)(struct intel_engine_cs *engine);
209 void (*irq_disable)(struct intel_engine_cs *engine);
211 int (*init_hw)(struct intel_engine_cs *engine);
212 void (*reset_hw)(struct intel_engine_cs *engine,
213 struct drm_i915_gem_request *req);
215 int (*init_context)(struct drm_i915_gem_request *req);
217 int (*emit_flush)(struct drm_i915_gem_request *request,
219 #define EMIT_INVALIDATE BIT(0)
220 #define EMIT_FLUSH BIT(1)
221 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
222 int (*emit_bb_start)(struct drm_i915_gem_request *req,
223 u64 offset, u32 length,
224 unsigned int dispatch_flags);
225 #define I915_DISPATCH_SECURE BIT(0)
226 #define I915_DISPATCH_PINNED BIT(1)
227 #define I915_DISPATCH_RS BIT(2)
228 int (*emit_request)(struct drm_i915_gem_request *req);
230 /* Pass the request to the hardware queue (e.g. directly into
231 * the legacy ringbuffer or to the end of an execlist).
233 * This is called from an atomic context with irqs disabled; must
236 void (*submit_request)(struct drm_i915_gem_request *req);
238 /* Some chipsets are not quite as coherent as advertised and need
239 * an expensive kick to force a true read of the up-to-date seqno.
240 * However, the up-to-date seqno is not always required and the last
241 * seen value is good enough. Note that the seqno will always be
242 * monotonic, even if not coherent.
244 void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
245 void (*cleanup)(struct intel_engine_cs *engine);
247 /* GEN8 signal/wait table - never trust comments!
248 * signal to signal to signal to signal to signal to
249 * RCS VCS BCS VECS VCS2
250 * --------------------------------------------------------------------
251 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
252 * |-------------------------------------------------------------------
253 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
254 * |-------------------------------------------------------------------
255 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
256 * |-------------------------------------------------------------------
257 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
258 * |-------------------------------------------------------------------
259 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
260 * |-------------------------------------------------------------------
263 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
264 * ie. transpose of g(x, y)
266 * sync from sync from sync from sync from sync from
267 * RCS VCS BCS VECS VCS2
268 * --------------------------------------------------------------------
269 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
270 * |-------------------------------------------------------------------
271 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
272 * |-------------------------------------------------------------------
273 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
274 * |-------------------------------------------------------------------
275 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
276 * |-------------------------------------------------------------------
277 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
278 * |-------------------------------------------------------------------
281 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
282 * ie. transpose of f(x, y)
285 u32 sync_seqno[I915_NUM_ENGINES-1];
288 #define GEN6_SEMAPHORE_LAST VECS_HW
289 #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
290 #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
292 /* our mbox written by others */
293 u32 wait[GEN6_NUM_SEMAPHORES];
294 /* mboxes this ring signals to */
295 i915_reg_t signal[GEN6_NUM_SEMAPHORES];
297 u64 signal_ggtt[I915_NUM_ENGINES];
301 int (*sync_to)(struct drm_i915_gem_request *req,
302 struct drm_i915_gem_request *signal);
303 int (*signal)(struct drm_i915_gem_request *req);
307 struct tasklet_struct irq_tasklet;
308 spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */
309 struct execlist_port {
310 struct drm_i915_gem_request *request;
313 struct list_head execlist_queue;
314 unsigned int fw_domains;
315 bool disable_lite_restore_wa;
317 u32 ctx_desc_template;
320 * List of breadcrumbs associated with GPU requests currently
323 struct list_head request_list;
326 * Seqno of request most recently submitted to request_list.
327 * Used exclusively by hang checker to avoid grabbing lock while
328 * inspecting request list.
330 u32 last_submitted_seqno;
331 u32 last_pending_seqno;
333 /* An RCU guarded pointer to the last request. No reference is
334 * held to the request, users must carefully acquire a reference to
335 * the request using i915_gem_active_get_rcu(), or hold the
338 struct i915_gem_active last_request;
340 struct i915_gem_context *last_context;
342 struct intel_engine_hangcheck hangcheck;
344 bool needs_cmd_parser;
347 * Table of commands the command parser needs to know about
350 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
353 * Table of registers allowed in commands that read/write registers.
355 const struct drm_i915_reg_table *reg_tables;
359 * Returns the bitmask for the length field of the specified command.
360 * Return 0 for an unrecognized/invalid command.
362 * If the command parser finds an entry for a command in the engine's
363 * cmd_tables, it gets the command's length based on the table entry.
364 * If not, it calls this function to determine the per-engine length
365 * field encoding for the command (i.e. different opcode ranges use
366 * certain bits to encode the command length in the header).
368 u32 (*get_cmd_length_mask)(u32 cmd_header);
372 intel_engine_initialized(const struct intel_engine_cs *engine)
374 return engine->i915 != NULL;
377 static inline unsigned
378 intel_engine_flag(const struct intel_engine_cs *engine)
380 return 1 << engine->id;
384 intel_engine_sync_index(struct intel_engine_cs *engine,
385 struct intel_engine_cs *other)
390 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
391 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
392 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
393 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
394 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
397 idx = (other - engine) - 1;
399 idx += I915_NUM_ENGINES;
405 intel_flush_status_page(struct intel_engine_cs *engine, int reg)
408 clflush(&engine->status_page.page_addr[reg]);
413 intel_read_status_page(struct intel_engine_cs *engine, int reg)
415 /* Ensure that the compiler doesn't optimize away the load. */
416 return READ_ONCE(engine->status_page.page_addr[reg]);
420 intel_write_status_page(struct intel_engine_cs *engine,
423 engine->status_page.page_addr[reg] = value;
427 * Reads a dword out of the status page, which is written to from the command
428 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
431 * The following dwords have a reserved meaning:
432 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
433 * 0x04: ring 0 head pointer
434 * 0x05: ring 1 head pointer (915-class)
435 * 0x06: ring 2 head pointer (915-class)
436 * 0x10-0x1b: Context status DWords (GM45)
437 * 0x1f: Last written status offset. (GM45)
438 * 0x20-0x2f: Reserved (Gen6+)
440 * The area from dword 0x30 to 0x3ff is available for driver usage.
442 #define I915_GEM_HWS_INDEX 0x30
443 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
444 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
445 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
448 intel_engine_create_ring(struct intel_engine_cs *engine, int size);
449 int intel_ring_pin(struct intel_ring *ring);
450 void intel_ring_unpin(struct intel_ring *ring);
451 void intel_ring_free(struct intel_ring *ring);
453 void intel_engine_stop(struct intel_engine_cs *engine);
454 void intel_engine_cleanup(struct intel_engine_cs *engine);
456 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv);
458 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
460 int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
461 int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
463 static inline void intel_ring_emit(struct intel_ring *ring, u32 data)
465 *(uint32_t *)(ring->vaddr + ring->tail) = data;
469 static inline void intel_ring_emit_reg(struct intel_ring *ring, i915_reg_t reg)
471 intel_ring_emit(ring, i915_mmio_reg_offset(reg));
474 static inline void intel_ring_advance(struct intel_ring *ring)
478 * This serves as a placeholder in the code so that the reader
479 * can compare against the preceding intel_ring_begin() and
480 * check that the number of dwords emitted matches the space
481 * reserved for the command packet (i.e. the value passed to
482 * intel_ring_begin()).
486 static inline u32 intel_ring_offset(struct intel_ring *ring, u32 value)
488 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
489 return value & (ring->size - 1);
492 int __intel_ring_space(int head, int tail, int size);
493 void intel_ring_update_space(struct intel_ring *ring);
495 void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
497 void intel_engine_setup_common(struct intel_engine_cs *engine);
498 int intel_engine_init_common(struct intel_engine_cs *engine);
499 int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
500 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
502 static inline int intel_engine_idle(struct intel_engine_cs *engine,
505 /* Wait upon the last request to be completed */
506 return i915_gem_active_wait_unlocked(&engine->last_request,
510 int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
511 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
512 int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine);
513 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
514 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
516 u64 intel_engine_get_active_head(struct intel_engine_cs *engine);
517 static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
519 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
522 int init_workarounds_ring(struct intel_engine_cs *engine);
525 * Arbitrary size for largest possible 'add request' sequence. The code paths
526 * are complex and variable. Empirical measurement shows that the worst case
527 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
528 * we need to allocate double the largest single packet within that emission
529 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
531 #define MIN_SPACE_FOR_ADD_REQUEST 336
533 static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
535 return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
538 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
539 int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
541 static inline void intel_wait_init(struct intel_wait *wait, u32 seqno)
547 static inline bool intel_wait_complete(const struct intel_wait *wait)
549 return RB_EMPTY_NODE(&wait->node);
552 bool intel_engine_add_wait(struct intel_engine_cs *engine,
553 struct intel_wait *wait);
554 void intel_engine_remove_wait(struct intel_engine_cs *engine,
555 struct intel_wait *wait);
556 void intel_engine_enable_signaling(struct drm_i915_gem_request *request);
558 static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
560 return rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh);
563 static inline bool intel_engine_wakeup(const struct intel_engine_cs *engine)
567 /* Note that for this not to dangerously chase a dangling pointer,
568 * we must hold the rcu_read_lock here.
570 * Also note that tsk is likely to be in !TASK_RUNNING state so an
571 * early test for tsk->state != TASK_RUNNING before wake_up_process()
572 * is unlikely to be beneficial.
574 if (intel_engine_has_waiter(engine)) {
575 struct task_struct *tsk;
578 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
580 wakeup = wake_up_process(tsk);
587 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
588 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
589 unsigned int intel_kick_waiters(struct drm_i915_private *i915);
590 unsigned int intel_kick_signalers(struct drm_i915_private *i915);
592 static inline bool intel_engine_is_active(struct intel_engine_cs *engine)
594 return i915_gem_active_isset(&engine->last_request);
597 #endif /* _INTEL_RINGBUFFER_H_ */