1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
4 #include <linux/hashtable.h>
5 #include "i915_gem_batch_pool.h"
7 #define I915_CMD_HASH_ORDER 9
9 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
10 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
11 * to give some inclination as to some of the magic values used in the various
14 #define CACHELINE_BYTES 64
15 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
18 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
19 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
20 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
22 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
23 * cacheline, the Head Pointer must not be greater than the Tail
26 #define I915_RING_FREE_SPACE 64
28 struct intel_hw_status_page {
30 unsigned int gfx_addr;
31 struct drm_i915_gem_object *obj;
34 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
35 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
37 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
38 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
40 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
41 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
43 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
44 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
46 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
47 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
49 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
50 #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
52 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
53 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
55 #define gen8_semaphore_seqno_size sizeof(uint64_t)
56 #define GEN8_SEMAPHORE_OFFSET(__from, __to) \
57 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
58 #define GEN8_SIGNAL_OFFSET(__ring, to) \
59 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
60 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
61 #define GEN8_WAIT_OFFSET(__ring, from) \
62 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
63 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
65 enum intel_ring_hangcheck_action {
73 #define HANGCHECK_SCORE_RING_HUNG 31
75 struct intel_ring_hangcheck {
78 unsigned user_interrupts;
80 enum intel_ring_hangcheck_action action;
82 u32 instdone[I915_NUM_INSTDONE_REG];
85 struct intel_ringbuffer {
86 struct drm_i915_gem_object *obj;
87 void __iomem *virtual_start;
90 struct intel_engine_cs *engine;
91 struct list_head link;
99 /** We track the position of the requests in the ring buffer, and
100 * when each is retired we increment last_retired_head as the GPU
101 * must have finished processing the request and so we know we
102 * can advance the ringbuffer up to that position.
104 * last_retired_head is set to -1 after the value is consumed so
105 * we can detect new retirements.
107 u32 last_retired_head;
110 struct i915_gem_context;
111 struct drm_i915_reg_table;
114 * we use a single page to load ctx workarounds so all of these
115 * values are referred in terms of dwords
117 * struct i915_wa_ctx_bb:
118 * offset: specifies batch starting position, also helpful in case
119 * if we want to have multiple batches at different offsets based on
120 * some criteria. It is not a requirement at the moment but provides
121 * an option for future use.
122 * size: size of the batch in DWORDS
124 struct i915_ctx_workarounds {
125 struct i915_wa_ctx_bb {
128 } indirect_ctx, per_ctx;
129 struct drm_i915_gem_object *obj;
132 struct intel_engine_cs {
133 struct drm_i915_private *i915;
135 enum intel_engine_id {
139 VCS2, /* Keep instances of the same type engine together. */
142 #define I915_NUM_ENGINES 5
143 #define _VCS(n) (VCS + (n))
144 unsigned int exec_id;
146 unsigned int guc_id; /* XXX same as hw_id? */
148 struct intel_ringbuffer *buffer;
149 struct list_head buffers;
152 * A pool of objects to use as shadow copies of client batch buffers
153 * when the command parser is enabled. Prevents the client from
154 * modifying the batch contents after software parsing.
156 struct i915_gem_batch_pool batch_pool;
158 struct intel_hw_status_page status_page;
159 struct i915_ctx_workarounds wa_ctx;
161 unsigned irq_refcount; /* protected by dev_priv->irq_lock */
162 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
163 struct drm_i915_gem_request *trace_irq_req;
164 bool __must_check (*irq_get)(struct intel_engine_cs *ring);
165 void (*irq_put)(struct intel_engine_cs *ring);
167 int (*init_hw)(struct intel_engine_cs *ring);
169 int (*init_context)(struct drm_i915_gem_request *req);
171 void (*write_tail)(struct intel_engine_cs *ring,
173 int __must_check (*flush)(struct drm_i915_gem_request *req,
174 u32 invalidate_domains,
176 int (*add_request)(struct drm_i915_gem_request *req);
177 /* Some chipsets are not quite as coherent as advertised and need
178 * an expensive kick to force a true read of the up-to-date seqno.
179 * However, the up-to-date seqno is not always required and the last
180 * seen value is good enough. Note that the seqno will always be
181 * monotonic, even if not coherent.
183 void (*irq_seqno_barrier)(struct intel_engine_cs *ring);
184 u32 (*get_seqno)(struct intel_engine_cs *ring);
185 void (*set_seqno)(struct intel_engine_cs *ring,
187 int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
188 u64 offset, u32 length,
189 unsigned dispatch_flags);
190 #define I915_DISPATCH_SECURE 0x1
191 #define I915_DISPATCH_PINNED 0x2
192 #define I915_DISPATCH_RS 0x4
193 void (*cleanup)(struct intel_engine_cs *ring);
195 /* GEN8 signal/wait table - never trust comments!
196 * signal to signal to signal to signal to signal to
197 * RCS VCS BCS VECS VCS2
198 * --------------------------------------------------------------------
199 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
200 * |-------------------------------------------------------------------
201 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
202 * |-------------------------------------------------------------------
203 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
204 * |-------------------------------------------------------------------
205 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
206 * |-------------------------------------------------------------------
207 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
208 * |-------------------------------------------------------------------
211 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
212 * ie. transpose of g(x, y)
214 * sync from sync from sync from sync from sync from
215 * RCS VCS BCS VECS VCS2
216 * --------------------------------------------------------------------
217 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
218 * |-------------------------------------------------------------------
219 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
220 * |-------------------------------------------------------------------
221 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
222 * |-------------------------------------------------------------------
223 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
224 * |-------------------------------------------------------------------
225 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
226 * |-------------------------------------------------------------------
229 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
230 * ie. transpose of f(x, y)
233 u32 sync_seqno[I915_NUM_ENGINES-1];
237 /* our mbox written by others */
238 u32 wait[I915_NUM_ENGINES];
239 /* mboxes this ring signals to */
240 i915_reg_t signal[I915_NUM_ENGINES];
242 u64 signal_ggtt[I915_NUM_ENGINES];
246 int (*sync_to)(struct drm_i915_gem_request *to_req,
247 struct intel_engine_cs *from,
249 int (*signal)(struct drm_i915_gem_request *signaller_req,
250 /* num_dwords needed by caller */
251 unsigned int num_dwords);
255 struct tasklet_struct irq_tasklet;
256 spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */
257 struct list_head execlist_queue;
258 unsigned int fw_domains;
259 unsigned int next_context_status_buffer;
260 unsigned int idle_lite_restore_wa;
261 bool disable_lite_restore_wa;
262 u32 ctx_desc_template;
263 u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
264 int (*emit_request)(struct drm_i915_gem_request *request);
265 int (*emit_flush)(struct drm_i915_gem_request *request,
266 u32 invalidate_domains,
268 int (*emit_bb_start)(struct drm_i915_gem_request *req,
269 u64 offset, unsigned dispatch_flags);
272 * List of objects currently involved in rendering from the
275 * Includes buffers having the contents of their GPU caches
276 * flushed, not necessarily primitives. last_read_req
277 * represents when the rendering involved will be completed.
279 * A reference is held on the buffer while on this list.
281 struct list_head active_list;
284 * List of breadcrumbs associated with GPU requests currently
287 struct list_head request_list;
290 * Seqno of request most recently submitted to request_list.
291 * Used exclusively by hang checker to avoid grabbing lock while
292 * inspecting request list.
294 u32 last_submitted_seqno;
295 unsigned user_interrupts;
297 bool gpu_caches_dirty;
299 wait_queue_head_t irq_queue;
301 struct i915_gem_context *last_context;
303 struct intel_ring_hangcheck hangcheck;
306 struct drm_i915_gem_object *obj;
308 volatile u32 *cpu_page;
311 bool needs_cmd_parser;
314 * Table of commands the command parser needs to know about
317 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
320 * Table of registers allowed in commands that read/write registers.
322 const struct drm_i915_reg_table *reg_tables;
326 * Returns the bitmask for the length field of the specified command.
327 * Return 0 for an unrecognized/invalid command.
329 * If the command parser finds an entry for a command in the ring's
330 * cmd_tables, it gets the command's length based on the table entry.
331 * If not, it calls this function to determine the per-ring length field
332 * encoding for the command (i.e. certain opcode ranges use certain bits
333 * to encode the command length in the header).
335 u32 (*get_cmd_length_mask)(u32 cmd_header);
339 intel_engine_initialized(struct intel_engine_cs *engine)
341 return engine->i915 != NULL;
344 static inline unsigned
345 intel_engine_flag(struct intel_engine_cs *engine)
347 return 1 << engine->id;
351 intel_ring_sync_index(struct intel_engine_cs *engine,
352 struct intel_engine_cs *other)
357 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
358 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
359 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
360 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
361 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
364 idx = (other - engine) - 1;
366 idx += I915_NUM_ENGINES;
372 intel_flush_status_page(struct intel_engine_cs *engine, int reg)
375 clflush(&engine->status_page.page_addr[reg]);
380 intel_read_status_page(struct intel_engine_cs *engine, int reg)
382 /* Ensure that the compiler doesn't optimize away the load. */
383 return READ_ONCE(engine->status_page.page_addr[reg]);
387 intel_write_status_page(struct intel_engine_cs *engine,
390 engine->status_page.page_addr[reg] = value;
394 * Reads a dword out of the status page, which is written to from the command
395 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
398 * The following dwords have a reserved meaning:
399 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
400 * 0x04: ring 0 head pointer
401 * 0x05: ring 1 head pointer (915-class)
402 * 0x06: ring 2 head pointer (915-class)
403 * 0x10-0x1b: Context status DWords (GM45)
404 * 0x1f: Last written status offset. (GM45)
405 * 0x20-0x2f: Reserved (Gen6+)
407 * The area from dword 0x30 to 0x3ff is available for driver usage.
409 #define I915_GEM_HWS_INDEX 0x30
410 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
411 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
412 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
414 struct intel_ringbuffer *
415 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
416 int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
417 struct intel_ringbuffer *ringbuf);
418 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
419 void intel_ringbuffer_free(struct intel_ringbuffer *ring);
421 void intel_stop_engine(struct intel_engine_cs *engine);
422 void intel_cleanup_engine(struct intel_engine_cs *engine);
424 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
426 int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
427 int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
428 static inline void intel_ring_emit(struct intel_engine_cs *engine,
431 struct intel_ringbuffer *ringbuf = engine->buffer;
432 iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
435 static inline void intel_ring_emit_reg(struct intel_engine_cs *engine,
438 intel_ring_emit(engine, i915_mmio_reg_offset(reg));
440 static inline void intel_ring_advance(struct intel_engine_cs *engine)
442 struct intel_ringbuffer *ringbuf = engine->buffer;
443 ringbuf->tail &= ringbuf->size - 1;
445 int __intel_ring_space(int head, int tail, int size);
446 void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
447 bool intel_engine_stopped(struct intel_engine_cs *engine);
449 int __must_check intel_engine_idle(struct intel_engine_cs *engine);
450 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno);
451 int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
452 int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);
454 void intel_fini_pipe_control(struct intel_engine_cs *engine);
455 int intel_init_pipe_control(struct intel_engine_cs *engine);
457 int intel_init_render_ring_buffer(struct drm_device *dev);
458 int intel_init_bsd_ring_buffer(struct drm_device *dev);
459 int intel_init_bsd2_ring_buffer(struct drm_device *dev);
460 int intel_init_blt_ring_buffer(struct drm_device *dev);
461 int intel_init_vebox_ring_buffer(struct drm_device *dev);
463 u64 intel_ring_get_active_head(struct intel_engine_cs *engine);
465 int init_workarounds_ring(struct intel_engine_cs *engine);
467 static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
469 return ringbuf->tail;
473 * Arbitrary size for largest possible 'add request' sequence. The code paths
474 * are complex and variable. Empirical measurement shows that the worst case
475 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
476 * we need to allocate double the largest single packet within that emission
477 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
479 #define MIN_SPACE_FOR_ADD_REQUEST 336
481 static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
483 return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR;
486 #endif /* _INTEL_RINGBUFFER_H_ */