1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
4 #include <linux/hashtable.h>
5 #include "i915_gem_batch_pool.h"
6 #include "i915_gem_request.h"
8 #define I915_CMD_HASH_ORDER 9
10 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
11 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
12 * to give some inclination as to some of the magic values used in the various
15 #define CACHELINE_BYTES 64
16 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
19 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
20 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
21 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
23 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
24 * cacheline, the Head Pointer must not be greater than the Tail
27 #define I915_RING_FREE_SPACE 64
29 struct intel_hw_status_page {
35 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
36 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
38 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
39 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
41 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
42 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
44 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
45 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
47 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
48 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
50 #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
51 #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
53 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
54 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
56 #define gen8_semaphore_seqno_size sizeof(uint64_t)
57 #define GEN8_SEMAPHORE_OFFSET(__from, __to) \
58 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
59 #define GEN8_SIGNAL_OFFSET(__ring, to) \
60 (dev_priv->semaphore->node.start + \
61 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
62 #define GEN8_WAIT_OFFSET(__ring, from) \
63 (dev_priv->semaphore->node.start + \
64 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
66 enum intel_engine_hangcheck_action {
74 #define HANGCHECK_SCORE_RING_HUNG 31
76 #define I915_MAX_SLICES 3
77 #define I915_MAX_SUBSLICES 3
79 #define instdone_slice_mask(dev_priv__) \
80 (INTEL_GEN(dev_priv__) == 7 ? \
81 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
83 #define instdone_subslice_mask(dev_priv__) \
84 (INTEL_GEN(dev_priv__) == 7 ? \
85 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)
87 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
88 for ((slice__) = 0, (subslice__) = 0; \
89 (slice__) < I915_MAX_SLICES; \
90 (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
91 (slice__) += ((subslice__) == 0)) \
92 for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
93 (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
95 struct intel_instdone {
97 /* The following exist only in the RCS engine */
99 u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
100 u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
103 struct intel_engine_hangcheck {
107 enum intel_engine_hangcheck_action action;
109 struct intel_instdone instdone;
113 struct i915_vma *vma;
116 struct intel_engine_cs *engine;
118 struct list_head request_list;
126 /** We track the position of the requests in the ring buffer, and
127 * when each is retired we increment last_retired_head as the GPU
128 * must have finished processing the request and so we know we
129 * can advance the ringbuffer up to that position.
131 * last_retired_head is set to -1 after the value is consumed so
132 * we can detect new retirements.
134 u32 last_retired_head;
137 struct i915_gem_context;
138 struct drm_i915_reg_table;
141 * we use a single page to load ctx workarounds so all of these
142 * values are referred in terms of dwords
144 * struct i915_wa_ctx_bb:
145 * offset: specifies batch starting position, also helpful in case
146 * if we want to have multiple batches at different offsets based on
147 * some criteria. It is not a requirement at the moment but provides
148 * an option for future use.
149 * size: size of the batch in DWORDS
151 struct i915_ctx_workarounds {
152 struct i915_wa_ctx_bb {
155 } indirect_ctx, per_ctx;
156 struct i915_vma *vma;
159 struct drm_i915_gem_request;
160 struct intel_render_state;
162 struct intel_engine_cs {
163 struct drm_i915_private *i915;
165 enum intel_engine_id {
169 VCS2, /* Keep instances of the same type engine together. */
172 #define I915_NUM_ENGINES 5
173 #define _VCS(n) (VCS + (n))
174 unsigned int exec_id;
175 enum intel_engine_hw_id {
182 enum intel_engine_hw_id guc_id; /* XXX same as hw_id? */
185 unsigned int irq_shift;
186 struct intel_ring *buffer;
188 struct intel_render_state *render_state;
190 /* Rather than have every client wait upon all user interrupts,
191 * with the herd waking after every interrupt and each doing the
192 * heavyweight seqno dance, we delegate the task (of being the
193 * bottom-half of the user interrupt) to the first client. After
194 * every interrupt, we wake up one client, who does the heavyweight
195 * coherent seqno read and either goes back to sleep (if incomplete),
196 * or wakes up all the completed clients in parallel, before then
197 * transferring the bottom-half status to the next client in the queue.
199 * Compared to walking the entire list of waiters in a single dedicated
200 * bottom-half, we reduce the latency of the first waiter by avoiding
201 * a context switch, but incur additional coherent seqno reads when
202 * following the chain of request breadcrumbs. Since it is most likely
203 * that we have a single client waiting on each seqno, then reducing
204 * the overhead of waking that client is much preferred.
206 struct intel_breadcrumbs {
207 struct task_struct __rcu *irq_seqno_bh; /* bh for interrupts */
210 spinlock_t lock; /* protects the lists of requests */
211 struct rb_root waiters; /* sorted by retirement, priority */
212 struct rb_root signals; /* sorted by retirement */
213 struct intel_wait *first_wait; /* oldest waiter by retirement */
214 struct task_struct *signaler; /* used for fence signalling */
215 struct drm_i915_gem_request *first_signal;
216 struct timer_list fake_irq; /* used after a missed interrupt */
217 struct timer_list hangcheck; /* detect missed interrupts */
219 unsigned long timeout;
221 bool irq_enabled : 1;
222 bool rpm_wakelock : 1;
226 * A pool of objects to use as shadow copies of client batch buffers
227 * when the command parser is enabled. Prevents the client from
228 * modifying the batch contents after software parsing.
230 struct i915_gem_batch_pool batch_pool;
232 struct intel_hw_status_page status_page;
233 struct i915_ctx_workarounds wa_ctx;
234 struct i915_vma *scratch;
236 u32 irq_keep_mask; /* always keep these interrupts */
237 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
238 void (*irq_enable)(struct intel_engine_cs *engine);
239 void (*irq_disable)(struct intel_engine_cs *engine);
241 int (*init_hw)(struct intel_engine_cs *engine);
242 void (*reset_hw)(struct intel_engine_cs *engine,
243 struct drm_i915_gem_request *req);
245 int (*init_context)(struct drm_i915_gem_request *req);
247 int (*emit_flush)(struct drm_i915_gem_request *request,
249 #define EMIT_INVALIDATE BIT(0)
250 #define EMIT_FLUSH BIT(1)
251 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
252 int (*emit_bb_start)(struct drm_i915_gem_request *req,
253 u64 offset, u32 length,
254 unsigned int dispatch_flags);
255 #define I915_DISPATCH_SECURE BIT(0)
256 #define I915_DISPATCH_PINNED BIT(1)
257 #define I915_DISPATCH_RS BIT(2)
258 int (*emit_request)(struct drm_i915_gem_request *req);
260 /* Pass the request to the hardware queue (e.g. directly into
261 * the legacy ringbuffer or to the end of an execlist).
263 * This is called from an atomic context with irqs disabled; must
266 void (*submit_request)(struct drm_i915_gem_request *req);
268 /* Some chipsets are not quite as coherent as advertised and need
269 * an expensive kick to force a true read of the up-to-date seqno.
270 * However, the up-to-date seqno is not always required and the last
271 * seen value is good enough. Note that the seqno will always be
272 * monotonic, even if not coherent.
274 void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
275 void (*cleanup)(struct intel_engine_cs *engine);
277 /* GEN8 signal/wait table - never trust comments!
278 * signal to signal to signal to signal to signal to
279 * RCS VCS BCS VECS VCS2
280 * --------------------------------------------------------------------
281 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
282 * |-------------------------------------------------------------------
283 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
284 * |-------------------------------------------------------------------
285 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
286 * |-------------------------------------------------------------------
287 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
288 * |-------------------------------------------------------------------
289 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
290 * |-------------------------------------------------------------------
293 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
294 * ie. transpose of g(x, y)
296 * sync from sync from sync from sync from sync from
297 * RCS VCS BCS VECS VCS2
298 * --------------------------------------------------------------------
299 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
300 * |-------------------------------------------------------------------
301 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
302 * |-------------------------------------------------------------------
303 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
304 * |-------------------------------------------------------------------
305 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
306 * |-------------------------------------------------------------------
307 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
308 * |-------------------------------------------------------------------
311 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
312 * ie. transpose of f(x, y)
315 u32 sync_seqno[I915_NUM_ENGINES-1];
318 #define GEN6_SEMAPHORE_LAST VECS_HW
319 #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
320 #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
322 /* our mbox written by others */
323 u32 wait[GEN6_NUM_SEMAPHORES];
324 /* mboxes this ring signals to */
325 i915_reg_t signal[GEN6_NUM_SEMAPHORES];
327 u64 signal_ggtt[I915_NUM_ENGINES];
331 int (*sync_to)(struct drm_i915_gem_request *req,
332 struct drm_i915_gem_request *signal);
333 int (*signal)(struct drm_i915_gem_request *req);
337 struct tasklet_struct irq_tasklet;
338 spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */
339 struct execlist_port {
340 struct drm_i915_gem_request *request;
343 struct list_head execlist_queue;
344 unsigned int fw_domains;
345 bool disable_lite_restore_wa;
347 u32 ctx_desc_template;
350 * List of breadcrumbs associated with GPU requests currently
353 struct list_head request_list;
356 * Seqno of request most recently submitted to request_list.
357 * Used exclusively by hang checker to avoid grabbing lock while
358 * inspecting request list.
360 u32 last_submitted_seqno;
361 u32 last_pending_seqno;
363 /* An RCU guarded pointer to the last request. No reference is
364 * held to the request, users must carefully acquire a reference to
365 * the request using i915_gem_active_get_rcu(), or hold the
368 struct i915_gem_active last_request;
370 struct i915_gem_context *last_context;
372 struct intel_engine_hangcheck hangcheck;
374 bool needs_cmd_parser;
377 * Table of commands the command parser needs to know about
380 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
383 * Table of registers allowed in commands that read/write registers.
385 const struct drm_i915_reg_table *reg_tables;
389 * Returns the bitmask for the length field of the specified command.
390 * Return 0 for an unrecognized/invalid command.
392 * If the command parser finds an entry for a command in the engine's
393 * cmd_tables, it gets the command's length based on the table entry.
394 * If not, it calls this function to determine the per-engine length
395 * field encoding for the command (i.e. different opcode ranges use
396 * certain bits to encode the command length in the header).
398 u32 (*get_cmd_length_mask)(u32 cmd_header);
401 static inline unsigned
402 intel_engine_flag(const struct intel_engine_cs *engine)
404 return 1 << engine->id;
408 intel_engine_sync_index(struct intel_engine_cs *engine,
409 struct intel_engine_cs *other)
414 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
415 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
416 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
417 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
418 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
421 idx = (other->id - engine->id) - 1;
423 idx += I915_NUM_ENGINES;
429 intel_flush_status_page(struct intel_engine_cs *engine, int reg)
432 clflush(&engine->status_page.page_addr[reg]);
437 intel_read_status_page(struct intel_engine_cs *engine, int reg)
439 /* Ensure that the compiler doesn't optimize away the load. */
440 return READ_ONCE(engine->status_page.page_addr[reg]);
444 intel_write_status_page(struct intel_engine_cs *engine,
447 engine->status_page.page_addr[reg] = value;
451 * Reads a dword out of the status page, which is written to from the command
452 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
455 * The following dwords have a reserved meaning:
456 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
457 * 0x04: ring 0 head pointer
458 * 0x05: ring 1 head pointer (915-class)
459 * 0x06: ring 2 head pointer (915-class)
460 * 0x10-0x1b: Context status DWords (GM45)
461 * 0x1f: Last written status offset. (GM45)
462 * 0x20-0x2f: Reserved (Gen6+)
464 * The area from dword 0x30 to 0x3ff is available for driver usage.
466 #define I915_GEM_HWS_INDEX 0x30
467 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
468 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
469 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
472 intel_engine_create_ring(struct intel_engine_cs *engine, int size);
473 int intel_ring_pin(struct intel_ring *ring);
474 void intel_ring_unpin(struct intel_ring *ring);
475 void intel_ring_free(struct intel_ring *ring);
477 void intel_engine_stop(struct intel_engine_cs *engine);
478 void intel_engine_cleanup(struct intel_engine_cs *engine);
480 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv);
482 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
484 int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
485 int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
487 static inline void intel_ring_emit(struct intel_ring *ring, u32 data)
489 *(uint32_t *)(ring->vaddr + ring->tail) = data;
493 static inline void intel_ring_emit_reg(struct intel_ring *ring, i915_reg_t reg)
495 intel_ring_emit(ring, i915_mmio_reg_offset(reg));
498 static inline void intel_ring_advance(struct intel_ring *ring)
502 * This serves as a placeholder in the code so that the reader
503 * can compare against the preceding intel_ring_begin() and
504 * check that the number of dwords emitted matches the space
505 * reserved for the command packet (i.e. the value passed to
506 * intel_ring_begin()).
510 static inline u32 intel_ring_offset(struct intel_ring *ring, u32 value)
512 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
513 return value & (ring->size - 1);
516 int __intel_ring_space(int head, int tail, int size);
517 void intel_ring_update_space(struct intel_ring *ring);
519 void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
521 void intel_engine_setup_common(struct intel_engine_cs *engine);
522 int intel_engine_init_common(struct intel_engine_cs *engine);
523 int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
524 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
526 static inline int intel_engine_idle(struct intel_engine_cs *engine,
529 /* Wait upon the last request to be completed */
530 return i915_gem_active_wait(&engine->last_request, flags);
533 int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
534 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
535 int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine);
536 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
537 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
539 u64 intel_engine_get_active_head(struct intel_engine_cs *engine);
540 u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine);
542 static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
544 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
547 int init_workarounds_ring(struct intel_engine_cs *engine);
549 void intel_engine_get_instdone(struct intel_engine_cs *engine,
550 struct intel_instdone *instdone);
553 * Arbitrary size for largest possible 'add request' sequence. The code paths
554 * are complex and variable. Empirical measurement shows that the worst case
555 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
556 * we need to allocate double the largest single packet within that emission
557 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
559 #define MIN_SPACE_FOR_ADD_REQUEST 336
561 static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
563 return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
566 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
567 int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
569 static inline void intel_wait_init(struct intel_wait *wait, u32 seqno)
575 static inline bool intel_wait_complete(const struct intel_wait *wait)
577 return RB_EMPTY_NODE(&wait->node);
580 bool intel_engine_add_wait(struct intel_engine_cs *engine,
581 struct intel_wait *wait);
582 void intel_engine_remove_wait(struct intel_engine_cs *engine,
583 struct intel_wait *wait);
584 void intel_engine_enable_signaling(struct drm_i915_gem_request *request);
586 static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
588 return rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh);
591 static inline bool intel_engine_wakeup(const struct intel_engine_cs *engine)
595 /* Note that for this not to dangerously chase a dangling pointer,
596 * we must hold the rcu_read_lock here.
598 * Also note that tsk is likely to be in !TASK_RUNNING state so an
599 * early test for tsk->state != TASK_RUNNING before wake_up_process()
600 * is unlikely to be beneficial.
602 if (intel_engine_has_waiter(engine)) {
603 struct task_struct *tsk;
606 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
608 wakeup = wake_up_process(tsk);
615 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
616 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
617 unsigned int intel_kick_waiters(struct drm_i915_private *i915);
618 unsigned int intel_kick_signalers(struct drm_i915_private *i915);
620 static inline bool intel_engine_is_active(struct intel_engine_cs *engine)
622 return i915_gem_active_isset(&engine->last_request);
625 #endif /* _INTEL_RINGBUFFER_H_ */