2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
28 #include <linux/i2c.h>
29 #include <linux/delay.h>
33 #include "intel_drv.h"
37 #include "intel_sdvo_regs.h"
39 static char *tv_format_names[] = {
40 "NTSC_M" , "NTSC_J" , "NTSC_443",
41 "PAL_B" , "PAL_D" , "PAL_G" ,
42 "PAL_H" , "PAL_I" , "PAL_M" ,
43 "PAL_N" , "PAL_NC" , "PAL_60" ,
44 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
45 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
49 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
51 struct intel_sdvo_priv {
54 /* Register for the SDVO device: SDVOB or SDVOC */
57 /* Active outputs controlled by this SDVO output */
58 uint16_t controlled_output;
61 * Capabilities of the SDVO device returned by
62 * i830_sdvo_get_capabilities()
64 struct intel_sdvo_caps caps;
66 /* Pixel clock limitations reported by the SDVO device, in kHz */
67 int pixel_clock_min, pixel_clock_max;
70 * For multiple function SDVO device,
71 * this is for current attached outputs.
73 uint16_t attached_output;
76 * This is set if we're going to treat the device as TV-out.
78 * While we have these nice friendly flags for output types that ought
79 * to decide this for us, the S-Video output on our HDMI+S-Video card
80 * shows up as RGB1 (VGA).
84 /* This is for current tv format name */
87 /* This contains all current supported TV format */
88 char *tv_format_supported[TV_FORMAT_NUM];
89 int format_supported_num;
90 struct drm_property *tv_format_property;
91 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
94 * This is set if we treat the device as HDMI, instead of DVI.
99 * This is set if we detect output of sdvo device as LVDS.
104 * This is sdvo flags for input timing.
109 * This is sdvo fixed pannel mode pointer
111 struct drm_display_mode *sdvo_lvds_fixed_mode;
114 * Returned SDTV resolutions allowed for the current format, if the
115 * device reported it.
117 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
120 * supported encoding mode, used to determine whether HDMI is
123 struct intel_sdvo_encode encode;
125 /* DDC bus used by this SDVO output */
128 /* Mac mini hack -- use the same DDC as the analog connector */
129 struct i2c_adapter *analog_ddc_bus;
132 u16 save_active_outputs;
133 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
134 struct intel_sdvo_dtd save_output_dtd[16];
136 /* add the property for the SDVO-TV */
137 struct drm_property *left_property;
138 struct drm_property *right_property;
139 struct drm_property *top_property;
140 struct drm_property *bottom_property;
141 struct drm_property *hpos_property;
142 struct drm_property *vpos_property;
144 /* add the property for the SDVO-TV/LVDS */
145 struct drm_property *brightness_property;
146 struct drm_property *contrast_property;
147 struct drm_property *saturation_property;
148 struct drm_property *hue_property;
150 /* Add variable to record current setting for the above property */
151 u32 left_margin, right_margin, top_margin, bottom_margin;
152 /* this is to get the range of margin.*/
153 u32 max_hscan, max_vscan;
154 u32 max_hpos, cur_hpos;
155 u32 max_vpos, cur_vpos;
156 u32 cur_brightness, max_brightness;
157 u32 cur_contrast, max_contrast;
158 u32 cur_saturation, max_saturation;
159 u32 cur_hue, max_hue;
163 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags);
166 * Writes the SDVOB or SDVOC with the given value, but always writes both
167 * SDVOB and SDVOC to work around apparent hardware issues (according to
168 * comments in the BIOS).
170 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
172 struct drm_device *dev = intel_output->base.dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
175 u32 bval = val, cval = val;
178 if (sdvo_priv->output_device == SDVOB) {
179 cval = I915_READ(SDVOC);
181 bval = I915_READ(SDVOB);
184 * Write the registers twice for luck. Sometimes,
185 * writing them only once doesn't appear to 'stick'.
186 * The BIOS does this too. Yay, magic
188 for (i = 0; i < 2; i++)
190 I915_WRITE(SDVOB, bval);
192 I915_WRITE(SDVOC, cval);
197 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
200 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
205 struct i2c_msg msgs[] = {
207 .addr = sdvo_priv->slave_addr >> 1,
213 .addr = sdvo_priv->slave_addr >> 1,
223 if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
229 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
233 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
236 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
238 struct i2c_msg msgs[] = {
240 .addr = sdvo_priv->slave_addr >> 1,
250 if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
257 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
258 /** Mapping of command numbers to names, for debug output */
259 static const struct _sdvo_cmd_name {
262 } sdvo_cmd_names[] = {
263 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
264 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
265 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
266 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
267 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
268 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
269 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
270 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
271 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
272 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
273 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
274 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
275 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
276 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
277 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
278 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
279 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
280 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
306 /* Add the op code for SDVO enhancements */
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
354 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
355 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
357 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
358 void *args, int args_len)
360 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
363 DRM_DEBUG_KMS("%s: W: %02X ",
364 SDVO_NAME(sdvo_priv), cmd);
365 for (i = 0; i < args_len; i++)
366 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
369 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
370 if (cmd == sdvo_cmd_names[i].cmd) {
371 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
375 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
376 DRM_LOG_KMS("(%02X)", cmd);
380 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
381 void *args, int args_len)
385 intel_sdvo_debug_write(intel_output, cmd, args, args_len);
387 for (i = 0; i < args_len; i++) {
388 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
392 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
395 static const char *cmd_status_names[] = {
401 "Target not specified",
402 "Scaling not supported"
405 static void intel_sdvo_debug_response(struct intel_output *intel_output,
406 void *response, int response_len,
409 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
412 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
413 for (i = 0; i < response_len; i++)
414 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
417 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
418 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
420 DRM_LOG_KMS("(??? %d)", status);
424 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
425 void *response, int response_len)
432 /* Read the command response */
433 for (i = 0; i < response_len; i++) {
434 intel_sdvo_read_byte(intel_output,
435 SDVO_I2C_RETURN_0 + i,
436 &((u8 *)response)[i]);
439 /* read the return status */
440 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
443 intel_sdvo_debug_response(intel_output, response, response_len,
445 if (status != SDVO_CMD_STATUS_PENDING)
454 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
456 if (mode->clock >= 100000)
458 else if (mode->clock >= 50000)
465 * Don't check status code from this as it switches the bus back to the
466 * SDVO chips which defeats the purpose of doing a bus switch in the first
469 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
472 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
475 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
477 struct intel_sdvo_set_target_input_args targets = {0};
480 if (target_0 && target_1)
481 return SDVO_CMD_STATUS_NOTSUPP;
484 targets.target_1 = 1;
486 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
489 status = intel_sdvo_read_response(intel_output, NULL, 0);
491 return (status == SDVO_CMD_STATUS_SUCCESS);
495 * Return whether each input is trained.
497 * This function is making an assumption about the layout of the response,
498 * which should be checked against the docs.
500 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
502 struct intel_sdvo_get_trained_inputs_response response;
505 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
506 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
507 if (status != SDVO_CMD_STATUS_SUCCESS)
510 *input_1 = response.input0_trained;
511 *input_2 = response.input1_trained;
515 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
520 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
521 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
523 return (status == SDVO_CMD_STATUS_SUCCESS);
526 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
531 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
533 status = intel_sdvo_read_response(intel_output, NULL, 0);
534 return (status == SDVO_CMD_STATUS_SUCCESS);
537 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
540 u8 status, state = SDVO_ENCODER_STATE_ON;
543 case DRM_MODE_DPMS_ON:
544 state = SDVO_ENCODER_STATE_ON;
546 case DRM_MODE_DPMS_STANDBY:
547 state = SDVO_ENCODER_STATE_STANDBY;
549 case DRM_MODE_DPMS_SUSPEND:
550 state = SDVO_ENCODER_STATE_SUSPEND;
552 case DRM_MODE_DPMS_OFF:
553 state = SDVO_ENCODER_STATE_OFF;
557 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
559 status = intel_sdvo_read_response(intel_output, NULL, 0);
561 return (status == SDVO_CMD_STATUS_SUCCESS);
564 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
568 struct intel_sdvo_pixel_clock_range clocks;
571 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
574 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
576 if (status != SDVO_CMD_STATUS_SUCCESS)
579 /* Convert the values from units of 10 kHz to kHz. */
580 *clock_min = clocks.min * 10;
581 *clock_max = clocks.max * 10;
586 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
591 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
594 status = intel_sdvo_read_response(intel_output, NULL, 0);
595 return (status == SDVO_CMD_STATUS_SUCCESS);
598 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
599 struct intel_sdvo_dtd *dtd)
603 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
604 status = intel_sdvo_read_response(intel_output, &dtd->part1,
606 if (status != SDVO_CMD_STATUS_SUCCESS)
609 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
610 status = intel_sdvo_read_response(intel_output, &dtd->part2,
612 if (status != SDVO_CMD_STATUS_SUCCESS)
618 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
619 struct intel_sdvo_dtd *dtd)
621 return intel_sdvo_get_timing(intel_output,
622 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
625 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
626 struct intel_sdvo_dtd *dtd)
628 return intel_sdvo_get_timing(intel_output,
629 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
632 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
633 struct intel_sdvo_dtd *dtd)
637 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
638 status = intel_sdvo_read_response(intel_output, NULL, 0);
639 if (status != SDVO_CMD_STATUS_SUCCESS)
642 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
643 status = intel_sdvo_read_response(intel_output, NULL, 0);
644 if (status != SDVO_CMD_STATUS_SUCCESS)
650 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
651 struct intel_sdvo_dtd *dtd)
653 return intel_sdvo_set_timing(intel_output,
654 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
657 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
658 struct intel_sdvo_dtd *dtd)
660 return intel_sdvo_set_timing(intel_output,
661 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
665 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
670 struct intel_sdvo_preferred_input_timing_args args;
671 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
674 memset(&args, 0, sizeof(args));
677 args.height = height;
680 if (sdvo_priv->is_lvds &&
681 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
682 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
685 intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
686 &args, sizeof(args));
687 status = intel_sdvo_read_response(output, NULL, 0);
688 if (status != SDVO_CMD_STATUS_SUCCESS)
694 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
695 struct intel_sdvo_dtd *dtd)
699 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
702 status = intel_sdvo_read_response(output, &dtd->part1,
704 if (status != SDVO_CMD_STATUS_SUCCESS)
707 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
710 status = intel_sdvo_read_response(output, &dtd->part2,
712 if (status != SDVO_CMD_STATUS_SUCCESS)
718 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
722 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
723 status = intel_sdvo_read_response(intel_output, &response, 1);
725 if (status != SDVO_CMD_STATUS_SUCCESS) {
726 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
727 return SDVO_CLOCK_RATE_MULT_1X;
729 DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
735 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
739 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
740 status = intel_sdvo_read_response(intel_output, NULL, 0);
741 if (status != SDVO_CMD_STATUS_SUCCESS)
747 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
748 struct drm_display_mode *mode)
750 uint16_t width, height;
751 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
752 uint16_t h_sync_offset, v_sync_offset;
754 width = mode->crtc_hdisplay;
755 height = mode->crtc_vdisplay;
757 /* do some mode translations */
758 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
759 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
761 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
762 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
764 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
765 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
767 dtd->part1.clock = mode->clock / 10;
768 dtd->part1.h_active = width & 0xff;
769 dtd->part1.h_blank = h_blank_len & 0xff;
770 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
771 ((h_blank_len >> 8) & 0xf);
772 dtd->part1.v_active = height & 0xff;
773 dtd->part1.v_blank = v_blank_len & 0xff;
774 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
775 ((v_blank_len >> 8) & 0xf);
777 dtd->part2.h_sync_off = h_sync_offset & 0xff;
778 dtd->part2.h_sync_width = h_sync_len & 0xff;
779 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
781 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
782 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
783 ((v_sync_len & 0x30) >> 4);
785 dtd->part2.dtd_flags = 0x18;
786 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
787 dtd->part2.dtd_flags |= 0x2;
788 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
789 dtd->part2.dtd_flags |= 0x4;
791 dtd->part2.sdvo_flags = 0;
792 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
793 dtd->part2.reserved = 0;
796 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
797 struct intel_sdvo_dtd *dtd)
799 mode->hdisplay = dtd->part1.h_active;
800 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
801 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
802 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
803 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
804 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
805 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
806 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
808 mode->vdisplay = dtd->part1.v_active;
809 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
810 mode->vsync_start = mode->vdisplay;
811 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
812 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
813 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
814 mode->vsync_end = mode->vsync_start +
815 (dtd->part2.v_sync_off_width & 0xf);
816 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
817 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
818 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
820 mode->clock = dtd->part1.clock * 10;
822 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
823 if (dtd->part2.dtd_flags & 0x2)
824 mode->flags |= DRM_MODE_FLAG_PHSYNC;
825 if (dtd->part2.dtd_flags & 0x4)
826 mode->flags |= DRM_MODE_FLAG_PVSYNC;
829 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
830 struct intel_sdvo_encode *encode)
834 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
835 status = intel_sdvo_read_response(output, encode, sizeof(*encode));
836 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
837 memset(encode, 0, sizeof(*encode));
844 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
848 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
849 status = intel_sdvo_read_response(output, NULL, 0);
851 return (status == SDVO_CMD_STATUS_SUCCESS);
854 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
859 intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
860 status = intel_sdvo_read_response(output, NULL, 0);
862 return (status == SDVO_CMD_STATUS_SUCCESS);
866 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
869 uint8_t set_buf_index[2];
875 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
876 intel_sdvo_read_response(output, &av_split, 1);
878 for (i = 0; i <= av_split; i++) {
879 set_buf_index[0] = i; set_buf_index[1] = 0;
880 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
882 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
883 intel_sdvo_read_response(output, &buf_size, 1);
886 for (j = 0; j <= buf_size; j += 8) {
887 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
889 intel_sdvo_read_response(output, pos, 8);
896 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
897 uint8_t *data, int8_t size, uint8_t tx_rate)
899 uint8_t set_buf_index[2];
901 set_buf_index[0] = index;
902 set_buf_index[1] = 0;
904 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
906 for (; size > 0; size -= 8) {
907 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
911 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
914 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
919 for (i = 0; i < size; i++)
925 #define DIP_TYPE_AVI 0x82
926 #define DIP_VERSION_AVI 0x2
927 #define DIP_LEN_AVI 13
929 struct dip_infoframe {
957 /* Packet Byte #6~13 */
958 uint16_t top_bar_end;
959 uint16_t bottom_bar_start;
960 uint16_t left_bar_end;
961 uint16_t right_bar_start;
965 uint8_t channel_count:3;
967 uint8_t coding_type:4;
969 uint8_t sample_size:2; /* SS0, SS1 */
970 uint8_t sample_frequency:3;
973 uint8_t coding_type_private:5;
976 uint8_t channel_allocation;
979 uint8_t level_shift:4;
980 uint8_t downmix_inhibit:1;
983 } __attribute__ ((packed)) u;
984 } __attribute__((packed));
986 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
987 struct drm_display_mode * mode)
989 struct dip_infoframe avi_if = {
990 .type = DIP_TYPE_AVI,
991 .version = DIP_VERSION_AVI,
995 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
997 intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
1001 static void intel_sdvo_set_tv_format(struct intel_output *output)
1004 struct intel_sdvo_tv_format format;
1005 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1006 uint32_t format_map, i;
1009 for (i = 0; i < TV_FORMAT_NUM; i++)
1010 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1013 format_map = 1 << i;
1014 memset(&format, 0, sizeof(format));
1015 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1016 sizeof(format) : sizeof(format_map));
1018 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map,
1021 status = intel_sdvo_read_response(output, NULL, 0);
1022 if (status != SDVO_CMD_STATUS_SUCCESS)
1023 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
1024 SDVO_NAME(sdvo_priv));
1027 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1028 struct drm_display_mode *mode,
1029 struct drm_display_mode *adjusted_mode)
1031 struct intel_output *output = enc_to_intel_output(encoder);
1032 struct intel_sdvo_priv *dev_priv = output->dev_priv;
1034 if (dev_priv->is_tv) {
1035 struct intel_sdvo_dtd output_dtd;
1038 /* We need to construct preferred input timings based on our
1039 * output timings. To do that, we have to set the output
1040 * timings, even though this isn't really the right place in
1041 * the sequence to do it. Oh well.
1045 /* Set output timings */
1046 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1047 intel_sdvo_set_target_output(output,
1048 dev_priv->controlled_output);
1049 intel_sdvo_set_output_timing(output, &output_dtd);
1051 /* Set the input timing to the screen. Assume always input 0. */
1052 intel_sdvo_set_target_input(output, true, false);
1055 success = intel_sdvo_create_preferred_input_timing(output,
1060 struct intel_sdvo_dtd input_dtd;
1062 intel_sdvo_get_preferred_input_timing(output,
1064 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1065 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1067 drm_mode_set_crtcinfo(adjusted_mode, 0);
1069 mode->clock = adjusted_mode->clock;
1071 adjusted_mode->clock *=
1072 intel_sdvo_get_pixel_multiplier(mode);
1076 } else if (dev_priv->is_lvds) {
1077 struct intel_sdvo_dtd output_dtd;
1080 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1081 /* Set output timings */
1082 intel_sdvo_get_dtd_from_mode(&output_dtd,
1083 dev_priv->sdvo_lvds_fixed_mode);
1085 intel_sdvo_set_target_output(output,
1086 dev_priv->controlled_output);
1087 intel_sdvo_set_output_timing(output, &output_dtd);
1089 /* Set the input timing to the screen. Assume always input 0. */
1090 intel_sdvo_set_target_input(output, true, false);
1093 success = intel_sdvo_create_preferred_input_timing(
1100 struct intel_sdvo_dtd input_dtd;
1102 intel_sdvo_get_preferred_input_timing(output,
1104 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1105 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1107 drm_mode_set_crtcinfo(adjusted_mode, 0);
1109 mode->clock = adjusted_mode->clock;
1111 adjusted_mode->clock *=
1112 intel_sdvo_get_pixel_multiplier(mode);
1118 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1119 * SDVO device will be told of the multiplier during mode_set.
1121 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1126 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1127 struct drm_display_mode *mode,
1128 struct drm_display_mode *adjusted_mode)
1130 struct drm_device *dev = encoder->dev;
1131 struct drm_i915_private *dev_priv = dev->dev_private;
1132 struct drm_crtc *crtc = encoder->crtc;
1133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1134 struct intel_output *output = enc_to_intel_output(encoder);
1135 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1137 int sdvo_pixel_multiply;
1138 struct intel_sdvo_in_out_map in_out;
1139 struct intel_sdvo_dtd input_dtd;
1145 /* First, set the input mapping for the first input to our controlled
1146 * output. This is only correct if we're a single-input device, in
1147 * which case the first input is the output from the appropriate SDVO
1148 * channel on the motherboard. In a two-input device, the first input
1149 * will be SDVOB and the second SDVOC.
1151 in_out.in0 = sdvo_priv->controlled_output;
1154 intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1155 &in_out, sizeof(in_out));
1156 status = intel_sdvo_read_response(output, NULL, 0);
1158 if (sdvo_priv->is_hdmi) {
1159 intel_sdvo_set_avi_infoframe(output, mode);
1160 sdvox |= SDVO_AUDIO_ENABLE;
1163 /* We have tried to get input timing in mode_fixup, and filled into
1165 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1166 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1167 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1169 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1171 /* If it's a TV, we already set the output timing in mode_fixup.
1172 * Otherwise, the output timing is equal to the input timing.
1174 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1175 /* Set the output timing to the screen */
1176 intel_sdvo_set_target_output(output,
1177 sdvo_priv->controlled_output);
1178 intel_sdvo_set_output_timing(output, &input_dtd);
1181 /* Set the input timing to the screen. Assume always input 0. */
1182 intel_sdvo_set_target_input(output, true, false);
1184 if (sdvo_priv->is_tv)
1185 intel_sdvo_set_tv_format(output);
1187 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1188 * provide the device with a timing it can support, if it supports that
1189 * feature. However, presumably we would need to adjust the CRTC to
1190 * output the preferred timing, and we don't support that currently.
1193 success = intel_sdvo_create_preferred_input_timing(output, clock,
1196 struct intel_sdvo_dtd *input_dtd;
1198 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1199 intel_sdvo_set_input_timing(output, &input_dtd);
1202 intel_sdvo_set_input_timing(output, &input_dtd);
1205 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1207 intel_sdvo_set_clock_rate_mult(output,
1208 SDVO_CLOCK_RATE_MULT_1X);
1211 intel_sdvo_set_clock_rate_mult(output,
1212 SDVO_CLOCK_RATE_MULT_2X);
1215 intel_sdvo_set_clock_rate_mult(output,
1216 SDVO_CLOCK_RATE_MULT_4X);
1220 /* Set the SDVO control regs. */
1221 if (IS_I965G(dev)) {
1222 sdvox |= SDVO_BORDER_ENABLE |
1223 SDVO_VSYNC_ACTIVE_HIGH |
1224 SDVO_HSYNC_ACTIVE_HIGH;
1226 sdvox |= I915_READ(sdvo_priv->output_device);
1227 switch (sdvo_priv->output_device) {
1229 sdvox &= SDVOB_PRESERVE_MASK;
1232 sdvox &= SDVOC_PRESERVE_MASK;
1235 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1237 if (intel_crtc->pipe == 1)
1238 sdvox |= SDVO_PIPE_B_SELECT;
1240 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1241 if (IS_I965G(dev)) {
1242 /* done in crtc_mode_set as the dpll_md reg must be written early */
1243 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1244 /* done in crtc_mode_set as it lives inside the dpll register */
1246 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1249 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1250 sdvox |= SDVO_STALL_SELECT;
1251 intel_sdvo_write_sdvox(output, sdvox);
1254 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1256 struct drm_device *dev = encoder->dev;
1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258 struct intel_output *intel_output = enc_to_intel_output(encoder);
1259 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1262 if (mode != DRM_MODE_DPMS_ON) {
1263 intel_sdvo_set_active_outputs(intel_output, 0);
1265 intel_sdvo_set_encoder_power_state(intel_output, mode);
1267 if (mode == DRM_MODE_DPMS_OFF) {
1268 temp = I915_READ(sdvo_priv->output_device);
1269 if ((temp & SDVO_ENABLE) != 0) {
1270 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1274 bool input1, input2;
1278 temp = I915_READ(sdvo_priv->output_device);
1279 if ((temp & SDVO_ENABLE) == 0)
1280 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1281 for (i = 0; i < 2; i++)
1282 intel_wait_for_vblank(dev);
1284 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1288 /* Warn if the device reported failure to sync.
1289 * A lot of SDVO devices fail to notify of sync, but it's
1290 * a given it the status is a success, we succeeded.
1292 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1293 DRM_DEBUG_KMS("First %s output reported failure to "
1294 "sync\n", SDVO_NAME(sdvo_priv));
1298 intel_sdvo_set_encoder_power_state(intel_output, mode);
1299 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1304 static void intel_sdvo_save(struct drm_connector *connector)
1306 struct drm_device *dev = connector->dev;
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308 struct intel_output *intel_output = to_intel_output(connector);
1309 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1312 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1313 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1315 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1316 intel_sdvo_set_target_input(intel_output, true, false);
1317 intel_sdvo_get_input_timing(intel_output,
1318 &sdvo_priv->save_input_dtd_1);
1321 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1322 intel_sdvo_set_target_input(intel_output, false, true);
1323 intel_sdvo_get_input_timing(intel_output,
1324 &sdvo_priv->save_input_dtd_2);
1327 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1329 u16 this_output = (1 << o);
1330 if (sdvo_priv->caps.output_flags & this_output)
1332 intel_sdvo_set_target_output(intel_output, this_output);
1333 intel_sdvo_get_output_timing(intel_output,
1334 &sdvo_priv->save_output_dtd[o]);
1337 if (sdvo_priv->is_tv) {
1338 /* XXX: Save TV format/enhancements. */
1341 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1344 static void intel_sdvo_restore(struct drm_connector *connector)
1346 struct drm_device *dev = connector->dev;
1347 struct intel_output *intel_output = to_intel_output(connector);
1348 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1351 bool input1, input2;
1354 intel_sdvo_set_active_outputs(intel_output, 0);
1356 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1358 u16 this_output = (1 << o);
1359 if (sdvo_priv->caps.output_flags & this_output) {
1360 intel_sdvo_set_target_output(intel_output, this_output);
1361 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1365 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1366 intel_sdvo_set_target_input(intel_output, true, false);
1367 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1370 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1371 intel_sdvo_set_target_input(intel_output, false, true);
1372 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1375 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1377 if (sdvo_priv->is_tv) {
1378 /* XXX: Restore TV format/enhancements. */
1381 intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1383 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1385 for (i = 0; i < 2; i++)
1386 intel_wait_for_vblank(dev);
1387 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1388 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1389 DRM_DEBUG_KMS("First %s output reported failure to "
1390 "sync\n", SDVO_NAME(sdvo_priv));
1393 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1396 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1397 struct drm_display_mode *mode)
1399 struct intel_output *intel_output = to_intel_output(connector);
1400 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1402 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1403 return MODE_NO_DBLESCAN;
1405 if (sdvo_priv->pixel_clock_min > mode->clock)
1406 return MODE_CLOCK_LOW;
1408 if (sdvo_priv->pixel_clock_max < mode->clock)
1409 return MODE_CLOCK_HIGH;
1411 if (sdvo_priv->is_lvds == true) {
1412 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1415 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1418 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1425 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1429 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1430 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1431 if (status != SDVO_CMD_STATUS_SUCCESS)
1437 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1439 struct drm_connector *connector = NULL;
1440 struct intel_output *iout = NULL;
1441 struct intel_sdvo_priv *sdvo;
1443 /* find the sdvo connector */
1444 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1445 iout = to_intel_output(connector);
1447 if (iout->type != INTEL_OUTPUT_SDVO)
1450 sdvo = iout->dev_priv;
1452 if (sdvo->output_device == SDVOB && sdvoB)
1455 if (sdvo->output_device == SDVOC && !sdvoB)
1463 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1467 struct intel_output *intel_output;
1468 DRM_DEBUG_KMS("\n");
1473 intel_output = to_intel_output(connector);
1475 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1476 status = intel_sdvo_read_response(intel_output, &response, 2);
1478 if (response[0] !=0)
1484 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1488 struct intel_output *intel_output = to_intel_output(connector);
1490 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1491 intel_sdvo_read_response(intel_output, &response, 2);
1494 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1495 status = intel_sdvo_read_response(intel_output, &response, 2);
1497 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1501 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1504 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1505 intel_sdvo_read_response(intel_output, &response, 2);
1509 intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
1511 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1514 if (sdvo_priv->caps.output_flags &
1515 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1517 if (sdvo_priv->caps.output_flags &
1518 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1520 if (sdvo_priv->caps.output_flags &
1521 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1523 if (sdvo_priv->caps.output_flags &
1524 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1526 if (sdvo_priv->caps.output_flags &
1527 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1530 if (sdvo_priv->caps.output_flags &
1531 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1534 if (sdvo_priv->caps.output_flags &
1535 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1541 static struct drm_connector *
1542 intel_find_analog_connector(struct drm_device *dev)
1544 struct drm_connector *connector;
1545 struct intel_output *intel_output;
1547 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1548 intel_output = to_intel_output(connector);
1549 if (intel_output->type == INTEL_OUTPUT_ANALOG)
1556 intel_analog_is_connected(struct drm_device *dev)
1558 struct drm_connector *analog_connector;
1559 analog_connector = intel_find_analog_connector(dev);
1561 if (!analog_connector)
1564 if (analog_connector->funcs->detect(analog_connector) ==
1565 connector_status_disconnected)
1571 enum drm_connector_status
1572 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1574 struct intel_output *intel_output = to_intel_output(connector);
1575 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1576 enum drm_connector_status status = connector_status_connected;
1577 struct edid *edid = NULL;
1579 edid = drm_get_edid(&intel_output->base,
1580 intel_output->ddc_bus);
1582 /* when there is no edid and no monitor is connected with VGA
1583 * port, try to use the CRT ddc to read the EDID for DVI-connector
1586 sdvo_priv->analog_ddc_bus &&
1587 !intel_analog_is_connected(intel_output->base.dev))
1588 edid = drm_get_edid(&intel_output->base,
1589 sdvo_priv->analog_ddc_bus);
1591 /* Don't report the output as connected if it's a DVI-I
1592 * connector with a non-digital EDID coming out.
1594 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1595 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1596 sdvo_priv->is_hdmi =
1597 drm_detect_hdmi_monitor(edid);
1599 status = connector_status_disconnected;
1603 intel_output->base.display_info.raw_edid = NULL;
1605 } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1606 status = connector_status_disconnected;
1611 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1615 struct intel_output *intel_output = to_intel_output(connector);
1616 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1618 intel_sdvo_write_cmd(intel_output,
1619 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1620 if (sdvo_priv->is_tv) {
1621 /* add 30ms delay when the output type is SDVO-TV */
1624 status = intel_sdvo_read_response(intel_output, &response, 2);
1626 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1628 if (status != SDVO_CMD_STATUS_SUCCESS)
1629 return connector_status_unknown;
1632 return connector_status_disconnected;
1634 if (intel_sdvo_multifunc_encoder(intel_output) &&
1635 sdvo_priv->attached_output != response) {
1636 if (sdvo_priv->controlled_output != response &&
1637 intel_sdvo_output_setup(intel_output, response) != true)
1638 return connector_status_unknown;
1639 sdvo_priv->attached_output = response;
1641 return intel_sdvo_hdmi_sink_detect(connector, response);
1644 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1646 struct intel_output *intel_output = to_intel_output(connector);
1647 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1650 /* set the bus switch and get the modes */
1651 num_modes = intel_ddc_get_modes(intel_output);
1654 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1655 * link between analog and digital outputs. So, if the regular SDVO
1656 * DDC fails, check to see if the analog output is disconnected, in
1657 * which case we'll look there for the digital DDC data.
1659 if (num_modes == 0 &&
1660 sdvo_priv->analog_ddc_bus &&
1661 !intel_analog_is_connected(intel_output->base.dev)) {
1662 struct i2c_adapter *digital_ddc_bus;
1664 /* Switch to the analog ddc bus and try that
1666 digital_ddc_bus = intel_output->ddc_bus;
1667 intel_output->ddc_bus = sdvo_priv->analog_ddc_bus;
1669 (void) intel_ddc_get_modes(intel_output);
1671 intel_output->ddc_bus = digital_ddc_bus;
1676 * Set of SDVO TV modes.
1677 * Note! This is in reply order (see loop in get_tv_modes).
1678 * XXX: all 60Hz refresh?
1680 struct drm_display_mode sdvo_tv_modes[] = {
1681 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1682 416, 0, 200, 201, 232, 233, 0,
1683 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1684 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1685 416, 0, 240, 241, 272, 273, 0,
1686 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1687 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1688 496, 0, 300, 301, 332, 333, 0,
1689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1690 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1691 736, 0, 350, 351, 382, 383, 0,
1692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1693 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1694 736, 0, 400, 401, 432, 433, 0,
1695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1696 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1697 736, 0, 480, 481, 512, 513, 0,
1698 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1699 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1700 800, 0, 480, 481, 512, 513, 0,
1701 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1702 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1703 800, 0, 576, 577, 608, 609, 0,
1704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1705 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1706 816, 0, 350, 351, 382, 383, 0,
1707 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1708 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1709 816, 0, 400, 401, 432, 433, 0,
1710 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1711 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1712 816, 0, 480, 481, 512, 513, 0,
1713 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1714 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1715 816, 0, 540, 541, 572, 573, 0,
1716 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1717 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1718 816, 0, 576, 577, 608, 609, 0,
1719 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1720 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1721 864, 0, 576, 577, 608, 609, 0,
1722 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1723 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1724 896, 0, 600, 601, 632, 633, 0,
1725 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1726 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1727 928, 0, 624, 625, 656, 657, 0,
1728 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1729 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1730 1016, 0, 766, 767, 798, 799, 0,
1731 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1732 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1733 1120, 0, 768, 769, 800, 801, 0,
1734 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1735 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1736 1376, 0, 1024, 1025, 1056, 1057, 0,
1737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1740 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1742 struct intel_output *output = to_intel_output(connector);
1743 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1744 struct intel_sdvo_sdtv_resolution_request tv_res;
1745 uint32_t reply = 0, format_map = 0;
1750 /* Read the list of supported input resolutions for the selected TV
1753 for (i = 0; i < TV_FORMAT_NUM; i++)
1754 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1757 format_map = (1 << i);
1758 memcpy(&tv_res, &format_map,
1759 sizeof(struct intel_sdvo_sdtv_resolution_request) >
1760 sizeof(format_map) ? sizeof(format_map) :
1761 sizeof(struct intel_sdvo_sdtv_resolution_request));
1763 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1765 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1766 &tv_res, sizeof(tv_res));
1767 status = intel_sdvo_read_response(output, &reply, 3);
1768 if (status != SDVO_CMD_STATUS_SUCCESS)
1771 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1772 if (reply & (1 << i)) {
1773 struct drm_display_mode *nmode;
1774 nmode = drm_mode_duplicate(connector->dev,
1777 drm_mode_probed_add(connector, nmode);
1782 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1784 struct intel_output *intel_output = to_intel_output(connector);
1785 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1786 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1787 struct drm_display_mode *newmode;
1790 * Attempt to get the mode list from DDC.
1791 * Assume that the preferred modes are
1792 * arranged in priority order.
1794 intel_ddc_get_modes(intel_output);
1795 if (list_empty(&connector->probed_modes) == false)
1798 /* Fetch modes from VBT */
1799 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1800 newmode = drm_mode_duplicate(connector->dev,
1801 dev_priv->sdvo_lvds_vbt_mode);
1802 if (newmode != NULL) {
1803 /* Guarantee the mode is preferred */
1804 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1805 DRM_MODE_TYPE_DRIVER);
1806 drm_mode_probed_add(connector, newmode);
1811 list_for_each_entry(newmode, &connector->probed_modes, head) {
1812 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1813 sdvo_priv->sdvo_lvds_fixed_mode =
1814 drm_mode_duplicate(connector->dev, newmode);
1821 static int intel_sdvo_get_modes(struct drm_connector *connector)
1823 struct intel_output *output = to_intel_output(connector);
1824 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1826 if (sdvo_priv->is_tv)
1827 intel_sdvo_get_tv_modes(connector);
1828 else if (sdvo_priv->is_lvds == true)
1829 intel_sdvo_get_lvds_modes(connector);
1831 intel_sdvo_get_ddc_modes(connector);
1833 if (list_empty(&connector->probed_modes))
1839 void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1841 struct intel_output *intel_output = to_intel_output(connector);
1842 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1843 struct drm_device *dev = connector->dev;
1845 if (sdvo_priv->is_tv) {
1846 if (sdvo_priv->left_property)
1847 drm_property_destroy(dev, sdvo_priv->left_property);
1848 if (sdvo_priv->right_property)
1849 drm_property_destroy(dev, sdvo_priv->right_property);
1850 if (sdvo_priv->top_property)
1851 drm_property_destroy(dev, sdvo_priv->top_property);
1852 if (sdvo_priv->bottom_property)
1853 drm_property_destroy(dev, sdvo_priv->bottom_property);
1854 if (sdvo_priv->hpos_property)
1855 drm_property_destroy(dev, sdvo_priv->hpos_property);
1856 if (sdvo_priv->vpos_property)
1857 drm_property_destroy(dev, sdvo_priv->vpos_property);
1859 if (sdvo_priv->is_tv) {
1860 if (sdvo_priv->saturation_property)
1861 drm_property_destroy(dev,
1862 sdvo_priv->saturation_property);
1863 if (sdvo_priv->contrast_property)
1864 drm_property_destroy(dev,
1865 sdvo_priv->contrast_property);
1866 if (sdvo_priv->hue_property)
1867 drm_property_destroy(dev, sdvo_priv->hue_property);
1869 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1870 if (sdvo_priv->brightness_property)
1871 drm_property_destroy(dev,
1872 sdvo_priv->brightness_property);
1877 static void intel_sdvo_destroy(struct drm_connector *connector)
1879 struct intel_output *intel_output = to_intel_output(connector);
1880 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1882 if (intel_output->i2c_bus)
1883 intel_i2c_destroy(intel_output->i2c_bus);
1884 if (intel_output->ddc_bus)
1885 intel_i2c_destroy(intel_output->ddc_bus);
1886 if (sdvo_priv->analog_ddc_bus)
1887 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
1889 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1890 drm_mode_destroy(connector->dev,
1891 sdvo_priv->sdvo_lvds_fixed_mode);
1893 if (sdvo_priv->tv_format_property)
1894 drm_property_destroy(connector->dev,
1895 sdvo_priv->tv_format_property);
1897 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
1898 intel_sdvo_destroy_enhance_property(connector);
1900 drm_sysfs_connector_remove(connector);
1901 drm_connector_cleanup(connector);
1903 kfree(intel_output);
1907 intel_sdvo_set_property(struct drm_connector *connector,
1908 struct drm_property *property,
1911 struct intel_output *intel_output = to_intel_output(connector);
1912 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1913 struct drm_encoder *encoder = &intel_output->enc;
1914 struct drm_crtc *crtc = encoder->crtc;
1916 bool changed = false;
1917 uint8_t cmd, status;
1918 uint16_t temp_value;
1920 ret = drm_connector_property_set_value(connector, property, val);
1924 if (property == sdvo_priv->tv_format_property) {
1925 if (val >= TV_FORMAT_NUM) {
1929 if (sdvo_priv->tv_format_name ==
1930 sdvo_priv->tv_format_supported[val])
1933 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
1937 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1940 if (sdvo_priv->left_property == property) {
1941 drm_connector_property_set_value(connector,
1942 sdvo_priv->right_property, val);
1943 if (sdvo_priv->left_margin == temp_value)
1946 sdvo_priv->left_margin = temp_value;
1947 sdvo_priv->right_margin = temp_value;
1948 temp_value = sdvo_priv->max_hscan -
1949 sdvo_priv->left_margin;
1950 cmd = SDVO_CMD_SET_OVERSCAN_H;
1951 } else if (sdvo_priv->right_property == property) {
1952 drm_connector_property_set_value(connector,
1953 sdvo_priv->left_property, val);
1954 if (sdvo_priv->right_margin == temp_value)
1957 sdvo_priv->left_margin = temp_value;
1958 sdvo_priv->right_margin = temp_value;
1959 temp_value = sdvo_priv->max_hscan -
1960 sdvo_priv->left_margin;
1961 cmd = SDVO_CMD_SET_OVERSCAN_H;
1962 } else if (sdvo_priv->top_property == property) {
1963 drm_connector_property_set_value(connector,
1964 sdvo_priv->bottom_property, val);
1965 if (sdvo_priv->top_margin == temp_value)
1968 sdvo_priv->top_margin = temp_value;
1969 sdvo_priv->bottom_margin = temp_value;
1970 temp_value = sdvo_priv->max_vscan -
1971 sdvo_priv->top_margin;
1972 cmd = SDVO_CMD_SET_OVERSCAN_V;
1973 } else if (sdvo_priv->bottom_property == property) {
1974 drm_connector_property_set_value(connector,
1975 sdvo_priv->top_property, val);
1976 if (sdvo_priv->bottom_margin == temp_value)
1978 sdvo_priv->top_margin = temp_value;
1979 sdvo_priv->bottom_margin = temp_value;
1980 temp_value = sdvo_priv->max_vscan -
1981 sdvo_priv->top_margin;
1982 cmd = SDVO_CMD_SET_OVERSCAN_V;
1983 } else if (sdvo_priv->hpos_property == property) {
1984 if (sdvo_priv->cur_hpos == temp_value)
1987 cmd = SDVO_CMD_SET_POSITION_H;
1988 sdvo_priv->cur_hpos = temp_value;
1989 } else if (sdvo_priv->vpos_property == property) {
1990 if (sdvo_priv->cur_vpos == temp_value)
1993 cmd = SDVO_CMD_SET_POSITION_V;
1994 sdvo_priv->cur_vpos = temp_value;
1995 } else if (sdvo_priv->saturation_property == property) {
1996 if (sdvo_priv->cur_saturation == temp_value)
1999 cmd = SDVO_CMD_SET_SATURATION;
2000 sdvo_priv->cur_saturation = temp_value;
2001 } else if (sdvo_priv->contrast_property == property) {
2002 if (sdvo_priv->cur_contrast == temp_value)
2005 cmd = SDVO_CMD_SET_CONTRAST;
2006 sdvo_priv->cur_contrast = temp_value;
2007 } else if (sdvo_priv->hue_property == property) {
2008 if (sdvo_priv->cur_hue == temp_value)
2011 cmd = SDVO_CMD_SET_HUE;
2012 sdvo_priv->cur_hue = temp_value;
2013 } else if (sdvo_priv->brightness_property == property) {
2014 if (sdvo_priv->cur_brightness == temp_value)
2017 cmd = SDVO_CMD_SET_BRIGHTNESS;
2018 sdvo_priv->cur_brightness = temp_value;
2021 intel_sdvo_write_cmd(intel_output, cmd, &temp_value, 2);
2022 status = intel_sdvo_read_response(intel_output,
2024 if (status != SDVO_CMD_STATUS_SUCCESS) {
2025 DRM_DEBUG_KMS("Incorrect SDVO command \n");
2031 if (changed && crtc)
2032 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
2038 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
2039 .dpms = intel_sdvo_dpms,
2040 .mode_fixup = intel_sdvo_mode_fixup,
2041 .prepare = intel_encoder_prepare,
2042 .mode_set = intel_sdvo_mode_set,
2043 .commit = intel_encoder_commit,
2046 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2047 .dpms = drm_helper_connector_dpms,
2048 .save = intel_sdvo_save,
2049 .restore = intel_sdvo_restore,
2050 .detect = intel_sdvo_detect,
2051 .fill_modes = drm_helper_probe_single_connector_modes,
2052 .set_property = intel_sdvo_set_property,
2053 .destroy = intel_sdvo_destroy,
2056 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2057 .get_modes = intel_sdvo_get_modes,
2058 .mode_valid = intel_sdvo_mode_valid,
2059 .best_encoder = intel_best_encoder,
2062 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2064 drm_encoder_cleanup(encoder);
2067 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2068 .destroy = intel_sdvo_enc_destroy,
2073 * Choose the appropriate DDC bus for control bus switch command for this
2074 * SDVO output based on the controlled output.
2076 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2077 * outputs, then LVDS outputs.
2080 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
2083 unsigned int num_bits;
2085 /* Make a mask of outputs less than or equal to our own priority in the
2088 switch (dev_priv->controlled_output) {
2089 case SDVO_OUTPUT_LVDS1:
2090 mask |= SDVO_OUTPUT_LVDS1;
2091 case SDVO_OUTPUT_LVDS0:
2092 mask |= SDVO_OUTPUT_LVDS0;
2093 case SDVO_OUTPUT_TMDS1:
2094 mask |= SDVO_OUTPUT_TMDS1;
2095 case SDVO_OUTPUT_TMDS0:
2096 mask |= SDVO_OUTPUT_TMDS0;
2097 case SDVO_OUTPUT_RGB1:
2098 mask |= SDVO_OUTPUT_RGB1;
2099 case SDVO_OUTPUT_RGB0:
2100 mask |= SDVO_OUTPUT_RGB0;
2104 /* Count bits to find what number we are in the priority list. */
2105 mask &= dev_priv->caps.output_flags;
2106 num_bits = hweight16(mask);
2108 /* if more than 3 outputs, default to DDC bus 3 for now */
2112 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2113 dev_priv->ddc_bus = 1 << num_bits;
2117 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
2119 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2122 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
2124 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2125 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2126 if (status != SDVO_CMD_STATUS_SUCCESS)
2131 static struct intel_output *
2132 intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
2134 struct drm_device *dev = chan->drm_dev;
2135 struct drm_connector *connector;
2136 struct intel_output *intel_output = NULL;
2138 list_for_each_entry(connector,
2139 &dev->mode_config.connector_list, head) {
2140 if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
2141 intel_output = to_intel_output(connector);
2145 return intel_output;
2148 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2149 struct i2c_msg msgs[], int num)
2151 struct intel_output *intel_output;
2152 struct intel_sdvo_priv *sdvo_priv;
2153 struct i2c_algo_bit_data *algo_data;
2154 const struct i2c_algorithm *algo;
2156 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
2158 intel_sdvo_chan_to_intel_output(
2159 (struct intel_i2c_chan *)(algo_data->data));
2160 if (intel_output == NULL)
2163 sdvo_priv = intel_output->dev_priv;
2164 algo = intel_output->i2c_bus->algo;
2166 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
2167 return algo->master_xfer(i2c_adap, msgs, num);
2170 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2171 .master_xfer = intel_sdvo_master_xfer,
2175 intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
2177 struct drm_i915_private *dev_priv = dev->dev_private;
2178 struct sdvo_device_mapping *my_mapping, *other_mapping;
2180 if (output_device == SDVOB) {
2181 my_mapping = &dev_priv->sdvo_mappings[0];
2182 other_mapping = &dev_priv->sdvo_mappings[1];
2184 my_mapping = &dev_priv->sdvo_mappings[1];
2185 other_mapping = &dev_priv->sdvo_mappings[0];
2188 /* If the BIOS described our SDVO device, take advantage of it. */
2189 if (my_mapping->slave_addr)
2190 return my_mapping->slave_addr;
2192 /* If the BIOS only described a different SDVO device, use the
2193 * address that it isn't using.
2195 if (other_mapping->slave_addr) {
2196 if (other_mapping->slave_addr == 0x70)
2202 /* No SDVO device info is found for another DVO port,
2203 * so use mapping assumption we had before BIOS parsing.
2205 if (output_device == SDVOB)
2212 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2214 struct drm_connector *connector = &intel_output->base;
2215 struct drm_encoder *encoder = &intel_output->enc;
2216 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2217 bool ret = true, registered = false;
2219 sdvo_priv->is_tv = false;
2220 intel_output->needs_tv_clock = false;
2221 sdvo_priv->is_lvds = false;
2223 if (device_is_registered(&connector->kdev)) {
2224 drm_sysfs_connector_remove(connector);
2229 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
2230 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
2231 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
2233 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
2235 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2236 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2238 if (intel_sdvo_get_supp_encode(intel_output,
2239 &sdvo_priv->encode) &&
2240 intel_sdvo_get_digital_encoding_mode(intel_output) &&
2241 sdvo_priv->is_hdmi) {
2242 /* enable hdmi encoding mode if supported */
2243 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
2244 intel_sdvo_set_colorimetry(intel_output,
2245 SDVO_COLORIMETRY_RGB256);
2246 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2247 intel_output->clone_mask =
2248 (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2249 (1 << INTEL_ANALOG_CLONE_BIT);
2251 } else if (flags & SDVO_OUTPUT_SVID0) {
2253 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
2254 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2255 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2256 sdvo_priv->is_tv = true;
2257 intel_output->needs_tv_clock = true;
2258 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2259 } else if (flags & SDVO_OUTPUT_RGB0) {
2261 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
2262 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2263 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2264 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2265 (1 << INTEL_ANALOG_CLONE_BIT);
2266 } else if (flags & SDVO_OUTPUT_RGB1) {
2268 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
2269 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2270 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2271 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2272 (1 << INTEL_ANALOG_CLONE_BIT);
2273 } else if (flags & SDVO_OUTPUT_LVDS0) {
2275 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
2276 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2277 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2278 sdvo_priv->is_lvds = true;
2279 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2280 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2281 } else if (flags & SDVO_OUTPUT_LVDS1) {
2283 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
2284 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2285 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2286 sdvo_priv->is_lvds = true;
2287 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2288 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2291 unsigned char bytes[2];
2293 sdvo_priv->controlled_output = 0;
2294 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
2295 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2296 SDVO_NAME(sdvo_priv),
2297 bytes[0], bytes[1]);
2300 intel_output->crtc_mask = (1 << 0) | (1 << 1);
2302 if (ret && registered)
2303 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2310 static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2312 struct intel_output *intel_output = to_intel_output(connector);
2313 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2314 struct intel_sdvo_tv_format format;
2315 uint32_t format_map, i;
2318 intel_sdvo_set_target_output(intel_output,
2319 sdvo_priv->controlled_output);
2321 intel_sdvo_write_cmd(intel_output,
2322 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
2323 status = intel_sdvo_read_response(intel_output,
2324 &format, sizeof(format));
2325 if (status != SDVO_CMD_STATUS_SUCCESS)
2328 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2329 sizeof(format_map) : sizeof(format));
2331 if (format_map == 0)
2334 sdvo_priv->format_supported_num = 0;
2335 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2336 if (format_map & (1 << i)) {
2337 sdvo_priv->tv_format_supported
2338 [sdvo_priv->format_supported_num++] =
2343 sdvo_priv->tv_format_property =
2344 drm_property_create(
2345 connector->dev, DRM_MODE_PROP_ENUM,
2346 "mode", sdvo_priv->format_supported_num);
2348 for (i = 0; i < sdvo_priv->format_supported_num; i++)
2349 drm_property_add_enum(
2350 sdvo_priv->tv_format_property, i,
2351 i, sdvo_priv->tv_format_supported[i]);
2353 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
2354 drm_connector_attach_property(
2355 connector, sdvo_priv->tv_format_property, 0);
2359 static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2361 struct intel_output *intel_output = to_intel_output(connector);
2362 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2363 struct intel_sdvo_enhancements_reply sdvo_data;
2364 struct drm_device *dev = connector->dev;
2366 uint16_t response, data_value[2];
2368 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2370 status = intel_sdvo_read_response(intel_output, &sdvo_data,
2372 if (status != SDVO_CMD_STATUS_SUCCESS) {
2373 DRM_DEBUG_KMS(" incorrect response is returned\n");
2376 response = *((uint16_t *)&sdvo_data);
2378 DRM_DEBUG_KMS("No enhancement is supported\n");
2381 if (sdvo_priv->is_tv) {
2382 /* when horizontal overscan is supported, Add the left/right
2385 if (sdvo_data.overscan_h) {
2386 intel_sdvo_write_cmd(intel_output,
2387 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
2388 status = intel_sdvo_read_response(intel_output,
2390 if (status != SDVO_CMD_STATUS_SUCCESS) {
2391 DRM_DEBUG_KMS("Incorrect SDVO max "
2395 intel_sdvo_write_cmd(intel_output,
2396 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
2397 status = intel_sdvo_read_response(intel_output,
2399 if (status != SDVO_CMD_STATUS_SUCCESS) {
2400 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2403 sdvo_priv->max_hscan = data_value[0];
2404 sdvo_priv->left_margin = data_value[0] - response;
2405 sdvo_priv->right_margin = sdvo_priv->left_margin;
2406 sdvo_priv->left_property =
2407 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2409 sdvo_priv->left_property->values[0] = 0;
2410 sdvo_priv->left_property->values[1] = data_value[0];
2411 drm_connector_attach_property(connector,
2412 sdvo_priv->left_property,
2413 sdvo_priv->left_margin);
2414 sdvo_priv->right_property =
2415 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2417 sdvo_priv->right_property->values[0] = 0;
2418 sdvo_priv->right_property->values[1] = data_value[0];
2419 drm_connector_attach_property(connector,
2420 sdvo_priv->right_property,
2421 sdvo_priv->right_margin);
2422 DRM_DEBUG_KMS("h_overscan: max %d, "
2423 "default %d, current %d\n",
2424 data_value[0], data_value[1], response);
2426 if (sdvo_data.overscan_v) {
2427 intel_sdvo_write_cmd(intel_output,
2428 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
2429 status = intel_sdvo_read_response(intel_output,
2431 if (status != SDVO_CMD_STATUS_SUCCESS) {
2432 DRM_DEBUG_KMS("Incorrect SDVO max "
2436 intel_sdvo_write_cmd(intel_output,
2437 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
2438 status = intel_sdvo_read_response(intel_output,
2440 if (status != SDVO_CMD_STATUS_SUCCESS) {
2441 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2444 sdvo_priv->max_vscan = data_value[0];
2445 sdvo_priv->top_margin = data_value[0] - response;
2446 sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2447 sdvo_priv->top_property =
2448 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2450 sdvo_priv->top_property->values[0] = 0;
2451 sdvo_priv->top_property->values[1] = data_value[0];
2452 drm_connector_attach_property(connector,
2453 sdvo_priv->top_property,
2454 sdvo_priv->top_margin);
2455 sdvo_priv->bottom_property =
2456 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2457 "bottom_margin", 2);
2458 sdvo_priv->bottom_property->values[0] = 0;
2459 sdvo_priv->bottom_property->values[1] = data_value[0];
2460 drm_connector_attach_property(connector,
2461 sdvo_priv->bottom_property,
2462 sdvo_priv->bottom_margin);
2463 DRM_DEBUG_KMS("v_overscan: max %d, "
2464 "default %d, current %d\n",
2465 data_value[0], data_value[1], response);
2467 if (sdvo_data.position_h) {
2468 intel_sdvo_write_cmd(intel_output,
2469 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
2470 status = intel_sdvo_read_response(intel_output,
2472 if (status != SDVO_CMD_STATUS_SUCCESS) {
2473 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2476 intel_sdvo_write_cmd(intel_output,
2477 SDVO_CMD_GET_POSITION_H, NULL, 0);
2478 status = intel_sdvo_read_response(intel_output,
2480 if (status != SDVO_CMD_STATUS_SUCCESS) {
2481 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2484 sdvo_priv->max_hpos = data_value[0];
2485 sdvo_priv->cur_hpos = response;
2486 sdvo_priv->hpos_property =
2487 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2489 sdvo_priv->hpos_property->values[0] = 0;
2490 sdvo_priv->hpos_property->values[1] = data_value[0];
2491 drm_connector_attach_property(connector,
2492 sdvo_priv->hpos_property,
2493 sdvo_priv->cur_hpos);
2494 DRM_DEBUG_KMS("h_position: max %d, "
2495 "default %d, current %d\n",
2496 data_value[0], data_value[1], response);
2498 if (sdvo_data.position_v) {
2499 intel_sdvo_write_cmd(intel_output,
2500 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
2501 status = intel_sdvo_read_response(intel_output,
2503 if (status != SDVO_CMD_STATUS_SUCCESS) {
2504 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2507 intel_sdvo_write_cmd(intel_output,
2508 SDVO_CMD_GET_POSITION_V, NULL, 0);
2509 status = intel_sdvo_read_response(intel_output,
2511 if (status != SDVO_CMD_STATUS_SUCCESS) {
2512 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2515 sdvo_priv->max_vpos = data_value[0];
2516 sdvo_priv->cur_vpos = response;
2517 sdvo_priv->vpos_property =
2518 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2520 sdvo_priv->vpos_property->values[0] = 0;
2521 sdvo_priv->vpos_property->values[1] = data_value[0];
2522 drm_connector_attach_property(connector,
2523 sdvo_priv->vpos_property,
2524 sdvo_priv->cur_vpos);
2525 DRM_DEBUG_KMS("v_position: max %d, "
2526 "default %d, current %d\n",
2527 data_value[0], data_value[1], response);
2530 if (sdvo_priv->is_tv) {
2531 if (sdvo_data.saturation) {
2532 intel_sdvo_write_cmd(intel_output,
2533 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
2534 status = intel_sdvo_read_response(intel_output,
2536 if (status != SDVO_CMD_STATUS_SUCCESS) {
2537 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2540 intel_sdvo_write_cmd(intel_output,
2541 SDVO_CMD_GET_SATURATION, NULL, 0);
2542 status = intel_sdvo_read_response(intel_output,
2544 if (status != SDVO_CMD_STATUS_SUCCESS) {
2545 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2548 sdvo_priv->max_saturation = data_value[0];
2549 sdvo_priv->cur_saturation = response;
2550 sdvo_priv->saturation_property =
2551 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2553 sdvo_priv->saturation_property->values[0] = 0;
2554 sdvo_priv->saturation_property->values[1] =
2556 drm_connector_attach_property(connector,
2557 sdvo_priv->saturation_property,
2558 sdvo_priv->cur_saturation);
2559 DRM_DEBUG_KMS("saturation: max %d, "
2560 "default %d, current %d\n",
2561 data_value[0], data_value[1], response);
2563 if (sdvo_data.contrast) {
2564 intel_sdvo_write_cmd(intel_output,
2565 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
2566 status = intel_sdvo_read_response(intel_output,
2568 if (status != SDVO_CMD_STATUS_SUCCESS) {
2569 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2572 intel_sdvo_write_cmd(intel_output,
2573 SDVO_CMD_GET_CONTRAST, NULL, 0);
2574 status = intel_sdvo_read_response(intel_output,
2576 if (status != SDVO_CMD_STATUS_SUCCESS) {
2577 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2580 sdvo_priv->max_contrast = data_value[0];
2581 sdvo_priv->cur_contrast = response;
2582 sdvo_priv->contrast_property =
2583 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2585 sdvo_priv->contrast_property->values[0] = 0;
2586 sdvo_priv->contrast_property->values[1] = data_value[0];
2587 drm_connector_attach_property(connector,
2588 sdvo_priv->contrast_property,
2589 sdvo_priv->cur_contrast);
2590 DRM_DEBUG_KMS("contrast: max %d, "
2591 "default %d, current %d\n",
2592 data_value[0], data_value[1], response);
2594 if (sdvo_data.hue) {
2595 intel_sdvo_write_cmd(intel_output,
2596 SDVO_CMD_GET_MAX_HUE, NULL, 0);
2597 status = intel_sdvo_read_response(intel_output,
2599 if (status != SDVO_CMD_STATUS_SUCCESS) {
2600 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2603 intel_sdvo_write_cmd(intel_output,
2604 SDVO_CMD_GET_HUE, NULL, 0);
2605 status = intel_sdvo_read_response(intel_output,
2607 if (status != SDVO_CMD_STATUS_SUCCESS) {
2608 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2611 sdvo_priv->max_hue = data_value[0];
2612 sdvo_priv->cur_hue = response;
2613 sdvo_priv->hue_property =
2614 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2616 sdvo_priv->hue_property->values[0] = 0;
2617 sdvo_priv->hue_property->values[1] =
2619 drm_connector_attach_property(connector,
2620 sdvo_priv->hue_property,
2621 sdvo_priv->cur_hue);
2622 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2623 data_value[0], data_value[1], response);
2626 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
2627 if (sdvo_data.brightness) {
2628 intel_sdvo_write_cmd(intel_output,
2629 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
2630 status = intel_sdvo_read_response(intel_output,
2632 if (status != SDVO_CMD_STATUS_SUCCESS) {
2633 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2636 intel_sdvo_write_cmd(intel_output,
2637 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
2638 status = intel_sdvo_read_response(intel_output,
2640 if (status != SDVO_CMD_STATUS_SUCCESS) {
2641 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2644 sdvo_priv->max_brightness = data_value[0];
2645 sdvo_priv->cur_brightness = response;
2646 sdvo_priv->brightness_property =
2647 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2649 sdvo_priv->brightness_property->values[0] = 0;
2650 sdvo_priv->brightness_property->values[1] =
2652 drm_connector_attach_property(connector,
2653 sdvo_priv->brightness_property,
2654 sdvo_priv->cur_brightness);
2655 DRM_DEBUG_KMS("brightness: max %d, "
2656 "default %d, current %d\n",
2657 data_value[0], data_value[1], response);
2663 bool intel_sdvo_init(struct drm_device *dev, int output_device)
2665 struct drm_connector *connector;
2666 struct intel_output *intel_output;
2667 struct intel_sdvo_priv *sdvo_priv;
2672 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2673 if (!intel_output) {
2677 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
2678 sdvo_priv->output_device = output_device;
2680 intel_output->dev_priv = sdvo_priv;
2681 intel_output->type = INTEL_OUTPUT_SDVO;
2683 /* setup the DDC bus. */
2684 if (output_device == SDVOB)
2685 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
2687 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
2689 if (!intel_output->i2c_bus)
2690 goto err_inteloutput;
2692 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
2694 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2695 intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
2697 /* Read the regs to test if we can talk to the device */
2698 for (i = 0; i < 0x40; i++) {
2699 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
2700 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2701 output_device == SDVOB ? 'B' : 'C');
2706 /* setup the DDC bus. */
2707 if (output_device == SDVOB) {
2708 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2709 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2710 "SDVOB/VGA DDC BUS");
2712 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2713 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2714 "SDVOC/VGA DDC BUS");
2717 if (intel_output->ddc_bus == NULL)
2720 /* Wrap with our custom algo which switches to DDC mode */
2721 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2723 /* In default case sdvo lvds is false */
2724 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
2726 if (intel_sdvo_output_setup(intel_output,
2727 sdvo_priv->caps.output_flags) != true) {
2728 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2729 output_device == SDVOB ? 'B' : 'C');
2734 connector = &intel_output->base;
2735 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2736 connector->connector_type);
2738 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2739 connector->interlace_allowed = 0;
2740 connector->doublescan_allowed = 0;
2741 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2743 drm_encoder_init(dev, &intel_output->enc,
2744 &intel_sdvo_enc_funcs, intel_output->enc.encoder_type);
2746 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
2748 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
2749 if (sdvo_priv->is_tv)
2750 intel_sdvo_tv_create_property(connector);
2752 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
2753 intel_sdvo_create_enhance_property(connector);
2755 drm_sysfs_connector_add(connector);
2757 intel_sdvo_select_ddc_bus(sdvo_priv);
2759 /* Set the input timing to the screen. Assume always input 0. */
2760 intel_sdvo_set_target_input(intel_output, true, false);
2762 intel_sdvo_get_input_pixel_clock_range(intel_output,
2763 &sdvo_priv->pixel_clock_min,
2764 &sdvo_priv->pixel_clock_max);
2767 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2768 "clock range %dMHz - %dMHz, "
2769 "input 1: %c, input 2: %c, "
2770 "output 1: %c, output 2: %c\n",
2771 SDVO_NAME(sdvo_priv),
2772 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2773 sdvo_priv->caps.device_rev_id,
2774 sdvo_priv->pixel_clock_min / 1000,
2775 sdvo_priv->pixel_clock_max / 1000,
2776 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2777 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2778 /* check currently supported outputs */
2779 sdvo_priv->caps.output_flags &
2780 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2781 sdvo_priv->caps.output_flags &
2782 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2787 if (sdvo_priv->analog_ddc_bus != NULL)
2788 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2789 if (intel_output->ddc_bus != NULL)
2790 intel_i2c_destroy(intel_output->ddc_bus);
2791 if (intel_output->i2c_bus != NULL)
2792 intel_i2c_destroy(intel_output->i2c_bus);
2794 kfree(intel_output);